<s> bool AArch64PassConfig :: addPreEmitPass ( ) { addPass ( & UnpackMachineBundlesID ) ; addPass ( createAArch64BranchFixupPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , I . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>


<s> static bool ix86_must_pass_in_stack ( const function_arg_info & arg ) { if ( must_pass_in_stack_var_size_or_pad ( arg ) ) return true ; return ( ! TARGET_64BIT && arg . mode == TImode && arg . type && TREE_CODE ( arg . type ) != VECTOR_TYPE ) ; } </s>

Return if we do not know how to pass TYPE solely in registers .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: ERet : expandERet ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool OR1KInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == OR1K :: JR ) return true ; if ( I -> getOpcode ( ) == OR1K :: J ) { if ( ! AllowModify ) { TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = 0 ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( 0 ) . getMBB ( ) ) ) { TBB = 0 ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } return true ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void PPCPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( createPPCVSXSwapRemovalPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> void x86_elf_aligned_common ( FILE * file , const char * name , unsigned HOST_WIDE_INT size , int align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) fprintf ( file , ".largecomm\t" ) ; else fprintf ( file , "%s" , COMMON_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

This says how to output assembler code to declare an uninitialized external linkage data object . For medium model x86-64 we need to use .largecomm opcode for large objects .


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
<<
"alignment  : "
<<
MF
.
getFrameInfo
(
)
.
getObjectAlignment
(
FrameIndex
)
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"
"alignment  : "
"\n"


<s> bool aarch64_expand_vec_perm_const ( rtx target , rtx op0 , rtx op1 , rtx sel ) { struct expand_vec_perm_d d ; int i , nelt , which ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; for ( i = which = 0 ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , 0 , i ) ; int ei = INTVAL ( e ) & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; d . perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( ! rtx_equal_p ( op0 , op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = op0 ; d . one_vector_p = true ; break ; } return aarch64_expand_vec_perm_const_1 ( & d ) ; } </s>


"the destination register can't equal the base register in an "

"instruction that modifies the base register."

ParseInstruction - Parse one assembly instruction .


<s> bool AArch64TargetLowering :: isMulAddWithConstProfitable ( const SDValue & AddNode , const SDValue & ConstNode ) const { const EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) || VT . getScalarSizeInBits ( ) > 64 ) return true ; const ConstantSDNode * C1Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; const ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C1 = C1Node -> getSExtValue ( ) ; const APInt C1C2 = C1Node -> getAPIntValue ( ) * C2Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C1 ) || isLegalAddImmediate ( C1C2 . getSExtValue ( ) ) ) return true ; SmallVector < AArch64_IMM :: ImmInsnModel , 4 > Insn ; AArch64_IMM :: expandMOVImm ( C1C2 . getZExtValue ( ) , VT . getSizeInBits ( ) , Insn ) ; if ( Insn . size ( ) > 1 ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


<s> const MCPhysReg * SICRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_O32_SaveList ; } </s>


<s> bool X86InstrInfo :: canMakeTailCallConditional ( SmallVectorImpl < MachineOperand > & BranchCond , const MachineInstr & TailCall ) const { if ( TailCall . getOpcode ( ) != X86 :: TCRETURNdi && TailCall . getOpcode ( ) != X86 :: TCRETURNdi64 ) { return false ; } const MachineFunction * MF = TailCall . getParent ( ) -> getParent ( ) ; if ( Subtarget . isTargetWin64 ( ) && MF -> hasWinCFI ( ) ) { return false ; } assert ( BranchCond . size ( ) == 1 ) ; if ( BranchCond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) { return false ; } const X86MachineFunctionInfo * X86FI = MF -> getInfo < X86MachineFunctionInfo > ( ) ; if ( X86FI -> getTCReturnAddrDelta ( ) != 0 || TailCall . getOperand ( 1 ) . getImm ( ) != 0 ) { return false ; } return true ; } </s>

Returns true if the tail call can be made conditional on BranchCond .


<s> SDValue AArch64TargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { LLVM_DEBUG ( dbgs ( ) << "AArch64TargetLowering::getAddr\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , AArch64II :: MO_PAGE | Flags ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , AArch64II :: MO_PAGEOFF | AArch64II :: MO_NC | Flags ) ; SDValue ADRP = DAG . getNode ( AArch64ISD :: ADRP , DL , Ty , Hi ) ; return DAG . getNode ( AArch64ISD :: ADDlow , DL , Ty , ADRP , Lo ) ; } </s>

Return the address accessed by this recipe .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"\nnew fndecl target specific options:\n"

"\nold fndecl target specific options:\n"

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: Small ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC::G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> static rtx csky_function_arg ( cumulative_args_t pcum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; if ( * pcum < CSKY_NPARM_REGS ) return gen_rtx_REG ( mode , CSKY_FIRST_PARM_REGNUM + * pcum ) ; return NULL_RTX ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const MCPhysReg ReservedGPR32 [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const MCPhysReg ReservedGPR64 [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedGPR32 ) ; ++ I ) Reserved . set ( ReservedGPR32 [ I ] ) ; if ( Subtarget . isTargetNaCl ( ) ) { Reserved . set ( Mips :: T6 ) ; Reserved . set ( Mips :: T7 ) ; Reserved . set ( Mips :: T8 ) ; } for ( unsigned I = 0 ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( ! Subtarget . isABICalls ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: DSPPos ) ; Reserved . set ( Mips :: DSPSCount ) ; Reserved . set ( Mips :: DSPCarry ) ; Reserved . set ( Mips :: DSPEFI ) ; Reserved . set ( Mips :: DSPOutFlag ) ; if ( Subtarget . inMips16Mode ( ) ) { const MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; Reserved . set ( Mips :: T0 ) ; Reserved . set ( Mips :: T1 ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "saveS2" ) || MipsFI -> hasSaveS2 ( ) ) Reserved . set ( Mips :: S2 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void altivec_expand_stvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx store = gen_rtx_SET ( op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( par ) ; } </s>

Generate code for a `` stvx '' or `` stvxl '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s> bool sparc_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; return for_each_rtx ( & x , & sparc_tls_symbol_ref_1 , 0 ) ; } </s>

Return 1 if X contains a thread-local symbol .


<s> static int aarch64_unspec_may_trap_p ( const_rtx x , unsigned flags ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTSMALLPIC : case UNSPEC_GOTSMALLPIC28K : case UNSPEC_GOTTINYPIC : return 0 ; default : break ; } return default_unspec_may_trap_p ( x , flags ) ; } </s>


<s> static bool loongarch_pass_by_reference ( cumulative_args_t cum_v , const function_arg_info & arg ) { HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; struct loongarch_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ; } return ! IN_RANGE ( size , 0 , 2 * UNITS_PER_WORD ) ; } </s>


<s> static machine_mode aarch64_reg_save_mode ( unsigned int regno ) { if ( GP_REGNUM_P ( regno ) ) return DImode ; if ( FP_REGNUM_P ( regno ) ) switch ( crtl -> abi -> id ( ) ) { case ARM_PCS_AAPCS64 : return DFmode ; case ARM_PCS_SIMD : return TFmode ; case ARM_PCS_SVE : if ( aarch64_emit_cfi_for_reg_p ( regno ) ) return VNx2DImode ; return VNx16QImode ; case ARM_PCS_TLSDESC : case ARM_PCS_UNKNOWN : break ; } if ( PR_REGNUM_P ( regno ) ) return VNx16BImode ; gcc_unreachable ( ) ; } </s>

Return the mode a register save/restore should use . DImode for integer registers , DFmode for FP registers in non-SIMD functions ( they only save the bottom half of a 128 bit register ) , or TFmode for FP registers in SIMD functions .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool IsVolatile , bool AlwaysInline , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


"\n%s -G value = %d, Arch = %s, ISA = %d\n"


<s> bool ARMBaseInstrInfo :: hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr * DefMI , unsigned DefIdx ) const { const InstrItineraryData * ItinData = SchedModel . getInstrItineraries ( ) ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return false ; unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( DDomain == ARMII :: DomainGeneral ) { unsigned DefClass = DefMI -> getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - 1 && DefCycle <= 2 ) ; } return false ; } </s>

Compute operand latency of a def of 'Reg ' .

ARM ARM ARMII::DomainMask ARMII::DomainGeneral 1 2


<s> unsigned getLinkageSize ( ) const { return LinkageSize ; } </s>

getLinkageSize - Return the size of the PowerPC ABI linkage area .


<s> bool mips_const_vector_same_bytes_p ( rtx op , machine_mode mode ) { int i , bytes ; HOST_WIDE_INT val , first_byte ; rtx first ; if ( ! mips_const_vector_same_val_p ( op , mode ) ) return false ; first = CONST_VECTOR_ELT ( op , 0 ) ; bytes = GET_MODE_UNIT_SIZE ( mode ) ; val = INTVAL ( first ) ; first_byte = val & 0xff ; for ( i = 1 ; i < bytes ; i ++ ) { val >>= 8 ; if ( ( val & 0xff ) != first_byte ) return false ; } return true ; } </s>

Return true if OP is a constant vector with the number of units in MODE , and each unit has the same value as well as replicated bytes in the value .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static inline bool offset_6bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , - 32 , 31 ) ) ; } </s>

Return true if OFFSET is a signed 6-bit value multiplied by the size of MODE .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


"\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "


<s> static rtx_insn * get_next_active_insn ( rtx_insn * insn , rtx_insn * tail ) { if ( insn == NULL_RTX || insn == tail ) return NULL ; while ( 1 ) { insn = NEXT_INSN ( insn ) ; if ( insn == NULL_RTX || insn == tail ) return NULL ; if ( CALL_P ( insn ) || JUMP_P ( insn ) || JUMP_TABLE_DATA_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && INSN_CODE ( insn ) != CODE_FOR_stack_tie ) ) break ; } return insn ; } </s>

Return the next insn after INSN that is found before TAIL is reached , skipping any `` non-active '' insns - insns that will not actually occupy an issue slot . Return NULL_RTX if such an insn is not found .


<s> static bool rs6000_scalar_mode_supported_p ( machine_mode mode ) { if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( TARGET_FLOAT128 && ( mode == KFmode || mode == IFmode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> bool MipsSEInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 1 ) . getImm ( ) != ( 1 << 4 ) ) return false ; else if ( isDSPControlWrite ) { Src = & MI . getOperand ( 0 ) ; Dest = & MI . getOperand ( 2 ) ; } else { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 2 ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode || GET_MODE ( x ) == HFmode ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . ulow ( ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


Control the placement of special register scavenging spill slots when allocating a stack frame .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; if ( StringRef ( constraint ) == "wc" && type -> isIntegerTy ( 1 ) ) return CW_Register ; else if ( ( StringRef ( constraint ) == "wa" || StringRef ( constraint ) == "wd" || StringRef ( constraint ) == "wf" ) && type -> isVectorTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "ws" && type -> isDoubleTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "wi" && type -> isIntegerTy ( 64 ) ) return CW_Register ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .

PowerPC PPC "wc" 1 "wa" "wd" "wf" "ws" "wi" 64


"Error: You are using the detectroundchange "

"option to detect rounding changes that will "

"cause LEON errata. The only way to fix this "

"is to remove the call to fesetround from "


"Unaligned memory access not supported: not "

"DSP extension not enabled: not running pass "

"Only supporting little endian: not running pass "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const KudeyarTargetMachine & getTargetMachine ( ) { return static_cast < const KudeyarTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> enum aarch64_symbol_type aarch64_classify_symbolic_expression ( rtx x , enum aarch64_symbol_context context ) { rtx offset ; split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , offset , context ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .


<s> bool PPCFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( MF . getInfo < PPCFunctionInfo > ( ) -> shrinkWrapDisabled ( ) ) return false ; return ! MF . getSubtarget < PPCSubtarget > ( ) . is32BitELFABI ( ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> bool OpenRISCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool classof ( const ARMConstantPoolValue * ACPV ) { return ACPV -> isMachineBasicBlock ( ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > 4 ) mem_count += 2 ; else mem_count += 1 ; } free ( bbs ) ; if ( mem_count && mem_count <= 32 ) return 32 / mem_count ; return nunroll ; } </s>

This function adjusts the unroll factor based on the hardware capabilities . For ex , bdver3 has a loop buffer which makes unrolling of smaller loops less important . This function decides the unroll factor using number of memory references ( value 32 is used ) as a heuristic .


<s> void ix86_expand_sse2_abs ( rtx target , rtx input ) { machine_mode mode = GET_MODE ( target ) ; rtx tmp0 , tmp1 , x ; switch ( mode ) { case V4SImode : tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_UNIT_BITSIZE ( mode ) - 1 ) , NULL , 0 , OPTAB_DIRECT ) ; tmp1 = expand_simple_binop ( mode , XOR , tmp0 , input , NULL , 0 , OPTAB_DIRECT ) ; x = expand_simple_binop ( mode , MINUS , tmp1 , tmp0 , target , 0 , OPTAB_DIRECT ) ; break ; case V8HImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( mode , SMAX , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; case V16QImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( V16QImode , UMIN , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Calculate integer abs ( ) using only SSE2 instructions .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static rtx_insn * mips16_emit_constants_1 ( machine_mode mode , rtx value , rtx_insn * insn ) { if ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) { rtx size = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; return emit_insn_after ( gen_consttable_int ( value , size ) , insn ) ; } if ( SCALAR_FLOAT_MODE_P ( mode ) ) return emit_insn_after ( gen_consttable_float ( value ) , insn ) ; if ( VECTOR_MODE_P ( mode ) ) { int i ; for ( i = 0 ; i < CONST_VECTOR_NUNITS ( value ) ; i ++ ) insn = mips16_emit_constants_1 ( GET_MODE_INNER ( mode ) , CONST_VECTOR_ELT ( value , i ) , insn ) ; return insn ; } gcc_unreachable ( ) ; } </s>

Output constant VALUE after instruction INSN and return the last instruction emitted . MODE is the mode of the constant .


"Unused function on X86. Otherwise need a test case."

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; bool hasAVX2 = Subtarget . hasAVX2 ( ) ; uint16_t validDomains = 0 ; if ( domain && lookup ( MI . getOpcode ( ) , domain ) ) validDomains = 0xe ; else if ( domain && lookupAVX2 ( MI . getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? 0xe : 0x6 ; return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> static bool sparc_pic_register_p ( rtx x ) { if ( ! REG_P ( x ) || ! pic_offset_table_rtx ) return false ; if ( x == pic_offset_table_rtx ) return true ; if ( ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ( HARD_REGISTER_P ( x ) || lra_in_progress || reload_in_progress ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return false ; } </s>

Return true if X is a representation of the PIC register .


<s> bool MipsPassConfig :: addInstSelector ( ) { addPass ( createMipsModuleISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMips16ISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMipsSEISelDag ( getMipsTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( getOptLevel ( ) <= EnableGlobalISelAtO ) setGlobalISel ( true ) ; } </s>


<s> void ix86_reset_previous_fndecl ( void ) { tree new_tree = target_option_current_node ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; ix86_previous_fndecl = NULL_TREE ; } </s>

Set targets globals to the default ( or current # pragma GCC target if active ) . Invalidate ix86_previous_fndecl cache .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> static rtx nds32_expand_priority_builtin ( enum insn_code icode , tree exp , rtx target , const char * name ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; if ( ! nds32_check_constant_argument ( icode , 0 , op0 , name ) ) return NULL_RTX ; if ( ! nds32_check_constant_argument ( icode , 1 , op1 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , 0 , op0 ) ; op1 = nds32_legitimize_argument ( icode , 1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>


<s> static bool aarch64_return_in_msb ( const_tree valtype ) { machine_mode dummy_mode ; int dummy_int ; if ( ! BYTES_BIG_ENDIAN ) return false ; if ( ! aarch64_composite_type_p ( valtype , TYPE_MODE ( valtype ) ) || int_size_in_bytes ( valtype ) <= 0 || int_size_in_bytes ( valtype ) > 16 ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( valtype ) , valtype , & dummy_mode , & dummy_int , NULL ) ) return false ; return true ; } </s>

Return TRUE if VALTYPE is padded to its least significant bits .


<s>
void
A57ChainingConstraint
::
apply
(
PBQPRAGraph
&
G
)
{
const
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
LiveIntervals
&
LIs
=
G
.
getMetadata
(
)
.
LIS
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
LLVM_DEBUG
(
MF
.
dump
(
)
)
;
for
(
const
auto
&
MBB
:
MF
)
{
Chains
.
clear
(
)
;
for
(
const
auto
&
MI
:
MBB
)
{
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
regJustKilledBefore
(
LIs
,
r
,
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
printReg
(
r
,
TRI
)
<<
" at "
;
MI
.
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
Register
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
Register
Ra
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
Register
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
break
;
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
static
int
crx_address_cost
(
rtx
addr
)
{
enum
crx_addrtype
addrtype
;
struct
crx_address
address
;
int
cost
=
2
;
addrtype
=
crx_decompose_address
(
addr
,
&
address
)
;
gcc_assert
(
addrtype
!=
CRX_INVALID
)
;
if
(
addrtype
==
CRX_ABSOLUTE
)
cost
+=
2
;
if
(
addrtype
==
CRX_POST_INC
)
cost
-=
2
;
if
(
address
.
base
)
cost
++
;
if
(
address
.
index
&&
address
.
scale
==
1
)
cost
+=
5
;
if
(
address
.
disp
&&
!
INT_CST4
(
INTVAL
(
address
.
disp
)
)
)
cost
+=
2
;
if
(
TARGET_DEBUG_ADDR
)
{
fprintf
(
stderr
,
"\n======\nTARGET_ADDRESS_COST = %d\n"
,
cost
)
;
debug_rtx
(
addr
)
;
}
return
cost
;
}
</s>


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = 1024 ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) { unsigned NotTakenBranchCost = 1 ; unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > 4 ) { PredCost += ( ( TCycles + FCycles - 4 ) / 4 ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; } return PredCost <= UnpredCost ; } </s>


<s> bool PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static int vax_address_cost ( rtx x ) { return ( 1 + ( GET_CODE ( x ) == REG ? 0 : vax_address_cost_1 ( x ) ) ) ; } </s>

Return the cost in cycles of a memory address , relative to register indirect . Each of the following adds the indicated number of cycles : 1 - symbolic address 1 - pre-decrement 1 - indexing and/or offset ( register ) 2 - indirect


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . padShortFunctions ( ) ) { addPass ( createX86PadShortFunctions ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>


<s> void ARMELFStreamer :: Reset ( ) { ExTab = NULL ; FnStart = NULL ; Personality = NULL ; PersonalityIndex = NUM_PERSONALITY_INDEX ; FPReg = ARM :: SP ; FPOffset = 0 ; SPOffset = 0 ; PendingOffset = 0 ; UsedFP = false ; CantUnwind = false ; Opcodes . clear ( ) ; UnwindOpAsm . Reset ( ) ; } </s>


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) ; const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( STI . getInstrInfo ( ) ) ; const TargetMachine & TM = F . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; LongBranchSeqSize = ! IsPIC ? 2 : ( ABI . IsN64 ( ) ? 10 : ( ! STI . isTargetNaCl ( ) ? 9 : 10 ) ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( IsPIC && static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( IsPIC ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
VarArgsFrameIndex
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
break
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShift
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
SHL_PARTS
:
return
LowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
case
ISD
::
SRA_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
VSETCC
:
return
LowerVSETCC
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> int pa_fmpyaddoperands ( rtx * operands ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( ! ( mode == GET_MODE ( operands [ 1 ] ) && mode == GET_MODE ( operands [ 2 ] ) && mode == GET_MODE ( operands [ 3 ] ) && mode == GET_MODE ( operands [ 4 ] ) && mode == GET_MODE ( operands [ 5 ] ) ) ) return 0 ; if ( ! ( GET_CODE ( operands [ 1 ] ) == REG && GET_CODE ( operands [ 2 ] ) == REG && GET_CODE ( operands [ 3 ] ) == REG && GET_CODE ( operands [ 4 ] ) == REG && GET_CODE ( operands [ 5 ] ) == REG ) ) return 0 ; if ( ! rtx_equal_p ( operands [ 3 ] , operands [ 4 ] ) && ! rtx_equal_p ( operands [ 3 ] , operands [ 5 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 3 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 1 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 2 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 4 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 5 ] , operands [ 0 ] ) ) return 0 ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ 0 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 1 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 2 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 3 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 4 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 5 ] ) ) != FPUPPER_REGS ) ) return 0 ; return 1 ; } </s>

Returns 1 if the 6 operands specified in OPERANDS are suitable for use in fmpyadd instructions .


<s> int loongarch_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct loongarch_address_info addr ; int factor ; if ( ! loongarch_classify_address ( & addr , x , mode , false ) ) return 0 ; if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; else factor = 1 ; if ( loongarch_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : case ADDRESS_REG_REG : case ADDRESS_CONST_INT : return factor ; case ADDRESS_LO_SUM : return factor + 1 ; case ADDRESS_SYMBOLIC : return factor * loongarch_symbol_insns ( addr . symbol_type , mode ) ; } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at address X . Return 0 if X is n't valid for MODE . Assume that multiword moves may need to be split into word moves if MIGHT_SPLIT_P , otherwise assume that a single load or store is enough .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align Alignment , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == MVT :: i8 || Ty == MVT :: i16 || Ty == MVT :: i32 ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == MVT :: f64 || Ty == MVT :: v2f64 ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == MVT :: v16i1 || Ty == MVT :: v8i1 || Ty == MVT :: v4i1 ) ) { if ( Fast ) * Fast = true ; return true ; } if ( ( Ty == MVT :: v4i8 || Ty == MVT :: v8i8 || Ty == MVT :: v4i16 ) && Alignment >= VT . getScalarSizeInBits ( ) / 8 ) { if ( Fast ) * Fast = true ; return true ; } if ( Ty == MVT :: v16i8 || Ty == MVT :: v8i16 || Ty == MVT :: v8f16 || Ty == MVT :: v4i32 || Ty == MVT :: v4f32 || Ty == MVT :: v2i64 || Ty == MVT :: v2f64 ) { if ( Fast ) * Fast = true ; return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void LanaiInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> const KudeyarRegisterInfo & KudeyarInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static int arm_compute_static_chain_stack_bytes ( void ) { if ( IS_NESTED ( arm_current_func_type ( ) ) && ( ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) || ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK && ! df_regs_ever_live_p ( LR_REGNUM ) ) ) && arm_r3_live_at_start_p ( ) && crtl -> args . pretend_args_size == 0 ) return 4 ; return 0 ; } </s>

Compute the number of bytes used to store the static chain register on the stack , above the stack frame . We need to know this accurately to get the alignment of the rest of the stack frame correct .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static bool arm_cannot_copy_insn_p ( rtx insn ) { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET ) { rtx rhs = SET_SRC ( XVECEXP ( pat , 0 , 0 ) ) ; if ( GET_CODE ( rhs ) == UNSPEC && XINT ( rhs , 1 ) == UNSPEC_PIC_BASE ) return TRUE ; if ( GET_CODE ( rhs ) == MEM && GET_CODE ( XEXP ( rhs , 0 ) ) == UNSPEC && XINT ( XEXP ( rhs , 0 ) , 1 ) == UNSPEC_PIC_BASE ) return TRUE ; } return FALSE ; } </s>

Must not copy any rtx that uses a pc-relative address .


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_74KC : case PROCESSOR_74KF2_1 : case PROCESSOR_74KF1_1 : case PROCESSOR_74KF3_2 : case PROCESSOR_R10000 : return 4 ; case PROCESSOR_20KC : case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R5900 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : case PROCESSOR_OCTEON : case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : case PROCESSOR_I6400 : return 2 ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return 3 ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_LOONGSON_3A : case PROCESSOR_P5600 : return 4 ; case PROCESSOR_XLP : return ( reload_completed ? 4 : 3 ) ; default : return 1 ; } } </s>

Return the number of instructions that can be issued per cycle .


<s> void altivec_expand_lvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx load = gen_rtx_SET ( tmp , op1 ) ; rtx lvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , load , lvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , tmp , tmp , sel ) , UNSPEC_VPERM ) ; gcc_assert ( REG_P ( op0 ) ) ; emit_insn ( par ) ; emit_insn ( gen_rtx_SET ( op0 , vperm ) ) ; } </s>

Generate code for an `` lvx '' , `` lvxl '' , or `` lve * x '' built-in for a little endian target with -maltivec=be specified . Issue the load followed by an element-reversing permute .


<s> void ARMMachOTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileMachO :: Initialize ( Ctx , TM ) ; LSDASection = getMachOSection ( "__TEXT" , "__gcc_except_tab" , 0 , SectionKind :: getReadOnlyWithRel ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( MIB ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri 0


<s> unsigned MipsAsmParser :: checkEarlyTargetMatchPredicate ( MCInst & Inst , const OperandVector & Operands ) { switch ( Inst . getOpcode ( ) ) { default : return Match_Success ; case Mips :: DATI : case Mips :: DAHI : case Mips :: DATI_MM64R6 : case Mips :: DAHI_MM64R6 : if ( static_cast < MipsOperand & > ( * Operands [ 1 ] ) . isValidForTie ( static_cast < MipsOperand & > ( * Operands [ 2 ] ) ) ) return Match_Success ; return Match_RequiresSameSrcAndDst ; } } </s>

Validate the instruction match against any complex target predicates before rendering any operands to it .


<s> static void rs6000_assemble_visibility ( tree decl , int vis ) { if ( TARGET_XCOFF ) return ; if ( DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS && TREE_CODE ( decl ) == FUNCTION_DECL ) { static const char * const visibility_types [ ] = { NULL , "protected" , "hidden" , "internal" } ; const char * name , * type ; name = ( ( * targetm . strip_name_encoding ) ( IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ) ; type = visibility_types [ vis ] ; fprintf ( asm_out_file , "\t.%s\t%s\n" , type , name ) ; fprintf ( asm_out_file , "\t.%s\t.%s\n" , type , name ) ; } else default_assemble_visibility ( decl , vis ) ; } </s>

Emit an assembler directive to set symbol visibility for DECL to VISIBILITY_TYPE .


<s> bool ARM64RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> hasVarSizedObjects ( ) && ! hasBasePointer ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { this -> MF = & MF ; SetupMachineFunction ( MF ) ; EmitConstantPool ( MF . getConstantPool ( ) ) ; EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; O << "\n\n" ; emitFunctionStart ( MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printInstruction ( II ) ; ++ EmittedInsts ; } O << '\n' ; } emitFunctionEnd ( MF ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / 4 ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips 16 4 4 0


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , Register Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const X86FrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return Is64Bit ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool sh_is_logical_t_store_expr ( rtx op , rtx_insn * insn ) { if ( ! logical_operator ( op , SImode ) ) return false ; rtx ops [ 2 ] = { XEXP ( op , 0 ) , XEXP ( op , 1 ) } ; int op_is_t_count = 0 ; for ( int i = 0 ; i < 2 ; ++ i ) { if ( t_reg_operand ( ops [ i ] , VOIDmode ) || negt_reg_operand ( ops [ i ] , VOIDmode ) ) op_is_t_count ++ ; else { set_of_reg op_set = sh_find_set_of_reg ( ops [ i ] , insn , prev_nonnote_nondebug_insn_bb ) ; if ( op_set . set_src == NULL_RTX ) continue ; if ( t_reg_operand ( op_set . set_src , VOIDmode ) || negt_reg_operand ( op_set . set_src , VOIDmode ) || sh_is_logical_t_store_expr ( op_set . set_src , op_set . insn ) ) op_is_t_count ++ ; } } return op_is_t_count == 2 ; } </s>

Given an op rtx and an insn , try to find out whether the result of the specified op consists only of logical operations on T bit stores .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI -> getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI -> getObjectAlignment ( Obj ) ; int ObjectSize = MFI -> getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI -> getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> static bool mips_return_in_memory ( tree type , tree fndecl ATTRIBUTE_UNUSED ) { if ( TARGET_OLDABI ) return ( TYPE_MODE ( type ) == BLKmode ) ; else return ( ( int_size_in_bytes ( type ) > ( 2 * UNITS_PER_WORD ) ) || ( int_size_in_bytes ( type ) == - 1 ) ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY . Under the old ( i.e. , 32 and O64 ABIs ) all BLKmode objects are returned in memory . Under the new ( N32 and 64-bit MIPS ABIs ) small structures are returned in a register . Objects with varying size must still be returned in memory , of course .


<s> bool AArch64TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const char * DCPU16TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case DCPU16ISD :: RET_FLAG : return "DCPU16ISD::RET_FLAG" ; case DCPU16ISD :: RETI_FLAG : return "DCPU16ISD::RETI_FLAG" ; case DCPU16ISD :: CALL : return "DCPU16ISD::CALL" ; case DCPU16ISD :: Wrapper : return "DCPU16ISD::Wrapper" ; case DCPU16ISD :: BR_CC : return "DCPU16ISD::BR_CC" ; case DCPU16ISD :: SELECT_CC : return "DCPU16ISD::SELECT_CC" ; case DCPU16ISD :: SMUL : return "DCPU16ISD::SMUL" ; case DCPU16ISD :: UMUL : return "DCPU16ISD::UMUL" ; } } </s>


<s> void aarch64_gen_unlikely_cbranch ( enum rtx_code code , machine_mode cc_mode , rtx label_ref ) { rtx x ; x = gen_rtx_fmt_ee ( code , VOIDmode , gen_rtx_REG ( cc_mode , CC_REGNUM ) , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( VOIDmode , label_ref ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } </s>

Generate RTL for a conditional branch with rtx comparison CODE in mode CC_MODE . The destination of the unlikely conditional branch is LABEL_REF .


<s> void AArch64AsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! AArch64FI -> getLOHRelated ( ) . empty ( ) ) EmitLOHs ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> rtx nds32_expand_load_multiple ( int base_regno , int count , rtx base_addr , rtx basemem , bool update_base_reg_p , rtx * update_base_reg ) { int par_index ; int offset ; int start_idx ; rtx result ; rtx new_addr , mem , reg ; if ( count == 1 ) { reg = gen_rtx_REG ( SImode , base_regno ) ; if ( update_base_reg_p ) { * update_base_reg = gen_reg_rtx ( SImode ) ; return gen_unaligned_load_update_base_w ( * update_base_reg , reg , base_addr ) ; } else return gen_unaligned_load_w ( reg , gen_rtx_MEM ( SImode , base_addr ) ) ; } if ( update_base_reg_p ) { result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; start_idx = 1 ; } else { result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; start_idx = 0 ; } if ( update_base_reg_p ) { offset = count * 4 ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; * update_base_reg = gen_reg_rtx ( SImode ) ; XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( * update_base_reg , new_addr ) ; } for ( par_index = 0 ; par_index < count ; par_index ++ ) { offset = par_index * 4 ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , 0 , ( par_index + start_idx ) ) = gen_rtx_SET ( reg , mem ) ; } return result ; } </s>

Functions to expand load_multiple and store_multiple . They are auxiliary extern functions to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> static int nds32_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { if ( TARGET_PIPELINE_GRAYWOLF ) { if ( GET_MODE_SIZE ( mode ) == 8 ) { if ( from == FP_REGS && to != FP_REGS ) return 3 ; if ( from != FP_REGS && to == FP_REGS ) return 2 ; } else { if ( ( from == FP_REGS && to != FP_REGS ) || ( from != FP_REGS && to == FP_REGS ) ) return 2 ; } } if ( ( from == FP_REGS && to != FP_REGS ) || ( from != FP_REGS && to == FP_REGS ) ) return 3 ; else if ( from == HIGH_REGS || to == HIGH_REGS ) return optimize_size ? 6 : 2 ; else return 2 ; } </s>

Describing Relative Costs of Operations .


<s> static bool forward_branch_p ( rtx_insn * insn ) { rtx lab = JUMP_LABEL ( insn ) ; gcc_assert ( lab != NULL_RTX ) ; if ( INSN_ADDRESSES_SET_P ( ) ) return INSN_ADDRESSES ( INSN_UID ( lab ) ) > INSN_ADDRESSES ( INSN_UID ( insn ) ) ; while ( insn ) { if ( insn == lab ) return true ; else insn = NEXT_INSN ( insn ) ; } return false ; } </s>

Return 1 if INSN branches forward . Should be using insn_addresses to avoid walking through all the insns ...


<s> static rtx ix86_expand_int_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , flags , tmp ) ) ; return gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; } </s>

Generate insn patterns to do an integer compare of OPERANDS .


<s>
void
SHUXIMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

SHUXI
SHUXI
4
"Unexpected instruction size!"


<s>
void
final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
opvec
ATTRIBUTE_UNUSED
,
int
noperands
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_DUMPISIZE
)
fprintf
(
asm_out_file
,
"\n! at %04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
TARGET_RELAX
)
{
if
(
rtx
note
=
find_reg_note
(
insn
,
REG_LABEL_OPERAND
,
NULL_RTX
)
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
switch
(
GET_CODE
(
pattern
)
)
{
case
SET
:
if
(
GET_CODE
(
SET_SRC
(
pattern
)
)
!=
CALL
&&
get_attr_type
(
insn
)
!=
TYPE_SFUNC
)
{
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
}
case
CALL
:
asm_fprintf
(
asm_out_file
,
"\t.uses %LL%d\n"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
}
}
</s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s> bool sh_vector_mode_supported_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return false ; } </s>

Implements target hook vector_mode_supported_p .


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
MipsRegisterInfo
::
getRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
{
if
(
MI
.
getOpcode
(
)
==
Mips
::
ULW
||
MI
.
getOpcode
(
)
==
Mips
::
USW
||
MI
.
getOpcode
(
)
==
Mips
::
ULH
||
MI
.
getOpcode
(
)
==
Mips
::
ULHu
)
emitGlobalAddressUnaligned
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
4
)
;
else
if
(
MI
.
getOpcode
(
)
==
Mips
::
USH
)
emitGlobalAddressUnaligned
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
8
)
;
else
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
Mips
Mips::ULW
Mips::USW
Mips::ULH
Mips::ULHu
4
Mips::USH
8
"Unable to encode MachineOperand!"
0


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSIWithSVE
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
std
::
vector
<
CalleeSavedInfo
>
CSI
;
for
(
unsigned
i
=
0
;
i
<
CSIWithSVE
.
size
(
)
;
++
i
)
{
if
(
MFI
->
getStackRegionToHandleCSR
(
CSIWithSVE
[
i
]
.
getReg
(
)
)
!=
nullptr
)
continue
;
CSI
.
push_back
(
CSIWithSVE
[
i
]
)
;
}
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; bool isLiveIn = MF . getRegInfo ( ) . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool isKill = ! isLiveIn ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>


<s> BitVector CJGRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( CJG :: SR ) ; Reserved . set ( CJG :: PC ) ; Reserved . set ( CJG :: SP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> rtx mmix_gen_compare_reg ( RTX_CODE code , rtx x , rtx y ) { enum machine_mode ccmode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg ; enum machine_mode mode = GET_MODE ( x ) == VOIDmode ? GET_MODE ( y ) : GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ? DFmode : DImode ; if ( ! mmix_valid_comparison ( code , mode , x ) ) return NULL_RTX ; cc_reg = gen_reg_rtx ( ccmode ) ; if ( ! REG_P ( x ) && ! REG_P ( y ) ) x = force_reg ( mode , x ) ; if ( ! REG_P ( y ) && ( GET_CODE ( y ) != CONST_INT || ! CONST_OK_FOR_LETTER_P ( INTVAL ( y ) , 'I' ) ) ) y = force_reg ( mode , y ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( ccmode , x , y ) ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit a compare insn if possible and return the rtx for the cc-reg in the proper mode , or NULL_RTX if this is not a valid comparison .


<s>
void
LEGMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

LEG
LEG
4
"Unexpected instruction size!"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx altivec_expand_ld_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; tree arglist = TREE_OPERAND ( exp , 1 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 ; enum machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_altivec_lvx_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_altivec_lvx_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_altivec_lvx_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_altivec_lvx_v4sf ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = TREE_VALUE ( arglist ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; tmode = insn_data [ icode ] . operand [ 0 ] . mode ; mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
auto
EmitMI
=
[
&
]
(
const
RegPairInfo
&
RPI
)
{
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
;
if
(
ReverseCSRRestoreSeq
)
for
(
const
RegPairInfo
&
RPI
:
reverse
(
RegPairs
)
)
EmitMI
(
RPI
)
;
else
for
(
const
RegPairInfo
&
RPI
:
RegPairs
)
EmitMI
(
RPI
)
;
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; emitXRayTable ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
ADDE
:
return
performADDECombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SUBE
:
return
performSUBECombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
)
;
case
ISD
::
SHL
:
return
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips
Mips
ISD::ADDE
ISD::AND
ISD::OR
ISD::SUBE
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


"if conversion tried to stop defining used CPSR"

Convert the instruction into a predicated instruction .


"ARM64 pseudo instruction expansion pass"

getPassName - Return a nice clean name for a pass .


<s> static bool arm_align_anon_bitfield ( void ) { return TARGET_AAPCS_BASED ; } </s>

AAPCS requires that anonymous bitfields affect structure alignment .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
nullptr
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool aarch64_evpc_zip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; high = nelt / 2 ; if ( d -> perm [ 0 ] == high ) ; else if ( d -> perm [ 0 ] == 0 ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * 2 ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * 2 + 1 ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out = d -> target ; if ( high ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip2v16qi ; break ; case V8QImode : gen = gen_aarch64_zip2v8qi ; break ; case V8HImode : gen = gen_aarch64_zip2v8hi ; break ; case V4HImode : gen = gen_aarch64_zip2v4hi ; break ; case V4SImode : gen = gen_aarch64_zip2v4si ; break ; case V2SImode : gen = gen_aarch64_zip2v2si ; break ; case V2DImode : gen = gen_aarch64_zip2v2di ; break ; case V4HFmode : gen = gen_aarch64_zip2v4hf ; break ; case V8HFmode : gen = gen_aarch64_zip2v8hf ; break ; case V4SFmode : gen = gen_aarch64_zip2v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip2v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip1v16qi ; break ; case V8QImode : gen = gen_aarch64_zip1v8qi ; break ; case V8HImode : gen = gen_aarch64_zip1v8hi ; break ; case V4HImode : gen = gen_aarch64_zip1v4hi ; break ; case V4SImode : gen = gen_aarch64_zip1v4si ; break ; case V2SImode : gen = gen_aarch64_zip1v2si ; break ; case V2DImode : gen = gen_aarch64_zip1v2di ; break ; case V4HFmode : gen = gen_aarch64_zip1v4hf ; break ; case V8HFmode : gen = gen_aarch64_zip1v8hf ; break ; case V4SFmode : gen = gen_aarch64_zip1v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip1v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the ZIP instructions .


<s>
StringRef
getPassName
(
)
const
override
{
return
"CSKY Constant Islands"
;
}
</s>


<s> bool mep_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class regclass ) { if ( from == to ) return false ; if ( TARGET_64BIT_CR_REGS && ( regclass == CR_REGS || regclass == LOADABLE_CR_REGS ) && ( GET_MODE_SIZE ( to ) < 8 || GET_MODE_SIZE ( from ) < 8 ) ) return true ; return false ; } </s>

Return true if the registers in CLASS can not represent the change from modes FROM to TO .


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> static enum arm_cond_code get_arm_condition_code ( rtx comparison ) { enum arm_cond_code code = maybe_get_arm_condition_code ( comparison ) ; gcc_assert ( code != ARM_NV ) ; return code ; } </s>

Returns the index of the ARM condition code string in ` arm_condition_codes ' . COMPARISON should be an rtx like ` ( eq ( ... ) ( ... ) ) ' .


<s> bool X86PassConfig :: addInstSelector ( ) { addPass ( createX86ISelDag ( getX86TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ; addPass ( createX86GlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static tree arm_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { valist = arm_extract_valist_ptr ( valist ) ; return std_gimplify_va_arg_expr ( valist , type , pre_p , post_p ) ; } </s>


<s> bool ix86_use_lea_for_mov ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 ; if ( ! TARGET_OPT_AGU || optimize_function_for_size_p ( cfun ) ) return false ; if ( ! REG_P ( operands [ 0 ] ) || ! REG_P ( operands [ 1 ] ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = true_regnum ( operands [ 1 ] ) ; return ix86_lea_outperforms ( insn , regno0 , regno1 , INVALID_REGNUM , 0 , false ) ; } </s>

Return true if we should emit lea instruction instead of mov instruction .