<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>


<s> static void ATTRIBUTE_UNUSED ix86_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( ix86_in_large_data_p ( decl ) ) SYMBOL_REF_FLAGS ( XEXP ( rtl , 0 ) ) |= SYMBOL_FLAG_FAR_ADDR ; } </s>

Implements target vector targetm.asm.encode_section_info .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static void mips_save_reg ( rtx reg , rtx mem ) { if ( GET_MODE ( reg ) == DFmode && ! TARGET_FLOAT64 ) { rtx x1 , x2 ; if ( mips_split_64bit_move_p ( mem , reg ) ) mips_split_64bit_move ( mem , reg ) ; else emit_move_insn ( mem , reg ) ; x1 = mips_frame_set ( mips_subword ( mem , 0 ) , mips_subword ( reg , 0 ) ) ; x2 = mips_frame_set ( mips_subword ( mem , 1 ) , mips_subword ( reg , 1 ) ) ; mips_set_frame_expr ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x1 , x2 ) ) ) ; } else { if ( TARGET_MIPS16 && REGNO ( reg ) != GP_REG_FIRST + 31 && ! M16_REG_P ( REGNO ( reg ) ) ) { emit_move_insn ( MIPS_PROLOGUE_TEMP ( GET_MODE ( reg ) ) , reg ) ; emit_move_insn ( mem , MIPS_PROLOGUE_TEMP ( GET_MODE ( reg ) ) ) ; } else emit_move_insn ( mem , reg ) ; mips_set_frame_expr ( mips_frame_set ( mem , reg ) ) ; } } </s>

Save register REG to MEM . Make the instruction frame-related .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
PrintImmValue
=
[
&
]
(
const
MCExpr
*
Val
,
const
char
*
VName
)
{
if
(
Val
->
getKind
(
)
==
MCExpr
::
Constant
)
{
if
(
auto
Imm
=
cast
<
MCConstantExpr
>
(
Val
)
->
getValue
(
)
)
OS
<<
VName
<<
Imm
;
}
else
if
(
Val
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
{
if
(
auto
*
SRE
=
dyn_cast
<
MCSymbolRefExpr
>
(
Val
)
)
{
const
MCSymbol
&
Sym
=
SRE
->
getSymbol
(
)
;
if
(
auto
SymName
=
Sym
.
getName
(
)
.
data
(
)
)
OS
<<
VName
<<
SymName
;
}
}
}
;
switch
(
Kind
)
{
case
Token
:
OS
<<
Tok
.
Data
;
break
;
case
Register
:
OS
<<
"Reg:"
<<
X86IntelInstPrinter
::
getRegisterName
(
Reg
.
RegNo
)
;
break
;
case
Immediate
:
PrintImmValue
(
Imm
.
Val
,
"Imm:"
)
;
break
;
case
Prefix
:
OS
<<
"Prefix:"
<<
Pref
.
Prefixes
;
break
;
case
Memory
:
OS
<<
"Memory: ModeSize="
<<
Mem
.
ModeSize
;
if
(
Mem
.
Size
)
OS
<<
",Size="
<<
Mem
.
Size
;
if
(
Mem
.
BaseReg
)
OS
<<
",BaseReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
BaseReg
)
;
if
(
Mem
.
IndexReg
)
OS
<<
",IndexReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
IndexReg
)
;
if
(
Mem
.
Scale
)
OS
<<
",Scale="
<<
Mem
.
Scale
;
if
(
Mem
.
Disp
)
PrintImmValue
(
Mem
.
Disp
,
",Disp="
)
;
if
(
Mem
.
SegReg
)
OS
<<
",SegReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
SegReg
)
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

X86
"Reg:"
X86
"Imm:"
"Prefix:"
"Memory: ModeSize="
",Size="
",BaseReg="
X86
",IndexReg="
X86
",Scale="
",Disp="
",SegReg="
X86


<s> void X86FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , MCCFIInstruction CFIInst ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . getMMI ( ) . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

Wraps up getting a CFI index and building a MachineInstr for it .


<s> static bool examine_argument ( machine_mode mode , const_tree type , int in_return , int * int_nregs , int * sse_nregs ) { enum x86_64_reg_class regclass [ MAX_CLASSES ] ; int n = classify_argument ( mode , type , regclass , 0 ) ; * int_nregs = 0 ; * sse_nregs = 0 ; if ( ! n ) return true ; for ( n -- ; n >= 0 ; n -- ) switch ( regclass [ n ] ) { case X86_64_INTEGER_CLASS : case X86_64_INTEGERSI_CLASS : ( * int_nregs ) ++ ; break ; case X86_64_SSE_CLASS : case X86_64_SSEHF_CLASS : case X86_64_SSESF_CLASS : case X86_64_SSEDF_CLASS : ( * sse_nregs ) ++ ; break ; case X86_64_NO_CLASS : case X86_64_SSEUP_CLASS : break ; case X86_64_X87_CLASS : case X86_64_X87UP_CLASS : case X86_64_COMPLEX_X87_CLASS : if ( ! in_return ) return true ; break ; case X86_64_MEMORY_CLASS : gcc_unreachable ( ) ; } return false ; } </s>

Examine the argument and return set number of register required in each class . Return 0 iff parameter should be passed in memory .


<s> void LanaiTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( nullptr , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == 0 ) { Result = DAG . getTargetConstant ( 0 , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < 16 > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= 31 ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < 32 > ( Val ) ) && ( ( Val & 0xffff ) == 0 ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - 33554432 ) && ( Val <= 33554431 ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; default : break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> unsigned ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { if ( ! ArgTy -> isVectorTy ( ) ) return DL . getABITypeAlignment ( ArgTy ) ; return std :: min ( DL . getABITypeAlignment ( ArgTy ) , DL . getStackAlignment ( ) ) ; } </s>

Return the correct alignment for the current calling convention .


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s> static void sparc_conditional_register_usage ( void ) { if ( PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } if ( TARGET_ARCH32 && fixed_regs [ 5 ] ) fixed_regs [ 5 ] = 1 ; else if ( TARGET_ARCH64 && fixed_regs [ 5 ] == 2 ) fixed_regs [ 5 ] = 0 ; if ( ! TARGET_V9 ) { int regno ; for ( regno = SPARC_FIRST_V9_FP_REG ; regno <= SPARC_LAST_V9_FP_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; for ( regno = SPARC_FIRST_V9_FCC_REG + 1 ; regno <= SPARC_LAST_V9_FCC_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; } if ( ! TARGET_FPU ) { int regno ; for ( regno = 32 ; regno < SPARC_LAST_V9_FCC_REG ; regno ++ ) fixed_regs [ regno ] = 1 ; } if ( fixed_regs [ 2 ] == 2 ) fixed_regs [ 2 ] = ! TARGET_APP_REGS ; if ( fixed_regs [ 3 ] == 2 ) fixed_regs [ 3 ] = ! TARGET_APP_REGS ; if ( TARGET_ARCH32 && fixed_regs [ 4 ] == 2 ) fixed_regs [ 4 ] = ! TARGET_APP_REGS ; else if ( TARGET_CM_EMBMEDANY ) fixed_regs [ 4 ] = 1 ; else if ( fixed_regs [ 4 ] == 2 ) fixed_regs [ 4 ] = 0 ; if ( TARGET_FLAT ) { int regno ; memset ( sparc_leaf_regs , 0 , FIRST_PSEUDO_REGISTER ) ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) leaf_reg_remap [ regno ] = regno ; } if ( TARGET_VIS ) global_regs [ SPARC_GSR_REG ] = 1 ; } </s>

If ! TARGET_FPU , then make the fp registers and fp cc regs fixed so that they wo n't be allocated .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


"%qs attribute only applies to functions"

Handle a `` longcall '' attribute ; arguments as in struct attribute_spec.handler .


"function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, "

Advance the argument of type TYPE and mode MODE to the next argument position in CUM .


<s> static rtx mips16_stub_function ( const char * name ) { rtx x ; x = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( x ) |= ( SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION ) ; return x ; } </s>

Return a SYMBOL_REF for a MIPS16 function called NAME .


<s>
static
int
rs6000_arg_partial_bytes
(
cumulative_args_t
cum_v
,
machine_mode
mode
,
tree
type
,
bool
named
)
{
CUMULATIVE_ARGS
*
cum
=
get_cumulative_args
(
cum_v
)
;
bool
passed_in_gprs
=
true
;
int
ret
=
0
;
int
align_words
;
machine_mode
elt_mode
;
int
n_elts
;
rs6000_discover_homogeneous_aggregate
(
mode
,
type
,
&
elt_mode
,
&
n_elts
)
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
elt_mode
,
named
)
)
{
if
(
TARGET_64BIT
&&
!
cum
->
prototype
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
vregno
+
n_elts
>
ALTIVEC_ARG_MAX_REG
+
1
)
ret
=
(
ALTIVEC_ARG_MAX_REG
+
1
cum
->
vregno
)
*
16
;
}
if
(
TARGET_MACHO
&&
rs6000_darwin64_struct_check_p
(
mode
,
type
)
)
return
0
;
align_words
=
rs6000_parm_start
(
mode
,
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
elt_mode
)
)
{
unsigned
long
n_fpreg
=
(
GET_MODE_SIZE
(
elt_mode
)
+
7
)
>>
3
;
if
(
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
fregno
+
n_elts
*
n_fpreg
>
FP_ARG_MAX_REG
+
1
)
{
int
fpr
=
(
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
MIN
(
8
,
GET_MODE_SIZE
(
elt_mode
)
)
)
;
int
fpr_words
=
fpr
/
(
TARGET_32BIT
4
:
8
)
;
if
(
align_words
+
fpr_words
<
GP_ARG_NUM_REG
)
passed_in_gprs
=
true
;
else
ret
=
fpr
;
}
}
if
(
passed_in_gprs
&&
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
mode
,
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
ABS
:
lowerABS
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SHL
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN
ISD::ABS


Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST . Like the default implementation , but returns a lower bound .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Indirect Thunks"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
bool
AArch64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
if
(
!
BranchRelaxation
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64BranchRelaxation *****\n"
)
;
TII
=
(
const
AArch64InstrInfo
*
)
MF
->
getTarget
(
)
.
getSubtargetImpl
(
)
->
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
)
;
DEBUG
(
dumpBBs
(
)
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n"
)
;
DEBUG
(
dbgs
(
)
<<
'\n'
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


"passing %wd to argument %d of %qE, which expects"

Report that LOCATION has a call to FNDECL in which argument ARGNO has the value ACTUAL , whereas the function requires one of VALUE0 .. 3 . ARGNO counts from zero .


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> static void sparc_init_builtins ( void ) { if ( TARGET_VIS ) sparc_vis_init_builtins ( ) ; } </s>

Implement the TARGET_INIT_BUILTINS target hook . Create builtin functions for special SPARC instructions .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= 32 && ST -> hasAVX ( ) ) || ( DataWidth >= 8 && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s>
void
load_pic_register
(
)
{
int
orig_flag_pic
=
flag_pic
;
if
(
!
flag_pic
)
abort
(
)
;
if
(
get_pc_symbol_name
[
0
]
==
0
)
{
int
align
;
ASM_GENERATE_INTERNAL_LABEL
(
get_pc_symbol_name
,
"LGETPC"
,
0
)
;
text_section
(
)
;
align
=
floor_log2
(
FUNCTION_BOUNDARY
/
BITS_PER_UNIT
)
;
if
(
align
>
0
)
ASM_OUTPUT_ALIGN
(
asm_out_file
,
align
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
"LGETPC"
,
0
)
;
fputs
(
"\tretl\n\tadd\t%o7, %l7, %l7\n"
,
asm_out_file
)
;
}
global_offset_table
=
gen_rtx_SYMBOL_REF
(
Pmode
,
"_GLOBAL_OFFSET_TABLE_"
)
;
get_pc_symbol
=
gen_rtx_SYMBOL_REF
(
Pmode
,
get_pc_symbol_name
)
;
flag_pic
=
0
;
emit_insn
(
gen_get_pc
(
pic_offset_table_rtx
,
global_offset_table
,
get_pc_symbol
)
)
;
flag_pic
=
orig_flag_pic
;
emit_insn
(
gen_rtx_USE
(
VOIDmode
,
pic_offset_table_rtx
)
)
;
}
</s>


<s> static void emit_compare ( rtx_code code , rtx a , rtx b ) { emit_insn ( gen_rtx_SET ( gen_rtx_REG ( BImode , SR_F_REGNUM ) , gen_rtx_fmt_ee ( code , BImode , a , b ) ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a raw comparison for A CODE B .


<s> rtx mmix_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { return count == 0 ? ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? validize_mem ( gen_rtx_MEM ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , - 16 ) ) ) : get_hard_reg_initial_val ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ) : NULL_RTX ; } </s>


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void ARMAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { const bool WasThumb = isThumb ( StartInfo ) ; if ( ! EndInfo || WasThumb != isThumb ( * EndInfo ) ) { OutStreamer -> EmitAssemblerFlag ( WasThumb ? MCAF_Code16 : MCAF_Code32 ) ; } } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


Return a register that is zero iff CMP0 and CMP1 are equal . The register will have the same mode as CMP0 .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
bool
LEAUsesAG
=
ST
.
LEAusesAG
(
)
;
bool
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
bool
UseLEAForSP
=
ST
.
useLeaForSP
(
)
;
TSM
.
init
(
&
ST
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
{
if
(
!
isLEA
(
I
->
getOpcode
(
)
)
)
continue
;
if
(
optTwoAddrLEA
(
I
,
MBB
,
OptIncDec
,
UseLEAForSP
)
)
continue
;
if
(
IsSlowLEA
)
{
processInstructionForSlowLEA
(
I
,
MBB
)
;
}
else
if
(
IsSlow3OpsLEA
)
{
if
(
auto
*
NewMI
=
processInstrForSlow3OpLEA
(
*
I
,
MBB
)
)
{
MBB
.
erase
(
I
)
;
I
=
NewMI
;
}
}
}
if
(
LEAUsesAG
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
processInstruction
(
I
,
MBB
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > 1 && ML -> getSubLoops ( ) . empty ( ) ) return 5 ; } const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> bool gpr_or_gpr_p ( rtx op0 , rtx op1 ) { return ( ( REG_P ( op0 ) && INT_REGNO_P ( REGNO ( op0 ) ) ) || ( REG_P ( op1 ) && INT_REGNO_P ( REGNO ( op1 ) ) ) ) ; } </s>

Return true if either operand is a general purpose register .


<s> bool isLittleEndian ( ) const { return IsLittleEndian ; } </s>

Tests whether the target triple is little endian .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Lanai SET_FLAG ALU combiner pass"
;
}
</s>

Lanai
"Lanai SET_FLAG ALU combiner pass"


<s> static bool nds32_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( regno > FIRST_PSEUDO_REGISTER ) return true ; if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) && NDS32_IS_FPR_REGNUM ( regno ) ) { if ( NDS32_IS_EXT_FPR_REGNUM ( regno ) ) return ( NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) && ( mode == DFmode ) ) ; else if ( mode == SFmode || mode == SImode ) return NDS32_FPR_REGNO_OK_FOR_SINGLE ( regno ) ; else if ( mode == DFmode ) return NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) ; return false ; } if ( regno <= NDS32_LAST_GPR_REGNUM ) return ( targetm . hard_regno_nregs ( regno , mode ) == 1 || ! ( ( regno ) & 1 ) ) ; return false ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return ARM64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool sh_cfun_trap_exit_p ( void ) { return ( lookup_attribute ( "trap_exit" , DECL_ATTRIBUTES ( current_function_decl ) ) == NULL_TREE ) ; } </s>

Returns true if the current function has a `` trap_exit '' attribute set .


<s> bool X86InstrInfo :: isHighLatencyDef ( int opc ) const { switch ( opc ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDr : case X86 :: SQRTPSm : case X86 :: SQRTPSr : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : case X86 :: VDIVSDrm : case X86 :: VDIVSDrm_Int : case X86 :: VDIVSDrr : case X86 :: VDIVSDrr_Int : case X86 :: VDIVSSrm : case X86 :: VDIVSSrm_Int : case X86 :: VDIVSSrr : case X86 :: VDIVSSrr_Int : case X86 :: VSQRTPDm : case X86 :: VSQRTPDr : case X86 :: VSQRTPSm : case X86 :: VSQRTPSr : case X86 :: VSQRTSDm : case X86 :: VSQRTSDm_Int : case X86 :: VSQRTSDr : case X86 :: VSQRTSSm : case X86 :: VSQRTSSm_Int : case X86 :: VSQRTSSr : case X86 :: VSQRTPDZm : case X86 :: VSQRTPDZr : case X86 :: VSQRTPSZm : case X86 :: VSQRTPSZr : case X86 :: VSQRTSDZm : case X86 :: VSQRTSDZm_Int : case X86 :: VSQRTSDZr : case X86 :: VSQRTSSZm_Int : case X86 :: VSQRTSSZr : case X86 :: VSQRTSSZm : case X86 :: VDIVSDZrm : case X86 :: VDIVSDZrr : case X86 :: VDIVSSZrm : case X86 :: VDIVSSZrr : case X86 :: VGATHERQPSZrm : case X86 :: VGATHERQPDZrm : case X86 :: VGATHERDPDZrm : case X86 :: VGATHERDPSZrm : case X86 :: VPGATHERQDZrm : case X86 :: VPGATHERQQZrm : case X86 :: VPGATHERDDZrm : case X86 :: VPGATHERDQZrm : case X86 :: VSCATTERQPDZmr : case X86 :: VSCATTERQPSZmr : case X86 :: VSCATTERDPDZmr : case X86 :: VSCATTERDPSZmr : case X86 :: VPSCATTERQDZmr : case X86 :: VPSCATTERQQZmr : case X86 :: VPSCATTERDDZmr : case X86 :: VPSCATTERDQZmr : return true ; } } </s>

Return true if this opcode has high latency to its result .


<s> static void sparc_emit_set_const32 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx temp = op0 ; if ( can_create_pseudo_p ( ) ) temp = gen_reg_rtx ( mode ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { gcc_assert ( ! small_int_operand ( op1 , mode ) && ! const_high_operand ( op1 , mode ) ) ; emit_insn ( gen_rtx_SET ( temp , GEN_INT ( INTVAL ( op1 ) & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( mode , temp , GEN_INT ( INTVAL ( op1 ) & 0x3ff ) ) ) ) ; } else { emit_insn ( gen_rtx_SET ( temp , gen_rtx_HIGH ( mode , op1 ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_LO_SUM ( mode , temp , op1 ) ) ) ; } } </s>

We know it ca n't be done in one insn when we get here , the movsi expander guarentees this .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool SystemZFrameInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( SystemZ :: FP64RegClass . contains ( Reg ) ) TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , & SystemZ :: FP64RegClass , TRI ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ( LowReg == HighReg ? SystemZ :: MOV64rm : SystemZ :: MOV64rmm ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Define ) ; MIB . addReg ( hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ) ; MIB . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool aarch64_emit_approx_div ( rtx quo , rtx num , rtx den ) { machine_mode mode = GET_MODE ( quo ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) return false ; bool use_approx_division_p = ( flag_mlow_precision_div || ( aarch64_tune_params . approx_modes -> division & AARCH64_APPROX_MODE ( mode ) ) ) ; if ( ! flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) || ! use_approx_division_p ) return false ; if ( ! TARGET_SIMD && VECTOR_MODE_P ( mode ) ) return false ; rtx xrcp = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_recpe_type ( mode ) ) ( xrcp , den ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( flag_mlow_precision_div ) iterations -- ; rtx xtmp = gen_reg_rtx ( mode ) ; while ( iterations -- ) { emit_insn ( ( * get_recps_type ( mode ) ) ( xtmp , xrcp , den ) ) ; if ( iterations > 0 ) emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; } if ( num != CONST1_RTX ( mode ) ) { rtx xnum = force_reg ( mode , num ) ; emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xnum ) ) ; } emit_set_insn ( quo , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; return true ; } </s>

Emit the instruction sequence to compute the approximation for the division of NUM by DEN in QUO and return whether the sequence was emitted or not .


<s> static int aarch64_reassociation_width ( unsigned opc ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) return aarch64_tune_params -> vec_reassoc_width ; if ( INTEGRAL_MODE_P ( mode ) ) return aarch64_tune_params -> int_reassoc_width ; if ( FLOAT_MODE_P ( mode ) ) return aarch64_tune_params -> fp_reassoc_width ; return 1 ; } </s>

Return the reassociation width of treeop OPC with mode MODE .


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool PPCCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return false ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> static SDNode * getInt64 ( SelectionDAG * CurDAG , SDNode * N ) { SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; return getInt64 ( CurDAG , dl , Imm ) ; } </s>


<s> SDValue X86TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , NegatibleCost & Cost , unsigned Depth ) const { if ( SDValue Arg = isFNEG ( DAG , Op . getNode ( ) , Depth ) ) { Cost = NegatibleCost :: Cheaper ; return DAG . getBitcast ( Op . getValueType ( ) , Arg ) ; } EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case ISD :: FMA : case X86ISD :: FMSUB : case X86ISD :: FNMADD : case X86ISD :: FNMSUB : case X86ISD :: FMADD_RND : case X86ISD :: FMSUB_RND : case X86ISD :: FNMADD_RND : case X86ISD :: FNMSUB_RND : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == MVT :: f32 || SVT == MVT :: f64 ) || ! isOperationLegal ( ISD :: FMA , VT ) ) break ; SmallVector < SDValue , 4 > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = 0 ; i != 3 ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; bool NegA = ! ! NewOps [ 0 ] ; bool NegB = ! ! NewOps [ 1 ] ; bool NegC = ! ! NewOps [ 2 ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; Cost = ( NegA || NegB || NegC ) ? NegatibleCost :: Cheaper : NegatibleCost :: Neutral ; for ( int i = 0 , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } case X86ISD :: FRCP : if ( SDValue NegOp0 = getNegatedExpression ( Op . getOperand ( 0 ) , DAG , LegalOperations , ForCodeSize , Cost , Depth + 1 ) ) return DAG . getNode ( Opc , SDLoc ( Op ) , VT , NegOp0 ) ; break ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Cost , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { const DataLayout & DL = MF -> getDataLayout ( ) ; SectionKind Kind = CPE . getSectionKind ( & DL ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( DL , Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
LivePhysRegs
LiveRegs
(
getRegisterInfo
(
)
)
;
LiveRegs
.
addLiveOuts
(
MBB
)
;
SmallVector
<
std
::
pair
<
unsigned
,
const
MachineOperand
*
>
,
8
>
Clobbers
;
LiveRegs
.
stepForward
(
*
MIB
,
Clobbers
)
;
for
(
const
auto
&
C
:
Clobbers
)
{
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
)
;
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
|
RegState
::
Define
)
;
}
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


<s> static void add_constant ( int dest , int src , int value , int mark_frame ) { rtx_insn * insn ; int hi , lo ; if ( src == dest && value == 0 ) return ; if ( value == 0 ) { insn = emit_move_insn ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) ) ; if ( mark_frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; return ; } if ( value >= - 32768 && value <= 32767 ) { insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , GEN_INT ( value ) ) ) ; if ( mark_frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; return ; } hi = trunc_int_for_mode ( value & 0xffff0000 , SImode ) ; lo = value & 0xffff ; insn = emit_move_insn ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( hi ) ) ; if ( lo ) { insn = emit_insn ( gen_iorsi3 ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( lo ) ) ) ; } insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) ) ) ; if ( mark_frame ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( gen_rtx_REG ( SImode , dest ) , gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , dest ) , GEN_INT ( value ) ) ) ) ; } } </s>

Add a constant to the pool and return its label .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TSchedModel
.
init
(
STI
.
getSchedModel
(
)
,
&
STI
,
TII
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
MachineLoop
*
CurrLoop
=
MLI
.
getLoopFor
(
&
MBB
)
;
if
(
!
CurrLoop
||
CurrLoop
->
getHeader
(
)
!=
&
MBB
||
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static rtx ix86_delegitimize_tls_address ( rtx orig_x ) { rtx x = orig_x , unspec ; struct ix86_address addr ; if ( ! TARGET_TLS_DIRECT_SEG_REFS ) return orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) != PLUS || GET_MODE ( x ) != Pmode ) return orig_x ; if ( ix86_decompose_address ( x , & addr ) == 0 || addr . seg != DEFAULT_TLS_SEG_REG || addr . disp == NULL_RTX || GET_CODE ( addr . disp ) != CONST ) return orig_x ; unspec = XEXP ( addr . disp , 0 ) ; if ( GET_CODE ( unspec ) == PLUS && CONST_INT_P ( XEXP ( unspec , 1 ) ) ) unspec = XEXP ( unspec , 0 ) ; if ( GET_CODE ( unspec ) != UNSPEC || XINT ( unspec , 1 ) != UNSPEC_NTPOFF ) return orig_x ; x = XVECEXP ( unspec , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; if ( unspec != XEXP ( addr . disp , 0 ) ) x = gen_rtx_PLUS ( Pmode , x , XEXP ( XEXP ( addr . disp , 0 ) , 1 ) ) ; if ( addr . index ) { rtx idx = addr . index ; if ( addr . scale != 1 ) idx = gen_rtx_MULT ( Pmode , idx , GEN_INT ( addr . scale ) ) ; x = gen_rtx_PLUS ( Pmode , idx , x ) ; } if ( addr . base ) x = gen_rtx_PLUS ( Pmode , addr . base , x ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } </s>

Helper function for ix86_delegitimize_address . Attempt to delegitimize TLS local-exec accesses .


<s>
static
tree
ix86_canonical_va_list_type
(
tree
type
)
{
if
(
TARGET_64BIT
)
{
if
(
lookup_attribute
(
"ms_abi va_list"
,
TYPE_ATTRIBUTES
(
type
)
)
)
return
ms_va_list_type_node
;
if
(
(
TREE_CODE
(
type
)
==
ARRAY_TYPE
&&
integer_zerop
(
array_type_nelts
(
type
)
)
)
||
POINTER_TYPE_P
(
type
)
)
{
tree
elem_type
=
TREE_TYPE
(
type
)
;
if
(
TREE_CODE
(
elem_type
)
==
RECORD_TYPE
&&
lookup_attribute
(
"sysv_abi va_list"
,
TYPE_ATTRIBUTES
(
elem_type
)
)
)
return
sysv_va_list_type_node
;
}
return
NULL_TREE
;
}
return
std_canonical_va_list_type
(
type
)
;
}
</s>

Returns the canonical va_list type specified by TYPE . If there is no valid TYPE provided , it return NULL_TREE .

i386
"ms_abi va_list"
"sysv_abi va_list"


"\nrs6000_legitimate_address_p: return = %s, mode = %s, "

Debug version of rs6000_legitimate_address_p .


<s>
bool
MipsOs16
::
runOnModule
(
Module
&
M
)
{
bool
usingMask
=
Mips32FunctionMask
.
length
(
)
>
0
;
bool
doneUsingMask
=
false
;
DEBUG
(
dbgs
(
)
<<
"Run on Module MipsOs16 \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
if
(
usingMask
)
DEBUG
(
dbgs
(
)
<<
"using mask \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
unsigned
int
functionIndex
=
0
;
bool
modified
=
false
;
for
(
auto
&
F
:
M
)
{
if
(
F
.
isDeclaration
(
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Working on "
<<
F
.
getName
(
)
<<
"\n"
)
;
if
(
usingMask
)
{
if
(
!
doneUsingMask
)
{
if
(
functionIndex
==
Mips32FunctionMask
.
length
(
)
)
functionIndex
=
0
;
switch
(
Mips32FunctionMask
[
functionIndex
]
)
{
case
'1'
:
DEBUG
(
dbgs
(
)
<<
"mask forced mips32: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"nomips16"
)
;
break
;
case
'.'
:
doneUsingMask
=
true
;
break
;
default
:
break
;
}
functionIndex
++
;
}
}
else
{
if
(
needsFP
(
F
)
)
{
DEBUG
(
dbgs
(
)
<<
"os16 forced mips32: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"nomips16"
)
;
}
else
{
DEBUG
(
dbgs
(
)
<<
"os16 forced mips16: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"mips16"
)
;
}
}
}
return
modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

Mips
Mips
Mips
0
"Run on Module MipsOs16 \n"
Mips
"\n"
"using mask \n"
Mips
"\n"
0
"Working on "
"\n"
Mips
0
Mips
"mask forced mips32: "
"\n"
"nomips16"
"os16 forced mips32: "
"\n"
"nomips16"
"os16 forced mips16: "
"\n"
"mips16"


<s> enum rtx_code ix86_fp_compare_code_to_integer ( enum rtx_code code ) { switch ( code ) { case GT : return GTU ; case GE : return GEU ; case ORDERED : case UNORDERED : return code ; break ; case UNEQ : return EQ ; break ; case UNLT : return LTU ; break ; case UNLE : return LEU ; break ; case LTGT : return NE ; break ; default : return UNKNOWN ; } } </s>

Convert comparison codes we use to represent FP comparison to integer code that will result in proper branch . Return UNKNOWN if no such code is available .


<s> bool MipsOptimizeMathLibCalls :: runOnFunction ( Function & F ) { if ( DisableOpt ) return false ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . inMips16Mode ( ) ) return false ; bool Changed = false ; Function :: iterator CurrBB ; const TargetLibraryInfo * LibInfo = & getAnalysis < TargetLibraryInfo > ( ) ; for ( Function :: iterator BB = F . begin ( ) , BE = F . end ( ) ; BB != BE ; ) { CurrBB = BB ++ ; for ( BasicBlock :: iterator II = CurrBB -> begin ( ) , IE = CurrBB -> end ( ) ; II != IE ; ++ II ) { CallInst * Call = dyn_cast < CallInst > ( & * II ) ; Function * CalledFunc ; if ( ! Call || ! ( CalledFunc = Call -> getCalledFunction ( ) ) ) continue ; LibFunc :: Func LibFunc ; Attribute A = CalledFunc -> getAttributes ( ) . getAttribute ( AttributeSet :: FunctionIndex , "use-soft-float" ) ; if ( ( A . isStringAttribute ( ) && ( A . getValueAsString ( ) == "true" ) ) || TM . Options . UseSoftFloat ) continue ; if ( CalledFunc -> hasLocalLinkage ( ) || ! CalledFunc -> hasName ( ) || ! LibInfo -> getLibFunc ( CalledFunc -> getName ( ) , LibFunc ) ) continue ; switch ( LibFunc ) { case LibFunc :: sqrtf : case LibFunc :: sqrt : if ( optimizeSQRT ( Call , CalledFunc , * CurrBB , BB ) ) break ; continue ; default : continue ; } Changed = true ; break ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

Mips Mips Mips Mips Mips "use-soft-float" "true"


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( Triple ( TT ) ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> int following_call ( rtx insn ) { if ( ! TARGET_JUMP_IN_DELAY ) return 0 ; insn = PREV_INSN ( insn ) ; while ( insn && GET_CODE ( insn ) == NOTE ) insn = PREV_INSN ( insn ) ; if ( insn && ( ( GET_CODE ( insn ) == CALL_INSN && get_attr_type ( insn ) != TYPE_DYNCALL ) || ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) != SEQUENCE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if INSN ( a jump insn ) immediately follows a call to a named function . This is used to avoid filling the delay slot of the jump since it can usually be eliminated by modifying RP in the delay slot of the call .


<s> void PPCAIXAsmPrinter :: emitEndOfAsmFile ( Module & M ) { if ( M . empty ( ) ) return ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) ; PPCTargetStreamer * TS = static_cast < PPCTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first , TM ) ) ; OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> emitLabel ( I . second ) ; if ( TS != nullptr ) TS -> emitTCEntry ( * I . first ) ; } } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> static rtx sparc_legitimize_pic_address ( rtx orig , rtx reg ) { bool gotdata_op = false ; if ( GET_CODE ( orig ) == SYMBOL_REF || ( GET_CODE ( orig ) == LABEL_REF && ! can_use_mov_pic_label_ref ( orig ) ) ) { rtx pic_ref , address ; rtx_insn * insn ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } if ( flag_pic == 2 ) { rtx temp_reg = ( ! can_create_pseudo_p ( ) ? reg : gen_reg_rtx ( Pmode ) ) ; if ( TARGET_ARCH64 ) { emit_insn ( gen_movdi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movdi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } else { emit_insn ( gen_movsi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movsi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } address = temp_reg ; gotdata_op = true ; } else address = orig ; crtl -> uses_pic_offset_table = 1 ; if ( gotdata_op ) { if ( TARGET_ARCH64 ) insn = emit_insn ( gen_movdi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; else insn = emit_insn ( gen_movsi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; } else { pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; insn = emit_move_insn ( reg , pic_ref ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS && XEXP ( XEXP ( orig , 0 ) , 0 ) == pic_offset_table_rtx ) return orig ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , reg ) ; offset = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , base == reg ? NULL_RTX : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( can_create_pseudo_p ( ) ) offset = force_reg ( Pmode , offset ) ; else gcc_unreachable ( ) ; } return gen_rtx_PLUS ( Pmode , base , offset ) ; } else if ( GET_CODE ( orig ) == LABEL_REF ) crtl -> uses_pic_offset_table = 1 ; return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


"invalid feature modifier %qs for 'cpu' target %s"

Handle the argument CPU_STR to the cpu= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> bool SystemZElimCompare :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . ) Return a number of integer regsiters advanced over .


"considering end of repeat loop at insn %d\n"

Figure out where to put LABEL , which is the label for a repeat loop . The loop ends just before LAST_INSN . If SHARED , insns other than the `` repeat '' might use LABEL to jump to the loop 's continuation point . Return the last instruction in the adjusted loop .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createSparcELFObjectWriter ( OS , is64Bit ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> int arm_no_early_alu_shift_dep ( rtx producer , rtx consumer ) { rtx value = PATTERN ( producer ) ; rtx op = PATTERN ( consumer ) ; rtx early_op ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , 0 , 0 ) ; value = XEXP ( value , 0 ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , 0 , 0 ) ; op = XEXP ( op , 1 ) ; early_op = XEXP ( op , 0 ) ; if ( GET_CODE ( early_op ) == REG ) early_op = op ; return ! reg_overlap_mentioned_p ( value , early_op ) ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value or amount dependency on the result of PRODUCER .


<s> static bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) || ( TARGET_HAVE_MVE && ( VALID_MVE_MODE ( mode1 ) || VALID_MVE_STRUCT_MODE ( mode1 ) ) && ( VALID_MVE_MODE ( mode2 ) || VALID_MVE_STRUCT_MODE ( mode2 ) ) ) ) return true ; return false ; } </s>


<s> int rs6000_trampoline_size ( void ) { int ret = 0 ; switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? 12 : 24 ; break ; case ABI_DARWIN : case ABI_V4 : ret = ( TARGET_32BIT ) ? 40 : 48 ; break ; } return ret ; } </s>

Length in units of the trampoline for entering a nested function .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Mips ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool mips_pad_arg_upward ( enum machine_mode mode , tree type ) { if ( ! BYTES_BIG_ENDIAN ) return true ; if ( type != 0 ? INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_INT ) return false ; if ( mips_abi == ABI_O64 ) if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return false ; if ( mips_abi != ABI_EABI ) return true ; if ( mode != BLKmode ) return ( GET_MODE_BITSIZE ( mode ) >= PARM_BOUNDARY ) ; else return ( int_size_in_bytes ( type ) >= ( PARM_BOUNDARY / BITS_PER_UNIT ) ) ; } </s>

Return true if FUNCTION_ARG_PADDING ( MODE , TYPE ) should return upward rather than downward . In other words , return true if the first byte of the stack slot has useful data , false if the last byte does .


<s>
SDValue
SystemZTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

SystemZ
SystemZ
ISD::InputArg
"Unsupported calling convention"


<s> void SparcTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( 0 , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> inline Predicate getPredicate ( unsigned Condition , unsigned Hint ) { return ( Predicate ) ( ( Condition & ~ BR_HINT_MASK ) | ( Hint & BR_HINT_MASK ) ) ; } </s>

Returns the comparison predicate underlying the intrinsic .


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( funcInfo . MF -> getTarget ( ) ) ; bool UseFastISel = TM . Options . EnableFastISel && Subtarget . hasMips32 ( ) && ! Subtarget . hasMips32r6 ( ) && ! Subtarget . inMips16Mode ( ) && ! Subtarget . inMicroMipsMode ( ) ; if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) ) UseFastISel = false ; return UseFastISel ? Mips :: createFastISel ( funcInfo , libInfo ) : nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

Mips Mips Mips Mips Mips Mips Mips Mips Mips::createFastISel


<s> bool X86TargetLowering :: shouldSplatInsEltVarIndex ( EVT VT ) const { return isTypeLegal ( VT ) ; } </s>

Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead .


<s> MCOperand SystemZMCInstLower :: lowerOperand ( const MachineOperand & MO ) const { switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) ) ; default : { MCSymbolRefExpr :: VariantKind Kind = getVariantKind ( MO . getTargetFlags ( ) ) ; return MCOperand :: CreateExpr ( getExpr ( MO , Kind ) ) ; } } } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"DCPU16 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned X86TargetLowering :: getAddressSpace ( ) const { if ( Subtarget . is64Bit ( ) ) return ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) ? 256 : 257 ; return 256 ; } </s>

Return the address space of the Pointer type .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
TOY
::
NumTargetFixupKinds
]
=
{
{
"fixup_toy_mov_hi16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_toy_mov_lo16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
{
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> unsigned getMaximumJumpTableSize ( ) const { return MaxJumpTableSize ; } </s>

Return upper limit for number of entries in a jump table .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( auto CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case Mips :: BPOSGE32_PSEUDO : return emitBPOSGE32 ( MI , BB ) ; case Mips :: SNZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_B ) ; case Mips :: SNZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_H ) ; case Mips :: SNZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_W ) ; case Mips :: SNZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_D ) ; case Mips :: SNZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_V ) ; case Mips :: SZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_B ) ; case Mips :: SZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_H ) ; case Mips :: SZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_W ) ; case Mips :: SZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_D ) ; case Mips :: SZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_V ) ; case Mips :: COPY_FW_PSEUDO : return emitCOPY_FW ( MI , BB ) ; case Mips :: COPY_FD_PSEUDO : return emitCOPY_FD ( MI , BB ) ; case Mips :: INSERT_FW_PSEUDO : return emitINSERT_FW ( MI , BB ) ; case Mips :: INSERT_FD_PSEUDO : return emitINSERT_FD ( MI , BB ) ; case Mips :: FILL_FW_PSEUDO : return emitFILL_FW ( MI , BB ) ; case Mips :: FILL_FD_PSEUDO : return emitFILL_FD ( MI , BB ) ; case Mips :: FEXP2_W_1_PSEUDO : return emitFEXP2_W_1 ( MI , BB ) ; case Mips :: FEXP2_D_1_PSEUDO : return emitFEXP2_D_1 ( MI , BB ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static int rs6000_variable_issue_1 ( rtx_insn * insn , int more ) { last_scheduled_insn = insn ; if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) { cached_can_issue_more = more ; return cached_can_issue_more ; } if ( insn_terminates_group_p ( insn , current_group ) ) { cached_can_issue_more = 0 ; return cached_can_issue_more ; } if ( recog_memoized ( insn ) < 0 ) return more ; if ( rs6000_sched_groups ) { if ( is_microcoded_insn ( insn ) ) cached_can_issue_more = 0 ; else if ( is_cracked_insn ( insn ) ) cached_can_issue_more = more > 2 ? more - 2 : 0 ; else cached_can_issue_more = more - 1 ; return cached_can_issue_more ; } if ( rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn ( insn ) ) return 0 ; cached_can_issue_more = more - 1 ; return cached_can_issue_more ; } </s>

Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle . Branches have their own dispatch slot which does not count against the GCC issue rate , but it changes the program flow so there are no other instructions to issue in this cycle .


"function parameters cannot have __fp16 type"


<s> static bool csky_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ! ( TARGET_HARD_FLOAT && mode1 != mode2 && ( mode1 == DFmode || mode2 == DFmode ) ) ; } </s>

Implement TARGET_MODES_TIEABLE_P . We ca n't tie DFmode with other modes when V_REGs might be in use because those registers mess with the stored bits .


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; dup = gen_vec_duplicate ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; machine_mode innermode = GET_MODE_INNER ( mode ) ; rtx reg ; start_sequence ( ) ; reg = force_reg ( innermode , val ) ; if ( GET_MODE ( reg ) != innermode ) reg = gen_lowpart ( innermode , reg ) ; SET_SRC ( PATTERN ( insn ) ) = gen_vec_duplicate ( mode , reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s> static void pop ( int rn ) { rtx x , sp_reg , reg ; if ( rn == FPUL_REG ) x = gen_pop_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_pop_fpscr ( ) ; else if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , 0 , 0 ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( sp_reg , plus_constant ( SImode , sp_reg , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; } </s>

Output RTL to pop register RN from the stack .


<s> bool aarch64_sve_prefetch_operand_p ( rtx op , machine_mode mode ) { struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , op , mode , false ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return known_eq ( addr . const_offset , 0 ) ; return addr . type == ADDRESS_REG_REG ; } </s>

Return true if OP is a valid address for an SVE PRF [ BHWD ] instruction , addressing memory of mode MODE .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; bool HasMicroMipsAttr = ! F . getFnAttribute ( "micromips" ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicroMipsAttr = ! F . getFnAttribute ( "nomicromips" ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


<s>
StringRef
getPassName
(
)
const
override
{
return
"SystemZ Comparison Elimination"
;
}
</s>

SystemZ
"SystemZ Comparison Elimination"


"invalid conversion from type %<bfloat16_t%>"

"invalid conversion to type %<bfloat16_t%>"

Return the diagnostic message string if conversion from FROMTYPE to TOTYPE is not allowed , NULL otherwise .


<s> StackOffset SystemZELFFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { StackOffset Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI , FrameReg ) ; return Offset + StackOffset :: getFixed ( SystemZMC :: ELFCallFrameSize ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool isValid ( ) { return isFIBase ( ) || ( isRegBase ( ) && getReg ( ) != 0 ) ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; SmallVector < IntrinsicInst * , 4 > Gathers ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather ) Gathers . push_back ( II ) ; } } if ( Gathers . empty ( ) ) return false ; for ( IntrinsicInst * I : Gathers ) lowerGather ( I ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
mmix_output_register_setting
(
FILE
*
stream
,
int
regno
,
int64_t
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\t"
)
;
if
(
insn_const_int_ok_for_constraint
(
value
,
CONSTRAINT_K
)
)
fprintf
(
stream
,
"NEGU %s,0,%"
PRId64
,
reg_names
[
regno
]
,
value
)
;
else
if
(
mmix_shiftable_wyde_value
(
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
uint64_t
)
value
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
"\n\tNEGU %s,0,%s"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
~
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
~
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
~
(
uint64_t
)
value
)
;
fprintf
(
stream
,
"\n\tNOR %s,%s,0"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
{
static
const
char
*
const
higher_parts
[
]
=
{
"L"
,
"ML"
,
"MH"
,
"H"
}
;
const
char
*
op
=
"SET"
;
const
char
*
line_begin
=
""
;
int
insns
=
0
;
int
i
;
int64_t
tmpvalue
=
value
;
for
(
i
=
0
;
i
<
4
&&
tmpvalue
!=
0
;
i
++
)
{
if
(
tmpvalue
&
65535
)
insns
++
;
tmpvalue
>>=
16
;
}
if
(
TARGET_BASE_ADDRESSES
&&
insns
==
3
)
{
fprintf
(
stream
,
"LDA %s,"
,
reg_names
[
regno
]
)
;
mmix_output_octa
(
stream
,
value
,
0
)
;
}
else
{
for
(
i
=
0
;
i
<
4
&&
value
!=
0
;
i
++
)
{
if
(
value
&
65535
)
{
fprintf
(
stream
,
"%s%s%s %s,#%x"
,
line_begin
,
op
,
higher_parts
[
i
]
,
reg_names
[
regno
]
,
(
int
)
(
value
&
65535
)
)
;
op
=
"INC"
;
line_begin
=
"\n\t"
;
}
value
>>=
16
;
}
}
}
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Output an optimal sequence for setting a register to a specific constant . Used in an alternative for const_ints in movdi , and when using large stack-frame offsets . Use do_begin_end to say if a line-starting TAB and newline before the first insn and after the last insn is wanted .


<s> static unsigned int aarch64_unspec_cond_code ( rtx_code code ) { switch ( code ) { case NE : return UNSPEC_COND_FCMNE ; case EQ : return UNSPEC_COND_FCMEQ ; case LT : return UNSPEC_COND_FCMLT ; case GT : return UNSPEC_COND_FCMGT ; case LE : return UNSPEC_COND_FCMLE ; case GE : return UNSPEC_COND_FCMGE ; case UNORDERED : return UNSPEC_COND_FCMUO ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_COND_ * code for comparison CODE .


"%<-mindirect-branch=%s%> and %<-mcmodel=large%> are not "

"%<-mindirect-branch%> and %<-fcf-protection%> are not "

"%<-mfunction-return=%s%> and %<-mcmodel=large%> are not "

"%<-mfunction-return%> and %<-fcf-protection%> are not "

Set the indirect_branch_type field from the function FNDECL .


<s> static void rs6000_init_sched_context ( void * _sc , bool clean_p ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; if ( clean_p ) { sc -> cached_can_issue_more = 0 ; sc -> last_scheduled_insn = NULL ; sc -> load_store_pendulum = 0 ; sc -> divide_cnt = 0 ; sc -> vec_pairing = 0 ; } else { sc -> cached_can_issue_more = cached_can_issue_more ; sc -> last_scheduled_insn = last_scheduled_insn ; sc -> load_store_pendulum = load_store_pendulum ; sc -> divide_cnt = divide_cnt ; sc -> vec_pairing = vec_pairing ; } } </s>

If CLEAN_P is true then initializes _SC with clean data , and from the global context otherwise .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( AArch64 :: isX18ReservedByDefault ( TT ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> rtx ix86_memtag_set_tag ( rtx untagged , rtx tag , rtx target ) { if ( ix86_lam_type == lam_u57 ) { unsigned HOST_WIDE_INT and_imm = ( HOST_WIDE_INT_1U << IX86_HWASAN_TAG_SIZE ) - 1 ; emit_insn ( gen_andqi3 ( tag , tag , GEN_INT ( and_imm ) ) ) ; } tag = expand_simple_binop ( Pmode , ASHIFT , tag , GEN_INT ( IX86_HWASAN_SHIFT ) , NULL_RTX , 1 , OPTAB_WIDEN ) ; rtx ret = expand_simple_binop ( Pmode , IOR , untagged , tag , target , 1 , OPTAB_DIRECT ) ; return ret ; } </s>


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr & MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp , LiveVariables * LV ) const { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . add ( Src ) ; isKill = true ; isUndef = false ; if ( LV ) LV -> replaceKillInstruction ( SrcReg , MI , * Copy ) ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } addPass ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void SparcFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( ! DisableLeafProc && isLeafProc ( MF ) ) { SparcMachineFunctionInfo * MFI = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MFI -> setLeafProc ( true ) ; remapRegsForLeafProc ( MF ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( 4 - i - 1 ) * 8 ) ) & 0xff ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> Relocator :: Size X86_64Relocator :: getSize ( Relocation :: Type pType ) const { return X86_64ApplyFunctions [ pType ] . size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 Atom pad short functions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool X86TargetLowering :: reduceSelectOfFPConstantLoads ( EVT CmpOpVT ) const { bool IsFPSetCC = CmpOpVT . isFloatingPoint ( ) && CmpOpVT != MVT :: f128 ; return ! IsFPSetCC || ! Subtarget . isTarget64BitLP64 ( ) || ! Subtarget . hasAVX ( ) ; } </s>

Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition .


<s> bool prefersVectorizedAddressing ( ) { return false ; } </s>

Return true if target does n't mind addresses in vectors .


<s> bool PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
XSP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { assert ( 0 && "UNIMP" ) ; } </s>


<s> static void emit_and_preserve ( rtx seq , rtx reg , rtx reg2 ) { rtx slot = gen_rtx_MEM ( word_mode , plus_constant ( stack_pointer_rtx , SPARC_STACK_BIAS ) ) ; emit_insn ( gen_stack_pointer_dec ( GEN_INT ( STACK_BOUNDARY / BITS_PER_UNIT ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , slot , reg ) ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( VOIDmode , adjust_address ( slot , word_mode , UNITS_PER_WORD ) , reg2 ) ) ; emit_insn ( seq ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( VOIDmode , reg2 , adjust_address ( slot , word_mode , UNITS_PER_WORD ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , slot ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( STACK_BOUNDARY / BITS_PER_UNIT ) ) ) ; } </s>

Emit the sequence of insns SEQ while preserving the registers .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 load / store optimization pass"
;
}
</s>


<s> const uint16_t * DLXRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { const uint16_t t = 5 ; return & t ; } </s>


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
if
(
!
WidenVMOVS
||
!
MI
->
isCopy
(
)
)
return
false
;
unsigned
DstRegS
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
SrcRegS
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
->
definesRegister
(
DstRegD
,
TRI
)
||
MI
->
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
->
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
*
MI
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
int
ImpDefIdx
=
MI
->
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
->
RemoveOperand
(
ImpDefIdx
)
;
MI
->
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
->
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
->
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
AddDefaultPred
(
MIB
)
;
MI
->
getOperand
(
1
)
.
setIsUndef
(
)
;
MIB
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
->
getOperand
(
1
)
.
isKill
(
)
)
{
MI
->
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
->
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
*
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool isLegalMaskedLoad ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked load .


<s> bool LanaiInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return false ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int rs6000_psave_function_arg ( machine_mode mode , const_tree type , int align_words , rtx * rvec ) { int k = 0 ; if ( align_words < GP_ARG_NUM_REG ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( align_words + n_words > GP_ARG_NUM_REG || mode == BLKmode || ( TARGET_32BIT && TARGET_POWERPC64 ) ) { machine_mode rmode = TARGET_32BIT ? SImode : DImode ; int i = 0 ; if ( align_words + n_words > GP_ARG_NUM_REG ) { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } do { rtx r = gen_rtx_REG ( rmode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * GET_MODE_SIZE ( rmode ) ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_words != 0 ) ; } else { rtx r = gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , const0_rtx ) ; } } else { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } return k ; } </s>

We have an argument of MODE and TYPE that goes into FPRs or VRs , but must also be copied into the parameter save area starting at offset ALIGN_WORDS . Fill in RVEC with the elements corresponding to the GPRs and/or memory . Return the number of elements used .


<s> void LEGFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = LEG :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: SUBrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: SUBri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void MipsAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { OutStreamer . AddBlankLine ( ) ; getTargetStreamer ( ) . emitDirectiveSetPop ( ) ; } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> unsigned ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return 1 ; if ( MI -> isBundle ( ) ) { unsigned Latency = 0 ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != ARM :: t2IT ) Latency += getInstrLatency ( ItinData , & * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) ) ) { * PredCost = 1 ; } if ( ! ItinData ) return MI -> mayLoad ( ) ? 3 : 1 ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < 0 ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI -> hasOneMemOperand ( ) ? ( * MI -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Adj = adjustDefLatency ( Subtarget , MI , & MCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


<s> void thumb2_asm_output_opcode ( FILE * stream ) { char buff [ 5 ] ; int n ; if ( arm_condexec_mask ) { for ( n = 0 ; n < arm_condexec_masklen ; n ++ ) buff [ n ] = ( arm_condexec_mask & ( 1 << n ) ) ? 't' : 'e' ; buff [ n ] = 0 ; asm_fprintf ( stream , "i%s\t%s\n\t" , buff , arm_condition_codes [ arm_current_cc ] ) ; arm_condexec_mask = 0 ; } } </s>


<s>
TargetLoweringBase
::
AtomicRMWExpansionKind
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
->
is64Bit
(
)
64
:
32
;
const
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
{
return
needsCmpXchgNb
(
MemType
)
AtomicRMWExpansionKind
::
CmpXChg
:
AtomicRMWExpansionKind
::
;
}
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
AtomicRMWExpansionKind
::
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
AtomicRMWExpansionKind
::
CmpXChg
:
AtomicRMWExpansionKind
::
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
return
AtomicRMWExpansionKind
::
CmpXChg
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static int rs6000_get_some_local_dynamic_name_1 ( rtx * px , void * data ATTRIBUTE_UNUSED ) { rtx x = * px ; if ( GET_CODE ( x ) == SYMBOL_REF ) { const char * str = XSTR ( x , 0 ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) { cfun -> machine -> some_ld_name = str ; return 1 ; } } return 0 ; } </s>

Helper function for rs6000_get_some_local_dynamic_name .


<s> class LLVM_LIBRARY_VISIBILITY X86MCInstLower { MCContext & Ctx ; Mangler * Mang ; const MachineFunction & MF ; const TargetMachine & TM ; const MCAsmInfo & MAI ; X86AsmPrinter & AsmPrinter ; public : X86MCInstLower ( Mangler * mang , const MachineFunction & MF , X86AsmPrinter & asmprinter ) ; void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCSymbol * GetSymbolFromOperand ( const MachineOperand & MO ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; private : MachineModuleInfoMachO & getMachOMMI ( ) const ; } </s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
if
(
!
selectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> Register SparcInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { SparcMachineFunctionInfo * SparcFI = MF -> getInfo < SparcMachineFunctionInfo > ( ) ; Register GlobalBaseReg = SparcFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * PtrRC = Subtarget . is64Bit ( ) ? & SP :: I64RegsRegClass : & SP :: IntRegsRegClass ; GlobalBaseReg = RegInfo . createVirtualRegister ( PtrRC ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( SP :: GETPCX ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Sparc Sparc Sparc Sparc Sparc Sparc SP::I64RegsRegClass SP::IntRegsRegClass SP::GETPCX Sparc


<s> static bool mips_load_call_address ( enum mips_call_type type , rtx dest , rtx addr ) { if ( TARGET_EXPLICIT_RELOCS && ! ( type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP ) && mips_ok_for_lazy_binding_p ( addr ) ) { addr = mips_got_load ( dest , addr , SYMBOL_GOTOFF_CALL ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , addr ) ) ; return true ; } else { mips_emit_move ( dest , addr ) ; return false ; } } </s>

Load function address ADDR into register DEST . SIBCALL_P is true if the address is needed for a sibling call .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

PowerPC PPC 0 PPCISD::FSEL "PPCISD::FSEL" PPCISD::FCFID "PPCISD::FCFID" PPCISD::FCTIDZ "PPCISD::FCTIDZ" PPCISD::FCTIWZ "PPCISD::FCTIWZ" PPCISD::STFIWX "PPCISD::STFIWX" PPCISD::VMADDFP "PPCISD::VMADDFP" PPCISD::VNMSUBFP "PPCISD::VNMSUBFP" PPCISD::VPERM "PPCISD::VPERM" PPCISD::Hi "PPCISD::Hi" PPCISD::Lo "PPCISD::Lo" PPCISD::TOC_ENTRY "PPCISD::TOC_ENTRY" PPCISD::DYNALLOC "PPCISD::DYNALLOC" PPCISD::GlobalBaseReg "PPCISD::GlobalBaseReg" PPCISD::SRL "PPCISD::SRL" PPCISD::SRA "PPCISD::SRA" PPCISD::SHL "PPCISD::SHL" PPCISD::EXTSW_32 "PPCISD::EXTSW_32" PPCISD::STD_32 "PPCISD::STD_32" PPCISD::CALL_SVR4 "PPCISD::CALL_SVR4" PPCISD::CALL_Darwin "PPCISD::CALL_Darwin" PPCISD::NOP "PPCISD::NOP" PPCISD::MTCTR "PPCISD::MTCTR" PPCISD::BCTRL_Darwin "PPCISD::BCTRL_Darwin" PPCISD::BCTRL_SVR4 "PPCISD::BCTRL_SVR4" PPCISD::RET_FLAG "PPCISD::RET_FLAG" PPCISD::MFCR "PPCISD::MFCR" PPCISD::VCMP "PPCISD::VCMP" PPCISD::VCMPo "PPCISD::VCMPo" PPCISD::LBRX "PPCISD::LBRX" PPCISD::STBRX "PPCISD::STBRX" PPCISD::LARX "PPCISD::LARX" PPCISD::STCX "PPCISD::STCX" PPCISD::COND_BRANCH "PPCISD::COND_BRANCH" PPCISD::MFFS "PPCISD::MFFS" PPCISD::MTFSB0 "PPCISD::MTFSB0" PPCISD::MTFSB1 "PPCISD::MTFSB1" PPCISD::FADDRTZ "PPCISD::FADDRTZ" PPCISD::MTFSF "PPCISD::MTFSF" PPCISD::TC_RETURN "PPCISD::TC_RETURN"