<s> unsigned getPointerSize ( ) const { return 8 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> static tree mips_std_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { tree addr , t , type_size , rounded_size , valist_tmp ; unsigned HOST_WIDE_INT align , boundary ; bool indirect ; indirect = pass_va_arg_by_reference ( type ) ; if ( indirect ) type = build_pointer_type ( type ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = targetm . calls . function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; if ( boundary > align ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - 1 ) ) ; gimplify_and_add ( t , pre_p ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build2 ( BIT_AND_EXPR , TREE_TYPE ( valist ) , valist_tmp , build_int_cst ( TREE_TYPE ( valist ) , - boundary ) ) ) ; gimplify_and_add ( t , pre_p ) ; } else boundary = align ; boundary *= BITS_PER_UNIT ; if ( boundary < TYPE_ALIGN ( type ) ) { type = build_variant_type_copy ( type ) ; SET_TYPE_ALIGN ( type , boundary ) ; } type_size = size_in_bytes ( type ) ; rounded_size = round_up ( type_size , align ) ; gimplify_expr ( & rounded_size , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = valist_tmp ; if ( PAD_VARARGS_DOWN && ! integer_zerop ( rounded_size ) ) { t = fold_build2_loc ( input_location , GT_EXPR , sizetype , rounded_size , size_int ( align ) ) ; t = fold_build3 ( COND_EXPR , sizetype , t , size_zero_node , size_binop ( MINUS_EXPR , rounded_size , type_size ) ) ; addr = fold_build_pointer_plus ( addr , t ) ; } t = fold_build_pointer_plus ( valist_tmp , rounded_size ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( indirect ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>

Like std_gimplify_va_arg_expr , but apply alignment to zero-sized types as well .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const Thumb1RegisterInfo & MRI , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> bool isKMasked ( ) const { return ( Attributes & ( KMergeMasked | KZeroMasked ) ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds any of k-masked opcodes .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
;
if
(
Constraint
.
length
(
)
>
1
)
return
;
char
Letter
=
Constraint
[
0
]
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
unsigned
Value
=
CST
->
getZExtValue
(
)
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'J'
:
case
'L'
:
if
(
(
short
)
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'K'
:
if
(
(
Value
>>
16
)
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'N'
:
if
(
(
int
)
Value
>
0
&&
isPowerOf2_32
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'P'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> void thumb1_gen_const_int ( rtx op0 , HOST_WIDE_INT op1 ) { bool mov_done_p = false ; int i ; for ( i = 0 ; i < 3 ; i ++ ) { int byte = ( op1 >> ( 8 * ( 3 - i ) ) ) & 0xff ; if ( byte ) { emit_set_insn ( op0 , mov_done_p ? gen_rtx_PLUS ( SImode , op0 , GEN_INT ( byte ) ) : GEN_INT ( byte ) ) ; mov_done_p = true ; } if ( mov_done_p ) emit_set_insn ( op0 , gen_rtx_ASHIFT ( SImode , op0 , GEN_INT ( 8 ) ) ) ; } if ( ! mov_done_p ) emit_set_insn ( op0 , GEN_INT ( op1 & 0xff ) ) ; else if ( op1 & 0xff ) emit_set_insn ( op0 , gen_rtx_PLUS ( SImode , op0 , GEN_INT ( op1 & 0xff ) ) ) ; } </s>

Emit a sequence of movs/adds/shift to produce a 32-bit constant . Avoid generating useless code when one of the bytes is zero .


<s> static bool mips_mode_ok_for_mov_fmt_p ( machine_mode mode ) { switch ( mode ) { case CCFmode : case SFmode : return TARGET_HARD_FLOAT ; case DFmode : return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ; case V2SFmode : return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT ; default : return false ; } } </s>

Return true if moves in mode MODE can use the FPU 's mov.fmt instruction .


<s> static void assign_int_registers ( HOST_WIDE_INT bitpos , assign_data_t * data ) { int intoffset = data -> intoffset ; machine_mode mode ; int nregs ; if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != 0 ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; data -> nregs += 1 ; mode = word_mode ; regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign the bits of the structure between PARMS- > intoffset and BITPOS to integer registers .


<s> std :: string getNodeLabel ( NodeRef Node , GraphType * ) { if ( Node -> getValue ( ) == MachineGadgetGraph :: ArgNodeSentinel ) return "ARGS" ; std :: string Str ; raw_string_ostream OS ( Str ) ; OS << * Node -> getValue ( ) ; return OS . str ( ) ; } </s>

Print a DDG node either in concise form ( -ddg-dot-only ) or verbose mode ( -ddg-dot ) .


<s> inline void X86EncodeLiteralsPass :: buildXor ( MachineInstr & MI , unsigned Index , uint64_t Operand ) { MachineBasicBlock * PMBB = MI . getParent ( ) ; MachineBasicBlock :: instr_iterator Iter = skip ( PMBB , Index ) ; int64_t Offset = MI . getOperand ( 3 ) . getImm ( ) ; unsigned XOROpc = getXorOpc ( MI ) ; addRegOffset ( BuildMI ( * PMBB , Iter , MI . getDebugLoc ( ) , TII -> get ( XOROpc ) ) , X86 :: RBP , true , Offset ) . addImm ( Operand ) ; } </s>

Build and insert Res = G_XOR Op0 , Op1 .


<s> bool aarch64_uimm12_shift ( HOST_WIDE_INT val ) { return ( ( val & ( ( ( HOST_WIDE_INT ) 0xfff ) << 0 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xfff ) << 12 ) ) == val ) ; } </s>

Return true if val can be encoded as a 12-bit unsigned immediate with a left shift of 0 or 12 bits .


<s> bool X86TargetLowering :: isLoadBitCastBeneficial ( EVT LoadVT , EVT BitcastVT ) const { if ( ! Subtarget . hasDQI ( ) && BitcastVT == MVT :: v8i1 ) return false ; return TargetLowering :: isLoadBitCastBeneficial ( LoadVT , BitcastVT ) ; } </s>

Return true if the following transform is beneficial : fold ( conv ( load x ) ) - > ( load ( conv * ) x ) On architectures that do n't natively support some vector loads efficiently , casting the load to a smaller vector of larger types and loading is more efficient , however , this can be undone by optimizations in dag combiner .


";; Emitting minipool after insn %u;\ address %ld; align %d (bytes)\n"


<s> bool sh_is_logical_t_store_expr ( rtx op , rtx_insn * insn ) { if ( ! logical_operator ( op , SImode ) ) return false ; rtx ops [ 2 ] = { XEXP ( op , 0 ) , XEXP ( op , 1 ) } ; int op_is_t_count = 0 ; for ( int i = 0 ; i < 2 ; ++ i ) { if ( t_reg_operand ( ops [ i ] , VOIDmode ) || negt_reg_operand ( ops [ i ] , VOIDmode ) ) op_is_t_count ++ ; else { set_of_reg op_set = sh_find_set_of_reg ( ops [ i ] , insn , prev_nonnote_insn_bb ) ; if ( op_set . set_src == NULL_RTX ) continue ; if ( t_reg_operand ( op_set . set_src , VOIDmode ) || negt_reg_operand ( op_set . set_src , VOIDmode ) || sh_is_logical_t_store_expr ( op_set . set_src , op_set . insn ) ) op_is_t_count ++ ; } } return op_is_t_count == 2 ; } </s>

Given an op rtx and an insn , try to find out whether the result of the specified op consists only of logical operations on T bit stores .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; unsigned opcode = MI . getOpcode ( ) ; uint16_t validDomains = 0 ; if ( domain ) { if ( lookup ( MI . getOpcode ( ) , domain , ReplaceableInstrs ) ) { validDomains = 0xe ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = 0xe ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = Subtarget . hasDQI ( ) ? 0xe : 0x8 ; } else if ( const uint16_t * table = lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQMasked ) ) { if ( domain == 1 || ( domain == 3 && table [ 3 ] == opcode ) ) validDomains = Subtarget . hasDQI ( ) ? 0xa : 0x8 ; else validDomains = Subtarget . hasDQI ( ) ? 0xc : 0x8 ; } } return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> static rtx swap_selector_for_mode ( machine_mode mode ) { unsigned int swap2 [ 16 ] = { 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 } ; unsigned int swap4 [ 16 ] = { 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 , 11 , 10 , 9 , 8 , 15 , 14 , 13 , 12 } ; unsigned int swap8 [ 16 ] = { 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 , 9 , 8 , 11 , 10 , 13 , 12 , 15 , 14 } ; unsigned int swap16 [ 16 ] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 } ; unsigned int * swaparray , i ; rtx perm [ 16 ] ; switch ( mode ) { case V2DFmode : case V2DImode : swaparray = swap2 ; break ; case V4SFmode : case V4SImode : swaparray = swap4 ; break ; case V8HImode : swaparray = swap8 ; break ; case V16QImode : swaparray = swap16 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < 16 ; ++ i ) perm [ i ] = GEN_INT ( swaparray [ i ] ) ; return force_reg ( V16QImode , gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , perm ) ) ) ; } </s>

Return a constant vector for use as a little-endian permute control vector to reverse the order of elements of the given vector mode .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - MF . getSubtarget < SparcSubtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc Sparc Sparc Sparc Sparc Sparc SP::SAVEri SP::SAVErr 0 SP::ADDri SP::ADDrr Sparc SP SP::I6 SP::I7 SP::O7


<s> static void aarch64_init_builtins ( ) { aarch64_general_init_builtins ( ) ; aarch64_sve :: init_builtins ( ) ; } </s>


<s> bool isMem ( ) const override { return false ; } </s>


<s> static bool ix86_check_avx_upper_register ( const_rtx exp ) { if ( SUBREG_P ( exp ) ) exp = SUBREG_REG ( exp ) ; return ( REG_P ( exp ) && ( VALID_AVX256_REG_OR_OI_MODE ( GET_MODE ( exp ) ) || VALID_AVX512F_REG_OR_XI_MODE ( GET_MODE ( exp ) ) ) ) ; } </s>

Check if a 256bit or 512 bit AVX register is referenced inside of EXP .


<s> X86GenInstrInfo :: MachineOutlinerInstrType X86InstrInfo :: getOutliningType ( MachineInstr & MI ) const { if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_condbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_blx"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) || thumb_far_jump_used_p ( ) || df_regs_ever_live_p ( LR_REGNUM ) ) ; } </s>

Return true if the current function needs to save/restore LR .


<s> static bool fa726te_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int * cost ) { if ( dep_type == REG_DEP_TRUE && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 && get_attr_conds ( dep ) == CONDS_SET ) { if ( get_attr_conds ( insn ) == CONDS_USE && get_attr_type ( insn ) != TYPE_BRANCH ) { * cost = 3 ; return false ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC || get_attr_conds ( insn ) == CONDS_USE ) { * cost = 0 ; return false ; } } return true ; } </s>


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ; else return 0 ; } </s>


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MipsSubtarget & Subtarget = MF -> getSubtarget < MipsSubtarget > ( ) ; const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( "interrupt" ) ) { if ( Subtarget . hasMips64 ( ) ) return Subtarget . hasMips64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . hasMips32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_CheriPureCap ( ) ) return CSR_Cheri_Purecap_SaveList ; if ( Subtarget . isCheri ( ) ) return CSR_N64_Cheri_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>

Mips Mips Mips Mips "interrupt" Mips Mips Mips


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Mips
::
NumTargetFixupKinds
]
=
{
{
"fixup_Mips_NONE"
,
0
,
0
,
0
}
,
{
"fixup_Mips_16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_26"
,
0
,
26
,
0
}
,
{
"fixup_Mips_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Mips_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Mips_64"
,
0
,
64
,
0
}
,
{
"fixup_Mips_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int mmix_shiftable_wyde_value ( uint64_t value ) { int i ; int has_candidate = 0 ; for ( i = 0 ; i < 4 ; i ++ ) { if ( value & 65535 ) { if ( has_candidate ) return 0 ; else has_candidate = 1 ; } value >>= 16 ; } return 1 ; } </s>

Return 1 if value is 0 .. 65535 * 2 * * ( 16 * N ) for N=0 .. 3. else return 0 .


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> int arm_split_constant ( enum rtx_code code , enum machine_mode mode , rtx insn , HOST_WIDE_INT val , rtx target , rtx source , int subtargets ) { rtx cond ; if ( insn && GET_CODE ( PATTERN ( insn ) ) == COND_EXEC ) cond = COND_EXEC_TEST ( PATTERN ( insn ) ) ; else cond = NULL_RTX ; if ( subtargets || code == SET || ( GET_CODE ( target ) == REG && GET_CODE ( source ) == REG && REGNO ( target ) != REGNO ( source ) ) ) { if ( ! after_arm_reorg && ! cond && ( arm_gen_constant ( code , mode , NULL_RTX , val , target , source , 1 , 0 ) > arm_constant_limit + ( code != SET ) ) ) { if ( code == SET ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , GEN_INT ( val ) ) ) ; return 1 ; } else { rtx temp = subtargets ? gen_reg_rtx ( mode ) : target ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , GEN_INT ( val ) ) ) ; if ( code == MINUS ) emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_MINUS ( mode , temp , source ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , mode , source , temp ) ) ) ; return 2 ; } } } return arm_gen_constant ( code , mode , cond , val , target , source , subtargets , 1 ) ; } </s>

Emit a sequence of insns to handle a large constant . CODE is the code of the operation required , it can be any of SET , PLUS , IOR , AND , XOR , MINUS ; MODE is the mode in which the operation is being performed ; VAL is the integer to operate on ; SOURCE is the other operand ( a register , or a null-pointer for SET ) ; SUBTARGETS means it is safe to create scratch registers if that will either produce a simpler sequence , or we will want to cse the values . Return value is the number of insns emitted .


<s> static void mips_reorg ( void ) { if ( TARGET_MIPS16 ) mips16_lay_out_constants ( ) ; else if ( TARGET_EXPLICIT_RELOCS ) { if ( mips_flag_delayed_branch ) dbr_schedule ( get_insns ( ) , dump_file ) ; mips_avoid_hazards ( ) ; if ( TUNE_MIPS4130 && TARGET_VR4130_ALIGN ) vr4130_align_insns ( ) ; } } </s>


<s> void UnwindOpcodeAssembler :: EmitRegSave ( uint32_t RegSave ) { if ( RegSave == 0u ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_RA_AUTH_CODE ) ; return ; } if ( RegSave & ( 1u << 4 ) ) { uint32_t Mask = RegSave & 0xff0u ; uint32_t Range = countTrailingOnes ( Mask >> 5 ) ; Mask &= ~ ( 0xffffffe0u << Range ) ; uint32_t UnmaskedReg = RegSave & 0xfff0u & ( ~ Mask ) ; if ( UnmaskedReg == 0u ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4 | Range ) ; RegSave &= 0x000fu ; } else if ( UnmaskedReg == ( 1u << 14 ) ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range ) ; RegSave &= 0x000fu ; } } if ( ( RegSave & 0xfff0u ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK_R4 | ( RegSave >> 4 ) ) ; if ( ( RegSave & 0x000fu ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK | ( RegSave & 0x000fu ) ) ; } </s>

Emit unwind opcodes for .save directives .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) , bool MatchingInlineAsm = false ) { if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> void X86PassConfig :: addPreRegAlloc ( ) { addPass ( createX86CallFrameOptimization ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"ARM pre- register allocation load / store optimization pass"

getPassName - Return a nice clean name for a pass .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , Subtarget . isLittleEndian ( ) ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * GISel = new AArch64GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> RegBankInfo . reset ( new AArch64RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool i386_pe_valid_dllimport_attribute_p ( const_tree decl ) { if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; return true ; } </s>

Handle the -mno-fun-dllimport target switch .


<s> static void pru_asm_function_prologue ( FILE * file ) { if ( flag_verbose_asm || flag_debug_asm ) pru_dump_frame_layout ( file ) ; } </s>


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> void pa_hpux_asm_output_external ( FILE * file , tree decl , const char * name ) { gcc_assert ( file == asm_out_file ) ; extern_symbol p = { decl , name } ; vec_safe_push ( extern_symbols , p ) ; } </s>

Mark DECL ( name NAME ) as an external reference ( assembler output file FILE ) . This saves the names to output at the end of the file if actually referenced .


<s> static rtx ix86_expand_sse_fabs ( rtx op0 , rtx * smask ) { machine_mode vmode , mode = GET_MODE ( op0 ) ; rtx xa , mask ; xa = gen_reg_rtx ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; mask = ix86_build_signbit_mask ( vmode , VECTOR_MODE_P ( mode ) , true ) ; if ( ! VECTOR_MODE_P ( mode ) ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) ) ; tmp = gen_rtx_VEC_SELECT ( mode , mask , tmp ) ; mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , tmp ) ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , xa , gen_rtx_AND ( mode , op0 , mask ) ) ) ; if ( smask ) * smask = mask ; return xa ; } </s>

Expand fabs ( OP0 ) and return a new rtx that holds the result . The mask for masking out the sign-bit is stored in * SMASK , if that is non-null .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . isOSWindows ( ) || TargetABI == ARMBaseTargetMachine :: ARM_ABI_AAPCS16 ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } initAsmInfo ( ) ; } </s>


<s> static rtx aarch64_bit_representation ( rtx x ) { if ( CONST_DOUBLE_P ( x ) ) x = gen_lowpart ( int_mode_for_mode ( GET_MODE ( x ) ) . require ( ) , x ) ; return x ; } </s>

If X is a CONST_DOUBLE , return its bit representation as a constant integer , otherwise return X unmodified .


<s> int PPCTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCostInst ( Opcode , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void aarch64_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , rtx sel ) { machine_mode vmode = GET_MODE ( target ) ; unsigned int nelt = GET_MODE_NUNITS ( vmode ) ; bool one_vector_p = rtx_equal_p ( op0 , op1 ) ; rtx mask ; mask = aarch64_simd_gen_const_vector_dup ( vmode , one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; sel = expand_simple_binop ( vmode , AND , sel , mask , NULL , 0 , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) { if ( ! one_vector_p ) mask = aarch64_simd_gen_const_vector_dup ( vmode , nelt - 1 ) ; sel = expand_simple_binop ( vmode , XOR , sel , mask , NULL , 0 , OPTAB_LIB_WIDEN ) ; } aarch64_expand_vec_perm_1 ( target , op0 , op1 , sel ) ; } </s>

Expand a vec_perm with the operands given by TARGET , OP0 , OP1 and SEL . NELT is the number of elements in the vector .


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" || CPU == "pentium" || CPU == "pentium-mmx" || CPU == "geode" ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , ( uint64_t ) 15 ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool Thumb2RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> inline set_of_reg sh_find_set_of_reg ( rtx reg , rtx_insn * insn , F stepfunc , bool ignore_reg_reg_copies = false ) { set_of_reg result ; result . insn = insn ; result . set_rtx = NULL_RTX ; result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_set_p ( reg , i ) ) { if ( CALL_P ( i ) ) break ; result . insn = i ; result . set_rtx = set_of ( reg , i ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , 1 ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) { reg = SUBREG_REG ( result . set_src ) ; continue ; } break ; } } if ( result . set_src != NULL && result . set_rtx == NULL ) result . set_src = NULL ; return result ; } </s>

Given a reg rtx and a start insn , try to find the insn that sets the specified reg by using the specified insn stepping function , such as 'prev_nonnote_insn_bb ' . When the insn is found , try to extract the rtx of the reg set .


<s> static bool aarch64_extending_load_p ( stmt_vec_info stmt_info ) { gassign * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ; if ( ! assign || ! CONVERT_EXPR_CODE_P ( gimple_assign_rhs_code ( assign ) ) ) return false ; tree rhs = gimple_assign_rhs1 ( stmt_info -> stmt ) ; tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( rhs ) ; if ( ! INTEGRAL_TYPE_P ( lhs_type ) || ! INTEGRAL_TYPE_P ( rhs_type ) || TYPE_PRECISION ( lhs_type ) <= TYPE_PRECISION ( rhs_type ) ) return false ; stmt_vec_info def_stmt_info = stmt_info -> vinfo -> lookup_def ( rhs ) ; return ( def_stmt_info && STMT_VINFO_DATA_REF ( def_stmt_info ) && DR_IS_READ ( STMT_VINFO_DATA_REF ( def_stmt_info ) ) ) ; } </s>

Return true if STMT_INFO extends the result of a load .


<s> bool KudeyarFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; KudeyarMachineFunctionInfo * MFI = MF . getInfo < KudeyarMachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 4 ) ; if ( CSI . size ( ) > 1 ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: PUSHA ) ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } else { unsigned Reg = CSI [ 0 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: PUSH_R ) ) . addReg ( Reg , RegState :: Kill ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Kudeyar :: PUSH_R ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else return true ; } else if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"Unexpected operand for inline assembly"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( const Type * Ty ) const { const TargetMachine & TM = getTargetMachine ( ) ; if ( TM . getSubtarget < PPCSubtarget > ( ) . isDarwin ( ) ) return 4 ; return 4 ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> SDNode * TeeRISCDAGToDAGISel :: Select ( SDNode * N ) { DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case TeeRISC_ISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfo > ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : 0 ; LibInfo = getAnalysisIfAvailable < TargetLibraryInfo > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
PPCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
PPC
::
GPRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR
;
else
if
(
PPC
::
G8RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR8
;
else
if
(
PPC
::
F4RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
FMR
;
else
if
(
PPC
::
CRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
MCRF
;
else
if
(
PPC
::
VRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
VOR
;
else
if
(
PPC
::
CRBITRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
CROR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
const
MCInstrDesc
&
MCID
=
get
(
Opc
)
;
if
(
MCID
.
getNumOperands
(
)
==
3
)
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DestReg
)
.
addReg
(
SrcReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

PowerPC
PPC
PPC::GPRCRegClass
PPC::OR
PPC::G8RCRegClass
PPC::OR8
PPC::F4RCRegClass
PPC::FMR
PPC::CRRCRegClass
PPC::MCRF
PPC::VRRCRegClass
PPC::VOR
PPC::CRBITRCRegClass
PPC::CROR
"Impossible reg-to-reg copy"
3


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> getDesc ( ) . mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s>
bool
ARMTargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeAllocSizeInBits
(
SubVecTy
)
;
bool
EltIs64Bits
=
DL
.
getTypeAllocSizeInBits
(
EltTy
)
==
64
;
if
(
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
||
EltIs64Bits
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
Op0
->
getType
(
)
->
getVectorNumElements
(
)
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
static
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
arm_neon_vst2
,
Intrinsic
::
arm_neon_vst3
,
Intrinsic
::
arm_neon_vst4
}
;
Function
*
VstNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
SubVecTy
)
;
SmallVector
<
Value
*
,
6
>
Ops
;
Type
*
Int8Ptr
=
Builder
.
getInt8PtrTy
(
SI
->
getPointerAddressSpace
(
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
Int8Ptr
)
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
getInt32
(
SI
->
getAlignment
(
)
)
)
;
Builder
.
CreateCall
(
VstNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> bool aarch64_atomic_ldop_supported_p ( enum rtx_code code ) { if ( ! TARGET_LSE ) return false ; switch ( code ) { case SET : case AND : case IOR : case XOR : case MINUS : case PLUS : return true ; default : return false ; } } </s>

Test whether the target supports using a atomic load-operate instruction . CODE is the operation and AFTER is TRUE if the data in memory after the operation should be returned and FALSE if the data before the operation should be returned . Returns FALSE if the operation is n't supported by the architecture .


<s> MachineInstr * SystemZInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , MachineInstr * LoadMI ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static bool aarch64_sve_pred_mode_p ( machine_mode mode ) { return ( TARGET_SVE && ( mode == VNx16BImode || mode == VNx8BImode || mode == VNx4BImode || mode == VNx2BImode ) ) ; } </s>

Return true if MODE is an SVE predicate mode .


<s> Register SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; const SystemZSubtarget * Subtarget = & MF . getSubtarget < SystemZSubtarget > ( ) ; SystemZCallingConventionRegisters * Regs = Subtarget -> getSpecialRegisters ( ) ; return TFI -> hasFP ( MF ) ? Regs -> getFramePointerRegister ( ) : Regs -> getStackPointerRegister ( ) ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static int mips_fpr_return_fields ( tree valtype , tree * fields ) { tree field ; int i ; if ( ! TARGET_NEWABI ) return 0 ; if ( TREE_CODE ( valtype ) != RECORD_TYPE ) return 0 ; i = 0 ; for ( field = TYPE_FIELDS ( valtype ) ; field != 0 ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( TREE_CODE ( TREE_TYPE ( field ) ) != REAL_TYPE ) return 0 ; if ( i == 2 ) return 0 ; fields [ i ++ ] = field ; } return i ; } </s>

See whether VALTYPE is a record whose fields should be returned in floating-point registers . If so , return the number of fields and list them in FIELDS ( which should have two elements ) . Return 0 otherwise . For n32 & n64 , a structure with one or two fields is returned in floating-point registers as long as every field has a floating-point type . The C++ FE used to remove zero-width bit-fields in GCC 11 and earlier . To make a proper diagnostic , this function will set HAS_CXX_ZERO_WIDTH_BF to true once a C++ zero-width bit-field shows up , and then ignore it . We had failed to ignore C++17 empty bases in GCC 7 , 8 , 9 , 10 , and 11 . This caused an ABI incompatibility between C++14 and C++17 . This is fixed now and to make a proper diagnostic , this function will set HAS_CXX17_EMPTY_BASE to true once a C++17 empty base shows up , and then ignore it . The caller should use the value of HAS_CXX17_EMPTY_BASE and/or HAS_CXX_ZERO_WIDTH_BF to emit a proper -Wpsabi inform .


<s>
std
::
unique_ptr
<
LanaiOperand
>
LanaiAsmParser
::
parseIdentifier
(
)
{
SMLoc
Start
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
SMLoc
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
const
MCExpr
*
Res
,
*
RHS
=
nullptr
;
LanaiMCExpr
::
VariantKind
Kind
=
LanaiMCExpr
::
VK_Lanai_None
;
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
Identifier
)
return
nullptr
;
StringRef
Identifier
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
if
(
Identifier
.
equals_insensitive
(
"hi"
)
)
Kind
=
LanaiMCExpr
::
VK_Lanai_ABS_HI
;
else
if
(
Identifier
.
equals_insensitive
(
"lo"
)
)
Kind
=
LanaiMCExpr
::
VK_Lanai_ABS_LO
;
if
(
Kind
!=
LanaiMCExpr
::
VK_Lanai_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
LParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected '('"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
}
if
(
Lexer
.
getKind
(
)
==
AsmToken
::
Plus
&&
Parser
.
parseExpression
(
RHS
)
)
return
nullptr
;
if
(
Kind
!=
LanaiMCExpr
::
VK_Lanai_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
RParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected ')'"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
}
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
MCSymbol
*
Sym
=
getContext
(
)
.
getOrCreateSymbol
(
Identifier
)
;
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Sym
,
getContext
(
)
)
;
Res
=
LanaiMCExpr
::
create
(
Kind
,
Expr
,
getContext
(
)
)
;
if
(
RHS
)
Res
=
MCBinaryExpr
::
createAdd
(
Res
,
RHS
,
getContext
(
)
)
;
return
LanaiOperand
::
createImm
(
Res
,
Start
,
End
)
;
}
</s>

Parse an identifier or string ( as a quoted identifier ) and set Res to the identifier contents .

Lanai
Lanai
Lanai
1
Lanai
Lanai
Lanai
"hi"
Lanai
Lanai
"lo"
Lanai
Lanai
Lanai
Lanai
"Expected '('"
Lanai
Lanai
"Expected ')'"
1
Lanai
LanaiOperand::createImm


<s> unsigned char PPCSubtarget :: classifyGlobalReference ( const GlobalValue * GV ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return PPCII :: MO_PIC_FLAG | PPCII :: MO_NLP_FLAG ; unsigned char flags = PPCII :: MO_PIC_FLAG ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( ! GV -> hasLocalLinkage ( ) && GV -> hasDefaultVisibility ( ) ) { flags |= PPCII :: MO_NLP_FLAG ; } return flags ; } if ( GV -> isStrongDefinitionForLinker ( ) ) return flags ; return flags | PPCII :: MO_NLP_FLAG ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool AArch64InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: SBFMXri : case AArch64 :: UBFMXri : if ( MI . getOperand ( 2 ) . getImm ( ) != 0 || MI . getOperand ( 3 ) . getImm ( ) != 31 ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = AArch64 :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , const CCValAssign & VA ) { MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


"Only optimizing constant comparisons so far"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


"No expandLargeImm(SP, StackSize, false, TII, MBB, MBBI, dl);"


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; TII = static_cast < const AArch64InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_src , permute_tmp ; gcc_assert ( ! reload_in_progress && ! lra_in_progress && ! reload_completed ) ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , 0 ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source ) : source ; permute_src = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_tmp = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_src ) ) ; emit_insn ( gen_rtx_SET ( dest , permute_tmp ) ) ; } </s>

Emit a little-endian store to vector memory location DEST from VSX register SOURCE in mode MODE . The store is done with two permuting insn 's that represent an xxpermdi and an stxvd2x .


<s> const ARMSubtarget & getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return true ; if ( Kind == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , unsigned EncodingAlignment ) const { if ( SelectAddressPCRel ( N , Base ) ) return false ; int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( hasSPE ( ) && SelectAddressEVXRegReg ( N , Base , Index , DAG ) ) return true ; if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( 1 ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; const ARMSubtarget * Subtarget = & getARMSubtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static rtx_insn * aarch64_speculation_establish_tracker ( ) { rtx sp = gen_rtx_REG ( DImode , SP_REGNUM ) ; rtx tracker = gen_rtx_REG ( DImode , SPECULATION_TRACKER_REGNUM ) ; start_sequence ( ) ; rtx cc = aarch64_gen_compare_reg ( EQ , sp , const0_rtx ) ; emit_insn ( gen_cstoredi_neg ( tracker , gen_rtx_NE ( CCmode , cc , const0_rtx ) , cc ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } </s>

Generate a code sequence to establish the tracker variable from the contents of SP .


<s>
static
const
char
*
arm_invalid_within_doloop
(
const
rtx_insn
*
insn
)
{
if
(
!
TARGET_HAVE_LOB
)
return
default_invalid_within_doloop
(
insn
)
;
if
(
CALL_P
(
insn
)
)
return
"Function call in the loop."
;
if
(
reg_mentioned_p
(
gen_rtx_REG
(
SImode
,
LR_REGNUM
)
,
insn
)
)
return
"LR is used inside loop."
;
return
;
}
</s>

NULL if insn INSN is valid within a low-overhead loop . Otherwise return why doloop can not be applied .

arm
"Function call in the loop."
"LR is used inside loop."


"********** AArch64 Conditional Compares **********\n"


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && ( N -> getOpcode ( ) == ISD :: LOAD || N -> getOpcode ( ) == ISD :: STORE ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == ISD :: ADD && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::LOAD ISD::STORE ISD::SEXTLOAD ARM ISD::ADD ISD::POST_INC ISD::POST_DEC


<s> bool SystemZTTIImpl :: hasDivRemOp ( Type * DataType , bool IsSigned ) { EVT VT = TLI -> getValueType ( DL , DataType ) ; return ( VT . isScalarInteger ( ) && TLI -> isTypeLegal ( VT ) ) ; } </s>

Return true if the target has a unified operation to calculate division and remainder .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & , unsigned TCycles , unsigned TExtra , MachineBasicBlock & , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = 1024 ; unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; return ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor <= UnpredCost ; } </s>


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { KnownBits Known2 ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : Known = DAG . computeKnownBits ( Op . getOperand ( 1 ) , Depth + 1 ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


"\nrs6000_preferred_reload_class, return %s, rclass = %s, "

Debug version of rs6000_preferred_reload_class .


<s> bool isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const override { ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( 1 ) ) ; return Mask && Mask -> getValue ( ) . isIntN ( 16 ) ; } </s>

Return if the target supports combining a chain like :


<s> const SDValue & getValue ( ) const { return getOperand ( 3 ) ; } </s>


<s> TargetPassConfig * UPTTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new UPTPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM::tRestore
0


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: Trap || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::Trap SystemZ::CallJG SystemZ::CallBR


<s> bool ARMAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb" ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb_func" ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".code" ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".syntax" ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void PPCInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , 4 > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = 0 , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; } </s>


<s> Optional < MCFixupKind > ELFPPCAsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . isOSBinFormatELF ( ) ) { unsigned Type ; if ( TT . isPPC64 ( ) ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; } if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool isMem ( ) const override { return Kind == Memory ; } </s>


<s> StackOffset VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( ! hasFP ( MF ) ) { FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = VE :: SX17 ; else FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> gimple * fold ( gimple_folder & f ) const OVERRIDE { poly_uint64 nelts = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( f . lhs ) ) ; poly_uint64 base = m_base * exact_div ( nelts , 2 ) ; vec_perm_builder builder ( nelts , 2 , 3 ) ; for ( unsigned int i = 0 ; i < 3 ; ++ i ) { builder . quick_push ( base + i ) ; builder . quick_push ( base + i + nelts ) ; } return fold_permute ( f , builder ) ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> void rs6000_emit_cbranch ( enum rtx_code code , rtx loc ) { rtx condition_rtx , loc_ref ; condition_rtx = rs6000_generate_compare ( code ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , loc ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s> bool aarch64_reinterpret_float_as_int ( rtx value , unsigned HOST_WIDE_INT * intval ) { if ( aarch64_float_const_zero_rtx_p ( value ) ) { * intval = 0 ; return true ; } scalar_float_mode mode ; if ( ! CONST_DOUBLE_P ( value ) || ! is_a < scalar_float_mode > ( GET_MODE ( value ) , & mode ) || GET_MODE_BITSIZE ( mode ) > HOST_BITS_PER_WIDE_INT || GET_MODE_BITSIZE ( mode ) > GET_MODE_BITSIZE ( DFmode ) ) return false ; unsigned HOST_WIDE_INT ival = 0 ; long res [ 2 ] ; real_to_target ( res , CONST_DOUBLE_REAL_VALUE ( value ) , REAL_MODE_FORMAT ( mode ) ) ; if ( mode == DFmode ) { int order = BYTES_BIG_ENDIAN ? 1 : 0 ; ival = zext_hwi ( res [ order ] , 32 ) ; ival |= ( zext_hwi ( res [ 1 - order ] , 32 ) << 32 ) ; } else ival = zext_hwi ( res [ 0 ] , 32 ) ; * intval = ival ; return true ; } </s>

Return the binary representation of floating point constant VALUE in INTVAL . If the value can not be converted , return false without setting INTVAL . The conversion is done in the given MODE .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> const SparcSubtarget * SparcTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < SparcSubtarget > ( TargetTriple , CPU , FS , * this , this -> is64Bit ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Sparc Sparc Sparc "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" Sparc


<s> int xstormy16_interrupt_function_p ( ) { tree attributes ; if ( ! cfun ) return 0 ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return lookup_attribute ( "interrupt" , attributes ) != NULL_TREE ; } </s>

Return nonzero if the function is an interrupt function .


"Tiny codesize model not supported on X86"

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> static machine_mode mode_from_flags ( unsigned int f ) { if ( f & CC_FLAG_FP ) return CC_Fmode ; if ( f & CC_FLAG_O ) { if ( f & CC_FLAG_C ) return CCmode ; else return CC_ZSOmode ; } else if ( f & CC_FLAG_C ) return CC_ZSCmode ; else return CC_ZSmode ; } </s>

Convert a set of flags to a CC_MODE that can implement it .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . isDarwin ( ) ) return 4 ; unsigned Align = Subtarget . isPPC64 ( ) ? 8 : 4 ; if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , Subtarget . hasQPX ( ) ? 32 : 16 ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> static unsigned int aarch64_sve_adjust_stmt_cost ( vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , unsigned int stmt_cost ) { if ( kind == vector_stmt && aarch64_extending_load_p ( stmt_info ) ) stmt_cost = 0 ; if ( kind == vector_stmt && aarch64_integer_truncation_p ( stmt_info ) ) stmt_cost = 0 ; if ( STMT_VINFO_GROUPED_ACCESS ( stmt_info ) ) { stmt_vec_info first = DR_GROUP_FIRST_ELEMENT ( stmt_info ) ; unsigned int count = DR_GROUP_SIZE ( first ) - DR_GROUP_GAP ( first ) ; unsigned int elt_bits = GET_MODE_UNIT_BITSIZE ( TYPE_MODE ( vectype ) ) ; if ( multiple_p ( count * elt_bits , 256 ) && aarch64_advsimd_ldp_stp_p ( kind , stmt_info ) ) stmt_cost *= 2 ; } return stmt_cost ; } </s>

STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost for STMT_INFO , which has cost kind KIND and which when vectorized would operate on vector type VECTYPE . Adjust the cost as necessary for SVE targets .


"Can't load this register from stack slot"


<s>
bool
X86TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
assert
(
cast
<
FixedVectorType
>
(
SVI
->
getType
(
)
)
->
getNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
SmallVector
<
unsigned
,
4
>
Indices
;
auto
Mask
=
SVI
->
getShuffleMask
(
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Indices
.
push_back
(
Mask
[
i
]
)
;
ArrayRef
<
ShuffleVectorInst
*
>
Shuffles
=
makeArrayRef
(
SVI
)
;
IRBuilder
<
>
Builder
(
SI
)
;
X86InterleavedAccessGroup
Grp
(
SI
,
Shuffles
,
Indices
,
Factor
,
Subtarget
,
Builder
)
;
return
Grp
.
isSupported
(
)
&&
Grp
.
lowerIntoOptimizedSequence
(
)
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> static void find_constant ( rtx in_rtx , imm_info * imm_values ) { if ( INSN_P ( in_rtx ) ) in_rtx = PATTERN ( in_rtx ) ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , in_rtx , ALL ) if ( const_rtx x = * iter ) switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case CONST_INT : ( imm_values -> imm ) ++ ; if ( x86_64_immediate_operand ( CONST_CAST_RTX ( x ) , SImode ) ) ( imm_values -> imm32 ) ++ ; else ( imm_values -> imm64 ) ++ ; break ; case CONST_DOUBLE : case CONST_WIDE_INT : ( imm_values -> imm ) ++ ; ( imm_values -> imm64 ) ++ ; break ; case CODE_LABEL : if ( LABEL_KIND ( x ) == LABEL_NORMAL ) { ( imm_values -> imm ) ++ ; ( imm_values -> imm32 ) ++ ; } break ; default : break ; } } </s>

Compute number of immediate operands of an instruction .


<s> void CJGInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << StringRef ( getRegisterName ( RegNo ) ) ; } </s>


<s> bool LC2200AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static unsigned getReturnSaveOffset ( bool LP64 , bool isMacho ) { if ( isMacho ) return LP64 ? 16 : 8 ; return 4 ; } </s>

getReturnSaveOffset - Return the previous frame offset to save the return address .


<s> static void loongarch_option_override ( void ) { loongarch_option_override_internal ( & global_options ) ; } </s>


<s> int SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } else { FrameReg = SP :: O6 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } } </s>

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


<s> bool mips_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( ! mips_mode_ok_for_mov_fmt_p ( mode1 ) && ! mips_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ; } </s>


<s> static int pad_groups ( FILE * dump , int sched_verbose , rtx_insn * prev_head_insn , rtx_insn * tail ) { rtx_insn * insn , * next_insn ; rtx nop ; int issue_rate ; int can_issue_more ; int group_end ; int group_count = 0 ; issue_rate = rs6000_issue_rate ( ) ; can_issue_more = issue_rate ; insn = get_next_active_insn ( prev_head_insn , tail ) ; next_insn = get_next_active_insn ( insn , tail ) ; while ( insn != NULL_RTX ) { can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; group_end = ( next_insn == NULL_RTX || GET_MODE ( next_insn ) == TImode ) ; if ( next_insn == NULL_RTX ) break ; if ( group_end ) { if ( can_issue_more && ( rs6000_sched_insert_nops == sched_finish_pad_groups ) && ! insn_terminates_group_p ( insn , current_group ) && ! insn_terminates_group_p ( next_insn , previous_group ) ) { if ( ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; while ( can_issue_more ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } } can_issue_more = issue_rate ; group_count ++ ; } insn = next_insn ; next_insn = get_next_active_insn ( insn , tail ) ; } return group_count ; } </s>

Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the dispatch group boundaries that the scheduler had marked . Pad with nops any dispatch groups which have vacant issue slots , in order to force the scheduler 's grouping on the processor dispatcher . The function returns the number of dispatch groups found .


<s> bool X86InstrInfo :: isDataInvariant ( MachineInstr & MI ) { if ( MI . mayLoad ( ) || MI . mayStore ( ) ) return false ; if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) ) return true ; unsigned Opcode = MI . getOpcode ( ) ; using namespace X86 ; if ( isIMUL ( Opcode ) ) return true ; if ( isBSF ( Opcode ) || isBSR ( Opcode ) || isLZCNT ( Opcode ) || isPOPCNT ( Opcode ) || isTZCNT ( Opcode ) ) return true ; if ( isBLCFILL ( Opcode ) || isBLCI ( Opcode ) || isBLCIC ( Opcode ) || isBLCMSK ( Opcode ) || isBLCS ( Opcode ) || isBLSFILL ( Opcode ) || isBLSI ( Opcode ) || isBLSIC ( Opcode ) || isBLSMSK ( Opcode ) || isBLSR ( Opcode ) || isTZMSK ( Opcode ) ) return true ; if ( isBEXTR ( Opcode ) || isBZHI ( Opcode ) ) return true ; if ( isROL ( Opcode ) || isROR ( Opcode ) || isSAR ( Opcode ) || isSHL ( Opcode ) || isSHR ( Opcode ) || isSHLD ( Opcode ) || isSHRD ( Opcode ) ) return true ; if ( isADC ( Opcode ) || isADD ( Opcode ) || isAND ( Opcode ) || isOR ( Opcode ) || isSBB ( Opcode ) || isSUB ( Opcode ) || isXOR ( Opcode ) ) return true ; if ( isADCX ( Opcode ) || isADOX ( Opcode ) || isANDN ( Opcode ) ) return true ; if ( isDEC ( Opcode ) || isINC ( Opcode ) || isNEG ( Opcode ) ) return true ; if ( isNOT ( Opcode ) ) return true ; if ( isMOVSX ( Opcode ) || isMOVZX ( Opcode ) || isMOVSXD ( Opcode ) || isMOV ( Opcode ) ) return true ; if ( isRORX ( Opcode ) || isSARX ( Opcode ) || isSHLX ( Opcode ) || isSHRX ( Opcode ) ) return true ; if ( isLEA ( Opcode ) ) return true ; return false ; } </s>

Returns true if the instruction has no behavior ( specified or otherwise ) that is based on the value of any of its register operands .


<s> bool SystemZMCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = 0 ; I != Count ; ++ I ) OW -> Write8 ( 7 ) ; return true ; } </s>


<s> pru_byterange pru_calc_byterange ( HOST_WIDE_INT cval , machine_mode mode ) { const pru_byterange invalid_range = { - 1 , - 1 } ; pru_byterange r = invalid_range ; enum { ST_FFS , ST_INRANGE , ST_TRAILING_ZEROS } st = ST_FFS ; int i ; for ( i = 0 ; i < GET_MODE_SIZE ( mode ) ; i ++ ) { const int b = cval & ( ( 1U << BITS_PER_UNIT ) - 1 ) ; cval >>= BITS_PER_UNIT ; if ( b == 0x00 && ( st == ST_FFS || st == ST_TRAILING_ZEROS ) ) ; else if ( b == 0x00 && st == ST_INRANGE ) st = ST_TRAILING_ZEROS ; else if ( b == 0xff && st == ST_FFS ) { st = ST_INRANGE ; r . start = i ; r . nbytes = 1 ; } else if ( b == 0xff && st == ST_INRANGE ) r . nbytes ++ ; else return invalid_range ; } if ( st != ST_TRAILING_ZEROS && st != ST_INRANGE ) return invalid_range ; return r ; } </s>

Parse the given CVAL integer value , and extract the `` filling '' byte range of consecutive 0xff byte values . Rest of bytes must be 0x00 . There must be only one range in the given value . This range would typically be used to calculate the parameters of PRU instructions ZERO and FILL . The parameter MODE determines the maximum byte range to consider in the given input constant . Example input : cval = 0xffffffffffffff00 = -256 mode = SImode Return value : start = 1 nbytes = 3 On error , return a range with -1 for START and NBYTES .


<s>
bool
SparcAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
O
<<
"\n\n"
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
)
;
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.type\t"
<<
CurrentFnName
<<
", #function\n"
;
O
<<
CurrentFnName
<<
":\n"
;
NumberForBB
.
clear
(
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
NumberForBB
[
I
->
getBasicBlock
(
)
]
=
BBNumber
++
;
}
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printInstruction
(
II
)
;
++
EmittedInsts
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Sparc
Sparc
"\n\n"
"\t.globl\t"
"\t.type\t"
", #function\n"
":\n"


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ Stack Align: May be called with mis-aligned SP.\n"

"\t%@ args = %d, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; const char * SymName = CLI . SymName ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeSupported ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; if ( ! Addr . getGlobalValue ( ) ) return false ; unsigned DestAddress ; if ( SymName ) DestAddress = materializeExternalCallSym ( SymName ) ; else DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 WinAlloca Expander"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static bool sh_function_value_regno_p ( const unsigned int regno ) { return ( ( regno ) == FIRST_RET_REG || ( TARGET_SH2E && ( regno ) == FIRST_FP_RET_REG ) || ( TARGET_SHMEDIA_FPU && ( regno ) == FIRST_FP_RET_REG ) ) ; } </s>

Return true if N is a possible register number of function value .


<s> bool ARMPassConfig :: addInstSelector ( ) { addPass ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && TM -> Options . EnableFastISel ) addPass ( createARMGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> bool LanaiInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * ) const { if ( LdSt . getNumOperands ( ) != 4 ) return false ; if ( ! LdSt . getOperand ( 1 ) . isReg ( ) || ! LdSt . getOperand ( 2 ) . isImm ( ) || ! ( LdSt . getOperand ( 3 ) . isImm ( ) && LdSt . getOperand ( 3 ) . getImm ( ) == LPAC :: ADD ) ) return false ; switch ( LdSt . getOpcode ( ) ) { default : return false ; case Lanai :: LDW_RI : case Lanai :: LDW_RR : case Lanai :: SW_RR : case Lanai :: SW_RI : Width = 4 ; break ; case Lanai :: LDHs_RI : case Lanai :: LDHz_RI : case Lanai :: STH_RI : Width = 2 ; break ; case Lanai :: LDBs_RI : case Lanai :: LDBz_RI : case Lanai :: STB_RI : Width = 1 ; break ; } BaseOp = & LdSt . getOperand ( 1 ) ; Offset = LdSt . getOperand ( 2 ) . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; return true ; } </s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( getARMSubtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( createARMOptimizeBarriersPass ( ) ) ; if ( getARMSubtarget ( ) . useConstIslands ( ) ) addPass ( createARMConstantIslandPass ( ) ) ; if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createARMNaClRewritePass ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static tree rs6000_builtin_reciprocal ( tree fndecl ) { switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case VSX_BUILTIN_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ; case VSX_BUILTIN_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_4SF ] ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> void PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = Subtarget . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( isBranch ( Inst ) || Inst . getOpcode ( ) == LoongArch :: BL ) { Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


"\n========== quad_load_store, return %s\n"

Return true if this is a load or store quad operation . This function does not handle the atomic quad memory instructions .


Hook to validate the current # pragma GCC target and set the arch custom mode state . If ARGS is NULL , then POP_TARGET is used to reset the options .


"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s>
unsigned
SystemZInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
break
;
if
(
!
getBranchInfo
(
*
I
)
.
Target
->
isMBB
(
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

SystemZ
SystemZ
"code size not handled"
0


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & Args = F . getArgumentList ( ) ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : Args ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + 1 , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ i ] , Regs , Offsets ) ; } ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMMOVE ) ; } </s>

Emit target-specific code that performs a memmove .


<s> bool AArch64InstrInfo :: isLdStPairSuppressed ( const MachineInstr & MI ) const { return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOSuppressPair ; } ) ; } </s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return MVT :: v2i64 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return MVT :: f128 ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return MVT :: i64 ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> Optional < MCFixupKind > ARMAsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( ! EnableX86LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { SmallVector < MachineInstr * , 16 > LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; if ( MF . getFunction ( ) -> optForMinSize ( ) ) Changed |= removeRedundantLEAs ( LEAs ) ; Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; if ( ! TARGET_64BIT ) return 0 ; if ( pa_function_arg_size ( mode , type ) > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + pa_function_arg_size ( mode , type ) <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .


<s> bool nds32_can_use_bclr_p ( HOST_WIDE_INT ival ) { int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival ) & mask ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bclr ' instruction can be used with IVAL .


<s> static inline tree rs6000_builtin_type ( int id ) { tree t ; t = rs6000_builtin_types [ id < 0 ? ~ id : id ] ; return id < 0 ? build_pointer_type ( t ) : t ; } </s>

Convert a type stored into a struct altivec_builtin_types as ID , into a tree . The types are in rs6000_builtin_types : negative values create a pointer type for the type associated to ~ID . Note it is a logical NOT , rather than a negation , otherwise you can not represent a pointer type for ID 0 .


<s> bool sh_lshrsi_clobbers_t_reg_p ( rtx shift_amount ) { gcc_assert ( CONST_INT_P ( shift_amount ) ) ; const int shift_amount_i = std :: abs ( INTVAL ( shift_amount ) ) & 31 ; if ( shift_amount_i == 31 ) return true ; return ( ashl_lshr_seq [ shift_amount_i ] . clobbers_t & LSHR_CLOBBERS_T ) != 0 ; } </s>

Return true if a logical right shift consisting of 1/2/8/16 shift instructions will clobber the T bit .