<s> void d30v_expand_epilogue ( ) { rtx sp = stack_pointer_rtx ; d30v_stack_t * info = d30v_stack_info ( ) ; int i ; rtx mem_di = NULL_RTX ; rtx mem_si = NULL_RTX ; rtx post_inc ; int extra_stack ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) emit_move_insn ( sp , frame_pointer_rtx ) ; if ( info -> save_offset ) emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( info -> save_offset ) ) ) ; post_inc = gen_rtx ( POST_INC , Pmode , sp ) ; mem_di = gen_rtx ( MEM , DImode , post_inc ) ; mem_si = gen_rtx ( MEM , SImode , post_inc ) ; for ( i = ACCUM_FIRST ; i <= ACCUM_LAST ; i ++ ) if ( info -> save_p [ i ] ) { rtx acc_tmp = gen_rtx ( REG , DImode , GPR_ATMP_FIRST ) ; emit_insn ( gen_movdi ( acc_tmp , mem_di ) ) ; emit_insn ( gen_movdi ( gen_rtx ( REG , DImode , i ) , acc_tmp ) ) ; } for ( i = GPR_FIRST ; i <= GPR_LAST ; i += 2 ) if ( info -> save_p [ i ] == 2 ) emit_insn ( gen_movdi ( gen_rtx ( REG , DImode , i ) , mem_di ) ) ; extra_stack = 0 ; for ( i = GPR_FIRST ; i <= GPR_LAST ; i ++ ) if ( info -> save_p [ i ] == 1 ) { if ( cfun -> machine -> eh_epilogue_sp_ofs && i == GPR_LINK ) extra_stack = 4 ; else { if ( extra_stack ) { emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( extra_stack ) ) ) ; extra_stack = 0 ; } emit_insn ( gen_movsi ( gen_rtx ( REG , SImode , i ) , mem_si ) ) ; } } if ( ( info -> memrefs_1word & 1 ) != 0 ) extra_stack += UNITS_PER_WORD ; extra_stack += current_function_pretend_args_size + info -> varargs_size ; if ( extra_stack ) { if ( cfun -> machine -> eh_epilogue_sp_ofs ) emit_insn ( gen_addsi3 ( cfun -> machine -> eh_epilogue_sp_ofs , cfun -> machine -> eh_epilogue_sp_ofs , GEN_INT ( extra_stack ) ) ) ; else emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( extra_stack ) ) ) ; } if ( cfun -> machine -> eh_epilogue_sp_ofs ) emit_insn ( gen_addsi3 ( sp , sp , cfun -> machine -> eh_epilogue_sp_ofs ) ) ; emit_jump_insn ( gen_rtx_RETURN ( VOIDmode ) ) ; } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in output_function_prologue ( ) , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> int VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static bool mips_cfun_has_inflexible_gp_ref_p ( void ) { if ( crtl -> has_nonlocal_goto ) return true ; if ( TARGET_ABICALLS_PIC2 ) { if ( ! TARGET_EXPLICIT_RELOCS ) return true ; if ( crtl -> profile ) return true ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return true ; } return mips_find_gp_ref ( & cfun -> machine -> has_inflexible_gp_insn_p , mips_insn_has_inflexible_gp_ref_p ) ; } </s>

Return true if the current function refers to the global pointer in a way that forces $ 28 to be valid . This means that we ca n't change the choice of global pointer , even for NewABI code . One example of this ( and one which needs several checks ) is that $ 28 must be valid when calling traditional MIPS lazy-binding stubs . ( This restriction does not apply to PLTs . )


<s> const SystemZSubtarget * SystemZTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SystemZSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

SystemZ SystemZ SystemZ "target-cpu" "target-features" "use-soft-float" "+soft-float" ",+soft-float" SystemZ


<s> static bool mips_rewrite_small_data_p ( rtx x ) { enum mips_symbol_type symbol_type ; return ( TARGET_EXPLICIT_RELOCS && mips_symbolic_constant_p ( x , & symbol_type ) && symbol_type == SYMBOL_SMALL_DATA ) ; } </s>

Return true if X is a small data address that can be rewritten as a LO_SUM .


"Must not have more than 6553 virtual functions!"

"Warning: Did not recognize vcall instruction, but I need to make sure it has room!\n"

runOnMachineFunction - Emit the function body .


<s> bool easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return false ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ; else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , 0 ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , 1 ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) == - 1 && INTVAL ( CONST_VECTOR_ELT ( op , 1 ) ) == - 1 ) return true ; return false ; } else if ( mode == V1TImode ) return false ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( vspltis_shifted ( op ) != 0 ) return true ; return false ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || isTargetAndroid ( ) ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( Subtarget . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( PPC :: X2 ) ; else Reserved . reset ( PPC :: R2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BR_JT : return lowerBR_JT ( Op , DAG ) ; case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return lowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: VAARG : return lowerVAARG ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: ADD : return lowerADD ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BR_JT ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::VAARG ISD::FCOPYSIGN ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::ADD ISD::FP_TO_SINT


<s> bool X86TargetLowering :: isIntDivCheap ( EVT VT , AttributeSet Attr ) const { bool OptSize = Attr . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> void expand_fusion_gpr_load ( rtx * operands ) { rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == ZERO_EXTEND || ( TARGET_P8_FUSION_SIGN && GET_CODE ( orig_mem ) == SIGN_EXTEND ) ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( ZERO_EXTEND , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_GPR ) ; emit_insn ( gen_rtx_SET ( target , new_mem ) ) ; if ( extend == SIGN_EXTEND ) { int sub_off = ( ( BYTES_BIG_ENDIAN ) ? GET_MODE_SIZE ( extend_mode ) - GET_MODE_SIZE ( target_mode ) : 0 ) ; rtx sign_reg = simplify_subreg ( target_mode , target , extend_mode , sub_off ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_SIGN_EXTEND ( extend_mode , sign_reg ) ) ) ; } return ; } </s>

During the peephole2 pass , adjust and expand the insns for a load fusion sequence . We adjust the addis register to use the target register . If the load sign extends , we adjust the code to do the zero extending load , and an explicit sign extension later since the fusion only covers zero extending loads . The operands are : operands [ 0 ] register set with addis ( to be replaced with target ) operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] .


<s> void ARMWinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; emitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


<s> static rtx aarch64_simd_make_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; rtx const_dup ; rtx const_vec = NULL_RTX ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_const = 0 ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL_RTX && aarch64_simd_valid_immediate ( const_vec , mode , false , NULL ) ) return const_vec ; else if ( ( const_dup = aarch64_simd_dup_constant ( vals ) ) != NULL_RTX ) return const_dup ; else if ( const_vec != NULL_RTX ) return const_vec ; else return NULL_RTX ; } </s>

Generate code to load VALS , which is a PARALLEL containing only constants ( for vec_init ) or CONST_VECTOR , efficiently into a register . Returns an RTX to copy into the register , or NULL_RTX for a PARALLEL that can not be converted into a CONST_VECTOR .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . getScalarType ( ) == MVT :: i1 ) return false ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) == 64 ) return false ; return isTypeLegal ( VT . getSimpleVT ( ) ) ; } </s>


<s> ISD :: NodeType getExtendForAtomicCmpSwapArg ( ) const override { return ISD :: ZERO_EXTEND ; } </s>

Returns how the platform 's atomic compare and swap expects its comparison value to be extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , unsigned RegIndex , Register Addr , uint64_t MemSize , MachinePointerInfo & MPO , CCValAssign & VA ) override { unsigned MaxSize = MemSize * 8 ; if ( ! Arg . IsFixed ) MaxSize = 0 ; Register ValVReg = Arg . Regs [ RegIndex ] ; if ( VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ) { MVT LocVT = VA . getLocVT ( ) ; MVT ValVT = VA . getValVT ( ) ; if ( VA . getValVT ( ) == MVT :: i8 || VA . getValVT ( ) == MVT :: i16 ) { std :: swap ( ValVT , LocVT ) ; MemSize = VA . getValVT ( ) . getStoreSize ( ) ; } ValVReg = extendRegister ( ValVReg , VA , MaxSize ) ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBits ( ) < LocVT . getSizeInBits ( ) ) ValVReg = MIRBuilder . buildTrunc ( RegTy , ValVReg ) . getReg ( 0 ) ; } else { MemSize = VA . getValVT ( ) . getStoreSize ( ) ; } assignValueToAddress ( ValVReg , Addr , MemSize , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Token
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
k_Register
:
OS
<<
"Reg: #"
<<
getReg
(
)
<<
"\n"
;
break
;
case
k_Immediate
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
k_MemoryRegRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+#"
<<
getMemIndexReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryRegImmImm
:
assert
(
getMemIndex
(
)
!=
nullptr
&&
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+"
<<
*
getMemIndex
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+#"
<<
getMemIndexReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroImmImm
:
assert
(
getMemIndex
(
)
!=
nullptr
&&
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+"
<<
*
getMemIndex
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_CCOp
:
OS
<<
"CCOp: "
<<
getCCVal
(
)
<<
"\n"
;
break
;
case
k_RDOp
:
OS
<<
"RDOp: "
<<
getRDVal
(
)
<<
"\n"
;
break
;
case
k_MImmOp
:
OS
<<
"MImm: ("
<<
getMImmVal
(
)
<<
(
getM0Flag
(
)
")0"
:
")1"
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> const AArch64MCExpr * AArch64MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) AArch64MCExpr ( Expr , Kind ) ; } </s>


<s> bool AArch64RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == AArch64 :: WZR || PhysReg == AArch64 :: XZR ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> int pa_function_arg_size ( machine_mode mode , const_tree type ) { HOST_WIDE_INT size ; size = mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ; if ( size >= ( 1 << ( HOST_BITS_PER_INT - 2 ) ) ) size = 0 ; return ( int ) CEIL ( size , UNITS_PER_WORD ) ; } </s>

Figure out the size in words of the function argument .


<s> void sparc_emit_fixunsdi ( rtx * operands , machine_mode mode ) { rtx i0 , i1 , f0 , in , out , limit ; out = operands [ 0 ] ; in = force_reg ( mode , operands [ 1 ] ) ; rtx_code_label * neglab = gen_label_rtx ( ) ; rtx_code_label * donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , const_double_from_real_value ( REAL_VALUE_ATOF ( "9223372036854775808.0" , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( out , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , in ) ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_rtx_SET ( f0 , gen_rtx_MINUS ( mode , in , limit ) ) ) ; emit_insn ( gen_rtx_SET ( i0 , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , f0 ) ) ) ) ; emit_insn ( gen_movdi ( i1 , const1_rtx ) ) ; emit_insn ( gen_ashldi3 ( i1 , i1 , GEN_INT ( 63 ) ) ) ; emit_insn ( gen_xordi3 ( out , i0 , i1 ) ) ; emit_label ( donelab ) ; } </s>

Generate an FP to unsigned DImode conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> SDValue X86TargetLowering :: getSqrtEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) && Reciprocal ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE2 ( ) && ! Reciprocal ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; UseOneConstNR = false ; return DAG . getNode ( X86ISD :: FRSQRT , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! Subtarget . allowsUnalignedFPAccess ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static void ix86_option_override ( void ) { opt_pass * pass_insert_vzeroupper = make_pass_insert_vzeroupper ( g ) ; struct register_pass_info insert_vzeroupper_info = { pass_insert_vzeroupper , "reload" , 1 , PASS_POS_INSERT_AFTER } ; opt_pass * pass_stv = make_pass_stv ( g ) ; struct register_pass_info stv_info = { pass_stv , "combine" , 1 , PASS_POS_INSERT_AFTER } ; ix86_option_override_internal ( true , & global_options , & global_options_set ) ; register_pass ( & insert_vzeroupper_info ) ; register_pass ( & stv_info ) ; } </s>

Implement the TARGET_OPTION_OVERRIDE hook .


<s> InstructionCost ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: GetElementPtr && Idx != 0 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnes ( ) ) return 0 ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= 32 ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return 0 ; } if ( Inst && ST -> hasVFP2Base ( ) && isFPSatMinMaxPattern ( Inst , Imm ) ) return 0 ; if ( Inst && Opcode == Instruction :: ICmp && Idx == 1 && Imm . isAllOnesValue ( ) ) { ICmpInst :: Predicate Pred = cast < ICmpInst > ( Inst ) -> getPredicate ( ) ; if ( Pred == ICmpInst :: ICMP_SGT || Pred == ICmpInst :: ICMP_SLE ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( Imm + 1 , Ty , CostKind ) ) ; } return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> inline tree function_instance :: displacement_vector_type ( ) const { return acle_vector_types [ 0 ] [ mode_suffix ( ) . displacement_vector_type ] ; } </s>

Return the type of the function 's vector index or offset argument , or null if does n't have a vector index or offset argument .


<s>
SDValue
LanaiTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
IsVarArg
,
Ins
,
DL
,
DAG
,
InVals
)
;
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

Lanai
Lanai
ISD::InputArg
"Unsupported calling convention"


<s> bool aarch64_sve_dup_immediate_p ( rtx x ) { x = aarch64_bit_representation ( unwrap_const_vec_duplicate ( x ) ) ; if ( ! CONST_INT_P ( x ) ) return false ; HOST_WIDE_INT val = INTVAL ( x ) ; if ( val & 0xff ) return IN_RANGE ( val , - 0x80 , 0x7f ) ; return IN_RANGE ( val , - 0x8000 , 0x7f00 ) ; } </s>

Return true if X is a valid immediate for the SVE DUP and CPY instructions .


<s> void ia64_asm_output_external ( FILE * file , tree decl , const char * name ) { if ( TREE_SYMBOL_REFERENCED ( DECL_ASSEMBLER_NAME ( decl ) ) ) { int need_visibility = ( ( * targetm . binds_local_p ) ( decl ) && maybe_assemble_visibility ( decl ) ) ; if ( ( TARGET_HPUX_LD || ! TARGET_GNU_AS ) && TREE_CODE ( decl ) == FUNCTION_DECL ) ( * targetm . asm_out . globalize_decl_name ) ( file , decl ) ; else if ( need_visibility && ! TARGET_GNU_AS ) ( * targetm . asm_out . globalize_label ) ( file , name ) ; } } </s>

Emit text to declare externally defined variables and functions , because the Intel assembler does not support undefined externals .


<s> static machine_mode aarch64_c_mode_for_suffix ( char suffix ) { if ( suffix == 'q' ) return TFmode ; return VOIDmode ; } </s>


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , MaybeAlign Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( isa < VectorType > ( DataTy ) ) { unsigned NumElts = DataTy -> getVectorNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


"Altivec is not implemented on AIX yet."

Return a mask of call-preserved registers for the given calling convention on the current function .


Relax the instruction in the given fragment to the next wider instruction .


<s> TargetPassConfig * DLXTargetMachine :: createPassConfig ( PassManagerBase & PassManager ) { return new DLXPassConfig ( * this , & PassManager ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , I . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> virtual bool isBranchWithImm ( unsigned Opc ) const { return false ; } </s>

isBranchWithImm - Return true if the branch contains an immediate operand (


<s>
unsigned
getReg
(
)
const
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> bool X86TTI :: isLegalMaskedLoad ( Type * DataTy , int Consecutive ) const { int DataWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( ( DataWidth < 32 ) || ( Consecutive == 0 ) ) return false ; if ( ST -> hasAVX512 ( ) || ST -> hasAVX2 ( ) ) return true ; return false ; } </s>

Return true if the target supports masked load .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; if ( ! EnableBasePointer ) return false ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> static bool is_nonpipeline_insn ( rtx_insn * insn ) { enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; type = get_attr_type ( insn ) ; if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT || type == TYPE_DSQRT || type == TYPE_MFCR || type == TYPE_MFCRF || type == TYPE_MFJMPR ) { return true ; } return false ; } </s>

Return true if the instruction is nonpipelined on the Cell .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
InstructionCost
AArch64TTIImpl
::
getGatherScatterOpCost
(
unsigned
Opcode
,
Type
*
DataTy
,
const
Value
*
Ptr
,
bool
VariableMask
,
Align
Alignment
,
TTI
::
TargetCostKind
CostKind
,
const
Instruction
*
I
)
{
if
(
!
isa
<
ScalableVectorType
>
(
DataTy
)
)
return
BaseT
::
getGatherScatterOpCost
(
Opcode
,
DataTy
,
Ptr
,
VariableMask
,
Alignment
,
CostKind
,
I
)
;
auto
*
VT
=
cast
<
VectorType
>
(
DataTy
)
;
auto
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
DataTy
)
;
ElementCount
LegalVF
=
LT
.
second
.
getVectorElementCount
(
)
;
Optional
<
unsigned
>
MaxNumVScale
=
getMaxVScale
(
)
;
assert
(
MaxNumVScale
&&
"Expected valid max vscale value"
)
;
InstructionCost
MemOpCost
=
getMemoryOpCost
(
Opcode
,
VT
->
getElementType
(
)
,
Alignment
,
0
,
CostKind
,
I
)
;
unsigned
MaxNumElementsPerGather
=
MaxNumVScale
.
getValue
(
)
*
LegalVF
.
getKnownMinValue
(
)
;
return
LT
.
first
*
MaxNumElementsPerGather
*
MemOpCost
;
}
</s>

Calculate the cost of Gather / Scatter operation .


<s> void mmix_init_expanders ( ) { init_machine_status = mmix_init_machine_status ; } </s>


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( TARGET_HAVE_MVE && VALID_MVE_PRED_MODE ( mode ) ) mode = HImode ; if ( TARGET_HAVE_MVE && VALID_MVE_MODE ( mode ) ) return mve_vector_mem_operand ( mode , x , strict_p ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) || ( TARGET_HAVE_MVE && VALID_MVE_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_cpu_attr ) { case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return 2 ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return 5 ; case CPU_POWER8 : return 7 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( const Type * Ty ) const { if ( Subtarget -> is64Bit ( ) ) { unsigned TyAlign = TD -> getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget -> hasSSE1 ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s>
X86TTI
::
PopcntSupportKind
X86TTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
ST
->
hasSSE41
(
)
PSK_FastHardware
:
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> static void compute_save_world_info ( rs6000_stack_t * info ) { info -> world_save_p = 1 ; info -> world_save_p = ( WORLD_SAVE_P ( info ) && DEFAULT_ABI == ABI_DARWIN && ! cfun -> has_nonlocal_label && info -> first_fp_reg_save == FIRST_SAVED_FP_REGNO && info -> first_gp_reg_save == FIRST_SAVED_GP_REGNO && info -> first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info -> cr_save_p ) ; if ( WORLD_SAVE_P ( info ) ) { rtx_insn * insn ; for ( insn = get_last_insn_anywhere ( ) ; insn ; insn = PREV_INSN ( insn ) ) if ( CALL_P ( insn ) && SIBLING_CALL_P ( insn ) ) { info -> world_save_p = 0 ; break ; } } if ( WORLD_SAVE_P ( info ) ) { info -> vrsave_size = 4 ; info -> lr_save_p = 1 ; if ( info -> vrsave_mask == 0 ) info -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info -> first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ; } return ; } </s>

For a very restricted set of circumstances , we can cut down the size of prologues/epilogues by calling our own save/restore-the-world routines .


<s> bool ix86_function_arg_regno_p ( int regno ) { int i ; if ( ! TARGET_64BIT ) return ( regno < REGPARM_MAX || ( TARGET_MMX && MMX_REGNO_P ( regno ) && ( regno < FIRST_MMX_REG + MMX_REGPARM_MAX ) ) || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) ) ; if ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) return true ; if ( ! regno ) return true ; for ( i = 0 ; i < REGPARM_MAX ; i ++ ) if ( regno == x86_64_int_parameter_registers [ i ] ) return true ; return false ; } </s>

Return true when register may be used to pass function parameters .


<s> static double calc_defect ( double x , int constant , int factor ) { double y0 = ( constant - ( int ) floor ( ( x * factor * 64. ) ) ) / 16384. ; double y1 = 2 * y0 - y0 * y0 * ( x + BIAS / ( 1. * ( 1LL << 30 ) ) ) ; double y2d0 , y2d ; int y2d1 ; double d , d2 ; y1 = floor ( y1 * ( 1024 * 1024 * 1024 ) ) / ( 1024 * 1024 * 1024 ) ; d = y1 - 1 / x ; if ( d > max_defect ) { max_defect = d ; max_defect_x = x ; } if ( d < min_defect ) { min_defect = d ; min_defect_x = x ; } y2d0 = floor ( y1 * x * ( 1LL << 60 - 16 ) ) ; y2d1 = ( int ) ( long long ) y2d0 ; y2d = - floor ( ( y1 - y0 / ( 1 << 30 - 14 ) ) * y2d1 ) / ( 1LL << 44 ) ; d2 = y1 + y2d - 1 / x ; if ( d2 > max_defect2 ) { max_defect2 = d2 ; max_defect2_x = x ; } if ( d2 < min_defect2 ) { min_defect2 = d2 ; min_defect2_x = x ; } note_defect3 ( ( 1 << CUTOFF_BITS ) - 1 , d2 , y2d , x ) ; note_defect3 ( 1 << CUTOFF_BITS , d2 , y2d , x ) ; note_defect3 ( ( 1U << 31 ) - ( 1 << CUTOFF_BITS ) , d2 , y2d , x ) ; note_defect3 ( ( 1U << 31 ) - 1 , d2 , y2d , x ) ; note_defect3 ( - 1 , d2 , y2d , x ) ; note_defect3 ( - ( 1 << CUTOFF_BITS ) , d2 , y2d , x ) ; note_defect3 ( ( 1U << 31 ) - ( 1 << CUTOFF_BITS ) + 1 , d2 , y2d , x ) ; note_defect3 ( - ( 1U << 31 ) , d2 , y2d , x ) ; return d ; } </s>


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { EnableVPU = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = "ve" ; ParseSubtargetFeatures ( CPUName , CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"MMIX Internal: This is not a recognized address"


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> static std :: unique_ptr < MipsOperand > CreateReg ( unsigned Index , StringRef Str , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = std :: make_unique < MipsOperand > ( k_RegisterIndex , Parser ) ; Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> RegIdx . Tok . Data = Str . data ( ) ; Op -> RegIdx . Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> struct machine_function * rs6000_init_machine_status ( void ) { stack_info . reload_completed = 0 ; return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Functions to init , mark and free struct machine_function . These will be called , via pointer variables , from push_function_context and pop_function_context .


<s> unsigned CJGRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return CJG :: SP ; } </s>


<s> bool X86TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasFnAttribute ( Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; Register FIReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildFrameIndex ( FIReg , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg ; } Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( AArch64 :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> int sh2a_get_function_vector_number ( rtx x ) { if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { tree t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return 0 ; for ( tree list = SH_ATTRIBUTES ( t ) ; list ; list = TREE_CHAIN ( list ) ) if ( is_attribute_p ( "function_vector" , TREE_PURPOSE ( list ) ) ) return TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( list ) ) ) ; return 0 ; } else return 0 ; } </s>

Returns the function vector number , if the attribute 'function_vector ' is assigned , otherwise returns zero .


<s> unsigned X86TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RAX : X86 :: EAX ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] [ 0 ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static rtx frame_insn ( rtx x ) { x = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

Emit the specified insn and mark it as frame related . FIXME : Rename this to emit_frame_insn .


<s>
bool
X86RegisterAllocator
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
outs
(
)
<<
"\n"
<<
"=====================\n"
<<
MF
.
getName
(
)
<<
"()\n====================="
<<
"\n"
;
MachineRegisterInfo
&
regInfo
=
MF
.
getRegInfo
(
)
;
for
(
auto
&
MBB
:
MF
)
{
reloop
:
for
(
auto
&
MI
:
MBB
)
{
const
TargetInstrInfo
*
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
auto
mi
=
&
MI
;
if
(
mi
->
isInsertSubreg
(
)
)
{
unsigned
SubIdx
=
mi
->
getOperand
(
3
)
.
getImm
(
)
;
mi
->
RemoveOperand
(
3
)
;
assert
(
mi
->
getOperand
(
0
)
.
getSubReg
(
)
==
0
&&
"Unexpected subreg idx"
)
;
mi
->
getOperand
(
0
)
.
setSubReg
(
SubIdx
)
;
mi
->
getOperand
(
0
)
.
setIsUndef
(
mi
->
getOperand
(
1
)
.
isUndef
(
)
)
;
mi
->
RemoveOperand
(
1
)
;
mi
->
setDesc
(
TII
->
get
(
TargetOpcode
::
COPY
)
)
;
(
getIterForMI
(
MI
)
)
->
eraseFromParent
(
)
;
goto
reloop
;
}
}
outs
(
)
<<
"Contents of MachineBasicBlock:\n"
;
outs
(
)
<<
MBB
<<
"\n"
;
outs
(
)
.
flush
(
)
;
}
spilledRegisters
.
clear
(
)
;
BEGINNING
:
for
(
LiveRange
*
LR
:
interferenceGraph
)
{
delete
LR
;
}
interferenceGraph
.
clear
(
)
;
interferenceGraphRetrieval
.
clear
(
)
;
livenessInformation
.
clear
(
)
;
phiNodes
.
clear
(
)
;
calcGlobalLivenessInfo
(
MF
,
regInfo
)
;
if
(
interferenceGraph
.
size
(
)
>
0
&&
color
(
MF
,
regInfo
)
==
EXIT_STATUS_T
::
SPILLED
)
{
goto
BEGINNING
;
}
for
(
MachineInstr
*
MI
:
getPhiNodes
(
)
)
{
MI
->
eraseFromParent
(
)
;
}
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
NoPHIs
)
;
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
NoVRegs
)
;
outs
(
)
<<
"\n\n"
;
for
(
auto
&
MBB
:
MF
)
{
outs
(
)
<<
"Contents of MachineBasicBlock:\n"
;
outs
(
)
<<
MBB
<<
"\n"
;
outs
(
)
.
flush
(
)
;
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> enum aarch64_symbol_type aarch64_classify_symbolic_expression ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , offset ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .


"Tiny codesize model not supported on X86"

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
bool
PPCCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
Register
SwiftErrorVReg
)
const
{
assert
(
(
(
Val
&&
!
VRegs
.
empty
(
)
)
||
(
!
Val
&&
VRegs
.
empty
(
)
)
)
&&
"Return value without a vreg"
)
;
if
(
VRegs
.
size
(
)
>
0
)
return
false
;
MIRBuilder
.
buildInstr
(
PPC
::
BLR8
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> Align PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > 1 && ML -> getSubLoops ( ) . empty ( ) ) return Align ( 32 ) ; } const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return Align ( 32 ) ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> void X86CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const X86TargetLowering & TLI = * getTLI < X86TargetLowering > ( ) ; LLVMContext & Context = OrigArg . Ty -> getContext ( ) ; EVT VT = TLI . getValueType ( DL , OrigArg . Ty ) ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == 1 ) { SplitArgs . push_back ( OrigArg ) ; return ; } SmallVector < uint64_t , 4 > BitOffsets ; SmallVector < unsigned , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( LLT { * PartTy , DL } ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; BitOffsets . push_back ( PartVT . getSizeInBits ( ) * i ) ; SplitRegs . push_back ( Info . Reg ) ; } PerformArgSplit ( SplitRegs , BitOffsets ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP , Mips :: RA } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 , Mips :: RA_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegClass . begin ( ) , EReg = Mips :: CPU64RegsRegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const ARMRegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool timode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = pseudo_reg_set ( insn ) ; if ( ! def_set ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn , TImode ) ; if ( GET_MODE ( dst ) != TImode || ( GET_MODE ( src ) != TImode && ! CONST_SCALAR_INT_P ( src ) ) ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; if ( MEM_P ( dst ) && misaligned_operand ( dst , TImode ) && ! TARGET_SSE_UNALIGNED_STORE_OPTIMAL ) return false ; if ( REG_P ( dst ) && ! single_def_chain_p ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case REG : return single_def_chain_p ( src ) ; case CONST_WIDE_INT : return true ; case CONST_INT : return standard_sse_constant_p ( src , TImode ) ; case MEM : return ( REG_P ( dst ) && ( ! misaligned_operand ( src , TImode ) || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL ) ) ; case AND : if ( ! MEM_P ( dst ) && GET_CODE ( XEXP ( src , 0 ) ) == NOT && REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) && ( REG_P ( XEXP ( src , 1 ) ) || CONST_SCALAR_INT_P ( XEXP ( src , 1 ) ) || timode_mem_p ( XEXP ( src , 1 ) ) ) ) return true ; return REG_P ( XEXP ( src , 0 ) ) && ( REG_P ( XEXP ( src , 1 ) ) || CONST_SCALAR_INT_P ( XEXP ( src , 1 ) ) || timode_mem_p ( XEXP ( src , 1 ) ) ) ; case IOR : case XOR : return REG_P ( XEXP ( src , 0 ) ) && ( REG_P ( XEXP ( src , 1 ) ) || CONST_SCALAR_INT_P ( XEXP ( src , 1 ) ) || timode_mem_p ( XEXP ( src , 1 ) ) ) ; case NOT : return REG_P ( XEXP ( src , 0 ) ) || timode_mem_p ( XEXP ( src , 0 ) ) ; case ASHIFT : case LSHIFTRT : case ASHIFTRT : case ROTATERT : case ROTATE : return REG_P ( XEXP ( src , 0 ) ) && CONST_INT_P ( XEXP ( src , 1 ) ) && ( INTVAL ( XEXP ( src , 1 ) ) & ~ 0x7f ) == 0 ; default : return false ; } } </s>

The TImode version of scalar_to_vector_candidate_p .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; ConstPoolId2AddrMap . resize ( AFI -> getNumPICLabels ( ) ) ; JumpTableId2AddrMap . resize ( AFI -> getNumJumpTables ( ) ) ; IsPIC = isPIC ; } </s>

This method must be called before any actual lowering is done .


<s> static bool rs6000_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > 4 && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 && ! FLOAT128_2REG_P ( mode ) ) return true ; return false ; } </s>


<s> int vfp3_const_double_for_bits ( rtx operand ) { REAL_VALUE_TYPE r0 ; if ( ! CONST_DOUBLE_P ( operand ) ) return 0 ; REAL_VALUE_FROM_CONST_DOUBLE ( r0 , operand ) ; if ( exact_real_truncate ( DFmode , & r0 ) ) { HOST_WIDE_INT value = real_to_integer ( & r0 ) ; value = value & 0xffffffff ; if ( ( value != 0 ) && ( ( value & ( value - 1 ) ) == 0 ) ) return int_log2 ( value ) ; } return 0 ; } </s>

If X is a CONST_DOUBLE with a value that is a power of 2 whose log2 is in [ 1 , 32 ] , return that log2 . Otherwise return -1 . This is used in the patterns for vcvt.s32.f32 floating-point to fixed-point conversions .


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : if ( OpSize == 32 ) { switch ( GenericOpc ) { case TargetOpcode :: G_SHL : return AArch64 :: LSLVWr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVWr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVWr ; default : return GenericOpc ; } } else if ( OpSize == 64 ) { switch ( GenericOpc ) { case TargetOpcode :: G_GEP : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SHL : return AArch64 :: LSLVXr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVXr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVXr ; default : return GenericOpc ; } } case AArch64 :: FPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDSrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBSrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULSrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVSrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDDrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBDrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULDrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVDrr ; case TargetOpcode :: G_OR : return AArch64 :: ORRv8i8 ; default : return GenericOpc ; } } } ; return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s>
void
PPCAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
MCInst
TmpInst
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
DBG_VALUE
:
{
if
(
!
isVerbose
(
)
||
!
OutStreamer
.
hasRawTextSupport
(
)
)
return
;
SmallString
<
32
>
Str
;
raw_svector_ostream
O
(
Str
)
;
unsigned
NOps
=
MI
->
getNumOperands
(
)
;
assert
(
NOps
==
4
)
;
O
<<
'\t'
<<
MAI
->
getCommentString
(
)
<<
"DEBUG_VALUE: "
;
DIVariable
V
(
const_cast
<
MDNode
*
>
(
MI
->
getOperand
(
NOps
1
)
.
getMetadata
(
)
)
)
;
O
<<
V
.
getName
(
)
;
O
<<
" <- "
;
assert
(
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
MI
->
getOperand
(
1
)
.
isImm
(
)
)
;
O
<<
'['
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
'+'
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
']'
;
O
<<
"+"
;
printOperand
(
MI
,
NOps
2
,
O
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
case
PPC
::
MovePCtoLR
:
case
PPC
::
MovePCtoLR8
:
{
MCSymbol
*
PICBase
=
MF
->
getPICBaseSymbol
(
)
;
TmpInst
.
setOpcode
(
PPC
::
BL_Darwin
)
;
TmpInst
.
addOperand
(
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
PICBase
,
OutContext
)
)
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
OutStreamer
.
EmitLabel
(
PICBase
)
;
return
;
}
case
PPC
::
LDtoc
:
{
LowerPPCMachineInstrToMCInst
(
MI
,
TmpInst
,
*
this
)
;
TmpInst
.
setOpcode
(
PPC
::
LD
)
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
1
)
;
assert
(
MO
.
isGlobal
(
)
)
;
MCSymbol
*
&
TOCEntry
=
TOC
[
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
]
;
if
(
TOCEntry
==
0
)
TOCEntry
=
GetTempSymbol
(
"C"
,
TOCLabelID
++
)
;
const
MCExpr
*
Exp
=
MCSymbolRefExpr
::
Create
(
TOCEntry
,
MCSymbolRefExpr
::
VK_PPC_TOC
,
OutContext
)
;
TmpInst
.
getOperand
(
1
)
=
MCOperand
::
CreateExpr
(
Exp
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
return
;
}
case
PPC
::
MFCRpseud
:
OutStreamer
.
AddComment
(
PPCInstPrinter
::
getRegisterName
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
)
;
TmpInst
.
setOpcode
(
PPC
::
MFCR
)
;
TmpInst
.
addOperand
(
MCOperand
::
CreateReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
return
;
}
LowerPPCMachineInstrToMCInst
(
MI
,
TmpInst
,
*
this
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( regs_ever_live [ first_reg ] && ( ! call_used_regs [ first_reg ] || ( first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != 0 ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) ) ) break ; if ( flag_pic && current_function_uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


<s> bool FPGATTIImpl :: isLegalMaskedStore ( Type * DataType ) { return true ; } </s>

Return true if the target supports masked store .


<s> bool useAA ( ) const override { return isCortexA53 ( ) ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> void ix86_split_convert_uns_si_sse ( rtx operands [ ] ) { machine_mode vecmode ; rtx value , large , zero_or_two31 , input , two31 , x ; large = operands [ 1 ] ; zero_or_two31 = operands [ 2 ] ; input = operands [ 3 ] ; two31 = operands [ 4 ] ; vecmode = GET_MODE ( large ) ; value = gen_rtx_REG ( vecmode , REGNO ( operands [ 0 ] ) ) ; if ( MEM_P ( input ) ) { if ( vecmode == V4SFmode ) emit_insn ( gen_vec_setv4sf_0 ( value , CONST0_RTX ( V4SFmode ) , input ) ) ; else emit_insn ( gen_sse2_loadlpd ( value , CONST0_RTX ( V2DFmode ) , input ) ) ; } else { input = gen_rtx_REG ( vecmode , REGNO ( input ) ) ; emit_move_insn ( value , CONST0_RTX ( vecmode ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_sse_movss ( value , value , input ) ) ; else emit_insn ( gen_sse2_movsd ( value , value , input ) ) ; } emit_move_insn ( large , two31 ) ; emit_move_insn ( zero_or_two31 , MEM_P ( two31 ) ? large : two31 ) ; x = gen_rtx_fmt_ee ( LE , vecmode , large , value ) ; emit_insn ( gen_rtx_SET ( large , x ) ) ; x = gen_rtx_AND ( vecmode , zero_or_two31 , large ) ; emit_insn ( gen_rtx_SET ( zero_or_two31 , x ) ) ; x = gen_rtx_MINUS ( vecmode , value , zero_or_two31 ) ; emit_insn ( gen_rtx_SET ( value , x ) ) ; large = gen_rtx_REG ( V4SImode , REGNO ( large ) ) ; emit_insn ( gen_ashlv4si3 ( large , large , GEN_INT ( 31 ) ) ) ; x = gen_rtx_REG ( V4SImode , REGNO ( value ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_fix_truncv4sfv4si2 ( x , value ) ) ; else emit_insn ( gen_sse2_cvttpd2dq ( x , value ) ) ; value = x ; emit_insn ( gen_xorv4si3 ( value , value , large ) ) ; } </s>

Post-reload splitter for converting an SF or DFmode value in an SSE register into an unsigned SImode .


<s> SDValue AArch64TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && Subtarget -> useRSqrt ( ) ) ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRSQRTE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Estimate , & Flags ) ; Step = DAG . getNode ( AArch64ISD :: FRSQRTS , DL , VT , Operand , Step , & Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , & Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( 0.0 , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , ISD :: SETEQ ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Operand , Estimate , & Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? ISD :: VSELECT : ISD :: SELECT , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> void markGlobalAsPromotedToConstantPool ( const GlobalVariable * GV ) { PromotedGlobals . insert ( GV ) ; } </s>

Indicate to the backend that GV has had its storage changed to inside a constant pool .


"unsupported cpu name returned from kernel "

Returns the canonical AT_PLATFORM if present , otherwise NULL .


<s> static rtx_insn * rs6000_frame_related ( rtx_insn * insn , rtx reg , HOST_WIDE_INT val , rtx reg2 , rtx repl2 ) { rtx repl ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) { gcc_checking_assert ( val == 0 ) ; repl = NULL_RTX ; } else repl = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ; rtx pat = PATTERN ( insn ) ; if ( ! repl && ! reg2 ) { if ( GET_CODE ( pat ) == PARALLEL ) for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } set_used_flags ( pat ) ; if ( GET_CODE ( pat ) == SET ) { if ( repl ) pat = simplify_replace_rtx ( pat , reg , repl ) ; if ( reg2 ) pat = simplify_replace_rtx ( pat , reg2 , repl2 ) ; } else if ( GET_CODE ( pat ) == PARALLEL ) { pat = shallow_copy_rtx ( pat ) ; XVEC ( pat , 0 ) = shallow_copy_rtvec ( XVEC ( pat , 0 ) ) ; for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( repl ) set = simplify_replace_rtx ( set , reg , repl ) ; if ( reg2 ) set = simplify_replace_rtx ( set , reg2 , repl2 ) ; XVECEXP ( pat , 0 , i ) = set ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } } else gcc_unreachable ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , copy_rtx_if_shared ( pat ) ) ; return insn ; } </s>

Add to 'insn ' a note which is PATTERN ( INSN ) but with REG replaced with ( plus : P ( reg 1 ) VAL ) , and with REG2 replaced with RREG if REG2 is not NULL . It would be nice if dwarf2out_frame_debug_expr could deduce these equivalences by itself so it was n't necessary to hold its hand so much . Do n't be tempted to always supply d2_f_d_e with the actual cfa register , ie . r31 when we are using a hard frame pointer . That fails when saving regs off r1 , and sched moves the r31 setup past the reg saves .


<s> static bool rs6000_save_toc_in_prologue_p ( void ) { return ( cfun && cfun -> machine && cfun -> machine -> save_toc_in_prologue ) ; } </s>

Return whether we need to always update the saved TOC pointer when we update the stack pointer .


<s> SDValue LC3TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && "Unsupported" ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_LC3 ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> const MipsRegisterInfo & Mips16InstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
unsigned
MipsCodeEmitter
::
getJumpTargetOpValue
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
MachineOperand
MO
=
MI
.
getOperand
(
OpNo
)
;
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unexpected jump target operand kind."
)
;
return
0
;
}
</s>

getJumpTargetOpValue - Return binary encoding of the jump target operand .

Mips
Mips
"Unexpected jump target operand kind."
0


<s> bool X86FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> int first_fp_reg_to_save ( void ) { int first_reg ; for ( first_reg = 14 + 32 ; first_reg <= 63 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; return first_reg ; } </s>


<s> static rtx sh_function_arg ( cumulative_args_t ca_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ! TARGET_SH5 && mode == VOIDmode ) return GEN_INT ( ca -> renesas_abi ? 1 : 0 ) ; if ( ! TARGET_SH5 && sh_pass_in_reg_p ( * ca , mode , type ) && ( named || ! ( TARGET_HITACHI || ca -> renesas_abi ) ) ) { int regno ; if ( mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ( ! FUNCTION_ARG_SCmode_WART || ( sh_round_reg ( * ca , mode ) & 1 ) ) ) { rtx r1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( sh_round_reg ( * ca , mode ) ^ 1 ) ) , const0_rtx ) ; rtx r2 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ( sh_round_reg ( * ca , mode ) + 1 ) ^ 1 ) ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( SCmode , gen_rtvec ( 2 , r1 , r2 ) ) ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && ca -> free_single_fp_reg && mode == SFmode ) return gen_rtx_REG ( mode , ca -> free_single_fp_reg ) ; regno = ( BASE_ARG_REG ( mode ) + sh_round_reg ( * ca , mode ) ) ^ ( mode == SFmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ! TARGET_HITACHI && ! ca -> renesas_abi ) ; return gen_rtx_REG ( mode , regno ) ; } if ( TARGET_SH5 ) { if ( mode == VOIDmode && TARGET_SHCOMPACT ) return GEN_INT ( ca -> call_cookie ) ; if ( mode == SFmode && ca -> free_single_fp_reg ) return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , ca -> free_single_fp_reg ) ; if ( ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT ) && ( named || ! ca -> prototype_p ) && ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { if ( ! ca -> prototype_p && TARGET_SHMEDIA ) return SH5_PROTOTYPELESS_FLOAT_ARG ( * ca , mode ) ; return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , FIRST_FP_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; } if ( ca -> arg_count [ ( int ) SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! TARGET_SHCOMPACT || ( ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * ca , mode , type , named ) ) ) ) { return gen_rtx_REG ( mode , ( FIRST_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_INT ] ) ) ; } return NULL_RTX ; } return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On SH the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
UP
.
UpperBound
=
true
;
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


"All AArch64 cmps should have 2 operands"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
bool
ARMCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
!
Val
==
!
VReg
&&
"Return value without a vreg"
)
;
auto
Ret
=
MIRBuilder
.
buildInstrNoInsert
(
ARM
::
BX_RET
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
if
(
!
lowerReturnVal
(
MIRBuilder
,
Val
,
VReg
,
Ret
)
)
return
false
;
MIRBuilder
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

ARM
ARM
"Return value without a vreg"
ARM::BX_RET
ARMCC::AL


<s> int X86RegisterInfo :: getDwarfRegNum ( unsigned RegNo , bool isEH ) const { const X86Subtarget * Subtarget = & TM . getSubtarget < X86Subtarget > ( ) ; unsigned Flavour = DWARFFlavour :: X86_64 ; if ( ! Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetDarwin ( ) ) { if ( isEH ) Flavour = DWARFFlavour :: X86_32_DarwinEH ; else Flavour = DWARFFlavour :: X86_32_Generic ; } else if ( Subtarget -> isTargetCygMing ( ) ) { Flavour = DWARFFlavour :: X86_32_Generic ; } else { Flavour = DWARFFlavour :: X86_32_Generic ; } } return X86GenRegisterInfo :: getDwarfRegNumFull ( RegNo , Flavour ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s> bool AArch64TargetLowering :: shouldExpandGetActiveLaneMask ( EVT ResVT , EVT OpVT ) const { if ( ! Subtarget -> hasSVE ( ) ) return true ; if ( ResVT != MVT :: nxv2i1 && ResVT != MVT :: nxv4i1 && ResVT != MVT :: nxv8i1 && ResVT != MVT :: nxv16i1 ) return true ; if ( OpVT != MVT :: i32 && OpVT != MVT :: i64 ) return true ; return false ; } </s>

Return true if the @ llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder .


<s> int arm_no_early_alu_shift_dep ( rtx producer , rtx consumer ) { rtx value , op ; rtx early_op ; if ( ! arm_get_set_operands ( producer , consumer , & value , & op ) ) return 0 ; if ( ( early_op = arm_find_shift_sub_rtx ( op ) ) ) return ! reg_overlap_mentioned_p ( value , early_op ) ; return 0 ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value or amount dependency on the result of PRODUCER .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


<s> int mips_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { int size ; HARD_REG_SET left ; size = 0x8000 ; COPY_HARD_REG_SET ( left , reg_class_contents [ ( int ) rclass ] ) ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) ST_REGS ] ) ) { if ( mips_hard_regno_mode_ok ( ST_REG_FIRST , mode ) ) size = MIN ( size , 4 ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) ST_REGS ] ) ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( mips_hard_regno_mode_ok ( FP_REG_FIRST , mode ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) size = MIN ( size , UNITS_PER_MSA_REG ) ; else size = MIN ( size , UNITS_PER_FPREG ) ; } AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) FP_REGS ] ) ; } if ( ! hard_reg_set_empty_p ( left ) ) size = MIN ( size , UNITS_PER_WORD ) ; return ( GET_MODE_SIZE ( mode ) + size - 1 ) / size ; } </s>

Implement CLASS_MAX_NREGS . Usually all registers are word-sized . The only supported exception is -mgp64 -msingle-float , which has 64-bit words but 32-bit float registers . A word-based calculation is correct even in that case , since -msingle-float disallows multi-FPR values . The FP status registers are an exception to this rule . They are always 4 bytes wide as they only hold condition code modes , and CCmode is always considered to be 4 bytes wide .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static void sparc_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; tree type = arg . type ; machine_mode mode = arg . mode ; int regno , padding ; function_arg_slotno ( cum , mode , type , arg . named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ; else { if ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) { const int size = int_size_in_bytes ( type ) ; if ( size <= 0 ) cum -> words ++ ; else cum -> words += CEIL_NWORDS ( size ) ; } else cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ; } } </s>

Handle the TARGET_FUNCTION_ARG_ADVANCE hook . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> static unsigned int mips_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return alignment ; } </s>

Implement TARGET_FUNCTION_ARG_BOUNDARY . Every parameter gets at least PARM_BOUNDARY bits of alignment , but will be given anything up to STACK_BOUNDARY bits if the type requires it .


<s> bool isSubregFoldable ( ) const override { return true ; } </s>

Check whether the target can fold a load that feeds a subreg operand ( or a subreg operand that feeds a store ) .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s>
bool
ARM64InstrInfo
::
isFPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
ARM64
::
FPR64RegClass
.
contains
(
DstReg
)
||
ARM64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
ARM64
::
ORRv16i8
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


"// rs6000_variable_issue (more = %d) = %d\n"

Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle . Branches have their own dispatch slot which does not count against the GCC issue rate , but it changes the program flow so there are no other instructions to issue in this cycle .


<s> static void ix86_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned HOST_WIDE_INT ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = HOST_WIDE_INT_1U << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( ix86_tune , false ) ; } </s>


"Unknown fence ordering in emitLeadingFence"


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Mcpu = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getMcpu ( ) ; if ( Mcpu == PPC :: MCPU_PWR6 || Mcpu == PPC :: MCPU_PWR7 || Mcpu == PPC :: MCPU_PWR8 || Mcpu == PPC :: MCPU_PWR9 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static bool loongarch_memmodel_needs_release_fence ( enum memmodel model ) { switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : return true ; case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : case MEMMODEL_RELAXED : return false ; default : gcc_unreachable ( ) ; } } </s>

Return true if a FENCE should be emitted to before a memory access to implement the release portion of memory model MODEL .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Branch Expansion Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void X86AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { X86MCInstLower MCInstLowering ( OutContext , Mang , * this ) ; switch ( MI -> getOpcode ( ) ) { case TargetOpcode :: DBG_VALUE : if ( isVerbose ( ) && OutStreamer . hasRawTextSupport ( ) ) { std :: string TmpStr ; raw_string_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; case X86 :: MOVPC32r : { MCInst TmpInst ; MCSymbol * PICBase = MCInstLowering . GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( X86 :: CALLpcrel32 ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( X86 :: POP32r ) ; TmpInst . getOperand ( 0 ) = MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case X86 :: ADD32ri : { if ( MI -> getOperand ( 2 ) . getTargetFlags ( ) != X86II :: MO_GOT_ABSOLUTE_ADDRESS ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( 2 ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MCInstLowering . GetPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( X86 :: ADD32ri ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( DotExpr ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool DCPU16AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


Initialize register TARGET from the elements in PARALLEL rtx VALS .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( VT . getSizeInBits ( ) == 64 ) return false ; if ( ExperimentalVectorShuffleLegality ) return isTypeLegal ( SVT ) ; if ( ( SVT . is128BitVector ( ) && Subtarget -> hasSSSE3 ( ) ) || ( SVT . is256BitVector ( ) && Subtarget -> hasInt256 ( ) ) ) { bool isLegal = true ; for ( unsigned I = 0 , E = M . size ( ) ; I != E ; ++ I ) { if ( M [ I ] >= ( int ) SVT . getVectorNumElements ( ) || ShuffleCrosses128bitLane ( SVT , I , M [ I ] ) ) { isLegal = false ; break ; } } if ( isLegal ) return true ; } return ( SVT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , SVT ) || isCommutedMOVLMask ( M , SVT ) || isMOVHLPSMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isSHUFPMask ( M , SVT , true ) || isPSHUFDMask ( M , SVT ) || isPSHUFDMask ( M , SVT , true ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isBlendMask ( M , SVT , Subtarget -> hasSSE41 ( ) , Subtarget -> hasInt256 ( ) ) || ( Subtarget -> hasSSE41 ( ) && isINSERTPSMask ( M , SVT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static int distance_non_agu_define ( unsigned int regno1 , unsigned int regno2 , rtx_insn * insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; int distance = 0 ; bool found = false ; if ( insn != BB_HEAD ( bb ) ) distance = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , PREV_INSN ( insn ) , & found ) ; if ( ! found && distance < LEA_SEARCH_THRESHOLD ) { edge e ; edge_iterator ei ; bool simple_loop = false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( e -> src == bb ) { simple_loop = true ; break ; } if ( simple_loop ) distance = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , BB_END ( bb ) , & found ) ; else { int shortest_dist = - 1 ; bool found_in_bb = false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { int bb_dist = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , BB_END ( e -> src ) , & found_in_bb ) ; if ( found_in_bb ) { if ( shortest_dist < 0 ) shortest_dist = bb_dist ; else if ( bb_dist > 0 ) shortest_dist = MIN ( bb_dist , shortest_dist ) ; found = true ; } } distance = shortest_dist ; } } if ( ! found ) return - 1 ; return distance >> 1 ; } </s>

Search backward for non-agu definition of register number REGNO1 or register number REGNO2 in INSN 's basic block until 1 . Pass LEA_SEARCH_THRESHOLD instructions , or 2 . Reach neighbour BBs boundary , or 3 . Reach agu definition . Returns the distance between the non-agu definition point and INSN . If no definition point , returns -1 .


<s> bool X86TargetLowering :: isBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: PMULUDQ : case X86ISD :: FMAX : case X86ISD :: FMIN : case X86ISD :: FMAXC : case X86ISD :: FMINC : case X86ISD :: FAND : case X86ISD :: FANDN : case X86ISD :: FOR : case X86ISD :: FXOR : return true ; } return TargetLoweringBase :: isBinOp ( Opcode ) ; } </s>

Add x86-specific opcodes to the default list .


<s> bool ARMTargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( auto * Ld = dyn_cast < MaskedLoadSDNode > ( ExtVal . getOperand ( 0 ) ) ) { if ( Ld -> isExpandingLoad ( ) ) return false ; } if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == ISD :: ADD || U -> getOpcode ( ) == ISD :: SUB || U -> getOpcode ( ) == ISD :: SHL || U -> getOpcode ( ) == ARMISD :: VSHLIMM ) ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .

ARM ARM 0 ISD::ADD ISD::SUB ISD::SHL ARMISD::VSHLIMM


<s> void AArch64AsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! AArch64FI -> getLOHRelated ( ) . empty ( ) ) emitLOHs ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> TargetIRAnalysis SystemZTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( SystemZTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s> bool aarch64_use_simple_return_insn_p ( void ) { if ( aarch64_simd_decl_p ( cfun -> decl ) && ! crtl -> is_leaf ) return false ; return true ; } </s>

Return false for non-leaf SIMD functions in order to avoid shrink-wrapping them . Doing this will lose the necessary save/restore of FP registers .


<s> bool symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return true ; } return false ; } </s>

Return true if OP contains a symbol reference


<s> MachineInstr * ARM64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == ARM64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & ARM64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == ARM64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & ARM64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .