<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Cond
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterInfo
&
TRI
=
*
MRI
.
getTargetRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
getCMovFromCond
(
(
X86
::
CondCode
)
Cond
[
0
]
.
getImm
(
)
,
TRI
.
getRegSizeInBits
(
RC
)
/
8
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> static void nds32_emit_load_store ( rtx reg , rtx mem , enum machine_mode mode , int offset , bool load_p ) { rtx new_mem ; new_mem = adjust_address ( mem , mode , offset ) ; if ( load_p ) emit_move_insn ( reg , new_mem ) ; else emit_move_insn ( new_mem , reg ) ; } </s>


<s>
void
pa_asm_output_aligned_bss
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
bss_section
(
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_TYPE_DIRECTIVE
(
stream
,
name
,
"object"
)
;
ASM_OUTPUT_SIZE_DIRECTIVE
(
stream
,
name
,
size
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_LABEL
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.block "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
size
)
;
}
</s>

This function places uninitialized global data in the bss section . The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this function on the SOM port to prevent uninitialized global data from being placed in the data section .

pa
"\t.align %u\n"
"object"
"\t.align %u\n"
"\t.block "
"\n"


<s> InstructionCost AArch64TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> bool PPCLoopInstrFormPrep :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; SuccPrepCount = 0 ; bool MadeChange = false ; for ( Loop * I : * LI ) for ( Loop * L : depth_first ( I ) ) MadeChange |= runOnLoop ( L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"Not all fixup kinds added to Infos array"


<s> static void winnt_d_os_builtins ( void ) { d_add_builtin_version ( "Windows" ) ; EXTRA_TARGET_D_OS_VERSIONS ( ) ; } </s>

Implement TARGET_D_OS_VERSIONS for Windows targets .


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
addPass
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
(
DisableA15SDOptimization
||
!
getARMSubtarget
(
)
.
isCortexA15
(
)
)
&&
getARMSubtarget
(
)
.
hasNEON
(
)
)
addPass
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
addPass
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
addPass
(
&
IfConverterID
)
;
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
addPass
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM
ARM::DPRRegClass
ARM
ARM
ARM


<s> bool ARMPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Ins ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) ; const MipsABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , 1 ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void SystemZPassConfig :: addPostRewrite ( ) { addPass ( createSystemZPostRewritePass ( getSystemZTargetMachine ( ) ) ) ; } </s>

Add passes to be run immediately after virtual registers are rewritten to physical registers .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , I . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int vspltis_shifted ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i , j ; unsigned nunits ; unsigned mask ; HOST_WIDE_INT val ; if ( mode != V16QImode && mode != V8HImode && mode != V4SImode ) return false ; if ( ! can_create_pseudo_p ( ) ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? 0 : nunits - 1 ) ; if ( EASY_VECTOR_15 ( val ) ) ; else if ( EASY_VECTOR_MSB ( val , inner ) ) ; else return 0 ; for ( i = 1 ; i < nunits ; ++ i ) { unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i ; HOST_WIDE_INT elt_val = const_vector_elt_as_int ( op , elt ) ; if ( val != elt_val ) { if ( elt_val == 0 ) { for ( j = i + 1 ; j < nunits ; ++ j ) { unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j ; if ( const_vector_elt_as_int ( op , elt2 ) != 0 ) return 0 ; } return ( nunits - i ) * GET_MODE_SIZE ( inner ) ; } else if ( ( elt_val & mask ) == mask ) { for ( j = i + 1 ; j < nunits ; ++ j ) { unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j ; if ( ( const_vector_elt_as_int ( op , elt2 ) & mask ) != mask ) return 0 ; } return - ( ( nunits - i ) * GET_MODE_SIZE ( inner ) ) ; } else return 0 ; } } return 0 ; } </s>

Like vsplitis_constant , but allow the value to be shifted left with a VSLDOI instruction , filling in the bottom elements with 0 or -1 . Return 0 if the constant can not be generated with VSLDOI . Return positive for the number of zeroes to shift in , or negative for the number of 0xff bytes to shift in . OP is a CONST_VECTOR .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
,
Subtarget
)
;
case
ISD
::
SHL
:
Val
=
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips
Mips
ISD::AND
ISD::OR
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


<s> rtx rs6000_force_indexed_or_indirect_mem ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; gcc_assert ( MEM_P ( x ) ) ; if ( can_create_pseudo_p ( ) && ! indexed_or_indirect_operand ( x , mode ) ) { rtx addr = XEXP ( x , 0 ) ; if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , force_reg ( Pmode , addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX and LDBRX that only take reg+reg addressing .


<s>
static
bool
cortexa7_younger
(
FILE
*
file
,
int
verbose
,
rtx_insn
*
insn
)
{
if
(
recog_memoized
(
insn
)
<
0
)
{
if
(
verbose
>
5
)
fprintf
(
file
,
";; not cortexa7_younger %d\n"
,
INSN_UID
(
insn
)
)
;
return
false
;
}
switch
(
get_attr_type
(
insn
)
)
{
case
TYPE_ALU_IMM
:
case
TYPE_ALUS_IMM
:
case
TYPE_LOGIC_IMM
:
case
TYPE_LOGICS_IMM
:
case
TYPE_EXTEND
:
case
TYPE_MVN_IMM
:
case
TYPE_MOV_IMM
:
case
TYPE_MOV_REG
:
case
TYPE_MOV_SHIFT
:
case
TYPE_MOV_SHIFT_REG
:
case
TYPE_BRANCH
:
case
TYPE_CALL
:
return
true
;
default
:
return
false
;
}
}
</s>

Return true if and only if this insn can dual-issue as younger .


<s> void OutgoingValueHandler :: assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO ) { MachineMemOperand * MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 0 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
const
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
0
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


"BasePointer is not implemented on AIX yet."

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s> static bool aarch64_integer_truncation_p ( stmt_vec_info stmt_info ) { gassign * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ; if ( ! assign || ! CONVERT_EXPR_CODE_P ( gimple_assign_rhs_code ( assign ) ) ) return false ; tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( gimple_assign_rhs1 ( assign ) ) ; return ( INTEGRAL_TYPE_P ( lhs_type ) && INTEGRAL_TYPE_P ( rhs_type ) && TYPE_PRECISION ( lhs_type ) < TYPE_PRECISION ( rhs_type ) ) ; } </s>

Return true if STMT_INFO is an integer truncation .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != MVT :: v4f64 && VT != MVT :: v4f32 ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 0 ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 4 ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass 0 ARM::t2LDRi12 0 ARM


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr & MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI . mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI . getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , * DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s>
SDValue
CAHPTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_CAHP
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
CAHPISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"stack re-alignment, but LLVM couldn't handle it "

"(probably because it has a dynamic alloca)."

"SP has to be saved in order to align variable sized stack object!"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool SystemZTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 32 > ( Imm ) || isUInt < 32 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> static void mips_sim_wait_insn ( struct mips_sim * state , rtx_insn * insn ) { mips_sim_wait_regs ( state , insn ) ; mips_sim_wait_units ( state , insn ) ; } </s>

Advance simulation state STATE until INSN is ready to issue .


<s> const char * standard_80387_constant_opcode ( rtx x ) { switch ( standard_80387_constant_p ( x ) ) { case 1 : return "fldz" ; case 2 : return "fld1" ; case 3 : return "fldlg2" ; case 4 : return "fldln2" ; case 5 : return "fldl2e" ; case 6 : return "fldl2t" ; case 7 : return "fldpi" ; case 8 : case 9 : return "#" ; default : gcc_unreachable ( ) ; } } </s>

Return the opcode of the special instruction to be used to load the constant X .


<s> virtual unsigned int execute ( function * ) { return rest_of_insert_bti ( ) ; } </s>


<s> void MipsELFStreamer :: EmitMipsOptionRecords ( ) { for ( const auto & I : MipsOptionRecords ) I -> EmitMipsOptionRecord ( ) ; } </s>

Emits all the option records stored up until the point it 's called .


<s> int loongarch_idiv_insns ( machine_mode mode ATTRIBUTE_UNUSED ) { int count ; count = 1 ; if ( TARGET_CHECK_ZERO_DIV ) count += 2 ; return count ; } </s>

Return the number of instructions needed for an integer division .


<s> rtx expand ( function_expander & e ) const override { for ( unsigned int i = 0 ; i < 2 ; ++ i ) e . args [ i ] = e . convert_to_pmode ( e . args [ i ] ) ; return e . use_exact_insn ( code_for_while ( m_unspec , Pmode , e . gp_mode ( 0 ) ) ) ; } </s>


<s> static inline int mov_insn_size ( machine_mode mode , bool consider_sh2a ) { const int mode_sz = GET_MODE_SIZE ( mode ) ; if ( ( consider_sh2a && TARGET_SH2A_DOUBLE && mode == DFmode ) || ( TARGET_FMOVD && mode == DFmode ) ) return mode_sz ; else { const int max_mov_sz = GET_MODE_SIZE ( SImode ) ; return mode_sz >= max_mov_sz ? max_mov_sz : mode_sz ; } } </s>

Determine the size of the fundamental move insn that will be used for the specified mode .


<s> static bool hppa_rtx_costs_shadd_p ( rtx x ) { if ( GET_CODE ( x ) != PLUS || ! REG_P ( XEXP ( x , 1 ) ) ) return false ; rtx op0 = XEXP ( x , 0 ) ; if ( GET_CODE ( op0 ) == ASHIFT && CONST_INT_P ( XEXP ( op0 , 1 ) ) && REG_P ( XEXP ( op0 , 0 ) ) ) { unsigned HOST_WIDE_INT x = UINTVAL ( XEXP ( op0 , 1 ) ) ; return x == 1 || x == 2 || x == 3 ; } if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( XEXP ( op0 , 1 ) ) && REG_P ( XEXP ( op0 , 0 ) ) ) { unsigned HOST_WIDE_INT x = UINTVAL ( XEXP ( op0 , 1 ) ) ; return x == 2 || x == 4 || x == 8 ; } return false ; } </s>

Return true if X represents a ( possibly non-canonical ) shNadd pattern . The machine mode of X is known to be SImode or DImode .


<s> bool isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const override { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case V16QImode : case V8HImode : case V4SFmode : case V4SImode : case V2DFmode : case V2DImode : case V1TImode : case TImode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return false ; break ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s>
unsigned
ARMBaseInstrInfo
::
getNumMicroOps
(
const
InstrItineraryData
*
ItinData
,
const
MachineInstr
*
MI
)
const
{
if
(
!
ItinData
||
ItinData
->
isEmpty
(
)
)
return
1
;
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
Class
=
Desc
.
getSchedClass
(
)
;
int
ItinUOps
=
ItinData
->
getNumMicroOps
(
Class
)
;
if
(
ItinUOps
>=
0
)
return
ItinUOps
;
unsigned
Opc
=
MI
->
getOpcode
(
)
;
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Unexpected multi-uops instruction!"
)
;
case
ARM
::
VLDMQIA
:
case
ARM
::
VSTMQIA
:
return
2
;
case
ARM
::
VLDMDIA
:
case
ARM
::
VLDMDIA_UPD
:
case
ARM
::
VLDMDDB_UPD
:
case
ARM
::
VLDMSIA
:
case
ARM
::
VLDMSIA_UPD
:
case
ARM
::
VLDMSDB_UPD
:
case
ARM
::
VSTMDIA
:
case
ARM
::
VSTMDIA_UPD
:
case
ARM
::
VSTMDDB_UPD
:
case
ARM
::
VSTMSIA
:
case
ARM
::
VSTMSIA_UPD
:
case
ARM
::
VSTMSDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
;
return
(
NumRegs
/
2
)
+
(
NumRegs
%
2
)
+
1
;
}
case
ARM
::
LDMIA_RET
:
case
ARM
::
LDMIA
:
case
ARM
::
LDMDA
:
case
ARM
::
LDMDB
:
case
ARM
::
LDMIB
:
case
ARM
::
LDMIA_UPD
:
case
ARM
::
LDMDA_UPD
:
case
ARM
::
LDMDB_UPD
:
case
ARM
::
LDMIB_UPD
:
case
ARM
::
STMIA
:
case
ARM
::
STMDA
:
case
ARM
::
STMDB
:
case
ARM
::
STMIB
:
case
ARM
::
STMIA_UPD
:
case
ARM
::
STMDA_UPD
:
case
ARM
::
STMDB_UPD
:
case
ARM
::
STMIB_UPD
:
case
ARM
::
tLDMIA
:
case
ARM
::
tLDMIA_UPD
:
case
ARM
::
tSTMIA_UPD
:
case
ARM
::
tPOP_RET
:
case
ARM
::
tPOP
:
case
ARM
::
tPUSH
:
case
ARM
::
t2LDMIA_RET
:
case
ARM
::
t2LDMIA
:
case
ARM
::
t2LDMDB
:
case
ARM
::
t2LDMIA_UPD
:
case
ARM
::
t2LDMDB_UPD
:
case
ARM
::
t2STMIA
:
case
ARM
::
t2STMDB
:
case
ARM
::
t2STMIA_UPD
:
case
ARM
::
t2STMDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
+
1
;
if
(
Subtarget
.
isCortexA8
(
)
)
{
if
(
NumRegs
<
4
)
return
2
;
int
A8UOps
=
(
NumRegs
/
2
)
;
if
(
NumRegs
%
2
)
++
A8UOps
;
return
A8UOps
;
}
else
if
(
Subtarget
.
isCortexA9
(
)
)
{
int
A9UOps
=
(
NumRegs
/
2
)
;
if
(
(
NumRegs
%
2
)
||
!
MI
->
hasOneMemOperand
(
)
||
(
*
MI
->
memoperands_begin
(
)
)
->
getAlignment
(
)
<
8
)
++
A9UOps
;
return
A9UOps
;
}
else
{
return
NumRegs
;
}
}
}
}
</s>

Return the number of issue slots required for this MI .


<s> static bool sparc_promote_prototypes ( tree fntype ATTRIBUTE_UNUSED ) { return TARGET_ARCH32 ? true : false ; } </s>

Handle the TARGET_PROMOTE_PROTOTYPES target hook . When a prototype says ` char ' or ` short ' , really pass an ` int ' .


<s> static void do_ifelse ( machine_mode cmpmode , rtx_code comparison , rtx a , rtx b , rtx cr , rtx true_label , profile_probability br_prob ) { gcc_assert ( ( a == NULL_RTX && b == NULL_RTX && cr != NULL_RTX ) || ( a != NULL_RTX && b != NULL_RTX ) ) ; if ( cr != NULL_RTX ) gcc_assert ( GET_MODE ( cr ) == cmpmode ) ; else cr = gen_reg_rtx ( cmpmode ) ; rtx label_ref = gen_rtx_LABEL_REF ( VOIDmode , true_label ) ; if ( a != NULL_RTX ) emit_move_insn ( cr , gen_rtx_COMPARE ( cmpmode , a , b ) ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( comparison , VOIDmode , cr , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , label_ref , pc_rtx ) ; rtx_insn * j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; add_reg_br_prob_note ( j , br_prob ) ; JUMP_LABEL ( j ) = true_label ; LABEL_NUSES ( true_label ) += 1 ; } </s>

Do a branch for an if/else decision . CMPMODE is the mode to use for the comparison . COMPARISON is the rtx code for the compare needed . A is the first thing to be compared . B is the second thing to be compared . CR is the condition code reg input , or NULL_RTX . TRUE_LABEL is the label to branch to if the condition is true . The return value is the CR used for the comparison . If CR is null_rtx , then a new register of CMPMODE is generated . If A and B are both null_rtx , then CR must not be null , and the compare is not generated so you can use this with a dot form insn .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( ( getFixupKindInfo ( Kind ) . TargetSize - 1 ) / 8 ) + 1 ; uint64_t Mask = ( ( uint64_t ) 1 << getFixupKindInfo ( Kind ) . TargetSize ) - 1 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) CurVal |= ( ( uint8_t ) Data [ Offset + i ] ) << ( i * 8 ) ; CurVal = ( CurVal & ~ Mask ) | ( ( CurVal + Value ) & Mask ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { Data [ Offset + i ] = uint8_t ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
DecodeStatus
CAHPDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
OS
,
raw_ostream
&
CS
)
const
{
if
(
Bytes
.
size
(
)
<
2
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
uint32_t
Inst
;
DecodeStatus
Result
;
uint8_t
is24bitInst
=
Bytes
[
0
]
&
1
;
if
(
is24bitInst
)
{
if
(
Bytes
.
size
(
)
<
3
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
Inst
=
Bytes
[
0
]
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
2
]
<<
16
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying CAHP 24bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable24
,
MI
,
Inst
,
Address
,
this
,
STI
)
;
Size
=
3
;
}
else
{
if
(
Bytes
.
size
(
)
<
2
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
Inst
=
support
::
endian
::
read16le
(
Bytes
.
data
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying CAHP 16bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable16
,
MI
,
Inst
,
Address
,
this
,
STI
)
;
Size
=
2
;
}
return
Result
;
}
</s>

Returns the disassembly of a single instruction .


<s> int registers_ok_for_quad_peep ( rtx reg1 , rtx reg2 ) { if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return 0 ; if ( ! FP_REGNO_P ( REGNO ( reg1 ) ) || ! FP_REGNO_P ( REGNO ( reg2 ) ) ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) == REGNO ( reg2 ) - 1 making them candidates for lfq and stfq insns . Note reg1 and reg2 * must * be hard registers . To be sure we will abort if we are passed pseudo registers .


<s> static bool rs6000_reg_live_or_pic_offset_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ; } return ( ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) ) && ! call_used_regs [ reg ] ) ; } </s>

Determine whether the gp REG is really used .


<s> static inline int addsubcosts ( rtx x ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == REG || GET_CODE ( XEXP ( x , 1 ) ) == SUBREG ) return 1 ; if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && CONST_OK_FOR_ADD ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 1 ; if ( TARGET_SHMEDIA ) switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST : case LABEL_REF : case SYMBOL_REF : return TARGET_SHMEDIA64 ? 5 : 3 ; case CONST_INT : if ( CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 2 ; else if ( CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) >> 16 ) ) return 3 ; else if ( CONST_OK_FOR_I16 ( ( INTVAL ( XEXP ( x , 1 ) ) >> 16 ) >> 16 ) ) return 4 ; default : return 5 ; } return 3 ; } </s>

Return the cost of an addition or a subtraction .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM pseudo instruction expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

ARM
"ARM pseudo instruction expansion pass"


"Intrinsic instructions can't commute operand 1"

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted .


<s> void MipsTargetMachine :: resetSubtarget ( MachineFunction * MF ) { DEBUG ( dbgs ( ) << "resetSubtarget\n" ) ; Subtarget = const_cast < MipsSubtarget * > ( getSubtargetImpl ( MF -> getFunction ( ) ) ) ; MF -> setSubtarget ( Subtarget ) ; } </s>

Reset the subtarget for the Mips target .


<s> bool X86TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { Type * MemType = SI -> getValueOperand ( ) -> getType ( ) ; bool NoImplicitFloatOps = SI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && Subtarget . hasSSE2 ( ) ) return false ; return needsCmpXchgNb ( MemType ) ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> void MipsCallLowering :: splitToValueTypes ( const DataLayout & DL , const ArgInfo & OrigArg , unsigned OriginalIndex , SmallVectorImpl < ArgInfo > & SplitArgs , SmallVectorImpl < unsigned > & SplitArgsOrigIndices ) const { SmallVector < EVT , 4 > SplitEVTs ; SmallVector < Register , 4 > SplitVRegs ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitEVTs ) ; for ( unsigned i = 0 ; i < SplitEVTs . size ( ) ; ++ i ) { ArgInfo Info = ArgInfo { OrigArg . Regs [ i ] , SplitEVTs [ i ] . getTypeForEVT ( Ctx ) } ; Info . Flags = OrigArg . Flags ; SplitArgs . push_back ( Info ) ; SplitArgsOrigIndices . push_back ( OriginalIndex ) ; } } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
BITCAST
:
ReplaceBITCASTResults
(
N
,
Results
,
DAG
)
;
return
;
case
AArch64ISD
::
SADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
SADDV
)
;
return
;
case
AArch64ISD
::
UADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
UADDV
)
;
return
;
case
AArch64ISD
::
SMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMIN
,
AArch64ISD
::
SMINV
)
;
return
;
case
AArch64ISD
::
UMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMIN
,
AArch64ISD
::
UMINV
)
;
return
;
case
AArch64ISD
::
SMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMAX
,
AArch64ISD
::
SMAXV
)
;
return
;
case
AArch64ISD
::
UMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMAX
,
AArch64ISD
::
UMAXV
)
;
return
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = SystemZMC :: CallFrameSize ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = SystemZMC :: CallFrameSize + MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"X86 Support for protection of register spills"


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : case AArch64 :: ZPRRegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : case AArch64 :: ZPR2RegClassID : case AArch64 :: ZPR3RegClassID : case AArch64 :: ZPR4RegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = getMipsRegisterNumbering ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; Mips :: Fixups FixupKind ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { case MCSymbolRefExpr :: VK_Mips_GPREL : FixupKind = Mips :: fixup_Mips_GPREL16 ; break ; case MCSymbolRefExpr :: VK_Mips_GOT_CALL : FixupKind = Mips :: fixup_Mips_CALL16 ; break ; case MCSymbolRefExpr :: VK_Mips_GOT16 : FixupKind = Mips :: fixup_Mips_GOT_Global ; break ; case MCSymbolRefExpr :: VK_Mips_GOT : FixupKind = Mips :: fixup_Mips_GOT_Local ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_HI : FixupKind = Mips :: fixup_Mips_HI16 ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_LO : FixupKind = Mips :: fixup_Mips_LO16 ; break ; case MCSymbolRefExpr :: VK_Mips_TLSGD : FixupKind = Mips :: fixup_Mips_TLSGD ; break ; case MCSymbolRefExpr :: VK_Mips_TLSLDM : FixupKind = Mips :: fixup_Mips_TLSLDM ; break ; case MCSymbolRefExpr :: VK_Mips_DTPREL_HI : FixupKind = Mips :: fixup_Mips_DTPREL_HI ; break ; case MCSymbolRefExpr :: VK_Mips_DTPREL_LO : FixupKind = Mips :: fixup_Mips_DTPREL_LO ; break ; case MCSymbolRefExpr :: VK_Mips_GOTTPREL : FixupKind = Mips :: fixup_Mips_GOTTPREL ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_HI : FixupKind = Mips :: fixup_Mips_TPREL_HI ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_LO : FixupKind = Mips :: fixup_Mips_TPREL_LO ; break ; default : break ; } Fixups . push_back ( MCFixup :: Create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool X86AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << "(%rip)" ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; printOperand ( MI , OpNo , O ) ; return false ; case 'P' : printPCRelImm ( MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo , O , 0 , AsmVariant ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> fma_forest * fma_root_node :: get_forest ( ) { return this -> m_forest ; } </s>

Get the actual forest associated with a non root node as the one the node points to might have been merged into another one . In that case the pointer in the root nodes are updated so we return the forest pointer of a root node pointed to by the initial forest . Despite being a oneliner , this method is defined here as it references a method from fma_root_node .


<s> bool OR1KAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'H' : if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << OR1KInstPrinter :: getRegisterName ( Reg ) ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { struct cl_target_option cl_opts ; if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; cl_target_option_save ( & cl_opts , opts ) ; arm_configure_build_target ( & arm_active_target , & cl_opts , opts_set , false ) ; arm_option_check_internal ( opts ) ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s> static bool adjacent_mem_locations ( rtx mem1 , rtx mem2 ) { rtx reg1 , reg2 ; HOST_WIDE_INT off1 , size1 , off2 , size2 ; if ( get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) ) return ( ( REGNO ( reg1 ) == REGNO ( reg2 ) ) && ( ( off1 + size1 == off2 ) || ( off2 + size2 == off1 ) ) ) ; return false ; } </s>

If the target storage locations of arguments MEM1 and MEM2 are adjacent , then return the argument that has the lower address . Otherwise , return NULL_RTX .


<s> bool X86DynAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasDynAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = 4096 ; if ( MF . getFunction ( ) . hasFnAttribute ( "stack-probe-size" ) ) { MF . getFunction ( ) . getFnAttribute ( "stack-probe-size" ) . getValueAsString ( ) . getAsInteger ( 0 , StackProbeSize ) ; } NoStackArgProbe = MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ; if ( NoStackArgProbe ) StackProbeSize = INT64_MAX ; LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx aarch64_simd_vect_par_cnst_half ( machine_mode mode , bool high ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits / 2 ) ; int high_base = nunits / 2 ; int low_base = 0 ; int base ; rtx t1 ; int i ; if ( BYTES_BIG_ENDIAN ) base = high ? low_base : high_base ; else base = high ? high_base : low_base ; for ( i = 0 ; i < nunits / 2 ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( base + i ) ; t1 = gen_rtx_PARALLEL ( mode , v ) ; return t1 ; } </s>

Construct and return a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low ( HIGH == FALSE ) half of the vector - from the perspective of the architecture . This does not line up with GCC 's perspective on lane numbers , so we end up with different masks depending on our target endian-ness . The diagram below may help . We must draw the distinction when building masks which select one half of the vector . An instruction selecting architectural low-lanes for a big-endian target , must be described using a mask selecting GCC high-lanes . Big-Endian Little-EndianGCC 0 1 2 3 3 2 1 0 | x | x | x | x | | x | x | x | x |Architecture 3 2 1 0 3 2 1 0Low Mask : { 2 , 3 } { 0 , 1 } High Mask : { 0 , 1 } { 2 , 3 }


<s> const uint32_t * VERegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: Fast : default : return CSR_RegMask ; case CallingConv :: PreserveAll : return CSR_preserve_all_RegMask ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static const char * arm_shift_nmem ( enum rtx_code code ) { switch ( code ) { case ASHIFT : return ARM_LSL_NAME ; case ASHIFTRT : return "asr" ; case LSHIFTRT : return "lsr" ; case ROTATERT : return "ror" ; default : abort ( ) ; } } </s>

Return the name of a shifter operation .


<s>
SDValue
MMIXTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_MMIX
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
MMIXISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const SHUXIInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void ix86_emit_swdivsf ( rtx res , rtx a , rtx b , machine_mode mode ) { rtx x0 , x1 , e0 , e1 ; x0 = gen_reg_rtx ( mode ) ; e0 = gen_reg_rtx ( mode ) ; e1 = gen_reg_rtx ( mode ) ; x1 = gen_reg_rtx ( mode ) ; b = force_reg ( mode , b ) ; if ( mode == V16SFmode || mode == V8DFmode ) emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , b ) , UNSPEC_RCP14 ) ) ) ; else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , b ) , UNSPEC_RCP ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , b ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( e1 , gen_rtx_PLUS ( mode , x0 , x0 ) ) ) ; emit_insn ( gen_rtx_SET ( x1 , gen_rtx_MINUS ( mode , e1 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_MULT ( mode , a , x1 ) ) ) ; } </s>


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MipsABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == 0 ) return ; if ( ABI . IsCheriPureCap ( ) ) { if ( isInt < 11 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( Mips :: CIncOffsetImm ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( Mips :: CIncOffset ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } else if ( isInt < 16 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Opc = ABI . GetPtrAdduOp ( ) ; if ( Amount < 0 ) { Opc = ABI . GetPtrSubuOp ( ) ; Amount = - Amount ; } unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( Opc ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> static llvm :: Type * getVectorElementType ( llvm :: Type * Ty ) { return llvm :: cast < llvm :: FixedVectorType > ( Ty ) -> getElementType ( ) ; } </s>

Given a vector type , return the type of each element .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass ( createGlobalMergePass ( TM -> getTargetLowering ( ) ) ) ; return false ; } </s>


<s> static bool is_mem_ref ( rtx pat ) { const char * fmt ; int i , j ; bool ret = false ; if ( GET_CODE ( pat ) == MEM ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( pat ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( pat ) ) - 1 ; i >= 0 && ! ret ; i -- ) { if ( fmt [ i ] == 'e' ) ret |= is_mem_ref ( XEXP ( pat , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( pat , i ) - 1 ; j >= 0 ; j -- ) ret |= is_mem_ref ( XVECEXP ( pat , i , j ) ) ; } return ret ; } </s>


<s> void ARMJITInfo :: Initialize ( const MachineFunction & MF , bool isPIC ) { const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; ConstPoolId2AddrMap . resize ( AFI -> getNumPICLabels ( ) ) ; JumpTableId2AddrMap . resize ( AFI -> getNumJumpTables ( ) ) ; IsPIC = isPIC ; } </s>

This method must be called before any actual lowering is done .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
TM
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>


<s> static void force_into ( rtx value , rtx target ) { value = force_operand ( value , target ) ; if ( ! rtx_equal_p ( value , target ) ) emit_insn ( gen_move_insn ( target , value ) ) ; } </s>

Like force_operand , but guarantees that VALUE ends up in TARGET .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo , O ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>


<s> static unsigned arm_size_return_regs ( void ) { machine_mode mode ; if ( crtl -> return_rtx != 0 ) mode = GET_MODE ( crtl -> return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; return GET_MODE_SIZE ( mode ) ; } </s>

Calculate the size of the return value that is passed in registers .


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ Stack Align: May be called with mis-aligned SP.\n"

"\t%@ Non-secure entry function: called from non-secure code.\n"

"\t%@ args = %wd, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> rtx arm_gen_return_addr_mask ( void ) { rtx reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_return_addr_mask ( reg ) ) ; return reg ; } </s>

Generate a sequence of insns that will generate the correct return address mask depending on the physical architecture that the program is running on .


<s> static void aarch64_disqualify_components ( sbitmap , edge , sbitmap , bool ) { } </s>


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( doMergeWithPrevious && PI != MBB . begin ( ) && PI -> isCFIInstruction ( ) ) PI = std :: prev ( PI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = PI -> getOperand ( 2 ) . getImm ( ) ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset = PI -> getOperand ( 4 ) . getImm ( ) ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = - PI -> getOperand ( 2 ) . getImm ( ) ; } else return 0 ; PI = MBB . erase ( PI ) ; if ( PI != MBB . end ( ) && PI -> isCFIInstruction ( ) ) { auto CIs = MBB . getParent ( ) -> getFrameInstructions ( ) ; MCCFIInstruction CI = CIs [ PI -> getOperand ( 0 ) . getCFIIndex ( ) ] ; if ( CI . getOperation ( ) == MCCFIInstruction :: OpDefCfaOffset || CI . getOperation ( ) == MCCFIInstruction :: OpAdjustCfaOffset ) PI = MBB . erase ( PI ) ; } if ( ! doMergeWithPrevious ) MBBI = skipDebugInstructionsForward ( PI , MBB . end ( ) ) ; return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s>
MCSymbol
*
X86MCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
switch
(
MO
.
getTargetFlags
(
)
)
{
case
X86II
::
MO_DLLIMPORT
:
Name
+=
"__imp_"
;
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
Suffix
=
"$non_lazy_ptr"
;
break
;
}
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
)
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
break
;
}
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> static void pop ( int rn ) { rtx x , sp_reg , reg ; if ( rn == FPUL_REG ) x = gen_pop_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_pop_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , 0 , 0 ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( sp_reg , plus_constant ( SImode , sp_reg , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; } </s>

Output RTL to pop register RN from the stack .


<s> bool isImm ( ) const override { return Kind == Immediate || Kind == Expression ; } </s>


<s> bool X86FrameLowering :: stackProbeFunctionModifiesSP ( ) const { return STI . isOSWindows ( ) && ! STI . isTargetWin64 ( ) ; } </s>

Does the stack probe function call return with a modified stack pointer ?


<s> void X86DAGToDAGISel :: PostprocessISelDAG ( ) { if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; if ( N -> getMachineOpcode ( ) != TargetOpcode :: SUBREG_TO_REG ) continue ; unsigned SubRegIdx = N -> getConstantOperandVal ( 2 ) ; if ( SubRegIdx != X86 :: sub_xmm && SubRegIdx != X86 :: sub_ymm ) continue ; SDValue Move = N -> getOperand ( 1 ) ; if ( ! Move . isMachineOpcode ( ) ) continue ; switch ( Move . getMachineOpcode ( ) ) { default : continue ; case X86 :: VMOVAPDrr : case X86 :: VMOVUPDrr : case X86 :: VMOVAPSrr : case X86 :: VMOVUPSrr : case X86 :: VMOVDQArr : case X86 :: VMOVDQUrr : case X86 :: VMOVAPDYrr : case X86 :: VMOVUPDYrr : case X86 :: VMOVAPSYrr : case X86 :: VMOVUPSYrr : case X86 :: VMOVDQAYrr : case X86 :: VMOVDQUYrr : case X86 :: VMOVAPDZ128rr : case X86 :: VMOVUPDZ128rr : case X86 :: VMOVAPSZ128rr : case X86 :: VMOVUPSZ128rr : case X86 :: VMOVDQA32Z128rr : case X86 :: VMOVDQU32Z128rr : case X86 :: VMOVDQA64Z128rr : case X86 :: VMOVDQU64Z128rr : case X86 :: VMOVAPDZ256rr : case X86 :: VMOVUPDZ256rr : case X86 :: VMOVAPSZ256rr : case X86 :: VMOVUPSZ256rr : case X86 :: VMOVDQA32Z256rr : case X86 :: VMOVDQU32Z256rr : case X86 :: VMOVDQA64Z256rr : case X86 :: VMOVDQU64Z256rr : break ; } SDValue In = Move . getOperand ( 0 ) ; if ( ! In . isMachineOpcode ( ) || In . getMachineOpcode ( ) <= TargetOpcode :: GENERIC_OP_END ) continue ; uint64_t TSFlags = getInstrInfo ( ) -> get ( In . getMachineOpcode ( ) ) . TSFlags ; if ( ( TSFlags & X86II :: EncodingMask ) != X86II :: VEX && ( TSFlags & X86II :: EncodingMask ) != X86II :: EVEX && ( TSFlags & X86II :: EncodingMask ) != X86II :: XOP ) continue ; CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , In , N -> getOperand ( 2 ) ) ; if ( Move . getNode ( ) -> use_empty ( ) ) CurDAG -> RemoveDeadNode ( Move . getNode ( ) ) ; } } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> static char * rs6000_offload_options ( void ) { if ( TARGET_64BIT ) return xstrdup ( "-foffload-abi=lp64" ) ; else return xstrdup ( "-foffload-abi=ilp32" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


<s>
SDValue
MMIXTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

MMIX
MMIX
"unimplemented operand"
ISD::GlobalAddress
ISD::SELECT


<s> static rtx sparc_tls_got ( void ) { if ( flag_pic ) { crtl -> uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } if ( TARGET_SUN_TLS && TARGET_ARCH32 ) { load_got_register ( ) ; return global_offset_table_rtx ; } return copy_to_reg ( sparc_got ( ) ) ; } </s>

Return the Global Offset Table to be used in TLS mode .


<s>
static
bool
use_vfp_abi
(
enum
arm_pcs
pcs_variant
,
bool
is_double
)
{
if
(
pcs_variant
==
ARM_PCS_AAPCS_VFP
)
{
static
bool
seen_thumb1_vfp
=
false
;
if
(
TARGET_THUMB1
&&
!
seen_thumb1_vfp
)
{
sorry
(
"Thumb-1 %<hard-float%> VFP ABI"
)
;
seen_thumb1_vfp
=
true
;
}
return
true
;
}
if
(
pcs_variant
!=
ARM_PCS_AAPCS_LOCAL
)
return
false
;
return
(
TARGET_32BIT
&&
TARGET_HARD_FLOAT
&&
(
TARGET_VFP_DOUBLE
||
!
is_double
)
)
;
}
</s>

Return true if PCS_VARIANT should use VFP registers .


"PPC DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool fma_node :: root_p ( ) { return this -> m_root == this ; } </s>


<s> bool rx_is_restricted_memory_address ( rtx mem , machine_mode mode ) { if ( ! rx_is_legitimate_address ( mode , mem , reload_in_progress || reload_completed ) ) return false ; switch ( GET_CODE ( mem ) ) { case REG : return true ; case SUBREG : return RX_REG_P ( SUBREG_REG ( mem ) ) ; case PRE_DEC : case POST_INC : return false ; case PLUS : { rtx base , index ; base = XEXP ( mem , 0 ) ; index = XEXP ( mem , 1 ) ; if ( ! RX_REG_P ( base ) || ! CONST_INT_P ( index ) ) return false ; return IN_RANGE ( INTVAL ( index ) , 0 , ( 0x10000 * GET_MODE_SIZE ( mode ) ) - 1 ) ; } case SYMBOL_REF : return true ; default : gcc_unreachable ( ) ; } } </s>

Returns TRUE for simple memory addreses , ie ones that do not involve register indirect addressing or pre/post increment/decrement .


<s> bool reg_unused_after ( rtx reg , rtx_insn * insn ) { rtx set = single_set ( insn ) ; if ( set && ! MEM_P ( SET_DEST ( set ) ) && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return true ; while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( ! INSN_P ( insn ) ) continue ; rtx_code code = GET_CODE ( insn ) ; if ( code == CODE_LABEL ) return 1 ; if ( code == JUMP_INSN ) return false ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; bool retval = false ; for ( int i = 0 ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return false ; code = JUMP_INSN ; } if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return false ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) { if ( ! MEM_P ( SET_DEST ( set ) ) ) retval = true ; else return false ; } if ( set == NULL_RTX && reg_overlap_mentioned_p ( reg , PATTERN ( this_insn ) ) ) return false ; } if ( retval ) return true ; else if ( code == JUMP_INSN ) return false ; } rtx set = single_set ( insn ) ; if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return false ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return ! MEM_P ( SET_DEST ( set ) ) ; if ( set == NULL && reg_overlap_mentioned_p ( reg , PATTERN ( insn ) ) ) return false ; if ( code == CALL_INSN && call_used_regs [ REGNO ( reg ) ] ) return true ; } return true ; } </s>

Return nonzero if REG is not used after INSN . We assume REG is a reload reg , and therefore does not live past labels or calls or jumps .


<s> X86TargetMachine :: X86TargetMachine ( const Module & M , const std :: string & FS , bool is64Bit ) : Subtarget ( M , FS , is64Bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , Subtarget . getStackAlignment ( ) , Subtarget . is64Bit ( ) ? - 8 : - 4 ) , InstrInfo ( * this ) , JITInfo ( * this ) , TLInfo ( * this ) { DefRelocModel = getRelocationModel ( ) ; if ( getRelocationModel ( ) == Reloc :: Default ) { if ( Subtarget . isTargetDarwin ( ) || ( Subtarget . isTargetCygMing ( ) && ! Subtarget . isTargetWin64 ( ) ) ) setRelocationModel ( Reloc :: DynamicNoPIC ) ; else setRelocationModel ( Reloc :: Static ) ; } if ( Subtarget . isTargetELF ( ) && getRelocationModel ( ) == Reloc :: DynamicNoPIC ) setRelocationModel ( Reloc :: Static ) ; if ( Subtarget . is64Bit ( ) ) { if ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) setRelocationModel ( Reloc :: PIC_ ) ; if ( getCodeModel ( ) == CodeModel :: Default ) setCodeModel ( CodeModel :: Small ) ; } if ( Subtarget . isTargetCygMing ( ) ) Subtarget . setPICStyle ( PICStyles :: WinPIC ) ; else if ( Subtarget . isTargetDarwin ( ) ) { if ( Subtarget . is64Bit ( ) ) Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; else Subtarget . setPICStyle ( PICStyles :: Stub ) ; } else if ( Subtarget . isTargetELF ( ) ) { if ( Subtarget . is64Bit ( ) ) Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; else Subtarget . setPICStyle ( PICStyles :: GOT ) ; } } </s>


<s> int includes_rldic_lshift_p ( rtx shiftop , rtx andop ) { if ( GET_CODE ( andop ) == CONST_INT ) { unsigned HOST_WIDE_INT c , lsb , shift_mask ; c = INTVAL ( andop ) ; if ( c == 0 || c == HOST_WIDE_INT_M1U ) return 0 ; shift_mask = HOST_WIDE_INT_M1U ; shift_mask <<= INTVAL ( shiftop ) ; lsb = c & - c ; if ( - lsb != shift_mask ) return 0 ; c = ~ c ; c &= - lsb ; lsb = c & - c ; return c == - lsb ; } else return 0 ; } </s>

Return 1 if ANDOP is a mask suitable for use with an rldic insn to perform a left shift . It must have exactly SHIFTOP least significant 0 's , then one or more 1 's , then zero or more 0 's .


<s>
static
void
rs6000_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
rs6000_stack_t
*
info
=
rs6000_stack_info
(
)
;
if
(
TARGET_DEBUG_STACK
)
debug_stack_info
(
info
)
;
if
(
info
->
first_fp_reg_save
<
64
&&
!
FP_SAVE_INLINE
(
info
->
first_fp_reg_save
)
)
fprintf
(
file
,
"\t.extern %s%d%s\n\t.extern %s%d%s\n"
,
SAVE_FP_PREFIX
,
info
->
first_fp_reg_save
32
,
SAVE_FP_SUFFIX
,
RESTORE_FP_PREFIX
,
info
->
first_fp_reg_save
32
,
RESTORE_FP_SUFFIX
)
;
if
(
!
TARGET_POWER
&&
!
TARGET_POWERPC
&&
!
common_mode_defined
)
{
fputs
(
"\t.extern __mulh\n"
,
file
)
;
fputs
(
"\t.extern __mull\n"
,
file
)
;
fputs
(
"\t.extern __divss\n"
,
file
)
;
fputs
(
"\t.extern __divus\n"
,
file
)
;
fputs
(
"\t.extern __quoss\n"
,
file
)
;
fputs
(
"\t.extern __quous\n"
,
file
)
;
common_mode_defined
=
1
;
}
if
(
!
HAVE_prologue
)
{
start_sequence
(
)
;
emit_note
(
NOTE_INSN_DELETED
)
;
rs6000_emit_prologue
(
)
;
emit_note
(
NOTE_INSN_DELETED
)
;
{
rtx
insn
;
unsigned
addr
=
0
;
for
(
insn
=
get_insns
(
)
;
insn
!=
0
;
insn
=
NEXT_INSN
(
insn
)
)
{
INSN_ADDRESSES_NEW
(
insn
,
addr
)
;
addr
+=
4
;
}
}
if
(
TARGET_DEBUG_STACK
)
debug_rtx_list
(
get_insns
(
)
,
100
)
;
final
(
get_insns
(
)
,
file
,
FALSE
)
;
end_sequence
(
)
;
}
rs6000_pic_labelno
++
;
}
</s>


<s>
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> bool MipsAsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { MCOp = MCInstLowering . LowerOperand ( MO ) ; return MCOp . isValid ( ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> inline hashval_t bundle_state_hasher :: hash ( const value_type * state ) { unsigned result , i ; for ( result = i = 0 ; i < dfa_state_size ; i ++ ) result += ( ( ( unsigned char * ) state -> dfa_state ) [ i ] << ( ( i % CHAR_BIT ) * 3 + CHAR_BIT ) ) ; return result + state -> insn_num ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const ARMSubtarget & Subtarget = DAG . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget . isTargetNaCl ( ) || ! EnableARMAEABIFunctions || ! Subtarget . isAAPCS_ABI ( ) || Subtarget . isTargetMachO ( ) || Subtarget . isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> rtx i860_saveregs ( ) { rtx fn = gen_rtx_SYMBOL_REF ( Pmode , "__builtin_saveregs" ) ; rtx save = gen_reg_rtx ( Pmode ) ; rtx valreg = LIBCALL_VALUE ( Pmode ) ; rtx ret ; emit_move_insn ( save , valreg ) ; ret = emit_library_call_value ( fn , NULL_RTX , 1 , Pmode , 0 ) ; if ( GET_CODE ( ret ) != REG || REGNO ( ret ) < FIRST_PSEUDO_REGISTER ) ret = copy_to_reg ( ret ) ; emit_move_insn ( valreg , save ) ; return ret ; } </s>

Expand a library call to __builtin_saveregs .


<s> Sched :: Preference PPCTargetLowering :: getSchedulingPreference ( SDNode * N ) const { if ( DisableILPPref ) return TargetLowering :: getSchedulingPreference ( N ) ; return Sched :: ILP ; } </s>


<s> static unsigned int aarch64_case_values_threshold ( void ) { if ( optimize > 2 && selected_cpu -> tune -> max_case_values != 0 ) return selected_cpu -> tune -> max_case_values ; else return optimize_size ? default_case_values_threshold ( ) : 17 ; } </s>


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool ARMPassConfig :: addInstSelector ( ) { PM . add ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
unsigned
X86InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
X86
::
JMP_1
&&
X86
::
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
==
X86
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


"Instr doesn't have FrameIndex operand!"


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx aarch64_target_reg ( rtx target , machine_mode mode ) { if ( target && REG_P ( target ) && GET_MODE ( target ) == mode ) return target ; if ( ! can_create_pseudo_p ( ) ) { gcc_assert ( target ) ; return gen_lowpart ( mode , target ) ; } return gen_reg_rtx ( mode ) ; } </s>

Return TARGET if it is nonnull and a register of mode MODE . Otherwise , return a fresh register of mode MODE if we can , or TARGET reinterpreted as MODE if we ca n't .


<s> static int ix86_adjust_priority ( rtx_insn * insn , int priority ) { rtx set ; if ( reload_completed ) return priority ; if ( ! NONDEBUG_INSN_P ( insn ) ) return priority ; set = single_set ( insn ) ; if ( set ) { rtx tmp = SET_SRC ( set ) ; if ( REG_P ( tmp ) && HARD_REGISTER_P ( tmp ) && ! TEST_HARD_REG_BIT ( fixed_reg_set , REGNO ( tmp ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( tmp ) ) ) ) return current_sched_info -> sched_max_insns_priority ; } return priority ; } </s>

Hook for pre-reload schedule - set priority of moves from likely spilled HW registers to maximum , to schedule them at soon as possible . These are moves from function argument registers at the top of the function entry and moves from function return value registers after call .


<s> MachineMemOperand :: Flags AArch64TargetLowering :: getTargetMMOFlags ( const Instruction & I ) const { if ( Subtarget -> getProcFamily ( ) == AArch64Subtarget :: Falkor && I . getMetadata ( FALKOR_STRIDED_ACCESS_MD ) != nullptr ) return MOStridedAccess ; return MachineMemOperand :: MONone ; } </s>

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( TT . isOSDarwin ( ) || ReserveX18 ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . isPredicable ( ) ) return false ; if ( ( TID . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) { ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARMII::DomainMask ARMII::DomainNEON ARM ARM


<s> inline static rtx_insn * emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( VOIDmode , x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> SDValue SparcTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget -> is64Bit ( ) ) return LowerFormalArguments_64 ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ; return LowerFormalArguments_32 ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
static
void
som_output_text_section_asm_op
(
const
char
*
data
ATTRIBUTE_UNUSED
)
{
gcc_assert
(
TARGET_SOM
)
;
if
(
TARGET_GAS
)
{
if
(
cfun
&&
cfun
->
machine
&&
!
cfun
->
machine
->
in_nsubspa
)
{
cfun
->
machine
->
in_nsubspa
=
1
;
if
(
cfun
->
decl
&&
DECL_ONE_ONLY
(
cfun
->
decl
)
&&
!
DECL_WEAK
(
cfun
->
decl
)
)
{
output_section_asm_op
(
"\t.SPACE $TEXT$\n"
"\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
"ACCESS=44,SORT=24,COMDAT"
)
;
return
;
}
}
else
{
gcc_assert
(
!
cfun
||
!
cfun
->
machine
||
cfun
->
machine
->
in_nsubspa
==
2
)
;
in_section
=
;
}
output_section_asm_op
(
"\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$"
)
;
return
;
}
output_section_asm_op
(
"\t.SPACE $TEXT$\n\t.SUBSPA $CODE$"
)
;
}
</s>

A get_unnamed_section callback for switching to the text section . This function is only used with SOM . Because we do n't support named subspaces , we can only create a new subspace or switch back to the default text subspace .


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void iq2000_option_override ( void ) { target_flags &= ~ MASK_GPOPT ; iq2000_isa = IQ2000_ISA_DEFAULT ; iq2000_print_operand_punct [ '?' ] = 1 ; iq2000_print_operand_punct [ '#' ] = 1 ; iq2000_print_operand_punct [ '&' ] = 1 ; iq2000_print_operand_punct [ '!' ] = 1 ; iq2000_print_operand_punct [ '*' ] = 1 ; iq2000_print_operand_punct [ '@' ] = 1 ; iq2000_print_operand_punct [ '.' ] = 1 ; iq2000_print_operand_punct [ '(' ] = 1 ; iq2000_print_operand_punct [ ')' ] = 1 ; iq2000_print_operand_punct [ '[' ] = 1 ; iq2000_print_operand_punct [ ']' ] = 1 ; iq2000_print_operand_punct [ '<' ] = 1 ; iq2000_print_operand_punct [ '>' ] = 1 ; iq2000_print_operand_punct [ '{' ] = 1 ; iq2000_print_operand_punct [ '}' ] = 1 ; iq2000_print_operand_punct [ '^' ] = 1 ; iq2000_print_operand_punct [ '$' ] = 1 ; iq2000_print_operand_punct [ '+' ] = 1 ; iq2000_print_operand_punct [ '~' ] = 1 ; gpr_mode = SImode ; init_machine_status = iq2000_init_machine_status ; } </s>


<s> Register LanaiRegisterInfo :: getFrameRegister ( const MachineFunction & ) const { return Lanai :: FP ; } </s>


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


runOnMachineFunction - Emit the function body .


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ; int fp_reg_size = 8 ; int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> bool hasReservedCallFrame ( MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static bool offsettable_ok_by_alignment ( rtx op , HOST_WIDE_INT offset , machine_mode mode ) { tree decl ; unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( ! SYMBOL_REF_P ( op ) ) return false ; if ( mode_supports_dq_form ( mode ) ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == 0 ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == 0 ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > 32768 ) return false ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; return dalign >= dsize ; } } else gcc_unreachable ( ) ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; mask = dalign - 1 ; lsb = offset & - offset ; mask &= lsb - 1 ; dalign = mask + 1 ; return dalign >= dsize ; } </s>

Return true if a MODE sized memory accesses to OP plus OFFSET is known to not straddle a 32k boundary .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; addPass ( UnpackMachineBundlesID ) ; } PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
arm_output_multireg_pop
(
rtx
*
operands
,
bool
return_pc
,
rtx
cond
,
bool
reverse
,
bool
update
)
{
int
i
;
char
pattern
[
100
]
;
int
offset
;
const
char
*
conditional
;
int
num_saves
=
XVECLEN
(
operands
[
0
]
,
0
)
;
unsigned
int
regno
;
unsigned
int
regno_base
=
REGNO
(
operands
[
1
]
)
;
offset
=
0
;
offset
+=
update
1
:
0
;
offset
+=
return_pc
1
:
0
;
for
(
i
=
offset
;
i
<
num_saves
;
i
++
)
{
regno
=
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
;
gcc_assert
(
(
regno
!=
SP_REGNUM
)
||
(
regno_base
==
SP_REGNUM
)
)
;
if
(
regno
==
regno_base
)
gcc_assert
(
!
update
)
;
}
conditional
=
reverse
"%?%D0"
:
"%?%d0"
;
if
(
(
regno_base
==
SP_REGNUM
)
&&
TARGET_UNIFIED_ASM
)
{
gcc_assert
(
update
)
;
sprintf
(
pattern
,
"pop%s\t{"
,
conditional
)
;
}
else
{
if
(
regno_base
==
SP_REGNUM
)
sprintf
(
pattern
,
"ldm%sfd\t"
,
conditional
)
;
else
if
(
TARGET_UNIFIED_ASM
)
sprintf
(
pattern
,
"ldmia%s\t"
,
conditional
)
;
else
sprintf
(
pattern
,
"ldm%sia\t"
,
conditional
)
;
strcat
(
pattern
,
reg_names
[
regno_base
]
)
;
if
(
update
)
strcat
(
pattern
,
"!, {"
)
;
else
strcat
(
pattern
,
", {"
)
;
}
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
offset
)
,
0
)
)
]
)
;
for
(
i
=
offset
+
1
;
i
<
num_saves
;
i
++
)
{
strcat
(
pattern
,
", "
)
;
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
]
)
;
}
strcat
(
pattern
,
"}"
)
;
if
(
IS_INTERRUPT
(
arm_current_func_type
(
)
)
&&
return_pc
)
strcat
(
pattern
,
"^"
)
;
output_asm_insn
(
pattern
,
&
cond
)
;
}
</s>

OPERANDS [ 0 ] is the entire list of insns that constitute pop , OPERANDS [ 1 ] is the base register , RETURN_PC is true iff return insn is in the list , UPDATE is true iff the list contains explicit update of base register .


<s> uint64_t PPCFrameLowering :: getTOCSaveOffset ( ) const { return TOCSaveOffset ; } </s>

getTOCSaveOffset - Return the previous frame offset to save the TOC register � ? 64-bit SVR4 ABI only .


<s> void ix86_expand_convert_uns_sixf_sse ( rtx , rtx ) { gcc_unreachable ( ) ; } </s>

Not used , but eases macroization of patterns .


<s> static void ia64_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = ia64_function_arg_words ( type , mode ) ; int offset = ia64_function_arg_offset ( cum , type , words ) ; machine_mode hfa_mode = VOIDmode ; if ( cum -> words >= MAX_ARGUMENT_SLOTS ) { cum -> words += words + offset ; return ; } cum -> atypes [ cum -> words ] = ia64_arg_type ( mode ) ; cum -> words += words + offset ; if ( TARGET_ABI_OPEN_VMS ) { cum -> int_regs = cum -> words ; cum -> fp_regs = cum -> words ; return ; } if ( type ) hfa_mode = hfa_element_mode ( type , 0 ) ; if ( hfa_mode != VOIDmode && ( ! cum -> prototype || named ) ) { int fp_regs = cum -> fp_regs ; int int_regs = cum -> words - words ; int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; int byte_size ; int args_byte_size ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; args_byte_size = int_regs * UNITS_PER_WORD ; offset = 0 ; for ( ; ( offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS && args_byte_size < ( MAX_ARGUMENT_SLOTS * UNITS_PER_WORD ) ) ; ) { offset += hfa_size ; args_byte_size += hfa_size ; fp_regs ++ ; } cum -> fp_regs = fp_regs ; } else if ( mode == TFmode || mode == TCmode || ( ! FLOAT_MODE_P ( mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) ) cum -> int_regs = cum -> words ; else if ( cum -> prototype ) { if ( ! named ) cum -> int_regs = cum -> words ; else cum -> fp_regs += ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ? 2 : 1 ) ; } else { cum -> fp_regs += ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ? 2 : 1 ) ; cum -> int_regs = cum -> words ; } } </s>

Update CUM to point after this argument . This is patterned after ia64_function_arg .


<s> static void xstormy16_asm_out_destructor ( rtx symbol , int priority ) { const char * section = ".dtors" ; char buf [ 18 ] ; if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , ".dtors.%.5u" , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , 0 , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , POINTER_SIZE , 1 ) ; } </s>

Output constructors and destructors . Just like default_named_section_asm_out_ * but do n't set the sections writable .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; isA9 = STI -> isCortexA9 ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= ExpandFPMLxInstructions ( MBB ) ; } return Modified ; } </s>


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for LDP immediate"


<s> void ARMTargetAsmStreamer :: emitInst ( uint32_t Inst , char Suffix ) { OS << "\t.inst" ; if ( Suffix ) OS << "." << Suffix ; OS << "\t0x" << utohexstr ( Inst ) << "\n" ; } </s>

Callback used to implement the .inst directive .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
uint64_t
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
MipsMnemonicSpellCheck
(
Name
,
FBS
)
;
return
Error
(
NameLoc
,
"unknown instruction"
+
Suggestion
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
Mips
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"