<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = getDataLayout ( ) . getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; if ( MMI ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; if ( MAI -> doesSupportExceptionHandling ( ) ) { for ( const Function * Personality : MMI -> getPersonalities ( ) ) { if ( Personality ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( Personality , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( Personality ) , true ) ; } } } MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void LC3InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LC3 :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall2 ( Strex , Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr ) ; } </s>

Perform a store-conditional operation to Addr .


<s>
const
char
*
ix86_output_indirect_function_return
(
rtx
ret_op
)
{
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_keep
)
{
char
thunk_name
[
32
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
unsigned
int
regno
=
REGNO
(
ret_op
)
;
gcc_assert
(
regno
==
CX_REG
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_thunk_inline
)
{
bool
need_thunk
=
(
cfun
->
machine
->
function_return_type
==
indirect_branch_thunk
)
;
indirect_thunk_name
(
thunk_name
,
regno
,
need_prefix
,
true
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
{
if
(
need_thunk
)
{
indirect_return_via_cx_bnd
=
true
;
indirect_thunks_bnd_used
|=
1
<<
CX_REG
;
}
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
}
else
{
if
(
need_thunk
)
{
indirect_return_via_cx
=
true
;
indirect_thunks_used
|=
1
<<
CX_REG
;
}
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
return
""
;
}
else
return
"%!jmp\t%A0"
;
}
</s>

Output indirect function return . RET_OP is the function return target .


<s> bool addInstSelector ( ) override { addPass ( createUPTISelDag ( getUPTTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool Thumb1InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> int nds32_adjust_insn_length ( rtx_insn * insn , int length ) { rtx src , dst ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_move_df : case CODE_FOR_move_di : src = XEXP ( PATTERN ( insn ) , 1 ) ; dst = XEXP ( PATTERN ( insn ) , 0 ) ; if ( REG_P ( src ) && REG_P ( dst ) && ( REGNO ( src ) % 2 ) == 0 && ( REGNO ( dst ) % 2 ) == 0 ) length = 2 ; break ; default : break ; } return length ; } </s>

Computing the Length of an Insn . Modifies the length assigned to instruction INSN . LEN is the initially computed length of the insn .


<s> rtx loongarch_strip_unspec_address ( rtx op ) { rtx base , offset ; split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op ; } </s>

If OP is an UNSPEC address , return the address to which it refers , otherwise return OP itself .


<s> void LC3InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LC3 :: ADDrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( 0 ) ; } </s>


<s> bool aarch64_float_const_rtx_p ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; if ( mode == VOIDmode ) return false ; unsigned HOST_WIDE_INT ival ; if ( GET_CODE ( x ) == CONST_DOUBLE && SCALAR_FLOAT_MODE_P ( mode ) && aarch64_reinterpret_float_as_int ( x , & ival ) ) { scalar_int_mode imode = ( mode == HFmode ? SImode : int_mode_for_mode ( mode ) . require ( ) ) ; int num_instr = aarch64_internal_mov_immediate ( NULL_RTX , gen_int_mode ( ival , imode ) , false , imode ) ; return num_instr < 3 ; } return false ; } </s>

Return TRUE if rtx X is an immediate constant that can be moved using a single MOV ( +MOVK ) followed by an FMOV .


<s> void SHUXIInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << StringRef ( getRegisterName ( RegNo ) ) ; } </s>


"rs6000_secondary_memory_needed, return: %s, from_class = %s, "

Debug version of rs6000_secondary_memory_needed .


<s> MVT X86TargetLowering :: hasFastEqualityCompare ( unsigned NumBits ) const { MVT VT = MVT :: getIntegerVT ( NumBits ) ; if ( isTypeLegal ( VT ) ) return VT ; if ( NumBits == 128 && isTypeLegal ( MVT :: v16i8 ) ) return MVT :: v16i8 ; if ( NumBits == 256 && isTypeLegal ( MVT :: v32i8 ) ) return MVT :: v32i8 ; return MVT :: INVALID_SIMPLE_VALUE_TYPE ; } </s>

Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST .


<s> unsigned getNumFixupKinds ( ) const override { return OR1K :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> virtual unsigned int execute ( function * fun ) { return rs6000_analyze_swaps ( fun ) ; } </s>


<s>
static
void
complete_base_type
(
typeinfo
*
typeptr
,
char
*
buf
,
int
*
bufi
)
{
switch
(
typeptr
->
base
)
{
case
BT_CHAR
:
memcpy
(
&
buf
[
*
bufi
]
,
"qi"
,
2
)
;
break
;
case
BT_SHORT
:
memcpy
(
&
buf
[
*
bufi
]
,
"hi"
,
2
)
;
break
;
case
BT_INT
:
memcpy
(
&
buf
[
*
bufi
]
,
"si"
,
2
)
;
break
;
case
BT_LONG
:
memcpy
(
&
buf
[
*
bufi
]
,
"lg"
,
2
)
;
break
;
case
BT_LONGLONG
:
memcpy
(
&
buf
[
*
bufi
]
,
"di"
,
2
)
;
break
;
case
BT_FLOAT
:
memcpy
(
&
buf
[
*
bufi
]
,
"sf"
,
2
)
;
break
;
case
BT_DOUBLE
:
memcpy
(
&
buf
[
*
bufi
]
,
"df"
,
2
)
;
break
;
case
BT_LONGDOUBLE
:
memcpy
(
&
buf
[
*
bufi
]
,
"ld"
,
2
)
;
break
;
case
BT_INT128
:
memcpy
(
&
buf
[
*
bufi
]
,
"ti"
,
2
)
;
break
;
case
BT_FLOAT128
:
memcpy
(
&
buf
[
*
bufi
]
,
"tf"
,
2
)
;
break
;
case
BT_BOOL
:
memcpy
(
&
buf
[
*
bufi
]
,
"bi"
,
2
)
;
break
;
case
BT_STRING
:
memcpy
(
&
buf
[
*
bufi
]
,
"st"
,
2
)
;
break
;
case
BT_DECIMAL32
:
memcpy
(
&
buf
[
*
bufi
]
,
"sd"
,
2
)
;
break
;
case
BT_DECIMAL64
:
memcpy
(
&
buf
[
*
bufi
]
,
"dd"
,
2
)
;
break
;
case
BT_DECIMAL128
:
memcpy
(
&
buf
[
*
bufi
]
,
"td"
,
2
)
;
break
;
case
BT_IBM128
:
memcpy
(
&
buf
[
*
bufi
]
,
"if"
,
2
)
;
break
;
default
:
diag
(
pos
,
"unhandled basetype %d.\n"
,
typeptr
->
base
)
;
exit
(
1
)
;
}
*
bufi
+=
2
;
}
</s>

Convert a base type into a mode string .


<s> static rtx adjacent_mem_locations ( rtx mem1 , rtx mem2 ) { rtx reg1 , reg2 ; HOST_WIDE_INT off1 , size1 , off2 , size2 ; if ( MEM_P ( mem1 ) && MEM_P ( mem2 ) && get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) && REGNO ( reg1 ) == REGNO ( reg2 ) ) { if ( off1 + size1 == off2 ) return mem1 ; else if ( off2 + size2 == off1 ) return mem2 ; } return NULL_RTX ; } </s>

If the target storage locations of arguments MEM1 and MEM2 are adjacent , then return the argument that has the lower address . Otherwise , return NULL_RTX .


"local variable memory requirements exceed capacity"

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling . Also any insns generated here should have RTX_FRAME_RELATED_P ( insn ) = 1 so that the debug info generation code can handle them properly .


<s> void LanaiAsmBackend :: applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool , MCContext & ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void ix86_avx256_split_vector_move_misalign ( rtx op0 , rtx op1 ) { rtx m ; rtx ( * extract ) ( rtx , rtx , rtx ) ; rtx ( * load_unaligned ) ( rtx , rtx ) ; rtx ( * store_unaligned ) ( rtx , rtx ) ; machine_mode mode ; switch ( GET_MODE ( op0 ) ) { default : gcc_unreachable ( ) ; case V32QImode : extract = gen_avx_vextractf128v32qi ; load_unaligned = gen_avx_loaddquv32qi ; store_unaligned = gen_avx_storedquv32qi ; mode = V16QImode ; break ; case V8SFmode : extract = gen_avx_vextractf128v8sf ; load_unaligned = gen_avx_loadups256 ; store_unaligned = gen_avx_storeups256 ; mode = V4SFmode ; break ; case V4DFmode : extract = gen_avx_vextractf128v4df ; load_unaligned = gen_avx_loadupd256 ; store_unaligned = gen_avx_storeupd256 ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_LOAD && optimize_insn_for_speed_p ( ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , 0 ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , 16 ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( misaligned_operand ( op1 , GET_MODE ( op1 ) ) ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , op1 ) ) ; else emit_insn ( load_unaligned ( op0 , op1 ) ) ; } else if ( MEM_P ( op0 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_STORE && optimize_insn_for_speed_p ( ) ) { m = adjust_address ( op0 , mode , 0 ) ; emit_insn ( extract ( m , op1 , const0_rtx ) ) ; m = adjust_address ( op0 , mode , 16 ) ; emit_insn ( extract ( m , op1 , const1_rtx ) ) ; } else emit_insn ( store_unaligned ( op0 , op1 ) ) ; } else gcc_unreachable ( ) ; } </s>

Split 32-byte AVX unaligned load and store if needed .


"PowerPC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( NumBytes - i - 1 ) * 8 ) ) & 0xff ) ; } </s>


<s> static bool rs6000_expand_vec_perm_const_1 ( rtx target , rtx op0 , rtx op1 , unsigned char perm0 , unsigned char perm1 ) { rtx x ; if ( ( perm0 & 2 ) == ( perm1 & 2 ) ) { if ( perm0 & 2 ) op0 = op1 ; else op1 = op0 ; } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & 1 ; perm1 = ( perm1 & 1 ) + 2 ; } else if ( perm0 & 2 ) { if ( perm1 & 2 ) return false ; perm0 -= 2 ; perm1 += 2 ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & 2 ) == 0 ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == 2 ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , 4 ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( 2 , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } return true ; } </s>

Expand a Paired Single or VSX Permute Doubleword constant permutation . Return true if we match an efficient implementation .


<s>
static
void
vax_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
)
{
int
regno
;
int
mask
=
0
;
for
(
regno
=
0
;
regno
<
FIRST_PSEUDO_REGISTER
;
regno
++
)
if
(
regs_ever_live
[
regno
]
&&
!
call_used_regs
[
regno
]
)
mask
|=
1
<<
regno
;
fprintf
(
file
,
"\t.word 0x%x\n"
,
mask
)
;
if
(
dwarf2out_do_frame
(
)
)
{
const
char
*
label
=
dwarf2out_cfi_label
(
)
;
int
offset
=
0
;
for
(
regno
=
FIRST_PSEUDO_REGISTER
1
;
regno
>=
0
;
regno
)
if
(
regs_ever_live
[
regno
]
&&
!
call_used_regs
[
regno
]
)
dwarf2out_reg_save
(
label
,
regno
,
offset
-=
4
)
;
dwarf2out_reg_save
(
label
,
PC_REGNUM
,
offset
-=
4
)
;
dwarf2out_reg_save
(
label
,
FRAME_POINTER_REGNUM
,
offset
-=
4
)
;
dwarf2out_reg_save
(
label
,
ARG_POINTER_REGNUM
,
offset
-=
4
)
;
dwarf2out_def_cfa
(
label
,
FRAME_POINTER_REGNUM
,
(
offset
4
)
)
;
}
size
-=
STARTING_FRAME_OFFSET
;
if
(
size
>=
64
)
asm_fprintf
(
file
,
"\tmovab %wd(%Rsp),%Rsp\n"
,
size
)
;
else
if
(
size
)
asm_fprintf
(
file
,
"\tsubl2 $%wd,%Rsp\n"
,
size
)
;
}
</s>

Generate the assembly code for function entry . FILE is a stdio stream to output the code to . SIZE is an int : how many units of temporary storage to allocate . Refer to the array ` regs_ever_live ' to determine which registers to save ; ` regs_ever_live [ I ] ' is nonzero if register number I is ever used in the function . This function is responsible for knowing which registers should not be saved even if used .


<s> static bool ia64_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; unsigned char perm [ MAX_VECT_LEN ] ; unsigned int i , nelt , which ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = ! target ; gcc_assert ( sel . length ( ) == nelt ) ; gcc_checking_assert ( sizeof ( d . perm ) == sizeof ( perm ) ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { unsigned int ei = sel [ i ] & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; d . perm [ i ] = ei ; perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case 3 : if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) { d . one_operand_p = false ; break ; } for ( i = 0 ; i < nelt ; ++ i ) if ( d . perm [ i ] >= nelt ) d . perm [ i ] -= nelt ; case 1 : d . op1 = d . op0 ; d . one_operand_p = true ; break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . op0 = d . op1 ; d . one_operand_p = true ; break ; } if ( d . testing_p ) { d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_operand_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; bool ret = ia64_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } if ( ia64_expand_vec_perm_const_1 ( & d ) ) return true ; if ( which == 3 && d . one_operand_p ) { memcpy ( d . perm , perm , sizeof ( perm ) ) ; d . one_operand_p = false ; return ia64_expand_vec_perm_const_1 ( & d ) ; } return false ; } </s>


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return SP :: I1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( ! STI . getFeatureBits ( ) [ X86 :: FeatureNOPL ] ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> write8 ( 0x90 ) ; return true ; } uint64_t MaxNopLength = 10 ; if ( STI . getFeatureBits ( ) [ X86 :: ProcIntelSLM ] ) MaxNopLength = 7 ; else if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast15ByteNOP ] ) MaxNopLength = 15 ; else if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast11ByteNOP ] ) MaxNopLength = 11 ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> unsigned ARMFastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with one register operand and a result register in the given register class .


"operation not permitted on type %<bfloat16_t%>"

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == ARM :: t2LoopEndDec || MI -> getOpcode ( ) == ARM :: t2DoLoopStartTP || MI -> getOpcode ( ) == ARM :: t2WhileLoopStartLR || MI -> getOpcode ( ) == ARM :: t2WhileLoopStartTP ; } </s>

Return true if the given terminator MI is not expected to spill .


<s> unsigned LC3RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return LC3 :: SP ; } </s>


<s>
unsigned
X86TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"esp"
,
X86
::
ESP
)
.
Case
(
"rsp"
,
X86
::
RSP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> const CAHPRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> HOST_WIDE_INT ia64_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; ia64_compute_frame_size ( get_frame_size ( ) ) ; switch ( from ) { case FRAME_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : offset = - current_frame_info . total_size ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) offset += 16 + crtl -> outgoing_args_size ; break ; case STACK_POINTER_REGNUM : offset = 0 ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) offset += 16 + crtl -> outgoing_args_size ; break ; default : gcc_unreachable ( ) ; } break ; case ARG_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : offset = 16 - crtl -> args . pretend_args_size ; break ; case STACK_POINTER_REGNUM : offset = ( current_frame_info . total_size + 16 - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } return offset ; } </s>

Compute the initial difference between the specified pair of registers .


<s> static int ix86_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( ix86_save_reg ( regno , true ) ) nregs ++ ; return nregs ; } </s>

Return number of registers to be saved on the stack .


<s> static void ix86_conditional_register_usage ( void ) { int i , c_mask ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } c_mask = CALL_USED_REGISTERS_MASK ( TARGET_64BIT_MS_ABI ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_SSE ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) SSE_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) FLOAT_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } if ( ! TARGET_MPX ) for ( i = FIRST_BND_REG ; i <= LAST_BND_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } </s>

Update register usage after having seen the compiler flags .


<s> const X86TargetMachine * getTargetMachine ( ) const { return static_cast < const X86TargetMachine * > ( & TM ) ; } </s>

Return the target machine ( if available ) .


<s> void aarch64_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 ; rtx any_const = NULL_RTX ; rtx v0 = XVECEXP ( vals , 0 , 0 ) ; bool all_same = true ; for ( int i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) ) ++ n_var ; else any_const = x ; all_same &= rtx_equal_p ( x , v0 ) ; } if ( n_var == 0 ) { rtx constant = aarch64_simd_make_constant ( vals ) ; if ( constant != NULL_RTX ) { emit_move_insn ( target , constant ) ; return ; } } if ( all_same ) { rtx x = copy_to_mode_reg ( inner_mode , v0 ) ; aarch64_emit_move ( target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ; return ; } if ( n_var != n_elts ) { rtx copy = copy_rtx ( vals ) ; for ( int i = 0 ; i < n_elts ; i ++ ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) continue ; rtx subst = any_const ; for ( int bit = n_elts / 2 ; bit > 0 ; bit /= 2 ) { rtx test = XVECEXP ( copy , 0 , i ^ bit ) ; if ( CONST_INT_P ( test ) || CONST_DOUBLE_P ( test ) ) { subst = test ; break ; } } XVECEXP ( copy , 0 , i ) = subst ; } aarch64_expand_vector_init ( target , copy ) ; } enum insn_code icode = optab_handler ( vec_set_optab , mode ) ; gcc_assert ( icode != CODE_FOR_nothing ) ; for ( int i = 0 ; i < n_elts ; i ++ ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) continue ; x = copy_to_mode_reg ( inner_mode , x ) ; emit_insn ( GEN_FCN ( icode ) ( target , x , GEN_INT ( i ) ) ) ; } } </s>

Expand a vector initialisation sequence , such that TARGET is initialised to contain VALS .


<s>
MCSymbol
*
ARMMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
assert
(
0
&&
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .


<s> void AArch64RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII -> get ( AArch64 :: ADDXri ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , 0 , this , MF ) ) ; unsigned Shifter = AArch64_AM :: getShifterImm ( AArch64_AM :: LSL , 0 ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const override { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= 64 ) ; return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s>
static
void
add_sve_type_attribute
(
tree
type
,
unsigned
int
num_zr
,
unsigned
int
num_pr
,
const
char
*
mangled_name
)
{
tree
mangled_name_tree
=
(
mangled_name
get_identifier
(
mangled_name
)
:
NULL_TREE
)
;
tree
value
=
tree_cons
(
NULL_TREE
,
mangled_name_tree
,
NULL_TREE
)
;
value
=
tree_cons
(
NULL_TREE
,
size_int
(
num_pr
)
,
value
)
;
value
=
tree_cons
(
NULL_TREE
,
size_int
(
num_zr
)
,
value
)
;
TYPE_ATTRIBUTES
(
type
)
=
tree_cons
(
get_identifier
(
"SVE type"
)
,
value
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

Record that TYPE is an ABI-defined SVE type that contains NUM_ZR SVE vectors and NUM_PR SVE predicates . MANGLED_NAME , if nonnull , is the ABI-defined mangling of the type . ACLE_NAME is the < arm_sve.h > name of the type .


<s> static void mep_jmp_return_reorg ( rtx_insn * insns ) { rtx_insn * insn , * label , * ret ; int ret_code ; for ( insn = insns ; insn ; insn = NEXT_INSN ( insn ) ) if ( simplejump_p ( insn ) ) { label = ret = safe_as_a < rtx_insn * > ( JUMP_LABEL ( insn ) ) ; while ( ret && ( NOTE_P ( ret ) || LABEL_P ( ret ) || GET_CODE ( PATTERN ( ret ) ) == USE ) ) ret = NEXT_INSN ( ret ) ; if ( ret ) { ret_code = recog_memoized ( ret ) ; if ( ret_code == CODE_FOR_return_internal || ret_code == CODE_FOR_eh_return_internal ) { LABEL_NUSES ( label ) -- ; if ( LABEL_NUSES ( label ) == 0 ) delete_insn ( label ) ; PATTERN ( insn ) = copy_rtx ( PATTERN ( ret ) ) ; INSN_CODE ( insn ) = - 1 ; } } } } </s>

Replace a jump to a return , with a copy of the return . GCC does n't always do this on its own .


<s>
void
ARMConstantPoolValue
::
dump
(
)
const
{
cerr
<<
"  "
<<
*
this
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> static bool rs6000_vector_alignment_reachable ( const_tree type ATTRIBUTE_UNUSED , bool is_packed ) { if ( is_packed ) return false ; if ( TARGET_32BIT ) { if ( rs6000_alignment_flags == MASK_ALIGN_NATURAL ) return true ; if ( rs6000_alignment_flags == MASK_ALIGN_POWER ) return true ; return false ; } else { if ( TARGET_MACHO ) return false ; return true ; } } </s>

Return true iff , data reference of TYPE can reach vector alignment ( 16 ) after applying N number of iterations . This routine does not determine how may iterations are required to reach desired alignment .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; CallingConv :: ID CalleeCC = CI -> getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAtLeastAcquire ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new ARMFastISel ( funcInfo , libInfo ) ; } return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> void mips_final_prescan_insn ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( mips_need_noat_wrapper_p ( insn , opvec , noperands ) ) mips_push_asm_switch ( & mips_noat ) ; } </s>


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" PPC


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Constant Islands"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS ( ) ) { addPass ( new ReplaceFMULS ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> detectRoundChange ( ) ) { addPass ( new DetectRoundChange ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( getSparcTargetMachine ( ) ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; return val > - 256 && val < 256 && ( val & 3 ) == 0 ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const ARMBaseInstrInfo & TII , int NumBytes , ARMCC :: CondCodes Pred = ARMCC :: AL , unsigned PredReg = 0 ) { if ( isARM ) emitARMRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARMCC::CondCodes ARMCC::AL 0 ARM ARM ARM::SP ARM::SP ARM::SP ARM::SP


<s> StringRef getPassName ( ) const override { return X86_REGISTER_ALLOCATOR_PASS_NAME ; } </s>


<s> bool ix86_expand_strlen ( rtx out , rtx src , rtx eoschar , rtx align ) { if ( TARGET_UNROLL_STRLEN && TARGET_INLINE_ALL_STRINGOPS && eoschar == const0_rtx && optimize > 1 ) { rtx addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; emit_insn ( gen_sub2_insn ( out , addr ) ) ; return true ; } else return false ; } </s>


<s> bool PPCInstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; case PPC :: MULHD : case PPC :: MULLD : case PPC :: MULHW : case PPC :: MULLW : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::MULHD PPC::MULLD PPC::MULHW PPC::MULLW


<s> void Note ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Note ( L , Msg , Ranges ) ; } </s>

Emit a note at the location L , with the message Msg .


<s> MachineInstr & ARMBaseInstrInfo :: duplicate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const MachineInstr & Orig ) const { MachineInstr & Cloned = TargetInstrInfo :: duplicate ( MBB , InsertBefore , Orig ) ; MachineBasicBlock :: instr_iterator I = Cloned . getIterator ( ) ; for ( ; ; ) { switch ( I -> getOpcode ( ) ) { case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = I -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; I -> getOperand ( 1 ) . setIndex ( CPI ) ; I -> getOperand ( 2 ) . setImm ( PCLabelId ) ; break ; } } if ( ! I -> isBundledWithSucc ( ) ) break ; ++ I ; } return Cloned ; } </s>

Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore .


<s> static void loongarch_adjust_block_mem ( rtx mem , HOST_WIDE_INT length , rtx * loop_reg , rtx * loop_mem ) { * loop_reg = copy_addr_to_reg ( XEXP ( mem , 0 ) ) ; * loop_mem = change_address ( mem , BLKmode , * loop_reg ) ; set_mem_align ( * loop_mem , MIN ( MEM_ALIGN ( mem ) , length * BITS_PER_UNIT ) ) ; } </s>

Helper function for doing a loop-based block operation on memory reference MEM . Each iteration of the loop will operate on LENGTH bytes of MEM . Create a new base register for use within the loop and point it to the start of MEM . Create a new memory reference that uses this register . Store them in * LOOP_REG and * LOOP_MEM respectively .


<s> static int rs6000_emit_p9_fp_minmax ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return 0 ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return 0 ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) ) max_p = ! max_p ; else return 0 ; rs6000_emit_minmax ( dest , max_p ? SMAX : SMIN , op0 , op1 ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s> static bool mips_rewrite_small_data_p ( rtx x , enum mips_symbol_context context ) { enum mips_symbol_type symbol_type ; return ( mips_lo_relocs [ SYMBOL_GP_RELATIVE ] && ! mips_split_p [ SYMBOL_GP_RELATIVE ] && mips_symbolic_constant_p ( x , context , & symbol_type ) && symbol_type == SYMBOL_GP_RELATIVE ) ; } </s>

Return true if X is a small data address that can be rewritten as a LO_SUM .


<s> bool DCPU16Peephole :: runOnMachineFunction ( MachineFunction & MF ) { QII = static_cast < const DCPU16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; QRI = static_cast < const DCPU16RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; if ( DisableDCPU16Peephole ) return false ; for ( MachineFunction :: iterator mbbIter = MF . begin ( ) ; mbbIter != MF . end ( ) ; ++ mbbIter ) { MachineBasicBlock * mbb = mbbIter ; if ( ! DisableOptBrcc ) runOptBrcc ( mbb ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int thumb1_base_register_rtx_p ( rtx x , machine_mode mode , int strict_p ) { int regno ; if ( ! REG_P ( x ) ) return 0 ; regno = REGNO ( x ) ; if ( strict_p ) return THUMB1_REGNO_MODE_OK_FOR_BASE_P ( regno , mode ) ; return ( regno <= LAST_LO_REGNUM || regno > LAST_VIRTUAL_REGISTER || regno == FRAME_POINTER_REGNUM || ( GET_MODE_SIZE ( mode ) >= 4 && ( regno == STACK_POINTER_REGNUM || regno >= FIRST_PSEUDO_REGISTER || x == hard_frame_pointer_rtx || x == arg_pointer_rtx ) ) ) ; } </s>

Return nonzero if X is valid as a 16-bit Thumb state base register .


<s> bool SystemZRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator SaveMBBI , MachineBasicBlock :: iterator & UseMBBI , const TargetRegisterClass * RC , unsigned Reg ) const { MachineFunction & MF = * MBB . getParent ( ) ; const SystemZFrameLowering * TFI = static_cast < const SystemZFrameLowering * > ( TM . getFrameLowering ( ) ) ; unsigned Base = getFrameRegister ( MF ) ; uint64_t Offset = TFI -> getEmergencySpillSlotOffset ( MF ) ; DebugLoc DL ; unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( 0 ) ; BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base ) . addImm ( Offset ) . addReg ( 0 ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> static bool mayAlias ( MachineInstr & MIa , SmallVectorImpl < MachineInstr * > & MemInsns , AliasAnalysis * AA ) { for ( MachineInstr * MIb : MemInsns ) if ( MIa . mayAlias ( AA , * MIb , false ) ) return true ; return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


<s> bool aarch64_simd_mem_operand_p ( rtx op ) { return MEM_P ( op ) && ( GET_CODE ( XEXP ( op , 0 ) ) == POST_INC || REG_P ( XEXP ( op , 0 ) ) ) ; } </s>

Return TRUE if OP is a valid vector addressing mode .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: GPR32RegClassID : case Mips :: GPR64RegClassID : case Mips :: DSPRRegClassID : { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 32 ; case Mips :: AFGR64RegClassID : return 16 ; case Mips :: FGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> static rtx sparc_function_value_1 ( const_tree type , machine_mode mode , bool outgoing ) { int regbase = ( outgoing ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 32 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_record_value ( type , mode , 0 , 1 , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } else if ( TARGET_ARCH32 && mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle TARGET_FUNCTION_VALUE , and TARGET_LIBCALL_VALUE target hook . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s> MachineBasicBlock :: iterator LanaiFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
bool
WaitInsert
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
MF
.
getFunction
(
)
.
hasFnAttribute
(
Attribute
::
StrictFP
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
const
X86InstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MBB
.
begin
(
)
;
MI
!=
MBB
.
end
(
)
;
++
MI
)
{
if
(
!
isX87Instruction
(
*
MI
)
)
continue
;
if
(
!
(
MI
->
mayRaiseFPException
(
)
||
MI
->
mayLoadOrStore
(
)
)
||
isX87ControlInstruction
(
*
MI
)
)
continue
;
MachineBasicBlock
::
iterator
AfterMI
=
std
::
next
(
MI
)
;
if
(
AfterMI
!=
MBB
.
end
(
)
&&
isX87Instruction
(
*
AfterMI
)
&&
!
isX87NonWaitingControlInstruction
(
*
AfterMI
)
)
continue
;
BuildMI
(
MBB
,
AfterMI
,
MI
->
getDebugLoc
(
)
,
TII
->
get
(
X86
::
WAIT
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nInsert wait after:\t"
<<
*
MI
)
;
++
MI
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>


<s> static bool rs6000_vector_mode_supported_p ( enum machine_mode mode ) { if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const override { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> StackOffset ( const StackOffset & Other ) : Bytes ( Other . Bytes ) , ScalableBytes ( Other . ScalableBytes ) { } </s>


<s> bool ix86_epilogue_uses ( int regno ) { return ( epilogue_completed && cfun -> machine -> no_caller_saved_registers && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) ) ; } </s>

Return true if REGNO is used by the epilogue .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> MVT PPCTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == MVT :: f64 ) return MVT :: i32 ; return PPCTargetLowering :: getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> static void iq2000_select_rtx_section ( enum machine_mode mode , rtx x ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ) { mergeable_constant_section ( mode , align , 0 ) ; } </s>

Choose the section to use for the constant rtx expression X that has mode MODE .


<s> BitVector CAHPRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , CAHP :: X0 ) ; markSuperRegs ( Reserved , CAHP :: X1 ) ; markSuperRegs ( Reserved , CAHP :: X2 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCFrameLowering
*
PPCFI
=
static_cast
<
const
PPCFrameLowering
*
>
(
Subtarget
.
getFrameLowering
(
)
)
;
unsigned
StackEst
=
PPCFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

PowerPC
PPC
0
"Local offset must be negative"
PPC::ADDI
PPC::ADDI8
2
0
PPC
PPC
PPC
PPC


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == 0 && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ; unsigned Reg = I . getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> bool MandarinPassConfig :: addInstSelector ( ) { addPass ( createMandarinISelDag ( getMandarinTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool SystemZAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".insn" ) return ParseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; if ( IDVal == ".machine" ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void MipsInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << LowercaseString ( getRegisterName ( RegNo ) ) ; } </s>


<s> const ELFAttributeValue * ARMELFAttributeData :: getAttributeValue ( TagType pTag ) const { if ( pTag <= Tag_Max ) { const ELFAttributeValue & attr_value = m_Attrs [ pTag ] ; if ( attr_value . isInitialized ( ) ) { return & attr_value ; } else { return NULL ; } } else { UnknownAttrsMap :: const_iterator attr_it = m_UnknownAttrs . find ( pTag ) ; if ( attr_it == m_UnknownAttrs . end ( ) ) { return NULL ; } else { return & attr_it -> second ; } } } </s>

Extract a DWARF form value from a DIE specified by DIE offset .


<s> static rtx gen_lvx_v4si_move ( rtx dest , rtx src ) { gcc_assert ( MEM_P ( dest ) ^ MEM_P ( src ) ) ; gcc_assert ( GET_MODE ( dest ) == V4SImode && GET_MODE ( src ) == V4SImode ) ; if ( MEM_P ( dest ) ) return gen_altivec_stvx_v4si_internal ( dest , src ) ; else return gen_altivec_lvx_v4si_internal ( dest , src ) ; } </s>

Generate loads and stores for a move of v4si mode using lvx/stvx . This uses altivec_ { l , st } vx_ < mode > _internal which use unspecs to keep combine from changing what instruction gets used . DEST is the destination for the data . SRC is the source of the data for the move .


<s> HOST_WIDE_INT loongarch_debugger_offset ( rtx addr , HOST_WIDE_INT offset ) { rtx offset2 = const0_rtx ; rtx reg = eliminate_constant_term ( addr , & offset2 ) ; if ( offset == 0 ) offset = INTVAL ( offset2 ) ; if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { offset -= cfun -> machine -> frame . total_size ; if ( reg == hard_frame_pointer_rtx ) offset += cfun -> machine -> frame . hard_frame_pointer_offset ; } return offset ; } </s>

The LoongArch debug format wants all automatic variables and arguments to be in terms of the virtual frame pointer ( stack pointer before any adjustment in the function ) , while the LoongArch linker wants the frame pointer to be the stack pointer after the initial adjustment . So , we do the adjustment here . The arg pointer ( which is eliminated ) points to the virtual frame pointer , while the frame pointer ( which may be eliminated ) points to the stack pointer after the initial adjustments .


<s> int legitimate_constant_p ( rtx x ATTRIBUTE_UNUSED ) { return 1 ; } </s>

Nonzero if the constant value X is a legitimate general operand . It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s>
void
Cpu0InstPrinter
::
PrintSpecial
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
const
char
*
Code
)
const
{
assert
(
strcmp
(
Code
,
"arguments"
)
==
0
)
;
for
(
unsigned
i
=
0
;
i
<
MI
->
getNumOperands
(
)
1
;
i
++
)
{
if
(
i
!=
0
)
{
O
<<
", "
;
}
O
<<
"$r"
<<
i
<<
"|0"
;
}
}
</s>

Print information related to the specified machine instr that is independent of the operand , and may be independent of the instr itself .


<s> void setKind ( BaseKind K ) { Kind = K ; } </s>


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( CC == CallingConv :: CFGuard_Check ) return CSR_Win_AAPCS_CFGuard_Check_RegMask ; if ( CC == CallingConv :: SwiftTail ) { return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftTail_RegMask : CSR_AAPCS_SwiftTail_RegMask ; } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
static
tree
get_arm_sve_vector_bits_attributes
(
tree
old_attrs
,
tree
new_sve_type_args
)
{
tree
new_attrs
=
NULL_TREE
;
tree
*
ptr
=
&
new_attrs
;
for
(
tree
attr
=
old_attrs
;
attr
;
attr
=
TREE_CHAIN
(
attr
)
)
{
tree
name
=
get_attribute_name
(
attr
)
;
if
(
is_attribute_p
(
"SVE sizeless type"
,
name
)
)
continue
;
tree
args
=
TREE_VALUE
(
attr
)
;
if
(
is_attribute_p
(
"SVE type"
,
name
)
)
args
=
new_sve_type_args
;
*
ptr
=
tree_cons
(
TREE_PURPOSE
(
attr
)
,
args
,
NULL_TREE
)
;
ptr
=
&
TREE_CHAIN
(
*
ptr
)
;
}
return
new_attrs
;
}
</s>

ATTRS is the attribute list for a sizeless SVE type . Return the attributes of the associated fixed-length SVE type , taking the `` SVE type '' attributes from NEW_SVE_TYPE_ARGS .


<s> static bool callees_functions_use_frame_header ( function * fn ) { basic_block bb ; gimple_stmt_iterator gsi ; gimple * stmt ; tree called_fn_tree ; function * called_fn ; if ( fn -> cfg == NULL ) return true ; FOR_EACH_BB_FN ( bb , fn ) { for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { stmt = gsi_stmt ( gsi ) ; if ( is_gimple_call ( stmt ) ) { called_fn_tree = gimple_call_fndecl ( stmt ) ; if ( called_fn_tree != NULL ) { called_fn = DECL_STRUCT_FUNCTION ( called_fn_tree ) ; if ( called_fn == NULL || DECL_WEAK ( called_fn_tree ) || has_inlined_assembly ( called_fn ) || ! is_leaf_function ( called_fn ) || ! called_fn -> machine -> does_not_use_frame_header ) return true ; } else return true ; } } } return false ; } </s>

Return true if the argument stack space allocated by function FN is used . Return false if the space is needed or if the need for the space can not be determined .


<s>
unsigned
getOffsetReg
(
)
const
{
assert
(
isRegBase
(
)
&&
"Invalid offset register access!"
)
;
return
OffsetReg
;
}
</s>

Get the offset register of the pointer value .


<s> void LoongArchInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << '$' << getRegisterName ( RegNo ) ; } </s>


<s> static bool rs6000_use_blocks_for_decl_p ( const_tree decl ) { return ! DECL_THREAD_LOCAL_P ( decl ) ; } </s>

Do not place thread-local symbols refs in the object blocks .


<s> bool UPTInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case UPT :: MOVi32 : { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( 0 ) . isDead ( ) ; const MachineOperand & MO = MI . getOperand ( 1 ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( UPT :: MOVLOi16 ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( UPT :: MOVHIi16 ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | UPTII :: MO_LO16 ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | UPTII :: MO_HI16 ) ; MBB . erase ( MI ) ; return true ; } } } </s>

This function is called for all pseudo instructions that remain after register allocation .


"Tail call is handled in the normal case. See comments"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

Perform target-specific instruction verification .


Compare an SVE mode SVE_M and an Advanced SIMD mode ASIMD_M and return whether the SVE mode should be preferred over the Advanced SIMD one in aarch64_autovectorize_vector_modes .


<s> static bool nds32_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( ! TARGET_V3PUSH && ( cfun -> machine -> va_args_size == 0 ) && decl ) ; } </s>

Return true if it is ok to do sibling call optimization .


<s> bool X86FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { bool CompactUnwind = MF . getMMI ( ) . getContext ( ) . getObjectFileInfo ( ) -> getCompactUnwindSection ( ) != nullptr ; return ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) || ! CompactUnwind ) && MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: HiPE && ! MF . shouldSplitStack ( ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


"rs6000_cannot_change_mode_class, return %s, from = %s, "

Debug version of rs6000_cannot_change_mode_class .


<s> rtx aarch64_expand_rng_builtin ( tree exp , rtx target , int fcode , int ignore ) { rtx pat ; enum insn_code icode ; if ( fcode == AARCH64_BUILTIN_RNG_RNDR ) icode = CODE_FOR_aarch64_rndr ; else if ( fcode == AARCH64_BUILTIN_RNG_RNDRRS ) icode = CODE_FOR_aarch64_rndrrs ; else gcc_unreachable ( ) ; rtx rand = gen_reg_rtx ( DImode ) ; pat = GEN_FCN ( icode ) ( rand ) ; if ( ! pat ) return NULL_RTX ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx res_addr = expand_normal ( arg0 ) ; res_addr = convert_memory_address ( Pmode , res_addr ) ; rtx res_mem = gen_rtx_MEM ( DImode , res_addr ) ; emit_insn ( pat ) ; emit_move_insn ( res_mem , rand ) ; if ( ignore ) return target ; rtx cc_reg = gen_rtx_REG ( CC_Zmode , CC_REGNUM ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( EQ , SImode , cc_reg , const0_rtx ) ; emit_insn ( gen_aarch64_cstoresi ( target , cmp_rtx , cc_reg ) ) ; return target ; } </s>

Expand a random number builtin EXP with code FCODE , putting the result int TARGET . If IGNORE is true the return value is ignored .


<s> static bool ia64_skip_rtx_p ( const_rtx x ) { return get_spec_unspec_code ( x ) != - 1 ; } </s>


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; ArgInfo ArgRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( DL , ArgRetInfo , 0 , RetInfos , OrigArgIndices ) ; SmallVector < ISD :: OutputArg , 8 > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; MipsOutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> void MipsRegisterInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( NumBytes ) ; } } </s>

Mips Mips Mips Mips Mips Mips Mips Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::LW Mips::FP Mips::SP Mips::LW Mips::RA Mips::SP Mips::ADDiu Mips::SP Mips::SP


<s> bool ARMTargetLowering :: isLegalInterleavedAccessType ( unsigned Factor , VectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == 3 ) return false ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 ) return false ; if ( Subtarget -> hasNEON ( ) && VecSize == 64 ) return true ; return VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s>
void
SystemZInstrInfo
::
loadImmediate
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
unsigned
Reg
,
uint64_t
Value
)
const
{
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
unsigned
Opcode
;
if
(
isInt
<
16
>
(
Value
)
)
Opcode
=
SystemZ
::
LGHI
;
else
if
(
SystemZ
::
isImmLL
(
Value
)
)
Opcode
=
SystemZ
::
LLILL
;
else
if
(
SystemZ
::
isImmLH
(
Value
)
)
{
Opcode
=
SystemZ
::
LLILH
;
Value
>>=
16
;
}
else
{
assert
(
isInt
<
32
>
(
Value
)
&&
"Huge values not handled yet"
)
;
Opcode
=
SystemZ
::
LGFI
;
}
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
Reg
)
.
addImm
(
Value
)
;
}
</s>

Emit a series of instructions to load an immediate .

SystemZ
SystemZ
16
SystemZ::LGHI
SystemZ::isImmLL
SystemZ::LLILL
SystemZ::isImmLH
SystemZ::LLILH
16
32
"Huge values not handled yet"
SystemZ::LGFI


<s>
const
char
*
output_load_pcrel_sym
(
rtx
*
operands
)
{
if
(
flag_delayed_branch
)
{
output_asm_insn
(
"sethi\t%%hi(%a1-4), %0"
,
operands
)
;
output_asm_insn
(
"call\t%a2"
,
operands
)
;
output_asm_insn
(
" add\t%0, %%lo(%a1+4), %0"
,
operands
)
;
}
else
{
output_asm_insn
(
"sethi\t%%hi(%a1-8), %0"
,
operands
)
;
output_asm_insn
(
"add\t%0, %%lo(%a1-4), %0"
,
operands
)
;
output_asm_insn
(
"call\t%a2"
,
operands
)
;
output_asm_insn
(
" nop"
,
)
;
}
if
(
operands
[
2
]
==
got_helper_rtx
)
got_helper_needed
=
true
;
return
""
;
}
</s>


<s> bool isLittleEndian ( ) const { return isLittle ; } </s>

Tests whether the target triple is little endian .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( ( uint32_t ) Fixup . getKind ( ) == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static bool csky_rtx_costs ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ) { int code = GET_CODE ( x ) ; if ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK801 ) ) return ck802_ck801_rtx_costs ( x , code , outer_code , total , speed ) ; else if ( CSKY_TARGET_ARCH ( CK803 ) ) return ck803_rtx_costs ( x , code , outer_code , total , speed ) ; else if ( CSKY_TARGET_ARCH ( CK807 ) || CSKY_TARGET_ARCH ( CK810 ) ) return ck807_ck810_rtx_costs ( x , code , outer_code , total , speed ) ; else if ( CSKY_TARGET_ARCH ( CK860 ) ) return ck860_rtx_costs ( x , code , mode , outer_code , total , speed ) ; else gcc_unreachable ( ) ; } </s>

Implement TARGET_RTX_COSTS , to compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


"argument to %qs must be a 2-bit unsigned literal"


<s> uint64_t getFeatures ( ) const { return Features ; } </s>

Returns the vector of individual subtarget features .


<s> static int arm_save_coproc_regs ( void ) { int saved_size = 0 ; unsigned reg ; unsigned start_reg ; rtx insn ; for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG ( V2SImode , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; saved_size += 8 ; } if ( TARGET_HARD_FLOAT ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += 2 ) { if ( ( ! df_regs_ever_live_p ( reg ) || call_used_regs [ reg ] ) && ( ! df_regs_ever_live_p ( reg + 1 ) || call_used_regs [ reg + 1 ] ) ) { if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; start_reg = reg + 2 ; } } if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; } return saved_size ; } </s>

Emit RTL to save coprocessor registers on function entry . Returns the number of bytes pushed .


<s> void aarch64_split_add_offset ( scalar_int_mode mode , rtx dest , rtx src , rtx offset_rtx , rtx temp1 , rtx temp2 ) { aarch64_add_offset ( mode , dest , src , rtx_to_poly_int64 ( offset_rtx ) , temp1 , temp2 , false ) ; } </s>

Like aarch64_add_offset , but the offset is given as an rtx rather than a poly_int64 .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_fadd : case Intrinsic :: aarch64_sve_fsub : return instCombineSVEVectorBinOp ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static sbitmap rs6000_get_separate_components ( void ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( WORLD_SAVE_P ( info ) ) return NULL ; if ( TARGET_SPE_ABI ) return NULL ; gcc_assert ( ! ( info -> savres_strategy & SAVE_MULTIPLE ) && ! ( info -> savres_strategy & REST_MULTIPLE ) ) ; cfun -> machine -> n_components = 64 ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; int reg_size = TARGET_32BIT ? 4 : 8 ; int fp_reg_size = 8 ; if ( ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) ) { int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && rs6000_reg_live_or_pic_offset_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += reg_size ; } } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( ( TARGET_TOC && TARGET_MINIMAL_TOC ) || ( flag_pic == 1 && DEFAULT_ABI == ABI_V4 ) || ( flag_pic && DEFAULT_ABI == ABI_DARWIN ) ) bitmap_clear_bit ( components , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) ) { int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += fp_reg_size ; } } if ( info -> lr_save_p && ! ( flag_pic && ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) ) && ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) && ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) && ( info -> savres_strategy & SAVE_INLINE_VRS ) && ( info -> savres_strategy & REST_INLINE_VRS ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) ) bitmap_set_bit ( components , 0 ) ; } return components ; } </s>


<s> bool X86TargetLowering :: shouldConvertPhiType ( Type * From , Type * To ) const { if ( ! Subtarget . is64Bit ( ) ) return false ; return TargetLowering :: shouldConvertPhiType ( From , To ) ; } </s>

Given a set in interconnected phis of type 'From ' that are loaded/stored or bitcast to type 'To ' , return true if the set should be converted to 'To ' .


<s> static int mingw32_gt_pch_use_address ( void * & addr , size_t size , int fd , size_t offset ) { void * mmap_addr ; HANDLE mmap_handle ; char * object_name = NULL ; OSVERSIONINFO version_info ; int r ; version_info . dwOSVersionInfoSize = sizeof ( version_info ) ; if ( size == 0 ) return 0 ; if ( ( offset & ( va_granularity - 1 ) ) != 0 || size > pch_VA_max_size ) return - 1 ; GetVersionEx ( & version_info ) ; char local_object_name [ sizeof ( OBJECT_NAME_FMT ) + sizeof ( DWORD ) * 2 ] ; if ( version_info . dwMajorVersion > 4 ) { snprintf ( local_object_name , sizeof ( local_object_name ) , OBJECT_NAME_FMT "%lx" , GetCurrentProcessId ( ) ) ; object_name = local_object_name ; } mmap_handle = CreateFileMappingA ( ( HANDLE ) _get_osfhandle ( fd ) , NULL , PAGE_WRITECOPY | SEC_COMMIT , 0 , 0 , object_name ) ; if ( mmap_handle == NULL ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "CreateFileMapping" ) ; return - 1 ; } for ( r = 0 ; r < 5 ; r ++ ) { mmap_addr = MapViewOfFileEx ( mmap_handle , FILE_MAP_COPY , 0 , offset , size , addr ) ; if ( mmap_addr == addr ) break ; if ( r != 4 ) Sleep ( 500 ) ; } if ( mmap_addr != addr ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "MapViewOfFileEx" ) ; CloseHandle ( mmap_handle ) ; return - 1 ; } return 1 ; } </s>

ADDR is an address returned by gt_pch_get_address . Attempt to allocate SIZE bytes at the same address and load it with the data from FD at OFFSET . Return -1 if we could n't allocate memory at ADDR , return 0 if the memory is allocated but the data not loaded , return 1 if done .


<s> static struct machine_function * or1k_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Zero initialization is OK for all current fields .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createTOYELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool X86InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isTerminator ( ) ) return false ; if ( MCID . isBranch ( ) && ! MCID . isBarrier ( ) ) return true ; if ( ! MCID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s>
bool
ARMAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
&&
MO
.
getReg
(
)
!=
ARM
::
CPSR
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
{
MCOp
=
GetSymbolRef
(
MO
,
GetARMGVSymbol
(
MO
.
getGlobal
(
)
,
MO
.
getTargetFlags
(
)
)
)
;
break
;
}
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
GetSymbolRef
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
createFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

ARM
ARM
"unknown operand type"
ARM::CPSR
"Subregs should be eliminated!"
ARM


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream , raw_ostream & cStream ) const { CommentStream = & cStream ; InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = nullptr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * ) MII . get ( ) , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr , this ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s>
bool
OR1KAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
OR1KOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
&&
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
return
Error
(
getLexer
(
)
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in operand list"
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> static rtx gen_gpr_to_xmm_move_src ( enum machine_mode vmode , rtx gpr ) { switch ( GET_MODE_NUNITS ( vmode ) ) { case 1 : gcc_unreachable ( ) ; case 2 : return gen_rtx_VEC_CONCAT ( vmode , gpr , CONST0_RTX ( GET_MODE_INNER ( vmode ) ) ) ; default : return gen_rtx_VEC_MERGE ( vmode , gen_rtx_VEC_DUPLICATE ( vmode , gpr ) , CONST0_RTX ( vmode ) , GEN_INT ( HOST_WIDE_INT_1U ) ) ; } } </s>

Generate the canonical SET_SRC to move GPR to a VMODE vector register , zeroing the upper parts .


<s> static void aarch64_pop_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment , rtx * cfi_ops ) { machine_mode mode = aarch64_reg_save_mode ( regno1 ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg1 , * cfi_ops ) ; if ( regno2 == INVALID_REGNUM ) { rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; } } </s>

Pop the two registers numbered REGNO1 , REGNO2 from the stack , adjusting it afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s>
bool
ARMBaseInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugInstr
(
)
||
!
I
->
isTerminator
(
)
)
{
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
if
(
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
!
isPredicated
(
*
I
)
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
return
true
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


"Can only insert epilog into returning blocks"


<s> bool AArch64TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == 128 ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) || vzeroall_pattern ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_upper_reg_found = false ; note_stores ( insn , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return mode ; } </s>

Calculate mode of upper 128bit AVX registers after the insn .


<s> static bool sh_pass_in_reg_p ( const CUMULATIVE_ARGS & cum , machine_mode mode , const_tree type ) { return ( ( type == 0 || ( ! TREE_ADDRESSABLE ( type ) && ( ! ( TARGET_HITACHI || cum . renesas_abi ) || ! ( AGGREGATE_TYPE_P ( type ) || ( ! TARGET_FPU_ANY && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SFmode ) ) ) ) ) ) ) && ! cum . force_mem && ( TARGET_SH2E ? ( ( mode ) == BLKmode ? ( ( cum . arg_count [ ( int ) SH_ARG_INT ] * UNITS_PER_WORD + int_size_in_bytes ( type ) ) <= NPARM_REGS ( SImode ) * UNITS_PER_WORD ) : ( ( sh_round_reg ( cum , mode ) + sh_hard_regno_nregs ( BASE_ARG_REG ( mode ) , mode ) ) <= NPARM_REGS ( mode ) ) ) : sh_round_reg ( cum , mode ) < NPARM_REGS ( mode ) ) ) ; } </s>

Return true if arg of the specified mode should be be passed in a register or false otherwise .


"Arch64 does not support GOT PC rel with extra offset"

Get the target specific PC relative GOT entry relocation .


<s> static rtx mips_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return mips_function_value_1 ( NULL_TREE , NULL_TREE , mode ) ; } </s>


<s> bool Mips16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static bool arm_sched_can_speculate_insn ( rtx_insn * insn ) { switch ( get_attr_type ( insn ) ) { case TYPE_SDIV : case TYPE_UDIV : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_FSQRTS : case TYPE_FSQRTD : case TYPE_NEON_FP_SQRT_S : case TYPE_NEON_FP_SQRT_D : case TYPE_NEON_FP_SQRT_S_Q : case TYPE_NEON_FP_SQRT_D_Q : case TYPE_NEON_FP_DIV_S : case TYPE_NEON_FP_DIV_D : case TYPE_NEON_FP_DIV_S_Q : case TYPE_NEON_FP_DIV_D_Q : return false ; default : return true ; } } </s>

Implement TARGET_SCHED_CAN_SPECULATE_INSN . Return true if INSN can be scheduled for speculative execution . Reject the long-running division and square-root instructions .


<s> static int optimal_immediate_sequence_1 ( enum rtx_code code , unsigned HOST_WIDE_INT val , struct four_ints * return_sequence , int i ) { int remainder = val & 0xffffffff ; int insns = 0 ; do { int end ; unsigned int b1 , b2 , b3 , b4 ; unsigned HOST_WIDE_INT result ; int loc ; gcc_assert ( insns < 4 ) ; if ( i <= 0 ) i += 32 ; if ( remainder & ( ( TARGET_ARM ? ( 3 << ( i - 2 ) ) : ( 1 << ( i - 1 ) ) ) ) ) { loc = i ; if ( i <= 12 && TARGET_THUMB2 && code == PLUS ) result = remainder ; else { end = i - 8 ; if ( end < 0 ) end += 32 ; result = remainder & ( ( 0x0ff << end ) | ( ( i < end ) ? ( 0xff >> ( 32 - end ) ) : 0 ) ) ; i -= 8 ; } } else { i -= TARGET_ARM ? 2 : 1 ; continue ; } if ( TARGET_THUMB2 ) { b1 = ( remainder & 0xff000000 ) >> 24 ; b2 = ( remainder & 0x00ff0000 ) >> 16 ; b3 = ( remainder & 0x0000ff00 ) >> 8 ; b4 = remainder & 0xff ; if ( loc > 24 ) { unsigned int tmp = b1 & b2 & b3 & b4 ; unsigned int tmp2 = tmp + ( tmp << 8 ) + ( tmp << 16 ) + ( tmp << 24 ) ; unsigned int matching_bytes = ( tmp == b1 ) + ( tmp == b2 ) + ( tmp == b3 ) + ( tmp == b4 ) ; if ( tmp && ( matching_bytes >= 3 || ( matching_bytes == 2 && const_ok_for_op ( remainder & ~ tmp2 , code ) ) ) ) { result = tmp2 ; i = tmp != b1 ? 32 : tmp != b2 ? 24 : tmp != b3 ? 16 : 8 ; } else if ( b1 == b3 && ( ! b2 || ! b4 || ( remainder & 0x00ff0000 & ~ result ) ) ) { result = remainder & 0xff00ff00 ; i = 24 ; } } else if ( loc > 16 ) { if ( b2 == b4 ) { result = remainder & 0x00ff00ff ; i = 16 ; } } } return_sequence -> i [ insns ++ ] = result ; remainder &= ~ result ; if ( code == SET || code == MINUS ) code = PLUS ; } while ( remainder ) ; return insns ; } </s>

As for optimal_immediate_sequence , but starting at bit-position I .


<s> void mips_split_128bit_move ( rtx dest , rtx src ) { int byte , index ; rtx low_dest , low_src , d , s ; if ( FP_REG_RTX_P ( dest ) ) { gcc_assert ( ! MEM_P ( src ) ) ; rtx new_dest = dest ; if ( ! TARGET_64BIT ) { if ( GET_MODE ( dest ) != V4SImode ) new_dest = simplify_gen_subreg ( V4SImode , dest , GET_MODE ( dest ) , 0 ) ; } else { if ( GET_MODE ( dest ) != V2DImode ) new_dest = simplify_gen_subreg ( V2DImode , dest , GET_MODE ( dest ) , 0 ) ; } for ( byte = 0 , index = 0 ; byte < GET_MODE_SIZE ( TImode ) ; byte += UNITS_PER_WORD , index ++ ) { s = mips_subword_at_byte ( src , byte ) ; if ( ! TARGET_64BIT ) emit_insn ( gen_msa_insert_w ( new_dest , s , new_dest , GEN_INT ( 1 << index ) ) ) ; else emit_insn ( gen_msa_insert_d ( new_dest , s , new_dest , GEN_INT ( 1 << index ) ) ) ; } } else if ( FP_REG_RTX_P ( src ) ) { gcc_assert ( ! MEM_P ( dest ) ) ; rtx new_src = src ; if ( ! TARGET_64BIT ) { if ( GET_MODE ( src ) != V4SImode ) new_src = simplify_gen_subreg ( V4SImode , src , GET_MODE ( src ) , 0 ) ; } else { if ( GET_MODE ( src ) != V2DImode ) new_src = simplify_gen_subreg ( V2DImode , src , GET_MODE ( src ) , 0 ) ; } for ( byte = 0 , index = 0 ; byte < GET_MODE_SIZE ( TImode ) ; byte += UNITS_PER_WORD , index ++ ) { d = mips_subword_at_byte ( dest , byte ) ; if ( ! TARGET_64BIT ) emit_insn ( gen_msa_copy_s_w ( d , new_src , GEN_INT ( index ) ) ) ; else emit_insn ( gen_msa_copy_s_d ( d , new_src , GEN_INT ( index ) ) ) ; } } else { low_dest = mips_subword_at_byte ( dest , 0 ) ; low_src = mips_subword_at_byte ( src , 0 ) ; gcc_assert ( REG_P ( low_dest ) && REG_P ( low_src ) ) ; if ( REGNO ( low_dest ) <= REGNO ( low_src ) ) { for ( byte = 0 ; byte < GET_MODE_SIZE ( TImode ) ; byte += UNITS_PER_WORD ) { d = mips_subword_at_byte ( dest , byte ) ; s = mips_subword_at_byte ( src , byte ) ; mips_emit_move ( d , s ) ; } } else { for ( byte = GET_MODE_SIZE ( TImode ) - UNITS_PER_WORD ; byte >= 0 ; byte -= UNITS_PER_WORD ) { d = mips_subword_at_byte ( dest , byte ) ; s = mips_subword_at_byte ( src , byte ) ; mips_emit_move ( d , s ) ; } } } } </s>


<s>
bool
SparcAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
if
(
parseBranchModifiers
(
Operands
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

Sparc
Sparc
SparcOperand::CreateToken
0
"unexpected token"
"unexpected token"
"unexpected token"
"unexpected token"


<s> void X86MCCodeEmitter :: emitPrefix ( const MCInst & MI , raw_ostream & OS , const MCSubtargetInfo & STI ) const { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & X86II :: FormMask ) == X86II :: Pseudo ) return ; unsigned CurOp = X86II :: getOperandBias ( Desc ) ; unsigned CurByte = 0 ; bool Rex = false ; emitPrefixImpl ( TSFlags , CurOp , CurByte , Rex , MI , Desc , STI , OS ) ; } </s>

Append the prefixes of given instruction to the code buffer .


<s> bool Cpu0AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .