<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 1 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 2 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s>
const
char
*
getPassName
(
)
const
{
return
"TOY PreRmit"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static tree arm_stack_protect_guard ( void ) { if ( arm_stack_protector_guard == SSP_GLOBAL ) return default_stack_protect_guard ( ) ; return NULL_TREE ; } </s>

Implement TARGET_STACK_PROTECT_GUARD . In case of a global variable based guard use the default else return a null tree .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; case X86ISD :: SHUFPS : case X86ISD :: SHUFPD : case X86ISD :: PUNPCKHBW : case X86ISD :: PUNPCKHWD : case X86ISD :: PUNPCKHDQ : case X86ISD :: PUNPCKHQDQ : case X86ISD :: UNPCKHPS : case X86ISD :: UNPCKHPD : case X86ISD :: PUNPCKLBW : case X86ISD :: PUNPCKLWD : case X86ISD :: PUNPCKLDQ : case X86ISD :: PUNPCKLQDQ : case X86ISD :: UNPCKLPS : case X86ISD :: UNPCKLPD : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> SDValue MipsSETargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Val ; switch ( N -> getOpcode ( ) ) { case ISD :: ADDE : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : Val = performANDCombine ( N , DAG , DCI , Subtarget ) ; break ; case ISD :: SUBE : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMULCombine ( N , DAG , DCI , this ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRA : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRL : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: VSELECT : return performVSELECTCombine ( N , DAG ) ; case ISD :: XOR : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case ISD :: SETCC : Val = performSETCCCombine ( N , DAG ) ; break ; } if ( Val . getNode ( ) ) return Val ; return MipsTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

Mips Mips ISD::ADDE ISD::AND ISD::SUBE ISD::MUL ISD::SHL ISD::SRA ISD::SRL ISD::VSELECT ISD::XOR ISD::SETCC Mips


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
int
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
RoundUpToAlignment
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool or1k_legitimate_address_p ( machine_mode , rtx x , bool strict_p ) { rtx base , addend ; switch ( GET_CODE ( x ) ) { case REG : base = x ; break ; case PLUS : base = XEXP ( x , 0 ) ; addend = XEXP ( x , 1 ) ; if ( ! REG_P ( base ) ) return false ; if ( ! strict_p && virtual_frame_reg_operand ( base , VOIDmode ) ) return CONST_INT_P ( addend ) ; if ( ! satisfies_constraint_I ( addend ) ) return false ; break ; case LO_SUM : base = XEXP ( x , 0 ) ; if ( ! REG_P ( base ) ) return false ; x = XEXP ( x , 1 ) ; switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case LABEL_REF : break ; case UNSPEC : switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_TPOFF : case UNSPEC_GOTTPOFF : break ; default : return false ; } break ; default : return false ; } break ; default : return false ; } unsigned regno = REGNO ( base ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { if ( strict_p ) regno = reg_renumber [ regno ] ; else return true ; } if ( strict_p ) return regno <= 31 ; else return REGNO_OK_FOR_BASE_P ( regno ) ; } </s>

Worker for TARGET_LEGITIMATE_ADDRESS_P . Returns true if X is a legitimate address RTX on OpenRISC .


"%<__BELOW100__%> attribute only applies to variables"

"%<__BELOW100__%> attribute not allowed "

Handle an `` below '' attribute ; arguments as in struct attribute_spec.handler .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
.
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


"Switch should handle all register classes"


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( VT . getSizeInBits ( ) == 64 ) return false ; if ( ( SVT . is128BitVector ( ) && Subtarget -> hasSSSE3 ( ) ) || ( SVT . is256BitVector ( ) && Subtarget -> hasInt256 ( ) ) ) { bool isLegal = true ; for ( unsigned I = 0 , E = M . size ( ) ; I != E ; ++ I ) { if ( M [ I ] >= ( int ) SVT . getVectorNumElements ( ) || ShuffleCrosses128bitLane ( SVT , I , M [ I ] ) ) { isLegal = false ; break ; } } if ( isLegal ) return true ; } return ( SVT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isPSHUFDMask ( M , SVT ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const SystemZSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
case
ARMII
::
AddrMode3
:
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
case
ARMII
::
AddrModeT1_s
:
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> const PPCRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
unsigned
assignCustomValue
(
const
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
unsigned
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Reg
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM IR optimizations"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = Subtarget ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 16


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> bool Cpu0PassConfig :: addPreRegAlloc ( ) { addPass ( createCpu0EmitGPRestorePass ( getCpu0TargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool mips_find_gp_ref ( bool * cache , bool ( * pred ) ( rtx_insn * ) ) { rtx_insn * insn ; if ( ! * cache ) { push_topmost_sequence ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( USEFUL_INSN_P ( insn ) && pred ( insn ) ) { * cache = true ; break ; } pop_topmost_sequence ( ) ; } return * cache ; } </s>

Return true if predicate PRED is true for at least one instruction . Cache the result in * CACHE , and assume that the result is true if * CACHE is already true .


<s> unsigned PPCTTIImpl :: getPrefetchDistance ( ) { return 300 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> bool X86InstrInfo :: isHighLatencyDef ( int opc ) const { switch ( opc ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDm_Int : case X86 :: SQRTPDr : case X86 :: SQRTPDr_Int : case X86 :: SQRTPSm : case X86 :: SQRTPSm_Int : case X86 :: SQRTPSr : case X86 :: SQRTPSr_Int : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : case X86 :: VDIVSDrm : case X86 :: VDIVSDrm_Int : case X86 :: VDIVSDrr : case X86 :: VDIVSDrr_Int : case X86 :: VDIVSSrm : case X86 :: VDIVSSrm_Int : case X86 :: VDIVSSrr : case X86 :: VDIVSSrr_Int : case X86 :: VSQRTPDm : case X86 :: VSQRTPDm_Int : case X86 :: VSQRTPDr : case X86 :: VSQRTPDr_Int : case X86 :: VSQRTPSm : case X86 :: VSQRTPSm_Int : case X86 :: VSQRTPSr : case X86 :: VSQRTPSr_Int : case X86 :: VSQRTSDm : case X86 :: VSQRTSDm_Int : case X86 :: VSQRTSDr : case X86 :: VSQRTSSm : case X86 :: VSQRTSSm_Int : case X86 :: VSQRTSSr : return true ; } } </s>

Return true if this opcode has high latency to its result .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilderBase & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; int Offset = M -> getStackProtectorGuardOffset ( ) ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; StringRef GuardReg = M -> getStackProtectorGuardReg ( ) ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> static ARMCC :: CondCodes getPredicate ( const MachineInstr * MI , unsigned & PredReg ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: tBcc || Opc == ARM :: t2Bcc ) return ARMCC :: AL ; return llvm :: getInstrPredicate ( MI , PredReg ) ; } </s>

Returns the comparison predicate underlying the intrinsic .

ARM ARMCC::CondCodes ARM::tBcc ARM::t2Bcc ARMCC::AL


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 pseudo instruction expansion pass"
;
}
</s>


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) override { MIB . addUse ( PhysReg , RegState :: Implicit ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static int hppa_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == SHIFT_REGS ) return 0x100 ; else if ( to == SHIFT_REGS && FP_REG_CLASS_P ( from ) ) return 18 ; else if ( ( FP_REG_CLASS_P ( from ) && ! FP_REG_CLASS_P ( to ) ) || ( FP_REG_CLASS_P ( to ) && ! FP_REG_CLASS_P ( from ) ) ) return 16 ; else return 2 ; } </s>

Implement the TARGET_REGISTER_MOVE_COST hook . Compute extra cost of moving data between one register class and another . Make moves from SAR so expensive they should never happen . We used to have 0xffff here , but that generates overflow in rare cases . Copies involving a FP register and a non-FP register are relatively expensive because they must go through memory . Other copies are reasonably cheap .


<s> void split_di ( rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { while ( num -- ) { rtx op = operands [ num ] ; if ( GET_CODE ( op ) == MEM ) { lo_half [ num ] = adjust_address ( op , SImode , 0 ) ; hi_half [ num ] = adjust_address ( op , SImode , 4 ) ; } else { lo_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , 4 ) ; } } } </s>

Split one or more DImode RTL references into pairs of SImode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of DImode RTL to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


runOnMachineFunction - Emit the function body .


<s> bool PPCTargetLowering :: hasInlineStackProbe ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) == "inline-asm" ; return false ; } </s>

Returns true if stack probing through inline assembly is requested .

PowerPC PPC "probe-stack" "probe-stack" "inline-asm"


Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook .


<s> bool ThumbRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const ARMSubtarget & STI = MBB . getParent ( ) -> getSubtarget < ARMSubtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: saveScavengerRegister ( MBB , I , UseMI , RC , Reg ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static void rs6000_elf_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { default_elf_select_section_1 ( decl , reloc , align , flag_pic || DEFAULT_ABI == ABI_AIX ) ; } </s>

A C statement or statements to switch to the appropriate section for output of DECL . DECL is either a ` VAR_DECL ' node or a constant of some sort . RELOC indicates whether forming the initial value of DECL requires link-time relocations .


"unknown base architecture %<0x%x%>, %qs failed"

"some tuning parameters will fall back to default"


<s> void MipsTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { if ( ! isMicroMipsEnabled ( ) ) return ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; uint8_t Type = MCELF :: GetType ( Data ) ; if ( Type != ELF :: STT_FUNC ) return ; MCELF :: setOther ( Data , ELF :: STO_MIPS_MICROMIPS >> 2 ) ; } </s>

Emit a label for Symbol into the current section .


<s> void loongarch_split_move_insn ( rtx dest , rtx src , rtx insn ) { loongarch_split_move ( dest , src , insn ) ; } </s>

Split a move from SRC to DEST in INSN , given that loongarch_split_move_insn_p holds .


<s> TargetLowering :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { auto PTy = cast < PointerType > ( LI -> getPointerOperandType ( ) ) ; return needsCmpXchgNb ( PTy -> getElementType ( ) ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> SDValue AArch64TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && Subtarget -> useRSqrt ( ) ) ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRSQRTE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Estimate , Flags ) ; Step = DAG . getNode ( AArch64ISD :: FRSQRTS , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( 0.0 , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , ISD :: SETEQ ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? ISD :: VSELECT : ISD :: SELECT , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> static bool aarch64_composite_type_p ( const_tree type , machine_mode mode ) { if ( aarch64_short_vector_p ( type , mode ) ) return false ; if ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE ) ) return true ; if ( mode == BLKmode || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT ) return true ; return false ; } </s>

Return TRUE if the type , as described by TYPE and MODE , is a composite type as described in AAPCS64 \S 4.3 . This includes aggregate , union and array types . The C99 floating-point complex types are also considered as composite types , according to AAPCS64 \S 7.1.1 . The complex integer types , which are GCC extensions and out of the scope of AAPCS64 , are treated as composite types here as well . Note that MODE itself is not sufficient in determining whether a type is such a composite type or not . This is because stor-layout.c : compute_record_mode may have already changed the MODE ( BLKmode ) of a RECORD_TYPE TYPE to some other mode . For example , a structure with only one field may have its MODE set to the mode of the field . Also an integer mode whose size matches the size of the RECORD_TYPE type may be used to substitute the original mode ( i.e . BLKmode ) in certain circumstances . In other words , MODE can not be solely relied on .


<s> bool single_dest_per_chain ( const rtx & t ATTRIBUTE_UNUSED , insn_info_list_t * v , void * arg ATTRIBUTE_UNUSED ) { for ( int i = v -> length ( ) - 1 ; i >= 1 ; i -- ) { tag_insn_info * insn_info = ( * v ) [ i ] ; for ( int j = v -> length ( ) - 2 ; j >= 0 ; j -- ) { if ( in_same_chain ( insn_info -> insn , ( * v ) [ j ] -> insn , REGNO ( insn_info -> dest ) ) ) { v -> ordered_remove ( j ) ; i = v -> length ( ) ; break ; } } } return true ; } </s>

Callback function to traverse the tag map and drop loads that have the same destination and and in the same chain of occurrence . Routine always returns true to allow traversal through all of TAG_MAP .


<s> bool runOnFunction ( Function & F ) { PHINodeSet PromotablePHINodes = getPromotablePHINodes ( F ) ; B2IMap Bool2IntMap ; bool Changed = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { if ( ReturnInst * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( R -> getOperandUse ( 0 ) , PromotablePHINodes , Bool2IntMap ) ; if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"\nrs6000_secondary_reload_gpr, type = %s\n"

Convert reloads involving 64-bit gprs and misaligned offset addressing , or multiple 32-bit gprs and offsets that are too large , to use indirect addressing .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "min-legal-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "min-legal-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",min-legal-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , MaybeAlign ( Options . StackAlignmentOverride ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) { if ( TARGET_POWERPC64 ) { if ( size == 8 ) return true ; if ( size == 16 && TARGET_P9_VECTOR && mode != TDmode ) return true ; } if ( TARGET_P8_VECTOR ) { if ( mode == SImode ) return true ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> ISD :: NodeType getExtendForAtomicOps ( ) const override { return ISD :: ZERO_EXTEND ; } </s>

Returns how the platform 's atomic operations are extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


<s> void aarch64_register_pragmas ( void ) { targetm . target_option . pragma_parse = aarch64_pragma_target_parse ; targetm . resolve_overloaded_builtin = aarch64_resolve_overloaded_builtin ; targetm . check_builtin_call = aarch64_check_builtin_call ; c_register_pragma ( "GCC" , "aarch64" , aarch64_pragma_aarch64 ) ; } </s>


<s> rtx ix86_memtag_add_tag ( rtx base , poly_int64 offset , unsigned char tag_offset ) { rtx base_tag = gen_reg_rtx ( QImode ) ; rtx base_addr = gen_reg_rtx ( Pmode ) ; rtx tagged_addr = gen_reg_rtx ( Pmode ) ; rtx new_tag = gen_reg_rtx ( QImode ) ; unsigned HOST_WIDE_INT and_imm = ( HOST_WIDE_INT_1U << IX86_HWASAN_SHIFT ) - 1 ; emit_move_insn ( base_tag , ix86_memtag_extract_tag ( base , NULL_RTX ) ) ; emit_move_insn ( base_addr , ix86_memtag_untagged_pointer ( base , NULL_RTX ) ) ; emit_insn ( gen_add2_insn ( base_tag , gen_int_mode ( tag_offset , QImode ) ) ) ; emit_move_insn ( new_tag , base_tag ) ; emit_insn ( gen_andqi3 ( new_tag , new_tag , gen_int_mode ( and_imm , QImode ) ) ) ; emit_move_insn ( tagged_addr , ix86_memtag_set_tag ( base_addr , new_tag , NULL_RTX ) ) ; return plus_constant ( Pmode , tagged_addr , offset ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips MipsOptimizePICCall"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void mips16_load_branch_target ( rtx dest , rtx src ) { if ( TARGET_ABICALLS && ! TARGET_ABSOLUTE_ABICALLS ) { rtx page , low ; if ( mips_cfun_has_cprestore_slot_p ( ) ) mips_emit_move ( dest , mips_cprestore_slot ( dest , true ) ) ; else mips_emit_move ( dest , pic_offset_table_rtx ) ; page = mips_unspec_address ( src , SYMBOL_GOTOFF_PAGE ) ; low = mips_unspec_address ( src , SYMBOL_GOT_PAGE_OFST ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , PMODE_INSN ( gen_unspec_got , ( dest , page ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_LO_SUM ( Pmode , dest , low ) ) ) ; } else { src = mips_unspec_address ( src , SYMBOL_ABSOLUTE ) ; mips_emit_move ( dest , src ) ; } } </s>

Emit code to load LABEL_REF SRC into MIPS16 register DEST . This is called very late in mips_reorg , but the caller is required to run mips16_lay_out_constants on the result .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> StringRef getPassName ( ) const override { return SYSTEMZ_EXPAND_PSEUDO_NAME ; } </s>


<s> bool AArch64TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return CI -> isTailCall ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool AArch64TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { return CI -> isTailCall ( ) ; } </s>


<s> Register getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( ! Subtarget . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s>
static
void
mmix_asm_output_mi_thunk
(
FILE
*
stream
,
tree
fndecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
func
)
{
const
char
*
regname
=
reg_names
[
MMIX_FIRST_INCOMING_ARG_REGNUM
]
;
if
(
delta
>=
0
&&
delta
<
65536
)
fprintf
(
stream
,
"\tINCL %s,%d\n"
,
regname
,
(
int
)
delta
)
;
else
if
(
delta
<
0
&&
delta
>=
255
)
fprintf
(
stream
,
"\tSUBU %s,%s,%d\n"
,
regname
,
regname
,
(
int
)
delta
)
;
else
{
mmix_output_register_setting
(
stream
,
255
,
delta
,
1
)
;
fprintf
(
stream
,
"\tADDU %s,%s,$255\n"
,
regname
,
regname
)
;
}
fprintf
(
stream
,
"\tJMP "
)
;
assemble_name
(
stream
,
XSTR
(
XEXP
(
DECL_RTL
(
func
)
,
0
)
,
0
)
)
;
fprintf
(
stream
,
"\n"
)
;
}
</s>


<s> const TargetRegisterClass * X86RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & X86 :: CCRRegClass ) { if ( Is64Bit ) return & X86 :: GR64RegClass ; else return & X86 :: GR32RegClass ; } return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getArgOperand ( 3 ) -> getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> Register OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( Mips :: SP ) ) ; unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; Align Alignment = commonAlignment ( TFL -> getStackAlign ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Alignment ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
bool
AArch64AddressTypePromotion
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
)
return
false
;
if
(
F
.
isDeclaration
(
)
)
return
false
;
Func
=
&
F
;
ConsideredSExtType
=
Type
::
getInt64Ty
(
Func
->
getContext
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"*** "
<<
getPassName
(
)
<<
": "
<<
Func
->
getName
(
)
<<
'\n'
)
;
Instructions
SExtInsts
;
analyzeSExtension
(
SExtInsts
)
;
return
propagateSignExtension
(
SExtInsts
)
;
}
</s>


<s> int shift_insns_rtx ( rtx insn ) { rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; int shift_count = INTVAL ( XEXP ( set_src , 1 ) ) ; enum rtx_code shift_code = GET_CODE ( set_src ) ; switch ( shift_code ) { case ASHIFTRT : return ashiftrt_insns [ shift_count ] ; case LSHIFTRT : case ASHIFT : return shift_insns [ shift_count ] ; default : gcc_unreachable ( ) ; } } </s>

This is used in length attributes in sh.md to help compute the length of arbitrary constant shift instructions .


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; return LowerCall_Darwin_Or_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg 32 32 ISD::InputArg 32 PPC PPC PPC


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function * F = MF . getFunction ( ) ; if ( ! F -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F -> hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> void MipsSEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips::SP_64 Mips::SP


<s> static inline int sse_store_index ( machine_mode mode ) { if ( mode == E_HFmode ) mode = E_SFmode ; switch ( GET_MODE_SIZE ( mode ) ) { case 4 : return 0 ; case 8 : return 1 ; case 16 : return 2 ; case 32 : return 3 ; case 64 : return 4 ; default : return - 1 ; } } </s>

Return index of MODE in the sse load/store tables .


<s> unsigned getNumFixupKinds ( ) const override { return FISC :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: MEMBARRIER : return PerformMEMBARRIERCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineInstr
&
MI
)
const
{
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOAD_STACK_GUARD
)
{
expandLoadStackGuard
(
MI
)
;
MI
.
getParent
(
)
->
erase
(
MI
)
;
return
true
;
}
if
(
MI
.
getOpcode
(
)
==
ARM
::
MEMCPY
)
{
expandMEMCPY
(
MI
)
;
return
true
;
}
if
(
!
MI
.
isCopy
(
)
||
Subtarget
.
dontWidenVMOVS
(
)
||
!
Subtarget
.
hasFP64
(
)
)
return
false
;
Register
DstRegS
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
Register
SrcRegS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
.
definesRegister
(
DstRegD
,
TRI
)
||
MI
.
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
.
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
MI
)
;
MachineInstrBuilder
MIB
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
;
int
ImpDefIdx
=
MI
.
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
.
RemoveOperand
(
ImpDefIdx
)
;
MI
.
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
.
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
.
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
MI
.
getOperand
(
1
)
.
setIsUndef
(
)
;
MIB
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
.
getOperand
(
1
)
.
isKill
(
)
)
{
MI
.
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
.
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
Subtarget
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
IndirectTlsSegRefs
=
MF
.
getFunction
(
)
.
hasFnAttribute
(
"indirect-tls-seg-refs"
)
;
OptForSize
=
MF
.
getFunction
(
)
.
optForSize
(
)
;
OptForMinSize
=
MF
.
getFunction
(
)
.
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void X86RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Is64Bit ? X86 :: SUB64ri32 : X86 :: SUB32ri ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = ( Amount < 128 ) ? ( Is64Bit ? X86 :: ADD64ri8 : X86 :: ADD32ri8 ) : ( Is64Bit ? X86 :: ADD64ri32 : X86 :: ADD32ri ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { unsigned Opc = ( CalleeAmt < 128 ) ? ( Is64Bit ? X86 :: SUB64ri8 : X86 :: SUB32ri8 ) : ( Is64Bit ? X86 :: SUB64ri32 : X86 :: SUB32ri ) ; MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>


<s>
bool
SSEDomainFixPass
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
TII
=
static_cast
<
const
X86InstrInfo
*
>
(
MF
->
getTarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
MF
->
getTarget
(
)
.
getRegisterInfo
(
)
;
MBB
=
0
;
LiveRegs
=
0
;
Distance
=
0
;
assert
(
NumRegs
==
X86
::
VR128RegClass
.
getNumRegs
(
)
&&
"Bad regclass"
)
;
bool
anyregs
=
false
;
for
(
TargetRegisterClass
::
const_iterator
I
=
X86
::
VR128RegClass
.
begin
(
)
,
E
=
X86
::
VR128RegClass
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
MF
->
getRegInfo
(
)
.
isPhysRegUsed
(
*
I
)
)
{
anyregs
=
true
;
break
;
}
if
(
!
anyregs
)
return
false
;
MachineBasicBlock
*
Entry
=
MF
->
begin
(
)
;
SmallPtrSet
<
MachineBasicBlock
*
,
16
>
Visited
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
16
>
>
DFI
=
df_ext_begin
(
Entry
,
Visited
)
,
DFE
=
df_ext_end
(
Entry
,
Visited
)
;
DFI
!=
DFE
;
++
DFI
)
{
MBB
=
*
DFI
;
enterBasicBlock
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
MachineInstr
*
mi
=
I
;
if
(
mi
->
isDebugValue
(
)
)
continue
;
++
Distance
;
std
::
pair
<
uint16_t
,
uint16_t
>
domp
=
TII
->
GetSSEDomain
(
mi
)
;
if
(
domp
.
first
)
if
(
domp
.
second
)
visitSoftInstr
(
mi
,
domp
.
second
)
;
else
visitHardInstr
(
mi
,
domp
.
first
)
;
else
if
(
LiveRegs
)
visitGenericInstr
(
mi
)
;
}
if
(
LiveRegs
)
LiveOuts
.
insert
(
std
::
make_pair
(
MBB
,
LiveRegs
)
)
;
LiveRegs
=
0
;
}
for
(
LiveOutMap
::
const_iterator
i
=
LiveOuts
.
begin
(
)
,
e
=
LiveOuts
.
end
(
)
;
i
!=
e
;
++
i
)
delete
[
]
i
->
second
;
LiveOuts
.
clear
(
)
;
Avail
.
clear
(
)
;
Allocator
.
DestroyAll
(
)
;
return
false
;
}
</s>


<s> const char * AArch64TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ! Subtarget -> hasFPARMv8 ( ) ) return "r" ; if ( ConstraintVT . isFloatingPoint ( ) ) return "w" ; if ( ConstraintVT . isVector ( ) && ( ConstraintVT . getSizeInBits ( ) == 64 || ConstraintVT . getSizeInBits ( ) == 128 ) ) return "w" ; return "r" ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


"LoongArch didn't implement copyPhysReg"


<s> static const char * aarch64_mangle_type ( const_tree type ) { if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type ) , va_list_type ) ) return "St9__va_list" ; if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == 16 ) { if ( TYPE_MODE ( type ) == BFmode ) return "u6__bf16" ; else return "Dh" ; } if ( TYPE_NAME ( type ) != NULL ) { const char * res ; if ( ( res = aarch64_general_mangle_builtin_type ( type ) ) || ( res = aarch64_sve :: mangle_builtin_type ( type ) ) ) return res ; } return NULL ; } </s>


<s> LiveRange ( unsigned virtReg ) : LiveRange ( ) { virtRegs . insert ( virtReg ) ; } </s>

Constructs a new LiveRange object by copying segments and valnos from another LiveRange .


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s> void ARMHazardRecognizer :: Reset ( ) { LastMI = 0 ; FpMLxStalls = 0 ; ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : case CallingConv :: Swift : break ; } for ( const Argument & Arg : F -> args ( ) ) { if ( Arg . getArgNo ( ) >= 4 ) return false ; if ( Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: ByVal ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; for ( const Argument & Arg : F -> args ( ) ) { unsigned ArgNo = Arg . getArgNo ( ) ; unsigned SrcReg = GPRArgRegs [ ArgNo ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & Arg , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> void LC3bAsmPrinter :: emitFrameDirective ( ) { } </s>


"(cinsn 1 (set (mem/v:BLK (0|scratch:DI) [0  A8])\n"

"                (mem/v:BLK (reuse_rtx 0) [0  A8])\n"

"            ] UNSPEC_MEMORY_BLOCKAGE)))\n"

Test dumping an insn with repeated references to the same SCRATCH , to verify the rtx_reuse code .

"                (mem/v:BLK (reuse_rtx 0) [0  A8])\n"

"            ] UNSPEC_MEMORY_BLOCKAGE)))\n"


Return the probing interval for -fstack-clash-protection .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; unsigned LA = std :: max ( unsigned ( PostAlign ) , LogAlign ) ; if ( ! LA ) return PO ; return PO + UnknownPadding ( LA , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s>
unsigned
char
X86Subtarget
::
ClassifyGlobalReference
(
const
GlobalValue
*
GV
,
const
TargetMachine
&
TM
)
const
{
if
(
GV
->
hasDLLImportStorageClass
(
)
)
return
X86II
::
MO_DLLIMPORT
;
bool
isDecl
=
GV
->
isDeclarationForLinker
(
)
;
if
(
isPICStyleRIPRel
(
)
)
{
if
(
TM
.
getCodeModel
(
)
==
CodeModel
::
Large
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
->
hasDefaultVisibility
(
)
&&
(
isDecl
||
GV
->
isWeakForLinker
(
)
)
)
return
X86II
::
MO_GOTPCREL
;
}
else
if
(
!
isTargetWin64
(
)
)
{
assert
(
isTargetELF
(
)
&&
"Unknown rip-relative target"
)
;
if
(
!
GV
->
hasLocalLinkage
(
)
&&
GV
->
hasDefaultVisibility
(
)
)
return
X86II
::
MO_GOTPCREL
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isPICStyleGOT
(
)
)
{
if
(
GV
->
hasLocalLinkage
(
)
||
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_GOTOFF
;
return
X86II
::
MO_GOT
;
}
if
(
isPICStyleStubPIC
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_PIC_BASE_OFFSET
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
;
}
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
if
(
isPICStyleStubNoDynamic
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY
;
return
X86II
::
MO_NO_FLAG
;
}
return
X86II
::
MO_NO_FLAG
;
}
</s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> static unsigned bit_count ( unsigned HOST_WIDE_INT value ) { unsigned count = 0 ; while ( value ) { count ++ ; value &= value - 1 ; } return count ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - CHILD |ret | return address -- | | \ | | call saved | | registers | | / -- | | \ | | local | | variables frame pointer - > | | / -- | | \ | | outgoing | Decreasing | | arguments | addresses current stack pointer - > | | / | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V | |


<s> static bool xstormy16_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> const unsigned * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } static const unsigned CalleeSavedRegs [ ] = { ARM :: LR , ARM :: R11 , ARM :: R10 , ARM :: R9 , ARM :: R8 , ARM :: R7 , ARM :: R6 , ARM :: R5 , ARM :: R4 , ARM :: D15 , ARM :: D14 , ARM :: D13 , ARM :: D12 , ARM :: D11 , ARM :: D10 , ARM :: D9 , ARM :: D8 , 0 } ; static const unsigned DarwinCalleeSavedRegs [ ] = { ARM :: LR , ARM :: R7 , ARM :: R6 , ARM :: R5 , ARM :: R4 , ARM :: R11 , ARM :: R10 , ARM :: R8 , ARM :: D15 , ARM :: D14 , ARM :: D13 , ARM :: D12 , ARM :: D11 , ARM :: D10 , ARM :: D9 , ARM :: D8 , 0 } ; static const unsigned GhcCalleeSavedRegs [ ] = { 0 } ; return ghcCall ? GhcCalleeSavedRegs : STI . isTargetDarwin ( ) ? DarwinCalleeSavedRegs : CalleeSavedRegs ; } </s>


<s> static bool sparc_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { tree type = arg . type ; machine_mode mode = arg . mode ; if ( TARGET_ARCH32 ) return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) || mode == SCmode || GET_MODE_SIZE ( mode ) > 8 || ( type && VECTOR_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_TYPE_P ( type ) ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 16 ) || GET_MODE_SIZE ( mode ) > 16 ) ; } </s>

Handle the TARGET_PASS_BY_REFERENCE target hook . Specify whether to pass the argument by reference .


<s>
void
ELFTeeRISCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
unsigned
Size
=
getFixupKindSize
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
char
*
data
=
Data
+
Fixup
.
getOffset
(
)
;
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Cannot fixup unknown value."
)
;
case
1
:
llvm_unreachable
(
"Cannot fixup 1 byte value."
)
;
case
8
:
llvm_unreachable
(
"Cannot fixup 8 byte value."
)
;
case
4
:
case
2
:
llvm_unreachable
(
"Write Code here to fixup\n"
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void MipsAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned TargetOffset = getFixupKindInfo ( Kind ) . TargetOffset ; unsigned NumBytes = ( TargetOffset + getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= ( Value & Mask ) << TargetOffset ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>


<s> size_t parallel_elements ( rtx parallel_rtx ) { parallel_rtx = extract_pattern_from_insn ( parallel_rtx ) ; gcc_assert ( GET_CODE ( parallel_rtx ) == PARALLEL ) ; return XVECLEN ( parallel_rtx , 0 ) ; } </s>

Get the number of elements in a parallel rtx .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
)
return
CSR_AArch64_AAPCS_X18_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! Fn -> hasPersonalityFn ( ) || classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int64_t MinFixedObjOffset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI -> getObjectOffset ( I ) ) ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI -> CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; MF . getMMI ( ) . getWinEHFuncInfo ( Fn ) . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> int check_pic ( int i ) { switch ( flag_pic ) { case 1 : gcc_assert ( GET_CODE ( recog_data . operand [ i ] ) != SYMBOL_REF && ( GET_CODE ( recog_data . operand [ i ] ) != CONST || ( GET_CODE ( XEXP ( recog_data . operand [ i ] , 0 ) ) == MINUS && ( XEXP ( XEXP ( recog_data . operand [ i ] , 0 ) , 0 ) == global_offset_table ) && ( GET_CODE ( XEXP ( XEXP ( recog_data . operand [ i ] , 0 ) , 1 ) ) == CONST ) ) ) ) ; case 2 : default : return 1 ; } } </s>

Ensure that we are not using patterns that are not OK with PIC .


<s> rtl_opt_pass * make_pass_track_speculation ( gcc :: context * ctxt ) { return new pass_track_speculation ( ctxt ) ; } </s>


<s> unsigned postKnownBits ( unsigned LogAlign = 0 ) const { return std :: max ( LogAlign , internalKnownBits ( ) ) ; } </s>

Compute the number of known low bits of postOffset .


<s> static void load_lr_save ( int regno , rtx frame_reg_rtx , int offset ) { rtx mem = gen_frame_mem_offset ( Pmode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( Pmode , regno ) ; emit_move_insn ( reg , mem ) ; } </s>

Like cr , the move to lr instruction can be scheduled after the stack deallocation , but unlike cr , its stack frame save is still valid . So we only need to emit the cfa_restore on the correct instruction .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: GPR32RegClassID : case Mips :: GPR64RegClassID : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return 60 - TFI -> hasFP ( MF ) ; } case Mips :: DSPRRegClassID : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 64 ; case Mips :: AFGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool CSKYAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { switch ( Inst . getOpcode ( ) ) { default : return false ; case CSKY :: JBR32 : case CSKY :: JBT32 : case CSKY :: JBF32 : case CSKY :: JBSR32 : if ( ! STI . getFeatureBits ( ) [ CSKY :: Has2E3 ] ) return false ; return true ; case CSKY :: JBR16 : case CSKY :: JBT16 : case CSKY :: JBF16 : case CSKY :: LRW16 : case CSKY :: BR16 : return true ; } } </s>

Check whether the given instruction may need relaxation .


<s> static tree fold_build_vec_cmp ( tree_code code , tree type , tree arg0 , tree arg1 ) { tree cmp_type = truth_type_for ( type ) ; tree zero_vec = build_zero_cst ( type ) ; tree minus_one_vec = build_minus_one_cst ( type ) ; tree cmp = fold_build2 ( code , cmp_type , arg0 , arg1 ) ; return fold_build3 ( VEC_COND_EXPR , type , cmp , minus_one_vec , zero_vec ) ; } </s>

Helper function to handle the gimple folding of a vector compare operation . This sets up true/false vectors , and uses the VEC_COND_EXPR operation . CODE indicates which comparison is to be made . ( EQ , GT , ... ) . TYPE indicates the type of the result .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
.
startswith
(
".arch"
)
)
return
parseDirectiveArch
(
)
;
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".nops"
)
return
parseDirectiveNops
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalign"
)
return
parseDirectiveFPOStackAlign
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_pushreg"
)
return
parseDirectiveSEHPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_setframe"
)
return
parseDirectiveSEHSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_savereg"
)
return
parseDirectiveSEHSaveReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_savexmm"
)
return
parseDirectiveSEHSaveXMM
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_pushframe"
)
return
parseDirectiveSEHPushFrame
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool ARMFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( ARM :: FPCXTNS ) ; CSI . back ( ) . setRestored ( false ) ; } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void rs6000_expand_interleave ( rtx target , rtx op0 , rtx op1 , bool highp ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , 1 ) ; high = ( highp ? 0 : nelt / 2 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { perm . quick_push ( i + high ) ; perm . quick_push ( i + nelt + high ) ; } rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , perm ) ; } </s>


<s> enum nds32_16bit_address_type nds32_mem_format ( rtx op ) { machine_mode mode_test ; int val ; int regno ; if ( ! TARGET_16_BIT ) return ADDRESS_NOT_16BIT_FORMAT ; mode_test = GET_MODE ( op ) ; op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == REG && ( mode_test == SImode ) ) return ADDRESS_REG ; if ( GET_CODE ( op ) == REG && ( REGNO ( op ) < R8_REGNUM ) ) return ADDRESS_LO_REG_IMM3U ; if ( ( GET_CODE ( op ) == POST_INC ) && ( mode_test == SImode ) ) { regno = REGNO ( XEXP ( op , 0 ) ) ; if ( regno < 8 ) return ADDRESS_POST_INC_LO_REG_IMM3U ; } if ( ( GET_CODE ( op ) == POST_MODIFY ) && ( mode_test == SImode ) && ( REG_P ( XEXP ( XEXP ( op , 1 ) , 0 ) ) ) && ( CONST_INT_P ( XEXP ( XEXP ( op , 1 ) , 1 ) ) ) ) { regno = REGNO ( XEXP ( XEXP ( op , 1 ) , 0 ) ) ; val = INTVAL ( XEXP ( XEXP ( op , 1 ) , 1 ) ) ; if ( regno < 8 && val < 32 ) return ADDRESS_POST_INC_LO_REG_IMM3U ; } if ( ( GET_CODE ( op ) == PLUS ) && ( GET_CODE ( XEXP ( op , 0 ) ) == REG ) && ( GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ) { val = INTVAL ( XEXP ( op , 1 ) ) ; regno = REGNO ( XEXP ( op , 0 ) ) ; if ( regno > 7 && regno != SP_REGNUM && regno != FP_REGNUM ) return ADDRESS_NOT_16BIT_FORMAT ; switch ( mode_test ) { case QImode : if ( val >= 0 && val < 8 && regno < 8 ) return ADDRESS_LO_REG_IMM3U ; break ; case HImode : if ( val >= 0 && val < 16 && ( val % 2 == 0 ) && regno < 8 ) return ADDRESS_LO_REG_IMM3U ; break ; case SImode : case SFmode : case DFmode : if ( ( regno == FP_REGNUM ) && ( val >= 0 && val < 512 && ( val % 4 == 0 ) ) ) return ADDRESS_FP_IMM7U ; else if ( ( regno == SP_REGNUM ) && ( val >= 0 && val < 512 && ( val % 4 == 0 ) ) ) return ADDRESS_SP_IMM7U ; else if ( val >= 0 && val < 32 && ( val % 4 == 0 ) && regno < 8 ) return ADDRESS_LO_REG_IMM3U ; break ; default : break ; } } return ADDRESS_NOT_16BIT_FORMAT ; } </s>

A helper function to return memory format .


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , const function_arg_info & arg , bool incoming ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; const int regbase = incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ; int slotno , regno , padding ; tree type = arg . type ; machine_mode mode = arg . mode ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; bool named = arg . named ; slotno = function_arg_slotno ( cum , mode , type , named , incoming , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && VECTOR_INTEGER_TYPE_P ( type ) ) mclass = MODE_FLOAT ; if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( type && VECTOR_TYPE_P ( type ) && mode == BLKmode ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_vector_value ( size , slotno , named , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . else_blk ( ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


<s> bool isLegalMaskedScatter ( Type * DataType , MaybeAlign Alignment ) { return isVectorLaneType ( * getLaneType ( DataType ) ) ; } </s>

Return true if the target supports masked scatter .


<s> static bool nds32_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( ( GET_MODE_CLASS ( mode1 ) == MODE_INT && GET_MODE_CLASS ( mode2 ) == MODE_INT ) && GET_MODE_SIZE ( mode1 ) <= UNITS_PER_WORD && GET_MODE_SIZE ( mode2 ) <= UNITS_PER_WORD ) return true ; if ( GET_MODE_SIZE ( mode1 ) == GET_MODE_SIZE ( mode2 ) ) { if ( ( TARGET_FPU_SINGLE && ! TARGET_FPU_DOUBLE ) && ( mode1 == DFmode || mode2 == DFmode ) ) return false ; else return true ; } return false ; } </s>

Implement TARGET_MODES_TIEABLE_P . We can use general registers to tie QI/HI/SI modes together .


<s>
const
char
*
nds32_output_stack_pop
(
rtx
par_rtx
ATTRIBUTE_UNUSED
)
{
char
pattern
[
100
]
;
rtx
operands
[
3
]
;
int
rb_eh_data
=
cfun
->
machine
->
eh_return_data_first_regno
;
int
re_eh_data
=
cfun
->
machine
->
eh_return_data_last_regno
;
int
first_eh_data_regno
=
EH_RETURN_DATA_REGNO
(
0
)
;
int
rb_callee_saved
=
cfun
->
machine
->
callee_saved_first_gpr_regno
;
int
re_callee_saved
=
cfun
->
machine
->
callee_saved_last_gpr_regno
;
if
(
reg_mentioned_p
(
gen_rtx_REG
(
SImode
,
first_eh_data_regno
)
,
par_rtx
)
)
{
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_eh_data
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_eh_data
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop.s\t%s"
,
"%0, %1, { }"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
if
(
NDS32_V3PUSH_AVAILABLE_P
)
{
int
sp_adjust
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
sp_adjust
=
cfun
->
machine
->
local_size
+
cfun
->
machine
->
out_args_size
+
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
+
cfun
->
machine
->
callee_saved_fpr_regs_size
;
if
(
satisfies_constraint_Iu08
(
GEN_INT
(
sp_adjust
)
)
&&
NDS32_DOUBLE_WORD_ALIGN_P
(
sp_adjust
)
&&
!
cfun
->
calls_alloca
)
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
else
{
if
(
cfun
->
machine
->
callee_saved_first_fpr_regno
!=
SP_REGNUM
)
{
sp_adjust
=
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
+
cfun
->
machine
->
callee_saved_fpr_regs_size
;
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
}
else
{
operands
[
1
]
=
GEN_INT
(
0
)
;
}
}
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop25\t%%0, %%1"
)
;
}
else
{
int
pop_en4_only_p
=
0
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_callee_saved
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
if
(
!
cfun
->
machine
->
fp_size
&&
!
cfun
->
machine
->
gp_size
&&
!
cfun
->
machine
->
lp_size
&&
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
{
return
""
;
}
else
{
if
(
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
pop_en4_only_p
=
1
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop.s\t%s{%s%s%s }"
,
pop_en4_only_p
""
:
"%0, %1, "
,
cfun
->
machine
->
fp_size
" $fp"
:
""
,
cfun
->
machine
->
gp_size
" $gp"
:
""
,
cfun
->
machine
->
lp_size
" $lp"
:
""
)
;
}
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Function to output stack pop operation . We need to deal with normal stack pop multiple or stack v3pop .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


Implement TARGET_SETUP_INCOMING_VARARGS . On C-Sky the copy from the argument registers to the stack is emitted by the prologue hooks , so here we just have to note how much stack space to save .


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op . getNode ( ) , Op , Op0 , Op1 ) ) SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool ARMInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { if ( Opt == "reg-names-std" ) { DefaultAltIdx = ARM :: NoRegAltName ; return true ; } if ( Opt == "reg-names-raw" ) { DefaultAltIdx = ARM :: RegNamesRaw ; return true ; } return false ; } </s>

Customize the printer according to a command line option .

ARM ARM "reg-names-std" ARM::NoRegAltName "reg-names-raw" ARM::RegNamesRaw


"Only register-returns should be created by PCS"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const unsigned * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; callsEHReturn = ( MMI ? MMI -> callsEHReturn ( ) : false ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } static const unsigned GhcCalleeSavedRegs [ ] = { 0 } ; static const unsigned CalleeSavedRegs32Bit [ ] = { X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs32EHRet [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs64Bit [ ] = { X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegs64EHRet [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegsWin64 [ ] = { X86 :: RBX , X86 :: RBP , X86 :: RDI , X86 :: RSI , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: XMM6 , X86 :: XMM7 , X86 :: XMM8 , X86 :: XMM9 , X86 :: XMM10 , X86 :: XMM11 , X86 :: XMM12 , X86 :: XMM13 , X86 :: XMM14 , X86 :: XMM15 , 0 } ; if ( ghcCall ) { return GhcCalleeSavedRegs ; } else if ( Is64Bit ) { if ( IsWin64 ) return CalleeSavedRegsWin64 ; else return ( callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit ) ; } else { return ( callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit ) ; } } </s>


<s> static bool sh_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return true ; if ( MAYBE_BASE_REGISTER_RTX_P ( x , strict ) ) return true ; else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( x , 0 ) , strict ) ) return true ; else if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; if ( REG_P ( xop0 ) && REGNO ( xop0 ) == GBR_REG ) return gbr_displacement ( xop1 , mode ) ; if ( GET_MODE_SIZE ( mode ) <= 8 && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) && sh_legitimate_index_p ( mode , xop1 , TARGET_SH2A , false ) ) return true ; if ( GET_MODE_SIZE ( mode ) <= 4 || ( TARGET_FPU_DOUBLE && TARGET_FMOVD && mode == DFmode ) ) { if ( MAYBE_BASE_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_INDEX_REGISTER_RTX_P ( xop0 , strict ) ) return true ; if ( MAYBE_INDEX_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) ) return true ; } } return false ; } </s>

Recognize an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . Allow REG REG+disp REG+r0 REG++ -- REG GBR GBR+disp


<s> const MCExpr * X86TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s> void XNCMFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool MipsSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( hasMips64 ( ) ? & Mips :: CPU64RegsRegClass : & Mips :: CPURegsRegClass ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .

Mips Mips Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass


<s>
void
Thumb2HazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
ITBlockSize
)
{
ITBlockSize
;
}
else
if
(
Opcode
==
ARM
::
t2IT
)
{
unsigned
Mask
=
MI
->
getOperand
(
1
)
.
getImm
(
)
;
unsigned
NumTZ
=
CountTrailingZeros_32
(
Mask
)
;
assert
(
NumTZ
<=
3
&&
"Invalid IT mask!"
)
;
ITBlockSize
=
4
NumTZ
;
MachineBasicBlock
::
iterator
I
=
MI
;
for
(
unsigned
i
=
0
;
i
<
ITBlockSize
;
++
i
)
{
do
{
++
I
;
}
while
(
I
->
isDebugValue
(
)
)
;
ITBlockMIs
[
ITBlockSize
1
i
]
=
&
*
I
;
}
}
PostRAHazardRecognizer
::
EmitInstruction
(
SU
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool mep_ipipe_ldc_p ( rtx_insn * insn ) { rtx pat , src ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET ) { src = SET_SRC ( pat ) ; if ( GET_CODE ( src ) == UNSPEC || GET_CODE ( src ) == UNSPEC_VOLATILE ) src = XVECEXP ( src , 0 , 0 ) ; if ( REG_P ( src ) ) switch ( REGNO ( src ) ) { case PSW_REGNO : case LP_REGNO : case SAR_REGNO : case HI_REGNO : case LO_REGNO : return true ; } } return false ; } </s>

Return true if INSN is an ldc instruction that issues to the MeP-h1 integer pipeline . This is true for instructions that read from PSW , LP , SAR , HI and LO .


<s> int arm_const_double_rtx ( rtx x ) { REAL_VALUE_TYPE r ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return 0 ; if ( REAL_VALUES_EQUAL ( r , value_fp0 ) ) return 1 ; return 0 ; } </s>

Return TRUE if rtx X is a valid immediate FP constant .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) . getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ; } </s>


<s> int xstormy16_interrupt_function_p ( void ) { tree attributes ; if ( ! cfun ) return 0 ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return lookup_attribute ( "interrupt" , attributes ) != NULL_TREE ; } </s>

Return nonzero if the function is an interrupt function .


<s> rtx sfunc_uses_reg ( rtx_insn * insn ) { int i ; rtx pattern , part , reg_part , reg ; if ( ! NONJUMP_INSN_P ( insn ) ) return NULL_RTX ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return NULL_RTX ; for ( reg_part = NULL_RTX , i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return NULL_RTX ; reg = XEXP ( reg_part , 0 ) ; for ( i = XVECLEN ( pattern , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( part == reg_part || GET_CODE ( part ) == CLOBBER ) continue ; if ( reg_mentioned_p ( reg , ( ( GET_CODE ( part ) == SET && REG_P ( SET_DEST ( part ) ) ) ? SET_SRC ( part ) : part ) ) ) return NULL_RTX ; } return reg ; } </s>

If the instruction INSN is implemented by a special function , and we can positively find the register that is used to call the sfunc , and this register is not used anywhere else in this instruction - except as the destination of a set , return this register ; else , return 0 .


<s>
const
RegisterBank
&
X86RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
if
(
X86
::
GR8RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR16RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR32RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR64RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
LOW32_ADDR_ACCESSRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
LOW32_ADDR_ACCESS_RBPRegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
GPRRegBankID
)
;
if
(
X86
::
FR32XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
FR64XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR128XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR256XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR512RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
VECRRegBankID
)
;
llvm_unreachable
(
"Unsupported register kind yet."
)
;
}
</s>


<s> bool X86FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) || hasFP ( MF ) ) && MF . getFunction ( ) -> getCallingConv ( ) != CallingConv :: HiPE && ! MF . shouldSplitStack ( ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> HOST_WIDE_INT arm_compute_initial_elimination_offset ( unsigned int from , unsigned int to ) { arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; switch ( from ) { case ARG_POINTER_REGNUM : switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return 0 ; case FRAME_POINTER_REGNUM : return offsets -> soft_frame - offsets -> saved_args ; case ARM_HARD_FRAME_POINTER_REGNUM : return offsets -> frame - offsets -> saved_args - 4 ; case STACK_POINTER_REGNUM : return offsets -> outgoing_args - ( offsets -> saved_args + 4 ) ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; case FRAME_POINTER_REGNUM : switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return 0 ; case ARM_HARD_FRAME_POINTER_REGNUM : return offsets -> frame - offsets -> soft_frame ; case STACK_POINTER_REGNUM : return offsets -> outgoing_args - offsets -> soft_frame ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; default : gcc_unreachable ( ) ; } } </s>

Compute the distance from register FROM to register TO . These can be the arg pointer ( 26 ) , the soft frame pointer ( 25 ) , the stack pointer ( 13 ) or the hard frame pointer ( 11 ) . Typical stack layout looks like this : old stack pointer - > | | -- -- | | \ | | saved arguments for | | vararg functions | | / -- hard FP & arg pointer - > | | \ | | stack | | frame | | / -- | | \ | | call saved | | registers soft frame pointer - > | | / -- | | \ | | local | | variables | | / -- | | \ | | outgoing | | arguments current stack pointer - > | | / -- For a given funciton some or all of these stack compomnents may not be needed , giving rise to the possibility of eliminating some of the registers . The values returned by this function must reflect the behaviour of arm_expand_prologue ( ) and arm_compute_save_reg_mask ( ) . The sign of the number returned reflects the direction of stack growth , so the values are positive for all eliminations except from the soft frame pointer to the hard frame pointer .