<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Sparc
::
NumTargetFixupKinds
]
=
{
{
"fixup_sparc_call30"
,
2
,
30
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br22"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br19"
,
13
,
19
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br16_2"
,
10
,
2
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br16_14"
,
18
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_h44"
,
10
,
22
,
0
}
,
{
"fixup_sparc_m44"
,
22
,
10
,
0
}
,
{
"fixup_sparc_l44"
,
20
,
12
,
0
}
,
{
"fixup_sparc_hh"
,
10
,
22
,
0
}
,
{
"fixup_sparc_hm"
,
22
,
10
,
0
}
,
{
"fixup_sparc_pc22"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_pc10"
,
22
,
10
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_got22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_got10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_wplt30"
,
2
,
30
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_tls_gd_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_gd_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_gd_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_gd_call"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldm_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ldm_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ldm_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldm_call"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldo_hix22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ldo_lox10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ldo_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ie_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ie_ld"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_ldx"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_le_hix22"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_le_lox10"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void X86FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const MCCFIInstruction & CFIInst ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

Wraps up getting a CFI index and building a MachineInstr for it .


INSN is being issued in current solution . Account for its impact on the decoder model .


<s> unsigned getPrefLoopAlignment ( ) const { return PrefLoopAlignment ; } </s>


<s> static bool ix86_handle_option ( size_t code , const char * arg ATTRIBUTE_UNUSED , int value ) { switch ( code ) { case OPT_m3dnow : if ( ! value ) { target_flags &= ~ MASK_3DNOW_A ; target_flags_explicit |= MASK_3DNOW_A ; } return true ; case OPT_mmmx : if ( ! value ) { target_flags &= ~ ( MASK_3DNOW | MASK_3DNOW_A ) ; target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A ; } return true ; case OPT_msse : if ( ! value ) { target_flags &= ~ ( MASK_SSE2 | MASK_SSE3 ) ; target_flags_explicit |= MASK_SSE2 | MASK_SSE3 ; } return true ; case OPT_msse2 : if ( ! value ) { target_flags &= ~ MASK_SSE3 ; target_flags_explicit |= MASK_SSE3 ; } return true ; default : return true ; } } </s>


<s> static void seh_emit_push ( FILE * f , struct seh_frame_state * seh , rtx reg ) { unsigned int regno = REGNO ( reg ) ; gcc_checking_assert ( GENERAL_REGNO_P ( regno ) ) ; seh -> sp_offset += UNITS_PER_WORD ; if ( seh -> cfa_reg == stack_pointer_rtx ) seh -> cfa_offset += UNITS_PER_WORD ; fputs ( "\t.seh_pushreg\t" , f ) ; print_reg ( reg , 0 , f ) ; fputc ( '\n' , f ) ; } </s>

Emit an assembler directive to save REG via a PUSH .


<s> static MachineInstr * getDef ( unsigned Reg , const MachineRegisterInfo * MRI ) { if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return nullptr ; return MRI -> getUniqueVRegDef ( Reg ) ; } </s>

Get the concrete record with the specified name .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; bool IsRegCR ; if ( TRI -> isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> bool X86ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const X86Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; X86FL = STI -> getFrameLowering ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64MIPeepholeOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> isSSA ( ) ) return false ; bool Changed = false ; SmallSetVector < MachineInstr * , 8 > ToBeRemoved ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: ANDWrr : Changed = visitAND < uint32_t > ( MI , ToBeRemoved ) ; break ; case AArch64 :: ANDXrr : Changed = visitAND < uint64_t > ( MI , ToBeRemoved ) ; break ; case AArch64 :: ORRWrs : Changed = visitORR ( MI , ToBeRemoved ) ; } } } for ( MachineInstr * MI : ToBeRemoved ) MI -> eraseFromParent ( ) ; return Changed ; } </s>


<s>
const
Constant
*
X86TargetLowering
::
getTargetConstantFromLoad
(
LoadSDNode
*
LD
)
const
{
assert
(
LD
&&
"Unexpected null LoadSDNode"
)
;
return
getTargetConstantFromNode
(
LD
)
;
}
</s>

This method returns the constant pool value that will be loaded by LD .


<s> tree function_resolver :: resolve_uniform ( unsigned int nops , unsigned int nimm ) { unsigned int i , nargs ; type_suffix_index type ; if ( ! check_gp_argument ( nops + nimm , i , nargs ) || ( type = infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; i += 1 ; for ( ; i < nargs - nimm ; ++ i ) if ( ! require_matching_vector_type ( i , type ) ) return error_mark_node ; for ( ; i < nargs ; ++ i ) if ( ! require_integer_immediate ( i ) ) return error_mark_node ; return resolve_to ( mode_suffix_id , type ) ; } </s>

Resolve a ( possibly predicated ) function that takes NOPS like-typed vector arguments followed by NIMM integer immediates . Return the function decl of the resolved function on success , otherwise report a suitable error and return error_mark_node .


<s>
void
ARMBaseInstrInfo
::
buildOutlinedFrame
(
MachineBasicBlock
&
MBB
,
MachineFunction
&
MF
,
const
outliner
::
OutlinedFunction
&
OF
)
const
{
if
(
OF
.
FrameConstructionID
==
MachineOutlinerThunk
)
{
MachineInstr
*
Call
=
&
*
MBB
.
instr_end
(
)
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
unsigned
FuncOp
=
isThumb
2
:
0
;
unsigned
Opc
=
Call
->
getOperand
(
FuncOp
)
.
isReg
(
)
isThumb
ARM
::
tTAILJMPr
:
ARM
::
TAILJMPr
:
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBB
.
end
(
)
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
add
(
Call
->
getOperand
(
FuncOp
)
)
;
if
(
isThumb
&&
!
Call
->
getOperand
(
FuncOp
)
.
isReg
(
)
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
Call
->
eraseFromParent
(
)
;
}
auto
IsNonTailCall
=
[
]
(
MachineInstr
&
MI
)
{
return
MI
.
isCall
(
)
&&
!
MI
.
isReturn
(
)
;
}
;
if
(
llvm
::
any_of
(
MBB
.
instrs
(
)
,
IsNonTailCall
)
)
{
MachineBasicBlock
::
iterator
It
=
MBB
.
begin
(
)
;
MachineBasicBlock
::
iterator
Et
=
MBB
.
end
(
)
;
if
(
OF
.
FrameConstructionID
==
MachineOutlinerTailCall
||
OF
.
FrameConstructionID
==
MachineOutlinerThunk
)
Et
=
std
::
prev
(
MBB
.
end
(
)
)
;
if
(
!
MBB
.
isLiveIn
(
ARM
::
LR
)
)
MBB
.
addLiveIn
(
ARM
::
LR
)
;
bool
Auth
=
OF
.
Candidates
.
front
(
)
.
getMF
(
)
->
getInfo
<
ARMFunctionInfo
>
(
)
->
shouldSignReturnAddress
(
true
)
;
saveLROnStack
(
MBB
,
It
,
true
,
Auth
)
;
assert
(
OF
.
FrameConstructionID
!=
MachineOutlinerDefault
&&
"Can only fix up stack references once"
)
;
fixupPostOutline
(
MBB
)
;
restoreLRFromStack
(
MBB
,
Et
,
true
,
Auth
)
;
}
if
(
OF
.
FrameConstructionID
==
MachineOutlinerTailCall
||
OF
.
FrameConstructionID
==
MachineOutlinerThunk
)
return
;
BuildMI
(
MBB
,
MBB
.
end
(
)
,
DebugLoc
(
)
,
get
(
Subtarget
.
getReturnOpcode
(
)
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
if
(
OF
.
FrameConstructionID
!=
MachineOutlinerDefault
&&
OF
.
Candidates
[
0
]
.
CallConstructionID
!=
MachineOutlinerDefault
)
return
;
fixupPostOutline
(
MBB
)
;
}
</s>

Insert a custom frame for outlined functions .

ARM
ARM
2
0
ARM::tTAILJMPr
ARM::TAILJMPr
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::LR
ARM::LR
ARM
"Can only fix up stack references once"
ARMCC::AL
0


<s> bool SparcFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type = ARM_FT_UNKNOWN ; return machine ; } </s>

Functions to save and restore machine-specific function data .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"Unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
ParseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"Unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool mips_return_mode_in_fpr_p ( machine_mode mode ) { gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode ) ; return ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == V2SFmode || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) && GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) ; } </s>

Return true if the function return value MODE will get returned in a floating-point register .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
Mangler
*
Mang
,
MachineModuleInfo
*
MMI
,
unsigned
Encoding
,
MCStreamer
&
Streamer
)
const
{
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
return
MCSymbolRefExpr
::
Create
(
Mang
->
getSymbol
(
GV
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
"Can handle absptr encoding only"
ARM


<s> const TargetFrameLowering :: SpillSlot * ARMFrameLowering :: getCalleeSavedSpillSlots ( unsigned & NumEntries ) const { static const SpillSlot FixedSpillOffsets [ ] = { { ARM :: FPCXTNS , - 4 } } ; NumEntries = array_lengthof ( FixedSpillOffsets ) ; return FixedSpillOffsets ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> static int access_check ( const char * name , int mode ) { if ( mode == X_OK ) { struct stat st ; if ( stat ( name , & st ) < 0 || S_ISDIR ( st . st_mode ) ) return - 1 ; } return access ( name , mode ) ; } </s>

Check whether NAME can be accessed in MODE . This is like access , except that it never considers directories to be executable .


<s> static tree sparc_gimplify_va_arg ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { HOST_WIDE_INT size , rsize , align ; tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = 0 ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ROUND_UP ( size , UNITS_PER_WORD ) ; align = 0 ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= 2 * ( unsigned ) BITS_PER_WORD ) align = 2 * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == 0 ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold_build_pointer_plus_hwi ( incr , align - 1 ) ; incr = fold_convert ( sizetype , incr ) ; incr = fold_build2 ( BIT_AND_EXPR , sizetype , incr , size_int ( - align ) ) ; incr = fold_convert ( ptr_type_node , incr ) ; } gimplify_expr ( & incr , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = incr ; if ( BYTES_BIG_ENDIAN && size < rsize ) addr = fold_build_pointer_plus_hwi ( incr , rsize - size ) ; if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } else if ( align == 0 && TYPE_ALIGN ( type ) > BITS_PER_WORD ) { tree tmp = create_tmp_var ( type , "va_arg_tmp" ) ; tree dest_addr = build_fold_addr_expr ( tmp ) ; tree copy = build_call_expr ( builtin_decl_implicit ( BUILT_IN_MEMCPY ) , 3 , dest_addr , addr , size_int ( rsize ) ) ; TREE_ADDRESSABLE ( tmp ) = 1 ; gimplify_and_add ( copy , pre_p ) ; addr = dest_addr ; } else addr = fold_convert ( ptrtype , addr ) ; incr = fold_build_pointer_plus_hwi ( incr , rsize ) ; gimplify_assign ( valist , incr , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> virtual bool isReg ( ) const LLVM_OVERRIDE { return Kind == KindReg ; } </s>


<s> static void pa_output_function_prologue ( FILE * file ) { pa_output_function_label ( file ) ; remove_useless_addtr_insns ( 0 ) ; } </s>

On HP-PA , move-double insns between fpu and cpu need an 8-byte block of memory . If any fpu reg is used in the function , we allocate such a block here , at the bottom of the frame , just in case it 's needed . If this function is a leaf procedure , then we may choose not to do a `` save '' insn . The decision about whether or not to do this is made in regclass.c .


<s> static rtx xstormy16_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; mode = TYPE_MODE ( valtype ) ; PROMOTE_MODE ( mode , 0 , valtype ) ; return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ; } </s>


<s> static char * rs6000_offload_options ( void ) { if ( TARGET_64BIT ) return xstrdup ( "-foffload-abi=lp64" ) ; else return xstrdup ( "-foffload-abi=ilp32" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


Write the extra assembler code needed to declare a function properly .


<s>
bool
WinEHStatePass
::
runOnFunction
(
Function
&
F
)
{
StringRef
WinEHParentName
=
F
.
getFnAttribute
(
"wineh-parent"
)
.
getValueAsString
(
)
;
if
(
WinEHParentName
!=
F
.
getName
(
)
&&
!
WinEHParentName
.
empty
(
)
)
return
false
;
if
(
!
F
.
hasPersonalityFn
(
)
)
return
false
;
PersonalityFn
=
dyn_cast
<
Function
>
(
F
.
getPersonalityFn
(
)
->
stripPointerCasts
(
)
)
;
if
(
!
PersonalityFn
)
return
false
;
Personality
=
classifyEHPersonality
(
PersonalityFn
)
;
if
(
!
isFuncletEHPersonality
(
Personality
)
)
return
false
;
if
(
WinEHParentName
.
empty
(
)
)
{
bool
HasPads
=
false
;
for
(
BasicBlock
&
BB
:
F
)
{
if
(
BB
.
isEHPad
(
)
)
{
HasPads
=
true
;
break
;
}
}
if
(
!
HasPads
)
return
false
;
}
F
.
addFnAttr
(
"no-frame-pointer-elim"
,
"true"
)
;
emitExceptionRegistrationRecord
(
&
F
)
;
auto
*
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
std
::
unique_ptr
<
WinEHFuncInfo
>
FuncInfoPtr
;
if
(
!
MMI
)
FuncInfoPtr
.
reset
(
new
WinEHFuncInfo
(
)
)
;
WinEHFuncInfo
&
FuncInfo
=
*
(
MMI
&
MMI
->
getWinEHFuncInfo
(
&
F
)
:
FuncInfoPtr
.
get
(
)
)
;
FuncInfo
.
EHRegNode
=
RegNode
;
switch
(
Personality
)
{
default
:
llvm_unreachable
(
"unexpected personality function"
)
;
case
EHPersonality
::
MSVC_CXX
:
addCXXStateStores
(
F
,
FuncInfo
)
;
break
;
case
EHPersonality
::
MSVC_X86SEH
:
addSEHStateStores
(
F
,
FuncInfo
)
;
break
;
}
PersonalityFn
=
nullptr
;
Personality
=
EHPersonality
::
Unknown
;
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

X86
"wineh-parent"
"no-frame-pointer-elim"
"true"
"unexpected personality function"
X86


<s> void ARMBaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? 2 : 0 ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? ARM :: tTAILJMPr : ARM :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( ARM :: LR ) ) MBB . addLiveIn ( ARM :: LR ) ; saveLROnStack ( MBB , It ) ; emitCFIForLRSaveOnStack ( MBB , It ) ; restoreLRFromStack ( MBB , Et ) ; emitCFIForLRRestoreFromStack ( MBB , Et ) ; } if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) return ; BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

ARM ARM 2 0 ARM::tTAILJMPr ARM::TAILJMPr ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL ARM::LR ARM::LR ARMCC::AL


Add a function to the list of static constructors .


<s> static HARD_REG_SET ix86_zero_call_used_regs ( HARD_REG_SET need_zeroed_hardregs ) { HARD_REG_SET zeroed_hardregs ; bool all_sse_zeroed = false ; int all_st_zeroed_num = 0 ; bool all_mm_zeroed = false ; CLEAR_HARD_REG_SET ( zeroed_hardregs ) ; rtx zero_all_vec_insn = zero_all_vector_registers ( need_zeroed_hardregs ) ; if ( zero_all_vec_insn ) { emit_insn ( zero_all_vec_insn ) ; all_sse_zeroed = true ; } bool exit_with_mmx_mode = ( crtl -> return_rtx && ( MMX_REG_P ( crtl -> return_rtx ) ) ) ; if ( ! exit_with_mmx_mode ) { all_st_zeroed_num = zero_all_st_registers ( need_zeroed_hardregs ) ; if ( all_st_zeroed_num > 0 ) for ( unsigned int regno = FIRST_STACK_REG ; regno <= LAST_STACK_REG ; regno ++ ) if ( all_st_zeroed_num == 8 || ! ( ( all_st_zeroed_num >= 6 && regno == REGNO ( crtl -> return_rtx ) ) || ( all_st_zeroed_num == 6 && ( regno == ( REGNO ( crtl -> return_rtx ) + 1 ) ) ) ) ) SET_HARD_REG_BIT ( zeroed_hardregs , regno ) ; } else { unsigned int exit_mmx_regno = REGNO ( crtl -> return_rtx ) ; all_mm_zeroed = zero_all_mm_registers ( need_zeroed_hardregs , exit_mmx_regno ) ; if ( all_mm_zeroed ) for ( unsigned int regno = FIRST_MMX_REG ; regno <= LAST_MMX_REG ; regno ++ ) if ( regno != exit_mmx_regno ) SET_HARD_REG_BIT ( zeroed_hardregs , regno ) ; } for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( ! TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) continue ; if ( ! zero_call_used_regno_p ( regno , all_sse_zeroed , exit_with_mmx_mode && ! all_mm_zeroed ) ) continue ; SET_HARD_REG_BIT ( zeroed_hardregs , regno ) ; machine_mode mode = zero_call_used_regno_mode ( regno ) ; rtx reg = gen_rtx_REG ( mode , regno ) ; rtx tmp = gen_rtx_SET ( reg , CONST0_RTX ( mode ) ) ; switch ( mode ) { case E_SImode : if ( ! TARGET_USE_MOV0 || optimize_insn_for_size_p ( ) ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , tmp , clob ) ) ; } case E_V4SFmode : case E_HImode : case E_V2SImode : emit_insn ( tmp ) ; break ; default : gcc_unreachable ( ) ; } } return zeroed_hardregs ; } </s>

Generate a sequence of instructions that zero registers specified by NEED_ZEROED_HARDREGS . Return the ZEROED_HARDREGS that are actually zeroed .


<s> void CSKYTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s> static bool aarch64_hard_regno_call_part_clobbered ( rtx_insn * insn , unsigned int regno , machine_mode mode ) { bool simd_p = insn && CALL_P ( insn ) && aarch64_simd_call_p ( insn ) ; return FP_REGNUM_P ( regno ) && maybe_gt ( GET_MODE_SIZE ( mode ) , simd_p ? 16 : 8 ) ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The callee only saves the lower 64 bits of a 128-bit register . Tell the compiler the callee clobbers the top 64 bits when restoring the bottom 64 bits .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return ; Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 ) - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
int
AArch64AsmParser
::
tryParseRegister
(
)
{
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
unsigned
RegNum
=
MatchRegisterName
(
lowerCase
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
AArch64
::
FP
)
.
Case
(
"lr"
,
AArch64
::
LR
)
.
Case
(
"x31"
,
AArch64
::
XZR
)
.
Case
(
"w31"
,
AArch64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


"  Preloading operand for insn %d into r%d\n"

Convert operand OP in INSN . We should handle memory operands and uninitialized registers . All other register uses are converted during registers conversion .


<s> int vfp3_const_double_for_bits ( rtx x ) { const REAL_VALUE_TYPE * r ; if ( ! CONST_DOUBLE_P ( x ) ) return - 1 ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_NEGATIVE ( * r ) || REAL_VALUE_ISNAN ( * r ) || REAL_VALUE_ISINF ( * r ) || ! real_isinteger ( r , SFmode ) ) return - 1 ; HOST_WIDE_INT hwint = exact_log2 ( real_to_integer ( r ) ) ; if ( ! IN_RANGE ( hwint , 1 , 32 ) ) return - 1 ; return hwint ; } </s>

If X is a CONST_DOUBLE with a value that is a power of 2 whose log2 is in [ 1 , 32 ] , return that log2 . Otherwise return -1 . This is used in the patterns for vcvt.s32.f32 floating-point to fixed-point conversions .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
Suffix
=
"$stub"
;
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
==
0
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = X86FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const X86InstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; unsigned PC ; if ( TM -> getSubtarget < X86Subtarget > ( ) . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( & X86 :: GR32RegClass ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: MOVPC32r ) , PC ) . addImm ( 0 ) ; if ( TM -> getSubtarget < X86Subtarget > ( ) . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: ADD32ri ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , X86II :: MO_GOT_ABSOLUTE_ADDRESS ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void mark_swaps_for_removal ( swap_web_entry * insn_entry , unsigned int i ) { rtx insn = insn_entry [ i ] . insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; if ( insn_entry [ i ] . is_load ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; while ( link ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( use_insn ) ] . will_delete = 1 ; link = link -> next ; } } } else if ( insn_entry [ i ] . is_store ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REG ( use ) ) ; if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) continue ; struct df_link * link = DF_REF_CHAIN ( use ) ; while ( link ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( def_insn ) ] . will_delete = 1 ; link = link -> next ; } } } } </s>

Mark the xxswapdi instructions associated with permuting loads and stores for removal . Note that we only flag them for deletion here , as there is a possibility of a swap being reached from multiple loads , etc .


<s> rtx prepare_scc_operands ( enum rtx_code code ) { rtx t_reg = gen_rtx_REG ( SImode , T_REG ) ; enum rtx_code oldcode = code ; enum machine_mode mode ; switch ( code ) { case NE : gcc_unreachable ( ) ; case LT : code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) { rtx tmp = sh_compare_op0 ; sh_compare_op0 = sh_compare_op1 ; sh_compare_op1 = tmp ; } mode = GET_MODE ( sh_compare_op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( sh_compare_op1 ) ; sh_compare_op0 = force_reg ( mode , sh_compare_op0 ) ; if ( ( code != EQ && code != NE && ( sh_compare_op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && sh_compare_op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) sh_compare_op1 = force_reg ( mode , sh_compare_op1 ) ; if ( ( TARGET_SH4 || TARGET_SH2A ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ( mode == SFmode ? emit_sf_insn : emit_df_insn ) ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , t_reg , gen_rtx_fmt_ee ( code , SImode , sh_compare_op0 , sh_compare_op1 ) ) , gen_rtx_USE ( VOIDmode , get_fpscr_rtx ( ) ) ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , t_reg , gen_rtx_fmt_ee ( code , SImode , sh_compare_op0 , sh_compare_op1 ) ) ) ; return t_reg ; } </s>

Prepare the operands for an scc instruction ; make sure that the compare has been done .


<s> bool isThumb ( ) const { return IsThumb ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s>
bool
ARMCodeGenPrepare
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
||
DisableCGP
)
return
false
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
return
false
;
const
TargetMachine
&
TM
=
TPC
->
getTM
<
TargetMachine
>
(
)
;
ST
=
&
TM
.
getSubtarget
<
ARMSubtarget
>
(
F
)
;
bool
MadeChange
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Running on "
<<
F
.
getName
(
)
<<
"\n"
)
;
for
(
BasicBlock
&
BB
:
F
)
{
auto
&
Insts
=
BB
.
getInstList
(
)
;
for
(
auto
&
I
:
Insts
)
{
if
(
AllVisited
.
count
(
&
I
)
)
continue
;
if
(
isa
<
ICmpInst
>
(
I
)
)
{
auto
&
CI
=
cast
<
ICmpInst
>
(
I
)
;
if
(
CI
.
isSigned
(
)
||
!
isa
<
IntegerType
>
(
CI
.
getOperand
(
0
)
->
getType
(
)
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Searching from: "
<<
CI
<<
"\n"
)
;
for
(
auto
&
Op
:
CI
.
operands
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
Op
)
)
MadeChange
|=
TryToPromote
(
I
)
;
}
}
}
LLVM_DEBUG
(
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
{
dbgs
(
)
<<
F
;
report_fatal_error
(
"Broken function after type promotion"
)
;
}
)
;
}
if
(
MadeChange
)
LLVM_DEBUG
(
dbgs
(
)
<<
"After ARMCodeGenPrepare: "
<<
F
<<
"\n"
)
;
return
MadeChange
;
}
</s>

ARM
ARM
ARM
"ARM CGP: Running on "
"\n"
0
"ARM CGP: Searching from: "
"\n"
"Broken function after type promotion"
"After ARMCodeGenPrepare: "
"\n"


<s> static rtx rs6000_complex_function_value ( machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_SIZE ( inner ) ; if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= 4 ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= 8 ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + 1 ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } </s>

Return an RTX representing where to find the function value of a function returning MODE .


<s> static bool is_fmul_fmac_insn ( rtx_insn * insn , bool fmul_ok ) { enum attr_type t ; if ( ! NONDEBUG_INSN_P ( insn ) ) return false ; if ( recog_memoized ( insn ) < 0 ) return false ; t = get_attr_type ( insn ) ; return is_fmac_op ( t ) || ( fmul_ok && is_fmul_op ( t ) ) ; } </s>

Return whether INSN is an FMUL ( if FMUL_OK is true ) or FMADD/FMSUB instruction .


<s> static bool rs6000_attribute_takes_identifier_p ( const_tree attr_id ) { return is_attribute_p ( "altivec" , attr_id ) ; } </s>

Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain identifier as an argument , so the front end should n't look it up .


<s> bool isMem ( ) const override { return false ; } </s>


<s> static inline tree rs6000_builtin_type ( int id ) { tree t ; t = rs6000_builtin_types [ id < 0 ? ~ id : id ] ; return id < 0 ? build_pointer_type ( t ) : t ; } </s>

Convert a type stored into a struct altivec_builtin_types as ID , into a tree . The types are in rs6000_builtin_types : negative values create a pointer type for the type associated to ~ID . Note it is a logical NOT , rather than a negation , otherwise you can not represent a pointer type for ID 0 .


<s> static bool rs6000_emit_move_si_sf_subreg ( rtx dest , rtx source , machine_mode mode ) { if ( TARGET_DIRECT_MOVE_64BIT && ! lra_in_progress && ! reload_completed && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ; return true ; } } return false ; } </s>

Helper function to change moves with : ( SUBREG : SF ( REG : SI ) ) and ( SUBREG : SI ( REG : SF ) ) into separate UNSPEC insns . In the PowerPC architecture , scalar SFmode values are stored as DFmode values in the VSX registers . We need to convert the bits before we can use a direct move or operate on the bits in the vector register as an integer type . Skip things like ( set ( SUBREG : SI ( ... ) ( SUBREG : SI ( ... ) ) .


"empty class %qT parameter passing ABI "


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> void X86TargetLowering :: finalizeLowering ( MachineFunction & MF ) const { if ( hasCopyImplyingStackAdjustment ( MF ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setHasCopyImplyingStackAdjustment ( true ) ; } TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; auto IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == ".arch_extension" ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else if ( IsCOFF ) { if ( IDVal == ".seh_stackalloc" ) parseDirectiveSEHAllocStack ( Loc ) ; else if ( IDVal == ".seh_endprologue" ) parseDirectiveSEHPrologEnd ( Loc ) ; else if ( IDVal == ".seh_save_r19r20_x" ) parseDirectiveSEHSaveR19R20X ( Loc ) ; else if ( IDVal == ".seh_save_fplr" ) parseDirectiveSEHSaveFPLR ( Loc ) ; else if ( IDVal == ".seh_save_fplr_x" ) parseDirectiveSEHSaveFPLRX ( Loc ) ; else if ( IDVal == ".seh_save_reg" ) parseDirectiveSEHSaveReg ( Loc ) ; else if ( IDVal == ".seh_save_reg_x" ) parseDirectiveSEHSaveRegX ( Loc ) ; else if ( IDVal == ".seh_save_regp" ) parseDirectiveSEHSaveRegP ( Loc ) ; else if ( IDVal == ".seh_save_regp_x" ) parseDirectiveSEHSaveRegPX ( Loc ) ; else if ( IDVal == ".seh_save_lrpair" ) parseDirectiveSEHSaveLRPair ( Loc ) ; else if ( IDVal == ".seh_save_freg" ) parseDirectiveSEHSaveFReg ( Loc ) ; else if ( IDVal == ".seh_save_freg_x" ) parseDirectiveSEHSaveFRegX ( Loc ) ; else if ( IDVal == ".seh_save_fregp" ) parseDirectiveSEHSaveFRegP ( Loc ) ; else if ( IDVal == ".seh_save_fregp_x" ) parseDirectiveSEHSaveFRegPX ( Loc ) ; else if ( IDVal == ".seh_set_fp" ) parseDirectiveSEHSetFP ( Loc ) ; else if ( IDVal == ".seh_add_fp" ) parseDirectiveSEHAddFP ( Loc ) ; else if ( IDVal == ".seh_nop" ) parseDirectiveSEHNop ( Loc ) ; else if ( IDVal == ".seh_save_next" ) parseDirectiveSEHSaveNext ( Loc ) ; else if ( IDVal == ".seh_startepilogue" ) parseDirectiveSEHEpilogStart ( Loc ) ; else if ( IDVal == ".seh_endepilogue" ) parseDirectiveSEHEpilogEnd ( Loc ) ; else if ( IDVal == ".seh_trap_frame" ) parseDirectiveSEHTrapFrame ( Loc ) ; else if ( IDVal == ".seh_pushframe" ) parseDirectiveSEHMachineFrame ( Loc ) ; else if ( IDVal == ".seh_context" ) parseDirectiveSEHContext ( Loc ) ; else if ( IDVal == ".seh_clear_unwound_to_call" ) parseDirectiveSEHClearUnwoundToCall ( Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new ARMHazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget ) ; return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> unsigned AArch64TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) const { return ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / 128 ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"cannot use va_start in interrupt function"

Implement the stdarg/varargs va_start macro . STDARG_P is non-zero if this is stdarg.h instead of varargs.h . VALIST is the tree of the va_list variable to initialize . NEXTARG is the machine independent notion of the 'next ' argument after the variable arguments .


<s> static enum rtx_code ix86_fp_swap_condition ( enum rtx_code code ) { switch ( code ) { case GT : return TARGET_IEEE_FP ? UNKNOWN : UNLT ; case GE : return TARGET_IEEE_FP ? UNKNOWN : UNLE ; case UNLT : return TARGET_IEEE_FP ? UNKNOWN : GT ; case UNLE : return TARGET_IEEE_FP ? UNKNOWN : GE ; default : return swap_condition ( code ) ; } } </s>

Return a comparison we can do and that it is equivalent to swap_condition ( code ) apart possibly from orderedness . But , never change orderedness if TARGET_IEEE_FP , returning UNKNOWN in that case if necessary .


<s> virtual void initializePass ( ) { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( & MachinePipelinerID ) ; addPass ( createMVETPAndVPTOptimisationsPass ( ) ) ; addPass ( createMLxExpansionPass ( ) ) ; if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool PPCSubtarget :: enableSubRegLiveness ( ) const { return UseSubRegLiveness ; } </s>

Enable tracking of subregister liveness in register allocator .


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT
:
return
":got:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL
:
return
":gottprel:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
case
VK_GOTOFF
:
return
":gotoff:"
;
case
VK_GOTOFF_G3
:
return
":gotoff_g3:"
;
case
VK_GOTOFF_G2
:
return
":gotoff_g2:"
;
case
VK_GOTOFF_G2_NC
:
return
":gotoff_g2_nc:"
;
case
VK_GOTOFF_G1
:
return
":gotoff_g1:"
;
case
VK_GOTOFF_G1_NC
:
return
":gotoff_g1_nc:"
;
case
VK_GOTOFF_G0
:
return
":gotoff_g0:"
;
case
VK_GOTOFF_G0_NC
:
return
":gotoff_g0_nc:"
;
case
VK_SEC_HI12
:
return
":sec_hi12:"
;
case
VK_SEC_LO12
:
return
":sec_lo12:"
;
case
VK_SEC
:
return
":sec:"
;
case
VK_SEC_G3
:
return
":sec_g3:"
;
case
VK_SEC_G2
:
return
":sec_g2:"
;
case
VK_SEC_G2_NC
:
return
":sec_g2_nc:"
;
case
VK_SEC_G1
:
return
":sec_g1:"
;
case
VK_SEC_G1_NC
:
return
":sec_g1_nc:"
;
case
VK_SEC_G0
:
return
":sec_g0:"
;
case
VK_SEC_G0_NC
:
return
":sec_g0_nc:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> static inline int desc_is_active ( unsigned char qp , unw_word t , struct unw_state_record * sr ) { if ( sr -> when_target <= sr -> region_start + MIN ( ( int ) t , sr -> region_len - 1 ) ) return 0 ; if ( qp > 0 ) { if ( ( sr -> pr_val & ( 1UL << qp ) ) == 0 ) return 0 ; sr -> pr_mask |= ( 1UL << qp ) ; } return 1 ; } </s>


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; switch ( MI -> getOpcode ( ) ) { case SystemZ :: Return : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R14D ) ; break ; case SystemZ :: CallBRASL : LoweredMI = MCInstBuilder ( SystemZ :: BRASL ) . addReg ( SystemZ :: R14D ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBASR : LoweredMI = MCInstBuilder ( SystemZ :: BASR ) . addReg ( SystemZ :: R14D ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; break ; case SystemZ :: CallJG : LoweredMI = MCInstBuilder ( SystemZ :: JG ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBR : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R1D ) ; break ; case SystemZ :: IILF64 : LoweredMI = MCInstBuilder ( SystemZ :: IILF ) . addReg ( SystemZMC :: getRegAsGR32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: IIHF64 : LoweredMI = MCInstBuilder ( SystemZ :: IIHF ) . addReg ( SystemZMC :: getRegAsGRH32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: RISBHH : case SystemZ :: RISBHL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBHG ) ; break ; case SystemZ :: RISBLH : case SystemZ :: RISBLL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBLG ) ; break ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRILow ( MI , SystemZ :: NAME ) ; break LOWER_LOW ( IILL ) ; LOWER_LOW ( IILH ) ; LOWER_LOW ( NILL ) ; LOWER_LOW ( NILH ) ; LOWER_LOW ( NILF ) ; LOWER_LOW ( OILL ) ; LOWER_LOW ( OILH ) ; LOWER_LOW ( OILF ) ; LOWER_LOW ( XILF ) ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRIHigh ( MI , SystemZ :: NAME ) ; break LOWER_HIGH ( IIHL ) ; LOWER_HIGH ( IIHH ) ; LOWER_HIGH ( NIHL ) ; LOWER_HIGH ( NIHH ) ; LOWER_HIGH ( NIHF ) ; LOWER_HIGH ( OIHL ) ; LOWER_HIGH ( OIHH ) ; LOWER_HIGH ( OIHF ) ; LOWER_HIGH ( XIHF ) ; default : Lower . lower ( MI , LoweredMI ) ; break ; } OutStreamer . EmitInstruction ( LoweredMI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool PPCLoopDataPrefetch :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
unsigned
Size
=
getFixupKindSize
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
(
Size
==
0
||
isIntN
(
Size
*
8
+
1
,
Value
)
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void do_add3 ( rtx dest , rtx src1 , rtx src2 ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_adddi3 ( dest , src1 , src2 ) ) ; else emit_insn ( gen_addsi3 ( dest , src1 , src2 ) ) ; } </s>

Emit an add of the proper mode for DEST . DEST is the destination register for the add . SRC1 is the first add input . SRC2 is the second add input . Computes DEST = SRC1+SRC2 .


<s> bool ARMBaseRegisterInfo :: isInlineAsmReadOnlyReg ( const MachineFunction & MF , unsigned PhysReg ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , ARM :: PC ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved . test ( PhysReg ) ; } </s>

Returns true if PhysReg can not be written to in inline asm statements .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case 'x' : return C_RegisterClass ; case 'R' : return C_Memory ; } } if ( Constraint == "ZC" ) return C_Memory ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> unsigned char AArch64Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) && ! GV -> hasInternalLinkage ( ) ) return AArch64II :: MO_GOT ; auto * F = dyn_cast < Function > ( GV ) ; if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream , raw_ostream & cStream ) const { InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = 0 ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , loggerFn , ( void * ) & vStream , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: CPURegsRegClassID : case Mips :: CPU64RegsRegClassID : case Mips :: DSPRegsRegClassID : { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 32 ; case Mips :: AFGR64RegClassID : return 16 ; case Mips :: FGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> TargetLoweringBase :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { Type * MemType = SI -> getValueOperand ( ) -> getType ( ) ; bool NoImplicitFloatOps = SI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE1 ( ) || Subtarget . hasX87 ( ) ) ) return AtomicExpansionKind :: None ; return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: Expand : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> bool X86TargetLowering :: isBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: ANDNP : case X86ISD :: PCMPGT : case X86ISD :: FMAX : case X86ISD :: FMIN : case X86ISD :: FANDN : return true ; } return TargetLoweringBase :: isBinOp ( Opcode ) ; } </s>

Add x86-specific opcodes to the default list .


<s> bool FISCTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_FISC ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) return false ; return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SPARC Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void loongarch_conditional_register_usage ( void ) { if ( ! TARGET_HARD_FLOAT ) accessible_reg_set &= ~ ( reg_class_contents [ FP_REGS ] | reg_class_contents [ FCC_REGS ] ) ; } </s>


<s> void AArch64TargetStreamer :: emitCurrentConstantPool ( ) { ConstantPools -> emitForCurrentSection ( Streamer ) ; } </s>

Callback used to implement the .ltorg directive .


<s>
static
void
process_cfa_adjust_cfa
(
FILE
*
out_file
,
rtx
pat
,
rtx
insn
,
bool
unwind
,
bool
frame
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
if
(
dest
==
stack_pointer_rtx
)
{
if
(
GET_CODE
(
src
)
==
PLUS
)
{
rtx
op0
=
XEXP
(
src
,
0
)
;
rtx
op1
=
XEXP
(
src
,
1
)
;
gcc_assert
(
op0
==
dest
&&
GET_CODE
(
op1
)
==
CONST_INT
)
;
if
(
INTVAL
(
op1
)
<
0
)
{
gcc_assert
(
!
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.fframe "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
INTVAL
(
op1
)
)
;
}
else
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
}
else
{
gcc_assert
(
src
==
hard_frame_pointer_rtx
)
;
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
}
}
else
if
(
dest
==
hard_frame_pointer_rtx
)
{
gcc_assert
(
src
==
stack_pointer_rtx
)
;
gcc_assert
(
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.vframe r%d\n"
,
ia64_debugger_regno
(
REGNO
(
dest
)
)
)
;
}
else
gcc_unreachable
(
)
;
}
</s>

This function processes a SET pattern for REG_CFA_ADJUST_CFA .


"rs6000_secondary_reload_inner:%d, type = %s\n"

Better tracing for rs6000_secondary_reload_inner .


<s> static const char * get_decl_name ( tree fn ) { tree name ; if ( ! fn ) return "<null>" ; name = DECL_NAME ( fn ) ; if ( ! name ) return "<no-name>" ; return IDENTIFIER_POINTER ( name ) ; } </s>

Helper function for printing the function name when debugging .


<s> static unsigned int sparc_min_arithmetic_precision ( void ) { return 32 ; } </s>


<s> unsigned Emitter < CodeEmitter > :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) { if ( MO . isReg ( ) ) return ARMRegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , ARM :: reloc_arm_branch , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , ARM :: reloc_arm_branch ) ; else if ( MO . isCPI ( ) ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Reloc = ( ( TID . TSFlags & ARMII :: FormMask ) == ARMII :: VFPLdStFrm ) ? ARM :: reloc_arm_vfp_cp_entry : ARM :: reloc_arm_cp_entry ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , ARM :: reloc_arm_relative ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , ARM :: reloc_arm_branch ) ; else { cerr << MO ; llvm_unreachable ( 0 ) ; } return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool VEInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { VECC :: CondCodes CC = static_cast < VECC :: CondCodes > ( Cond [ 0 ] . getImm ( ) ) ; Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( CC ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .

VE VE VECC::CondCodes VECC::CondCodes 0 0


<s> bool X86TargetLowering :: shouldFoldSelectWithIdentityConstant ( unsigned Opcode , EVT VT ) const { if ( ! Subtarget . hasAVX512 ( ) ) return false ; if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) ) return false ; if ( ! VT . isVector ( ) ) return false ; return true ; } </s>

Return true if pulling a binary operation into a select with an identity constant is profitable .


<s> rtx aarch64_mask_from_zextract_ops ( rtx width , rtx pos ) { gcc_assert ( CONST_INT_P ( width ) ) ; gcc_assert ( CONST_INT_P ( pos ) ) ; unsigned HOST_WIDE_INT mask = ( ( unsigned HOST_WIDE_INT ) 1 << UINTVAL ( width ) ) - 1 ; return GEN_INT ( mask << UINTVAL ( pos ) ) ; } </s>

Return the bitmask CONST_INT to select the bits required by a zero extract operation of width WIDTH at bit position POS .


<s> void function_expander :: add_address_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 , true ) ; create_address_operand ( & m_ops . last ( ) , x ) ; } </s>

Add an address operand with value X . The static operand data says what mode and form the address must have .


<s> MachineBasicBlock :: iterator SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; if ( Size ) emitSPAdjustment ( MF , MBB , I , Size , SP :: ADDrr , SP :: ADDri ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Sparc Sparc 0 SP::ADJCALLSTACKDOWN SP SP::ADDrr SP::ADDri


<s>
void
pa_asm_output_aligned_bss
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
switch_to_section
(
bss_section
)
;
ASM_OUTPUT_TYPE_DIRECTIVE
(
stream
,
name
,
"object"
)
;
ASM_OUTPUT_SIZE_DIRECTIVE
(
stream
,
name
,
size
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_LABEL
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.block "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
size
)
;
}
</s>

This function places uninitialized global data in the bss section . The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this function on the SOM port to prevent uninitialized global data from being placed in the data section .

pa
"object"
"\t.align %u\n"
"\t.block "
"\n"


<s> int aarch64_simd_attr_length_move ( rtx_insn * insn ) { machine_mode mode ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ 0 ] ) && REG_P ( recog_data . operand [ 1 ] ) ) { mode = GET_MODE ( recog_data . operand [ 0 ] ) ; switch ( mode ) { case OImode : return 8 ; case CImode : return 12 ; case XImode : return 16 ; default : gcc_unreachable ( ) ; } } return 4 ; } </s>

Compute and return the length of aarch64_simd_mov < mode > , where < mode > is one of VSTRUCT modes : OI , CI or XI .


<s> static bool is_load_insn ( rtx insn , rtx * load_mem ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; if ( CALL_P ( insn ) ) return false ; return is_load_insn1 ( PATTERN ( insn ) , load_mem ) ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return DLX :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> StringRef getSymbol ( ) const { return S ; } </s>

Get the target address and flags for the named symbol .


<s> bool isBarrier ( ) const { return Kind == k_Barrier && ! getBarriernXSModifier ( ) ; } </s>

Tests if this is an Order dependence that is marked as a barrier .


<s> static int arm_sched_reorder ( FILE * file , int verbose , rtx_insn * * ready , int * n_readyp , int clock ) { switch ( arm_tune ) { case TARGET_CPU_cortexa7 : cortexa7_sched_reorder ( file , verbose , ready , n_readyp , clock ) ; break ; default : break ; } return arm_issue_rate ( ) ; } </s>


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( ( TSFlags & X86II :: NOTRACK ) || ( Flags & X86 :: IP_HAS_NOTRACK ) ) OS << "\tnotrack\t" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONMoveFixPass ( ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool MipsCCState :: originalTypeIsVectorFloat ( const Type * Ty ) { if ( Ty -> isVectorTy ( ) && Ty -> isFPOrFPVectorTy ( ) ) return true ; return false ; } </s>

Return true if the original type was vXfXX / vXfXX .


"parameter passing for argument of type %qT "

"when C++17 is enabled changed to match C++14 "

"with %<[[no_unique_address]]%> members "

"ELFv2 parameter passing for an argument "

"containing zero-width bit fields but that is "

"otherwise a homogeneous aggregate was "

If an argument , whose type is described by TYPE and MODE , is a homogeneous float or vector aggregate that shall be passed in FP/vector registers according to the ELFv2 ABI , return the homogeneous element mode in * ELT_MODE and the number of elements in * N_ELTS , and return TRUE . Otherwise , set * ELT_MODE to MODE and * N_ELTS to 1 , and return FALSE .


<s> opt_machine_mode arm_mode_to_pred_mode ( machine_mode mode ) { switch ( GET_MODE_NUNITS ( mode ) ) { case 16 : return V16BImode ; case 8 : return V8BImode ; case 4 : return V4BImode ; } return opt_machine_mode ( ) ; } </s>

Return the mode for the MVE vector of predicates corresponding to MODE .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool MipsTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return nullptr ; MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ; CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return CommutedMI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

ARM ARM ARM::MOVCCr ARM::t2MOVCCr 0 ARMCC::CondCodes ARMCC::AL ARM::CPSR ARMCC::getOppositeCondition


<s> static void ix86_pad_returns ( void ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) { basic_block bb = e -> src ; rtx_insn * ret = BB_END ( bb ) ; rtx_insn * prev ; bool replace = false ; if ( ! JUMP_P ( ret ) || ! ANY_RETURN_P ( PATTERN ( ret ) ) || optimize_bb_for_size_p ( bb ) ) continue ; for ( prev = PREV_INSN ( ret ) ; prev ; prev = PREV_INSN ( prev ) ) if ( active_insn_p ( prev ) || LABEL_P ( prev ) ) break ; if ( prev && LABEL_P ( prev ) ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( EDGE_FREQUENCY ( e ) && e -> src -> index >= 0 && ! ( e -> flags & EDGE_FALLTHRU ) ) { replace = true ; break ; } } if ( ! replace ) { prev = prev_active_insn ( ret ) ; if ( prev && ( ( JUMP_P ( prev ) && any_condjump_p ( prev ) ) || CALL_P ( prev ) ) ) replace = true ; if ( ! prev && ! optimize_function_for_size_p ( cfun ) ) replace = true ; } if ( replace ) { emit_jump_insn_before ( gen_simple_return_internal_long ( ) , ret ) ; delete_insn ( ret ) ; } } } </s>

AMD Athlon works faster when RET is not destination of conditional jump or directly preceded by other jump instruction . We avoid the penalty by inserting NOP just before the RET instructions in such cases .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; if ( ! STI . isThumb2 ( ) ) return false ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> static bool is_fmac_op ( enum attr_type t ) { return ( t == TYPE_FMACS ) || ( t == TYPE_FMACD ) || ( t == TYPE_NEON_FP_MLA_S ) ; } </s>

Return whether T is the attribute of a FMADD/FMSUB-like instruction .


<s>
void
X86AsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
bool
is16BitMode
=
STI
.
getFeatureBits
(
)
[
X86
::
Mode16Bit
]
;
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
,
is16BitMode
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> int sh_dynamicalize_shift_p ( rtx count ) { return shift_insns [ INTVAL ( count ) ] > 1 + SH_DYNAMIC_SHIFT_COST ; } </s>

Return true if it is potentially beneficial to use a dynamic shift instruction ( shad / shar ) instead of a combination of 1/2/8/16 shift instructions for the specified shift count . If dynamic shifts are not available , always return false .


<s> enum aarch64_symbol_type aarch64_classify_tls_symbol ( rtx x ) { enum tls_model tls_kind = tls_symbolic_operand_type ( x ) ; switch ( tls_kind ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : return TARGET_TLS_DESC ? SYMBOL_SMALL_TLSDESC : SYMBOL_SMALL_TLSGD ; case TLS_MODEL_INITIAL_EXEC : switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : return SYMBOL_TINY_TLSIE ; default : return SYMBOL_SMALL_TLSIE ; } case TLS_MODEL_LOCAL_EXEC : if ( aarch64_tls_size == 12 ) return SYMBOL_TLSLE12 ; else if ( aarch64_tls_size == 24 ) return SYMBOL_TLSLE24 ; else if ( aarch64_tls_size == 32 ) return SYMBOL_TLSLE32 ; else if ( aarch64_tls_size == 48 ) return SYMBOL_TLSLE48 ; else gcc_unreachable ( ) ; case TLS_MODEL_EMULATED : case TLS_MODEL_NONE : return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } </s>

Classify a TLS symbol into one of the TLS kinds .


<s> static inline bool mode_supports_pre_incdec_p ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_PRE_INCDEC ) != 0 ) ; } </s>

Helper function to say whether a mode supports PRE_INC or PRE_DEC .


<s> static HOST_WIDE_INT get_label_padding ( rtx label ) { HOST_WIDE_INT align , min_insn_size ; align = 1 << label_to_alignment ( label ) ; min_insn_size = TARGET_THUMB ? 2 : 4 ; return align > min_insn_size ? align - min_insn_size : 0 ; } </s>

Return the maximum amount of padding that will be inserted before label LABEL .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII , Out ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; bool tDest = ARM :: tGPRRegClass . contains ( DestReg ) ; bool tSrc = ARM :: tGPRRegClass . contains ( SrcReg ) ; unsigned Opc = ARM :: tMOVgpr2gpr ; if ( tDest && tSrc ) Opc = ARM :: tMOVr ; else if ( tSrc ) Opc = ARM :: tMOVtgpr2gpr ; else if ( tDest ) Opc = ARM :: tMOVgpr2tgpr ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>

ARM ARM::GPRRegClass ARM ARM::tGPRRegClass ARM::tGPRRegClass ARM::tMOVgpr2gpr ARM::tMOVr ARM::tMOVtgpr2gpr ARM::tMOVgpr2tgpr


"%<__delay_cycles%> only takes constant arguments"

"%<__delay_cycles%> only takes non-negative cycle counts"

"%<__delay_cycles%> is limited to 32-bit loop counts"

Emit a sequence of one or more delay_cycles_X insns , in order to generate code that delays exactly ARG cycles .


<s> bool SystemZTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void arm_emit_fp16_const ( rtx c ) { long bits ; bits = real_to_target ( NULL , CONST_DOUBLE_REAL_VALUE ( c ) , HFmode ) ; if ( WORDS_BIG_ENDIAN ) assemble_zeros ( 2 ) ; assemble_integer ( GEN_INT ( bits ) , 2 , BITS_PER_WORD , 1 ) ; if ( ! WORDS_BIG_ENDIAN ) assemble_zeros ( 2 ) ; } </s>

Emit a fp16 constant appropriately padded to occupy a 4-byte word . HFmode constant pool entries are actually loaded with ldr .


<s> OperandMatchResultTy PPCAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; int64_t IntVal ; if ( MatchRegisterName ( RegNo , IntVal ) ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named , bool incoming_p ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; slotno = function_arg_slotno ( cum , mode , type , named , incoming_p , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 16 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST + 2 * slotno ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) { if ( ( regno - SPARC_FP_ARG_FIRST ) >= SPARC_INT_ARG_MAX * 2 ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ) ) ; else return reg ; } else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming_p ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


<s> TargetTransformInfo SystemZTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( SystemZTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> int regs_used ( rtx x , int is_dest ) { enum rtx_code code ; const char * fmt ; int i , used = 0 ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( x ) + is_dest ) ) ; return 0 ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( GET_CODE ( y ) != REG ) break ; if ( REGNO ( y ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return 0 ; } case SET : return regs_used ( SET_SRC ( x ) , 0 ) | regs_used ( SET_DEST ( x ) , 16 ) ; case RETURN : return 0x00ffff00 ; case CLOBBER : is_dest = 1 ; break ; case MEM : is_dest = 0 ; break ; case CALL : used |= 0x00ff00f0 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return used ; } </s>

Given a X , a pattern of an insn or a part of it , return a mask of used general registers . Bits 0 .. 15 mean that the respective registers are used as inputs in the instruction . Bits 16 .. 31 mean that the registers 0 .. 15 , respectively , are used as outputs , or are clobbered . IS_DEST should be set to 16 if X is the destination of a SET , else to 0 .


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static bool loongarch_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return loongarch_const_insns ( x ) > 0 ; } </s>


<s> bool hasAndNotCompare ( SDValue ) const override { return true ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ( ! SYMBOL_REF_LOCAL_P ( x ) || ( SYMBOL_REF_DECL ( x ) ? DECL_WEAK ( SYMBOL_REF_DECL ( x ) ) : 0 ) ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , MVT VT ) const { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && VT . getSizeInBits ( ) == 128 ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT ) || isCommutedSHUFPMask ( Mask , VT ) ) ; } return false ; } </s>


<s> void ix86_expand_reduc ( rtx ( * fn ) ( rtx , rtx , rtx ) , rtx dest , rtx in ) { rtx half , dst , vec = in ; machine_mode mode = GET_MODE ( in ) ; int i ; if ( TARGET_SSE4_1 && mode == V8HImode && fn == gen_uminv8hi3 ) { emit_insn ( gen_sse4_1_phminposuw ( dest , in ) ) ; return ; } for ( i = GET_MODE_BITSIZE ( mode ) ; i > GET_MODE_UNIT_BITSIZE ( mode ) ; i >>= 1 ) { half = gen_reg_rtx ( mode ) ; emit_reduc_half ( half , vec , i ) ; if ( i == GET_MODE_UNIT_BITSIZE ( mode ) * 2 ) dst = dest ; else dst = gen_reg_rtx ( mode ) ; emit_insn ( fn ( dst , half , vec ) ) ; vec = dst ; } } </s>

Expand a vector reduction . FN is the binary pattern to reduce ; DEST is the destination ; IN is the input vector .


<s> static bool mips_vector_mode_supported_p ( enum machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : return TARGET_DSP ; default : return false ; } } </s>

Target hook for vector_mode_supported_p .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { if ( ! isLegalAddressImmediate ( AM . BaseOffs , getValueType ( Ty , true ) , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; int Scale = AM . Scale ; switch ( getValueType ( Ty ) . getSimpleVT ( ) ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : case MVT :: i64 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( AM . Scale & 1 ) return false ; return isPowerOf2_32 ( AM . Scale ) ; } break ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getFnAttributes ( ) . hasOptimizeForSizeAttr ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || N -> getOpcode ( ) == X86ISD :: TC_RETURN ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>


<s> virtual const TargetRegisterClass * getRepRegClassFor ( MVT VT ) const { if ( VT == MVT :: Untyped ) return Subtarget -> hasDSP ( ) ? & Mips :: ACC64DSPRegClass : & Mips :: ACC64RegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> bool PPCFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> void SparcELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


The darwin64 ABI calls for us to recurse down through structs , looking for elements passed in registers . Unfortunately , we have to track int register count here also because of misalignments in powerpc alignment mode .


<s> HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function ) { HOST_WIDE_INT frame_size , apparent_frame_size ; int args_size , n_global_fp_regs = 0 ; bool save_local_in_regs_p = false ; unsigned int i ; if ( leaf_function && ! cfun -> calls_alloca ) args_size = 0 ; else args_size = crtl -> outgoing_args_size + REG_PARM_STACK_SPACE ( cfun -> decl ) ; if ( TARGET_ARCH64 ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_global_or_fp_reg_p ( i , 0 ) ) n_global_fp_regs += 2 ; } else { for ( i = 0 ; i < 8 ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; } if ( TARGET_FLAT ) for ( i = 16 ; i < 32 ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( size == 0 && n_global_fp_regs == 0 && args_size == 0 && ! save_local_in_regs_p ) frame_size = apparent_frame_size = 0 ; else { apparent_frame_size = ROUND_UP ( size - STARTING_FRAME_OFFSET , 8 ) ; apparent_frame_size += n_global_fp_regs * 4 ; frame_size = apparent_frame_size + ROUND_UP ( args_size , 8 ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size ; sparc_apparent_frame_size = apparent_frame_size ; sparc_n_global_fp_regs = n_global_fp_regs ; sparc_save_local_in_regs_p = save_local_in_regs_p ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
->
isDarwin
(
)
)
RegName
=
PPCRegisterInfo
::
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_K6 : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_PENTIUM4 : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_NOCONA : return 3 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Optimize Call Frame"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> EVT AArch64TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool LC3bAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { LC3bFI = MF . getInfo < LC3bFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( EH_SJLJ_LONGJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETUP_DISPATCH ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( TS1AM ) TARGET_NODE_CASE ( VEC_BROADCAST ) TARGET_NODE_CASE ( REPL_I32 ) TARGET_NODE_CASE ( REPL_F32 ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER VE


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . optForSize ( ) ; MinimizeSize = MF . getFunction ( ) . optForMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>