<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
bool
X86InstrInfo
::
classifyLEAReg
(
MachineInstr
&
MI
,
const
MachineOperand
&
Src
,
unsigned
Opc
,
bool
AllowSP
,
Register
&
NewSrc
,
bool
&
isKill
,
MachineOperand
&
ImplicitOp
,
LiveVariables
*
LV
)
const
{
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
TargetRegisterClass
*
RC
;
if
(
AllowSP
)
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64RegClass
:
&
X86
::
GR32RegClass
;
}
else
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64_NOSPRegClass
:
&
X86
::
GR32_NOSPRegClass
;
}
Register
SrcReg
=
Src
.
getReg
(
)
;
isKill
=
MI
.
killsRegister
(
SrcReg
)
;
if
(
Opc
!=
X86
::
LEA64_32r
)
{
NewSrc
=
SrcReg
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
if
(
NewSrc
.
isVirtual
(
)
&&
!
MF
.
getRegInfo
(
)
.
constrainRegClass
(
NewSrc
,
RC
)
)
return
false
;
return
true
;
}
if
(
SrcReg
.
isPhysical
(
)
)
{
ImplicitOp
=
Src
;
ImplicitOp
.
setImplicit
(
)
;
NewSrc
=
getX86SubSuperRegister
(
SrcReg
,
64
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
}
else
{
NewSrc
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MachineInstr
*
Copy
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
TargetOpcode
::
COPY
)
)
.
addReg
(
NewSrc
,
RegState
::
Define
|
RegState
::
Undef
,
X86
::
sub_32bit
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
isKill
=
true
;
if
(
LV
)
LV
->
replaceKillInstruction
(
SrcReg
,
MI
,
*
Copy
)
;
}
return
true
;
}
</s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> size_t THMToTHMStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> static bool dep_between_memop_and_curr ( rtx memop ) { rtx load_reg ; int opno ; gcc_assert ( GET_CODE ( memop ) == SET ) ; if ( ! REG_P ( SET_DEST ( memop ) ) ) return false ; load_reg = SET_DEST ( memop ) ; for ( opno = 1 ; opno < recog_data . n_operands ; opno ++ ) { rtx operand = recog_data . operand [ opno ] ; if ( REG_P ( operand ) && reg_overlap_mentioned_p ( load_reg , operand ) ) return true ; } return false ; } </s>

Check if there is a register dependency between a load and the insn for which we hold recog_data .


<s> static hashval_t hash ( const char * s ) { return htab_hash_string ( s ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> static bool mips_got_symbol_type_p ( enum mips_symbol_type type ) { switch ( type ) { case SYMBOL_GOT_PAGE_OFST : case SYMBOL_GOT_DISP : return true ; default : return false ; } } </s>

Return true if symbols of type TYPE require a GOT access .


<s> const X86InstrInfo * getInstrInfo ( ) const { return Subtarget -> getInstrInfo ( ) ; } </s>


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ 5 ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ 6 ] ) ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_RELEASE ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_ACQUIRE ) ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ; cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; } if ( mod_f != MEMMODEL_RELAXED ) emit_label ( label2 ) ; if ( ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( mod_f == MEMMODEL_RELAXED ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool AArch64TargetLowering :: isLegalAddImmediate ( int64_t Immed ) const { if ( ( Immed >> 12 ) == 0 || ( ( Immed & 0xfff ) == 0 && Immed >> 24 == 0 ) ) return true ; return false ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s>
unsigned
getReg
(
)
const
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
return
Base
.
Reg
;
}
</s>

Returns the register associated with this edge .


<s> bool AArch64AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0xd503201f , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void X86PassConfig :: addPreEmitPass ( ) { addPass ( createCookieSetterPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } addPass ( createX86FixupVCalls ( ) ) ; addPass ( createMOVToLEAPass ( ) ) ; addPass ( createEquivSubstPass ( ) ) ; if ( TM -> Options . NOPInsertion ) { addPass ( createNOPInsertionPass ( Is64Bit ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> int includes_rldicr_lshift_p ( rtx shiftop , rtx andop ) { if ( GET_CODE ( andop ) == CONST_INT ) { HOST_WIDE_INT c , lsb , shift_mask ; shift_mask = ~ 0 ; shift_mask <<= INTVAL ( shiftop ) ; c = INTVAL ( andop ) ; lsb = c & - c ; if ( ( lsb & shift_mask ) == 0 ) return 0 ; return c == - lsb && lsb != 1 ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , lsb , shift_mask_low ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < 64 ) { HOST_WIDE_INT high , shift_mask_high ; high = CONST_DOUBLE_HIGH ( andop ) ; if ( low == 0 ) { shift_mask_high = ~ 0 ; if ( INTVAL ( shiftop ) > 32 ) shift_mask_high <<= INTVAL ( shiftop ) - 32 ; lsb = high & - high ; if ( ( lsb & shift_mask_high ) == 0 ) return 0 ; return high == - lsb ; } if ( high != ~ 0 ) return 0 ; } shift_mask_low = ~ 0 ; shift_mask_low <<= INTVAL ( shiftop ) ; lsb = low & - low ; if ( ( lsb & shift_mask_low ) == 0 ) return 0 ; return low == - lsb && lsb != 1 ; } else return 0 ; } </s>

Return 1 if ANDOP is a mask suitable for use with an rldicr insn to perform a left shift . It must have SHIFTOP or more least significant 0 's , with the remainder of the word 1 's .


<s> int pa_attr_length_indirect_call ( rtx_insn * insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) return 12 ; if ( TARGET_FAST_INDIRECT_CALLS ) return 8 ; if ( TARGET_PORTABLE_RUNTIME ) return 16 ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) return 8 ; if ( ! flag_pic ) return 12 ; if ( ! optimize_size ) { if ( TARGET_NO_SPACE_REGS ) return 28 ; if ( TARGET_PA_20 ) return 32 ; } return 20 ; } </s>

Return the attribute length of the indirect call instruction INSN . The length must match the code generated by output_indirect call . The returned length includes the delay slot . Currently , the delay slot of an indirect call sequence is not exposed and it is used by the sequence itself .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SSE execution domain fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int ix86_comp_type_attributes ( tree type1 , tree type2 ) { const char * const rtdstr = TARGET_RTD ? "cdecl" : "stdcall" ; if ( TREE_CODE ( type1 ) != FUNCTION_TYPE ) return 1 ; if ( ( ! lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( type2 ) ) ) || ( ix86_function_regparm ( type1 , NULL ) != ix86_function_regparm ( type2 , NULL ) ) ) return 0 ; if ( ! lookup_attribute ( "sseregparm" , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( "sseregparm" , TYPE_ATTRIBUTES ( type2 ) ) ) return 0 ; if ( ! lookup_attribute ( rtdstr , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( rtdstr , TYPE_ATTRIBUTES ( type2 ) ) ) return 0 ; return 1 ; } </s>

Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s> static int function_arg_slotno ( const struct sparc_args * cum , machine_mode mode , const_tree type , bool named , bool incoming , int * pregno , int * ppadding ) { const int regbase = incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ; int slotno = cum -> words , regno ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; * pregno = - 1 ; * ppadding = - 1 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) { slotno ++ ; * ppadding = 1 ; } else * ppadding = 0 ; if ( type && VECTOR_TYPE_P ( type ) ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; if ( TARGET_64BIT && TARGET_FPU && named && type && ( TREE_CODE ( type ) == RECORD_TYPE || VECTOR_TYPE_P ( type ) ) ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { classify_data_t data = { false , false } ; traverse_record_type < classify_data_t , classify_registers > ( type , named , & data ) ; if ( data . fp_regs ) { if ( slotno >= SPARC_FP_ARG_MAX - 1 && ! data . fp_regs_in_first_word ) return - 1 ; } else { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; } return slotno ; } regno = SPARC_FP_ARG_FIRST + slotno * 2 ; } else { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; } </s>


"Only DWARF debug format is supported for interrupt "

Set the func_type field from the function FNDECL .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static reg_class_t ix86_preferred_output_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; mode = GET_MODE ( x ) ; if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) return MAYBE_SSE_CLASS_P ( regclass ) ? ALL_SSE_REGS : NO_REGS ; if ( IS_STACK_MODE ( mode ) ) return FLOAT_CLASS_P ( regclass ) ? regclass : NO_REGS ; return regclass ; } </s>

Discourage putting floating-point values in SSE registers unless SSE math is being used , and likewise for the 387 registers .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> void mips_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , mips_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s>
bool
ARMBaseInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
instr_iterator
I
=
MBB
.
instr_end
(
)
;
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugInstr
(
)
||
!
I
->
isTerminator
(
)
)
{
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
}
if
(
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
true
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
instr_end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
{
if
(
AllowModify
&&
!
isPredicated
(
MBB
.
back
(
)
)
&&
isUncondBranchOpcode
(
MBB
.
back
(
)
.
getOpcode
(
)
)
&&
TBB
&&
MBB
.
isLayoutSuccessor
(
TBB
)
)
removeBranch
(
MBB
)
;
return
true
;
}
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= expandMBB ( MBB ) ; if ( Modified ) MF . RenumberBlocks ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool supportsEfficientVectorElementLoadStore ( ) { return ST -> getProcFamily ( ) == AArch64Subtarget :: ThunderX2T99 ; } </s>

If target has efficient vector element load/store instructions , it can return true here so that insertion/extraction costs are not added to the scalarization cost of a load/store .


<s> bool AArch64TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( VT1 . isVector ( ) || VT2 . isVector ( ) || ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; uint64_t NumBits1 = VT1 . getFixedSizeInBits ( ) ; uint64_t NumBits2 = VT2 . getFixedSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
static
int
getMemScale
(
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> bool X86AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( ".code" ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void expand_small_movmem_or_setmem ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int size , rtx done_label , bool issetmem ) { rtx_code_label * label = ix86_expand_aligntest ( count , size , false ) ; machine_mode mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 1 ) ; rtx modesize ; int n ; if ( issetmem ) { if ( ! vec_value ) { if ( GET_MODE ( value ) == VOIDmode && size > 8 ) mode = Pmode ; else if ( GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( GET_MODE ( value ) ) ) mode = GET_MODE ( value ) ; } else mode = GET_MODE ( vec_value ) , value = vec_value ; } else { if ( size >= 32 ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= 16 ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , count , 1 ) ; destmem = offset_address ( destmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; if ( ! issetmem ) { srcmem = offset_address ( srcmem , count , 1 ) ; srcmem = offset_address ( srcmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; } for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; } </s>

Test if COUNT & SIZE is nonzero and if so , expand movme or setmem sequence that is valid for SIZE .. 2 * SIZE-1 bytes and jump to DONE_LABEL .


<s> bool FixAllFDIVSQRT :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < SparcSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = DebugLoc ( ) ; bool Modified = false ; for ( auto MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( MI . isInlineAsm ( ) ) { std :: string AsmString ( MI . getOperand ( InlineAsm :: MIOp_AsmString ) . getSymbolName ( ) ) ; std :: string FSQRTDOpCode ( "fsqrtd" ) ; std :: string FDIVDOpCode ( "fdivd" ) ; std :: transform ( AsmString . begin ( ) , AsmString . end ( ) , AsmString . begin ( ) , :: tolower ) ; if ( AsmString . find ( FSQRTDOpCode ) == 0 ) { Opcode = SP :: FSQRTD ; } else if ( AsmString . find ( FDIVDOpCode ) == 0 ) { Opcode = SP :: FDIVD ; } } if ( Opcode == SP :: FSQRTD || Opcode == SP :: FDIVD ) { for ( int InsertedCount = 0 ; InsertedCount < 5 ; InsertedCount ++ ) BuildMI ( MBB , MBBI , DL , TII . get ( SP :: NOP ) ) ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; for ( int InsertedCount = 0 ; InsertedCount < 28 ; InsertedCount ++ ) BuildMI ( MBB , NMBBI , DL , TII . get ( SP :: NOP ) ) ; Modified = true ; } } } return Modified ; } </s>


<s>
static
void
copy_fp_args
(
rtx_insn
*
insn
)
{
rtx
link
;
rtx
xoperands
[
2
]
;
for
(
link
=
CALL_INSN_FUNCTION_USAGE
(
insn
)
;
link
;
link
=
XEXP
(
link
,
1
)
)
{
int
arg_mode
,
regno
;
rtx
use
=
XEXP
(
link
,
0
)
;
if
(
!
(
GET_CODE
(
use
)
==
USE
&&
GET_CODE
(
XEXP
(
use
,
0
)
)
==
REG
&&
FUNCTION_ARG_REGNO_P
(
REGNO
(
XEXP
(
use
,
0
)
)
)
)
)
continue
;
arg_mode
=
GET_MODE
(
XEXP
(
use
,
0
)
)
;
regno
=
REGNO
(
XEXP
(
use
,
0
)
)
;
if
(
regno
>=
32
&&
regno
<=
39
)
{
if
(
arg_mode
==
SFmode
)
{
xoperands
[
0
]
=
XEXP
(
use
,
0
)
;
xoperands
[
1
]
=
gen_rtx_REG
(
SImode
,
26
(
regno
32
)
/
2
)
;
output_asm_insn
(
"{fstws|fstw} %0,-16(%%sr0,%%r30)"
,
xoperands
)
;
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
)
;
}
else
{
xoperands
[
0
]
=
XEXP
(
use
,
0
)
;
xoperands
[
1
]
=
gen_rtx_REG
(
DImode
,
25
(
regno
34
)
/
2
)
;
output_asm_insn
(
"{fstds|fstd} %0,-16(%%sr0,%%r30)"
,
xoperands
)
;
output_asm_insn
(
"ldw -12(%%sr0,%%r30),%R1"
,
xoperands
)
;
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
)
;
}
}
}
}
</s>

Copy any FP arguments in INSN into integer registers .


<s> bool ARMTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForNode ( CallConv , true , isVarArg ) ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static bool ix86_unordered_fp_compare ( enum rtx_code code ) { if ( ! TARGET_IEEE_FP ) return false ; switch ( code ) { case GT : case GE : case LT : case LE : return false ; case EQ : case NE : case LTGT : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return true ; default : gcc_unreachable ( ) ; } } </s>

Figure out whether to use unordered fp comparisons .


<s> bool ARMConstantPoolSymbol :: hasSameValue ( ARMConstantPoolValue * ACPV ) { const ARMConstantPoolSymbol * ACPS = dyn_cast < ARMConstantPoolSymbol > ( ACPV ) ; return ACPS && CPV_streq ( ACPS -> S , S ) && ARMConstantPoolValue :: hasSameValue ( ACPV ) ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( Kind == 1 ) { if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RC_NOX0RegClass ; return & PPC :: GPRC_NOR0RegClass ; } if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> bool X86InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / 8 > 64 ) return false ; unsigned Opc1 = Load1 -> getMachineOpcode ( ) ; unsigned Opc2 = Load2 -> getMachineOpcode ( ) ; if ( Opc1 != Opc2 ) return false ; switch ( Opc1 ) { default : break ; case X86 :: LD_Fp32m : case X86 :: LD_Fp64m : case X86 :: LD_Fp80m : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : return false ; } EVT VT = Load1 -> getValueType ( 0 ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : if ( Subtarget . is64Bit ( ) ) { if ( NumLoads >= 3 ) return false ; } else if ( NumLoads ) { return false ; } break ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : case MVT :: f32 : case MVT :: f64 : if ( NumLoads ) return false ; break ; } return true ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> static int mt_add_branches ( rtx * x , void * insn ) { if ( GET_CODE ( * x ) == LABEL_REF ) { branch_info * branch = xmalloc ( sizeof ( * branch ) ) ; rtx label = XEXP ( * x , 0 ) ; label_info * info ; for ( info = mt_labels ; info ; info = info -> next ) if ( info -> label == label ) break ; if ( ! info ) { info = xmalloc ( sizeof ( * info ) ) ; info -> next = mt_labels ; mt_labels = info ; info -> label = label ; info -> branches = NULL ; } branch -> next = info -> branches ; info -> branches = branch ; branch -> insn = insn ; } return 0 ; } </s>

If * X is a label , add INSN to the list of branches for that label .


<s>
MachineBasicBlock
*
SHUXITargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
assert
(
Opc
==
SHUXI
::
Select
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SHUXI
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SHUXI
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
.
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
ResValue
=
Outs
[
i
]
.
Val
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
AExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
ResValue
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void altivec_expand_vec_perm_le ( rtx operands [ 4 ] ) { rtx notx , iorx , unspec ; rtx target = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx sel = operands [ 3 ] ; rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; } if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target , unspec ) ; } </s>

Similarly to altivec_expand_vec_perm_const_le , we must adjust the permute control vector . But here it 's not a constant , so we must generate a vector NAND or NOR to do the adjustment .


<s> static enum aarch64_parse_opt_result aarch64_parse_tune ( const char * to_parse , const struct processor * * res ) { const struct processor * cpu ; char * str = ( char * ) alloca ( strlen ( to_parse ) + 1 ) ; strcpy ( str , to_parse ) ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strcmp ( cpu -> name , str ) == 0 ) { * res = cpu ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool nds32_n9_last_load_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; if ( nds32_register_ports_config == REG_PORT_2R1W ) { if ( post_update_insn_p ( producer ) ) return false ; size_t i ; size_t n_elems = parallel_elements ( producer ) ; rtx base_reg = extract_base_reg ( producer ) ; for ( i = 0 ; i < n_elems ; ++ i ) { rtx load_rtx = extract_nth_access_rtx ( producer , i ) ; rtx list_element = SET_DEST ( load_rtx ) ; if ( rtx_equal_p ( base_reg , list_element ) && i != n_elems - 1 ) { last_def_reg = base_reg ; break ; } } return n9_2r1w_consumed_by_ex_dep_p ( consumer , last_def_reg ) ; } else return n9_3r2w_consumed_by_ex_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to EX .


<s>
static
void
mips_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
const
char
*
fnname
;
if
(
TARGET_MIPS16
&&
TARGET_HARD_FLOAT_ABI
&&
crtl
->
args
.
info
.
fp_code
!=
0
)
mips16_build_function_stub
(
)
;
fnname
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
mips_start_function_definition
(
fnname
,
TARGET_MIPS16
)
;
if
(
!
flag_inhibit_size_directive
)
{
const
struct
mips_frame_info
*
frame
;
frame
=
&
cfun
->
machine
->
frame
;
fprintf
(
file
,
"\t.frame\t%s,"
HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
"# vars= "
HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
", args= "
HOST_WIDE_INT_PRINT_DEC
", gp= "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
reg_names
[
frame_pointer_needed
HARD_FRAME_POINTER_REGNUM
:
STACK_POINTER_REGNUM
]
,
(
frame_pointer_needed
frame
->
total_size
frame
->
hard_frame_pointer_offset
:
frame
->
total_size
)
,
reg_names
[
RETURN_ADDR_REGNUM
]
,
frame
->
var_size
,
frame
->
num_gp
,
frame
->
num_fp
,
frame
->
args_size
,
frame
->
cprestore_size
)
;
fprintf
(
file
,
"\t.mask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
frame
->
mask
,
frame
->
gp_save_offset
)
;
fprintf
(
file
,
"\t.fmask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
frame
->
fmask
,
frame
->
fp_save_offset
)
;
}
if
(
mips_must_initialize_gp_p
(
)
&&
mips_current_loadgp_style
(
)
==
LOADGP_OLDABI
)
{
if
(
TARGET_MIPS16
)
{
output_asm_insn
(
"li\t$2,%%hi(_gp_disp)"
,
0
)
;
output_asm_insn
(
"addiu\t$3,$pc,%%lo(_gp_disp)"
,
0
)
;
output_asm_insn
(
"sll\t$2,16"
,
0
)
;
output_asm_insn
(
"addu\t$2,$3"
,
0
)
;
}
else
{
mips_push_asm_switch
(
&
mips_noreorder
)
;
output_asm_insn
(
".cpload\t%^"
,
0
)
;
if
(
!
cfun
->
machine
->
all_noreorder_p
)
mips_pop_asm_switch
(
&
mips_noreorder
)
;
else
mips_push_asm_switch
(
&
mips_nomacro
)
;
}
}
else
if
(
cfun
->
machine
->
all_noreorder_p
)
{
mips_push_asm_switch
(
&
mips_noreorder
)
;
mips_push_asm_switch
(
&
mips_nomacro
)
;
}
mips_output_cplocal
(
)
;
}
</s>

Set up the stack and frame ( if desired ) for the function .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return MVT :: v2i64 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return MVT :: f128 ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return MVT :: i64 ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static bool mips16_unextended_reference_p ( machine_mode mode , rtx base , unsigned HOST_WIDE_INT offset ) { if ( mode != BLKmode && offset % GET_MODE_SIZE ( mode ) == 0 ) { if ( GET_MODE_SIZE ( mode ) == 4 && base == stack_pointer_rtx ) return offset < 256U * GET_MODE_SIZE ( mode ) ; return offset < 32U * GET_MODE_SIZE ( mode ) ; } return false ; } </s>

Return true if a value at OFFSET bytes from BASE can be accessed using an unextended mips16 instruction . MODE is the mode of the value . Usually the offset in an unextended instruction is a 5-bit field . The offset is unsigned and shifted left once for HIs , twice for SIs , and so on . An exception is SImode accesses off the stack pointer , which have an 8-bit immediate field .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; unsigned opcode = MI . getOpcode ( ) ; uint16_t validDomains = 0 ; if ( domain ) { if ( lookup ( MI . getOpcode ( ) , domain , ReplaceableInstrs ) ) { validDomains = 0xe ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2InsertExtract ) ) { if ( ! Subtarget . hasAVX2 ( ) ) return std :: make_pair ( 0 , 0 ) ; validDomains = 0xe ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) && lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) ) { if ( const uint16_t * table = lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQMasked ) ) { if ( domain == 1 || ( domain == 3 && table [ 3 ] == opcode ) ) validDomains = 0xa ; else validDomains = 0xc ; } } } return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> static rtx_insn * rs6000_emit_allocate_stack_1 ( HOST_WIDE_INT size_int , rtx orig_sp ) { rtx_insn * insn ; rtx size_rtx = GEN_INT ( - size_int ) ; if ( size_int > 32767 ) { rtx tmp_reg = gen_rtx_REG ( Pmode , 0 ) ; if ( get_last_insn ( ) == NULL_RTX ) emit_note ( NOTE_INSN_DELETED ) ; insn = emit_move_insn ( tmp_reg , size_rtx ) ; try_split ( PATTERN ( insn ) , insn , 0 ) ; size_rtx = tmp_reg ; } if ( Pmode == SImode ) insn = emit_insn ( gen_movsi_update_stack ( stack_pointer_rtx , stack_pointer_rtx , size_rtx , orig_sp ) ) ; else insn = emit_insn ( gen_movdi_di_update_stack ( stack_pointer_rtx , stack_pointer_rtx , size_rtx , orig_sp ) ) ; rtx par = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( par ) == PARALLEL ) ; rtx set = XVECEXP ( par , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; rtx mem = SET_DEST ( set ) ; gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } return insn ; } </s>

Allocate SIZE_INT bytes on the stack using a store with update style insn and set the appropriate attributes for the generated insn . Return the first insn which adjusts the stack pointer or the last insn before the stack adjustment loop . SIZE_INT is used to create the CFI note for the allocation . SIZE_RTX is an rtx containing the size of the adjustment . Note that since stacks grow to lower addresses its runtime value is -SIZE_INT . ORIG_SP contains the backchain value that must be stored at * sp .


<s>
SDValue
SystemZTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

SystemZ
SystemZ
ISD::BR_CC
ISD::SELECT_CC
ISD::GlobalAddress
ISD::JumpTable
ISD::ConstantPool
"Should not custom lower this!"


Define the ` __builtin_va_list ' type for the ABI .


<s> bool AArch64TargetLowering :: shouldNormalizeToSelectSequence ( LLVMContext & , EVT ) const { return false ; } </s>

Returns true if we should normalize select ( N0 & N1 , X , Y ) = > select ( N0 , select ( N1 , X , Y ) , Y ) and select ( N0|N1 , X , Y ) = > select ( N0 , select ( N1 , X , Y , Y ) ) if it is likely that it saves us from materializing N0 and N1 in an integer register .


<s>
std
::
string
str
(
)
const
{
std
::
string
S
;
raw_string_ostream
OS
(
S
)
;
OS
<<
"{"
;
StartInst
->
print
(
OS
,
,
true
)
;
OS
<<
" -> "
;
LastInst
->
print
(
OS
,
,
true
)
;
if
(
KillInst
)
{
OS
<<
" (kill @ "
;
KillInst
->
print
(
OS
,
,
true
)
;
OS
<<
")"
;
}
OS
<<
"}"
;
return
OS
.
str
(
)
;
}
</s>

Return the twine contents as a std : :string .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> bool isImm ( ) const { return Kind == Immediate ; } </s>


<s> void EmitInstruction ( uint32_t Val , raw_ostream & OS ) const { for ( unsigned i = 0 ; i != 4 ; ++ i ) { EmitByte ( Val & 0xff , OS ) ; Val >>= 8 ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void sparc_emit_fixunsdi ( rtx * operands , machine_mode mode ) { rtx i0 , i1 , f0 , in , out , limit ; out = operands [ 0 ] ; in = force_reg ( mode , operands [ 1 ] ) ; rtx_code_label * neglab = gen_label_rtx ( ) ; rtx_code_label * donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( "9223372036854775808.0" , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , in ) ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f0 , gen_rtx_MINUS ( mode , in , limit ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , i0 , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , f0 ) ) ) ) ; emit_insn ( gen_movdi ( i1 , const1_rtx ) ) ; emit_insn ( gen_ashldi3 ( i1 , i1 , GEN_INT ( 63 ) ) ) ; emit_insn ( gen_xordi3 ( out , i0 , i1 ) ) ; emit_label ( donelab ) ; } </s>

Generate an FP to unsigned DImode conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> static void remove_non_convertible_regs ( bitmap candidates ) { if ( TARGET_64BIT ) timode_remove_non_convertible_regs ( candidates ) ; else dimode_remove_non_convertible_regs ( candidates ) ; } </s>

For a given bitmap of insn UIDs scans all instruction and remove insn from CANDIDATES in case it has both convertible and not convertible definitions . All insns in a bitmap are conversion candidates according to scalar_to_vector_candidate_p . Currently it implies all insns are single_set .


<s> static const char * svprfop_token ( enum aarch64_svprfop prfop ) { switch ( prfop ) { AARCH64_FOR_SVPRFOP ( CASE ) case AARCH64_NUM_SVPRFOPS : break ; } gcc_unreachable ( ) ; } </s>

Return the assembly token for svprfop value PRFOP .


<s> static bool mips_save_reg_p ( unsigned int regno ) { if ( regno == GLOBAL_POINTER_REGNUM ) return ( TARGET_ABICALLS && TARGET_NEWABI && cfun -> machine -> global_pointer == regno ) ; if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == GP_REG_FIRST + 31 && regs_ever_live [ regno ] ) return true ; if ( TARGET_MIPS16 ) { tree return_type ; return_type = DECL_RESULT ( current_function_decl ) ; if ( regno == GP_REG_FIRST + 18 && regs_ever_live [ regno ] ) return true ; if ( regno == GP_REG_FIRST + 31 && mips16_hard_float && ! aggregate_value_p ( return_type , current_function_decl ) && GET_MODE_CLASS ( DECL_MODE ( return_type ) ) == MODE_FLOAT && GET_MODE_SIZE ( DECL_MODE ( return_type ) ) <= UNITS_PER_FPVALUE ) return true ; } return false ; } </s>

Return true if the current function must save REGNO .


<s>
Register
MipsOutgoingValueHandler
::
extendRegister
(
Register
ValReg
,
const
CCValAssign
&
VA
)
{
LLT
LocTy
{
VA
.
getLocVT
(
)
}
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
SExt
:
{
return
MIRBuilder
.
buildSExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
ZExt
:
{
return
MIRBuilder
.
buildZExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
AExt
:
{
return
MIRBuilder
.
buildAnyExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
Full
:
return
ValReg
;
default
:
break
;
}
llvm_unreachable
(
"unable to extend register"
)
;
}
</s>

Extend a register to the location type given in VA , capped at extending to at most MaxSize bits .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> bool X86TTIImpl :: enableInterleavedAccessVectorization ( ) { return ! ( ST -> isAtom ( ) ) ; } </s>

Enable matching of interleaved access groups .


<s> Register SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ; } </s>


<s> Optional < Value * > X86TTIImpl :: simplifyDemandedUseBitsIntrinsic ( InstCombiner & IC , IntrinsicInst & II , APInt DemandedMask , KnownBits & Known , bool & KnownBitsComputed ) const { switch ( II . getIntrinsicID ( ) ) { default : break ; case Intrinsic :: x86_mmx_pmovmskb : case Intrinsic :: x86_sse_movmsk_ps : case Intrinsic :: x86_sse2_movmsk_pd : case Intrinsic :: x86_sse2_pmovmskb_128 : case Intrinsic :: x86_avx_movmsk_ps_256 : case Intrinsic :: x86_avx_movmsk_pd_256 : case Intrinsic :: x86_avx2_pmovmskb : { unsigned ArgWidth ; if ( II . getIntrinsicID ( ) == Intrinsic :: x86_mmx_pmovmskb ) { ArgWidth = 8 ; } else { auto * ArgType = cast < FixedVectorType > ( II . getArgOperand ( 0 ) -> getType ( ) ) ; ArgWidth = ArgType -> getNumElements ( ) ; } APInt DemandedElts = DemandedMask . zextOrTrunc ( ArgWidth ) ; Type * VTy = II . getType ( ) ; if ( DemandedElts . isZero ( ) ) { return ConstantInt :: getNullValue ( VTy ) ; } Known . Zero . setBitsFrom ( ArgWidth ) ; KnownBitsComputed = true ; break ; } } return None ; } </s>

Can be used to implement target-specific instruction combining .


<s> static inline unsigned long ia64_rse_is_rnat_slot ( unsigned long * addr ) { return ia64_rse_slot_num ( addr ) == 0x3f ; } </s>

Return TRUE if ADDR is the address of an RNAT slot .


<s> void rs6000_emit_cbranch ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx = rs6000_generate_compare ( operands [ 0 ] , mode ) ; rtx loc_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; rtx ite = gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , ite ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( scalar_int_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) + 1 ) >= 0 && ( INTVAL ( mask ) & ( ( HOST_WIDE_INT_1U << INTVAL ( shft_amnt ) ) - 1 ) ) == 0 ; } </s>

Return true if the mask and a shift amount from an RTX of the form ( x < < SHFT_AMNT ) & MASK are valid to combine into a UBFIZ instruction of mode MODE . See the * andim_ashift < mode > _bfiz pattern .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
const
X86TargetMachine
*
TM
=
static_cast
<
const
X86TargetMachine
*
>
(
&
MF
.
getTarget
(
)
)
;
const
X86Subtarget
&
STI
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
STI
.
is64Bit
(
)
&&
(
TM
->
getCodeModel
(
)
==
CodeModel
::
Small
||
TM
->
getCodeModel
(
)
==
CodeModel
::
Kernel
)
)
return
false
;
if
(
!
TM
->
isPositionIndependent
(
)
)
return
false
;
X86MachineFunctionInfo
*
X86FI
=
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
unsigned
GlobalBaseReg
=
X86FI
->
getGlobalBaseReg
(
)
;
if
(
GlobalBaseReg
==
0
)
return
false
;
MachineBasicBlock
&
FirstMBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
FirstMBB
.
begin
(
)
;
DebugLoc
DL
=
FirstMBB
.
findDebugLoc
(
MBBI
)
;
MachineRegisterInfo
&
RegInfo
=
MF
.
getRegInfo
(
)
;
const
X86InstrInfo
*
TII
=
STI
.
getInstrInfo
(
)
;
unsigned
PC
;
if
(
STI
.
isPICStyleGOT
(
)
)
PC
=
RegInfo
.
createVirtualRegister
(
&
X86
::
GR32RegClass
)
;
else
PC
=
GlobalBaseReg
;
if
(
STI
.
is64Bit
(
)
)
{
if
(
TM
->
getCodeModel
(
)
==
CodeModel
::
Medium
)
{
BuildMI
(
FirstMBB
,
MBBI
,
DL
,
TII
->
get
(
X86
::
LEA64r
)
,
PC
)
.
addReg
(
X86
::
RIP
)
.
addImm
(
0
)
.
addReg
(
0
)
.
addExternalSymbol
(
"_GLOBAL_OFFSET_TABLE_"
)
.
addReg
(
0
)
;
}
else
if
(
TM
->
getCodeModel
(
)
==
CodeModel
::
Large
)
{
unsigned
Scratch
=
RegInfo
.
createVirtualRegister
(
&
X86
::
GR64RegClass
)
;
BuildMI
(
FirstMBB
,
MBBI
,
DL
,
TII
->
get
(
X86
::
MOVGOT64r
)
,
PC
)
.
addReg
(
Scratch
,
RegState
::
Undef
|
RegState
::
Define
)
.
addExternalSymbol
(
"_GLOBAL_OFFSET_TABLE_"
)
;
}
else
{
llvm_unreachable
(
"unexpected code model"
)
;
}
}
else
{
BuildMI
(
FirstMBB
,
MBBI
,
DL
,
TII
->
get
(
X86
::
MOVPC32r
)
,
PC
)
.
addImm
(
0
)
;
if
(
STI
.
isPICStyleGOT
(
)
)
{
BuildMI
(
FirstMBB
,
MBBI
,
DL
,
TII
->
get
(
X86
::
ADD32ri
)
,
GlobalBaseReg
)
.
addReg
(
PC
)
.
addExternalSymbol
(
"_GLOBAL_OFFSET_TABLE_"
,
X86II
::
MO_GOT_ABSOLUTE_ADDRESS
)
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void ix86_function_specific_restore ( struct gcc_options * opts , struct gcc_options * , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned HOST_WIDE_INT ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; ix86_prefetch_sse = ptr -> prefetch_sse ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; ix86_tune_cost = processor_cost_table [ ix86_tune ] ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = HOST_WIDE_INT_1U << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( opts , ix86_tune , false ) ; } </s>


<s> static void ix86_output_indirect_branch_via_reg ( rtx call_op , bool sibcall_p ) { char thunk_name_buf [ 32 ] ; char * thunk_name ; enum indirect_thunk_prefix need_prefix = indirect_thunk_need_prefix ( current_output_insn ) ; int regno = REGNO ( call_op ) ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_inline ) { if ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) { int i = regno ; if ( i >= FIRST_REX_INT_REG ) i -= ( FIRST_REX_INT_REG - LAST_INT_REG - 1 ) ; indirect_thunks_used |= 1 << i ; } indirect_thunk_name ( thunk_name_buf , regno , need_prefix , false ) ; thunk_name = thunk_name_buf ; } else thunk_name = NULL ; if ( sibcall_p ) { if ( thunk_name != NULL ) fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; else output_indirect_thunk ( regno ) ; } else { if ( thunk_name != NULL ) { fprintf ( asm_out_file , "\tcall\t%s\n" , thunk_name ) ; return ; } char indirectlabel1 [ 32 ] ; char indirectlabel2 [ 32 ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; fputs ( "\tjmp\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; else output_indirect_thunk ( regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; fputs ( "\tcall\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel1 ) ; fputc ( '\n' , asm_out_file ) ; } } </s>

Output indirect branch via a call and return thunk . CALL_OP is a register which contains the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : call __x86_indirect_thunk_reg and a tail call is converted to : jmp __x86_indirect_thunk_reg


<s> static inline unsigned int rx_round_up ( unsigned int value , unsigned int alignment ) { alignment -= 1 ; return ( value + alignment ) & ( ~ alignment ) ; } </s>

Return VALUE rounded up to the next ALIGNMENT boundary .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static rtx aarch64_gen_loadwb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case E_DImode : return gen_loadwb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; case E_DFmode : return gen_loadwb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; case E_TFmode : return gen_loadwb_pairtf_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_VREG ) ) ; default : gcc_unreachable ( ) ; } } </s>

Load the pair of register REG , REG2 of mode MODE from stack location BASE , adjusting it by ADJUSTMENT afterwards .


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen_neon_vzip_internal ( d -> vmode , out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> unsigned X86InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameLoadOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return 1 ; } } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool Dcpu16PassConfig :: addInstSelector ( ) { PM . add ( createDcpu16ISelDag ( getDcpu16TargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> static void rs6000_elf_asm_init_sections ( void ) { toc_section = get_unnamed_section ( 0 , rs6000_elf_output_toc_section_asm_op , NULL ) ; sdata2_section = get_unnamed_section ( SECTION_WRITE , output_section_asm_op , SDATA2_SECTION_ASM_OP ) ; } </s>


<s> static int pa_issue_rate ( ) { switch ( pa_cpu ) { case PROCESSOR_700 : return 1 ; case PROCESSOR_7100 : return 2 ; case PROCESSOR_7100LC : return 2 ; case PROCESSOR_7200 : return 2 ; case PROCESSOR_8000 : return 4 ; default : abort ( ) ; } } </s>

The 700 can only issue a single insn at a time . The 7XXX processors can issue two insns at a time . The 8000 can issue 4 insns at a time .


<s>
unsigned
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
isDarwinABI
=
Subtarget
.
isDarwinABI
(
)
;
if
(
(
isPPC64
&&
VT
!=
MVT
::
i64
&&
VT
!=
MVT
::
i32
)
||
(
!
isPPC64
&&
VT
!=
MVT
::
i32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
MVT
::
i64
;
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
(
isDarwinABI
||
isPPC64
)
0
:
PPC
::
R2
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
isDarwinABI
)
0
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { Register GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool AArch64TargetLowering :: useLoadStackGuardNode ( ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return true ; return TargetLowering :: useLoadStackGuardNode ( ) ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


"  Skipping pass: no machine model present.\n"


<s> static bool high_pressure ( machine_mode mode ) { if ( r0_life_regions >= R0_MAX_LIFE_REGIONS ) return true ; if ( mode == SFmode ) return ( CURR_REGMODE_PRESSURE ( SFmode ) > SFMODE_MAX_WEIGHT ) ; else return ( CURR_REGMODE_PRESSURE ( SImode ) > SIMODE_MAX_WEIGHT ) ; } </s>

Return true if the pressure is high for MODE .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
report_fatal_error
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s> static unsigned rs6000_add_stmt_cost ( class vec_info * vinfo , void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , tree vectype , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost += rs6000_adjust_vect_cost_per_stmt ( kind , stmt_info ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( vinfo , stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; if ( ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec ) || ( where == vect_body && kind == vector_stmt ) ) rs6000_vect_nonmem = true ; } return retval ; } </s>


<s> bool runOnFunction ( Function & F ) override { X86LowerAMXType LAT ( F ) ; bool C = LAT . visit ( ) ; return C ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool FISCPassConfig :: addInstSelector ( ) { addPass ( createFISCISelDag ( getFISCTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>


"TOC pointer used in a function using PC-Relative addressing!"


<s> static void loongarch_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct loongarch_arg_info info ; loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; cum -> num_fprs = info . fpr_offset + info . num_fprs ; cum -> num_gprs = info . gpr_offset + info . num_gprs ; } </s>


<s> TargetPassConfig * ARMBaseTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new ARMPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> unsigned getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins"


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv :: X86_FastCall ) ; SecurityCheckCookie -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool ia64_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == BR_REG ( 0 ) ? crtl -> is_leaf : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> int mips_split_const_insns ( rtx x ) { unsigned int low , high ; low = mips_const_insns ( mips_subword ( x , false ) ) ; high = mips_const_insns ( mips_subword ( x , true ) ) ; gcc_assert ( low > 0 && high > 0 ) ; return low + high ; } </s>

X is a doubleword constant that can be handled by splitting it into two words and loading each word separately . Return the number of instructions required to do this , assuming that BASE_INSN_LENGTH is the length of one instruction .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Um
:
case
InlineAsm
::
Constraint_Un
:
case
InlineAsm
::
Constraint_Uq
:
case
InlineAsm
::
Constraint_Us
:
case
InlineAsm
::
Constraint_Ut
:
case
InlineAsm
::
Constraint_Uv
:
case
InlineAsm
::
Constraint_Uy
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"Unexpected asm memory constraint"


"inserting int3 after trailing call instruction:\n"

"inserting int3 in trailing empty MBB:\n"

runOnMachineFunction - Emit the function body .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned PPCFastISel :: fastEmit_i ( MVT Ty , MVT VT , unsigned Opc , uint64_t Imm ) { if ( Opc != ISD :: Constant ) return 0 ; if ( VT == MVT :: i1 && PPCSubTarget -> useCRBits ( ) ) { unsigned ImmReg = createResultReg ( & PPC :: CRBITRCRegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == 0 ? PPC :: CRUNSET : PPC :: CRSET ) , ImmReg ) ; return ImmReg ; } if ( VT != MVT :: i64 && VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 && VT != MVT :: i1 ) return 0 ; const TargetRegisterClass * RC = ( ( VT == MVT :: i64 ) ? & PPC :: G8RCRegClass : & PPC :: GPRCRegClass ) ; if ( VT == MVT :: i64 ) return PPCMaterialize64BitInt ( Imm , RC ) ; else return PPCMaterialize32BitInt ( Imm , RC ) ; } </s>

This method is called by target-independent code to request that an instruction with the given type , opcode , and immediate operand be emitted .


<s> bool X86FrameLowering :: canUseLEAForSPInEpilogue ( const MachineFunction & MF ) const { return ! MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) || hasFP ( MF ) ; } </s>

Check that LEA can be used on SP in an epilogue sequence for MF .


<s> const char * i386_nlm_strip_name_encoding ( const char * str ) { const char * name = default_strip_name_encoding ( str ) ; if ( * str != '*' && ( * name == '_' || * name == '@' ) ) { const char * p = strchr ( name + 1 , '@' ) ; if ( p ) { ++ name ; if ( ISDIGIT ( p [ 1 ] ) ) name = ggc_alloc_string ( name , p - name ) ; else { gcc_assert ( ISDIGIT ( * name ) ) ; name ++ ; gcc_assert ( name == p ) ; } } } return name ; } </s>

Strip the stdcall/fastcall/regparm pre-/suffix .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? Mips :: FP : Mips :: SP ; } </s>


<s> void X86FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { emitStackProbeInlineStub ( MF , MBB , MBBI , DL , true ) ; } else { emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog ) ; } } </s>


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SPISD :: NodeType ) Opcode ) { case SPISD :: FIRST_NUMBER : break ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; case SPISD :: TAIL_CALL : return "SPISD::TAIL_CALL" ; } return nullptr ; } </s>


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? Subtarget -> getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * static_cast < const AArch64TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , & Args , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ( ! df_regs_ever_live_p ( regno ) || call_used_regs [ regno ] ) && ( ! df_regs_ever_live_p ( regno + 1 ) || call_used_regs [ regno + 1 ] ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < MipsSubtarget > ( ) . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>


<s> static bool pru_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == POINTER_SIZE / BITS_PER_UNIT && aligned_p && text_segment_operand ( x , VOIDmode ) ) { fputs ( "\t.4byte\t%pmem(" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( ")\n" , asm_out_file ) ; return true ; } else if ( size == INIT_ARRAY_ENTRY_BYTES && aligned_p && text_segment_operand ( x , VOIDmode ) ) { fputs ( "\t.2byte\t%pmem(" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( ")\n" , asm_out_file ) ; return true ; } else { return default_assemble_integer ( x , size , aligned_p ) ; } } </s>

Implement ` TARGET_ASM_INTEGER ' . Target hook for assembling integer objects . PRU version needs special handling for references to pmem . Code copied from AVR .


<s> static const char * detect_caches_amd ( unsigned max_ext_level ) { unsigned eax , ebx , ecx , edx ; struct cache_desc level1 , level2 = { 0 , 0 , 0 } ; if ( max_ext_level < 0x80000005 ) return "" ; __cpuid ( 0x80000005 , eax , ebx , ecx , edx ) ; level1 . sizekb = ( ecx >> 24 ) & 0xff ; level1 . assoc = ( ecx >> 16 ) & 0xff ; level1 . line = ecx & 0xff ; if ( max_ext_level >= 0x80000006 ) detect_l2_cache ( & level2 ) ; return describe_cache ( level1 , level2 ) ; } </s>

Returns the description of caches for an AMD processor .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT == MVT :: v2i32 ) return std :: make_pair ( 0U , & SP :: IntPairRegClass ) ; else return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SystemZ Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int X86TTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID IID , Type * RetTy , ArrayRef < Value * > Args , FastMathFlags FMF , unsigned VF ) { return BaseT :: getIntrinsicInstrCost ( IID , RetTy , Args , FMF , VF ) ; } </s>


<s> bool ARMConstantPoolMBB :: hasSameValue ( ARMConstantPoolValue * ACPV ) { const ARMConstantPoolMBB * ACPMBB = dyn_cast < ARMConstantPoolMBB > ( ACPV ) ; return ACPMBB && ACPMBB -> MBB == MBB && ARMConstantPoolValue :: hasSameValue ( ACPV ) ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void neon_split_vcombine ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = HARD_REGNO_NREGS ( src1 , halfmode ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( destlo , operands [ 1 ] ) ; rtx y = gen_rtx_SET ( desthi , operands [ 2 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x , y ) ) ) ; return ; } if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> void OR1KInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s>
MachineInstr
*
LanaiInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
MI
.
getOpcode
(
)
==
Lanai
::
SELECT
&&
"unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
1
:
2
)
;
unsigned
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
getOppositeCondition
(
LPCC
::
CondCode
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
copyImplicitOps
(
MI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> MachineInstr * SparcInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned OpNum = Ops [ 0 ] ; bool isFloat = false ; MachineInstr * NewMI = NULL ; switch ( MI -> getOpcode ( ) ) { case SP :: ORrr : if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 1 ) . getReg ( ) == SP :: G0 && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 2 ) . isReg ( ) ) { if ( OpNum == 0 ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: STri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: LDri ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; case SP :: FMOVS : isFloat = true ; case SP :: FMOVD : if ( OpNum == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: STFri : SP :: STDFri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: LDFri : SP :: LDDFri ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static Optional < unsigned > getTag ( const TargetRegisterInfo * TRI , const MachineInstr & MI , const LoadInfo & LI ) { unsigned Dest = LI . DestReg ? TRI -> getEncodingValue ( LI . DestReg ) : 0 ; unsigned Base = TRI -> getEncodingValue ( LI . BaseReg ) ; unsigned Off ; if ( LI . OffsetOpnd == nullptr ) Off = 0 ; else if ( LI . OffsetOpnd -> isGlobal ( ) || LI . OffsetOpnd -> isSymbol ( ) || LI . OffsetOpnd -> isCPI ( ) ) return None ; else if ( LI . OffsetOpnd -> isReg ( ) ) Off = ( 1 << 5 ) | TRI -> getEncodingValue ( LI . OffsetOpnd -> getReg ( ) ) ; else Off = LI . OffsetOpnd -> getImm ( ) >> 2 ; return makeTag ( Dest , Base , Off ) ; } </s>

getTag - Return an opaque tag representing the current state of the union .


<s> void nds32_asm_file_start_for_isr ( void ) { int i ; for ( i = 0 ; i < NDS32_N_ISR_VECTORS ; i ++ ) { nds32_isr_vectors [ i ] . category = NDS32_ISR_NONE ; strcpy ( nds32_isr_vectors [ i ] . func_name , "" ) ; nds32_isr_vectors [ i ] . save_reg = NDS32_PARTIAL_SAVE ; nds32_isr_vectors [ i ] . nested_type = NDS32_NOT_NESTED ; nds32_isr_vectors [ i ] . total_n_vectors = 0 ; strcpy ( nds32_isr_vectors [ i ] . nmi_name , "" ) ; strcpy ( nds32_isr_vectors [ i ] . warm_name , "" ) ; } } </s>

A helper function to handle isr stuff at the beginning of asm file .


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getTarget
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
;
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARM::tPUSH
ARM::tPOP


<s> void MipsTargetELFStreamer :: emitAssignment ( MCSymbol * Symbol , const MCExpr * Value ) { if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; uint8_t Type = MCELF :: GetType ( Data ) ; if ( ( Type != ELF :: STT_FUNC ) || ! ( MCELF :: getOther ( Data ) & ( ELF :: STO_MIPS_MICROMIPS >> 2 ) ) ) return ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; MCELF :: setOther ( SymbolData , ELF :: STO_MIPS_MICROMIPS >> 2 ) ; } </s>


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .