<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , Subtarget -> isABI_O32 ( ) , Subtarget -> isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget -> mipsSEUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool TOYPassConfig :: addInstSelector ( ) { addPass ( createTOYISelDag ( getTOYTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { CommentStream = & CStream ; InternalInstruction InternalInstr ; dlog_t LoggerFn = logger ; if ( & VStream == & nulls ( ) ) LoggerFn = nullptr ; Region R ( Bytes , Address ) ; int Ret = decodeInstruction ( & InternalInstr , regionReader , ( const void * ) & R , LoggerFn , ( void * ) & VStream , ( const void * ) MII . get ( ) , Address , fMode ) ; if ( Ret ) { Size = InternalInstr . readerCursor - Address ; return Fail ; } else { Size = InternalInstr . length ; return ( ! translateInstruction ( Instr , InternalInstr , this ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> void KudeyarAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( "\t.frame\t$" + StringRef ( KudeyarInstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + "," + Twine ( stackSize ) ) ; } </s>

Kudeyar Kudeyar "\t.frame\t$" Kudeyar ","


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
if
(
!
SelectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget -> is64Bit ( ) ? 64 : 32 ; const Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) { return nullptr ; } else if ( hasMFENCE ( * Subtarget ) ) { Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence ) ; } else { return nullptr ; } LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> static void sparc_emit_set_const64_longway ( rtx op0 , rtx temp , unsigned HOST_WIDE_INT high_bits , unsigned HOST_WIDE_INT low_bits ) { rtx sub_temp ; if ( reload_in_progress || reload_completed ) sub_temp = op0 ; else sub_temp = gen_reg_rtx ( DImode ) ; if ( ( high_bits & 0xfffffc00 ) != 0 ) { emit_insn ( gen_safe_HIGH64 ( temp , high_bits ) ) ; if ( ( high_bits & ~ 0xfffffc00 ) != 0 ) emit_insn ( gen_rtx_SET ( VOIDmode , sub_temp , gen_safe_OR64 ( temp , ( high_bits & 0x3ff ) ) ) ) ; else sub_temp = temp ; } else { emit_insn ( gen_safe_SET64 ( temp , high_bits ) ) ; sub_temp = temp ; } if ( ! reload_in_progress && ! reload_completed ) { rtx temp2 = gen_reg_rtx ( DImode ) ; rtx temp3 = gen_reg_rtx ( DImode ) ; rtx temp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp4 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( 32 ) ) ) ) ; emit_insn ( gen_safe_HIGH64 ( temp2 , low_bits ) ) ; if ( ( low_bits & ~ 0xfffffc00 ) != 0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , temp3 , gen_safe_OR64 ( temp2 , ( low_bits & 0x3ff ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp3 ) ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; } } else { rtx low1 = GEN_INT ( ( low_bits >> ( 32 - 12 ) ) & 0xfff ) ; rtx low2 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 ) ) & 0xfff ) ; rtx low3 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 - 8 ) ) & 0x0ff ) ; int to_shift = 12 ; if ( low1 != const0_rtx ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low1 ) ) ) ; sub_temp = op0 ; to_shift = 12 ; } else { to_shift += 12 ; } if ( low2 != const0_rtx ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low2 ) ) ) ; sub_temp = op0 ; to_shift = 8 ; } else { to_shift += 8 ; } emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; if ( low3 != const0_rtx ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low3 ) ) ) ; } } </s>

Full 64-bit constant decomposition . Even though this is the 'worst ' case , we still optimize a few things away .


<s> X86ProcFamilyEnum getProcFamily ( ) const { return X86ProcFamily ; } </s>


"%qE attribute applies only to initialized variables"

Handle a `` selectany '' attribute ; arguments as in struct attribute_spec.handler .


<s> int mve_vector_mem_operand ( machine_mode mode , rtx op , bool strict ) { enum rtx_code code ; int val , reg_no ; if ( REG_P ( op ) ) { reg_no = arm_effective_regno ( op , strict ) ; return ( ( ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ? reg_no <= LAST_LO_REGNUM : reg_no < LAST_ARM_REGNUM ) || ( ! strict && reg_no >= FIRST_PSEUDO_REGISTER ) ) ; } code = GET_CODE ( op ) ; if ( code == POST_INC || code == PRE_DEC || code == PRE_INC || code == POST_DEC ) { reg_no = arm_effective_regno ( XEXP ( op , 0 ) , strict ) ; return ( ( ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ? reg_no <= LAST_LO_REGNUM : ( reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM ) ) || ( ! strict && reg_no >= FIRST_PSEUDO_REGISTER ) ) ; } else if ( ( ( code == POST_MODIFY || code == PRE_MODIFY ) && GET_CODE ( XEXP ( op , 1 ) ) == PLUS && XEXP ( op , 0 ) == XEXP ( XEXP ( op , 1 ) , 0 ) && REG_P ( XEXP ( op , 0 ) ) && GET_CODE ( XEXP ( XEXP ( op , 1 ) , 1 ) ) == CONST_INT ) || ( reload_completed && code == PLUS && REG_P ( XEXP ( op , 0 ) ) && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ) { reg_no = arm_effective_regno ( XEXP ( op , 0 ) , strict ) ; if ( code == PLUS ) val = INTVAL ( XEXP ( op , 1 ) ) ; else val = INTVAL ( XEXP ( XEXP ( op , 1 ) , 1 ) ) ; switch ( mode ) { case E_V16QImode : case E_V8QImode : case E_V4QImode : if ( abs ( val ) > 127 ) return FALSE ; break ; case E_V8HImode : case E_V8HFmode : case E_V4HImode : case E_V4HFmode : if ( val % 2 != 0 || abs ( val ) > 254 ) return FALSE ; break ; case E_V4SImode : case E_V4SFmode : if ( val % 4 != 0 || abs ( val ) > 508 ) return FALSE ; break ; default : return FALSE ; } return ( ( ! strict && reg_no >= FIRST_PSEUDO_REGISTER ) || ( MVE_STN_LDW_MODE ( mode ) ? reg_no <= LAST_LO_REGNUM : ( reg_no < LAST_ARM_REGNUM && ( code == PLUS || reg_no != SP_REGNUM ) ) ) ) ; } return FALSE ; } </s>

This function returns TRUE on matching mode and op.1 . For given modes , check for [ Rn ] , return TRUE for Rn < = LO_REGS.2 . For other modes , check for [ Rn ] , return TRUE for Rn < R15 ( expect R13 ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool aarch64_sve_valid_immediate ( unsigned HOST_WIDE_INT val64 , simd_immediate_info * info ) { scalar_int_mode mode = DImode ; unsigned int val32 = val64 & 0xffffffff ; if ( val32 == ( val64 >> 32 ) ) { mode = SImode ; unsigned int val16 = val32 & 0xffff ; if ( val16 == ( val32 >> 16 ) ) { mode = HImode ; unsigned int val8 = val16 & 0xff ; if ( val8 == ( val16 >> 8 ) ) mode = QImode ; } } HOST_WIDE_INT val = trunc_int_for_mode ( val64 , mode ) ; if ( IN_RANGE ( val , - 0x80 , 0x7f ) ) { if ( info ) * info = simd_immediate_info ( mode , val ) ; return true ; } if ( ( val & 0xff ) == 0 && IN_RANGE ( val , - 0x8000 , 0x7f00 ) ) { if ( info ) * info = simd_immediate_info ( mode , val ) ; return true ; } if ( aarch64_bitmask_imm ( val64 , mode ) ) { if ( info ) * info = simd_immediate_info ( mode , val ) ; return true ; } return false ; } </s>

Return true if replicating VAL64 gives a valid immediate for an SVE MOV instruction . If INFO is nonnull , use it to describe valid immediates .


<s> void LanaiTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case LanaiISD :: SETCC : Known = KnownBits ( BitWidth ) ; Known . Zero . setBits ( 1 , BitWidth ) ; break ; case LanaiISD :: SELECT_CC : KnownBits Known2 ; Known = DAG . computeKnownBits ( Op -> getOperand ( 0 ) , Depth + 1 ) ; Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


"mips16 and nomips16 specified on the same function"

Reset the subtarget for the Mips target .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"A57 FP Anti-dependency breaker"
;
}
</s>


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op_true , rtx op_false , rtx cond , rtx cc_op0 , rtx cc_op1 ) { machine_mode dest_mode = GET_MODE ( dest ) ; machine_mode mask_mode = GET_MODE ( cc_op0 ) ; enum rtx_code rcode = GET_CODE ( cond ) ; machine_mode cc_mode = CCmode ; rtx mask ; rtx cond2 ; rtx tmp ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return 0 ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return 0 ; break ; case GTU : case GEU : case LTU : case LEU : cc_mode = CCUNSmode ; break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return 0 ; if ( invert_move ) { tmp = op_true ; op_true = op_false ; op_false = tmp ; } cond2 = gen_rtx_fmt_ee ( NE , cc_mode , gen_lowpart ( dest_mode , mask ) , CONST0_RTX ( dest_mode ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( dest_mode , cond2 , op_true , op_false ) ) ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

PowerPC PPC PPC PPC 0 PPC::VRSAVE PPC::CR2 PPC::CR4 PPC PPC PPC PPC::MFCR PPC::R12 PPC::STW PPC::R12


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool ARMTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! DisableLdStOpti && ! Subtarget . isThumb ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None && ! DisableIfConversion && ! Subtarget . isThumb ( ) ) PM . add ( createIfConverterPass ( ) ) ; PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool CJGFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( CJG :: POP ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
void
AArch64FrameLowering
::
orderFrameObjects
(
const
MachineFunction
&
MF
,
SmallVectorImpl
<
int
>
&
ObjectsToAllocate
)
const
{
if
(
!
OrderFrameObjects
||
ObjectsToAllocate
.
empty
(
)
)
return
;
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
std
::
vector
<
FrameObject
>
FrameObjects
(
MFI
.
getObjectIndexEnd
(
)
)
;
for
(
auto
&
Obj
:
ObjectsToAllocate
)
{
FrameObjects
[
Obj
]
.
IsValid
=
true
;
FrameObjects
[
Obj
]
.
ObjectIndex
=
Obj
;
}
GroupBuilder
GB
(
FrameObjects
)
;
for
(
auto
&
MBB
:
MF
)
{
for
(
auto
&
MI
:
MBB
)
{
if
(
MI
.
isDebugInstr
(
)
)
continue
;
int
OpIndex
;
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
STGloop
:
case
AArch64
::
STZGloop
:
OpIndex
=
3
;
break
;
case
AArch64
::
STGOffset
:
case
AArch64
::
STZGOffset
:
case
AArch64
::
ST2GOffset
:
case
AArch64
::
STZ2GOffset
:
OpIndex
=
1
;
break
;
default
:
OpIndex
=
1
;
}
int
TaggedFI
=
1
;
if
(
OpIndex
>=
0
)
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OpIndex
)
;
if
(
MO
.
isFI
(
)
)
{
int
FI
=
MO
.
getIndex
(
)
;
if
(
FI
>=
0
&&
FI
<
MFI
.
getObjectIndexEnd
(
)
&&
FrameObjects
[
FI
]
.
IsValid
)
TaggedFI
=
FI
;
}
}
if
(
TaggedFI
>=
0
)
GB
.
AddMember
(
TaggedFI
)
;
else
GB
.
EndCurrentGroup
(
)
;
}
GB
.
EndCurrentGroup
(
)
;
}
const
AArch64FunctionInfo
&
AFI
=
*
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
Optional
<
int
>
TBPI
=
AFI
.
getTaggedBasePointerIndex
(
)
;
if
(
TBPI
)
{
FrameObjects
[
*
TBPI
]
.
ObjectFirst
=
true
;
FrameObjects
[
*
TBPI
]
.
GroupFirst
=
true
;
int
FirstGroupIndex
=
FrameObjects
[
*
TBPI
]
.
GroupIndex
;
if
(
FirstGroupIndex
>=
0
)
for
(
FrameObject
&
Object
:
FrameObjects
)
if
(
Object
.
GroupIndex
==
FirstGroupIndex
)
Object
.
GroupFirst
=
true
;
}
llvm
::
stable_sort
(
FrameObjects
,
FrameObjectCompare
)
;
int
i
=
0
;
for
(
auto
&
Obj
:
FrameObjects
)
{
if
(
!
Obj
.
IsValid
)
break
;
ObjectsToAllocate
[
i
++
]
=
Obj
.
ObjectIndex
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Final frame order:\n"
;
for
(
auto
&
Obj
:
FrameObjects
)
{
if
(
!
Obj
.
IsValid
)
break
;
dbgs
(
)
<<
"  "
<<
Obj
.
ObjectIndex
<<
": group "
<<
Obj
.
GroupIndex
;
if
(
Obj
.
ObjectFirst
)
dbgs
(
)
<<
", first"
;
if
(
Obj
.
GroupFirst
)
dbgs
(
)
<<
", group-first"
;
dbgs
(
)
<<
"\n"
;
}
)
;
}
</s>


<s> SDValue MipsSETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: SMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Mult , true , true , DAG ) ; case ISD :: UMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Multu , true , true , DAG ) ; case ISD :: MULHS : return lowerMulDiv ( Op , MipsISD :: Mult , false , true , DAG ) ; case ISD :: MULHU : return lowerMulDiv ( Op , MipsISD :: Multu , false , true , DAG ) ; case ISD :: MUL : return lowerMulDiv ( Op , MipsISD :: Mult , true , false , DAG ) ; case ISD :: SDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRem , true , true , DAG ) ; case ISD :: UDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRemU , true , true , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_VOID : return lowerINTRINSIC_VOID ( Op , DAG ) ; } return MipsTargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::LOAD ISD::STORE ISD::SMUL_LOHI MipsISD::Mult ISD::UMUL_LOHI MipsISD::Multu ISD::MULHS MipsISD::Mult ISD::MULHU MipsISD::Multu ISD::MUL MipsISD::Mult ISD::SDIVREM MipsISD::DivRem ISD::UDIVREM MipsISD::DivRemU ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_VOID Mips


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static void vector_init_bshuffle ( rtx target , rtx elt , machine_mode mode , machine_mode inner_mode ) { rtx t1 , final_insn , sel ; int bmask ; t1 = gen_reg_rtx ( mode ) ; elt = convert_modes ( SImode , inner_mode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; switch ( mode ) { case V2SImode : final_insn = gen_bshufflev2si_vis ( target , t1 , t1 ) ; bmask = 0x45674567 ; break ; case V4HImode : final_insn = gen_bshufflev4hi_vis ( target , t1 , t1 ) ; bmask = 0x67676767 ; break ; case V8QImode : final_insn = gen_bshufflev8qi_vis ( target , t1 , t1 ) ; bmask = 0x77777777 ; break ; default : gcc_unreachable ( ) ; } sel = force_reg ( SImode , GEN_INT ( bmask ) ) ; emit_insn ( gen_bmasksi_vis ( gen_reg_rtx ( SImode ) , sel , const0_rtx ) ) ; emit_insn ( final_insn ) ; } </s>

Subroutine of sparc_expand_vector_init . Emit code to initialize all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn . MODE and INNER_MODE are the modes describing TARGET .


<s> static int iamcu_alignment ( tree type , int align ) { machine_mode mode ; if ( align < 32 || TYPE_USER_ALIGN ( type ) ) return align ; type = strip_array_types ( type ) ; if ( TYPE_ATOMIC ( type ) ) return align ; mode = TYPE_MODE ( type ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_INT : case MODE_COMPLEX_INT : case MODE_COMPLEX_FLOAT : case MODE_FLOAT : case MODE_DECIMAL_FLOAT : return 32 ; default : return align ; } } </s>

Compute the alignment for a variable for Intel MCU psABI . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have .


<s> const LegalizerInfo * getLegalizerInfo ( ) const override { return nullptr ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> bool nds32_n13_last_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; return n13_consumed_by_e2_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to E2 .


<s> static rtx mips_cprestore_slot ( rtx temp , bool load_p ) { rtx base ; HOST_WIDE_INT offset ; mips_get_cprestore_base_and_offset ( & base , & offset , load_p ) ; return gen_frame_mem ( Pmode , mips_add_offset ( temp , base , offset ) ) ; } </s>

Return a MEM rtx for the cprestore slot . LOAD_P is true if we are going to load from it , false if we are going to store to it . Use TEMP as a temporary register if need be .


<s> bool aarch64_offset_7bit_signed_scaled_p ( machine_mode mode , HOST_WIDE_INT offset ) { return ( offset >= - 64 * GET_MODE_SIZE ( mode ) && offset < 64 * GET_MODE_SIZE ( mode ) && offset % GET_MODE_SIZE ( mode ) == 0 ) ; } </s>

Return true if OFFSET is a signed 7-bit value multiplied by the size of MODE .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < LoongArchSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
MipsInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\t.set\tpush\n"
;
O
<<
"\t.set\tmips32r2\n"
;
break
;
case
Mips
::
Save16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
SaveX16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
case
Mips
::
Restore16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
RestoreX16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
}
if
(
!
printAliasInstr
(
MI
,
O
)
&&
!
printAlias
(
*
MI
,
O
)
)
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\n\t.set\tpop"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { auto Reloc = STI . getTargetTriple ( ) . getEnvironment ( ) == Triple :: GNUILP32 ? ELF :: R_AARCH64_P32_TLSDESC_CALL : ELF :: R_AARCH64_TLSDESC_CALL ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , MCFixupKind ( FirstLiteralRelocationKind + Reloc ) ) ) ; return ; } if ( MI . getOpcode ( ) == AArch64 :: CompilerBarrier || MI . getOpcode ( ) == AArch64 :: SPACE ) { return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint32_t > ( OS , Binary , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> const CallLowering * PPCSubtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s> machine_mode memory_vector_mode ( const function_instance & ) const override { return m_mode ; } </s>

If the function addresses memory , return a vector mode whose GET_MODE_NUNITS is the number of elements addressed and whose GET_MODE_INNER is the mode of a single scalar memory element .


<s> static rtx arm_expand_unop_builtin ( enum insn_code icode , tree arglist , rtx target , int do_load ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of unop insns .


<s> bool isCall ( unsigned Opcode , bool * IsIndirectCall ) { * IsIndirectCall = false ; switch ( Opcode ) { default : return false ; case Mips :: JAL : case Mips :: BAL_BR : case Mips :: BLTZAL : case Mips :: BGEZAL : return true ; case Mips :: JALR : * IsIndirectCall = true ; return true ; } } </s>

Mips Mips::JAL Mips::BAL_BR Mips::BLTZAL Mips::BGEZAL Mips::JALR


<s> static int ix86_mode_exit ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return X86_DIRFLAG_ANY ; case AVX_U128 : return ix86_avx_u128_mode_exit ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function exit .


<s> bool aarch64_masks_and_shift_for_bfi_p ( scalar_int_mode mode , unsigned HOST_WIDE_INT mask1 , unsigned HOST_WIDE_INT shft_amnt , unsigned HOST_WIDE_INT mask2 ) { unsigned HOST_WIDE_INT t ; if ( mask1 != ~ mask2 ) return false ; if ( mask2 == 0 || mask2 == HOST_WIDE_INT_M1U ) return false ; gcc_assert ( shft_amnt < GET_MODE_BITSIZE ( mode ) ) ; t = mask2 + ( HOST_WIDE_INT_1U << shft_amnt ) ; return ( t == ( t & - t ) ) ; } </s>

Return true if the masks and a shift amount from an RTX of the form ( ( x & MASK1 ) | ( ( y < < SHIFT_AMNT ) & MASK2 ) ) are valid to combine into a BFI instruction of mode MODE . See * arch64_bfi patterns .


<s> void X86FrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; if ( Offset == 0 ) { MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: SUB64ri8 ) , StackPtr ) . addReg ( StackPtr ) . addImm ( 0 ) ; if ( ! InEpilogue ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; } while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = 0 ; if ( isSub && ! isEAXLiveIn ( MBB ) ) Reg = ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? X86 :: MOV64ri : X86 :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) && false ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; else MI -> setFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; continue ; } } MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( isSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> static void sparc_handle_vis_mul8x16 ( tree * n_elts , enum sparc_builtins fncode , tree inner_type , tree cst0 , tree cst1 ) { unsigned i , num = VECTOR_CST_NELTS ( cst0 ) ; int scale ; switch ( fncode ) { case SPARC_BUILTIN_FMUL8X16 : for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , i ) ) ) ; n_elts [ i ] = build_int_cst ( inner_type , val ) ; } break ; case SPARC_BUILTIN_FMUL8X16AU : scale = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , 0 ) ) ; for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , scale ) ; n_elts [ i ] = build_int_cst ( inner_type , val ) ; } break ; case SPARC_BUILTIN_FMUL8X16AL : scale = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , 1 ) ) ; for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , scale ) ; n_elts [ i ] = build_int_cst ( inner_type , val ) ; } break ; default : gcc_unreachable ( ) ; } } </s>

Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified by FNCODE . All of the elements in ELTS0 and ELTS1 lists must be integer constants . A tree list with the results of the multiplications is returned , and each element in the list is of INNER_TYPE .


<s> void KudeyarInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>


<s> const char * X86TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget . hasSSE2 ( ) ) return "Y" ; if ( Subtarget . hasSSE1 ( ) ) return "x" ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> unsigned SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ; } </s>


"r%d has non convertible def in insn %d\n"

"r%d has non convertible use in insn %d\n"

For a register REGNO , scan instructions for its defs and uses . Put REGNO in REGS if a def or use is n't in CANDIDATES .


<s> tree gimple_folder :: convert_pred ( gimple_seq & stmts , tree vectype , unsigned int argno ) { tree pred = gimple_call_arg ( call , argno ) ; if ( known_eq ( TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( pred ) ) , TYPE_VECTOR_SUBPARTS ( vectype ) ) ) return pred ; return gimple_build ( & stmts , VIEW_CONVERT_EXPR , truth_type_for ( vectype ) , pred ) ; } </s>

Convert predicate argument ARGNO so that it has the type appropriate for an operation on VECTYPE . Add any new statements to STMTS .


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) Known . Zero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpequq_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtsq_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : case Intrinsic :: ppc_altivec_vcmpgtuq_p : Known . Zero = ~ 1U ; break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
(
void
)
RetFastCC_ARM_APCS
;
(
void
)
FastCC_ARM_APCS
;
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
FloatABIType
==
FloatABI
::
Hard
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
ARM_AAPCS_VFP
:
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM


<s>
const
MCFixupKindInfo
&
Cpu0AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Cpu0
::
NumTargetFixupKinds
]
=
{
{
"fixup_Cpu0_32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Cpu0_PC24"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Cpu0_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOTTP"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TP_HI"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TP_LO"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_DTP_HI"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_DTP_LO"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_LO16"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
bool
X86CallFrameOptimization
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
STI
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
STI
->
getInstrInfo
(
)
;
TFL
=
STI
->
getFrameLowering
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
const
X86RegisterInfo
&
RegInfo
=
*
static_cast
<
const
X86RegisterInfo
*
>
(
STI
->
getRegisterInfo
(
)
)
;
SlotSize
=
RegInfo
.
getSlotSize
(
)
;
assert
(
isPowerOf2_32
(
SlotSize
)
&&
"Expect power of 2 stack slot size"
)
;
Log2SlotSize
=
Log2_32
(
SlotSize
)
;
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
||
!
isLegal
(
MF
)
)
return
false
;
unsigned
FrameSetupOpcode
=
TII
->
getCallFrameSetupOpcode
(
)
;
bool
Changed
=
false
;
ContextVector
CallSeqVector
;
for
(
auto
&
MBB
:
MF
)
for
(
auto
&
MI
:
MBB
)
if
(
MI
.
getOpcode
(
)
==
FrameSetupOpcode
)
{
CallContext
Context
;
collectCallInfo
(
MF
,
MBB
,
MI
,
Context
)
;
CallSeqVector
.
push_back
(
Context
)
;
}
if
(
!
isProfitable
(
MF
,
CallSeqVector
)
)
return
false
;
for
(
auto
CC
:
CallSeqVector
)
{
if
(
CC
.
UsePush
)
{
adjustCallSequence
(
MF
,
CC
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>


<s> static unsigned int insn_is_store_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET && MEM_P ( SET_DEST ( body ) ) ) return 1 ; if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && MEM_P ( SET_DEST ( set ) ) ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a store insn , including permuting stores that represent an stvxd2x instruction ; else return 0 .


<s> const TargetRegisterClass * X86RegisterInfo :: getGPRsForTailCall ( const MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsWin64 || ( F && F -> getCallingConv ( ) == CallingConv :: Win64 ) ) return & X86 :: GR64_TCW64RegClass ; else if ( Is64Bit ) return & X86 :: GR64_TCRegClass ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & X86 :: GR32RegClass ; return & X86 :: GR32_TCRegClass ; } </s>

getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS , STI ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Is64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , Address , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Is16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const Node * getDest ( ) const { return Dest ; } </s>

Get the current destination live range .


<s> const MCPhysReg * Cpu0RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_O32_SaveList ; } </s>


<s>
bool
AArch64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_MCSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
MO
.
getMCSymbol
(
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BEQ_MM
:
return
Mips
::
BNE_MM
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BNE_MM
:
return
Mips
::
BEQ_MM
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
case
Mips
::
BEQZC_MM
:
return
Mips
::
BNEZC_MM
;
case
Mips
::
BNEZC_MM
:
return
Mips
::
BEQZC_MM
;
case
Mips
::
BEQZC
:
return
Mips
::
BNEZC
;
case
Mips
::
BNEZC
:
return
Mips
::
BEQZC
;
case
Mips
::
BEQC
:
return
Mips
::
BNEC
;
case
Mips
::
BNEC
:
return
Mips
::
BEQC
;
case
Mips
::
BGTZC
:
return
Mips
::
BLEZC
;
case
Mips
::
BGEZC
:
return
Mips
::
BLTZC
;
case
Mips
::
BLTZC
:
return
Mips
::
BGEZC
;
case
Mips
::
BLEZC
:
return
Mips
::
BGTZC
;
case
Mips
::
BEQZC64
:
return
Mips
::
BNEZC64
;
case
Mips
::
BNEZC64
:
return
Mips
::
BEQZC64
;
case
Mips
::
BEQC64
:
return
Mips
::
BNEC64
;
case
Mips
::
BNEC64
:
return
Mips
::
BEQC64
;
case
Mips
::
BGEC64
:
return
Mips
::
BLTC64
;
case
Mips
::
BGEUC64
:
return
Mips
::
BLTUC64
;
case
Mips
::
BLTC64
:
return
Mips
::
BGEC64
;
case
Mips
::
BLTUC64
:
return
Mips
::
BGEUC64
;
case
Mips
::
BGTZC64
:
return
Mips
::
BLEZC64
;
case
Mips
::
BGEZC64
:
return
Mips
::
BLTZC64
;
case
Mips
::
BLTZC64
:
return
Mips
::
BGEZC64
;
case
Mips
::
BLEZC64
:
return
Mips
::
BGTZC64
;
case
Mips
::
BBIT0
:
return
Mips
::
BBIT1
;
case
Mips
::
BBIT1
:
return
Mips
::
BBIT0
;
case
Mips
::
BBIT032
:
return
Mips
::
BBIT132
;
case
Mips
::
BBIT132
:
return
Mips
::
BBIT032
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s>
SDValue
SystemZTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

SystemZ
SystemZ
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


"Cannot load this register from stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s>
void
mmix_asm_output_reg_push
(
FILE
*
stream
,
int
regno
)
{
fprintf
(
stream
,
"\tSUBU %s,%s,8\n\tSTOU %s,%s,0\n"
,
reg_names
[
MMIX_STACK_POINTER_REGNUM
]
,
reg_names
[
MMIX_STACK_POINTER_REGNUM
]
,
reg_names
[
MMIX_OUTPUT_REGNO
(
regno
)
]
,
reg_names
[
MMIX_STACK_POINTER_REGNUM
]
)
;
}
</s>


Convert the CONST_WIDE_INT operand OP to broadcast in MODE .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> bool PPCFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT Evt = TLI . getValueType ( Ty , true ) ; if ( Evt == MVT :: Other || ! Evt . isSimple ( ) ) return false ; VT = Evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BR_JT : return lowerBR_JT ( Op , DAG ) ; case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return lowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return lowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: ADD : return lowerADD ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BR_JT ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::ADD ISD::FP_TO_SINT


<s> rtx extract_offset_rtx ( rtx_insn * insn ) { rtx mem_rtx ; rtx plus_rtx ; rtx offset_rtx ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : return NULL_RTX ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case TYPE_FSTORE : mem_rtx = extract_mem_rtx ( insn ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( MEM_P ( mem_rtx ) ) ; if ( REG_P ( XEXP ( mem_rtx , 0 ) ) ) return NULL_RTX ; plus_rtx = XEXP ( mem_rtx , 0 ) ; switch ( GET_CODE ( plus_rtx ) ) { case SYMBOL_REF : case CONST : case POST_INC : case POST_DEC : return NULL_RTX ; case PLUS : if ( REG_P ( XEXP ( plus_rtx , 0 ) ) ) offset_rtx = XEXP ( plus_rtx , 1 ) ; else { gcc_assert ( REG_P ( XEXP ( plus_rtx , 1 ) ) ) ; offset_rtx = XEXP ( plus_rtx , 0 ) ; } if ( ARITHMETIC_P ( offset_rtx ) ) { gcc_assert ( GET_CODE ( offset_rtx ) == MULT ) ; gcc_assert ( REG_P ( XEXP ( offset_rtx , 0 ) ) ) ; offset_rtx = XEXP ( offset_rtx , 0 ) ; } break ; case LO_SUM : offset_rtx = XEXP ( plus_rtx , 1 ) ; break ; case POST_MODIFY : gcc_assert ( REG_P ( XEXP ( plus_rtx , 0 ) ) ) ; plus_rtx = XEXP ( plus_rtx , 1 ) ; gcc_assert ( GET_CODE ( plus_rtx ) == PLUS ) ; offset_rtx = XEXP ( plus_rtx , 0 ) ; break ; default : gcc_unreachable ( ) ; } return offset_rtx ; } </s>

Extract the offset rtx from load/store insns . The function returns NULL_RTX if offset is absent .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>


<s> static bool arm_cxx_key_method_may_be_inline ( void ) { return ! TARGET_AAPCS_BASED ; } </s>

The EABI says that an inline function may never be the key method .


<s> int function_arg_boundary ( enum machine_mode mode , tree type ) { unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return alignment ; } </s>

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs to be double word aligned . Doubleword align SPE vectors . Quadword align Altivec vectors . Quadword align large synthetic vector types .


<s> LLT AArch64TargetLowering :: getOptimalMemOpLLT ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return LLT :: fixed_vector ( 2 , 64 ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return LLT :: scalar ( 128 ) ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return LLT :: scalar ( 64 ) ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return LLT :: scalar ( 32 ) ; return LLT ( ) ; } </s>


<s> bool aarch64_mov128_immediate ( rtx imm ) { if ( GET_CODE ( imm ) == CONST_INT ) return true ; gcc_assert ( CONST_WIDE_INT_NUNITS ( imm ) == 2 ) ; rtx lo = GEN_INT ( CONST_WIDE_INT_ELT ( imm , 0 ) ) ; rtx hi = GEN_INT ( CONST_WIDE_INT_ELT ( imm , 1 ) ) ; return aarch64_internal_mov_immediate ( NULL_RTX , lo , false , DImode ) + aarch64_internal_mov_immediate ( NULL_RTX , hi , false , DImode ) <= 4 ; } </s>

Return whether imm is a 128-bit immediate which is simple enough to expand inline .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = static_cast < const ARMTargetMachine & > ( TM ) . TargetABI == ARMTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool hasFP ( const MachineFunction & ) const override { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool aarch64_is_long_call_p ( rtx sym ) { return aarch64_decl_is_long_call_p ( SYMBOL_REF_DECL ( sym ) ) ; } </s>

Return true if calls to symbol-ref SYM should be treated as long-calls ( ie called via a register ) .


<s> static tree aarch64_builtin_decl ( unsigned int code , bool initialize_p ) { unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return aarch64_general_builtin_decl ( subcode , initialize_p ) ; case AARCH64_BUILTIN_SVE : return aarch64_sve :: builtin_decl ( subcode , initialize_p ) ; } gcc_unreachable ( ) ; } </s>


<s>
int
MipsRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .

Mips
Mips
"What is the dwarf register number"
1


<s> static void arm_pre_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_memory_barrier ( ) ) ; } </s>

Emit a memory barrier around an atomic sequence according to MODEL .


<s> PPCSubtarget & PPCSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_SWAP
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
return
lowerToVVP
(
Op
,
DAG
)
;
}
}
</s>

VE
VE
"Should not custom lower this!"
ISD::ATOMIC_FENCE
ISD::ATOMIC_SWAP
ISD::BlockAddress
ISD::ConstantPool
ISD::DYNAMIC_STACKALLOC
ISD::FRAMEADDR
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::JumpTable
ISD::LOAD
ISD::BUILD_VECTOR
VE
ISD::STORE
ISD::VASTART
ISD::VAARG


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( ! HasNopl ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> write8 ( 0x90 ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { return true ; } </s>

Helper functions for atomic operations .


"CFGuard check mechanism only used on 32-bit X86"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
bool
AArch64A53Fix835769
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"***** AArch64A53Fix835769 *****\n"
)
;
bool
Changed
=
false
;
TII
=
F
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
auto
&
MBB
:
F
)
{
Changed
|=
runOnBasicBlock
(
MBB
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static int arm_comp_type_attributes ( const_tree type1 , const_tree type2 ) { int l1 , l2 , s1 , s2 ; if ( TREE_CODE ( type1 ) != FUNCTION_TYPE ) return 1 ; l1 = lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; l2 = lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; s1 = lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; s2 = lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( l1 | l2 | s1 | s2 ) { if ( ( l1 != l2 ) || ( s1 != s2 ) ) return 0 ; if ( ( l1 & s2 ) || ( l2 & s1 ) ) return 0 ; } l1 = lookup_attribute ( "isr" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; if ( ! l1 ) l1 = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; l2 = lookup_attribute ( "isr" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( ! l2 ) l1 = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( l1 != l2 ) return 0 ; return 1 ; } </s>

Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s> static int get_spec_unspec_code ( const_rtx x ) { if ( GET_CODE ( x ) != UNSPEC ) return - 1 ; { int code ; code = XINT ( x , 1 ) ; switch ( code ) { case UNSPEC_LDA : case UNSPEC_LDS : case UNSPEC_LDS_A : case UNSPEC_LDSA : return code ; default : return - 1 ; } } } </s>

If X is an unspec part of a speculative load , return its code . Return -1 otherwise .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return nullptr ; return STI . isTargetDarwin ( ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> static void mips_sim_record_set ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { struct mips_sim * state ; unsigned int i ; state = data ; if ( REG_P ( x ) ) for ( i = 0 ; i < HARD_REGNO_NREGS ( REGNO ( x ) , GET_MODE ( x ) ) ; i ++ ) { state -> last_set [ REGNO ( x ) + i ] . insn = mips_sim_insn ; state -> last_set [ REGNO ( x ) + i ] . time = state -> time ; } } </s>

mips_sim_insn has just set X. Update the LAST_SET array in simulation state DATA .


<s> static int arm_adjust_cost ( rtx insn , rtx link , rtx dep , int cost ) { rtx i_pat , d_pat ; if ( arm_tune_xscale && REG_NOTE_KIND ( link ) == 0 && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { int shift_opnum = get_attr_shift ( insn ) ; enum attr_type attr_type = get_attr_type ( dep ) ; if ( shift_opnum != 0 && ( attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG ) ) { rtx shifted_operand ; int opno ; extract_insn ( insn ) ; shifted_operand = recog_data . operand [ shift_opnum ] ; extract_insn ( dep ) ; preprocess_constraints ( ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] == OP_IN ) continue ; if ( reg_overlap_mentioned_p ( recog_data . operand [ opno ] , shifted_operand ) ) return 2 ; } } } if ( REG_NOTE_KIND ( link ) == REG_DEP_ANTI || REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) return 0 ; if ( REG_NOTE_KIND ( link ) == 0 && GET_CODE ( insn ) == CALL_INSN ) return 1 ; if ( ( i_pat = single_set ( insn ) ) != NULL && GET_CODE ( SET_SRC ( i_pat ) ) == MEM && ( d_pat = single_set ( dep ) ) != NULL && GET_CODE ( SET_DEST ( d_pat ) ) == MEM ) { rtx src_mem = XEXP ( SET_SRC ( i_pat ) , 0 ) ; if ( ( GET_CODE ( src_mem ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( src_mem ) ) || reg_mentioned_p ( stack_pointer_rtx , src_mem ) || reg_mentioned_p ( frame_pointer_rtx , src_mem ) || reg_mentioned_p ( hard_frame_pointer_rtx , src_mem ) ) return 1 ; } return cost ; } </s>

This function implements the target macro TARGET_SCHED_ADJUST_COST . It corrects the value of COST based on the relationship between INSN and DEP through the dependence LINK . It returns the new value . There is a per-core adjust_cost hook to adjust scheduler costs and the per-core hook can choose to completely override the generic adjust_cost function . Only put bits of code into arm_adjust_cost that are common across all cores .


<s> bool MipsAsmPrinter :: doFinalization ( Module & M ) { for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I ) ; O << '\n' ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool ARMBaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; unsigned SrcReg , SrcReg2 ; int CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> bool fp_one_operand ( rtx op ) { REAL_VALUE_TYPE r ; if ( GET_MODE ( op ) != SFmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r , dconst1 ) ; } </s>

Nonzero if OP is a floating point value with value 1.0 .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , const BranchProbability & Probability ) const { if ( ! TCycles || ! FCycles ) return false ; unsigned TUnpredCost = Probability . scale ( TCycles ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 ; UnpredCost += Subtarget . getMispredictionPenalty ( ) / 10 ; return ( TCycles + FCycles + TExtra + FExtra ) <= UnpredCost ; } </s>


<s> static void aarch64_emit_bic ( machine_mode mode , rtx dst , rtx s1 , rtx s2 , int shift ) { rtx shift_rtx = GEN_INT ( shift ) ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case SImode : gen = gen_and_one_cmpl_lshrsi3 ; break ; case DImode : gen = gen_and_one_cmpl_lshrdi3 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , s2 , shift_rtx , s1 ) ) ; } </s>


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
void
ARMTargetStreamer
::
emitInst
(
uint32_t
Inst
,
char
Suffix
)
{
unsigned
Size
;
char
Buffer
[
4
]
;
const
bool
LittleEndian
=
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
->
isLittleEndian
(
)
;
switch
(
Suffix
)
{
case
'\0'
:
Size
=
4
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
++
)
{
const
unsigned
I
=
LittleEndian
(
Size
II
1
)
:
II
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I
*
CHAR_BIT
)
;
}
break
;
case
'n'
:
case
'w'
:
Size
=
(
Suffix
==
'n'
2
:
4
)
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
=
II
+
2
)
{
const
unsigned
I0
=
LittleEndian
II
+
0
:
II
+
1
;
const
unsigned
I1
=
LittleEndian
II
+
1
:
II
+
0
;
Buffer
[
Size
II
2
]
=
uint8_t
(
Inst
>>
I0
*
CHAR_BIT
)
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I1
*
CHAR_BIT
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid Suffix"
)
;
}
getStreamer
(
)
.
EmitBytes
(
StringRef
(
Buffer
,
Size
)
)
;
}
</s>

Callback used to implement the .inst directive .


<s> const ARMBaseInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> static void union_defs ( swap_web_entry * insn_entry , rtx insn , df_ref use ) { struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; gcc_assert ( NONDEBUG_INSN_P ( def_insn ) ) ; unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( def_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing definitions that reach USE . Detect whether USE is live-in to the current function .


<s> unsigned getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool NEONMoveFixPass :: runOnMachineFunction ( MachineFunction & Fn ) { ARMFunctionInfo * AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; const TargetMachine & TM = Fn . getTarget ( ) ; if ( AFI -> isThumbFunction ( ) ) return false ; TRI = TM . getRegisterInfo ( ) ; TII = static_cast < const ARMBaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= InsertMoves ( MBB ) ; } return Modified ; } </s>


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( RealignStack && ! MFI -> hasVarSizedObjects ( ) ) ; } </s>

True if the stack can be realigned for the target .


<s> bool mips_expand_block_move ( rtx dest , rtx src , rtx length ) { if ( ! ISA_HAS_LWL_LWR ) return false ; if ( CONST_INT_P ( length ) ) { if ( INTVAL ( length ) <= MIPS_MAX_MOVE_BYTES_STRAIGHT ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) , MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } } return false ; } </s>

Expand a movmemsi instruction , which copies LENGTH bytes from memory reference SRC to memory reference DEST .


<s> bool doInitialization ( Loop * L , LPPassManager & LPM ) override { LoadPairs . clear ( ) ; WideLoads . clear ( ) ; return true ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static void ATTRIBUTE_UNUSED loongarch_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.dtprelword\t" , file ) ; break ; case 8 : fputs ( "\t.dtpreldword\t" , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; fputs ( "+0x8000" , file ) ; } </s>


<s> int X86FrameLowering :: getInitialCFAOffset ( const MachineFunction & MF ) const { return TRI -> getSlotSize ( ) ; } </s>


"Unexpected instruction for custom inserter!"


<s> static machine_mode aarch64_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_SVE && aarch64_cmp_autovec_modes ( VNx16QImode , V16QImode ) ) return aarch64_full_sve_mode ( mode ) . else_mode ( word_mode ) ; if ( TARGET_SIMD ) return aarch64_vq_mode ( mode ) . else_mode ( word_mode ) ; return word_mode ; } </s>

Return 128-bit container as the preferred SIMD mode for MODE .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX512 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( Is64Bit && HasAVX512 ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( CC == CallingConv :: Cold ) return CSR_MostRegs_64_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> const uint32_t * VERegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_RegMask ; } </s>


<s> int nds32_target_alignment ( rtx_insn * label ) { rtx_insn * insn ; if ( optimize_size ) return 0 ; insn = next_active_insn ( label ) ; if ( insn == 0 ) return 0 ; else if ( ( get_attr_length ( insn ) % 4 ) == 0 ) return 2 ; else return 0 ; } </s>

Return align 2 ( log base 2 ) if the next instruction of LABEL is 4 byte .


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
,
Subtarget
)
;
case
ISD
::
SHL
:
Val
=
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips
Mips
ISD::AND
ISD::OR
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0
ARMCC::AL


<s> void MipsMCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> int fp_mov_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { long i ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , i ) ; return SPARC_SIMM13_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a single mov instruction .


<s> static inline int arm_arm_address_cost ( rtx x ) { enum rtx_code c = GET_CODE ( x ) ; if ( c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC ) return 0 ; if ( c == MEM || c == LABEL_REF || c == SYMBOL_REF ) return 10 ; if ( c == PLUS ) { if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) return 2 ; if ( ARITHMETIC_P ( XEXP ( x , 0 ) ) || ARITHMETIC_P ( XEXP ( x , 1 ) ) ) return 3 ; return 4 ; } return 6 ; } </s>

All address computations that can be done are free , but rtx cost returns the same for practically all of them . So we weight the different types of address here in the order ( most pref first ) : PRE/POST_INC/DEC , SHIFT or NON-INT sum , INT sum , REG , MEM or LABEL .


<s> static int scheduled_good_insn ( rtx_insn * last ) { if ( last && recog_memoized ( last ) >= 0 ) return 1 ; for ( ; last != NULL && ! NOTE_INSN_BASIC_BLOCK_P ( last ) && ! stops_p [ INSN_UID ( last ) ] ; last = PREV_INSN ( last ) ) if ( INSN_P ( last ) && recog_memoized ( last ) >= 0 ) return 1 ; return 0 ; } </s>

Returns 1 when a meaningful insn was scheduled between the last group barrier and LAST .


<s> bool ARMTTIImpl :: isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == 32 && ( ! Alignment || Alignment >= 4 ) ) || ( EltWidth == 16 && ( ! Alignment || Alignment >= 2 ) ) || EltWidth == 8 ) ; } </s>

Return true if the target supports masked gather .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips OptimizePICCall"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> DecodeStatus AArch64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { CommentStream = & CS ; Size = 0 ; if ( Bytes . size ( ) < 4 ) return Fail ; Size = 4 ; uint32_t Insn = ( Bytes [ 3 ] << 24 ) | ( Bytes [ 2 ] << 16 ) | ( Bytes [ 1 ] << 8 ) | ( Bytes [ 0 ] << 0 ) ; const uint8_t * Tables [ ] = { DecoderTable32 , DecoderTableFallback32 } ; for ( auto Table : Tables ) { DecodeStatus Result = decodeInstruction ( Table , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; if ( Register :: isPhysicalRegister ( Cond [ 1 ] . getReg ( ) ) ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool X86TTIImpl :: isLegalNTStore ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < 4 || DataSize > 32 || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == 32 ) return ST -> hasAVX ( ) ; else if ( DataSize == 16 ) return ST -> hasSSE1 ( ) ; return true ; } </s>

Return true if the target supports nontemporal store .


<s> bool AArch64PassConfig :: addPreEmitPass ( ) { addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < AArch64Subtarget > ( ) . isTargetMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void AArch64WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; EmitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


More limited version of SimplifyDemandedBits that can be used to `` look through '' ops that do n't contribute to the DemandedBits/DemandedElts - bitwise ops etc .


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn ) { ArgIsFixed . clear ( ) ; for ( unsigned i = 0 ; i < Ins . size ( ) ; ++ i ) ArgIsFixed . push_back ( true ) ; ArgIsShortVector . clear ( ) ; for ( unsigned i = 0 ; i < Ins . size ( ) ; ++ i ) ArgIsShortVector . push_back ( IsShortVectorType ( Ins [ i ] . ArgVT ) ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .


<s> static void constant_fp_to_128bit_vector ( rtx op , machine_mode mode , size_t byte_num , vec_const_128bit_type * info ) { unsigned bitsize = GET_MODE_BITSIZE ( mode ) ; unsigned num_words = bitsize / 32 ; const REAL_VALUE_TYPE * rtype = CONST_DOUBLE_REAL_VALUE ( op ) ; long real_words [ VECTOR_128BIT_WORDS ] ; gcc_assert ( num_words <= VECTOR_128BIT_WORDS && ( bitsize % 32 ) == 0 ) ; real_to_target ( real_words , rtype , mode ) ; for ( unsigned num = 0 ; num < num_words ; num ++ ) { unsigned endian_num = ( BYTES_BIG_ENDIAN ? num : num_words - 1 - num ) ; unsigned uvalue = real_words [ endian_num ] ; for ( int shift = 32 - 8 ; shift >= 0 ; shift -= 8 ) info -> bytes [ byte_num ++ ] = ( uvalue >> shift ) & 0xff ; } info -> fp_constant_p = true ; } </s>

Copy a floating point constant to the vector constant structure .


<s> static Mfix * create_fix_barrier ( Mfix * fix , HOST_WIDE_INT max_address ) { HOST_WIDE_INT count = 0 ; rtx_barrier * barrier ; rtx_insn * from = fix -> insn ; rtx_insn * selected = NULL ; int selected_cost ; HOST_WIDE_INT selected_address ; Mfix * new_fix ; HOST_WIDE_INT max_count = max_address - fix -> address ; rtx_code_label * label = gen_label_rtx ( ) ; selected_cost = arm_barrier_cost ( from ) ; selected_address = fix -> address ; while ( from && count < max_count ) { rtx_jump_table_data * tmp ; int new_cost ; gcc_assert ( ! BARRIER_P ( from ) ) ; if ( LABEL_P ( from ) ) count += get_label_padding ( from ) ; else count += get_attr_length ( from ) ; if ( tablejump_p ( from , NULL , & tmp ) ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } gcc_assert ( selected ) ; from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ; fix -> next = new_fix ; return new_fix ; } </s>

Find the best place in the insn stream in the range ( FIX- > address , MAX_ADDRESS ) to forcibly insert a minipool barrier . Create the barrier by inserting a jump and add a new fix entry for it .


<s> static bool aarch64_modifies_global_state_p ( aarch64_simd_builtin_datum * d ) { unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & FLAG_PREFETCH_MEMORY ) return true ; return flags & FLAG_WRITE_MEMORY ; } </s>

Return true if calls to the function could modify some form of global state .


<s> static bool rs6000_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { return rs6000_mode_dependent_address_ptr ( addr ) ; } </s>


<s> void emitThumbFunc ( MCSymbol * Func ) override { getAssembler ( ) . setIsThumbFunc ( Func ) ; emitSymbolAttribute ( Func , MCSA_ELF_TypeFunction ) ; } </s>

Note in the output that the specified Func is a Thumb mode function ( ARM target only ) .


<s> void AnalyzeCallResult ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn , const TargetLowering :: CallLoweringInfo & CLI ) { PreAnalyzeCallResultForF128 ( Ins , CLI ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeCallResult - Same as above except it 's specialized for calls which produce a single value .


<s> static bool loongarch_valid_pointer_mode ( scalar_int_mode mode ) { return mode == SImode || ( TARGET_64BIT && mode == DImode ) ; } </s>


<s>
void
X86AsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
bool
Is16BitMode
=
STI
.
getFeatureBits
(
)
[
X86
::
Is16Bit
]
;
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
,
Is16BitMode
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Inst
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Mips :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveX86CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } setMachineOutliner ( true ) ; initAsmInfo ( ) ; } </s>


<s> bool ARMTargetLowering :: useLoadStackGuardNode ( ) const { return Subtarget -> getTargetTriple ( ) . getObjectFormat ( ) == Triple :: MachO ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> bool convertSelectOfConstantsToMath ( ) const override { return true ; } </s>

Return true if a select of constants ( select Cond , C1 , C2 ) should be transformed into simple math ops with the condition value .


<s> static char * detect_caches_freebsd ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; size_t len = 4 ; sysctlbyname ( "machdep.cacheline_size" , & l1_line , & len , NULL , 0 ) ; l1_sizekb = 32 ; l1_assoc = 0 ; l2_sizekb = 512 ; return describe_cache ( l1_sizekb , l1_line , l1_assoc , l2_sizekb ) ; } </s>

Returns the description of caches on FreeBSD PPC .


<s> void aarch64_split_simd_move ( rtx dst , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { gcc_assert ( VECTOR_MODE_P ( src_mode ) ) ; emit_insn ( gen_aarch64_split_simd_mov ( src_mode , dst , src ) ) ; } } </s>


<s>
const
char
*
nds32_output_stack_push
(
rtx
par_rtx
)
{
char
pattern
[
100
]
;
rtx
operands
[
3
]
;
int
rb_va_args
=
cfun
->
machine
->
va_args_first_regno
;
int
re_va_args
=
cfun
->
machine
->
va_args_last_regno
;
int
last_argument_regno
=
NDS32_FIRST_GPR_REGNUM
+
NDS32_MAX_GPR_REGS_FOR_ARGS
1
;
int
rb_callee_saved
=
cfun
->
machine
->
callee_saved_first_gpr_regno
;
int
re_callee_saved
=
cfun
->
machine
->
callee_saved_last_gpr_regno
;
if
(
reg_mentioned_p
(
gen_rtx_REG
(
SImode
,
last_argument_regno
)
,
par_rtx
)
)
{
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_va_args
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_va_args
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"push.s\t%s"
,
"%0, %1, { }"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
if
(
TARGET_V3PUSH
&&
!
nds32_isr_function_p
(
current_function_decl
)
&&
(
cfun
->
machine
->
va_args_size
==
0
)
)
{
int
sp_adjust
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
sp_adjust
=
cfun
->
machine
->
local_size
+
cfun
->
machine
->
out_args_size
+
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
;
if
(
satisfies_constraint_Iu08
(
GEN_INT
(
sp_adjust
)
)
&&
NDS32_DOUBLE_WORD_ALIGN_P
(
sp_adjust
)
)
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
else
operands
[
1
]
=
GEN_INT
(
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"push25\t%%0, %%1"
)
;
}
else
{
int
push_en4_only_p
=
0
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_callee_saved
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
if
(
!
cfun
->
machine
->
fp_size
&&
!
cfun
->
machine
->
gp_size
&&
!
cfun
->
machine
->
lp_size
&&
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
{
return
""
;
}
else
{
if
(
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
push_en4_only_p
=
1
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"push.s\t%s{%s%s%s }"
,
push_en4_only_p
""
:
"%0, %1, "
,
cfun
->
machine
->
fp_size
" $fp"
:
""
,
cfun
->
machine
->
gp_size
" $gp"
:
""
,
cfun
->
machine
->
lp_size
" $lp"
:
""
)
;
}
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Function to output stack push operation . We need to deal with normal stack push multiple or stack v3push .


"\tARM::shouldCoalesce - Coalesced Weight: "


<s> static machine_mode select_block_compare_mode ( unsigned HOST_WIDE_INT offset , unsigned HOST_WIDE_INT bytes , unsigned HOST_WIDE_INT align , bool word_mode_ok ) { unsigned HOST_WIDE_INT maxread = ROUND_UP ( bytes , align ) ; if ( word_mode_ok && bytes >= UNITS_PER_WORD ) return word_mode ; else if ( bytes == GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes == GET_MODE_SIZE ( HImode ) ) return HImode ; else if ( bytes == GET_MODE_SIZE ( QImode ) ) return QImode ; else if ( bytes < GET_MODE_SIZE ( SImode ) && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( HImode ) ) return HImode ; return QImode ; } </s>

Select the mode to be used for reading the next chunk of bytes in the compare . OFFSET is the current read offset from the beginning of the block . BYTES is the number of bytes remaining to be read . ALIGN is the minimum alignment of the memory blocks being compared in bytes .


<s> static bool r10k_safe_mem_expr_p ( tree expr , unsigned HOST_WIDE_INT offset ) { HOST_WIDE_INT bitoffset , bitsize ; tree inner , var_offset ; machine_mode mode ; int unsigned_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & volatile_p , false ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi ( DECL_SIZE_UNIT ( inner ) ) ; } </s>

Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is an in-range access to an automatic variable , or to an object with a link-time-constant address .


<s> bool NEONPreAllocPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= PreAllocNEONRegisters ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
getMipsRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
{
if
(
MI
.
getOpcode
(
)
==
Mips
::
ULW
||
MI
.
getOpcode
(
)
==
Mips
::
USW
||
MI
.
getOpcode
(
)
==
Mips
::
ULH
||
MI
.
getOpcode
(
)
==
Mips
::
ULHu
)
emitGlobalAddressUnaligned
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
4
)
;
else
if
(
MI
.
getOpcode
(
)
==
Mips
::
USH
)
emitGlobalAddressUnaligned
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
8
)
;
else
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
Mips
Mips::ULW
Mips::USW
Mips::ULH
Mips::ULHu
4
Mips::USH
8
"Unable to encode MachineOperand!"
0


<s> bool mips_hard_regno_scratch_ok ( unsigned int regno ) { if ( cfun -> machine -> interrupt_handler_p && ! df_regs_ever_live_p ( regno ) ) return false ; return true ; } </s>

Return nonzero if register REGNO can be used as a scratch register in peephole2 .


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( scalar_int_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( mask ) > 0 && UINTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( UINTVAL ( mask ) >> UINTVAL ( shft_amnt ) ) + 1 ) >= 0 && ( UINTVAL ( mask ) & ( ( HOST_WIDE_INT_1U << UINTVAL ( shft_amnt ) ) - 1 ) ) == 0 ; } </s>

Return true if the mask and a shift amount from an RTX of the form ( x < < SHFT_AMNT ) & MASK are valid to combine into a UBFIZ instruction of mode MODE . See the * andim_ashift < mode > _bfiz pattern .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) ) { return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static void csky_initialize_isa ( sbitmap isa , const enum csky_isa_feature * isa_bits ) { bitmap_clear ( isa ) ; while ( * isa_bits != CSKY_ISA_FEATURE_GET ( none ) ) bitmap_set_bit ( isa , * ( isa_bits ++ ) ) ; } </s>

Convert a static initializer array of feature bits to sbitmap representation .


<s> const TargetRegisterClass * X86RegisterInfo :: getGPRsForTailCall ( const MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsWin64 || ( F && F -> getCallingConv ( ) == CallingConv :: X86_64_Win64 ) ) return & X86 :: GR64_TCW64RegClass ; else if ( Is64Bit ) return & X86 :: GR64_TCRegClass ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & X86 :: GR32RegClass ; return & X86 :: GR32_TCRegClass ; } </s>

getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls .


<s> bool PPCTTIImpl :: useColdCCForColdCall ( Function & F ) { return EnablePPCColdCC ; } </s>

Return true if the input function which is cold at all call sites , should use coldcc calling convention .


<s> DecodeStatus ARMDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { if ( STI . getFeatureBits ( ) [ ARM :: ModeThumb ] ) return getThumbInstruction ( MI , Size , Bytes , Address , CS ) ; return getARMInstruction ( MI , Size , Bytes , Address , CS ) ; } </s>

Returns the disassembly of a single instruction .