<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Mips ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static int csky_arg_partial_bytes ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int param_size = csky_num_arg_regs ( arg . mode , arg . type , pcum -> is_stdarg ) ; int reg = pcum -> reg ; if ( FUNCTION_VARG_MODE_P ( arg . mode ) && ! pcum -> is_stdarg ) return 0 ; if ( reg < CSKY_NPARM_REGS && reg + param_size > CSKY_NPARM_REGS ) return ( CSKY_NPARM_REGS - reg ) * UNITS_PER_WORD ; return 0 ; } </s>

Implement TARGET_ARG_PARTIAL_BYTES . Return the number of bytes at the beginning of an argument that must be put in registers . The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack .


<s> bool AArch64InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: SUBSWrr : case AArch64 :: SUBSWrs : case AArch64 :: SUBSWrx : case AArch64 :: SUBSXrr : case AArch64 :: SUBSXrs : case AArch64 :: SUBSXrx : case AArch64 :: ADDSWrr : case AArch64 :: ADDSWrs : case AArch64 :: ADDSWrx : case AArch64 :: ADDSXrr : case AArch64 :: ADDSXrs : case AArch64 :: ADDSXrx : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWri : case AArch64 :: ADDSWri : case AArch64 :: SUBSXri : case AArch64 :: ADDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) ; return true ; case AArch64 :: ANDSWri : case AArch64 :: ANDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ( AArch64_AM :: decodeLogicalImmediate ( MI -> getOperand ( 2 ) . getImm ( ) , MI -> getOpcode ( ) == AArch64 :: ANDSWri ? 32 : 64 ) != 0 ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0 , op1 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 OP1 ) ) .


<s> static inline tree def_builtin_const ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin ( mask , mask2 , name , tcode , code ) ; if ( decl ) TREE_READONLY ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . const_p = true ; return decl ; } </s>

Likewise , but also marks the function as `` const '' .


<s>
void
machopic_output_stub
(
FILE
*
file
,
const
char
*
symb
,
const
char
*
stub
)
{
unsigned
int
length
;
char
*
binder_name
,
*
symbol_name
,
lazy_ptr_name
[
32
]
;
int
label
=
++
current_machopic_label_num
;
symb
=
(
*
targetm
.
strip_name_encoding
)
(
symb
)
;
length
=
strlen
(
stub
)
;
binder_name
=
alloca
(
length
+
32
)
;
GEN_BINDER_NAME_FOR_STUB
(
binder_name
,
stub
,
length
)
;
length
=
strlen
(
symb
)
;
symbol_name
=
alloca
(
length
+
32
)
;
GEN_SYMBOL_NAME_FOR_SYMBOL
(
symbol_name
,
symb
,
length
)
;
sprintf
(
lazy_ptr_name
,
"L%d$lz"
,
label
)
;
if
(
MACHOPIC_PURE
)
machopic_picsymbol_stub_section
(
)
;
else
machopic_symbol_stub_section
(
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
if
(
MACHOPIC_PURE
)
{
fprintf
(
file
,
"\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n"
,
label
,
label
)
;
fprintf
(
file
,
"\tmovl %s-LPC$%d(%%eax),%%edx\n"
,
lazy_ptr_name
,
label
)
;
fprintf
(
file
,
"\tjmp %%edx\n"
)
;
}
else
fprintf
(
file
,
"\tjmp *%s\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"%s:\n"
,
binder_name
)
;
if
(
MACHOPIC_PURE
)
{
fprintf
(
file
,
"\tlea %s-LPC$%d(%%eax),%%eax\n"
,
lazy_ptr_name
,
label
)
;
fprintf
(
file
,
"\tpushl %%eax\n"
)
;
}
else
fprintf
(
file
,
"\t pushl $%s\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\tjmp dyld_stub_binding_helper\n"
)
;
machopic_lazy_symbol_ptr_section
(
)
;
fprintf
(
file
,
"%s:\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"\t.long %s\n"
,
binder_name
)
;
}
</s>

Generate external symbol indirection stubs ( PIC and non-PIC ) .

i386
32
32
32
"L%d$lz"
"%s:\n"
"\t.indirect_symbol %s\n"
"\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n"
"\tmovl %s-LPC$%d(%%eax),%%edx\n"
"\tjmp %%edx\n"
"\tjmp *%s\n"
"%s:\n"
"\tlea %s-LPC$%d(%%eax),%%eax\n"
"\tpushl %%eax\n"
"\t pushl $%s\n"
"\tjmp dyld_stub_binding_helper\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"\t.long %s\n"


<s> OperandMatchResultTy SystemZAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { bool Result = ParseRegister ( RegNo , StartLoc , EndLoc , true ) ; bool PendingErrors = getParser ( ) . hasPendingError ( ) ; getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> static tree rs6000_fold_builtin ( tree fndecl , int n_args ATTRIBUTE_UNUSED , tree * args , bool ignore ATTRIBUTE_UNUSED ) { if ( DECL_BUILT_IN_CLASS ( fndecl ) == BUILT_IN_MD ) { enum rs6000_builtins fn_code = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; switch ( fn_code ) { case RS6000_BUILTIN_NANQ : case RS6000_BUILTIN_NANSQ : { tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; const char * str = c_getstr ( * args ) ; int quiet = fn_code == RS6000_BUILTIN_NANQ ; REAL_VALUE_TYPE real ; if ( str && real_nan ( & real , str , quiet , TYPE_MODE ( type ) ) ) return build_real ( type , real ) ; return NULL_TREE ; } case RS6000_BUILTIN_INFQ : case RS6000_BUILTIN_HUGE_VALQ : { tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; REAL_VALUE_TYPE inf ; real_inf ( & inf ) ; return build_real ( type , inf ) ; } default : break ; } } return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE ; } </s>

Target hook for early folding of built-ins , shamelessly stolen from ia64.cc .


<s> bool ProtectJTSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! Func . protectJT ( ) ) return false ; bool modified = false ; for ( MachineFunction :: iterator MBB = Func . begin ( ) ; MBB != Func . end ( ) ; MBB ++ ) { MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; while ( MI != MBB -> end ( ) ) { MachineBasicBlock :: iterator NMI = std :: next ( MI ) ; modified |= handleInst ( * MBB , MI ) ; MI = NMI ; } } return modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64BitTarget , bool Is64BitStackPtr , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( Is64BitStackPtr ) ; else Opc = isSub ? getSUBriOpcode ( Is64BitStackPtr , Offset ) : getADDriOpcode ( Is64BitStackPtr , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64BitTarget ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64BitTarget ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = isSub ? ( Is64BitTarget ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64BitTarget ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = nullptr ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> void PPCInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , 4 > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = 0 , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDframe : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) . add ( condCodeOp ( ) ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDframe ARM::t2ADDri 0 ARMCC::AL


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"fixupNeedsRelaxation() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static bool ix86_vector_mode_supported_p ( machine_mode mode ) { if ( ! TARGET_64BIT && GET_MODE_INNER ( mode ) == TImode ) return false ; if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) return true ; if ( ( TARGET_MMX || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE ( mode ) ) return true ; if ( ( TARGET_3DNOW || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE_3DNOW ( mode ) ) return true ; if ( mode == V2QImode ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> static bool ia64_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x , bool strict ) { if ( ia64_legitimate_address_reg ( x , strict ) ) return true ; else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC ) && ia64_legitimate_address_reg ( XEXP ( x , 0 ) , strict ) && XEXP ( x , 0 ) != arg_pointer_rtx ) return true ; else if ( GET_CODE ( x ) == POST_MODIFY && ia64_legitimate_address_reg ( XEXP ( x , 0 ) , strict ) && XEXP ( x , 0 ) != arg_pointer_rtx && ia64_legitimate_address_disp ( XEXP ( x , 0 ) , XEXP ( x , 1 ) , strict ) ) return true ; else return false ; } </s>


<s> const char * getPassName ( ) const override { return TLSCLEANUP_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: ERet : expandERet ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool PPCPassConfig :: addInstSelector ( ) { addPass ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"

"After expanding ARM pseudo instructions."


"instructions, but the target does not support ARM mode execution."

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> poly_uint64 aarch64_regmode_natural_size ( machine_mode mode ) { if ( ! aarch64_sve_vg . is_constant ( ) ) { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return BYTES_PER_SVE_PRED ; if ( vec_flags & VEC_SVE_DATA ) return BYTES_PER_SVE_VECTOR ; } return UNITS_PER_WORD ; } </s>


<s> static void ix86_store_bounds ( rtx ptr , rtx slot , rtx bounds , rtx slot_no ) { rtx addr ; addr = ix86_get_arg_address_for_bt ( slot , slot_no , stack_pointer_rtx ) ; if ( ! ptr ) { gcc_assert ( MEM_P ( slot ) ) ; ptr = copy_addr_to_reg ( slot ) ; } gcc_assert ( POINTER_BOUNDS_MODE_P ( GET_MODE ( bounds ) ) ) ; if ( ! register_operand ( bounds , BNDmode ) ) bounds = copy_to_mode_reg ( BNDmode , bounds ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_stx ( addr , ptr , bounds ) : gen_bnd32_stx ( addr , ptr , bounds ) ) ; } </s>

Expand pass uses this hook to store BOUNDS for call argument PTR passed in SLOT in case BOUNDS are not passed in a register . If SLOT is a memory , then BOUNDS are stored as for regular pointer stored in memory . PTR may be NULL in case SLOT is a memory . In such case value of PTR ( if required ) may be loaded from SLOT . If SLOT is NULL or a register then SLOT_NO is an integer constant holding number of the target dependent special slot which should be used to store BOUNDS .


<s> static void sparc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno , padding ; function_arg_slotno ( cum , mode , type , named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ; else { if ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) { const int size = int_size_in_bytes ( type ) ; if ( size <= 0 ) cum -> words ++ ; else cum -> words += CEIL_NWORDS ( size ) ; } else cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ; } } </s>

Handle the TARGET_FUNCTION_ARG_ADVANCE hook . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> static void ia64_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS next_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) ia64_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine -> n_varargs = n ; } } </s>

Do any needed setup for a variadic function . CUM has not been updated for the last named argument which has type TYPE and mode MODE . We generate the actual spill instructions during prologue generation .


<s> static bool arm_sets_movw_movt_fusible_p ( rtx prev_set , rtx curr_set ) { rtx set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , 0 ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , 0 ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; return false ; } </s>

Return true if the two back-to-back sets PREV_SET , CURR_SET are suitable for MOVW / MOVT macro fusion .


<s> rtx legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ) { rtx orig_x = x ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 1 ) , force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , force_operand ( XEXP ( x , 1 ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , force_operand ( XEXP ( x , 0 ) , NULL_RTX ) , XEXP ( x , 1 ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , force_operand ( XEXP ( x , 1 ) , NULL_RTX ) ) ; if ( x != orig_x && legitimate_address_p ( mode , x , FALSE ) ) return x ; if ( SPARC_SYMBOL_REF_TLS_P ( x ) ) x = legitimize_tls_address ( x ) ; else if ( flag_pic ) x = legitimize_pic_address ( x , mode , 0 ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 1 ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , copy_to_mode_reg ( Pmode , XEXP ( x , 1 ) ) ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 0 ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 1 ) , copy_to_mode_reg ( Pmode , XEXP ( x , 0 ) ) ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) x = copy_to_suggested_reg ( x , NULL_RTX , Pmode ) ; return x ; } </s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { EVT VT = getValueType ( DL , Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb1Only ( ) ) return isLegalT1ScaledAddressingMode ( AM , VT ) ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( Scale == 1 || ( AM . HasBaseReg && Scale == - 1 ) ) return true ; if ( ! AM . HasBaseReg && Scale == 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static std :: string readline ( FILE * f ) { char * buf = NULL ; int size = 0 ; int last = 0 ; const int buf_size = 128 ; if ( feof ( f ) ) return std :: string ( ) ; do { size += buf_size ; buf = ( char * ) xrealloc ( buf , size ) ; gcc_assert ( buf ) ; if ( ! fgets ( buf + last , buf_size , f ) ) return std :: string ( ) ; last = strnlen ( buf , size ) - 1 ; } while ( ! feof ( f ) && buf [ last ] != '\n' ) ; std :: string result ( buf ) ; free ( buf ) ; return result ; } </s>

Read an entire line from F until '\n ' or EOF .


<s>
const
TargetRegisterClass
*
MipsRegisterInfo
::
getPointerRegClass
(
const
MachineFunction
&
MF
,
unsigned
Kind
)
const
{
MipsABIInfo
ABI
=
MF
.
getSubtarget
<
MipsSubtarget
>
(
)
.
getABI
(
)
;
MipsPtrClass
PtrClassKind
=
static_cast
<
MipsPtrClass
>
(
Kind
)
;
switch
(
PtrClassKind
)
{
case
MipsPtrClass
::
Default
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GPR64RegClass
:
&
Mips
::
GPR32RegClass
;
case
MipsPtrClass
::
GPR16MM
:
return
&
Mips
::
GPRMM16RegClass
;
case
MipsPtrClass
::
StackPointer
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
SP64RegClass
:
&
Mips
::
SP32RegClass
;
case
MipsPtrClass
::
GlobalPointer
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GP64RegClass
:
&
Mips
::
GP32RegClass
;
}
llvm_unreachable
(
"Unknown pointer kind"
)
;
}
</s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> unsigned X86AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: EVEX ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX || ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: VEX ) return Match_Unsupported ; if ( MCID . TSFlags & X86II :: ExplicitVEXPrefix && ( ForcedVEXEncoding != VEXEncoding_VEX && ForcedVEXEncoding != VEXEncoding_VEX2 && ForcedVEXEncoding != VEXEncoding_VEX3 ) ) return Match_Unsupported ; return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86FixupSFB ( ) ) ; } addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> Register AArch64RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const AArch64InstrInfo * TII = MF . getSubtarget < AArch64Subtarget > ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( AArch64 :: ADDXri ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register BaseReg = MRI . createVirtualRegister ( & AArch64 :: GPR64spRegClass ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , 0 , this , MF ) ) ; unsigned Shifter = AArch64_AM :: getShifterImm ( AArch64_AM :: LSL , 0 ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; return BaseReg ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s>
int
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
IgnoreSPUpdates
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
MFI
.
getObjectOffset
(
FI
)
;
}
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> AArch64TargetLowering :: ConstraintType AArch64TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'z' : return C_Other ; case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const MCExpr * PPCAIXAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const Function * F = dyn_cast < Function > ( CV ) ) { MCSymbolXCOFF * FSym = cast < MCSymbolXCOFF > ( getSymbol ( F ) ) ; if ( ! FSym -> hasContainingCsect ( ) ) { const XCOFF :: StorageClass SC = F -> isDeclaration ( ) ? TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( F ) : XCOFF :: C_HIDEXT ; MCSectionXCOFF * Csect = OutStreamer -> getContext ( ) . getXCOFFSection ( FSym -> getName ( ) , XCOFF :: XMC_DS , F -> isDeclaration ( ) ? XCOFF :: XTY_ER : XCOFF :: XTY_SD , SC , SectionKind :: getData ( ) ) ; FSym -> setContainingCsect ( Csect ) ; } return MCSymbolRefExpr :: create ( FSym -> getContainingCsect ( ) -> getQualNameSymbol ( ) , OutContext ) ; } return PPCAsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s>
void
SystemZPostRASchedStrategy
::
schedNode
(
SUnit
*
SU
,
bool
IsTopNode
)
{
DEBUG
(
dbgs
(
)
<<
"** Scheduling SU("
<<
SU
->
NodeNum
<<
") "
;
if
(
Available
.
size
(
)
==
1
)
dbgs
(
)
<<
"(only one) "
;
Candidate
c
(
SU
,
*
HazardRec
)
;
c
.
dumpCosts
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
Available
.
erase
(
SU
)
;
HazardRec
->
EmitInstruction
(
SU
)
;
}
</s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .

SystemZ
SystemZ
"** Scheduling SU("
") "
1
"(only one) "
"\n"


<s> static unsigned int aarch64_estimated_sve_vq ( ) { return estimated_poly_value ( BITS_PER_SVE_VECTOR ) / 128 ; } </s>

Return an estimate for the number of quadwords in an SVE vector . This is equivalent to the number of Advanced SIMD vectors in an SVE vector .


Implemenation of targetm.vectorize.get_mask_mode .


<s>
bool
AArch64TargetLowering
::
SimplifyDemandedBitsForTargetNode
(
SDValue
Op
,
const
APInt
&
OriginalDemandedBits
,
const
APInt
&
OriginalDemandedElts
,
KnownBits
&
Known
,
TargetLoweringOpt
&
TLO
,
unsigned
Depth
)
const
{
unsigned
Opc
=
Op
.
getOpcode
(
)
;
switch
(
Opc
)
{
case
AArch64ISD
::
VSHL
:
{
SDValue
ShiftL
=
Op
;
SDValue
ShiftR
=
Op
->
getOperand
(
0
)
;
if
(
ShiftR
->
getOpcode
(
)
!=
AArch64ISD
::
VLSHR
)
return
false
;
if
(
!
ShiftL
.
hasOneUse
(
)
||
!
ShiftR
.
hasOneUse
(
)
)
return
false
;
unsigned
ShiftLBits
=
ShiftL
->
getConstantOperandVal
(
1
)
;
unsigned
ShiftRBits
=
ShiftR
->
getConstantOperandVal
(
1
)
;
if
(
ShiftRBits
!=
ShiftLBits
)
return
false
;
unsigned
ScalarSize
=
Op
.
getScalarValueSizeInBits
(
)
;
assert
(
ScalarSize
>
ShiftLBits
&&
"Invalid shift imm"
)
;
APInt
ZeroBits
=
APInt
::
getLowBitsSet
(
ScalarSize
,
ShiftLBits
)
;
APInt
UnusedBits
=
~
OriginalDemandedBits
;
if
(
(
ZeroBits
&
UnusedBits
)
!=
ZeroBits
)
return
false
;
return
TLO
.
CombineTo
(
Op
,
ShiftR
->
getOperand
(
0
)
)
;
}
}
return
TargetLowering
::
SimplifyDemandedBitsForTargetNode
(
Op
,
OriginalDemandedBits
,
OriginalDemandedElts
,
Known
,
TLO
,
Depth
)
;
}
</s>

Attempt to simplify any target nodes based on the demanded bits/elts , returning true on success .


<s> static bool isEqual ( const SlotWithTag & A , const SlotWithTag & B ) { return A == B ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> static bool isShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = CountPopulation_64 ( I ) ; Pos = countTrailingZeros ( I ) ; return true ; } </s>

Return true if this APInt value contains a non-empty sequence of ones with the remainder zero .


<s> int xstormy16_initial_elimination_offset ( int from , int to ) { struct xstormy16_stack_layout layout ; int result ; layout = xstormy16_compute_stack_layout ( ) ; if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = layout . sp_minus_fp - layout . locals_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - layout . locals_size ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = - layout . fp_minus_ap ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - ( layout . sp_minus_fp + layout . fp_minus_ap ) ; else gcc_unreachable ( ) ; return result ; } </s>

Determine how all the special registers get eliminated .


<s> bool enableInterleavedAccessVectorization ( ) { return true ; } </s>

Enable matching of interleaved access groups .


<s> MachineInstr * SparcInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned OpNum = Ops [ 0 ] ; bool isFloat = false ; MachineInstr * NewMI = NULL ; switch ( MI -> getOpcode ( ) ) { case SP :: ORrr : if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 1 ) . getReg ( ) == SP :: G0 && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 2 ) . isReg ( ) ) { if ( OpNum == 0 ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: STri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: LDri ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; case SP :: FMOVS : isFloat = true ; case SP :: FMOVD : if ( OpNum == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: STFri : SP :: STDFri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , false , false , isKill ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: LDFri : SP :: LDDFri ) ) . addReg ( DstReg , true , false , false , isDead ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> bool LanaiTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return isGlobalInSmallSectionImpl ( GO , TM ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> bool PPCTargetLowering :: splitValueIntoRegisterParts ( SelectionDAG & DAG , const SDLoc & DL , SDValue Val , SDValue * Parts , unsigned NumParts , MVT PartVT , Optional < CallingConv :: ID > CC ) const { EVT ValVT = Val . getValueType ( ) ; if ( PartVT == MVT :: f64 && ( ValVT == MVT :: i32 || ValVT == MVT :: i16 || ValVT == MVT :: i8 ) ) { Val = DAG . getNode ( ISD :: ZERO_EXTEND , DL , MVT :: i64 , Val ) ; Val = DAG . getNode ( ISD :: BITCAST , DL , MVT :: f64 , Val ) ; Parts [ 0 ] = Val ; return true ; } return false ; } </s>

Target-specific splitting of values into parts that fit a register storing a legal type .


<s> static bool aarch64_empty_mask_is_expensive ( unsigned ) { return false ; } </s>


<s> Relocator :: Result abs ( Relocation & pReloc , AArch64Relocator & pParent ) { ResolveInfo * rsym = pReloc . symInfo ( ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: DWord S = pReloc . symValue ( ) ; Relocation * dyn_rel = pParent . getRelRelMap ( ) . lookUp ( pReloc ) ; bool has_dyn_rel = ( dyn_rel != NULL ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( 0x0 == ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) ) { pReloc . target ( ) = S + A ; return Relocator :: OK ; } if ( rsym -> isLocal ( ) && has_dyn_rel ) { dyn_rel -> setAddend ( S + A ) ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & AArch64Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } if ( has_dyn_rel ) { if ( llvm :: ELF :: R_AARCH64_ABS64 == pReloc . type ( ) && llvm :: ELF :: R_AARCH64_RELATIVE == dyn_rel -> type ( ) ) { dyn_rel -> setAddend ( S + A ) ; } else { dyn_rel -> setAddend ( A ) ; return Relocator :: OK ; } } } pReloc . target ( ) = S + A ; return Relocator :: OK ; } </s>

Compute known bits for the absolute value .


<s> int getExtendResourceLenLimit ( ) const override { return 1 ; } </s>

The limit on resource length extension we accept in MachineCombiner Pass .


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
unsigned
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
unsigned
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> inline const type_suffix_info & function_instance :: type_suffix ( unsigned int i ) const { return type_suffixes [ type_suffix_ids [ i ] ] ; } </s>

Return information about type suffix I .


<s> void ix86_expand_clear ( rtx dest ) { rtx tmp ; gcc_assert ( reload_completed ) ; if ( GET_MODE_SIZE ( GET_MODE ( dest ) ) < 4 ) dest = gen_rtx_REG ( SImode , REGNO ( dest ) ) ; tmp = gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ; if ( ! TARGET_USE_MOV0 || optimize_insn_for_size_p ( ) ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , tmp , clob ) ) ; } emit_insn ( tmp ) ; } </s>

Generate either `` mov $ 0 , reg '' or `` xor reg , reg '' , as appropriate for the target .


<s> bool function_checker :: require_immediate_either_or ( unsigned int rel_argno , HOST_WIDE_INT value0 , HOST_WIDE_INT value1 ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; if ( actual != value0 && actual != value1 ) { report_neither_nor ( location , fndecl , argno , actual , 90 , 270 ) ; return false ; } return true ; } </s>

Check that argument REL_ARGNO is an integer constant expression that has the value VALUE0 or VALUE1 . REL_ARGNO counts from the end of the predication arguments .


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_operation ( pat , VOIDmode ) || vzeroall_operation ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_reg256_found = false ; note_stores ( pat , ix86_check_avx256_stores , & avx_reg256_found ) ; return avx_reg256_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return mode ; } </s>

Calculate mode of upper 128bit AVX registers after the insn .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool Cpu0SEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Cpu0 :: RetLR : expandRetLR ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static rtx mt_check_delay_slot ( rtx branch , rtx insn ) { rtx slot ; rtx tmp ; rtx p ; rtx jmp ; gcc_assert ( GET_CODE ( PATTERN ( branch ) ) == SEQUENCE ) ; if ( INSN_DELETED_P ( branch ) ) return NULL_RTX ; slot = XVECEXP ( PATTERN ( branch ) , 0 , 1 ) ; tmp = PATTERN ( insn ) ; note_stores ( PATTERN ( slot ) , insn_dependent_p_1 , & tmp ) ; if ( tmp ) return NULL_RTX ; jmp = XVECEXP ( PATTERN ( branch ) , 0 , 0 ) ; tmp = PATTERN ( jmp ) ; note_stores ( PATTERN ( slot ) , insn_dependent_p_1 , & tmp ) ; if ( ! tmp ) return branch ; p = PREV_INSN ( branch ) ; NEXT_INSN ( p ) = slot ; PREV_INSN ( slot ) = p ; NEXT_INSN ( slot ) = jmp ; PREV_INSN ( jmp ) = slot ; NEXT_INSN ( jmp ) = branch ; PREV_INSN ( branch ) = jmp ; XVECEXP ( PATTERN ( branch ) , 0 , 0 ) = NULL_RTX ; XVECEXP ( PATTERN ( branch ) , 0 , 1 ) = NULL_RTX ; delete_insn ( branch ) ; return jmp ; } </s>

If BRANCH has a filled delay slot , check if INSN is dependent upon it . If so , undo the delay slot fill . Returns the next insn , if we patch out the branch . Returns the branch insn , if we can not patch out the branch ( due to anti-dependency in the delay slot ) . In that case , the caller must insert nops at the branch target .


"force: group count = %d, can_issue_more = %d\n"

"done force: group count = %d, can_issue_more = %d\n"

Utility of the function redefine_groups . Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS in the same dispatch group . If so , insert nops before NEXT_INSN , in order to keep it `` far '' ( in a separate group ) from GROUP_INSNS , following one of the following schemes , depending on the value of the flag -minsert_sched_nops = X : ( 1 ) X == sched_finish_regroup_exact : insert exactly as many nops as needed in order to force NEXT_INSN into a separate group . ( 2 ) X < sched_finish_regroup_exact : insert exactly X nops . GROUP_END , CAN_ISSUE_MORE and GROUP_COUNT record the state after nop insertion ( has a group just ended , how many vacant issue slots remain in the last group , and how many dispatch groups were encountered so far ) .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; if ( MF . getMMI ( ) . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , SlotSize ) ; X86FI -> setHasSEHFramePtrSave ( true ) ; X86FI -> setSEHFramePtrSaveIndex ( FI ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y ) { enum machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


<s> void MipsRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> unsigned getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { if ( ArgTy -> isVectorTy ( ) ) return std :: min ( DL . getABITypeAlignment ( ArgTy ) , 8U ) ; return DL . getABITypeAlignment ( ArgTy ) ; } </s>

Return the correct alignment for the current calling convention .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s>
MachineBasicBlock
*
CAHPTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
assert
(
MI
.
getOpcode
(
)
==
CAHP
::
Select_GPR_Using_CC_GPR
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
HeadMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
TailMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
IfFalseMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
IfFalseMBB
)
;
F
->
insert
(
I
,
TailMBB
)
;
TailMBB
->
splice
(
TailMBB
->
begin
(
)
,
HeadMBB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
HeadMBB
->
end
(
)
)
;
TailMBB
->
transferSuccessorsAndUpdatePHIs
(
HeadMBB
)
;
HeadMBB
->
addSuccessor
(
IfFalseMBB
)
;
HeadMBB
->
addSuccessor
(
TailMBB
)
;
unsigned
LHS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
unsigned
RHS
=
MI
.
getOperand
(
2
)
.
getReg
(
)
;
auto
CC
=
static_cast
<
ISD
::
CondCode
>
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
unsigned
Opcode
=
getBranchOpcodeForIntCondCode
(
CC
)
;
BuildMI
(
HeadMBB
,
DL
,
TII
.
get
(
Opcode
)
)
.
addReg
(
LHS
)
.
addReg
(
RHS
)
.
addMBB
(
TailMBB
)
;
IfFalseMBB
->
addSuccessor
(
TailMBB
)
;
BuildMI
(
*
TailMBB
,
TailMBB
->
begin
(
)
,
DL
,
TII
.
get
(
CAHP
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
4
)
.
getReg
(
)
)
.
addMBB
(
HeadMBB
)
.
addReg
(
MI
.
getOperand
(
5
)
.
getReg
(
)
)
.
addMBB
(
IfFalseMBB
)
;
MI
.
eraseFromParent
(
)
;
return
TailMBB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
markSuperRegs
(
Reserved
,
ARM
::
ZR
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> int neon_struct_mem_operand ( rtx op ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( LABEL_REF_P ( ind ) || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; return FALSE ; } </s>

Return TRUE if OP is a mem suitable for loading/storing a Neon struct type .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool MipsSETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { MVT :: SimpleValueType SVT = VT . getSimpleVT ( ) . SimpleTy ; if ( Subtarget . systemSupportsUnalignedAccess ( ) ) { if ( Fast ) * Fast = true ; return true ; } switch ( SVT ) { case MVT :: i64 : case MVT :: i32 : if ( Fast ) * Fast = true ; return true ; default : return false ; } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


"emitEpilogue doesn't support framepointer-less functions"


"Unrecognised AArch64 memory constraint"

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void xstormy16_emit_cbranch ( enum rtx_code code , rtx loc ) { rtx op0 = xstormy16_compare_op0 ; rtx op1 = xstormy16_compare_op1 ; rtx condition_rtx , loc_ref , branch , cy_clobber ; rtvec vec ; enum machine_mode mode ; mode = GET_MODE ( op0 ) ; gcc_assert ( mode == HImode || mode == SImode ) ; if ( mode == SImode && ( code == GT || code == LE || code == GTU || code == LEU ) ) { int unsigned_p = ( code == GTU || code == LEU ) ; int gt_p = ( code == GT || code == GTU ) ; rtx lab = NULL_RTX ; if ( gt_p ) lab = gen_label_rtx ( ) ; xstormy16_emit_cbranch ( unsigned_p ? LTU : LT , gt_p ? lab : loc ) ; xstormy16_emit_cbranch ( gt_p ? NE : EQ , loc ) ; if ( gt_p ) emit_label ( lab ) ; return ; } else if ( mode == SImode && ( code == NE || code == EQ ) && op1 != const0_rtx ) { rtx lab = NULL_RTX ; int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; if ( code == EQ ) lab = gen_label_rtx ( ) ; for ( i = 0 ; i < num_words - 1 ; i ++ ) { xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( NE , code == EQ ? lab : loc ) ; } xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( code , loc ) ; if ( code == EQ ) emit_label ( lab ) ; return ; } if ( mode != HImode ) { rtx tmp ; tmp = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp , op0 ) ; op0 = tmp ; } condition_rtx = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , loc ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ; cy_clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( BImode ) ) ; if ( mode == HImode ) vec = gen_rtvec ( 2 , branch , cy_clobber ) ; else if ( code == NE || code == EQ ) vec = gen_rtvec ( 2 , branch , gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; else { rtx sub ; sub = gen_rtx_SET ( VOIDmode , op0 , gen_rtx_MINUS ( SImode , op0 , op1 ) ) ; sub = gen_rtx_CLOBBER ( SImode , op0 ) ; vec = gen_rtvec ( 3 , branch , sub , cy_clobber ) ; } emit_jump_insn ( gen_rtx_PARALLEL ( VOIDmode , vec ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static HOST_WIDE_INT ix86_static_rtx_alignment ( machine_mode mode ) { if ( mode == DFmode ) return 64 ; if ( ALIGN_MODE_128 ( mode ) ) return MAX ( 128 , GET_MODE_ALIGNMENT ( mode ) ) ; return GET_MODE_ALIGNMENT ( mode ) ; } </s>


<s> bool isProfitableForNoCSROpt ( const Function & F ) const override { return false ; } </s>

Check if the no-CSR optimisation is profitable for the given function .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , GenExecuteOnly ( EnableExecuteOnly ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) , GISel ( ) { } </s>


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) == ARMISD :: VMOVRRD ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , 2 > Copies ; for ( SDNode * U : VMov -> uses ( ) ) { if ( U -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies . insert ( U ) ; } if ( Copies . size ( ) > 2 ) return false ; for ( SDNode * U : VMov -> uses ( ) ) { SDValue UseChain = U -> getOperand ( 0 ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = U ; else { if ( U -> getOperand ( U -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = UseChain ; } } } else if ( Copy -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != ISD :: CopyToReg || ! Copy -> hasNUsesOfValue ( 1 , 0 ) ) return false ; if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else { return false ; } bool HasRet = false ; for ( const SDNode * U : Copy -> uses ( ) ) { if ( U -> getOpcode ( ) != ARMISD :: RET_FLAG && U -> getOpcode ( ) != ARMISD :: INTRET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> static bool is_power9_pairable_vec_type ( enum attr_type type ) { switch ( type ) { case TYPE_VECSIMPLE : case TYPE_VECCOMPLEX : case TYPE_VECDIV : case TYPE_VECCMP : case TYPE_VECPERM : case TYPE_VECFLOAT : case TYPE_VECFDIV : case TYPE_VECDOUBLE : return true ; default : break ; } return false ; } </s>

Return whether TYPE is a Power9 pairable vector instruction type .


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


<s> virtual void dump ( raw_ostream & OS ) const { } </s>

Dump the plan to stderr ( for debugging ) .


"getBranchTargetOpValue expects only expressions"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool isStackIdSafeForLocalArea ( unsigned StackId ) const override { return StackId != TargetStackID :: ScalableVector ; } </s>

This method returns whether or not it is safe for an object with the given stack id to be bundled into the local area .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) || STI . isTargetWatchOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>


<s> bool aarch64_sve_cmp_immediate_p ( rtx x , bool signed_p ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && ( signed_p ? IN_RANGE ( INTVAL ( elt ) , - 16 , 15 ) : IN_RANGE ( INTVAL ( elt ) , 0 , 127 ) ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE CMP instruction . SIGNED_P says whether the operand is signed rather than unsigned .


<s> void TOYFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = TOY :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: SUBrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: SUBri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static int pcrel_constant_p ( rtx x ) { if ( GET_CODE ( x ) == MINUS ) return symbol_mentioned_p ( XEXP ( x , 0 ) ) && label_mentioned_p ( XEXP ( x , 1 ) ) ; return FALSE ; } </s>

Return TRUE if this rtx is the difference of a symbol and a label , and will reduce to a PC-relative relocation in the object file . Expressions like this can be left alone when generating PIC , rather than forced through the GOT .


<s> static bool rs6000_save_toc_in_prologue_p ( void ) { return ( cfun && cfun -> machine && cfun -> machine -> save_toc_in_prologue ) ; } </s>

Return whether we need to always update the saved TOC pointer when we update the stack pointer .


<s>
void
LEGAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
isPCRel
)
const
{
unsigned
NumBytes
=
4
;
Value
=
adjustFixupValue
(
Fixup
,
Value
)
;
if
(
!
Value
)
{
return
;
}
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void mips_expand_vec_reduc ( rtx target , rtx in , rtx ( * gen ) ( rtx , rtx , rtx ) ) { machine_mode vmode = GET_MODE ( in ) ; unsigned char perm2 [ 2 ] ; rtx last , next , fold , x ; bool ok ; last = in ; fold = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case V2SFmode : perm2 [ 0 ] = 1 ; perm2 [ 1 ] = 2 ; ok = mips_expand_vselect_vconcat ( fold , last , last , perm2 , 2 ) ; gcc_assert ( ok ) ; break ; case V2SImode : emit_insn ( gen_loongson_punpckhwd ( fold , last , last ) ) ; break ; case V4HImode : emit_insn ( gen_loongson_punpckhwd_hi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 16 ) ) ; emit_insn ( gen_vec_shr_v4hi ( fold , last , x ) ) ; break ; case V8QImode : emit_insn ( gen_loongson_punpckhwd_qi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 16 ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 8 ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( target , last , fold ) ) ; } </s>


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ; DataSection . setAlignment ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ; BSSSection . setAlignment ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . EmitCodeAlignment ( Alignment , Alignment ) ; else OS . EmitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> bool MipsSERegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void MipsELFStreamer :: EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) { MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = 0 ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } createPendingLabelRelocs ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> rtx function_expander :: use_contiguous_load_insn ( insn_code icode ) { machine_mode mem_mode = memory_vector_mode ( ) ; add_output_operand ( icode ) ; add_mem_operand ( mem_mode , get_contiguous_base ( mem_mode ) ) ; add_input_operand ( icode , args [ 0 ] ) ; if ( GET_MODE_UNIT_BITSIZE ( mem_mode ) < type_suffix ( 0 ) . element_bits ) add_input_operand ( icode , CONSTM1_RTX ( VNx16BImode ) ) ; return generate_insn ( icode ) ; } </s>


<s> static bool use_rsqrt_p ( void ) { return ( ! flag_trapping_math && flag_unsafe_math_optimizations && ( ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_APPROX_RSQRT ) || flag_mrecip_low_precision_sqrt ) ) ; } </s>

Return true if it is safe to use the rsqrt optabs to optimize 1.0/sqrt .


<s> void rs6000_final_prescan_insn ( rtx_insn * insn , rtx [ ] , int ) { prepend_p_to_next_insn = ( get_attr_maybe_prefixed ( insn ) == MAYBE_PREFIXED_YES && get_attr_prefixed ( insn ) == PREFIXED_YES ) ; return ; } </s>

Define FINAL_PRESCAN_INSN if some processing needs to be done before outputting the assembler code . On the PowerPC , we remember if the current insn is a prefixed insn where we need to emit a ' p ' before the insn . In addition , if the insn is part of a PC-relative reference to an external label optimization , this is recorded also .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || ( isWin64Prologue ( MF ) && MFI . hasCopyImplyingStackAdjustment ( ) ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void SystemZTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'J' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'K' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'L' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ) ; return ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> void x86_elf_aligned_decl_common ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) { switch_to_section ( get_named_section ( decl , ".lbss" , 0 ) ) ; fputs ( LARGECOMM_SECTION_ASM_OP , file ) ; } else fputs ( COMMON_ASM_OP , file ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

This says how to output assembler code to declare an uninitialized external linkage data object . For medium model x86-64 we need to use LARGECOMM_SECTION_ASM_OP opcode for large objects .


<s> static unsigned aarch64_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


<s> SDValue PPCTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { EVT VT = N -> getValueType ( 0 ) ; if ( VT == MVT :: i64 && ! Subtarget . isPPC64 ( ) ) return SDValue ( ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; bool IsNegPow2 = ( - Divisor ) . isPowerOf2 ( ) ; unsigned Lg2 = ( IsNegPow2 ? - Divisor : Divisor ) . countTrailingZeros ( ) ; SDValue ShiftAmt = DAG . getConstant ( Lg2 , DL , VT ) ; SDValue Op = DAG . getNode ( PPCISD :: SRA_ADDZE , DL , VT , N0 , ShiftAmt ) ; Created . push_back ( Op . getNode ( ) ) ; if ( IsNegPow2 ) { Op = DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , Op ) ; Created . push_back ( Op . getNode ( ) ) ; } return Op ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> static bool convertible_comparison_p ( rtx_insn * insn , enum machine_mode mode ) { if ( TARGET_64BIT || mode != DImode ) return false ; if ( ! TARGET_SSE4_1 ) return false ; rtx def_set = single_set ( insn ) ; gcc_assert ( def_set ) ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; gcc_assert ( GET_CODE ( src ) == COMPARE ) ; if ( GET_CODE ( dst ) != REG || REGNO ( dst ) != FLAGS_REG || GET_MODE ( dst ) != CCZmode ) return false ; rtx op1 = XEXP ( src , 0 ) ; rtx op2 = XEXP ( src , 1 ) ; if ( op2 != CONST0_RTX ( GET_MODE ( op2 ) ) ) return false ; if ( GET_CODE ( op1 ) != IOR ) return false ; op2 = XEXP ( op1 , 1 ) ; op1 = XEXP ( op1 , 0 ) ; if ( ! SUBREG_P ( op1 ) || ! SUBREG_P ( op2 ) || GET_MODE ( op1 ) != SImode || GET_MODE ( op2 ) != SImode || ( ( SUBREG_BYTE ( op1 ) != 0 || SUBREG_BYTE ( op2 ) != GET_MODE_SIZE ( SImode ) ) && ( SUBREG_BYTE ( op2 ) != 0 || SUBREG_BYTE ( op1 ) != GET_MODE_SIZE ( SImode ) ) ) ) return false ; op1 = SUBREG_REG ( op1 ) ; op2 = SUBREG_REG ( op2 ) ; if ( op1 != op2 || ! REG_P ( op1 ) || GET_MODE ( op1 ) != DImode ) return false ; return true ; } </s>

Check if comparison INSN may be transformed into vector comparison . Currently we transform equality/inequality checks which look like : ( set ( reg : CCZ 17 flags ) ( compare : CCZ ( reg : TI x ) ( reg : TI y ) ) )


runOnMachineFunction - Emit the function body .


<s>
bool
TOYPreEmit
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
dbgs
(
)
<<
"********* TOY PreRmit *********\n"
)
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
Changed
|=
optimizeLoopBranch
(
MF
)
;
Changed
|=
removeFallThroughBranch
(
MF
)
;
Changed
|=
localValueNumbering
(
MF
)
;
return
Changed
;
}
</s>


<s> bool AArch64InstrInfo :: isPairableLdStInst ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: STRXui : case AArch64 :: STRWui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : case AArch64 :: LDRXui : case AArch64 :: LDRWui : case AArch64 :: LDRSWui : case AArch64 :: STURSi : case AArch64 :: STRSpre : case AArch64 :: STURDi : case AArch64 :: STRDpre : case AArch64 :: STURQi : case AArch64 :: STRQpre : case AArch64 :: STURWi : case AArch64 :: STRWpre : case AArch64 :: STURXi : case AArch64 :: STRXpre : case AArch64 :: LDURSi : case AArch64 :: LDRSpre : case AArch64 :: LDURDi : case AArch64 :: LDRDpre : case AArch64 :: LDURQi : case AArch64 :: LDRQpre : case AArch64 :: LDURWi : case AArch64 :: LDRWpre : case AArch64 :: LDURXi : case AArch64 :: LDRXpre : case AArch64 :: LDURSWi : return true ; } } </s>

Return true if pairing the given load or store may be paired with another .


<s> void LanaiAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned , uint64_t Value , bool ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: BUILD_VECTOR : return PerformBuildVectorCombine ( N , DAG , DCI , Subtarget , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> unsigned ARMFastISel :: fastEmitInst_i ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a single immediate operand , and a result register in the given register class .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( ! Subtarget . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) . hasOptSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>


<s> static int rs6000_hard_regno_mode_ok ( int regno , enum machine_mode mode ) { if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( regno + HARD_REGNO_NREGS ( regno , mode ) - 1 ) ; if ( FP_REGNO_P ( regno ) ) return ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && FP_REGNO_P ( regno + HARD_REGNO_NREGS ( regno , mode ) - 1 ) ) || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) ; if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( XER_REGNO_P ( regno ) ) return mode == PSImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ALTIVEC_VECTOR_MODE ( mode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return 1 ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> opt_machine_mode arm_mode_to_pred_mode ( machine_mode mode ) { switch ( GET_MODE_NUNITS ( mode ) ) { case 16 : return V16BImode ; case 8 : return V8BImode ; case 4 : return V4BImode ; case 2 : return V2QImode ; } return opt_machine_mode ( ) ; } </s>

Return the mode for the MVE vector of predicates corresponding to MODE .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= ExpandFPMLxInstructions ( MBB ) ; } return Modified ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'f' : return std :: make_pair ( 0U , & SP :: FPRegsRegClass ) ; case 'r' : if ( VT == MVT :: v2i32 ) return std :: make_pair ( 0U , & SP :: IntPairRegClass ) ; else return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void union_uses ( swap_web_entry * insn_entry , rtx insn , df_ref def ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( use_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing uses reached from DEF . Detect whether DEF is live-out from the current function .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( NumOps == 0 ) return false ; switch ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - 1 ] . OperandType ) { case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_IMMEDIATE : Target = Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; case MCOI :: OPERAND_PCREL : Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; default : return false ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> bool X86InstrInfo :: getConstValDefinedInReg ( const MachineInstr & MI , const Register Reg , int64_t & ImmVal ) const { if ( MI . getOpcode ( ) != X86 :: MOV32ri && MI . getOpcode ( ) != X86 :: MOV64ri ) return false ; if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 0 ) . getReg ( ) != Reg ) return false ; ImmVal = MI . getOperand ( 1 ) . getImm ( ) ; return true ; } </s>

Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; bool Modified = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>


<s>
AsmToken
LexToken
(
)
{
if
(
!
Lexer
)
{
SetError
(
SMLoc
(
)
,
"No MCAsmLexer installed"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
}
switch
(
AsmInfo
.
getAssemblerDialect
(
)
)
{
default
:
SetError
(
SMLoc
(
)
,
"Unhandled dialect"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
case
0
:
return
LexTokenUAL
(
)
;
}
}
</s>

LexToken - Read the next token and return its code .


<s> static tree ix86_build_builtin_va_list ( void ) { if ( TARGET_64BIT ) { tree sysv_va_list , ms_va_list ; sysv_va_list = ix86_build_builtin_va_list_64 ( ) ; sysv_va_list_type_node = build_variant_type_copy ( sysv_va_list ) ; ms_va_list = build_pointer_type ( char_type_node ) ; ms_va_list_type_node = build_variant_type_copy ( ms_va_list ) ; return ( ix86_abi == MS_ABI ) ? ms_va_list : sysv_va_list ; } else { return build_pointer_type ( char_type_node ) ; } } </s>


<s> bool PPCTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , ( Subtarget . isSVR4ABI ( ) && CallConv == CallingConv :: Cold ) ? RetCC_PPC_Cold : RetCC_PPC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) && hasAtomicRMW ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void ARMBankConflictHazardRecognizer :: Reset ( ) { Accesses . clear ( ) ; } </s>


<s> fma_forest :: fma_forest ( func_fma_steering * fma_steer , fma_root_node * fma_root , int id ) { memset ( this , 0 , sizeof ( * this ) ) ; this -> m_globals = fma_steer ; this -> m_roots = new std :: list < fma_root_node * > ; this -> m_roots -> push_back ( fma_root ) ; this -> m_id = id ; } </s>


<s> bool shouldBuildLookupTablesForConstant ( Constant * C ) const { if ( ST -> isROPI ( ) || ST -> isRWPI ( ) || ST -> isPIP ( ) ) return ! C -> needsRelocation ( ) ; return true ; } </s>

Return true if switches should be turned into lookup tables containing this constant value for the target .


<s> void CSKYTargetStreamer :: finish ( ) { if ( ConstantCounter != 0 ) { ConstantPool -> emitAll ( Streamer ) ; } finishAttributeSection ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SP :: G1 ) ; if ( ReserveAppRegisters ) { Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"%qE attribute ignored without %<-mcmse%> "

"%qE attribute only applies to base type of a "

Called upon detection of the use of the cmse_nonsecure_call attribute , this function will check whether the attribute is allowed here and will add the attribute to the function type tree or otherwise issue a diagnostic . The reason we check this at declaration time is to only allow the use of the attribute with declarations of function pointers and not function declarations . This function checks NODE is of the expected type and issues diagnostics otherwise using NAME . If it is not of the expected type * NO_ADD_ATTRS will be set to true .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT , Subtarget -> hasFp256 ( ) ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , VT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , VT , Subtarget ) || isUNPCKLMask ( M , VT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , VT , Subtarget -> hasInt256 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> int X86InstrInfo :: getSPAdjust ( const MachineInstr & MI ) const { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( isFrameInstr ( MI ) ) { unsigned StackAlign = TFI -> getStackAlignment ( ) ; int SPAdj = alignTo ( getFrameSize ( MI ) , StackAlign ) ; SPAdj -= getFrameAdjustment ( MI ) ; if ( ! isFrameSetup ( MI ) ) SPAdj = - SPAdj ; return SPAdj ; } if ( MI . isCall ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return 0 ; return - ( I -> getOperand ( 1 ) . getImm ( ) ) ; } switch ( MI . getOpcode ( ) ) { default : return 0 ; case X86 :: PUSH32i8 : case X86 :: PUSH32r : case X86 :: PUSH32rmm : case X86 :: PUSH32rmr : case X86 :: PUSHi32 : return 4 ; case X86 :: PUSH64i8 : case X86 :: PUSH64r : case X86 :: PUSH64rmm : case X86 :: PUSH64rmr : case X86 :: PUSH64i32 : return 8 ; } } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
SDValue
Cpu0TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Cpu0
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
assert
(
RVLocs
.
size
(
)
<=
1
&&
"Too many values to return!"
)
;
if
(
RVLocs
.
size
(
)
>
0
)
{
CCValAssign
&
VA
=
RVLocs
[
0
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
0
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
->
hasStructRetAttr
(
)
)
{
assert
(
false
&&
"Not yet implemented"
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
RVLocs
.
size
(
)
==
0
Cpu0ISD
::
Ret
:
Cpu0ISD
::
RetValue
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( Triple ( TT ) , is64bit ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s> void LC3FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == LC3 :: ADJCALLSTACKUP || I -> getOpcode ( ) == LC3 :: ADJCALLSTACKDOWN ) { MBB . erase ( I ) ; } return ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s>
void
CSKYAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Kind
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
bool
IsLittleEndian
=
(
Endian
==
support
::
little
)
;
if
(
IsLittleEndian
&&
(
NumBytes
==
4
)
)
{
Data
[
Offset
+
0
]
|=
uint8_t
(
(
Value
>>
16
)
&
0xff
)
;
Data
[
Offset
+
1
]
|=
uint8_t
(
(
Value
>>
24
)
&
0xff
)
;
Data
[
Offset
+
2
]
|=
uint8_t
(
Value
&
0xff
)
;
Data
[
Offset
+
3
]
|=
uint8_t
(
(
Value
>>
8
)
&
0xff
)
;
}
else
{
for
(
unsigned
I
=
0
;
I
!=
NumBytes
;
I
++
)
{
unsigned
Idx
=
IsLittleEndian
I
:
(
NumBytes
1
I
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
I
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; else if ( ! Subtarget . hasMips64 ( ) ) return CSR_O32_RegMask ; else if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; assert ( Subtarget . isABI_N64 ( ) ) ; return CSR_N64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .