<s> static void aarch64_save_callee_saves ( machine_mode mode , poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb ) { rtx_insn * insn ; unsigned regno ; unsigned regno2 ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { rtx reg , mem ; poly_int64 offset ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; regno = regno2 ; } else insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save the callee-saved registers from register number START to LIMIT to the stack at the location starting at offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true .


"Unknown fence ordering in emitLeadingFence"


<s>
virtual
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Assmebly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


<s> static rtx address_offset ( rtx op ) { if ( GET_CODE ( op ) == PRE_INC || GET_CODE ( op ) == PRE_DEC ) op = XEXP ( op , 0 ) ; else if ( GET_CODE ( op ) == PRE_MODIFY || GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == PLUS ) op = XEXP ( op , 1 ) ; if ( CONST_INT_P ( op ) ) return op ; return NULL_RTX ; } </s>

Given an address , return a constant offset term if one exists .


<s> bool X86AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return ! isInt < 8 > ( Value ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool X86TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? 64 : 32 ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> rtx legitimize_pic_address ( rtx orig , enum machine_mode mode ATTRIBUTE_UNUSED , rtx reg ) { if ( GET_CODE ( orig ) == SYMBOL_REF ) { rtx pic_ref , address ; rtx insn ; if ( reg == 0 ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; reg = gen_reg_rtx ( Pmode ) ; } if ( flag_pic == 2 ) { rtx temp_reg = ( ( reload_in_progress || reload_completed ) ? reg : gen_reg_rtx ( Pmode ) ) ; if ( TARGET_ARCH64 ) { emit_insn ( gen_movdi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movdi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } else { emit_insn ( gen_movsi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movsi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } address = temp_reg ; } else address = orig ; pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; current_function_uses_pic_offset_table = 1 ; insn = emit_move_insn ( reg , pic_ref ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_EQUAL , orig , REG_NOTES ( insn ) ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS && XEXP ( XEXP ( orig , 0 ) , 0 ) == pic_offset_table_rtx ) return orig ; if ( reg == 0 ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , Pmode , base == reg ? 0 : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( base , INTVAL ( offset ) ) ; else if ( ! reload_in_progress && ! reload_completed ) offset = force_reg ( Pmode , offset ) ; else gcc_unreachable ( ) ; } return gen_rtx_PLUS ( Pmode , base , offset ) ; } else if ( GET_CODE ( orig ) == LABEL_REF ) current_function_uses_pic_offset_table = 1 ; return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> const X86_64GOT & X86_64GNULDBackend :: getGOT ( ) const { assert ( m_pGOT != NULL ) ; return * m_pGOT ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> void CJGFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> Optional < DestSourcePair > ARMBaseInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == ARM :: VORRq && MI . getOperand ( 1 ) . getReg ( ) != MI . getOperand ( 2 ) . getReg ( ) ) ) return None ; return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> bool aarch64_simd_imm_zero_p ( rtx x , machine_mode mode ) { return x == CONST0_RTX ( mode ) ; } </s>

Return true if X is a uniform vector where all elements are either the floating-point constant 0.0 or the integer constant 0 .


<s> bool Cpu0LongBranch :: runOnMachineFunction ( MachineFunction & F ) { const Cpu0Subtarget & STI = static_cast < const Cpu0Subtarget & > ( F . getSubtarget ( ) ) ; const Cpu0InstrInfo * TII = static_cast < const Cpu0InstrInfo * > ( STI . getInstrInfo ( ) ) ; LongBranchSeqSize = ! IsPIC ? 2 : 10 ; if ( ! STI . enableLongBranchPass ( ) ) return false ; if ( IsPIC && static_cast < const Cpu0TargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < Cpu0MachineFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( IsPIC ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
char
*
emit_fusion_p9_store
(
rtx
mem
,
rtx
reg
,
rtx
tmp_reg
)
{
enum
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
store_string
;
int
r
;
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_store, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
store_string
=
"stfs"
;
else
if
(
mode
==
DFmode
)
store_string
=
"stfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_DFORM_SCALAR
)
{
if
(
mode
==
SFmode
)
store_string
=
"stxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
store_string
=
"stxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
QImode
:
store_string
=
"stb"
;
break
;
case
HImode
:
store_string
=
"sth"
;
break
;
case
SImode
:
case
SFmode
:
store_string
=
"stw"
;
break
;
case
DImode
:
case
DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
store_string
=
"std"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_store, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_store not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 store fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
store_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a store using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
"emit_fusion_p9_store, bad reg #1"
"stfs"
"stfd"
"stxssp"
"stxsd"
"stb"
"sth"
"stw"
"std"
"emit_fusion_p9_store, bad reg #2"
"emit_fusion_p9_store not MEM"
0
"power9 store fusion"
""


<s> static bool unspec_caller_rtx_p ( rtx pat ) { switch ( GET_CODE ( pat ) ) { case CONST : return unspec_caller_rtx_p ( XEXP ( pat , 0 ) ) ; case PLUS : case MINUS : if ( unspec_caller_rtx_p ( XEXP ( pat , 0 ) ) ) return true ; return unspec_caller_rtx_p ( XEXP ( pat , 1 ) ) ; case UNSPEC : if ( XINT ( pat , 1 ) == UNSPEC_CALLER ) return true ; default : break ; } return false ; } </s>

Check if PAT includes UNSPEC_CALLER unspec pattern .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , PPC :: ZERO ) ; markSuperRegs ( Reserved , PPC :: FP ) ; markSuperRegs ( Reserved , PPC :: BP ) ; markSuperRegs ( Reserved , PPC :: CTR ) ; markSuperRegs ( Reserved , PPC :: CTR8 ) ; markSuperRegs ( Reserved , PPC :: R1 ) ; markSuperRegs ( Reserved , PPC :: LR ) ; markSuperRegs ( Reserved , PPC :: LR8 ) ; markSuperRegs ( Reserved , PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( ! TM . isPPC64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; markSuperRegs ( Reserved , PPC :: R13 ) ; } if ( TM . isPPC64 ( ) ) markSuperRegs ( Reserved , PPC :: R13 ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R29 ) ; else markSuperRegs ( Reserved , PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) markSuperRegs ( Reserved , * I ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

PowerPC PPC PPC PPC PPC PPC::ZERO PPC::FP PPC::BP PPC::CTR PPC::CTR8 PPC::R1 PPC::LR PPC::LR8 PPC::RM PPC::VRSAVE PPC PPC PPC PPC::R2 PPC::R13 PPC PPC::R13 PPC::R31 PPC PPC::R29 PPC::R30 PPC PPC::R30 PPC::VRRCRegClass PPC::VRRCRegClass


<s> static bool aarch64_verify_type_context ( location_t loc , type_context_kind context , const_tree type , bool silent_p ) { return aarch64_sve :: verify_type_context ( loc , context , type , silent_p ) ; } </s>


<s> static rtx sparc_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return sparc_function_value_1 ( NULL_TREE , mode , false ) ; } </s>


<s> void PPCTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Store Pair Suppression"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
determineFrameLayout
(
MachineFunction
&
MF
)
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
TeeRISCMachineFunctionInfo
*
TFI
=
MF
.
getInfo
<
TeeRISCMachineFunctionInfo
>
(
)
;
TFI
->
adjustLoadArgsFI
(
MFI
)
;
TFI
->
adjustStoreVarArgsFI
(
MFI
)
;
unsigned
FrameSize
=
MFI
->
getStackSize
(
)
;
DEBUG
(
dbgs
(
)
<<
"Original Frame Size: "
<<
FrameSize
<<
"\n"
)
;
unsigned
TargetAlign
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
->
getStackAlignment
(
)
;
unsigned
AlignMask
=
TargetAlign
1
;
FrameSize
=
(
FrameSize
+
AlignMask
)
&
~
AlignMask
;
MFI
->
setStackSize
(
FrameSize
)
;
DEBUG
(
dbgs
(
)
<<
"Aligned Frame Size: "
<<
FrameSize
<<
"\n"
)
;
}
</s>

Determine the frame layout but do not update the machine function .

TeeRISC
TeeRISC
TeeRISC
"Original Frame Size: "
"\n"
1
"Aligned Frame Size: "
"\n"


Return an array that contains the bitmask target flag values and their names .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( ReserveR9 ) return CSR_NaCl_RegMask ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
void
SystemZPostRASchedStrategy
::
leaveMBB
(
)
{
DEBUG
(
dbgs
(
)
<<
"** Leaving "
<<
printMBBReference
(
*
MBB
)
<<
"\n"
;
)
;
advanceTo
(
MBB
->
getFirstTerminator
(
)
)
;
}
</s>

Tell the strategy that current MBB is done .


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , rtx offset , enum aarch64_symbol_context context ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_cmodel == AARCH64_CMODEL_LARGE ) return SYMBOL_FORCE_TO_MEM ; if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) || INTVAL ( offset ) < - 1048575 || INTVAL ( offset ) > 1048575 ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - 4294967263 ) , HOST_WIDE_INT_C ( 4294967264 ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_SMALL_GOT ; return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> const TargetRegisterClass * getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( RC == & AArch64 :: tcGPR64RegClass ) return & AArch64 :: GPR64RegClass ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> emitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>


<s> bool MipsPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> bool mips_pad_reg_upward ( machine_mode mode , tree type ) { if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_function_arg_padding ( mode , type ) == PAD_UPWARD ; } </s>

Likewise BLOCK_REG_PADDING ( MODE , TYPE , ... ) . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data . Return the opposite if the most significant byte does .


<s> static void sparc_solaris_elf_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { if ( HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE ) { solaris_elf_asm_comdat_section ( name , flags , decl ) ; return ; } fprintf ( asm_out_file , "\t.section\t\"%s\"" , name ) ; if ( ! ( flags & SECTION_DEBUG ) ) fputs ( ",#alloc" , asm_out_file ) ; if ( flags & SECTION_WRITE ) fputs ( ",#write" , asm_out_file ) ; if ( flags & SECTION_TLS ) fputs ( ",#tls" , asm_out_file ) ; if ( flags & SECTION_CODE ) fputs ( ",#execinstr" , asm_out_file ) ; if ( HAVE_AS_SPARC_NOBITS ) { if ( flags & SECTION_BSS ) fputs ( ",#nobits" , asm_out_file ) ; else fputs ( ",#progbits" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; } </s>

Solaris implementation of TARGET_ASM_NAMED_SECTION .

sparc "\t.section\t\"%s\"" ",#alloc" ",#write" ",#tls" ",#execinstr" ",#nobits" ",#progbits"


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
machine_mode
mode
,
unsigned
width
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
=
{
NULL_RTX
,
0
,
0
,
false
,
false
}
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
mode
,
false
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
info
.
element_width
)
;
lane_count
=
width
/
info
.
element_width
;
mode
=
GET_MODE_INNER
(
mode
)
;
if
(
GET_MODE_CLASS
(
mode
)
==
MODE_FLOAT
)
{
gcc_assert
(
info
.
shift
==
0
&&
!
info
.
mvn
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
const
unsigned
int
buf_size
=
20
;
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
value
)
,
buf_size
,
buf_size
,
1
,
mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
mnemonic
=
info
.
mvn
"mvni"
:
"movi"
;
shift_op
=
info
.
msl
"msl"
:
"lsl"
;
gcc_assert
(
CONST_INT_P
(
info
.
value
)
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
value
)
)
;
else
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
shift_op
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
break
;
case
ISD
::
BIT_CONVERT
:
Res
=
ExpandBIT_CONVERT
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
LowerShift
(
N
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::BIT_CONVERT
ISD::SRL
ISD::SRA


"lowerToVVP called for unexpected SDNode."


"dispatch_function_versions, clone %d, %s\n"

This function generates the dispatch function for multi-versioned functions . DISPATCH_DECL is the function which will contain the dispatch logic . FNDECLS are the function choices for dispatch , and is a tree chain . EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch code is generated .


<s> void MipsPassConfig :: addMachineSSAOptimization ( ) { addPass ( createMipsOptimizePICCallPass ( getMipsTargetMachine ( ) ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> void MipsInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> static rtx mmix_function_arg ( cumulative_args_t argsp , const function_arg_info & arg ) { return mmix_function_arg_1 ( argsp , arg , false ) ; } </s>

Return an rtx for a function argument to go in a register , and 0 for one that must go on stack .


<s> int ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 64 ) return 4 ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool ARMBaseInstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ 0 ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ 1 ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> static void ix86_option_override ( void ) { opt_pass * pass_insert_vzeroupper = make_pass_insert_vzeroupper ( g ) ; struct register_pass_info insert_vzeroupper_info = { pass_insert_vzeroupper , "reload" , 1 , PASS_POS_INSERT_AFTER } ; ix86_option_override_internal ( true , & global_options , & global_options_set ) ; register_pass ( & insert_vzeroupper_info ) ; } </s>

Implement the TARGET_OPTION_OVERRIDE hook .


<s> bool AArch64FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; static LoadStoreMethod PossibleClasses [ ] = { { & AArch64 :: GPR64RegClass , AArch64 :: LSPair64_LDR , AArch64 :: LS64_LDR } , { & AArch64 :: FPR64RegClass , AArch64 :: LSFPPair64_LDR , AArch64 :: LSFP64_LDR } , } ; unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( false , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> int sparc_absnegfloat_split_legitimate ( rtx x , rtx y ) { if ( GET_CODE ( x ) != REG ) return 0 ; if ( GET_CODE ( y ) != REG ) return 0 ; if ( REGNO ( x ) == REGNO ( y ) ) return 0 ; return 1 ; } </s>

Return 1 if x and y are some kind of REG and they refer to different hard registers . This test is guaranteed to be run after reload .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( SYMBOL_REF_P ( op ) ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || ! SYMBOL_REF_P ( XEXP ( XEXP ( op , 0 ) , 0 ) ) || ! CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> unsigned ARMFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , uint64_t Imm ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCFrameLowering
*
PPCFI
=
static_cast
<
const
PPCFrameLowering
*
>
(
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
)
;
unsigned
StackEst
=
PPCFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

PowerPC
PPC
0
"Local offset must be negative"
PPC::ADDI
PPC::ADDI8
2
0
PPC
PPC
PPC
PPC


<s>
const
char
*
ix86_output_function_return
(
bool
long_p
)
{
output_return_instrumentation
(
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_keep
)
{
char
thunk_name
[
32
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_thunk_inline
)
{
bool
need_thunk
=
(
cfun
->
machine
->
function_return_type
==
indirect_branch_thunk
)
;
indirect_thunk_name
(
thunk_name
,
INVALID_REGNUM
,
need_prefix
,
true
)
;
indirect_return_needed
|=
need_thunk
;
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
INVALID_REGNUM
)
;
return
""
;
}
if
(
!
long_p
)
return
"%!ret"
;
return
"rep%; ret"
;
}
</s>

Output function return . CALL_OP is the jump target . Add a REP prefix to RET if LONG_P is true and function return is kept .


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , LLT MemTy , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s> static bool mips_cfun_has_flexible_gp_ref_p ( void ) { if ( TARGET_ABICALLS_PIC2 && ! reload_completed && crtl -> uses_const_pool ) return true ; return mips_find_gp_ref ( & cfun -> machine -> has_flexible_gp_insn_p , mips_insn_has_flexible_gp_ref_p ) ; } </s>

Return true if the current function references the global pointer , but if those references do not inherently require the global pointer to be $ 28 . Assume ! mips_cfun_has_inflexible_gp_ref_p ( ) .


<s> static bool sparc_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { if ( TARGET_ARCH32 ) return ( TYPE_MODE ( type ) == BLKmode || TYPE_MODE ( type ) == TFmode || ( TREE_CODE ( type ) == VECTOR_TYPE && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( ( TYPE_MODE ( type ) == BLKmode && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 32 ) ) ; } </s>

Handle the TARGET_RETURN_IN_MEMORY target hook . Specify whether to return the return value in memory .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( Offset >= - 4096 && Offset <= 4095 ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( SP :: I6 , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } else { unsigned OffHi = ( unsigned ) Offset >> 10U ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: ADDrr ) , SP :: G1 ) . addReg ( SP :: G1 ) . addReg ( SP :: I6 ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( SP :: G1 , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset & ( ( 1 << 10 ) - 1 ) ) ; } } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> static void vr4130_true_reg_dependence_p_1 ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * insn_ptr = data ; if ( REG_P ( x ) && * insn_ptr != 0 && reg_referenced_p ( x , PATTERN ( * insn_ptr ) ) ) * insn_ptr = 0 ; } </s>

A note_stores callback used by vr4130_true_reg_dependence_p . DATA points to an rtx that is initially an instruction . Nullify the rtx if the instruction uses the value of register X .


<s> static void mips_sim_issue_nop ( struct mips_sim * state ) { if ( state -> insns_left == 0 ) mips_sim_next_cycle ( state ) ; state -> insns_left -- ; } </s>


<s> int mask_low_and_shift_len ( machine_mode mode , rtx mask , rtx shift ) { HOST_WIDE_INT shval ; shval = INTVAL ( shift ) & ( GET_MODE_BITSIZE ( mode ) - 1 ) ; return exact_log2 ( ( UINTVAL ( mask ) >> shval ) + 1 ) ; } </s>

The canonical form of a mask-low-and-shift-left operation is ( and ( ashift X SHIFT ) MASK ) where MASK has the lower SHIFT number of bits cleared . Thus we need to shift MASK to the right before checking if it is a valid mask value . MODE is the mode of the operation . If true return the length of the mask , otherwise return -1 .


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( TARGET_HAVE_MVE && VALID_MVE_MODE ( mode ) ) return mve_vector_mem_operand ( mode , x , strict_p ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) || ( TARGET_HAVE_MVE && VALID_MVE_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static int sh_pr_n_sets ( void ) { return DF_REG_DEF_COUNT ( PR_REG ) ; } </s>

For use by ALLOCATE_INITIAL_VALUE . Note that sh.md contains some 'special function ' patterns ( type sfunc ) that clobber pr , but that do not look like function calls to leaf_function_p . Hence we must do this extra check .


<s>
bool
X86FrameLowering
::
canUseAsPrologue
(
const
MachineBasicBlock
&
MBB
)
const
{
assert
(
MBB
.
getParent
(
)
&&
"Block is not attached to a function!"
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
return
!
TRI
->
needsStackRealignment
(
MF
)
||
!
MBB
.
isLiveIn
(
X86
::
EFLAGS
)
;
}
</s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> static void moxie_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx mem , fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , 4 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 16 ) ; emit_move_insn ( mem , fnaddr ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


<s> static rtx arm_gen_store_multiple_1 ( int count , int * regs , rtx * mems , rtx basereg , HOST_WIDE_INT wback_offset ) { int i = 0 , j ; rtx result ; if ( GET_CODE ( basereg ) == PLUS ) basereg = XEXP ( basereg , 0 ) ; if ( ! multiple_operation_profitable_p ( false , count , 0 ) ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( mems [ i ] , gen_rtx_REG ( SImode , regs [ i ] ) ) ; if ( wback_offset != 0 ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != 0 ? 1 : 0 ) ) ) ; if ( wback_offset != 0 ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( VOIDmode , basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) XVECEXP ( result , 0 , i ) = gen_rtx_SET ( VOIDmode , mems [ j ] , gen_rtx_REG ( SImode , regs [ j ] ) ) ; return result ; } </s>

Generate a store-multiple instruction . COUNT is the number of stores in the instruction ; REGS and MEMS are arrays containing the operands . BASEREG is the base register to be used in addressing the memory operands . WBACK_OFFSET is nonzero if the instruction should update the base register .


runOnMachineFunction - Emit the function body .


<s> bool AArch64FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const AArch64Subtarget & Subtarget = MF -> getSubtarget < AArch64Subtarget > ( ) ; const AArch64RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( ! RegInfo -> hasStackRealignment ( * MF ) ) return true ; return findScratchNonCalleeSaveRegister ( TmpMBB ) != AArch64 :: NoRegister ; } </s>


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const { return NumCycles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
optForSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool CSKYDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> hashval_t toc_hasher :: hash ( toc_hash_struct * thc ) { return rs6000_hash_constant ( thc -> key ) ^ thc -> key_mode ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> unsigned X86FrameLowering :: getInitialCFARegister ( const MachineFunction & MF ) const { return TRI -> getDwarfRegNum ( StackPtr , true ) ; } </s>


<s> bool CAHPFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"passing %qT to argument %d of %qE, but"

Like require_vector_type , but TYPE is inferred from previous arguments rather than being a fixed part of the function signature . This changes the nature of the error messages .


Return whether we need to emit an ELFv2 global entry point prologue .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { if ( funcInfo . MF -> getSubtarget < ARMSubtarget > ( ) . useFastISel ( ) ) return new ARMFastISel ( funcInfo , libInfo ) ; return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> Align ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { const Align ABITypeAlign ( DL . getABITypeAlignment ( ArgTy ) ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ; } </s>

Return the correct alignment for the current calling convention .


<s> static rtx rs6000_adjust_atomic_subword ( rtx orig_mem , rtx * pshift , rtx * pmask ) { rtx addr , align , shift , mask , mem ; HOST_WIDE_INT shift_mask ; machine_mode mode = GET_MODE ( orig_mem ) ; shift_mask = ( mode == QImode ? 0x18 : 0x10 ) ; addr = XEXP ( orig_mem , 0 ) ; addr = force_reg ( GET_MODE ( addr ) , addr ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - 4 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; mem = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; shift = gen_reg_rtx ( SImode ) ; addr = gen_lowpart ( SImode , addr ) ; rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashlsi3 ( tmp , addr , GEN_INT ( 3 ) ) ) ; emit_insn ( gen_andsi3 ( shift , tmp , GEN_INT ( shift_mask ) ) ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_simple_binop ( SImode , XOR , shift , GEN_INT ( shift_mask ) , shift , 1 , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; * pmask = mask ; return mem ; } </s>

A subroutine of the various atomic expanders . For sub-word operations , we must adjust things to operate on SImode . Given the original MEM , return a new aligned memory . Also build and return the quantities by which to shift and mask .


"PRINT_OPERAND_ADDRESS, invalid insn #1"

Print a memory address as an operand to reference that memory location .


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & , unsigned Depth ) const { if ( Op . getOpcode ( ) == X86ISD :: SETCC_CARRY ) return Op . getValueType ( ) . getScalarSizeInBits ( ) ; return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> bool mips_store_by_pieces_p ( unsigned HOST_WIDE_INT size , unsigned int align ) { if ( align <= BITS_PER_UNIT ) return size < 4 ; return size < 8 ; } </s>


<s> Value * AArch64TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; const unsigned TlsOffset = 0x48 ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * ThreadPointerFunc = Intrinsic :: getDeclaration ( M , Intrinsic :: aarch64_thread_pointer ) ; return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( 0 ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> void ix86_expand_floorceildf_32 ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; one = force_reg ( mode , const_double_from_real_value ( do_floor ? dconst1 : dconstm1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


<s> const SparcSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> void PPCPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & IfConverterID ) ; if ( ! DisableQPXLoadSplat ) addPass ( createPPCQPXLoadSplatPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SystemZ Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ix86_check_movabs ( rtx insn , int opnum ) { rtx set , mem ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; mem = XEXP ( set , opnum ) ; while ( SUBREG_P ( mem ) ) mem = SUBREG_REG ( mem ) ; gcc_assert ( MEM_P ( mem ) ) ; return volatile_ok || ! MEM_VOLATILE_P ( mem ) ; } </s>

Return nonzero if OPNUM 's MEM should be matched in movabs * patterns .


<s> bool X86ATTAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO ) ; else printOperand ( MI , OpNo ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] ) ; printOperand ( MI , OpNo ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( * MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; MinimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
bool
aarch64_validate_mtune
(
const
char
*
str
,
const
struct
processor
*
*
res
)
{
enum
aarch64_parse_opt_result
parse_res
=
aarch64_parse_tune
(
str
,
res
)
;
if
(
parse_res
==
AARCH64_PARSE_OK
)
return
true
;
switch
(
parse_res
)
{
case
AARCH64_PARSE_MISSING_ARG
:
error
(
"missing cpu name in %<-mtune=%s%>"
,
str
)
;
break
;
case
AARCH64_PARSE_INVALID_ARG
:
error
(
"unknown value %qs for %<-mtune%>"
,
str
)
;
aarch64_print_hint_for_core
(
str
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
false
;
}
</s>

Validate a command-line -mtune option . Parse the cpu specified in STR and throw errors if appropriate . Put the result , if it is valid , in RES . Return whether the option is valid .

aarch64
"missing cpu name in %<-mtune=%s%>"
"unknown value %qs for %<-mtune%>"


<s> static bool mips16_cfun_returns_in_fpr_p ( void ) { tree return_type = DECL_RESULT ( current_function_decl ) ; return ( TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI && ! aggregate_value_p ( return_type , current_function_decl ) && mips_return_mode_in_fpr_p ( DECL_MODE ( return_type ) ) ) ; } </s>

Return true if the current function returns its value in a floating-point register in MIPS16 mode .


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( * F . getFunction ( ) ) ) return false ; const SystemZSubtarget & ST = F . getSubtarget < SystemZSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>


<s> bool MipsFastISel :: fastSelectInstruction ( const Instruction * I ) { if ( ! TargetSupported ) return false ; switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> SDValue ARM64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? Subtarget -> getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const ARM64TargetLowering & TLI = * static_cast < const ARM64TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , CallingConv :: C , false , false , false , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


"********** AArch64 Conditional Compares **********\n"


<s> int rs6000_hard_regno_nregs ( int regno , enum machine_mode mode ) { if ( FP_REGNO_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_WORD - 1 ) / UNITS_PER_FP_WORD ; if ( TARGET_E500_DOUBLE && mode == DFmode ) return 1 ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_SPE_WORD - 1 ) / UNITS_PER_SPE_WORD ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_ALTIVEC_WORD - 1 ) / UNITS_PER_ALTIVEC_WORD ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . For the SPE , GPRs are 64 bits but only 32 bits are visible in scalar instructions . The upper 32 bits are only available to the SIMD instructions . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


<s>
SDValue
FISCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_FISC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
8
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
FISCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> inline bool libcall_hasher :: equal ( const value_type * p1 , const compare_type * p2 ) { return rtx_equal_p ( p1 , p2 ) ; } </s>


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> static bool rs6000_gen_pic_addr_diff_vec ( void ) { return rs6000_relative_jumptables ; } </s>


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void LEGRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case LEG :: LDR : case LEG :: STR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ; FIOp . ChangeToRegister ( LEG :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"


<s> bool VETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) { * Fast = true ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


"Skipping offset folding global address: "

"AArch64 doesn't support folding offsets into global "

Return true if folding a constant offset with the given GlobalAddress is legal .


"rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , IsO32 , Subtarget -> isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget -> mipsSEUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
output_asm_insn
(
"str\tr0, [%0, #0]"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tbne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { EVT VT = Op . getValueType ( ) ; const char * RecipOp ; if ( VT == MVT :: f32 && Subtarget -> hasSSE1 ( ) ) RecipOp = "divf" ; else if ( ( VT == MVT :: v4f32 && Subtarget -> hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget -> hasAVX ( ) ) ) RecipOp = "vec-divf" ; else return SDValue ( ) ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; return DCI . DAG . getNode ( X86ISD :: FRCP , SDLoc ( Op ) , VT , Op ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> static tree ia64_gimplify_va_arg ( tree valist , tree type , tree * pre_p , tree * post_p ) { if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { tree ptrtype = build_pointer_type ( type ) ; tree addr = std_gimplify_va_arg_expr ( valist , ptrtype , pre_p , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } if ( ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) ? int_size_in_bytes ( type ) > 8 : TYPE_ALIGN ( type ) > 8 * BITS_PER_UNIT ) { tree t = build ( PLUS_EXPR , TREE_TYPE ( valist ) , valist , build_int_cst ( NULL_TREE , 2 * UNITS_PER_WORD - 1 ) ) ; t = build ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( NULL_TREE , - 2 * UNITS_PER_WORD ) ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; } return std_gimplify_va_arg_expr ( valist , type , pre_p , post_p ) ; } </s>


<s> static void def_builtin ( int mask , const char * name , tree type , int code ) { if ( mask & target_flags ) { if ( rs6000_builtin_decls [ code ] ) abort ( ) ; rs6000_builtin_decls [ code ] = lang_hooks . builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; } } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> static reg_class_t aarch64_ira_change_pseudo_allocno_class ( int regno , reg_class_t allocno_class , reg_class_t best_class ) { enum machine_mode mode ; if ( allocno_class != ALL_REGS ) return allocno_class ; if ( best_class != ALL_REGS ) return best_class ; mode = PSEUDO_REGNO_MODE ( regno ) ; return FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ? FP_REGS : GENERAL_REGS ; } </s>

Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS . The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have the same cost even if ALL_REGS has a much larger cost . ALL_REGS is also used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory cost ( in this case the best class is the lowest cost one ) . Using ALL_REGS irrespectively of its cost results in bad allocations with many redundant int < - > FP moves which are expensive on various cores . To avoid this we do n't allow ALL_REGS as the allocno class , but force a decision between FP_REGS and GENERAL_REGS . We use the allocno class if it is n't ALL_REGS . Similarly , use the best class if it is n't ALL_REGS . Otherwise set the allocno class depending on the mode . The result of this is that it is no longer inefficient to have a higher memory move cost than the register move cost .


<s> virtual bool runOnFunction ( Function & Fn ) { if ( Fn . hasAvailableExternallyLinkage ( ) ) return false ; GlobalBaseReg = 0 ; SelectionDAGISel :: runOnFunction ( Fn ) ; InsertVRSaveCode ( Fn ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static enum mips_ucbranch_type mips_classify_branch_p6600 ( rtx_insn * insn ) { if ( ! insn || ! USEFUL_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) return UC_UNDEFINED ; if ( get_attr_jal ( insn ) == JAL_INDIRECT || get_attr_type ( insn ) == TYPE_JUMP ) return UC_OTHER ; if ( CALL_P ( insn ) && get_attr_jal ( insn ) == JAL_DIRECT ) return UC_BALC ; return UC_UNDEFINED ; } </s>

Subroutine of mips_avoid_hazard . We classify unconditional branches of interest for the P6600 for performance reasons . We 're interested in differentiating BALC from JIC , JIALC and BC .


<s> rtx maybe_get_pool_constant ( rtx x ) { x = ix86_delegitimize_address ( XEXP ( x , 0 ) ) ; if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) return get_pool_constant ( x ) ; return NULL_RTX ; } </s>

X is an unchanging MEM . If it is a constant pool reference , return the constant pool rtx , else NULL .


"%<#pragma GCC arm%> requires a string parameter"

"unknown %<#pragma GCC arm%> option %qs"


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


Try to add a comment on the PC-relative load .


<s> void mips_expand_conditional_branch ( rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx condition ; mips_emit_compare ( & code , & op0 , & op1 , TARGET_MIPS16 ) ; condition = gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; emit_jump_insn ( gen_condjump ( condition , operands [ 3 ] ) ) ; } </s>

Compare OPERANDS [ 1 ] with OPERANDS [ 2 ] using comparison code CODE and jump to OPERANDS [ 3 ] if the condition holds .


<s> static void sh_output_function_epilogue ( FILE * ) { } </s>


<s> static int do_reorder_for_imul ( rtx_insn * * ready , int n_ready ) { rtx_insn * insn ; rtx set , insn1 , insn2 ; sd_iterator_def sd_it ; dep_t dep ; int index = - 1 ; int i ; if ( ! TARGET_BONNELL ) return index ; insn = ready [ n_ready - 1 ] ; set = single_set ( insn ) ; if ( ! set ) return index ; if ( ! ( GET_CODE ( SET_SRC ( set ) ) == MULT && GET_MODE ( SET_SRC ( set ) ) == SImode ) ) return index ; for ( i = n_ready - 2 ; i >= 0 ; i -- ) { insn = ready [ i ] ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; insn2 = PATTERN ( insn ) ; if ( GET_CODE ( insn2 ) == PARALLEL ) insn2 = XVECEXP ( insn2 , 0 , 0 ) ; if ( GET_CODE ( insn2 ) == SET && GET_CODE ( SET_SRC ( insn2 ) ) == MULT && GET_MODE ( SET_SRC ( insn2 ) ) == SImode ) continue ; FOR_EACH_DEP ( insn , SD_LIST_FORW , sd_it , dep ) { rtx con ; con = DEP_CON ( dep ) ; if ( ! NONDEBUG_INSN_P ( con ) ) continue ; insn1 = PATTERN ( con ) ; if ( GET_CODE ( insn1 ) == PARALLEL ) insn1 = XVECEXP ( insn1 , 0 , 0 ) ; if ( GET_CODE ( insn1 ) == SET && GET_CODE ( SET_SRC ( insn1 ) ) == MULT && GET_MODE ( SET_SRC ( insn1 ) ) == SImode ) { sd_iterator_def sd_it1 ; dep_t dep1 ; index = i ; FOR_EACH_DEP ( con , SD_LIST_BACK , sd_it1 , dep1 ) { rtx pro ; pro = DEP_PRO ( dep1 ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( pro != insn ) index = - 1 ; } if ( index >= 0 ) break ; } } if ( index >= 0 ) break ; } return index ; } </s>

Try to reorder ready list to take advantage of Atom pipelined IMUL execution . It is applied if ( 1 ) IMUL instruction is on the top of list ; ( 2 ) There exists the only producer of independent IMUL instruction in ready list . Return index of IMUL producer if it was found and -1 otherwise .


<s> bool X86RetpolineThunks :: doInitialization ( Module & M ) { InsertedThunks = false ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static rtx rs6000_darwin64_record_arg ( CUMULATIVE_ARGS * orig_cum , const_tree type , bool named , bool retval ) { rtx rvec [ FIRST_PSEUDO_REGISTER ] ; int k = 1 , kbase = 1 ; HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; CUMULATIVE_ARGS copy_cum = * orig_cum ; CUMULATIVE_ARGS * cum = & copy_cum ; if ( ! retval && TYPE_ALIGN ( type ) >= 2 * BITS_PER_WORD && ( cum -> words % 2 ) != 0 ) cum -> words ++ ; cum -> intoffset = 0 ; cum -> use_stack = 0 ; cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , 0 , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = 0 ; rvec [ 0 ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } if ( k > 1 || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( k - kbase , & rvec [ kbase ] ) ) ; else return NULL_RTX ; } </s>

For the darwin64 ABI , we want to construct a PARALLEL consisting of the register ( s ) to be used for each field and subfield of a struct being passed by value , along with the offset of where the register 's value may be found in the block . FP fields go in FP register , vector fields go in vector registers , and everything else goes in int registers , packed as in memory . This code is also used for function return values . RETVAL indicates whether this is the case . Much of this is taken from the SPARC V9 port , which has a similar calling convention .


<s>
bool
AArch64CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
AArch64
::
RET_ReallyLR
)
;
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
bool
Success
=
true
;
if
(
VReg
)
{
const
AArch64TargetLowering
&
TLI
=
*
getTLI
<
AArch64TargetLowering
>
(
)
;
CCAssignFn
*
AssignFn
=
TLI
.
CCAssignFnForReturn
(
F
.
getCallingConv
(
)
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
F
.
getParent
(
)
->
getDataLayout
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeSet
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
,
ArrayRef
<
uint64_t
>
Offsets
)
{
MIRBuilder
.
buildExtract
(
Regs
,
Offsets
,
VReg
)
;
}
)
;
OutgoingArgHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
)
;
Success
=
handleAssignments
(
MIRBuilder
,
AssignFn
,
SplitArgs
,
Handler
)
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
Success
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , & STI , Alignment ) ; else OS . emitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
RM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
IsAndroid
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . isCortexA9 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> enum calling_abi ix86_cfun_abi ( void ) { return cfun ? cfun -> machine -> call_abi : ix86_abi ; } </s>

Returns value SYSV_ABI , MS_ABI dependent on cfun , specifying the call abi used .


<s>
unsigned
PPCInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
getLastNonDebugInstr
(
)
;
if
(
I
==
MBB
.
end
(
)
)
return
0
;
if
(
I
->
getOpcode
(
)
!=
PPC
::
B
&&
I
->
getOpcode
(
)
!=
PPC
::
BCC
&&
I
->
getOpcode
(
)
!=
PPC
::
BC
&&
I
->
getOpcode
(
)
!=
PPC
::
BCn
&&
I
->
getOpcode
(
)
!=
PPC
::
BDNZ8
&&
I
->
getOpcode
(
)
!=
PPC
::
BDNZ
&&
I
->
getOpcode
(
)
!=
PPC
::
BDZ8
&&
I
->
getOpcode
(
)
!=
PPC
::
BDZ
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
I
->
getOpcode
(
)
!=
PPC
::
BCC
&&
I
->
getOpcode
(
)
!=
PPC
::
BC
&&
I
->
getOpcode
(
)
!=
PPC
::
BCn
&&
I
->
getOpcode
(
)
!=
PPC
::
BDNZ8
&&
I
->
getOpcode
(
)
!=
PPC
::
BDNZ
&&
I
->
getOpcode
(
)
!=
PPC
::
BDZ8
&&
I
->
getOpcode
(
)
!=
PPC
::
BDZ
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> static bool ia64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) && ( ( mode1 == XFmode || mode1 == XCmode || mode1 == RFmode ) == ( mode2 == XFmode || mode2 == XCmode || mode2 == RFmode ) ) && ( mode1 == BImode ) == ( mode2 == BImode ) ) ; } </s>

Implement TARGET_MODES_TIEABLE_P . Do n't tie integer and FP modes , as that causes us to get integer registers allocated for FP instructions . XFmode only supported in FP registers so we ca n't tie it with any other modes .


<s> int ccr_bit ( rtx op , int scc_p ) { enum rtx_code code = GET_CODE ( op ) ; machine_mode cc_mode ; int cc_regnum ; int base_bit ; rtx reg ; if ( ! COMPARISON_P ( op ) ) return - 1 ; reg = XEXP ( op , 0 ) ; gcc_assert ( GET_CODE ( reg ) == REG && CR_REGNO_P ( REGNO ( reg ) ) ) ; cc_mode = GET_MODE ( reg ) ; cc_regnum = REGNO ( reg ) ; base_bit = 4 * ( cc_regnum - CR0_REGNO ) ; validate_condition_mode ( code , cc_mode ) ; gcc_assert ( ! scc_p || code == EQ || code == GT || code == LT || code == UNORDERED || code == GTU || code == LTU ) ; switch ( code ) { case NE : return scc_p ? base_bit + 3 : base_bit + 2 ; case EQ : return base_bit + 2 ; case GT : case GTU : case UNLE : return base_bit + 1 ; case LT : case LTU : case UNGE : return base_bit ; case ORDERED : case UNORDERED : return base_bit + 3 ; case GE : case GEU : return scc_p ? base_bit + 3 : base_bit ; case LE : case LEU : return scc_p ? base_bit + 3 : base_bit + 1 ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison operation , return the bit number in CCR to test . We know this is a valid comparison . SCC_P is 1 if this is for an scc . That means that % D will have been used instead of % C , so the bits will be in different places . Return -1 if OP is n't a valid comparison for some reason .


<s> bool ix86_legitimize_reload_address ( rtx x , machine_mode , int opnum , int type , int ) { if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 1 ) ) && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) { rtx base , index ; bool something_reloaded = false ; base = XEXP ( XEXP ( x , 0 ) , 1 ) ; if ( ! REG_OK_FOR_BASE_STRICT_P ( base ) ) { push_reload ( base , NULL_RTX , & XEXP ( XEXP ( x , 0 ) , 1 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; something_reloaded = true ; } index = XEXP ( x , 1 ) ; if ( ! REG_OK_FOR_INDEX_STRICT_P ( index ) ) { push_reload ( index , NULL_RTX , & XEXP ( x , 1 ) , NULL , INDEX_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; something_reloaded = true ; } gcc_assert ( something_reloaded ) ; return true ; } return false ; } </s>

Our implementation of LEGITIMIZE_RELOAD_ADDRESS . Returns a value to replace the input X , or the original X if no replacement is called for . The output parameter * WIN is 1 if the calling macro should goto WIN , 0 if it should not .


<s> const UPTRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) || Subtarget -> outlineAtomics ( ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> static void ix86_reorg ( void ) { compute_bb_for_insn ( ) ; if ( flag_mitigate_rop ) ix86_mitigate_rop ( ) ; if ( TARGET_SEH && current_function_has_exception_handlers ( ) ) ix86_seh_fixup_eh_fallthru ( ) ; if ( optimize && optimize_function_for_speed_p ( cfun ) ) { if ( TARGET_PAD_SHORT_FUNCTION ) ix86_pad_short_function ( ) ; else if ( TARGET_PAD_RETURNS ) ix86_pad_returns ( ) ; if ( TARGET_FOUR_JUMP_LIMIT ) ix86_avoid_jump_mispredicts ( ) ; } } </s>

Implement machine specific optimizations . We implement padding of returns for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window .


<s> const SparcRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>


<s> static bool pa_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; if ( TARGET_64BIT ) return size <= 0 ; else return size <= 0 || size > 8 ; } </s>

In the 32-bit runtime , arguments larger than eight bytes are passed by invisible reference . As a GCC extension , we also pass anything with a zero or variable size by reference . The 64-bit runtime does not describe passing any types by invisible reference . The internals of GCC ca n't currently handle passing empty structures , and zero or variable length arrays when they are not passed entirely on the stack or by reference . Thus , as a GCC extension , we pass these types by reference . The HP compiler does n't support these types , so hopefully there should n't be any compatibility issues . This may have to be revisited when HP releases a C99 compiler or updates the ABI .


<s> bool mips_split_64bit_move_p ( rtx dest , rtx src ) { if ( TARGET_64BIT ) return false ; if ( FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( mips_isa > 1 ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } return true ; } </s>

Return true if a 64-bit move from SRC to DEST should be split into two .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT . getSizeInBits ( ) == 16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; if ( VT . getSizeInBits ( ) == 32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( 2 , Size - 1 ) . getAsInteger ( 10 , RegNo ) ; if ( ! Failed && RegNo >= 0 && RegNo <= 31 ) { if ( VT != MVT :: Other && VT . getSizeInBits ( ) == 64 ) { Res . first = AArch64 :: FPR64RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR64RegClass ; } else { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : case G_BRCOND : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> void ARMTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { if ( ! ST -> isMClass ( ) ) return BasicTTIImplBase :: getUnrollingPreferences ( L , SE , UP ) ; if ( ! ST -> isThumb2 ( ) || L -> getNumBlocks ( ) != 1 ) return ; UP . OptSizeThreshold = 0 ; UP . PartialOptSizeThreshold = 0 ; BasicBlock * BB = L -> getLoopLatch ( ) ; if ( BB -> getParent ( ) -> optForSize ( ) ) return ; unsigned Cost = 0 ; for ( auto & I : * BB ) { if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , 4 > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } UP . Partial = true ; UP . Runtime = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = 4 ; if ( Cost < 12 ) UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> unsigned getNumFixupKinds ( ) const { return TOY :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . readMem = false ; Info . writeMem = false ; Info . vol = false ; Info . offset = 0 ; switch ( IntrData -> Type ) { case LOADA : case LOADU : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = ( IntrData -> Type == LOADA ? Info . memVT . getSizeInBits ( ) / 8 : 1 ) ; Info . readMem = true ; break ; } case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = 1 ; Info . readMem = true ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case STOREA : case STOREANT : case STOREU : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = ( IntrData -> Type == STOREU ? 1 : Info . memVT . getSizeInBits ( ) / 8 ) ; Info . writeMem = true ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static void mips16_rewrite_pool_refs ( rtx_insn * insn , struct mips16_constant_pool * pool ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , & PATTERN ( insn ) , ALL ) { rtx * loc = * iter ; if ( force_to_mem_operand ( * loc , Pmode ) ) { rtx mem = force_const_mem ( GET_MODE ( * loc ) , * loc ) ; validate_change ( insn , loc , mem , false ) ; } if ( MEM_P ( * loc ) ) { mips16_rewrite_pool_constant ( pool , & XEXP ( * loc , 0 ) ) ; iter . skip_subrtxes ( ) ; } else { if ( TARGET_MIPS16_TEXT_LOADS ) mips16_rewrite_pool_constant ( pool , loc ) ; if ( GET_CODE ( * loc ) == CONST || ( GET_CODE ( * loc ) == UNSPEC && XINT ( * loc , 1 ) == UNSPEC_TLS_GET_TP ) ) iter . skip_subrtxes ( ) ; } } } </s>

Rewrite * X so that constant pool references refer to the constant 's label instead . DATA points to the constant pool structure .