<s> static tree ix86_veclibabi_svml ( enum built_in_function fn , tree type_out , tree type_in ) { char name [ 20 ] ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { case BUILT_IN_EXP : case BUILT_IN_LOG : case BUILT_IN_LOG10 : case BUILT_IN_POW : case BUILT_IN_TANH : case BUILT_IN_TAN : case BUILT_IN_ATAN : case BUILT_IN_ATAN2 : case BUILT_IN_ATANH : case BUILT_IN_CBRT : case BUILT_IN_SINH : case BUILT_IN_SIN : case BUILT_IN_ASINH : case BUILT_IN_ASIN : case BUILT_IN_COSH : case BUILT_IN_COS : case BUILT_IN_ACOSH : case BUILT_IN_ACOS : if ( el_mode != DFmode || n != 2 ) return NULL_TREE ; break ; case BUILT_IN_EXPF : case BUILT_IN_LOGF : case BUILT_IN_LOG10F : case BUILT_IN_POWF : case BUILT_IN_TANHF : case BUILT_IN_TANF : case BUILT_IN_ATANF : case BUILT_IN_ATAN2F : case BUILT_IN_ATANHF : case BUILT_IN_CBRTF : case BUILT_IN_SINHF : case BUILT_IN_SINF : case BUILT_IN_ASINHF : case BUILT_IN_ASINF : case BUILT_IN_COSHF : case BUILT_IN_COSF : case BUILT_IN_ACOSHF : case BUILT_IN_ACOSF : if ( el_mode != SFmode || n != 4 ) return NULL_TREE ; break ; default : return NULL_TREE ; } bname = IDENTIFIER_POINTER ( DECL_NAME ( builtin_decl_implicit ( fn ) ) ) ; if ( fn == BUILT_IN_LOGF ) strcpy ( name , "vmlsLn4" ) ; else if ( fn == BUILT_IN_LOG ) strcpy ( name , "vmldLn2" ) ; else if ( n == 4 ) { sprintf ( name , "vmls%s" , bname + 10 ) ; name [ strlen ( name ) - 1 ] = '4' ; } else sprintf ( name , "vmld%s2" , bname + 10 ) ; name [ 4 ] &= ~ 0x20 ; arity = 0 ; for ( args = DECL_ARGUMENTS ( builtin_decl_implicit ( fn ) ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an SVML-style interface to a library with vectorized intrinsics .


<s> static bool ix86_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { return SSE_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 16 ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The only ABI that saves SSE registers across calls is Win64 ( thus no need to check the current ABI here ) , and with AVX enabled Win64 only guarantees that the low 16 bytes are saved .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
TM
=
&
Func
.
getTarget
(
)
;
const
X86Subtarget
&
ST
=
TM
->
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void ix86_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( & next_cum ) ; else setup_incoming_varargs_64 ( & next_cum ) ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SETCC : return PerformSETCCCombine ( N , DCI . DAG ) ; case ISD :: VSELECT : return PerformVSelectCombine ( N , DCI . DAG ) ; case ISD :: SIGN_EXTEND : return PerformSignExtendCombine ( N , DCI . DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case AArch64ISD :: NEON_VDUPLANE : return CombineVLDDUP ( N , DCI ) ; case AArch64ISD :: NEON_LD2DUP : case AArch64ISD :: NEON_LD3DUP : case AArch64ISD :: NEON_LD4DUP : return CombineBaseUpdate ( N , DCI ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : case Intrinsic :: aarch64_neon_vld1x2 : case Intrinsic :: aarch64_neon_vld1x3 : case Intrinsic :: aarch64_neon_vld1x4 : case Intrinsic :: aarch64_neon_vst1x2 : case Intrinsic :: aarch64_neon_vst1x3 : case Intrinsic :: aarch64_neon_vst1x4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : return CombineBaseUpdate ( N , DCI ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
TargetLowering
::
AtomicExpansionKind
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
.
is64Bit
(
)
64
:
32
;
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
{
return
needsCmpXchgNb
(
MemType
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
}
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
case
AtomicRMWInst
::
FAdd
:
case
AtomicRMWInst
::
FSub
:
return
AtomicExpansionKind
::
CmpXChg
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> inline const mode_suffix_info & function_instance :: mode_suffix ( ) const { return mode_suffixes [ mode_suffix_id ] ; } </s>

Return information about the function 's mode suffix .


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , const vec_perm_builder & perm ) { rtx x = expand_vec_perm_const ( vmode , op0 , op1 , perm , BLKmode , target ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool runOnFunction ( Function & F ) override { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < PPCTargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; PHINodeSet PromotablePHINodes = getPromotablePHINodes ( F ) ; B2IMap Bool2IntMap ; bool Changed = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { if ( auto * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( R -> getOperandUse ( 0 ) , PromotablePHINodes , Bool2IntMap ) ; if ( auto * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"********** AArch64 Conditional Compares **********\n"


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = STI . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void rs6000_elf_unique_section ( tree decl , int reloc ) { default_unique_section_1 ( decl , reloc , flag_pic || DEFAULT_ABI == ABI_AIX ) ; } </s>

A C statement to build up a unique section name , expressed as a STRING_CST node , and assign it to DECL_SECTION_NAME ( decl ) . RELOC indicates whether the initial value of EXP requires link-time relocations . If you do not define this macro , GCC will use the symbol name prefixed by ` . ' as the section name . Note - this macro can now be called for uninitialized data items as well as initialized data and functions .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DCI ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case AArch64ISD :: NVCAST : return performNVCASTCombine ( N ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: EXTRACT_VECTOR_ELT : return performAcrossLaneReductionCombine ( N , DAG , Subtarget ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , 0 ) . exists ( & mode ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


<s> int mmix_shiftable_wyde_value ( unsigned HOST_WIDEST_INT value ) { int i ; int has_candidate = 0 ; for ( i = 0 ; i < 4 ; i ++ ) { if ( value & 65535 ) { if ( has_candidate ) return 0 ; else has_candidate = 1 ; } value >>= 16 ; } return 1 ; } </s>

Return 1 if value is 0 .. 65535 * 2 * * ( 16 * N ) for N=0 .. 3. else return 0 .


<s> int pru_get_ctable_base_index ( unsigned HOST_WIDE_INT caddr ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( pru_ctable ) ; i ++ ) { if ( pru_ctable [ i ] . valid && IN_RANGE ( caddr , pru_ctable [ i ] . base , pru_ctable [ i ] . base + 0xff ) ) return i ; } return - 1 ; } </s>

Check if the given address can be addressed via CTABLE_BASE + UBYTE_OFFS , and return the base CTABLE index if possible .


<s> static int loongarch_immediate_operand_p ( int code , HOST_WIDE_INT x ) { switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : return true ; case ROTATE : case ROTATERT : return true ; case AND : case IOR : case XOR : return IMM12_OPERAND_UNSIGNED ( x ) ; case PLUS : case LT : case LTU : return IMM12_OPERAND ( x ) ; case EQ : case NE : case GT : case GTU : return x == 0 ; case GE : case GEU : return x == 1 ; case LE : return IMM12_OPERAND ( x + 1 ) ; case LEU : return IMM12_OPERAND ( x + 1 ) && x + 1 != 0 ; case SIGN_EXTRACT : case ZERO_EXTRACT : return 1 ; default : return x == 0 ; } } </s>

Return true if there is a instruction that implements CODE and if that instruction accepts X as an immediate operand .


<s> const char * Cpu0TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Cpu0ISD :: JmpLink : return "Cpu0ISD::JmpLink" ; case Cpu0ISD :: TailCall : return "Cpu0ISD::TailCall" ; case Cpu0ISD :: Hi : return "Cpu0ISD::Hi" ; case Cpu0ISD :: Lo : return "Cpu0ISD::Lo" ; case Cpu0ISD :: GPRel : return "Cpu0ISD::GPRel" ; case Cpu0ISD :: Ret : return "Cpu0ISD::Ret" ; case Cpu0ISD :: EH_RETURN : return "Cpu0ISD::EH_RETURN" ; case Cpu0ISD :: DivRem : return "Cpu0ISD::DivRem" ; case Cpu0ISD :: DivRemU : return "Cpu0ISD::DivRemU" ; case Cpu0ISD :: Wrapper : return "Cpu0ISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const MipsRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void AnalyzeCallResult ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn , const Type * RetTy , const char * Func ) { PreAnalyzeCallResult ( Ins , Fn , RetTy , Func ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; } </s>

AnalyzeCallResult - Same as above except it 's specialized for calls which produce a single value .


<s> static rtx function_arg_record_value ( const_tree type , machine_mode mode , int slotno , int named , int regbase ) { HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; struct function_arg_record_value_parms parms ; unsigned int nregs ; parms . ret = NULL_RTX ; parms . slotno = slotno ; parms . named = named ; parms . regbase = regbase ; parms . stack = 0 ; parms . nregs = 0 ; parms . intoffset = 0 ; function_arg_record_value_1 ( type , 0 , & parms , false ) ; if ( parms . intoffset != - 1 ) { unsigned int startbit , endbit ; int intslots , this_slotno ; startbit = parms . intoffset & - BITS_PER_WORD ; endbit = ( typesize * BITS_PER_UNIT + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = slotno + parms . intoffset / BITS_PER_WORD ; if ( intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno ) { intslots = MAX ( 0 , SPARC_INT_ARG_MAX - this_slotno ) ; parms . stack = 1 ; } parms . nregs += intslots ; } nregs = parms . nregs ; if ( nregs == 0 ) { if ( typesize <= 0 ) { return gen_rtx_REG ( mode , regbase ) ; } else { nregs = ( typesize + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs != 0 ) ; parms . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( parms . stack + nregs ) ) ; if ( parms . stack ) XVECEXP ( parms . ret , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; parms . nregs = 0 ; parms . intoffset = 0 ; function_arg_record_value_2 ( type , 0 , & parms , false ) ; function_arg_record_value_3 ( typesize * BITS_PER_UNIT , & parms ) ; gcc_assert ( parms . nregs == nregs ) ; return parms . ret ; } </s>

Used by function_arg and sparc_function_value_1 to implement the complex conventions of the 64-bit ABI for passing and returning structures . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . MODE is the argument 's machine mode . SLOTNO is the index number of the argument 's slot in the parameter array . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . REGBASE is the regno of the base register for the parameter array .


<s> CSKYSubtarget & CSKYSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPUName , StringRef TuneCPUName , StringRef FS ) { if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; UseHardFloat = false ; UseHardFloatABI = false ; HasFPUv2SingleFloat = false ; HasFPUv2DoubleFloat = false ; HasFPUv3SingleFloat = false ; HasFPUv3DoubleFloat = false ; HasBTST16 = false ; HasJAVA = false ; HasExtendLrw = false ; HasDoloop = false ; HasHighRegisters = false ; HasE1 = false ; HasE2 = false ; Has2E3 = false ; HasMP = false ; Has3E3r1 = false ; Has3r1E3r2 = false ; Has3r2E3r3 = false ; Has3E7 = false ; HasMP1E2 = false ; Has7E10 = false ; Has10E60 = false ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned AArch64RegisterBankInfo :: copyCost ( const RegisterBank & A , const RegisterBank & B , unsigned Size ) const { if ( & A == & AArch64 :: GPRRegBank && & B == & AArch64 :: FPRRegBank ) return 5 ; if ( & A == & AArch64 :: FPRRegBank && & B == & AArch64 :: GPRRegBank ) return 4 ; return RegisterBankInfo :: copyCost ( A , B , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .


<s> const uint16_t * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; return CSR_O32_SaveList ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > LanaiTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & Lanai :: GPRRegClass ) ; default : break ; } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> int getIntImmCostInst ( unsigned Opc , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vzipv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vzipv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


"%<asm%> flags not supported in thumb1 mode"

Worker function for TARGET_MD_ASM_ADJUST , while in thumb1 mode . Unlike the arm version , we do NOT implement asm flag outputs .


<s> void AArch64PassConfig :: addPreSched2 ( ) { addPass ( createAArch64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void ELFAArch64AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { const MCSection * Sec = Fixup . getValue ( ) -> FindAssociatedSection ( ) ; const MCSectionELF * SecELF = dyn_cast_or_null < const MCSectionELF > ( Sec ) ; if ( SecELF && SecELF -> getSectionName ( ) == ".eh_frame" ) Value = ByteSwap_32 ( unsigned ( Value ) ) ; } AArch64AsmBackend :: applyFixup ( Fixup , Data , DataSize , Value , IsPCRel ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? support :: endian :: read32le ( Bytes . data ( ) ) : support :: endian :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> int direct_return ( void ) { return ( reload_completed && xstormy16_compute_stack_layout ( ) . frame_size == 0 ) ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> void rs6000_expand_vector_set ( rtx target , rtx val , int elt ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx reg = gen_reg_rtx ( mode ) ; rtx mask , mem , x ; int width = GET_MODE_SIZE ( inner_mode ) ; int i ; if ( VECTOR_MEM_VSX_P ( mode ) && ( mode == V2DFmode || mode == V2DImode ) ) { rtx ( * set_func ) ( rtx , rtx , rtx , rtx ) = ( ( mode == V2DFmode ) ? gen_vsx_set_v2df : gen_vsx_set_v2di ) ; emit_insn ( set_func ( target , target , val , GEN_INT ( elt ) ) ) ; return ; } if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( inner_mode ) && elt == 0 ) { emit_move_insn ( target , gen_lowpart ( mode , val ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , 0 ) , val ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , reg , mem ) , x ) ) ) ; mask = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( 16 ) ) ; for ( i = 0 ; i < 16 ; ++ i ) XVECEXP ( mask , 0 , i ) = GEN_INT ( i ) ; for ( i = 0 ; i < width ; ++ i ) XVECEXP ( mask , 0 , elt * width + i ) = GEN_INT ( i + 0x10 ) ; x = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( mask , 0 ) ) ; if ( BYTES_BIG_ENDIAN ) x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , target , reg , force_reg ( V16QImode , x ) ) , UNSPEC_VPERM ) ; else { rtx notx = gen_rtx_NOT ( V16QImode , force_reg ( V16QImode , x ) ) ; rtx iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; rtx tmp = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , iorx ) ) ; x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , reg , target , tmp ) , UNSPEC_VPERM ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } </s>


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += "prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "min-legal-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "min-legal-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += "min-legal-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : "+soft-float," ; Key += FS ; FS = Key . substr ( FSStart ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , MaybeAlign ( Options . StackAlignmentOverride ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMicroMipsSizeReductionPass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsBranchExpansion ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'T' : return C_RegisterClass ; case 'U' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static bool sparc_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = SPARC_ICC_REG ; * p2 = SPARC_FCC_REG ; return true ; } </s>


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
VReg
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
MF
.
getDataLayout
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
if
(
!
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
)
{
MIRBuilder
.
buildUnmerge
(
Regs
,
VReg
)
;
}
)
)
return
false
;
OutgoingValueHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
RetCC_X86
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> CSKYTargetLowering :: ConstraintType CSKYTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'a' : case 'b' : case 'v' : case 'w' : case 'y' : return C_RegisterClass ; case 'c' : case 'l' : case 'h' : case 'z' : return C_Register ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


<s> virtual const ARMFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> TargetLowering :: ConstraintWeight AArch64TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : case 'y' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; case 'U' : if ( parsePredicateConstraint ( constraint ) != PredicateConstraint :: Invalid ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Del Useless jmp"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int mips_move_from_gpr_cost ( reg_class_t to ) { switch ( to ) { case M16_REGS : case GENERAL_REGS : return 2 ; case ACC_REGS : return 6 ; case FP_REGS : return 4 ; case COP0_REGS : case COP2_REGS : case COP3_REGS : return 5 ; default : return 0 ; } } </s>

Return the cost of moving a value from a GPR to a register of class TO . Return 0 for classes that are unions of other classes handled by this function .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> unsigned MipsAsmParser :: checkEarlyTargetMatchPredicate ( MCInst & Inst , const OperandVector & Operands ) { switch ( Inst . getOpcode ( ) ) { default : return Match_Success ; case Mips :: DATI : case Mips :: DAHI : if ( static_cast < MipsOperand & > ( * Operands [ 1 ] ) . isValidForTie ( static_cast < MipsOperand & > ( * Operands [ 2 ] ) ) ) return Match_Success ; return Match_RequiresSameSrcAndDst ; } } </s>

Validate the instruction match against any complex target predicates before rendering any operands to it .

Mips Mips Mips::DATI Mips::DAHI Mips 1 Mips 2


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) Changed |= processBlock ( B ) ; return Changed ; } </s>


<s> bool PPCQPXLoadSplat :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; bool MadeChange = false ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( auto MFI = MF . begin ( ) , MFIE = MF . end ( ) ; MFI != MFIE ; ++ MFI ) { MachineBasicBlock * MBB = & * MFI ; SmallVector < MachineInstr * , 4 > Splats ; for ( auto MBBI = MBB -> rbegin ( ) ; MBBI != MBB -> rend ( ) ; ++ MBBI ) { MachineInstr * MI = & * MBBI ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isCall ( ) ) { Splats . clear ( ) ; continue ; } for ( auto SI = Splats . begin ( ) ; SI != Splats . end ( ) ; ) { MachineInstr * SMI = * SI ; unsigned SplatReg = SMI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = SMI -> getOperand ( 1 ) . getReg ( ) ; if ( MI -> modifiesRegister ( SrcReg , TRI ) ) { switch ( MI -> getOpcode ( ) ) { default : SI = Splats . erase ( SI ) ; continue ; case PPC :: LFS : case PPC :: LFD : case PPC :: LFSU : case PPC :: LFDU : case PPC :: LFSUX : case PPC :: LFDUX : case PPC :: LFSX : case PPC :: LFDX : case PPC :: LFIWAX : case PPC :: LFIWZX : if ( SplatReg != SrcReg ) { unsigned SubRegIndex = TRI -> getSubRegIndex ( SrcReg , MI -> getOperand ( 0 ) . getReg ( ) ) ; unsigned SplatSubReg = TRI -> getSubReg ( SplatReg , SubRegIndex ) ; MI -> getOperand ( 0 ) . setReg ( SplatSubReg ) ; MI -> substituteRegister ( SrcReg , SplatReg , 0 , * TRI ) ; } SI = Splats . erase ( SI ) ; ++ MBBI ; SMI -> eraseFromParent ( ) ; -- MBBI ; ++ NumSimplified ; MadeChange = true ; continue ; } } if ( MI -> modifiesRegister ( SplatReg , TRI ) || ( SrcReg != SplatReg && MI -> readsRegister ( SplatReg , TRI ) ) ) { SI = Splats . erase ( SI ) ; continue ; } ++ SI ; } if ( MI -> getOpcode ( ) != PPC :: QVESPLATI && MI -> getOpcode ( ) != PPC :: QVESPLATIs && MI -> getOpcode ( ) != PPC :: QVESPLATIb ) continue ; if ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) continue ; if ( ! MI -> getOperand ( 1 ) . isKill ( ) ) continue ; Splats . push_back ( MI ) ; } } return MadeChange ; } </s>


<s> bool X86TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . hasSSE2 ( ) ) { PM . add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT , Subtarget -> hasAVX ( ) ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget ) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKH_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> rtx xstormy16_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode ; mode = TYPE_MODE ( valtype ) ; PROMOTE_MODE ( mode , 0 , valtype ) ; return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ; } </s>


<s> static unsigned HOST_WIDE_INT arm_shift_truncation_mask ( enum machine_mode mode ) { return mode == SImode ? 255 : 0 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK . SImode shifts use normal ARM insns and therefore guarantee that the shift count is modulo 256 . DImode shifts ( those implemented by lib1funcs.asm or by optabs.c ) guarantee no particular behavior for out-of-range counts .


<s> static void loongarch_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { HOST_WIDE_INT rounded_size ; HOST_WIDE_INT interval ; if ( flag_stack_clash_protection ) interval = STACK_CLASH_PROTECTION_GUARD_SIZE ; else interval = PROBE_INTERVAL ; rtx r12 = LARCH_PROLOGUE_TEMP2 ( Pmode ) ; rtx r14 = LARCH_PROLOGUE_TEMP3 ( Pmode ) ; size = size + first ; gcc_assert ( first <= 16384 ) ; rounded_size = ROUND_DOWN ( size , interval ) ; emit_move_insn ( r14 , GEN_INT ( interval ) ) ; if ( rounded_size != 0 ) { if ( rounded_size <= STACK_CLASH_MAX_UNROLL_PAGES * interval ) { for ( HOST_WIDE_INT i = 0 ; i < rounded_size ; i += interval ) { emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; emit_move_insn ( gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ) , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } dump_stack_clash_frame_info ( PROBE_INLINE , size != rounded_size ) ; } else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , stack_pointer_rtx , stack_pointer_rtx , r12 , r14 ) ) ; emit_insn ( gen_blockage ( ) ) ; dump_stack_clash_frame_info ( PROBE_LOOP , size != rounded_size ) ; } } else dump_stack_clash_frame_info ( NO_PROBE_SMALL_FRAME , true ) ; if ( size != rounded_size ) { if ( size - rounded_size >= 2048 ) { emit_move_insn ( r14 , GEN_INT ( size - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; } else emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( rounded_size - size ) ) ) ) ; } if ( first ) { emit_move_insn ( r12 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , r12 ) ) ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


Store the specified register of the given register class to the specified stack frame index .


<s> bool MipsSEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> unsigned DLXMachineFunctionInfo :: getGlobalBaseReg ( ) { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
static
void
pa_output_pic_pcrel_sequence
(
rtx
*
operands
)
{
gcc_assert
(
SYMBOL_REF_P
(
operands
[
0
]
)
||
LABEL_P
(
operands
[
0
]
)
)
;
if
(
TARGET_PA_20
)
{
if
(
TARGET_SOM
||
!
TARGET_GAS
)
{
operands
[
3
]
=
gen_label_rtx
(
)
;
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
operands
[
3
]
)
)
;
output_asm_insn
(
"mfia %1"
,
operands
)
;
output_asm_insn
(
"addil L'%0-%l3,%1"
,
operands
)
;
output_asm_insn
(
"ldo R'%0-%l3(%%r1),%2"
,
operands
)
;
}
else
{
output_asm_insn
(
"mfia %1"
,
operands
)
;
output_asm_insn
(
"addil L'%0-$PIC_pcrel$0+12,%1"
,
operands
)
;
output_asm_insn
(
"ldo R'%0-$PIC_pcrel$0+16(%%r1),%2"
,
operands
)
;
}
}
else
{
output_asm_insn
(
"{bl|b,l} .+8,%1"
,
operands
)
;
if
(
TARGET_SOM
||
!
TARGET_GAS
)
{
operands
[
3
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"addil L'%0-%l3,%1"
,
operands
)
;
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
operands
[
3
]
)
)
;
output_asm_insn
(
"ldo R'%0-%l3(%%r1),%2"
,
operands
)
;
}
else
{
output_asm_insn
(
"addil L'%0-$PIC_pcrel$0+4,%1"
,
operands
)
;
output_asm_insn
(
"ldo R'%0-$PIC_pcrel$0+8(%%r1),%2"
,
operands
)
;
}
}
}
</s>

Output a PIC pc-relative instruction sequence to load the address of OPERANDS [ 0 ] to register OPERANDS [ 2 ] . OPERANDS [ 0 ] is a symbol ref or a code label . OPERANDS [ 1 ] specifies the register to use to load the program counter . OPERANDS [ 3 ] may be used for label generation The sequence is always three instructions in length . The program counter recorded for PA 1.X is eight bytes more than that for PA 2.0 . Register % r1 is clobbered .


<s> static bool xstormy16_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilderBase & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntValTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( Val -> getType ( ) ) ) ; Val = Builder . CreateBitCast ( Val , IntValTy ) ; return Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> unsigned PPCTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed , const Instruction * I ) { if ( ID == Intrinsic :: bswap && ST -> hasP9Vector ( ) ) return TLI -> getTypeLegalizationCost ( DL , RetTy ) . first ; return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed , I ) ; } </s>

PowerPC PPC Intrinsic::ID Intrinsic::bswap


<s> static bool mips_get_unaligned_mem ( rtx op , HOST_WIDE_INT width , HOST_WIDE_INT bitpos , rtx * left , rtx * right ) { rtx first , last ; if ( width != 32 && ( ! TARGET_64BIT || width != 64 ) ) return false ; if ( bitpos % BITS_PER_UNIT != 0 ) return false ; if ( MEM_ALIGN ( op ) >= width ) return false ; first = adjust_address ( op , QImode , 0 ) ; last = adjust_address ( op , QImode , width / BITS_PER_UNIT - 1 ) ; if ( TARGET_BIG_ENDIAN ) * left = first , * right = last ; else * left = last , * right = first ; return true ; } </s>

Return true if it is possible to use left/right accesses for a bitfield of WIDTH bits starting BITPOS bits into * OP . When returning true , update * OP , * LEFT and * RIGHT as follows : * OP is a BLKmode reference to the whole field . * LEFT is a QImode reference to the first byte if big endian or the last byte if little endian . This address can be used in the left-side instructions ( lwl , swl , ldl , sdl ) . * RIGHT is a QImode reference to the opposite end of the field and can be used in the patterning right-side instruction .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 DAG->DAG Instruction Selection"
;
}
</s>


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static rtx ix86_expand_binop_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat , xops [ 3 ] ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( GET_MODE ( op1 ) == SImode && mode1 == TImode ) { rtx x = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_loadd ( x , op1 ) ) ; op1 = gen_lowpart ( TImode , x ) ; } gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; xops [ 0 ] = target ; xops [ 1 ] = op0 ; xops [ 2 ] = op1 ; if ( tmode == mode0 && tmode == mode1 ) { target = ix86_fixup_binary_operands ( UNKNOWN , tmode , xops ) ; op0 = xops [ 1 ] ; op1 = xops [ 2 ] ; } else if ( optimize || ! ix86_binary_operator_ok ( UNKNOWN , tmode , xops ) ) { op0 = force_reg ( mode0 , op0 ) ; op1 = force_reg ( mode1 , op1 ) ; target = gen_reg_rtx ( tmode ) ; } pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of binop insns .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
Subtarget
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
IndirectTlsSegRefs
=
MF
.
getFunction
(
)
.
hasFnAttribute
(
"indirect-tls-seg-refs"
)
;
OptForSize
=
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
OptForMinSize
=
MF
.
getFunction
(
)
.
hasMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
return
true
;
}
</s>


<s>
MCSymbol
*
TeeRISCMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .

TeeRISC
TeeRISC
"Unknown target flag on GV operand"
0


<s> static bool callee_saved_regno_p ( int regno ) { if ( ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; switch ( regno ) { case HARD_FRAME_POINTER_REGNUM : return frame_pointer_needed ; case LR_REGNUM : return ( frame_pointer_needed || ! crtl -> is_leaf || crtl -> uses_pic_offset_table || df_regs_ever_live_p ( regno ) ) ; case HW_TO_GCC_REGNO ( 25 ) : case HW_TO_GCC_REGNO ( 27 ) : case HW_TO_GCC_REGNO ( 29 ) : case HW_TO_GCC_REGNO ( 31 ) : return crtl -> calls_eh_return ; default : return false ; } } </s>

Returns true if REGNO must be saved for the current function .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned ARMCodeEmitter :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) { if ( MO . isReg ( ) ) return ARMRegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , ARM :: reloc_arm_branch , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , ARM :: reloc_arm_branch ) ; else if ( MO . isCPI ( ) ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Reloc = ( ( TID . TSFlags & ARMII :: FormMask ) == ARMII :: VFPLdStFrm ) ? ARM :: reloc_arm_vfp_cp_entry : ARM :: reloc_arm_cp_entry ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , ARM :: reloc_arm_relative ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , ARM :: reloc_arm_branch ) ; else { errs ( ) << MO ; llvm_unreachable ( 0 ) ; } return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


"constant argument out of range for %qs"

Return true if OPVAL can be used for operand OPNUM of instruction ICODE . The instruction should require a constant operand of some sort . The function prints an error if OPVAL is not valid .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 5 - HasFP ; } case ARM :: GPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; bool IsPagerando = MF . getFunction ( ) . isPagerando ( ) ; return 10 - HasFP - ( STI . isR9Reserved ( ) || IsPagerando ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
while
(
!
vec_safe_is_empty
(
branch_islands
)
)
{
branch_island
*
bi
=
&
branch_islands
->
last
(
)
;
const
char
*
label
=
IDENTIFIER_POINTER
(
bi
->
label_name
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
bi
->
function_name
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
if
(
flag_pic
)
{
if
(
TARGET_LINK_STACK
)
{
char
name
[
32
]
;
get_ppc476_thunk_name
(
name
)
;
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbl "
)
;
strcat
(
tmp_buf
,
name
)
;
strcat
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
}
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\nlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
branch_islands
->
pop
(
)
;
}
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; Register SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { Register Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> bool isLegalMaskedGather ( Type * DataType ) { return ST -> hasSVE ( ) ; } </s>

Return true if the target supports masked gather .


<s> static int loongarch_fp_mult_cost ( machine_mode mode ) { return mode == DFmode ? loongarch_cost -> fp_mult_df : loongarch_cost -> fp_mult_sf ; } </s>

Return the cost of floating-point multiplications of mode MODE .


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> size_t AArch64LongBranchStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


"relaxInstruction is not implemented yet"

Relax the instruction in the given fragment to the next wider instruction .


<s> bool AArch64CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; for ( auto & OrigArg : OrigArgs ) { splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildExtract ( Regs , Offsets , OrigArg . Reg ) ; } ) ; } const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * CallAssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? AArch64 :: BLR : AArch64 :: BL ) ; MIB . addOperand ( Callee ) ; auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; SmallVector < unsigned , 8 > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! handleAssignments ( MIRBuilder , CallAssignFn , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( 0 ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee . getReg ( ) , 0 ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , 8 > RegOffsets ; SmallVector < unsigned , 8 > SplitRegs ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { std :: copy ( Offsets . begin ( ) , Offsets . end ( ) , std :: back_inserter ( RegOffsets ) ) ; std :: copy ( Regs . begin ( ) , Regs . end ( ) , std :: back_inserter ( SplitRegs ) ) ; } ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! handleAssignments ( MIRBuilder , RetAssignFn , SplitArgs , Handler ) ) return false ; if ( ! RegOffsets . empty ( ) ) MIRBuilder . buildSequence ( OrigRet . Reg , SplitRegs , RegOffsets ) ; } return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> static void desc_prologue ( int body , unw_word rlen , unsigned char mask , unsigned char grsave , struct unw_state_record * sr ) { int i ; if ( ! ( sr -> in_body || sr -> first_region ) ) finish_prologue ( sr ) ; sr -> first_region = 0 ; if ( sr -> when_target < sr -> region_start + sr -> region_len ) { sr -> done = 1 ; return ; } for ( i = 0 ; i < sr -> epilogue_count ; ++ i ) pop ( sr ) ; sr -> epilogue_count = 0 ; sr -> epilogue_start = UNW_WHEN_NEVER ; if ( ! body ) push ( sr ) ; sr -> region_start += sr -> region_len ; sr -> region_len = rlen ; sr -> in_body = body ; if ( ! body ) { for ( i = 0 ; i < 4 ; ++ i ) { if ( mask & 0x8 ) set_reg ( sr -> curr . reg + save_order [ i ] , UNW_WHERE_GR , sr -> region_start + sr -> region_len - 1 , grsave ++ ) ; mask <<= 1 ; } sr -> gr_save_loc = grsave ; sr -> any_spills = 0 ; sr -> imask = 0 ; sr -> spill_offset = 0x10 ; } } </s>


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( ) ; } </s>


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s>
const
MCFixupKindInfo
&
SICAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SIC
::
NumTargetFixupKinds
]
=
{
{
"fixup_SIC_32"
,
0
,
32
,
0
}
,
{
"fixup_SIC_HI16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_LO16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_GOT"
,
0
,
16
,
0
}
,
{
"fixup_SIC_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_SIC_PC24"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_SIC_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_GOT_HI16"
,
0
,
16
,
0
}
,
{
"fixup_SIC_GOT_LO16"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


"number of supported overflow lines exceeded"

Get the next nonblank , noncomment line , returning 0 on EOF , 1 otherwise .


<s> static void addInst ( MachineInstr * MI ) { Blocks . back ( ) . insert ( MI ) ; PredicatedInsts . emplace ( MI , std :: make_unique < PredicatedMI > ( MI , CurrentPredicates ) ) ; } </s>


<s> static inline bool mips_constant_elt_p ( rtx x ) { return CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE ; } </s>

A subroutine of mips_expand_vec_init , match constant vector elements .


"the ABI of passing C structures with zero-width bit-fields"

Classify the argument of type TYPE and mode MODE . CLASSES will be filled by the register class used to pass each word of the operand . The number of words is returned . In case the parameter should be passed in memory , 0 is returned . As a special case for zero sized containers , classes [ 0 ] will be NO_CLASS and 1 is returned . BIT_OFFSET is used internally for handling records and specifies offset of the offset in bits modulo 256 to avoid overflow cases . See the x86-64 PS ABI for details .


<s>
SDValue
SparcTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Sparc32
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createFISCELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"ARM PIC Global Base Reg Initialization"

getPassName - Return a nice clean name for a pass .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>


<s> bool MipsAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> bool PPCFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ) return false ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( GuaranteedTailCallOpt && MF . getInfo < PPCFunctionInfo > ( ) -> hasFastCall ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool areOnlyUsersOf ( SDNode * N , ArrayRef < SDValue > ValidUsers ) { for ( SDNode :: use_iterator I = N -> use_begin ( ) , E = N -> use_end ( ) ; I != E ; ++ I ) if ( llvm :: all_of ( ValidUsers , [ & I ] ( SDValue V ) { return V . getNode ( ) != * I ; } ) ) return false ; return true ; } </s>

Return true if all the users of N are contained in Nodes .


<s> int mve_struct_mem_operand ( rtx op ) { rtx ind = XEXP ( op , 0 ) ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( GET_CODE ( ind ) == POST_INC ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; return FALSE ; } </s>

Return TRUE if OP is a mem suitable for loading/storing an MVE struct type .


<s> TargetPassConfig * ARMBaseTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new ARMPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void SystemZXPLINKFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void do_dispatch ( rtx_insn * insn , int mode ) { if ( mode == DISPATCH_INIT ) init_dispatch_sched ( ) ; else if ( mode == ADD_TO_DISPATCH_WINDOW ) add_to_dispatch_window ( insn ) ; } </s>

This routine is the driver of the dispatch scheduler .


<s> bool ARMTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn ( CallConv , isVarArg ) ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> unsigned getPrefetchDistance ( ) const override { return 4500 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> bool AArch64LowerHomogeneousPrologEpilog :: runOnModule ( Module & M ) { if ( skipModule ( M ) ) return false ; MachineModuleInfo * MMI = & getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return AArch64LowerHomogeneousPE ( & M , MMI ) . run ( ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
ARM_AAPCS_VFP
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s> static void mips_add_cfa_restore ( rtx reg ) { mips_epilogue . cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , reg , mips_epilogue . cfa_restores ) ; } </s>

Record that the epilogue has restored call-saved register REG .


<s> bool ARMAsmParser :: ParseInstruction ( const StringRef & Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { OwningPtr < ARMOperand > Op ; ARMOperand :: CreateToken ( Op , Name , NameLoc ) ; Operands . push_back ( Op . take ( ) ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { OwningPtr < ARMOperand > Op ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( Op . take ( ) ) ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( Op . take ( ) ) ; } } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> bool symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return true ; } return false ; } </s>

Return true if OP contains a symbol reference


<s> void umips_output_load_store_pair ( bool load_p , rtx * operands ) { rtx reg1 , reg2 , mem1 , mem2 ; if ( load_p ) { reg1 = operands [ 0 ] ; reg2 = operands [ 2 ] ; mem1 = operands [ 1 ] ; mem2 = operands [ 3 ] ; } else { reg1 = operands [ 1 ] ; reg2 = operands [ 3 ] ; mem1 = operands [ 0 ] ; mem2 = operands [ 2 ] ; } if ( REGNO ( reg2 ) == REGNO ( reg1 ) + 1 ) { umips_output_load_store_pair_1 ( load_p , reg1 , mem1 ) ; return ; } gcc_assert ( REGNO ( reg1 ) == REGNO ( reg2 ) + 1 ) ; umips_output_load_store_pair_1 ( load_p , reg2 , mem2 ) ; } </s>

Output the assembly instruction for a microMIPS LWP or SWP instruction . LOAD_P and OPERANDS are as for umips_load_store_pair_p .


<s> static unsigned rs6000_adjust_vect_cost_per_stmt ( enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info ) { if ( kind == scalar_stmt && stmt_info && stmt_info -> stmt && gimple_code ( stmt_info -> stmt ) == GIMPLE_ASSIGN ) { tree_code subcode = gimple_assign_rhs_code ( stmt_info -> stmt ) ; if ( subcode == COND_EXPR ) return 2 ; } return 0 ; } </s>

Adjust vectorization cost after calling rs6000_builtin_vectorization_cost . For some statement , we would like to further fine-grain tweak the cost on top of rs6000_builtin_vectorization_cost handling which does n't have any information on statement operation codes etc . One typical case here is COND_EXPR , it takes the same cost to simple FXU instruction when evaluating for scalar cost , but it should be priced more whatever transformed to either compare + branch or compare + isel instructions .


<s>
DecodeStatus
AArch64Disassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
Size
=
0
;
if
(
Bytes
.
size
(
)
<
4
)
return
Fail
;
Size
=
4
;
uint32_t
Insn
=
(
Bytes
[
3
]
<<
24
)
|
(
Bytes
[
2
]
<<
16
)
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
0
]
<<
0
)
;
const
uint8_t
*
Tables
[
]
=
{
DecoderTable32
,
DecoderTableFallback32
}
;
for
(
auto
Table
:
Tables
)
{
DecodeStatus
Result
=
decodeInstruction
(
Table
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDR_ZA
:
case
AArch64
::
STR_ZA
:
{
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZA
)
)
;
const
MCOperand
&
Imm4Op
=
MI
.
getOperand
(
2
)
;
assert
(
Imm4Op
.
isImm
(
)
&&
"Unexpected operand type!"
)
;
MI
.
addOperand
(
Imm4Op
)
;
break
;
}
case
AArch64
::
LD1_MXIPXX_H_B
:
case
AArch64
::
LD1_MXIPXX_V_B
:
case
AArch64
::
ST1_MXIPXX_H_B
:
case
AArch64
::
ST1_MXIPXX_V_B
:
case
AArch64
::
INSERT_MXIPZ_H_B
:
case
AArch64
::
INSERT_MXIPZ_V_B
:
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
EXTRACT_ZPMXI_H_B
:
case
AArch64
::
EXTRACT_ZPMXI_V_B
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
SMOVvi8to32_idx0
:
case
AArch64
::
SMOVvi8to64_idx0
:
case
AArch64
::
SMOVvi16to32_idx0
:
case
AArch64
::
SMOVvi16to64_idx0
:
case
AArch64
::
SMOVvi32to64_idx0
:
case
AArch64
::
UMOVvi8_idx0
:
case
AArch64
::
UMOVvi16_idx0
:
case
AArch64
::
UMOVvi32_idx0
:
case
AArch64
::
UMOVvi64_idx0
:
MI
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
break
;
}
if
(
Result
!=
MCDisassembler
::
Fail
)
return
Result
;
}
return
MCDisassembler
::
Fail
;
}
</s>

Returns the disassembly of a single instruction .


<s> static rtx aarch64_gen_load_pair ( machine_mode mode , rtx reg1 , rtx mem1 , rtx reg2 , rtx mem2 ) { switch ( mode ) { case DImode : return gen_load_pairdi ( reg1 , mem1 , reg2 , mem2 ) ; case DFmode : return gen_load_pairdf ( reg1 , mem1 , reg2 , mem2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and regurn a load pair isntruction of mode MODE to load register REG1 from MEM1 and register REG2 from MEM2 .


<s> static void core2i7_first_cycle_multipass_fini ( void * _data ) { ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; if ( data -> ready_try_change ) { sbitmap_free ( data -> ready_try_change ) ; data -> ready_try_change = NULL ; data -> ready_try_change_size = 0 ; } } </s>


<s> bool invalid_e500_subreg ( rtx op , machine_mode mode ) { if ( TARGET_E500_DOUBLE ) { if ( GET_CODE ( op ) == SUBREG && ( mode == SImode || mode == DImode || mode == TImode || mode == DDmode || mode == TDmode || mode == PTImode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DFmode || GET_MODE ( SUBREG_REG ( op ) ) == TFmode || GET_MODE ( SUBREG_REG ( op ) ) == IFmode || GET_MODE ( SUBREG_REG ( op ) ) == KFmode ) ) return true ; if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode || mode == IFmode || mode == KFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ; } if ( TARGET_SPE && GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && SPE_VECTOR_MODE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) return true ; return false ; } </s>

Return TRUE if OP is an invalid SUBREG operation on the e500 .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMipsELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> rtx aarch64_eh_return_handler_rtx ( void ) { rtx tmp = gen_frame_mem ( Pmode , plus_constant ( Pmode , hard_frame_pointer_rtx , UNITS_PER_WORD ) ) ; MEM_VOLATILE_P ( tmp ) = true ; return tmp ; } </s>

Implement EH_RETURN_HANDLER_RTX . EH returns need to either return normally or return to a previous frame after unwinding . An EH return uses a single shared return sequence . The epilogue is exactly like a normal epilogue except that it has an extra input register ( EH_RETURN_STACKADJ_RTX ) which contains the stack adjustment that must be applied after the frame has been destroyed . An extra label is inserted before the epilogue which initializes this register to zero , and this is the entry point for a normal return . An actual EH return updates the return address , initializes the stack adjustment and jumps directly into the epilogue ( bypassing the zeroing of the adjustment ) . Since the return address is typically saved on the stack when a function makes a call , the saved LR must be updated outside the epilogue . This poses problems as the store is generated well before the epilogue , so the offset of LR is not known yet . Also optimizations will remove the store as it appears dead , even after the epilogue is generated ( as the base or offset for loading LR is different in many cases ) . To avoid these problems this implementation forces the frame pointer in eh_return functions so that the location of LR is fixed and known early . It also marks the store volatile , so no optimization is permitted to remove the store .


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const { if ( MInfo . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: TCRETURNdi ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) . addImm ( 0 ) ) ; return It ; } if ( MInfo . CallConstructionID == MachineOutlinerNoLRSave || MInfo . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR , RegState :: Define ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return CallPt ; } </s>

Insert a call to an outlined function into the program .


<s> static bool expand_vec_perm_broadcast ( struct expand_vec_perm_d * d ) { unsigned i , elt , nelt = d -> nelt ; unsigned char perm2 [ 2 ] ; rtx temp ; bool ok ; if ( ! d -> one_operand_p ) return false ; elt = d -> perm [ 0 ] ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; switch ( d -> vmode ) { case E_V2SImode : case E_V2SFmode : perm2 [ 0 ] = elt ; perm2 [ 1 ] = elt + 2 ; ok = expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , perm2 , 2 ) ; gcc_assert ( ok ) ; break ; case E_V8QImode : if ( BYTES_BIG_ENDIAN ) elt = 7 - elt ; elt *= BITS_PER_UNIT ; temp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_extzv ( temp , gen_lowpart ( DImode , d -> op0 ) , GEN_INT ( 8 ) , GEN_INT ( elt ) ) ) ; emit_insn ( gen_mux1_brcst_qi ( d -> target , gen_lowpart ( QImode , temp ) ) ) ; break ; case E_V4HImode : default : gcc_unreachable ( ) ; } return true ; } </s>


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool AArch64VectorByElementOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const AArch64InstrInfo * AAII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( ST . getSchedModel ( ) , & ST , AAII ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; if ( earlyExitVectElement ( & MF ) ) return false ; bool Changed = false ; std :: map < unsigned , bool > VecInstElemTable ; SmallVector < MachineInstr * , 8 > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ; if ( optimizeVectElement ( MI , & VecInstElemTable ) ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } ++ MII ; } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86TargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86MaxStackAlignmentHeuristicPass ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static unsigned int sparc_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( regno == SPARC_GSR_REG ) return 1 ; if ( TARGET_ARCH64 ) { if ( SPARC_INT_REG_P ( regno ) || regno == FRAME_POINTER_REGNUM ) return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; return CEIL ( GET_MODE_SIZE ( mode ) , 4 ) ; } return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . On SPARC , ordinary registers hold 32 bits worth ; this means both integer and floating point registers . On v9 , integer regs hold 64 bits worth ; floating point regs hold 32 bits worth ( this includes the new fp regs as even the odd ones are included in the hard register count ) .


<s> rsqrte_type get_rsqrte_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrte_df2 ; case SFmode : return gen_aarch64_rsqrte_sf2 ; case V2DFmode : return gen_aarch64_rsqrte_v2df2 ; case V2SFmode : return gen_aarch64_rsqrte_v2sf2 ; case V4SFmode : return gen_aarch64_rsqrte_v4sf2 ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root initial estimate insn depending on machine mode .


<s> bool pa_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( int_size_in_bytes ( type ) > ( TARGET_64BIT ? 16 : 8 ) || int_size_in_bytes ( type ) <= 0 ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


Expand a builtin . These builtins are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the ARM_BUILTIN_DATA record that is passed into the function .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool AArch64CompressJumpTables :: runOnMachineFunction ( MachineFunction & MFIn ) { bool Changed = false ; MF = & MFIn ; const auto & ST = MF -> getSubtarget < AArch64Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ST . force32BitJumpTables ( ) && ! MF -> getFunction ( ) . hasMinSize ( ) ) return false ; if ( ! scanFunction ( ) ) return false ; for ( MachineBasicBlock & MBB : * MF ) { int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes ( MI ) ; } } return Changed ; } </s>


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s> void OR1KAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { auto I = MI -> getIterator ( ) ; auto E = MI -> getParent ( ) -> instr_end ( ) ; do { customEmitInstruction ( & * I ++ ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s>
void
XNCMInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> int ia64_move_ok ( rtx dst , rtx src ) { if ( GET_CODE ( dst ) != MEM ) return 1 ; if ( GET_CODE ( src ) == MEM ) return 0 ; if ( register_operand ( src , VOIDmode ) ) return 1 ; if ( INTEGRAL_MODE_P ( GET_MODE ( dst ) ) ) return src == const0_rtx ; else return satisfies_constraint_G ( src ) ; } </s>

Return 1 if the operands of a move are ok .


<s> static machine_mode rs6000_c_mode_for_suffix ( char suffix ) { if ( TARGET_FLOAT128_TYPE ) { if ( suffix == 'q' || suffix == 'Q' ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; } return VOIDmode ; } </s>