<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineInstr
*
MI
=
I
;
if
(
!
MI
->
isFullCopy
(
)
)
continue
;
MachineOperand
&
DstMO
=
MI
->
getOperand
(
0
)
;
MachineOperand
&
SrcMO
=
MI
->
getOperand
(
1
)
;
if
(
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
!
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
SrcRC
=
IsVRReg
(
SrcMO
.
getReg
(
)
,
MRI
)
&
PPC
::
VSHRCRegClass
:
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVRReg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown source for a VSX copy"
)
;
unsigned
NewVReg
=
MRI
.
createVirtualRegister
(
SrcRC
)
;
BuildMI
(
MBB
,
MI
,
MI
->
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
SUBREG_TO_REG
)
,
NewVReg
)
.
addImm
(
1
)
.
addOperand
(
SrcMO
)
.
addImm
(
IsVRReg
(
SrcMO
.
getReg
(
)
,
MRI
)
PPC
::
sub_128
:
PPC
::
sub_64
)
;
SrcMO
.
setReg
(
NewVReg
)
;
}
else
if
(
!
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
DstRC
=
IsVRReg
(
DstMO
.
getReg
(
)
,
MRI
)
&
PPC
::
VSHRCRegClass
:
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVRReg
(
DstMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown destination for a VSX copy"
)
;
unsigned
NewVReg
=
MRI
.
createVirtualRegister
(
DstRC
)
;
BuildMI
(
MBB
,
MI
,
MI
->
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
NewVReg
)
.
addOperand
(
SrcMO
)
;
SrcMO
.
setReg
(
NewVReg
)
;
SrcMO
.
setSubReg
(
IsVRReg
(
DstMO
.
getReg
(
)
,
MRI
)
PPC
::
sub_128
:
PPC
::
sub_64
)
;
}
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


"parameter passing for argument of type "

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; if ( ! ISA_HAS_LWL_LWR ) bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; else { if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; } mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , 0 , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s> insn_code function_expander :: direct_optab_handler_for_sign ( optab signed_op , optab unsigned_op , unsigned int suffix_i , machine_mode mode ) { if ( mode == VOIDmode ) mode = vector_mode ( suffix_i ) ; optab op = type_suffix ( suffix_i ) . unsigned_p ? unsigned_op : signed_op ; return :: direct_optab_handler ( op , mode ) ; } </s>

Choose between signed and unsigned direct optabs SIGNED_OP and UNSIGNED_OP based on the signedness of type suffix SUFFIX_I , then pick the appropriate optab handler for the mode . Use MODE as the mode if given , otherwise use the mode of type suffix SUFFIX_I .


<s> static void choose_basereg ( HOST_WIDE_INT cfa_offset , rtx & base_reg , HOST_WIDE_INT & base_offset , unsigned int align_reqested , unsigned int * align ) { const struct machine_function * m = cfun -> machine ; unsigned int hfp_align ; unsigned int drap_align ; unsigned int sp_align ; bool hfp_ok = fp_valid_at ( cfa_offset ) ; bool drap_ok = m -> fs . drap_valid ; bool sp_ok = sp_valid_at ( cfa_offset ) ; hfp_align = drap_align = sp_align = INCOMING_STACK_BOUNDARY ; if ( align_reqested ) { if ( m -> fs . realigned ) hfp_align = drap_align = sp_align = crtl -> stack_alignment_needed ; else if ( m -> fs . sp_realigned ) sp_align = crtl -> stack_alignment_needed ; hfp_ok = hfp_ok && hfp_align >= align_reqested ; drap_ok = drap_ok && drap_align >= align_reqested ; sp_ok = sp_ok && sp_align >= align_reqested ; } if ( m -> use_fast_prologue_epilogue ) { if ( hfp_ok ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( drap_ok ) { base_reg = crtl -> drap_reg ; base_offset = 0 - cfa_offset ; } else if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = 16 , tlen ; if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( drap_ok ) { toffset = 0 - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( hfp_ok ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; len = tlen ; } } } if ( align ) { if ( base_reg == stack_pointer_rtx ) * align = sp_align ; else if ( base_reg == crtl -> drap_reg ) * align = drap_align ; else if ( base_reg == hard_frame_pointer_rtx ) * align = hfp_align ; } } </s>

Choose a base register based upon alignment requested , speed and/or size .


<s> static const char * i386_find_on_wrapper_list ( const char * target ) { static char first_time = 1 ; static hash_table < wrapped_symbol_hasher > * wrappers ; if ( first_time ) { static char wrapper_list_buffer [ ] = CXX_WRAP_SPEC_LIST ; char * bufptr ; wrappers = new hash_table < wrapped_symbol_hasher > ( 8 ) ; for ( bufptr = wrapper_list_buffer ; * bufptr ; ++ bufptr ) { char * found = NULL ; if ( ISSPACE ( * bufptr ) ) continue ; if ( * bufptr == '_' ) found = bufptr ; while ( * bufptr && ! ISSPACE ( * bufptr ) ) ++ bufptr ; if ( * bufptr ) * bufptr = 0 ; if ( found ) * wrappers -> find_slot ( found , INSERT ) = found ; } first_time = 0 ; } return wrappers -> find ( target ) ; } </s>

Search for a function named TARGET in the list of library wrappers we are using , returning a pointer to it if found or NULL if not . This function might be called on quite a few symbols , and we only have the list of names of wrapped functions available to us as a spec string , so first time round we lazily initialise a hash table to make things quicker .


<s> static void store_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx dest , src , basereg ; rtx_insn * insn ; src = gen_rtx_REG ( word_mode , reg ) ; basereg = gen_rtx_REG ( Pmode , base ) ; if ( VAL_14_BITS_P ( disp ) ) { dest = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , basereg , disp ) ) ; insn = emit_move_insn ( dest , src ) ; } else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) { add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } dest = gen_rtx_MEM ( word_mode , tmpreg ) ; insn = emit_move_insn ( dest , src ) ; } else { rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , high ) ; dest = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; insn = emit_move_insn ( dest , src ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( word_mode , basereg , delta ) ) , src ) ) ; } if ( DO_FRAME_NOTES ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit RTL to store REG at the memory location specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns . Note in DISP > 8k case , we will leave the high part of the address in % r1 . There is code in expand_hppa_ { prologue , epilogue } that knows this .


<s> bool rs6000_is_valid_and_mask ( rtx mask , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; if ( mode == DImode ) return ( ne == 0 || nb == 63 || ( nb < 32 && ne <= nb ) ) ; if ( mode == SImode ) return ( nb < 32 && ne < 32 ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwinm , rldicl , or rldicr instruction , to implement an AND with it in mode MODE .


<s> static bool arm_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; bool can_inline = true ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ? caller_tree : target_option_default_node ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ? callee_tree : target_option_default_node ) ; if ( callee_opts == caller_opts ) return true ; struct arm_build_target caller_target ; struct arm_build_target callee_target ; caller_target . isa = sbitmap_alloc ( isa_num_bits ) ; callee_target . isa = sbitmap_alloc ( isa_num_bits ) ; arm_configure_build_target ( & caller_target , caller_opts , false ) ; arm_configure_build_target ( & callee_target , callee_opts , false ) ; if ( ! bitmap_subset_p ( callee_target . isa , caller_target . isa ) ) can_inline = false ; sbitmap_free ( caller_target . isa ) ; sbitmap_free ( callee_target . isa ) ; return can_inline ; } </s>

Hook to determine if one function can safely inline another .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Lanai Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void arm_adjust_block_mem ( rtx mem , HOST_WIDE_INT length , rtx * loop_reg , rtx * loop_mem ) { * loop_reg = copy_addr_to_reg ( XEXP ( mem , 0 ) ) ; * loop_mem = change_address ( mem , BLKmode , * loop_reg ) ; set_mem_align ( * loop_mem , MIN ( MEM_ALIGN ( mem ) , length * BITS_PER_UNIT ) ) ; } </s>

From mips_adjust_block_mem : Helper function for doing a loop-based block operation on memory reference MEM . Each iteration of the loop will operate on LENGTH bytes of MEM . Create a new base register for use within the loop and point it to the start of MEM . Create a new memory reference that uses this register . Store them in * LOOP_REG and * LOOP_MEM respectively .


<s>
TargetTransformInfo
MipsTargetMachine
::
getTargetTransformInfo
(
const
Function
&
F
)
const
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
LLVM_DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
MipsTTIImpl
(
this
,
F
)
)
;
}
</s>

Get a TargetTransformInfo implementation for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"
Mips


"Opcode has no flag setting equivalent!"

Return the opcode that set flags when possible .


<s> HOST_WIDE_INT aarch64_fold_sve_cnt_pat ( aarch64_svpattern pattern , unsigned int nelts_per_vq ) { unsigned int vl , const_vg ; if ( pattern >= AARCH64_SV_VL1 && pattern <= AARCH64_SV_VL8 ) vl = 1 + ( pattern - AARCH64_SV_VL1 ) ; else if ( pattern >= AARCH64_SV_VL16 && pattern <= AARCH64_SV_VL256 ) vl = 16 << ( pattern - AARCH64_SV_VL16 ) ; else if ( aarch64_sve_vg . is_constant ( & const_vg ) ) { unsigned int nelts = ( const_vg / 2 ) * nelts_per_vq ; switch ( pattern ) { case AARCH64_SV_POW2 : return 1 << floor_log2 ( nelts ) ; case AARCH64_SV_MUL4 : return nelts & - 4 ; case AARCH64_SV_MUL3 : return ( nelts / 3 ) * 3 ; case AARCH64_SV_ALL : return nelts ; default : gcc_unreachable ( ) ; } } else return - 1 ; poly_uint64 nelts_all = exact_div ( aarch64_sve_vg , 2 ) * nelts_per_vq ; if ( known_le ( vl , nelts_all ) ) return vl ; if ( known_gt ( vl , nelts_all ) ) return 0 ; return - 1 ; } </s>

Check whether we can calculate the number of elements in PATTERN at compile time , given that there are NELTS_PER_VQ elements per 128-bit block . Return the value if so , otherwise return -1 .


<s> static int get_max_pos ( state_t state ) { if ( cpu_unit_reservation_p ( state , pos_6 ) ) return 6 ; else if ( cpu_unit_reservation_p ( state , pos_5 ) ) return 5 ; else if ( cpu_unit_reservation_p ( state , pos_4 ) ) return 4 ; else if ( cpu_unit_reservation_p ( state , pos_3 ) ) return 3 ; else if ( cpu_unit_reservation_p ( state , pos_2 ) ) return 2 ; else if ( cpu_unit_reservation_p ( state , pos_1 ) ) return 1 ; else return 0 ; } </s>

The following function returns position in the two window bundle for given STATE .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x60000000 ) ; OW -> WriteZeros ( Count % 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void SystemZXPLINKFrameLowering :: inlineStackProbe ( MachineFunction & MF , MachineBasicBlock & PrologMBB ) const { auto * ZII = static_cast < const SystemZInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineInstr * StackAllocMI = nullptr ; for ( MachineInstr & MI : PrologMBB ) if ( MI . getOpcode ( ) == SystemZ :: XPLINK_STACKALLOC ) { StackAllocMI = & MI ; break ; } if ( StackAllocMI == nullptr ) return ; MachineBasicBlock & MBB = PrologMBB ; const DebugLoc DL = StackAllocMI -> getDebugLoc ( ) ; MachineBasicBlock * NextMBB ; MachineBasicBlock * StackExtMBB = MF . CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF . push_back ( StackExtMBB ) ; BuildMI ( StackExtMBB , DL , ZII -> get ( SystemZ :: LG ) , SystemZ :: R3D ) . addReg ( SystemZ :: R3D ) . addImm ( 72 ) . addReg ( 0 ) ; BuildMI ( StackExtMBB , DL , ZII -> get ( SystemZ :: CallBASR_STACKEXT ) ) . addReg ( SystemZ :: R3D ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( SystemZ :: LLGT ) , SystemZ :: R3D ) . addReg ( 0 ) . addImm ( 1208 ) . addReg ( 0 ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( SystemZ :: CG ) ) . addReg ( SystemZ :: R4D ) . addReg ( SystemZ :: R3D ) . addImm ( 64 ) . addReg ( 0 ) ; BuildMI ( MBB , StackAllocMI , DL , ZII -> get ( SystemZ :: BRC ) ) . addImm ( SystemZ :: CCMASK_ICMP ) . addImm ( SystemZ :: CCMASK_CMP_LT ) . addMBB ( StackExtMBB ) ; NextMBB = SystemZ :: splitBlockBefore ( StackAllocMI , & MBB ) ; MBB . addSuccessor ( NextMBB ) ; MBB . addSuccessor ( StackExtMBB ) ; BuildMI ( StackExtMBB , DL , ZII -> get ( SystemZ :: J ) ) . addMBB ( NextMBB ) ; StackExtMBB -> addSuccessor ( NextMBB ) ; StackAllocMI -> eraseFromParent ( ) ; recomputeLiveIns ( * NextMBB ) ; recomputeLiveIns ( * StackExtMBB ) ; } </s>

Replace a StackProbe inline-stub with the actual probe code inline .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> int ia64_depz_field_mask ( rtx rop , rtx rshift ) { unsigned HOST_WIDE_INT op = INTVAL ( rop ) ; unsigned HOST_WIDE_INT shift = INTVAL ( rshift ) ; op >>= shift ; return exact_log2 ( op + 1 ) ; } </s>

Check if OP is a mask suitible for use with SHIFT in a dep.z instruction . Return the length of the field , or < = 0 on failure .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { return createPPCMachineScheduler ( C ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMicroMipsSizeReducePass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsBranchExpansion ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> BitVector VERegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( VE :: SX8 ) ; Reserved . set ( VE :: SX9 ) ; Reserved . set ( VE :: SX10 ) ; Reserved . set ( VE :: SX11 ) ; Reserved . set ( VE :: SX12 ) ; Reserved . set ( VE :: SX13 ) ; Reserved . set ( VE :: SX14 ) ; Reserved . set ( VE :: SX15 ) ; Reserved . set ( VE :: SX16 ) ; Reserved . set ( VE :: SX17 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool mips_pad_arg_upward ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return true ; if ( type != 0 ? ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || FIXED_POINT_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) ) return false ; if ( mips_abi == ABI_O64 ) if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return false ; if ( mips_abi != ABI_EABI ) return true ; if ( mode != BLKmode ) return GET_MODE_BITSIZE ( mode ) >= PARM_BOUNDARY ; else return int_size_in_bytes ( type ) >= ( PARM_BOUNDARY / BITS_PER_UNIT ) ; } </s>

Return true if FUNCTION_ARG_PADDING ( MODE , TYPE ) should return upward rather than downward . In other words , return true if the first byte of the stack slot has useful data , false if the last byte does .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
&
STI
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
->
begin
(
)
,
MLI
->
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void rs6000_split_signbit ( rtx dest , rtx src ) { machine_mode d_mode = GET_MODE ( dest ) ; machine_mode s_mode = GET_MODE ( src ) ; rtx dest_di = ( d_mode == DImode ) ? dest : gen_lowpart ( DImode , dest ) ; rtx shift_reg = dest_di ; gcc_assert ( FLOAT128_IEEE_P ( s_mode ) && TARGET_POWERPC64 ) ; if ( MEM_P ( src ) ) { rtx mem = ( WORDS_BIG_ENDIAN ? adjust_address ( src , DImode , 0 ) : adjust_address ( src , DImode , 8 ) ) ; emit_insn ( gen_rtx_SET ( dest_di , mem ) ) ; } else { unsigned int r = reg_or_subregno ( src ) ; if ( INT_REGNO_P ( r ) ) shift_reg = gen_rtx_REG ( DImode , r + ( BYTES_BIG_ENDIAN == 0 ) ) ; else { gcc_assert ( VSX_REGNO_P ( r ) ) ; if ( s_mode == KFmode ) emit_insn ( gen_signbitkf2_dm2 ( dest_di , src ) ) ; else emit_insn ( gen_signbittf2_dm2 ( dest_di , src ) ) ; } } emit_insn ( gen_lshrdi3 ( dest_di , shift_reg , GEN_INT ( 63 ) ) ) ; return ; } </s>

Split a signbit operation on 64-bit machines with direct move . Also allow for the value to come from memory or if it is already loaded into a GPR .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( TS1AM ) TARGET_NODE_CASE ( VEC_BROADCAST ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER VE


<s> int standard_sse_constant_p ( rtx x ) { machine_mode mode ; if ( ! TARGET_SSE ) return 0 ; mode = GET_MODE ( x ) ; if ( x == const0_rtx || x == CONST0_RTX ( mode ) ) return 1 ; if ( vector_all_ones_operand ( x , mode ) ) switch ( mode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : if ( TARGET_SSE2 ) return 2 ; case V32QImode : case V16HImode : case V8SImode : case V4DImode : if ( TARGET_AVX2 ) return 2 ; case V64QImode : case V32HImode : case V16SImode : case V8DImode : if ( TARGET_AVX512F ) return 2 ; default : break ; } return 0 ; } </s>

Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


<s> const MCPhysReg * SystemZTargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { SystemZ :: R0D , SystemZ :: R1D , SystemZ :: R14D , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> static void ix86_init_platform_type_builtins ( void ) { make_cpu_type_builtin ( "__builtin_cpu_init" , IX86_BUILTIN_CPU_INIT , INT_FTYPE_VOID , false ) ; make_cpu_type_builtin ( "__builtin_cpu_is" , IX86_BUILTIN_CPU_IS , INT_FTYPE_PCCHAR , true ) ; make_cpu_type_builtin ( "__builtin_cpu_supports" , IX86_BUILTIN_CPU_SUPPORTS , INT_FTYPE_PCCHAR , true ) ; } </s>

Make builtins to get CPU type and features supported . The created builtins are : __builtin_cpu_init ( ) , to detect cpu type and features , __builtin_cpu_is ( `` < CPUNAME > '' ) , to check if cpu is of type < CPUNAME > , __builtin_cpu_supports ( `` < FEATURE > '' ) , to check if cpu supports < FEATURE >


<s> static void rs6000_emit_nmsub ( rtx dst , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( dst ) ; rtx r ; gcc_assert ( optab_handler ( fma_optab , mode ) != CODE_FOR_nothing ) ; r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1 , m2 , r ) ; r = gen_rtx_NEG ( mode , r ) ; emit_insn ( gen_rtx_SET ( dst , r ) ) ; } </s>

Generate a FNMSUB instruction : dst = -fma ( m1 , m2 , -a ) .


"lane index must be a constant immediate"

"total size and element size must be a nonzero "

Expand an AArch64 AdvSIMD builtin ( intrinsic ) .


<s> enum direction function_arg_padding ( enum machine_mode mode , tree type ) { if ( TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

Handle the FUNCTION_ARG_PADDING macro . For the 64 bit ABI structs are always stored left shifted in their argument slot .


<s> TargetIRAnalysis PPCTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( PPCTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> int first_fp_reg_to_save ( void ) { int first_reg ; for ( first_reg = 14 + 32 ; first_reg <= 63 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; return first_reg ; } </s>


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"multiple fast interrupt routines seen: %qE and %qE"

Perform any actions necessary before starting to compile FNDECL . For the RX we use this to make sure that we have the correct set of register masks selected . If FNDECL is NULL then we are compiling top level things .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> tree aarch64_general_builtin_decl ( unsigned code , bool ) { if ( code >= AARCH64_BUILTIN_MAX ) return error_mark_node ; return aarch64_builtin_decls [ code ] ; } </s>

Implement TARGET_BUILTIN_DECL for the AARCH64_BUILTIN_GENERAL group .


<s> bool X86TTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> static sbitmap aarch64_components_for_bb ( basic_block bb ) { bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ( ! call_used_regs [ regno ] ) && ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) bitmap_set_bit ( components , regno ) ; return components ; } </s>


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
AArch64
::
NumTargetFixupKinds
]
=
{
{
"fixup_aarch64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_movw"
,
5
,
16
,
0
}
,
{
"fixup_aarch64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> tree aarch64_fold_builtin ( tree fndecl , int n_args ATTRIBUTE_UNUSED , tree * args , bool ignore ATTRIBUTE_UNUSED ) { int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; switch ( fcode ) { BUILTIN_VDQF ( UNOP , abs , 2 ) return fold_build1 ( ABS_EXPR , type , args [ 0 ] ) ; VAR1 ( UNOP , floatv2si , 2 , v2sf ) VAR1 ( UNOP , floatv4si , 2 , v4sf ) VAR1 ( UNOP , floatv2di , 2 , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ 0 ] ) ; default : break ; } return NULL_TREE ; } </s>


<s> bool X86PassConfig :: addInstSelector ( ) { PM . add ( createX86ISelDag ( getX86TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! getX86Subtarget ( ) . is64Bit ( ) ) PM . add ( createGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static int ia64_issue_rate ( void ) { return 6 ; } </s>

Return the maximum number of instructions a cpu can issue .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == 0 ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void SHUXIFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s>
unsigned
getPointerSize
(
)
const
{
StringRef
Name
=
TheTarget
.
getName
(
)
;
if
(
Name
==
"ppc64"
||
Name
==
"ppc64le"
)
return
8
;
assert
(
Name
==
"ppc32"
&&
"Unknown target name!"
)
;
return
4
;
}
</s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void mips_expand_vec_minmax ( rtx target , rtx op0 , rtx op1 , rtx ( * cmp ) ( rtx , rtx , rtx ) , bool min_p ) { machine_mode vmode = GET_MODE ( target ) ; rtx tc , t0 , t1 , x ; tc = gen_reg_rtx ( vmode ) ; t0 = gen_reg_rtx ( vmode ) ; t1 = gen_reg_rtx ( vmode ) ; emit_insn ( cmp ( tc , op0 , op1 ) ) ; x = gen_rtx_AND ( vmode , tc , ( min_p ? op1 : op0 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t0 , x ) ) ; x = gen_rtx_NOT ( vmode , tc ) ; x = gen_rtx_AND ( vmode , x , ( min_p ? op0 : op1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t1 , x ) ) ; x = gen_rtx_IOR ( vmode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } </s>


<s> const TOYSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"  Preloading operand for insn %d into r%d\n"

Convert operand OP in INSN . We should handle memory operands and uninitialized registers . All other register uses are converted during registers conversion .


<s> static rtx_insn * emit_frame_save ( rtx frame_reg , machine_mode mode , unsigned int regno , int offset , HOST_WIDE_INT frame_reg_to_sp ) { rtx reg ; gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp , NULL_RTX , NULL_RTX ) ; } </s>

Save a register into the frame , and emit RTX_FRAME_RELATED_P notes . Save REGNO into [ FRAME_REG + OFFSET ] in mode MODE .


<s> static const char * mips_mdebug_abi_name ( void ) { switch ( mips_abi ) { case ABI_32 : return "abi32" ; case ABI_O64 : return "abiO64" ; case ABI_N32 : return "abiN32" ; case ABI_64 : return "abi64" ; case ABI_EABI : return TARGET_64BIT ? "eabi64" : "eabi32" ; default : gcc_unreachable ( ) ; } } </s>

Return the FOO in the name of the `` .mdebug.FOO '' section associated with the current ABI .


<s> rtx_insn * sh_check_add_incdec_notes ( rtx_insn * i ) { struct for_each_inc_dec_clb { static int func ( rtx mem ATTRIBUTE_UNUSED , rtx op ATTRIBUTE_UNUSED , rtx dest , rtx src ATTRIBUTE_UNUSED , rtx srcoff ATTRIBUTE_UNUSED , void * arg ) { gcc_assert ( REG_P ( dest ) ) ; rtx_insn * i = ( rtx_insn * ) arg ; if ( find_regno_note ( i , REG_INC , REGNO ( dest ) ) == NULL ) add_reg_note ( i , REG_INC , dest ) ; return 0 ; } } ; for_each_inc_dec ( PATTERN ( i ) , for_each_inc_dec_clb :: func , i ) ; return i ; } </s>

Given an insn check if it contains any post/pre inc/dec mem operands and add the REG_INC notes accordingly . FIXME : This function is very similar to lra.cc ( add_auto_inc_notes ) . FIXME : This function is currently used by peephole2 patterns because the peephole2 pass does not preserve REG_INC notes . If the notes are dropped the following passes will do wrong things .


<s>
unsigned
TOYInstrInfo
::
getGlobalBaseReg
(
MachineFunction
*
MF
)
const
{
llvm_unreachable
(
"getGlobalBaseReg not implemented\n"
)
;
}
</s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

TOY
TOY
"getGlobalBaseReg not implemented\n"


<s> static bool aarch64_pac_insn_p ( rtx x ) { if ( ! INSN_P ( x ) ) return x ; subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( x ) , ALL ) { rtx sub = * iter ; if ( sub && GET_CODE ( sub ) == UNSPEC ) { int unspec_val = XINT ( sub , 1 ) ; switch ( unspec_val ) { case UNSPEC_PACISP : return true ; default : return false ; } iter . skip_subrtxes ( ) ; } } return false ; } </s>

Check if X ( or any sub-rtx of X ) is a PACIASP/PACIBSP instruction .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
DAG
->
MF
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getCPUDirective
(
)
;
if
(
Directive
==
PPC
::
DIR_PWR7
||
Directive
==
PPC
::
DIR_PWR8
)
return
new
PPCDispatchGroupSBHazardRecognizer
(
II
,
DAG
)
;
if
(
Directive
!=
PPC
::
DIR_440
&&
Directive
!=
PPC
::
DIR_A2
&&
Directive
!=
PPC
::
DIR_E500mc
&&
Directive
!=
PPC
::
DIR_E5500
)
{
assert
(
DAG
->
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
DAG
)
;
}
return
new
ScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


"when storing %qT, %qE requires a vector"

"%qE requires a vector base and a scalar"

"%qE does not support 32-bit vector type %qT"

"%qE does not support 32-bit sign-extended"

"passing %qT to argument %d of %qE, which when"

" loading %qT expects a vector of %d-bit integers"

" storing %qT expects a vector of %d-bit integers"

"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a vector displacement in a gather-style address . There are three possible uses : - for loading into elements of type TYPE ( when LOAD_P is true ) - for storing from elements of type TYPE ( when LOAD_P is false ) - for prefetching data ( when TYPE is NUM_TYPE_SUFFIXES ) The overloaded function 's mode suffix determines the units of the displacement ( bytes for `` _offset '' , elements for `` _index '' ) . Return the associated mode on success , otherwise report an error and return MODE_none .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ; } </s>


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


Try to add a comment on the PC-relative load .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( NoFusing ) return NULL ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) && hasPartialRegUpdate ( MI -> getOpcode ( ) ) ) return 0 ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned Size = MFI -> getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI -> getObjectAlignment ( FrameIndex ) ; if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; unsigned RCSize = 0 ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; RCSize = 1 ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri8 ; RCSize = 2 ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri8 ; RCSize = 4 ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri8 ; RCSize = 8 ; break ; } if ( Size < RCSize ) return NULL ; MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return NULL ; SmallVector < MachineOperand , 4 > MOs ; MOs . push_back ( MachineOperand :: CreateFI ( FrameIndex ) ) ; return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MOs , Size , Alignment ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> const MCExpr * PPCTargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( ! Subtarget . isPPC64 ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; default : return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> static int ix86_simd_clone_usable ( struct cgraph_node * node ) { switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) return - 1 ; if ( ! TARGET_AVX ) return 0 ; return TARGET_AVX2 ? 2 : 1 ; case 'c' : if ( ! TARGET_AVX ) return - 1 ; return TARGET_AVX2 ? 1 : 0 ; break ; case 'd' : if ( ! TARGET_AVX2 ) return - 1 ; return 0 ; case 'e' : if ( ! TARGET_AVX512F ) return - 1 ; return 0 ; default : gcc_unreachable ( ) ; } } </s>

If SIMD clone NODE ca n't be used in a vectorized loop in current function , return -1 , otherwise return a badness of using it ( 0 if it is most desirable from vecsize_mangle point of view , 1 slightly less desirable , etc . ) .


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( EVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = ARM :: DPRRegisterClass ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = 2 ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = ARM :: DPRRegisterClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = ARM :: DPRRegisterClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = ARM :: DPRRegisterClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static tree aarch64_embedded_comparison_type ( stmt_vec_info stmt_info ) { if ( auto * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ) if ( gimple_assign_rhs_code ( assign ) == COND_EXPR ) { tree cond = gimple_assign_rhs1 ( assign ) ; if ( COMPARISON_CLASS_P ( cond ) ) return TREE_TYPE ( TREE_OPERAND ( cond , 0 ) ) ; } return NULL_TREE ; } </s>

If STMT_INFO is a COND_EXPR that includes an embedded comparison , return the scalar type of the values being compared . Return null otherwise .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> isTargetNaCl ( ) && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> virtual const X86Subtarget * getSubtarget ( ) { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


"-fstack-check=specific not implemented for MIPS16"

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


".relax_hint %%1\n\tsethi $r0, hi20(%%0)\n\t"

".relax_hint %%1\n\tadd $r0, $r0, $gp\n\t"

Auxiliary function for output TLS patterns .


<s> OperandMatchResultTy VEAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken Tok = Parser . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; RegNo = parseRegisterName ( & MatchRegisterName ) ; if ( RegNo == VE :: NoRegister ) RegNo = parseRegisterName ( & MatchRegisterAltName ) ; if ( RegNo != VE :: NoRegister ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


"use_as_extended_reg: converting non-extending mem load in "

"use_as_extended_reg: dest reg %d of extending insn %d is "

Given a reg that is known to be sign or zero extended at some insn , take the appropriate measures so that the extended value can be used as a reg at the specified insn and return the resulting reg rtx .


<s> static void ia64_set_sched_flags ( spec_info_t spec_info ) { unsigned int * flags = & ( current_sched_info -> flags ) ; if ( * flags & SCHED_RGN || * flags & SCHED_EBB || * flags & SEL_SCHED ) { int mask = 0 ; if ( ( mflag_sched_br_data_spec && ! reload_completed && optimize > 0 ) || ( mflag_sched_ar_data_spec && reload_completed ) ) { mask |= BEGIN_DATA ; if ( ! sel_sched_p ( ) && ( ( mflag_sched_br_in_data_spec && ! reload_completed ) || ( mflag_sched_ar_in_data_spec && reload_completed ) ) ) mask |= BE_IN_DATA ; } if ( mflag_sched_control_spec && ( ! sel_sched_p ( ) || reload_completed ) ) { mask |= BEGIN_CONTROL ; if ( ! sel_sched_p ( ) && mflag_sched_in_control_spec ) mask |= BE_IN_CONTROL ; } spec_info -> mask = mask ; if ( mask ) { * flags |= USE_DEPS_LIST | DO_SPECULATION ; if ( mask & BE_IN_SPEC ) * flags |= NEW_BBS ; spec_info -> flags = 0 ; if ( ( mask & CONTROL_SPEC ) && sel_sched_p ( ) && mflag_sel_sched_dont_check_control_spec ) spec_info -> flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL ; if ( sched_verbose >= 1 ) spec_info -> dump = sched_dump ; else spec_info -> dump = 0 ; if ( mflag_sched_count_spec_in_critical_path ) spec_info -> flags |= COUNT_SPEC_IN_CRITICAL_PATH ; } } else spec_info -> mask = 0 ; } </s>

Provide information about speculation capabilities .


<s> bool F2003fPassConfig :: addInstSelector ( ) { addPass ( createF2003fISelDag ( getF2003fTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const LegalizerInfo * PPCSubtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> bool DLXAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OS . write ( "\x15\0\0\0" , 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool mips_expand_vpc_loongson_even_odd ( struct expand_vec_perm_d * d ) { unsigned i , odd , nelt = d -> nelt ; rtx t0 , t1 , t2 , t3 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( nelt < 4 ) return false ; odd = d -> perm [ 0 ] ; if ( odd > 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i * 2 + odd ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( d -> vmode ) ; t1 = gen_reg_rtx ( d -> vmode ) ; switch ( d -> vmode ) { case V4HImode : emit_insn ( gen_loongson_punpckhhw ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklhw ( t1 , d -> op0 , d -> op1 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhhw ( d -> target , t1 , t0 ) ) ; else emit_insn ( gen_loongson_punpcklhw ( d -> target , t1 , t0 ) ) ; break ; case V8QImode : t2 = gen_reg_rtx ( d -> vmode ) ; t3 = gen_reg_rtx ( d -> vmode ) ; emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t1 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpckhbh ( t2 , t1 , t0 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t3 , t1 , t0 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhbh ( d -> target , t3 , t2 ) ) ; else emit_insn ( gen_loongson_punpcklbh ( d -> target , t3 , t2 ) ) ; break ; default : gcc_unreachable ( ) ; } return true ; } </s>

Recognize patterns for even-odd extraction .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getDarwinDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: DIR_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: DIR_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR8 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
Optional
<
RegImmPair
>
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
Register
Reg
)
const
{
int
Sign
=
1
;
int64_t
Offset
=
0
;
const
MachineOperand
&
Op0
=
MI
.
getOperand
(
0
)
;
if
(
!
Op0
.
isReg
(
)
||
Reg
!=
Op0
.
getReg
(
)
)
return
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
;
Offset
=
MI
.
getOperand
(
2
)
.
getImm
(
)
*
Sign
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Offset
<<
Shift
;
}
}
return
RegImmPair
{
MI
.
getOperand
(
1
)
.
getReg
(
)
,
Offset
}
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> bool arm_simd_check_vect_par_cnst_half_p ( rtx op , machine_mode mode , bool high ) { rtx ideal = arm_simd_vect_par_cnst_half ( mode , high ) ; HOST_WIDE_INT count_op = XVECLEN ( op , 0 ) ; HOST_WIDE_INT count_ideal = XVECLEN ( ideal , 0 ) ; int i = 0 ; if ( ! VECTOR_MODE_P ( mode ) ) return false ; if ( count_op != count_ideal ) return false ; for ( i = 0 ; i < count_ideal ; i ++ ) { rtx elt_op = XVECEXP ( op , 0 , i ) ; rtx elt_ideal = XVECEXP ( ideal , 0 , i ) ; if ( ! CONST_INT_P ( elt_op ) || INTVAL ( elt_ideal ) != INTVAL ( elt_op ) ) return false ; } return true ; } </s>

Check OP for validity as a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low lanes , from the perspective of the architecture . See the diagram above arm_simd_vect_par_cnst_half_p for more details .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


"\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "


<s> static tree ix86_builtin_reciprocal ( unsigned int fn , bool md_fn , bool ) { if ( ! ( TARGET_SSE_MATH && ! optimize_insn_for_size_p ( ) && flag_finite_math_only && ! flag_trapping_math && flag_unsafe_math_optimizations ) ) return NULL_TREE ; if ( md_fn ) switch ( fn ) { case IX86_BUILTIN_SQRTPS_NR : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR ) ; case IX86_BUILTIN_SQRTPS_NR256 : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR256 ) ; default : return NULL_TREE ; } else switch ( fn ) { case BUILT_IN_SQRTF : return ix86_get_builtin ( IX86_BUILTIN_RSQRTF ) ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> void rx_emit_stack_pushm ( rtx * operands ) { HOST_WIDE_INT last_reg ; rtx first_push ; gcc_assert ( CONST_INT_P ( operands [ 0 ] ) ) ; last_reg = ( INTVAL ( operands [ 0 ] ) / UNITS_PER_WORD ) - 1 ; gcc_assert ( GET_CODE ( operands [ 1 ] ) == PARALLEL ) ; first_push = XVECEXP ( operands [ 1 ] , 0 , 1 ) ; gcc_assert ( SET_P ( first_push ) ) ; first_push = SET_SRC ( first_push ) ; gcc_assert ( REG_P ( first_push ) ) ; asm_fprintf ( asm_out_file , "\tpushm\t%s-%s\n" , reg_names [ REGNO ( first_push ) - last_reg ] , reg_names [ REGNO ( first_push ) ] ) ; } </s>

Generate a PUSHM instruction that matches the given operands .


"Not expecting bundled instructions here"

Replace a StackProbe inline-stub with the actual probe code inline .


<s> static inline CSKYTargetStreamer :: SymbolIndex getEmptyKey ( ) { return { nullptr , CSKYMCExpr :: VK_CSKY_Invalid } ; } </s>

Empty key : no key should be generated that has no DILocalVariable .


<s>
void
CSKYAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
Res
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
Inst
.
dump
(
)
;
llvm_unreachable
(
"Opcode not expected!"
)
;
case
CSKY
::
LRW16
:
Res
.
setOpcode
(
CSKY
::
LRW32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
BR16
:
Res
.
setOpcode
(
CSKY
::
BR32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
case
CSKY
::
JBSR32
:
Res
.
setOpcode
(
CSKY
::
JSRI32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBR32
:
Res
.
setOpcode
(
CSKY
::
JMPI32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBT32
:
case
CSKY
::
JBF32
:
Res
.
setOpcode
(
Inst
.
getOpcode
(
)
==
CSKY
::
JBT32
CSKY
::
JBT_E
:
CSKY
::
JBF_E
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
2
)
)
;
break
;
case
CSKY
::
JBR16
:
Res
.
setOpcode
(
CSKY
::
JBR32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBT16
:
case
CSKY
::
JBF16
:
unsigned
opcode
;
if
(
STI
.
getFeatureBits
(
)
[
CSKY
::
HasE2
]
)
opcode
=
Inst
.
getOpcode
(
)
==
CSKY
::
JBT16
CSKY
::
JBT32
:
CSKY
::
JBF32
;
else
opcode
=
Inst
.
getOpcode
(
)
==
CSKY
::
JBT16
CSKY
::
JBT_E
:
CSKY
::
JBF_E
;
Res
.
setOpcode
(
opcode
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
2
)
)
;
break
;
}
Inst
=
std
::
move
(
Res
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> const char * loongarch_output_conditional_branch ( rtx_insn * insn , rtx * operands , const char * branch_if_true , const char * branch_if_false ) { unsigned int length ; rtx taken ; gcc_assert ( LABEL_P ( operands [ 0 ] ) ) ; length = get_attr_length ( insn ) ; if ( length <= 4 ) { return branch_if_true ; } rtx_code_label * not_taken = gen_label_rtx ( ) ; taken = operands [ 0 ] ; operands [ 0 ] = not_taken ; output_asm_insn ( branch_if_false , operands ) ; output_asm_insn ( "b\t%0" , & taken ) ; targetm . asm_out . internal_label ( asm_out_file , "L" , CODE_LABEL_NUMBER ( not_taken ) ) ; return "" ; } </s>

Return the assembly code for INSN , which has the operands given by OPERANDS , and which branches to OPERANDS [ 0 ] if some condition is true . BRANCH_IF_TRUE is the asm template that should be used if OPERANDS [ 0 ] is in range of a direct branch . BRANCH_IF_FALSE is an inverted version of BRANCH_IF_TRUE .


<s>
bool
SystemZInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
SystemZII
::
Branch
Branch
(
getBranchInfo
(
*
I
)
)
;
if
(
!
Branch
.
Target
->
isMBB
(
)
)
return
true
;
if
(
Branch
.
Type
!=
SystemZII
::
BranchNormal
)
return
true
;
if
(
Branch
.
CCMask
==
SystemZ
::
CCMASK_ANY
)
{
if
(
!
AllowModify
)
{
TBB
=
Branch
.
Target
->
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
Branch
.
Target
->
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
Branch
.
Target
->
getMBB
(
)
;
continue
;
}
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
Branch
.
Target
->
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCValid
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCMask
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
2
&&
TBB
&&
"Should have seen a conditional branch"
)
;
if
(
TBB
!=
Branch
.
Target
->
getMBB
(
)
)
return
true
;
unsigned
OldCCValid
=
Cond
[
0
]
.
getImm
(
)
;
unsigned
OldCCMask
=
Cond
[
1
]
.
getImm
(
)
;
if
(
OldCCValid
==
Branch
.
CCValid
&&
OldCCMask
==
Branch
.
CCMask
)
continue
;
return
false
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
bool
AArch64AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
&&
ExtraCode
[
0
]
!=
'a'
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
AArch64InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool SVEIntrinsicOpts :: runOnModule ( Module & M ) { bool Changed = false ; SmallSetVector < Function * , 4 > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: aarch64_sve_convert_from_svbool : case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : for ( User * U : F . users ( ) ) Functions . insert ( cast < Instruction > ( U ) -> getFunction ( ) ) ; break ; default : break ; } } if ( ! Functions . empty ( ) ) Changed |= optimizeFunctions ( Functions ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: CALL : return LowerCALL ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FORMAL_ARGUMENTS : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: RET : return LowerRET ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::CALL ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FORMAL_ARGUMENTS ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::RET ISD::SELECT ISD::SETCC


<s> int mmix_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ATTRIBUTE_UNUSED ) { return DW_EH_PE_absptr ; } </s>


<s>
static
bool
isValid
(
ReachingDefAnalysis
&
RDA
)
{
for
(
auto
&
Block
:
Blocks
)
{
if
(
isEntryPredicatedOnVCTP
(
Block
,
false
)
||
hasImplicitlyValidVPT
(
Block
,
RDA
)
)
continue
;
SmallVectorImpl
<
MachineInstr
*
>
&
Insts
=
Block
.
getInsts
(
)
;
for
(
auto
*
MI
:
Insts
)
{
if
(
isVCTP
(
MI
)
&&
getVPTInstrPredicate
(
*
MI
)
!=
ARMVCC
::
Then
)
return
false
;
if
(
MI
->
getOpcode
(
)
==
ARM
::
MVE_VPST
||
isVectorPredicate
(
MI
)
)
continue
;
if
(
!
isPredicatedOnVCTP
(
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops: Can't convert: "
<<
*
MI
)
;
return
false
;
}
}
}
return
true
;
}
</s>

Returns true if this iterator is still pointing at a valid entry .

ARM
ARMVCC::Then
ARM::MVE_VPST
"ARM Loops: Can't convert: "


"insertBranch must not be told to insert a fallthrough"

"Unconditional branch with multiple successors!"

"Lanai branch conditions should have one component."

Insert branch code into the end of the specified MachineBasicBlock .


<s> static rtx rs6000_load_constant_and_splat ( machine_mode mode , REAL_VALUE_TYPE dconst ) { rtx reg ; if ( mode == SFmode || mode == DFmode ) { rtx d = const_double_from_real_value ( dconst , mode ) ; reg = force_reg ( mode , d ) ; } else if ( mode == V4SFmode ) { rtx d = const_double_from_real_value ( dconst , SFmode ) ; rtvec v = gen_rtvec ( 4 , d , d , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else if ( mode == V2DFmode ) { rtx d = const_double_from_real_value ( dconst , DFmode ) ; rtvec v = gen_rtvec ( 2 , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else gcc_unreachable ( ) ; return reg ; } </s>

Load up a constant . If the mode is a vector mode , splat the value across all of the vector elements .


<s> static rtx sparc_function_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return sparc_function_arg_1 ( cum , arg , false ) ; } </s>

Handle the TARGET_FUNCTION_ARG target hook .


<s> Value * X86TargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) return M . getGlobalVariable ( "__security_cookie" ) ; return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . getMMI ( ) . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI -> getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI -> getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI -> getObjectSize ( FrameIndex ) ; MFI -> setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI -> CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM MLA / MLS expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void aarch64_expand_sve_vcond ( machine_mode data_mode , machine_mode cmp_mode , rtx * ops ) { machine_mode pred_mode = aarch64_get_mask_mode ( cmp_mode ) . require ( ) ; rtx pred = gen_reg_rtx ( pred_mode ) ; if ( FLOAT_MODE_P ( cmp_mode ) ) { if ( aarch64_expand_sve_vec_cmp_float ( pred , GET_CODE ( ops [ 3 ] ) , ops [ 4 ] , ops [ 5 ] , true ) ) std :: swap ( ops [ 1 ] , ops [ 2 ] ) ; } else aarch64_expand_sve_vec_cmp_int ( pred , GET_CODE ( ops [ 3 ] ) , ops [ 4 ] , ops [ 5 ] ) ; if ( ! aarch64_sve_reg_or_dup_imm ( ops [ 1 ] , data_mode ) ) ops [ 1 ] = force_reg ( data_mode , ops [ 1 ] ) ; if ( register_operand ( ops [ 1 ] , data_mode ) || ! aarch64_simd_reg_or_zero ( ops [ 2 ] , data_mode ) ) ops [ 2 ] = force_reg ( data_mode , ops [ 2 ] ) ; rtvec vec = gen_rtvec ( 3 , pred , ops [ 1 ] , ops [ 2 ] ) ; emit_set_insn ( ops [ 0 ] , gen_rtx_UNSPEC ( data_mode , vec , UNSPEC_SEL ) ) ; } </s>

Expand an SVE vcond pattern with operands OPS . DATA_MODE is the mode of the data being selected and CMP_MODE is the mode of the values being compared .


"attribute %<target%> argument not a string"

"FDPIC mode is not supported in Thumb-1 mode"

"invalid fpu for target attribute or pragma %qs"

"auto fpu selection not currently permitted here"

"invalid architecture for target attribute or pragma %qs"

"unknown target attribute or pragma %qs"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> bool isTarget64BitILP32 ( ) const { if ( NaClDontBreakABI ) { return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 ) ; } return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 || TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s> static unsigned int loongarch_integer_cost ( HOST_WIDE_INT value ) { struct loongarch_integer_op codes [ LARCH_MAX_INTEGER_OPS ] ; return loongarch_build_integer ( codes , value ) ; } </s>

Fill CODES with a sequence of rtl operations to load VALUE . Return the number of operations needed . Split interger in loongarch_output_move .


<s> DecodeStatus AArch64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { CommentStream = & cs ; uint8_t bytes [ 4 ] ; if ( Region . readBytes ( Address , 4 , bytes ) == - 1 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t insn = ( bytes [ 3 ] << 24 ) | ( bytes [ 2 ] << 16 ) | ( bytes [ 1 ] << 8 ) | ( bytes [ 0 ] << 0 ) ; DecodeStatus result = decodeInstruction ( DecoderTableA6432 , MI , insn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = 4 ; return result ; } MI . clear ( ) ; Size = 0 ; return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool Mips16RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( isLoad && usePartialVectorLoads ( N , Subtarget ) ) { return false ; } if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != MVT :: v4f64 && VT != MVT :: v4f32 ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 0 ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 4 ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: CPU64RegsRegClass : & Mips :: CPURegsRegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips::SP_64 Mips::SP Mips::FP_64 Mips::FP Mips::ZERO_64 Mips::ZERO Mips::DADDu Mips::ADDu 0 Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass 0 0 4 Mips


<s> static void arm_block_move_unaligned_loop ( rtx dest , rtx src , HOST_WIDE_INT length , unsigned int interleave_factor , HOST_WIDE_INT bytes_per_iter ) { rtx src_reg , dest_reg , final_src , test ; HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; arm_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; arm_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; rtx_code_label * label = gen_label_rtx ( ) ; emit_label ( label ) ; arm_block_move_unaligned_straight ( dest , src , bytes_per_iter , interleave_factor ) ; emit_move_insn ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; emit_move_insn ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; if ( leftover ) arm_block_move_unaligned_straight ( dest , src , leftover , interleave_factor ) ; } </s>

From mips_block_move_loop : Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER bytes at a time . LENGTH must be at least BYTES_PER_ITER . Assume that the memory regions do not overlap .


<s> static rtx mt_generate_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx scratch0 , scratch1 , const_scratch ; switch ( code ) { case GTU : case LTU : case GEU : case LEU : scratch0 = gen_reg_rtx ( SImode ) ; scratch1 = gen_reg_rtx ( SImode ) ; const_scratch = force_reg ( SImode , GEN_INT ( MT_MIN_INT ) ) ; emit_insn ( gen_addsi3 ( scratch0 , const_scratch , op0 ) ) ; emit_insn ( gen_addsi3 ( scratch1 , const_scratch , op1 ) ) ; break ; default : scratch0 = op0 ; scratch1 = op1 ; break ; } switch ( code ) { case GTU : code = GT ; break ; case LTU : code = LT ; break ; case GEU : code = GE ; break ; case LEU : code = LE ; break ; default : break ; } return gen_rtx_fmt_ee ( code , VOIDmode , scratch0 , scratch1 ) ; } </s>

Generate a compare for CODE . Return a brand-new rtx that represents the result of the compare .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ 5 ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 6 ] ) ) ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_release ( mod_s ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_acquire ( mod_s ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ; cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> static HOST_WIDE_INT csky_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size && align < BITS_PER_WORD ) return BITS_PER_WORD ; return align ; } </s>

Implement TARGET_CONSTANT_ALIGNMENT . Make strings word-aligned so strcpy from constants will be faster .


"-mcall-ms2sysv-xlogues is not compatible with %s"

Emits a warning for unsupported msabi to sysv pro/epilogues .


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( TARGET_ALTIVEC || TARGET_VSX ) return altivec_builtin_mask_for_load ; else return 0 ; } </s>


<s> inline static int number_of_first_bit_set ( unsigned mask ) { return ctz_hwi ( mask ) ; } </s>

Return the number ( counting from 0 ) of the least significant set bit in MASK .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . isOSWindows ( ) || TargetABI == ARMBaseTargetMachine :: ARM_ABI_AAPCS16 ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> int arm_split_constant ( enum rtx_code code , machine_mode mode , rtx insn , HOST_WIDE_INT val , rtx target , rtx source , int subtargets ) { rtx cond ; if ( insn && GET_CODE ( PATTERN ( insn ) ) == COND_EXEC ) cond = COND_EXEC_TEST ( PATTERN ( insn ) ) ; else cond = NULL_RTX ; if ( subtargets || code == SET || ( REG_P ( target ) && REG_P ( source ) && REGNO ( target ) != REGNO ( source ) ) ) { if ( ! cfun -> machine -> after_arm_reorg && ! cond && ( arm_gen_constant ( code , mode , NULL_RTX , val , target , source , 1 , 0 ) > ( arm_constant_limit ( optimize_function_for_size_p ( cfun ) ) + ( code != SET ) ) ) ) { if ( code == SET ) { if ( TARGET_USE_MOVT ) arm_emit_movpair ( target , GEN_INT ( val ) ) ; else emit_set_insn ( target , GEN_INT ( val ) ) ; return 1 ; } else { rtx temp = subtargets ? gen_reg_rtx ( mode ) : target ; if ( TARGET_USE_MOVT ) arm_emit_movpair ( temp , GEN_INT ( val ) ) ; else emit_set_insn ( temp , GEN_INT ( val ) ) ; if ( code == MINUS ) emit_set_insn ( target , gen_rtx_MINUS ( mode , temp , source ) ) ; else emit_set_insn ( target , gen_rtx_fmt_ee ( code , mode , source , temp ) ) ; return 2 ; } } } return arm_gen_constant ( code , mode , cond , val , target , source , subtargets , 1 ) ; } </s>

Emit a sequence of insns to handle a large constant . CODE is the code of the operation required , it can be any of SET , PLUS , IOR , AND , XOR , MINUS ; MODE is the mode in which the operation is being performed ; VAL is the integer to operate on ; SOURCE is the other operand ( a register , or a null-pointer for SET ) ; SUBTARGETS means it is safe to create scratch registers if that will either produce a simpler sequence , or we will want to cse the values . Return value is the number of insns emitted .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI . setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> static void or1k_print_operand_address ( FILE * file , machine_mode , rtx addr ) { rtx offset ; switch ( GET_CODE ( addr ) ) { case REG : fputc ( '0' , file ) ; break ; case PLUS : offset = XEXP ( addr , 1 ) ; addr = XEXP ( addr , 0 ) ; gcc_assert ( CONST_INT_P ( offset ) ) ; if ( GET_CODE ( addr ) == LO_SUM ) { print_reloc ( file , XEXP ( addr , 1 ) , INTVAL ( offset ) , RKIND_LO ) ; addr = XEXP ( addr , 0 ) ; } else output_addr_const ( file , offset ) ; break ; case LO_SUM : offset = XEXP ( addr , 1 ) ; addr = XEXP ( addr , 0 ) ; print_reloc ( file , offset , 0 , RKIND_LO ) ; break ; default : output_addr_const ( file , addr ) ; return ; } fprintf ( file , "(%s)" , reg_names [ REGNO ( addr ) ] ) ; } </s>

Worker for TARGET_PRINT_OPERAND_ADDRESS . Prints the argument ADDR , an address RTX , to the file FILE . The output is formed as expected by the OpenRISC assembler . Examples : RTX OUTPUT ( reg : SI 3 ) 0 ( r3 ) ( plus : SI ( reg : SI 3 ) ( const_int 4 ) ) 0x4 ( r3 ) ( lo_sum : SI ( reg : SI 3 ) ( symbol_ref : SI ( `` x '' ) ) ) ) lo ( x ) ( r3 )


<s>
bool
MipsAsmParser
::
ParseInstruction
(
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
if
(
requestsDoubleOperand
(
Name
)
)
{
setFpFormat
(
FP_FORMAT_D
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
}
else
{
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
MipsOperand::CreateToken
0
MipsOperand::CreateToken
1
MipsOperand::CreateToken
"c."
MipsOperand::CreateToken
"."
1
"Invalid conditional code"
1
MipsOperand::CreateImm
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>


<s> rtx aarch64_sls_create_blr_label ( int regnum ) { gcc_assert ( STUB_REGNUM_P ( regnum ) ) ; if ( optimize_function_for_size_p ( cfun ) ) { aarch64_sls_shared_thunks_needed = true ; const char * thunk_name = indirect_symbol_names [ regnum ] ; if ( aarch64_sls_shared_thunks [ regnum ] == NULL ) { tree decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( thunk_name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = 1 ; TREE_STATIC ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; resolve_unique_section ( decl , 0 , false ) ; aarch64_sls_shared_thunks [ regnum ] = decl ; } return gen_rtx_SYMBOL_REF ( Pmode , thunk_name ) ; } if ( cfun -> machine -> call_via [ regnum ] == NULL ) cfun -> machine -> call_via [ regnum ] = gen_rtx_LABEL_REF ( Pmode , gen_label_rtx ( ) ) ; return cfun -> machine -> call_via [ regnum ] ; } </s>

Function to create a BLR thunk . This thunk is used to mitigate straight line speculation . Instead of a simple BLR that can be speculated past , we emit a BL to this thunk , and this thunk contains a BR to the relevant register . These thunks have the relevant speculation barries put after their indirect branch so that speculation is blocked . We use such a thunk so the speculation barriers are kept off the architecturally executed path in order to reduce the performance overhead . When optimizing for size we use stubs shared by the linked object . When optimizing for performance we emit stubs for each function in the hope that the branch predictor can better train on jumps specific for a given function .


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
ModeSize
,
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
,
unsigned
FrontendSize
=
0
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
llvm
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
ModeSize
=
ModeSize
;
Res
->
Mem
.
FrontendSize
=
FrontendSize
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>