<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size ; size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( mode == SDmode ) || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> bool LC2200FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void MINA32FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void mips_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct mips_arg_info info ; mips_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < 2 && info . fpr_p ) cum -> fp_code += ( arg . mode == SFmode ? 1 : 2 ) << ( cum -> arg_number * 2 ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs = info . reg_offset + info . reg_words ; else if ( info . reg_words > 0 ) cum -> num_fprs += MAX_FPRS_PER_FMT ; if ( info . stack_words > 0 ) cum -> stack_words = info . stack_offset + info . stack_words ; cum -> arg_number ++ ; } </s>


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; ( void ) & CC_AArch64_DarwinPCS_VarArg ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> bool X86TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { SDValue BasePtr = cast < LoadSDNode > ( Load ) -> getBasePtr ( ) ; if ( BasePtr . getOpcode ( ) == X86ISD :: WrapperRIP ) if ( const auto * GA = dyn_cast < GlobalAddressSDNode > ( BasePtr . getOperand ( 0 ) ) ) return GA -> getTargetFlags ( ) != X86II :: MO_GOTTPOFF ; EVT VT = Load -> getValueType ( 0 ) ; if ( ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && ! Load -> hasOneUse ( ) ) { for ( auto UI = Load -> use_begin ( ) , UE = Load -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != 0 ) continue ; if ( UI -> getOpcode ( ) != ISD :: EXTRACT_SUBVECTOR || ! UI -> hasOneUse ( ) || UI -> use_begin ( ) -> getOpcode ( ) != ISD :: STORE ) return true ; } return false ; } return true ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> static bool aarch64_pragma_target_parse ( tree args , tree pop_target ) { if ( args ) { if ( ! aarch64_process_target_attr ( args , "pragma" ) ) return false ; aarch64_override_options_internal ( & global_options ) ; } else { pop_target = pop_target ? pop_target : target_option_default_node ; cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( pop_target ) ) ; } target_option_current_node = build_target_option_node ( & global_options ) ; aarch64_reset_previous_fndecl ( ) ; cpp_options * cpp_opts = cpp_get_options ( parse_in ) ; unsigned char saved_warn_unused_macros = cpp_opts -> warn_unused_macros ; cpp_opts -> warn_unused_macros = 0 ; aarch64_update_cpp_builtins ( parse_in ) ; cpp_opts -> warn_unused_macros = saved_warn_unused_macros ; if ( pop_target ) aarch64_save_restore_target_globals ( pop_target ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } return true ; } </s>

Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> static bool is_branch_slot_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ; return false ; } return false ; } </s>

The function returns true if INSN can be issued only from the branch slot .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


"switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch"

"assembler does not support %<-mabi=ilp32%>"

"return address signing is only supported for %<-mabi=lp64%>"


<s> uint64_t MipsPLT :: emit ( MemoryRegion & pRegion ) { uint64_t result = 0x0 ; iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < MipsPLT0 > ( ( * it ) ) . getValue ( ) , MipsPLT0 :: EntrySize ) ; result += MipsPLT0 :: EntrySize ; ++ it ; MipsPLTA * plta = 0 ; for ( iterator ie = end ( ) ; it != ie ; ++ it ) { plta = & ( llvm :: cast < MipsPLTA > ( * it ) ) ; memcpy ( buffer + result , plta -> getValue ( ) , MipsPLTA :: EntrySize ) ; result += MipsPLTA :: EntrySize ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .

Mips Mips 0x0 Mips Mips Mips Mips 0 Mips Mips Mips


<s> bool X86TargetLowering :: decomposeMulByConstant ( EVT VT , SDValue C ) const { APInt MulC ; if ( ! ISD :: isConstantSplatVector ( C . getNode ( ) , MulC ) ) return false ; if ( isOperationLegal ( ISD :: MUL , VT ) ) return false ; return ( MulC + 1 ) . isPowerOf2 ( ) || ( MulC - 1 ) . isPowerOf2 ( ) || ( 1 - MulC ) . isPowerOf2 ( ) || ( - ( MulC + 1 ) ) . isPowerOf2 ( ) ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> void mips_gen_conditional_trap ( rtx * operands ) { rtx op0 , op1 ; enum rtx_code cmp_code = GET_CODE ( operands [ 0 ] ) ; enum machine_mode mode = GET_MODE ( cmp_operands [ 0 ] ) ; switch ( cmp_code ) { case GT : cmp_code = LT ; break ; case LE : cmp_code = GE ; break ; case GTU : cmp_code = LTU ; break ; case LEU : cmp_code = GEU ; break ; default : break ; } if ( cmp_code == GET_CODE ( operands [ 0 ] ) ) { op0 = cmp_operands [ 0 ] ; op1 = cmp_operands [ 1 ] ; } else { op0 = cmp_operands [ 1 ] ; op1 = cmp_operands [ 0 ] ; } op0 = force_reg ( mode , op0 ) ; if ( ! arith_operand ( op1 , mode ) ) op1 = force_reg ( mode , op1 ) ; emit_insn ( gen_rtx_TRAP_IF ( VOIDmode , gen_rtx_fmt_ee ( cmp_code , mode , op0 , op1 ) , operands [ 1 ] ) ) ; } </s>

Emit a conditional trap . OPERANDS is the array of operands passed to the conditional_trap expander .


<s> static void ix86_output_indirect_branch_via_push ( rtx call_op , const char * xasm , bool sibcall_p ) { char thunk_name_buf [ 32 ] ; char * thunk_name ; char push_buf [ 64 ] ; enum indirect_thunk_prefix need_prefix = indirect_thunk_need_prefix ( current_output_insn ) ; int regno = - 1 ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_inline ) { if ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) indirect_thunk_needed = true ; indirect_thunk_name ( thunk_name_buf , regno , need_prefix , false ) ; thunk_name = thunk_name_buf ; } else thunk_name = NULL ; snprintf ( push_buf , sizeof ( push_buf ) , "push{%c}\t%s" , TARGET_64BIT ? 'q' : 'l' , xasm ) ; if ( sibcall_p ) { output_asm_insn ( push_buf , & call_op ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; else output_indirect_thunk ( regno ) ; } else { char indirectlabel1 [ 32 ] ; char indirectlabel2 [ 32 ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; fputs ( "\tjmp\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( MEM_P ( call_op ) ) { struct ix86_address parts ; rtx addr = XEXP ( call_op , 0 ) ; if ( ix86_decompose_address ( addr , & parts ) && parts . base == stack_pointer_rtx ) { if ( parts . index ) { addr = gen_rtx_MULT ( Pmode , parts . index , GEN_INT ( parts . scale ) ) ; addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , addr ) ; } else addr = stack_pointer_rtx ; rtx disp ; if ( parts . disp != NULL_RTX ) disp = plus_constant ( Pmode , parts . disp , UNITS_PER_WORD ) ; else disp = GEN_INT ( UNITS_PER_WORD ) ; addr = gen_rtx_PLUS ( Pmode , addr , disp ) ; call_op = gen_rtx_MEM ( GET_MODE ( call_op ) , addr ) ; } } output_asm_insn ( push_buf , & call_op ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; else output_indirect_thunk ( regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; fputs ( "\tcall\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel1 ) ; fputc ( '\n' , asm_out_file ) ; } } </s>

Output indirect branch via a call and return thunk . CALL_OP is the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : jmp L2 L1 : push CALL_OP jmp __x86_indirect_thunk L2 : call L1 and a tail call is converted to : push CALL_OP jmp __x86_indirect_thunk


<s> bool MandarinTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( Subtarget . isThumb2 ( ) && ! Subtarget . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
SADDSAT
:
case
ISD
::
SSUBSAT
:
Res
=
LowerSADDSUBSAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
ABS
:
lowerABS
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SHL
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::SADDSAT
ISD::SSUBSAT
0
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN
ISD::ABS


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } if ( Size >= 4 ) return MVT :: i32 ; else if ( Size >= 2 ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static bool mips_lwxs_address_p ( rtx addr ) { if ( ISA_HAS_LWXS && GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , 1 ) ) ) { rtx offset = XEXP ( addr , 0 ) ; if ( GET_CODE ( offset ) == MULT && REG_P ( XEXP ( offset , 0 ) ) && CONST_INT_P ( XEXP ( offset , 1 ) ) && INTVAL ( XEXP ( offset , 1 ) ) == 4 ) return true ; } return false ; } </s>

Return true if ADDR matches the pattern for the LWXS load scaled indexed address instruction . Note that such addresses are not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense , because their use is so restricted .


<s> static void xstormy16_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < NUM_ARGUMENT_REGISTERS && * cum + XSTORMY16_WORD_SIZE ( type , mode ) > NUM_ARGUMENT_REGISTERS ) * cum = NUM_ARGUMENT_REGISTERS ; * cum += XSTORMY16_WORD_SIZE ( type , mode ) ; } </s>

Update CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` TARGET_FUNCTION_ARG ' , etc . This function need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help . However , it makes life easier for xstormy16_build_va_list if it does update the word count .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroName = ( V && V -> isNullValue ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { return MI && OpNo && LI && false ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool fixed_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return false ; return fixed_regs [ reg ] ; } </s>

Return whether REG is a global user reg or has been specifed by -ffixed-REG . We should not restore these , and so can not use lmw or out-of-line restore functions if there are any . We also ca n't save them ( well , emit frame notes for them ) , because frame unwinding during exception handling will restore saved registers .


<s> void rs6000_call_sysv ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie ) { rtx func = func_desc ; rtx func_addr ; rtx call [ 4 ] ; rtx insn ; rtx abi_reg = NULL_RTX ; int n ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( ( INTVAL ( cookie ) & CALL_LONG ) != 0 && GET_CODE ( func_desc ) == SYMBOL_REF ) { func = rs6000_longcall_ref ( func_desc , tlsarg ) ; if ( TARGET_PLTSEQ ) abi_reg = func ; } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; if ( abi_reg ) { rtvec v = gen_rtvec ( 3 , func , func_desc , tlsarg ) ; rtx mark_func = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; emit_insn ( gen_rtx_SET ( func_addr , mark_func ) ) ; v = gen_rtvec ( 2 , func_addr , func_desc ) ; func_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; } else emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = gen_rtx_USE ( VOIDmode , cookie ) ; n = 2 ; if ( TARGET_SECURE_PLT && flag_pic && GET_CODE ( func_addr ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( func_addr ) ) call [ n ++ ] = gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ; call [ n ++ ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( n , call ) ) ; insn = emit_call_insn ( insn ) ; if ( abi_reg ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , abi_reg ) ; } </s>

Expand code to perform a call under the SYSV4 ABI .


<s> void CSKYFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const CSKYRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; if ( RI -> hasStackRealignment ( MF ) ) { Align MaxStackAlign = std :: max ( StackAlign , MFI . getMaxAlign ( ) ) ; FrameSize += ( MaxStackAlign . value ( ) - StackAlign . value ( ) ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s>
static
unsigned
int
aarch64_parse_boolean_options
(
const
char
*
option
,
const
struct
aarch64_flag_desc
*
flags
,
unsigned
int
initial_state
,
const
char
*
option_name
)
{
const
char
separator
=
'.'
;
const
char
*
specs
=
option
;
const
char
*
ntoken
=
option
;
unsigned
int
found_flags
=
initial_state
;
while
(
(
ntoken
=
strchr
(
specs
,
separator
)
)
)
{
size_t
token_length
=
ntoken
specs
;
unsigned
token_ops
=
aarch64_parse_one_option_token
(
specs
,
token_length
,
flags
,
option_name
)
;
if
(
!
token_ops
)
found_flags
=
0
;
found_flags
|=
token_ops
;
specs
=
++
ntoken
;
}
if
(
!
(
*
specs
)
)
{
error
(
"%s string ill-formed\n"
,
option_name
)
;
return
0
;
}
size_t
token_length
=
strlen
(
specs
)
;
unsigned
token_ops
=
aarch64_parse_one_option_token
(
specs
,
token_length
,
flags
,
option_name
)
;
if
(
!
token_ops
)
found_flags
=
0
;
found_flags
|=
token_ops
;
return
found_flags
;
}
</s>

Parse OPTION which is a comma-separated list of flags to enable . FLAGS gives the list of flags we understand , INITIAL_STATE gives any default state we inherit from the CPU tuning structures . OPTION_NAME gives the top-level option we are parsing in the -moverride string , for use in error messages .


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADD
:
if
(
Node
->
getSimpleValueType
(
0
)
.
isVector
(
)
&&
selectVecAddAsVecSubIfProfitable
(
Node
)
)
return
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"== "
"\n"
1
ISD::ADD
0
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


<s>
static
void
rs6000_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
rs6000_print_isa_options
(
file
,
indent
,
"Isa options set"
,
ptr
->
x_rs6000_isa_flags
)
;
rs6000_print_isa_options
(
file
,
indent
,
"Isa options explicit"
,
ptr
->
x_rs6000_isa_flags_explicit
)
;
}
</s>

powerpcspe
"Isa options set"
"Isa options explicit"


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! SrcVT . isSimple ( ) || ! DstVT . isSimple ( ) ) return false ; MVT SVT = SrcVT . getSimpleVT ( ) ; MVT DVT = DstVT . getSimpleVT ( ) ; if ( ! SVT . is128BitVector ( ) && ! ( Subtarget -> hasAVX ( ) && SVT . is256BitVector ( ) ) && ! ( Subtarget -> hasAVX512 ( ) && SVT . is512BitVector ( ) && ( Subtarget -> hasBWI ( ) || ( SVT . getScalarSizeInBits ( ) >= 32 && DVT . getScalarSizeInBits ( ) >= 32 ) ) ) ) return false ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> bool ARMBaseRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void LanaiTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case LanaiISD :: SETCC : Known = KnownBits ( BitWidth ) ; Known . Zero . setBits ( 1 , BitWidth ) ; break ; case LanaiISD :: SELECT_CC : KnownBits Known2 ; DAG . computeKnownBits ( Op -> getOperand ( 0 ) , Known , Depth + 1 ) ; DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Known2 , Depth + 1 ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
RegName
=
[
]
(
unsigned
Reg
)
{
if
(
Reg
)
return
LoongArchInstPrinter
::
getRegisterName
(
Reg
)
;
else
return
"noreg"
;
}
;
switch
(
Kind
)
{
case
KindTy
::
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register "
<<
RegName
(
getReg
(
)
)
<<
">"
;
break
;
case
KindTy
::
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

LoongArch
LoongArch
"noreg"
"<register "
">"
"'"
"'"


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> unsigned OR1KTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return OR1K :: R4 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
,
false
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOCAL_ESCAPE
)
{
MachineOperand
&
FI
=
MI
.
getOperand
(
FIOperandNum
)
;
Offset
=
TFI
->
getNonLocalFrameIndexReference
(
MF
,
FrameIndex
)
;
FI
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
false
,
true
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII , Out ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> static struct unw_reg_state * dup_state_stack ( struct unw_reg_state * rs ) { struct unw_reg_state * copy , * prev = NULL , * first = NULL ; while ( rs ) { copy = alloc_reg_state ( ) ; memcpy ( copy , rs , sizeof ( * copy ) ) ; if ( first ) prev -> next = copy ; else first = copy ; rs = rs -> next ; prev = copy ; } return first ; } </s>

Make a copy of the state stack . Non-recursive to avoid stack overflows .


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == ARM :: t2LoopEndDec || MI -> getOpcode ( ) == ARM :: t2DoLoopStartTP ; } </s>

Return true if the given terminator MI is not expected to spill .


<s>
static
void
mips_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
const
char
*
fnname
;
HOST_WIDE_INT
tsize
=
cfun
->
machine
->
frame
.
total_size
;
if
(
debug_info_level
!=
DINFO_LEVEL_TERSE
&&
write_symbols
==
SDB_DEBUG
)
SDB_OUTPUT_SOURCE_LINE
(
file
,
DECL_SOURCE_LINE
(
current_function_decl
)
)
;
if
(
TARGET_MIPS16
&&
!
TARGET_SOFT_FLOAT
&&
current_function_args_info
.
fp_code
!=
0
)
build_mips16_function_stub
(
file
)
;
if
(
!
FUNCTION_NAME_ALREADY_DECLARED
)
{
fnname
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
if
(
!
flag_inhibit_size_directive
)
{
fputs
(
"\t.ent\t"
,
file
)
;
assemble_name
(
file
,
fnname
)
;
fputs
(
"\n"
,
file
)
;
}
assemble_name
(
file
,
fnname
)
;
fputs
(
":\n"
,
file
)
;
}
if
(
TARGET_IRIX
&&
mips_abi
==
ABI_32
)
TREE_ASM_WRITTEN
(
DECL_NAME
(
cfun
->
decl
)
)
=
1
;
if
(
!
flag_inhibit_size_directive
)
{
fprintf
(
file
,
"\t.frame\t%s,"
HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
"# vars= "
HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
", args= "
HOST_WIDE_INT_PRINT_DEC
", gp= "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
(
reg_names
[
(
frame_pointer_needed
)
HARD_FRAME_POINTER_REGNUM
:
STACK_POINTER_REGNUM
]
)
,
(
(
frame_pointer_needed
&&
TARGET_MIPS16
)
tsize
cfun
->
machine
->
frame
.
args_size
:
tsize
)
,
reg_names
[
GP_REG_FIRST
+
31
]
,
cfun
->
machine
->
frame
.
var_size
,
cfun
->
machine
->
frame
.
num_gp
,
cfun
->
machine
->
frame
.
num_fp
,
cfun
->
machine
->
frame
.
args_size
,
cfun
->
machine
->
frame
.
cprestore_size
)
;
fprintf
(
file
,
"\t.mask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
cfun
->
machine
->
frame
.
mask
,
cfun
->
machine
->
frame
.
gp_save_offset
)
;
fprintf
(
file
,
"\t.fmask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
cfun
->
machine
->
frame
.
fmask
,
cfun
->
machine
->
frame
.
fp_save_offset
)
;
}
if
(
TARGET_ABICALLS
&&
!
TARGET_NEWABI
&&
cfun
->
machine
->
global_pointer
>
0
)
{
if
(
!
cfun
->
machine
->
all_noreorder_p
)
output_asm_insn
(
"%(.cpload\t%^%)"
,
0
)
;
else
output_asm_insn
(
"%(.cpload\t%^\n\t%<"
,
0
)
;
}
else
if
(
cfun
->
machine
->
all_noreorder_p
)
output_asm_insn
(
"%(%<"
,
0
)
;
mips_output_cplocal
(
)
;
}
</s>

Set up the stack and frame ( if desired ) for the function .


<s> bool ARMSubtarget :: enableSubRegLiveness ( ) const { if ( EnableSubRegLiveness . getNumOccurrences ( ) ) return EnableSubRegLiveness ; return hasMVEIntegerOps ( ) ; } </s>

Enable tracking of subregister liveness in register allocator .


<s>
const
char
*
pru_output_signed_cbranch_ubyteop2
(
rtx
*
operands
,
bool
is_near
)
{
static
char
buf
[
1024
]
;
enum
rtx_code
code
=
GET_CODE
(
operands
[
0
]
)
;
int
regop_sign_bit_pos
=
sign_bit_position
(
operands
[
1
]
)
;
const
char
*
cmp_opstr
;
const
char
*
rcmp_opstr
;
code
=
swap_condition
(
code
)
;
switch
(
code
)
{
case
LT
:
cmp_opstr
=
"qblt"
;
rcmp_opstr
=
"qbge"
;
break
;
case
LE
:
cmp_opstr
=
"qble"
;
rcmp_opstr
=
"qbgt"
;
break
;
case
GT
:
cmp_opstr
=
"qbgt"
;
rcmp_opstr
=
"qble"
;
break
;
case
GE
:
cmp_opstr
=
"qbge"
;
rcmp_opstr
=
"qblt"
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
code
==
LT
||
code
==
LE
)
{
if
(
is_near
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+8, %%1, %d\n\t"
"%s\t%%l3, %%1, %%u2"
,
regop_sign_bit_pos
,
cmp_opstr
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+12, %%1, %d\n\t"
"%s\t.+8, %%1, %%u2\n\t"
"jmp\t%%%%label(%%l3)"
,
regop_sign_bit_pos
,
rcmp_opstr
)
;
}
else
if
(
code
==
GT
||
code
==
GE
)
{
if
(
is_near
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t%%l3, %%1, %d\n\t"
"%s\t%%l3, %%1, %%u2"
,
regop_sign_bit_pos
,
cmp_opstr
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+8, %%1, %d\n\t"
"%s\t.+8, %%1, %%u2\n\t"
"jmp\t%%%%label(%%l3)"
,
regop_sign_bit_pos
,
rcmp_opstr
)
;
}
else
gcc_unreachable
(
)
;
return
buf
;
}
</s>

Optimized version of pru_output_signed_cbranch for constant second operand .


"Can only put epilog before 'ret' instruction!"


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> bool AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) ) return false ; return getTargetMachine ( ) . getOptLevel ( ) != 0 ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> static rtx_insn * gen_and2_insn ( rtx x , rtx y ) { enum insn_code icode = optab_handler ( and_optab , GET_MODE ( x ) ) ; gcc_assert ( insn_operand_matches ( icode , 0 , x ) ) ; gcc_assert ( insn_operand_matches ( icode , 1 , x ) ) ; gcc_assert ( insn_operand_matches ( icode , 2 , y ) ) ; return GEN_FCN ( icode ) ( x , x , y ) ; } </s>

Generate and return an insn body to AND X with Y .


<s>
static
void
ix86_code_end
(
void
)
{
rtx
xops
[
2
]
;
int
regno
;
for
(
regno
=
AX_REG
;
regno
<=
SP_REG
;
regno
++
)
{
char
name
[
32
]
;
tree
decl
;
if
(
!
(
pic_labels_used
&
(
1
<<
regno
)
)
)
continue
;
get_pc_thunk_name
(
name
,
regno
)
;
decl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
name
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
DECL_RESULT
(
decl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
DECL_IGNORED_P
(
decl
)
=
1
;
if
(
TARGET_MACHO
)
{
switch_to_section
(
darwin_sections
[
picbase_thunk_section
]
)
;
fputs
(
"\t.weak_definition\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
fputs
(
"\n\t.private_extern\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
DECL_WEAK
(
decl
)
=
1
;
}
else
if
(
USE_HIDDEN_LINKONCE
)
{
cgraph_node
::
create
(
decl
)
->
set_comdat_group
(
DECL_ASSEMBLER_NAME
(
decl
)
)
;
targetm
.
asm_out
.
unique_section
(
decl
,
0
)
;
switch_to_section
(
get_named_section
(
decl
,
,
0
)
)
;
targetm
.
asm_out
.
globalize_label
(
asm_out_file
,
name
)
;
fputs
(
"\t.hidden\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_DECLARE_FUNCTION_NAME
(
asm_out_file
,
name
,
decl
)
;
}
else
{
switch_to_section
(
text_section
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
}
DECL_INITIAL
(
decl
)
=
make_node
(
BLOCK
)
;
current_function_decl
=
decl
;
allocate_struct_function
(
decl
,
false
)
;
init_function_start
(
decl
)
;
cfun
->
is_thunk
=
true
;
first_function_block_is_cold
=
false
;
final_start_function
(
emit_barrier
(
)
,
asm_out_file
,
1
)
;
if
(
TARGET_PAD_SHORT_FUNCTION
)
{
int
i
=
8
;
while
(
i
)
fputs
(
"\tnop\n"
,
asm_out_file
)
;
}
xops
[
0
]
=
gen_rtx_REG
(
Pmode
,
regno
)
;
xops
[
1
]
=
gen_rtx_MEM
(
Pmode
,
stack_pointer_rtx
)
;
output_asm_insn
(
"mov%z0\t{%1, %0|%0, %1}"
,
xops
)
;
output_asm_insn
(
"%!ret"
,
)
;
final_end_function
(
)
;
init_insn_lengths
(
)
;
free_after_compilation
(
cfun
)
;
set_cfun
(
)
;
current_function_decl
=
;
}
if
(
flag_split_stack
)
file_end_indicate_split_stack
(
)
;
}
</s>

This function generates code for -fpic that loads % ebx with the return address of the caller and then returns .


<s> static bool mep_mentioned_p ( rtx in , rtx reg , int modes_too ) { const char * fmt ; int i ; enum rtx_code code ; if ( in == 0 ) return false ; if ( reg && GET_CODE ( reg ) != REG ) return false ; if ( GET_CODE ( in ) == LABEL_REF ) return ( reg == 0 ) ; code = GET_CODE ( in ) ; switch ( code ) { case MEM : if ( reg ) return mep_mentioned_p ( XEXP ( in , 0 ) , reg , modes_too ) ; return true ; case REG : if ( ! reg ) return false ; if ( modes_too && ( GET_MODE ( in ) != GET_MODE ( reg ) ) ) return false ; return ( REGNO ( in ) == REGNO ( reg ) ) ; case SCRATCH : case CC0 : case PC : case CONST_INT : case CONST_DOUBLE : return false ; default : break ; } if ( code == SET && ! reg ) return mep_mentioned_p ( SET_DEST ( in ) , reg , modes_too ) ; fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( in , i ) - 1 ; j >= 0 ; j -- ) if ( mep_mentioned_p ( XVECEXP ( in , i , j ) , reg , modes_too ) ) return true ; } else if ( fmt [ i ] == 'e' && mep_mentioned_p ( XEXP ( in , i ) , reg , modes_too ) ) return true ; } return false ; } </s>


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( ( DataWidth == 32 || DataWidth == 64 ) && ST -> hasAVX ( ) ) || ( ( DataWidth == 8 || DataWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool isThumb ( ) const { return getSTI ( ) . getFeatureBits ( ) [ ARM :: ModeThumb ] ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> const char * arm_strip_name_encoding ( const char * name ) { int skip ; while ( ( skip = arm_get_strip_length ( * name ) ) ) name += skip ; return name ; } </s>

Return a pointer to a function 's name with any and all prefix encodings stripped from it .


<s> unsigned LEGInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - 8 ) ; SrcML = MachineLocation ( Mips :: S1 ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - 12 ) ; SrcML = MachineLocation ( Mips :: S0 ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - 4 ) ; SrcML = MachineLocation ( Mips :: RA ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) ; const MipsABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , 1 ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static void iq2000_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_CODE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , Pmode , TRAMPOLINE_CODE_SIZE ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , Pmode , TRAMPOLINE_CODE_SIZE + GET_MODE_SIZE ( Pmode ) ) ; emit_move_insn ( mem , chain_value ) ; } </s>


<s> Register LanaiMachineFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & Lanai :: GPRRegClass ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
bool
AArch64InstrInfo
::
isLdStPairSuppressed
(
const
MachineInstr
*
MI
)
const
{
assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
&&
"Too many target MO flags"
)
;
for
(
auto
*
MM
:
MI
->
memoperands
(
)
)
{
if
(
MM
->
getFlags
(
)
&
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
)
{
return
true
;
}
}
return
false
;
}
</s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s> static bool isPairedLdSt ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : return false ; case AArch64 :: LDPSi : case AArch64 :: LDPSWi : case AArch64 :: LDPDi : case AArch64 :: LDPQi : case AArch64 :: LDPWi : case AArch64 :: LDPXi : case AArch64 :: STPSi : case AArch64 :: STPDi : case AArch64 :: STPQi : case AArch64 :: STPWi : case AArch64 :: STPXi : return true ; } } </s>

Returns whether the instruction is a paired load/store .


<s> static bool arm_function_value_regno_p ( const unsigned int regno ) { if ( regno == ARG_REGISTER ( 1 ) || ( TARGET_32BIT && TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT && regno == FIRST_VFP_REGNUM ) || ( TARGET_IWMMXT_ABI && regno == FIRST_IWMMXT_REGNUM ) ) return true ; return false ; } </s>


<s> const char * SICTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case SICISD :: JmpLink : return "SICISD::JmpLink" ; case SICISD :: TailCall : return "SICISD::TailCall" ; case SICISD :: Hi : return "SICISD::Hi" ; case SICISD :: Lo : return "SICISD::Lo" ; case SICISD :: GPRel : return "SICISD::GPRel" ; case SICISD :: Glob : return "SICISD::Glob" ; case SICISD :: Ret : return "SICISD::Ret" ; case SICISD :: EH_RETURN : return "SICISD::EH_RETURN" ; case SICISD :: DivRem : return "SICISD::DivRem" ; case SICISD :: DivRemU : return "SICISD::DivRemU" ; case SICISD :: Wrapper : return "SICISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

SIC SIC SICISD::JmpLink "SICISD::JmpLink" SICISD::TailCall "SICISD::TailCall" SICISD::Hi "SICISD::Hi" SICISD::Lo "SICISD::Lo" SICISD::GPRel "SICISD::GPRel" SICISD::Glob "SICISD::Glob" SICISD::Ret "SICISD::Ret" SICISD::EH_RETURN "SICISD::EH_RETURN" SICISD::DivRem "SICISD::DivRem" SICISD::DivRemU "SICISD::DivRemU" SICISD::Wrapper "SICISD::Wrapper"


<s> bool runOnMachineFunction ( MachineFunction & F ) override { AArch64FI = F . getInfo < AArch64FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction ( F ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> static bool arm_bfi_p ( rtx x , rtx * sub0 , rtx * sub1 ) { if ( GET_CODE ( x ) != IOR ) return false ; if ( GET_CODE ( XEXP ( x , 0 ) ) != AND || GET_CODE ( XEXP ( x , 1 ) ) != AND ) return false ; return ( arm_bfi_1_p ( XEXP ( x , 0 ) , XEXP ( x , 1 ) , sub0 , sub1 ) || arm_bfi_1_p ( XEXP ( x , 1 ) , XEXP ( x , 0 ) , sub1 , sub0 ) ) ; } </s>

Recognize a BFI idiom . Helper for arm_rtx_costs_internal . The format looks something like : ( IOR ( AND ( reg1 ) ( ~const1 ) ) ( AND ( ASHIFT ( reg2 ) ( const2 ) ) ( const1 ) ) ) where const1 is a consecutive sequence of 1-bits with the least-significant non-zero bit starting at bit position const2 . If const2 is zero , then the shift will not appear at all , due to canonicalization . The two arms of the IOR expression may be flipped .


<s> StackOffset SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> hasStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } else { FrameReg = SP :: O6 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


<s>
bool
ARMAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
&&
MO
.
getReg
(
)
!=
ARM
::
CPSR
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
{
MCOp
=
GetSymbolRef
(
MO
,
GetARMGVSymbol
(
MO
.
getGlobal
(
)
,
MO
.
getTargetFlags
(
)
)
)
;
break
;
}
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
GetSymbolRef
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

ARM
ARM
"unknown operand type"
ARM::CPSR
"Subregs should be eliminated!"
ARM


<s> static bool aarch64_advsimd_struct_mode_p ( machine_mode mode ) { return ( TARGET_SIMD && ( mode == OImode || mode == CImode || mode == XImode ) ) ; } </s>

Return true if MODE is any of the Advanced SIMD structure modes .


<s> bool isLittleEndian ( ) const { return IsLittle ; } </s>

Tests whether the target triple is little endian .


<s> const uint16_t * OR1KRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( * MF ) ; return TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ; } </s>


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s> static int enough_regs_for_param ( CUMULATIVE_ARGS * cum , tree type , enum machine_mode mode ) { int type_size ; int remaining_size ; if ( mode != BLKmode ) type_size = GET_MODE_BITSIZE ( mode ) ; else type_size = int_size_in_bytes ( type ) * BITS_PER_UNIT ; remaining_size = BITS_PER_WORD * ( MAX_REG_FOR_PASSING_ARGS - ( MIN_REG_FOR_PASSING_ARGS + cum -> ints ) + 1 ) ; if ( ( remaining_size >= type_size ) && ( type_size <= 2 * BITS_PER_WORD ) ) return ( type_size + BITS_PER_WORD - 1 ) / BITS_PER_WORD ; return 0 ; } </s>

If enough param regs are available for passing the param of type TYPE return * the number of registers needed else 0 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 EFLAGS copy lowering"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const ARMBaseInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


<s>
SDValue
OpenRISCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_OpenRISC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
OpenRISCISD
::
RET_FLAG
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
Reg
)
;
if
(
STI
.
getFeatureBits
(
)
[
ARM
::
HasMVEIntegerOps
]
)
return
RegNo
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isDFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
bit_cast
<
double
>
(
MO
.
getDFPImm
(
)
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool X86FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || ( hasFP ( MF ) && ! TRI -> needsStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern :: MC_PATTERN > & Patterns ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( ! Root . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ) return false ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> void rs6000_xcoff_declare_object_name ( FILE * file , const char * name , tree decl ) { struct declare_alias_data data = { file , false } ; ASM_OUTPUT_LABEL ( file , name ) ; symtab_node :: get_create ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; } </s>

This macro produces the initial definition of a object ( variable ) name . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> int attr_length_call ( rtx insn , int sibcall ) { int local_call ; rtx call_dest ; tree call_decl ; int length = 0 ; rtx pat = PATTERN ( insn ) ; unsigned long distance = - 1 ; if ( INSN_ADDRESSES_SET_P ( ) ) { unsigned long total ; total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == CALL ) call_dest = XEXP ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) , 0 ) ; else call_dest = XEXP ( XEXP ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) , 0 ) , 0 ) ; call_decl = SYMBOL_REF_DECL ( call_dest ) ; local_call = call_decl && ( * targetm . binds_local_p ) ( call_decl ) ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! sibcall && distance < 7600000 ) || distance < 240000 ) ) length += 8 ; else if ( TARGET_64BIT && ! local_call ) length += sibcall ? 28 : 24 ; else if ( ( TARGET_LONG_ABS_CALL || local_call ) && ! flag_pic ) length += 12 ; else if ( ( TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL ) || ( TARGET_64BIT && ! TARGET_GAS ) || ( TARGET_GAS && ( TARGET_LONG_PIC_PCREL_CALL || local_call ) ) ) { length += 20 ; if ( ! TARGET_PA_20 && ! TARGET_NO_SPACE_REGS ) length += 8 ; } else { length += 32 ; if ( TARGET_SOM ) length += length_fp_args ( insn ) ; if ( flag_pic ) length += 4 ; if ( ! TARGET_PA_20 ) { if ( ! sibcall ) length += 8 ; if ( ! TARGET_NO_SPACE_REGS ) length += 8 ; } } return length ; } </s>

Return the attribute length of the call instruction INSN . The SIBCALL flag indicates whether INSN is a regular call or a sibling call . The length returned must be longer than the code actually generated by output_call . Since branch shortening is done before delay branch sequencing , there is no way to determine whether or not the delay slot will be filled during branch shortening . Even when the delay slot is filled , we may have to add a nop if the delay slot contains a branch that ca n't reach its target . Thus , we always have to include the delay slot in the length estimate . This used to be done in pa_adjust_insn_length but we do it here now as some sequences always fill the delay slot and we can save four bytes in the estimate for these sequences .


<s> bool aarch64_operands_ok_for_ldpstp ( rtx * operands , bool load , machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; enum reg_class rclass_1 , rclass_2 ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) ) return false ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < 8 * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; gcc_assert ( known_eq ( GET_MODE_SIZE ( GET_MODE ( mem_1 ) ) , GET_MODE_SIZE ( GET_MODE ( mem_2 ) ) ) ) ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( ! aarch64_mem_pair_operand ( mem_1 , GET_MODE ( mem_1 ) ) && ! aarch64_mem_pair_operand ( mem_2 , GET_MODE ( mem_2 ) ) ) return false ; if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 ) ) ) rclass_2 = FP_REGS ; else rclass_2 = GENERAL_REGS ; if ( rclass_1 != rclass_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into ldp/stp . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s> bool TeeRISCFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool ThumbRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const ARMSubtarget & STI = MBB . getParent ( ) -> getSubtarget < ARMSubtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: saveScavengerRegister ( MBB , I , UseMI , RC , Reg ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( ARMCC :: AL ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) . add ( predOps ( ARMCC :: AL ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const OR1KTargetMachine * TM = static_cast < const OR1KTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; OR1KMachineFunctionInfo * OR1KFI = MF . getInfo < OR1KMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = OR1KFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const OR1KInstrInfo * TII = TM -> getInstrInfo ( ) ; unsigned Scratch1 = RegInfo . createVirtualRegister ( & OR1K :: GPRRegClass ) ; unsigned Scratch2 = RegInfo . createVirtualRegister ( & OR1K :: GPRRegClass ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: GETPC ) ) . addImm ( 0 ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: MOVHI ) , Scratch1 ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , OR1KII :: MO_GOTPCHI ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: ORI ) , Scratch2 ) . addReg ( Scratch1 ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , OR1KII :: MO_GOTPCLO ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: ADD ) , GlobalBaseReg ) . addReg ( OR1K :: R9 ) . addReg ( Scratch2 ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> InstructionCost SystemZTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { InstructionCost Cost = getVectorIntrinsicInstrCost ( ICA . getID ( ) , ICA . getReturnType ( ) ) ; if ( Cost != - 1 ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> static void mips_output_args_xfer ( int fp_code , char direction ) { unsigned int gparg , fparg , f ; CUMULATIVE_ARGS cum ; gcc_assert ( TARGET_OLDABI ) ; mips_init_cumulative_args ( & cum , NULL ) ; for ( f = ( unsigned int ) fp_code ; f != 0 ; f >>= 2 ) { machine_mode mode ; struct mips_arg_info info ; if ( ( f & 3 ) == 1 ) mode = SFmode ; else if ( ( f & 3 ) == 2 ) mode = DFmode ; else gcc_unreachable ( ) ; mips_get_arg_info ( & info , & cum , mode , NULL , true ) ; gparg = mips_arg_regno ( & info , false ) ; fparg = mips_arg_regno ( & info , true ) ; if ( mode == SFmode ) mips_output_32bit_xfer ( direction , gparg , fparg ) ; else mips_output_64bit_xfer ( direction , gparg , fparg ) ; mips_function_arg_advance ( pack_cumulative_args ( & cum ) , mode , NULL , true ) ; } } </s>

Write out code to move floating-point arguments into or out of general registers . FP_CODE is the code describing which arguments are present ( see the comment above the definition of CUMULATIVE_ARGS in mips.h ) . DIRECTION is as for mips_output_32bit_xfer .


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) { SDValue LHS = Op . getOperand ( 0 ) ; SDValue RHS = Op . getOperand ( 1 ) ; if ( Op -> getOpcode ( ) == ARMISD :: ADDE && isNullConstant ( LHS ) && isNullConstant ( RHS ) ) { Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; return ; } } break ; case ARMISD :: CMOV : { Known = DAG . computeKnownBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( 1 ) , Depth + 1 ) ; Known . Zero &= KnownRHS . Zero ; Known . One &= KnownRHS . One ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case ARMISD :: BFI : { Known = DAG . computeKnownBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .

ARM
ARM
256
"\n"
"unexpected instruction to relax: "


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> GetInstSizeInBytes ( J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s>
static
int
match_const_restriction
(
typeinfo
*
typedata
)
{
int
oldpos
=
pos
;
if
(
linebuf
[
pos
]
==
'<'
)
{
safe_inc_pos
(
)
;
oldpos
=
pos
;
char
*
x
=
match_integer
(
)
;
if
(
x
==
)
{
diag
(
oldpos
,
"malformed integer.\n"
)
;
return
0
;
}
consume_whitespace
(
)
;
if
(
linebuf
[
pos
]
==
'>'
)
{
typedata
->
restr
=
RES_BITS
;
typedata
->
val1
=
x
;
safe_inc_pos
(
)
;
return
1
;
}
else
if
(
linebuf
[
pos
]
!=
','
)
{
diag
(
pos
,
"malformed restriction.\n"
)
;
return
0
;
}
safe_inc_pos
(
)
;
oldpos
=
pos
;
char
*
y
=
match_integer
(
)
;
if
(
y
==
)
{
diag
(
oldpos
,
"malformed integer.\n"
)
;
return
0
;
}
typedata
->
restr
=
RES_RANGE
;
typedata
->
val1
=
x
;
typedata
->
val2
=
y
;
consume_whitespace
(
)
;
if
(
linebuf
[
pos
]
!=
'>'
)
{
diag
(
pos
,
"malformed restriction.\n"
)
;
return
0
;
}
safe_inc_pos
(
)
;
return
1
;
}
else
if
(
match_bracketed_pair
(
typedata
,
'{'
,
'}'
,
RES_VALUES
)
||
match_bracketed_pair
(
typedata
,
'['
,
']'
,
RES_VAR_RANGE
)
)
return
1
;
return
0
;
}
</s>

A const int argument may be restricted to certain values . This is indicated by one of the following occurring after the `` int ' token : < x > restricts the constant to x bits , interpreted as unsigned < x , y > restricts the constant to the inclusive range [ x , y ] [ x , y ] restricts the constant to the inclusive range [ x , y ] , but only applies if the argument is constant . { x , y } restricts the constant to one of two values , x or y . Here x and y are integer tokens . Note that the `` const '' token is a lie when the restriction is [ x , y ] , but this simplifies the parsing significantly and is hopefully forgivable . Return 1 for success , else 0 .


<s> void mips_expand_vcondv2sf ( rtx dest , rtx true_src , rtx false_src , enum rtx_code cond , rtx cmp_op0 , rtx cmp_op1 ) { rtx cmp_result ; bool reversed_p ; reversed_p = mips_reversed_fp_cond ( & cond ) ; cmp_result = mips_allocate_fcc ( CCV2mode ) ; emit_insn ( gen_scc_ps ( cmp_result , gen_rtx_fmt_ee ( cond , VOIDmode , cmp_op0 , cmp_op1 ) ) ) ; if ( reversed_p ) emit_insn ( gen_mips_cond_move_tf_ps ( dest , false_src , true_src , cmp_result ) ) ; else emit_insn ( gen_mips_cond_move_tf_ps ( dest , true_src , false_src , cmp_result ) ) ; } </s>

Implement : ( set temp ( COND : CCV2 CMP_OP0 CMP_OP1 ) ) ( set DEST ( unspec [ TRUE_SRC FALSE_SRC temp ] UNSPEC_MOVE_TF_PS ) )


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> unsigned int pure_scalable_type_info :: num_zr ( ) const { unsigned int res = 0 ; for ( unsigned int i = 0 ; i < pieces . length ( ) ; ++ i ) res += pieces [ i ] . num_zr ; return res ; } </s>

Return the total number of vector registers required by the PST .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void MipsTargetMachine :: resetSubtarget ( MachineFunction * MF ) { DEBUG ( dbgs ( ) << "resetSubtarget\n" ) ; Subtarget = const_cast < MipsSubtarget * > ( getSubtargetImpl ( * MF -> getFunction ( ) ) ) ; MF -> setSubtarget ( Subtarget ) ; return ; } </s>

Reset the subtarget for the Mips target .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const auto * DefaultSuperclass = TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; if ( Subtarget . hasVSX ( ) ) { if ( TM . isELFv2ABI ( ) || Subtarget . isAIXABI ( ) ) { if ( Subtarget . hasP9Vector ( ) && EnableGPRToVecSpills && RC == & PPC :: G8RCRegClass ) { InflateGP8RC ++ ; return & PPC :: SPILLTOVSRRCRegClass ; } if ( RC == & PPC :: GPRCRegClass && EnableGPRToVecSpills ) InflateGPRC ++ ; } for ( const auto * I = RC -> getSuperClasses ( ) ; * I ; ++ I ) { if ( getRegSizeInBits ( * * I ) != getRegSizeInBits ( * RC ) ) continue ; switch ( ( * I ) -> getID ( ) ) { case PPC :: VSSRCRegClassID : return Subtarget . hasP8Vector ( ) ? * I : DefaultSuperclass ; case PPC :: VSFRCRegClassID : case PPC :: VSRCRegClassID : return * I ; case PPC :: VSRpRCRegClassID : return Subtarget . pairedVectorMemops ( ) ? * I : DefaultSuperclass ; case PPC :: ACCRCRegClassID : case PPC :: UACCRCRegClassID : return Subtarget . hasMMA ( ) ? * I : DefaultSuperclass ; } } } return DefaultSuperclass ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::G8RCRegClass PPC::SPILLTOVSRRCRegClass PPC::GPRCRegClass PPC::VSSRCRegClassID PPC::VSFRCRegClassID PPC::VSRCRegClassID PPC::VSRpRCRegClassID PPC::ACCRCRegClassID PPC::UACCRCRegClassID


Value should be nonzero if functions must have frame pointers . Zero means the frame pointer need not be set up ( and parms may be accessed via the stack pointer ) in functions that seem suitable .


<s> static void mips_select_rtx_section ( enum machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( TARGET_MIPS16 ) { function_section ( current_function_decl ) ; } else if ( TARGET_EMBEDDED_DATA ) { mergeable_constant_section ( mode , align , 0 ) ; } else { if ( GET_MODE_SIZE ( mode ) <= ( unsigned ) mips_section_threshold && mips_section_threshold > 0 ) named_section ( 0 , ".sdata" , 0 ) ; else if ( flag_pic && symbolic_expression_p ( x ) ) named_section ( 0 , ".data.rel.ro" , 3 ) ; else mergeable_constant_section ( mode , align , 0 ) ; } } </s>

Choose the section to use for the constant rtx expression X that has mode MODE .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "use-soft-float" ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> static bool isReassociationCandidate ( const MachineInstr & Inst , bool & Commuted ) { if ( isAssociativeAndCommutative ( Inst ) && hasReassociableOperands ( Inst , Inst . getParent ( ) ) && hasReassociableSibling ( Inst , Commuted ) ) return true ; return false ; } </s>

Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociation , otherwise return false .


<s>
void
ix86_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
char
*
target_string
=
ix86_target_string
(
ptr
->
x_ix86_isa_flags
,
ptr
->
x_ix86_isa_flags2
,
ptr
->
x_target_flags
,
ptr
->
x_ix86_target_flags
,
,
,
ptr
->
x_ix86_fpmath
,
ptr
->
x_prefer_vector_width_type
,
ptr
->
x_ix86_move_max
,
ptr
->
x_ix86_store_max
,
false
,
true
)
;
gcc_assert
(
ptr
->
arch
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*sarch = %d (%s)\n"
,
indent
,
""
,
ptr
->
arch
,
processor_names
[
ptr
->
arch
]
)
;
gcc_assert
(
ptr
->
tune
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*stune = %d (%s)\n"
,
indent
,
""
,
ptr
->
tune
,
processor_names
[
ptr
->
tune
]
)
;
fprintf
(
file
,
"%*sbranch_cost = %d\n"
,
indent
,
""
,
ptr
->
branch_cost
)
;
if
(
target_string
)
{
fprintf
(
file
,
"%*s%s\n"
,
indent
,
""
,
target_string
)
;
free
(
target_string
)
;
}
}
</s>


<s> void mips_final_prescan_insn ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPEC_CONSTTABLE ) mips_set_text_contents_type ( asm_out_file , "__pool_" , INTVAL ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) , FALSE ) ; if ( mips_need_noat_wrapper_p ( insn , opvec , noperands ) ) mips_push_asm_switch ( & mips_noat ) ; } </s>


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I , * this ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( createX86InstructionSelector ( * this , * I , * RBI ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % Align ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI . ensureMaxAlignment ( Align ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


"insertBranch must not be told to insert a fallthrough"

"X86 branch conditions have one component!"

"Unconditional branch with multiple successors!"

"MBB cannot be the last block in function when the false "

Insert branch code into the end of the specified MachineBasicBlock .


<s> static bool aarch64_base_register_rtx_p ( rtx x , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && aarch64_regno_ok_for_base_p ( REGNO ( x ) , strict_p ) ) ; } </s>

Return true if X is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s>
static
void
addPredicate
(
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops: Adding VPT Predicate: "
<<
*
MI
)
;
CurrentPredicates
.
insert
(
MI
)
;
}
</s>


<s> bool hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) KnownZero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : KnownZero = ~ 1U ; break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> struct xstormy16_stack_layout xstormy16_compute_stack_layout ( ) { struct xstormy16_stack_layout layout ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; layout . locals_size = get_frame_size ( ) ; layout . register_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) layout . register_save_size += UNITS_PER_WORD ; if ( current_function_varargs || current_function_stdarg ) layout . stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ; else layout . stdarg_save_size = 0 ; layout . frame_size = ( layout . locals_size + layout . register_save_size + layout . stdarg_save_size ) ; if ( current_function_args_size <= 2048 && current_function_args_size != - 1 ) { if ( layout . frame_size + INCOMING_FRAME_SP_OFFSET + current_function_args_size <= 2048 ) layout . fp_minus_ap = layout . frame_size + INCOMING_FRAME_SP_OFFSET ; else layout . fp_minus_ap = 2048 - current_function_args_size ; } else layout . fp_minus_ap = ( layout . stdarg_save_size + layout . register_save_size + INCOMING_FRAME_SP_OFFSET ) ; layout . sp_minus_fp = ( layout . frame_size + INCOMING_FRAME_SP_OFFSET - layout . fp_minus_ap ) ; layout . first_local_minus_ap = layout . sp_minus_fp - layout . locals_size ; return layout ; } </s>


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
int
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
RoundUpToAlignment
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool aarch64_mode_valid_for_sched_fusion_p ( machine_mode mode ) { return mode == SImode || mode == DImode || mode == SFmode || mode == DFmode || ( aarch64_vector_mode_supported_p ( mode ) && known_eq ( GET_MODE_SIZE ( mode ) , 8 ) ) ; } </s>

Return true if MODE is one of the modes for which we support LDP/STP operations .


<s> SDValue SystemZDAGToDAGISel :: getUNDEF ( SDLoc DL , EVT VT ) const { SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , VT ) ; return SDValue ( N , 0 ) ; } </s>

Return an UNDEF node . UNDEF does not have a useful SDLoc .