<s> bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( SYMBOL_REF_P ( XVECEXP ( x , 0 , 0 ) ) && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base_oac && tocrel_offset_oac != const0_rtx ) { if ( INTVAL ( tocrel_offset_oac ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset_oac ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s> TargetPassConfig * Cpu0TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Cpu0PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool XNCMFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> DLXSubtarget & DLXSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> virtual void EmitInstruction ( const MCInst & Inst ) { if ( InstPrinter ) InstPrinter -> printInst ( & Inst , OS , "" ) ; else Inst . print ( OS , & MAI ) ; EmitEOL ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static void xputenv ( const char * string ) { if ( verbose ) fprintf ( stderr , "%s\n" , string ) ; putenv ( CONST_CAST ( char * , string ) ) ; } </s>

Add or change the value of an environment variable , outputting the change to standard error if in verbose mode .


<s> static bool sh_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( ! ALLOW_INDEXED_ADDRESS && GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REG_P ( XEXP ( x , 1 ) ) ) return false ; if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return true ; if ( MAYBE_BASE_REGISTER_RTX_P ( x , strict ) ) return true ; else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) && ! TARGET_SHMEDIA && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( x , 0 ) , strict ) ) return true ; else if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; if ( REG_P ( xop0 ) && REGNO ( xop0 ) == GBR_REG ) return gbr_displacement ( xop1 , mode ) ; if ( GET_MODE_SIZE ( mode ) <= 8 && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) && sh_legitimate_index_p ( mode , xop1 , TARGET_SH2A , false ) ) return true ; if ( ( ALLOW_INDEXED_ADDRESS || GET_MODE ( x ) == DImode || ( ( xop0 == stack_pointer_rtx || xop0 == hard_frame_pointer_rtx ) && REG_P ( xop1 ) && REGNO ( xop1 ) == R0_REG ) || ( ( xop1 == stack_pointer_rtx || xop1 == hard_frame_pointer_rtx ) && REG_P ( xop0 ) && REGNO ( xop0 ) == R0_REG ) ) && ( ( ! TARGET_SHMEDIA && GET_MODE_SIZE ( mode ) <= 4 ) || ( TARGET_SHMEDIA && GET_MODE_SIZE ( mode ) <= 8 ) || ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && mode == DFmode ) ) ) { if ( MAYBE_BASE_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_INDEX_REGISTER_RTX_P ( xop0 , strict ) ) return true ; if ( MAYBE_INDEX_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) ) return true ; } } return false ; } </s>

Recognize an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . Allow REG REG+disp REG+r0 REG++ -- REG GBR GBR+disp


<s> OperandMatchResultTy SparcAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = Parser . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; unsigned regKind = SparcOperand :: rk_None ; if ( matchRegisterName ( Tok , RegNo , regKind ) ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


<s> bool ix86_operands_ok_for_move_multiple ( rtx * operands , bool load , enum machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) != REGNO ( reg_2 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 + msize != offval_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into move multiple . LOAD is true if they are load instructions . MODE is the mode of memory operands .


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> bool e8_consumed_by_ex_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_STORE : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : case TYPE_MAC : case TYPE_DIV : case TYPE_BRANCH : case TYPE_STORE_MULTIPLE : return n8_consumed_by_ex_p ( consumer , def_reg ) ; default : gcc_unreachable ( ) ; } return reg_overlap_p ( def_reg , use_rtx ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return combineVECTOR_SHUFFLE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: STRICT_FP_ROUND : case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: STRICT_FP_EXTEND : case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
DAG
->
MF
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getMcpu
(
)
;
if
(
Directive
==
PPC
::
MCPU_PWR7
||
Directive
==
PPC
::
MCPU_PWR8
)
return
new
PPCDispatchGroupSBHazardRecognizer
(
II
,
DAG
)
;
if
(
Directive
!=
PPC
::
MCPU_440
&&
Directive
!=
PPC
::
MCPU_A2
&&
Directive
!=
PPC
::
MCPU_E500mc
&&
Directive
!=
PPC
::
MCPU_E5500
)
{
assert
(
DAG
->
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
DAG
)
;
}
return
new
ScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> bool shouldTransformSignedTruncationCheck ( EVT XVT , unsigned KeptBits ) const override { if ( XVT . isVector ( ) ) return false ; auto VTIsOk = [ ] ( EVT VT ) -> bool { return VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 || VT == MVT :: i64 ; } ; MVT KeptBitsVT = MVT :: getIntegerVT ( KeptBits ) ; return VTIsOk ( XVT ) && VTIsOk ( KeptBitsVT ) ; } </s>

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not : ( add x , ( 1 < < ( KeptBits-1 ) ) ) srccond ( 1 < < KeptBits ) Into it 's more traditional form : ( ( x < < C ) a > > C ) dstcond x Return true if we should transform .


<s> static inline HOST_WIDE_INT htm_spr_regno ( enum rs6000_builtins code ) { if ( code == HTM_BUILTIN_GET_TFHAR || code == HTM_BUILTIN_SET_TFHAR ) return TFHAR_REGNO ; else if ( code == HTM_BUILTIN_GET_TFIAR || code == HTM_BUILTIN_SET_TFIAR ) return TFIAR_REGNO ; gcc_assert ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR || code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return TEXASR_REGNO ; } </s>

Return the appropriate SPR regno associated with the given builtin .


"Expected SVE area to be calculated by this point"

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> const SystemZSubtarget * SystemZTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SystemZSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

SystemZ SystemZ SystemZ "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" SystemZ


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case E_SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case E_DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case E_HFmode : if ( ! TARGET_VFP_FP16INST ) break ; mode = SFmode ; * op1 = convert_to_mode ( mode , * op1 , 1 ) ; * op2 = convert_to_mode ( mode , * op2 , 1 ) ; case E_SFmode : case E_DFmode : if ( ! vfp_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! vfp_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


<s> void AArch64PostSelectOptimize :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> TargetPassConfig * ARM64TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new ARM64PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
void
SystemZAsmPrinter
::
emitFunctionEntryLabel
(
)
{
const
SystemZSubtarget
&
Subtarget
=
static_cast
<
const
SystemZSubtarget
&
>
(
MF
->
getSubtarget
(
)
)
;
if
(
Subtarget
.
getTargetTriple
(
)
.
isOSzOS
(
)
)
{
MCContext
&
OutContext
=
OutStreamer
->
getContext
(
)
;
MCSymbol
*
EPMarkerSym
=
OutContext
.
createTempSymbol
(
"CM_"
,
true
)
;
const
MachineFrameInfo
&
MFFrame
=
MF
->
getFrameInfo
(
)
;
bool
IsUsingAlloca
=
MFFrame
.
hasVarSizedObjects
(
)
;
uint8_t
Flags
=
0
;
if
(
IsUsingAlloca
)
Flags
|=
0x04
;
uint32_t
DSASize
=
MFFrame
.
getStackSize
(
)
;
uint32_t
DSAAndFlags
=
DSASize
&
0xFFFFFFE0
;
DSAAndFlags
|=
Flags
;
OutStreamer
->
AddComment
(
"XPLINK Routine Layout Entry"
)
;
OutStreamer
->
emitLabel
(
EPMarkerSym
)
;
OutStreamer
->
AddComment
(
"Eyecatcher 0x00C300C500C500"
)
;
OutStreamer
->
emitIntValueInHex
(
0x00C300C500C500
,
7
)
;
OutStreamer
->
AddComment
(
"Mark Type C'1'"
)
;
OutStreamer
->
emitInt8
(
0xF1
)
;
if
(
OutStreamer
->
isVerboseAsm
(
)
)
{
OutStreamer
->
AddComment
(
"DSA Size 0x"
+
Twine
::
utohexstr
(
DSASize
)
)
;
OutStreamer
->
AddComment
(
"Entry Flags"
)
;
if
(
Flags
&
0x04
)
OutStreamer
->
AddComment
(
"  Bit 2: 1 = Uses alloca"
)
;
else
OutStreamer
->
AddComment
(
"  Bit 2: 0 = Does not use alloca"
)
;
}
OutStreamer
->
emitInt32
(
DSAAndFlags
)
;
}
AsmPrinter
::
emitFunctionEntryLabel
(
)
;
}
</s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> bool OR1KAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool AArch64CallLowering :: isTypeIsValidForThisReturn ( EVT Ty ) const { return Ty . getSizeInBits ( ) == 64 ; } </s>

For targets which support the `` returned '' parameter attribute , returns true if the given type is a valid one to use with `` returned '' .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SystemZ Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SDValue SICTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; } return SDValue ( ) ; } </s>


<s> static int ia64_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = ia64_function_arg_words ( arg . type , arg . mode ) ; int offset = ia64_function_arg_offset ( cum , arg . type , words ) ; if ( cum -> words + offset >= MAX_ARGUMENT_SLOTS ) return 0 ; if ( words + cum -> words + offset <= MAX_ARGUMENT_SLOTS ) return 0 ; return ( MAX_ARGUMENT_SLOTS - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

Return number of bytes , at the beginning of the argument , that must be put in registers . 0 is the argument is entirely in registers or entirely in memory .


<s> static rtx sparc_function_incoming_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { return sparc_function_arg_1 ( cum , mode , type , named , true ) ; } </s>

Handle the TARGET_FUNCTION_INCOMING_ARG target hook .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"LC3b Assembly Printer"
;
}
</s>


<s> unsigned getBaseReg ( ) const { return BaseReg ; } </s>

Get the base register of the pointer value .


<s> static rtx aarch64_gen_unspec_cond ( rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) { rtvec vec = gen_rtvec ( 3 , pred , op0 , op1 ) ; return gen_rtx_UNSPEC ( pred_mode , vec , aarch64_unspec_cond_code ( code ) ) ; } </s>

Return an ( unspec : PRED_MODE [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) expression , where < X > is the operation associated with comparison CODE .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: CMov : return "MipsISD::CMov" ; case MipsISD :: SelectCC : return "MipsISD::SelectCC" ; case MipsISD :: FPSelectCC : return "MipsISD::FPSelectCC" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::Ret "MipsISD::Ret" MipsISD::CMov "MipsISD::CMov" MipsISD::SelectCC "MipsISD::SelectCC" MipsISD::FPSelectCC "MipsISD::FPSelectCC" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::FPRound "MipsISD::FPRound"


<s> const uint32_t * AArch64RegisterInfo :: getNoPreservedMask ( ) const { return CSR_AArch64_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> static int arm_block_set_max_insns ( void ) { if ( optimize_function_for_size_p ( cfun ) ) return 4 ; else return current_tune -> max_insns_inline_memset ; } </s>

Maximum number of instructions to set block of memory .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { short imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( N . getOperand ( 0 ) , LHSKnown ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { DAG . computeKnownBits ( N . getOperand ( 1 ) , RHSKnown ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> const TargetRegisterClass * ThumbRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: getPointerRegClass ( MF , Kind ) ; return & ARM :: tGPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static unsigned char ix86_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( MAYBE_INTEGER_CLASS_P ( rclass ) ) { if ( mode == XFmode ) return ( TARGET_64BIT ? 2 : 3 ) ; else if ( mode == XCmode ) return ( TARGET_64BIT ? 4 : 6 ) ; else return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } else { if ( COMPLEX_MODE_P ( mode ) ) return 2 ; else return 1 ; } } </s>

Implement the TARGET_CLASS_MAX_NREGS hook . On the 80386 , this is the size of MODE in words , except in the FP regs , where a single reg is always enough .


<s> int PPCRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return PPCGenRegisterInfo :: getDwarfRegNumFull ( RegNum , 0 ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned opc = N -> getOpcode ( ) ; switch ( opc ) { default : break ; case ISD :: ADDE : return PerformADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SDIVREM : case ISD :: UDIVREM : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::SDIVREM ISD::UDIVREM


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( * Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
MCFixupKindInfo
&
MINA32AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
MINA32
::
NumTargetFixupKinds
]
=
{
{
"fixup_u8"
,
0
,
8
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool isNonallocatableRegisterCalleeSave ( MCRegister Reg ) const override { return Reg == PPC :: LR || Reg == PPC :: LR8 ; } </s>

Some targets have non-allocatable registers that are n't technically part of the explicit callee saved register list , but should be handled as such in certain cases .


<s> static machine_mode mips_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_PAIRED_SINGLE_FLOAT && mode == SFmode ) return V2SFmode ; if ( ! ISA_HAS_MSA ) return word_mode ; switch ( mode ) { case E_QImode : return V16QImode ; case E_HImode : return V8HImode ; case E_SImode : return V4SImode ; case E_DImode : return V2DImode ; case E_SFmode : return V4SFmode ; case E_DFmode : return V2DFmode ; default : break ; } return word_mode ; } </s>


INSN is being issued in current solution . Account for its impact on the decoder model .


<s> static bool ix86_expand_vec_shift_qihi_constant ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { machine_mode qimode , himode ; HOST_WIDE_INT and_constant , xor_constant ; HOST_WIDE_INT shift_amount ; rtx vec_const_and , vec_const_xor ; rtx tmp , op1_subreg ; rtx ( * gen_shift ) ( rtx , rtx , rtx ) ; rtx ( * gen_and ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor ) ( rtx , rtx , rtx ) ; rtx ( * gen_sub ) ( rtx , rtx , rtx ) ; if ( ! CONST_INT_P ( op2 ) ) return false ; qimode = GET_MODE ( dest ) ; shift_amount = INTVAL ( op2 ) ; if ( shift_amount > 7 ) return false ; gcc_assert ( code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT ) ; xor_constant = 1 << ( 8 - shift_amount - 1 ) ; and_constant = ( code == ASHIFT ? 256 - ( 1 << shift_amount ) : ( 1 << ( 8 - shift_amount ) ) - 1 ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode = V16HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv16hi3 : ( code == ASHIFTRT ) ? gen_ashrv16hi3 : gen_lshrv16hi3 ) ; gen_and = gen_andv32qi3 ; gen_xor = gen_xorv32qi3 ; gen_sub = gen_subv32qi3 ; break ; case V64QImode : himode = V32HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv32hi3 : ( code == ASHIFTRT ) ? gen_ashrv32hi3 : gen_lshrv32hi3 ) ; gen_and = gen_andv64qi3 ; gen_xor = gen_xorv64qi3 ; gen_sub = gen_subv64qi3 ; break ; default : gcc_unreachable ( ) ; } tmp = gen_reg_rtx ( himode ) ; vec_const_and = gen_reg_rtx ( qimode ) ; op1_subreg = lowpart_subreg ( himode , op1 , qimode ) ; emit_insn ( gen_shift ( tmp , op1_subreg , op2 ) ) ; emit_move_insn ( dest , simplify_gen_subreg ( qimode , tmp , himode , 0 ) ) ; emit_move_insn ( vec_const_and , ix86_build_const_vector ( qimode , true , gen_int_mode ( and_constant , QImode ) ) ) ; emit_insn ( gen_and ( dest , dest , vec_const_and ) ) ; if ( code == ASHIFTRT ) { vec_const_xor = gen_reg_rtx ( qimode ) ; emit_move_insn ( vec_const_xor , ix86_build_const_vector ( qimode , true , gen_int_mode ( xor_constant , QImode ) ) ) ; emit_insn ( gen_xor ( dest , dest , vec_const_xor ) ) ; emit_insn ( gen_sub ( dest , dest , vec_const_xor ) ) ; } return true ; } </s>

Expand a vector operation shift by constant for a V * QImode in terms of the same operation on V * HImode . Return true if success .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> static void expand_strncmp_align_check ( rtx strncmp_label , rtx src_addr , HOST_WIDE_INT bytes ) { rtx lab_ref = gen_rtx_LABEL_REF ( VOIDmode , strncmp_label ) ; rtx src_pgoff = gen_reg_rtx ( GET_MODE ( src_addr ) ) ; do_and3 ( src_pgoff , src_addr , GEN_INT ( 0xfff ) ) ; rtx cond = gen_reg_rtx ( CCmode ) ; emit_move_insn ( cond , gen_rtx_COMPARE ( CCmode , src_pgoff , GEN_INT ( 4096 - bytes ) ) ) ; rtx cmp_rtx = gen_rtx_GE ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , lab_ref , pc_rtx ) ; rtx_insn * j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; add_reg_br_prob_note ( j , profile_probability :: unlikely ( ) ) ; JUMP_LABEL ( j ) = strncmp_label ; LABEL_NUSES ( strncmp_label ) += 1 ; } </s>

Generate page crossing check and branch code to set up for strncmp when we do n't have DI alignment . STRNCMP_LABEL is the label to branch if there is a page crossing . SRC_ADDR is the string address to be examined . BYTES is the max number of bytes to compare .


<s> const X86Subtarget & getSubtarget ( ) const { return * Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> static void nds32_group_float_insns ( rtx_insn * insn ) { df_ref def_record , use_record ; df_link * link ; rtx_insn * use_insn = NULL ; rtx group_id ; def_record = DF_INSN_DEFS ( insn ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( ! dominated_by_p ( CDI_DOMINATORS , BLOCK_FOR_INSN ( use_insn ) , BLOCK_FOR_INSN ( insn ) ) ) return ; use_record = DF_INSN_USES ( use_insn ) ; if ( DF_REF_CHAIN ( use_record ) && DF_REF_CHAIN ( use_record ) -> next ) return ; if ( ! active_insn_p ( use_insn ) ) return ; if ( ! nds32_float_reg_load_store_p ( use_insn ) || find_post_update_rtx ( use_insn ) != - 1 ) return ; } group_id = GEN_INT ( nds32_alloc_relax_group_id ( ) ) ; emit_insn_before ( gen_relax_group ( group_id ) , insn ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; emit_insn_before ( gen_relax_group ( group_id ) , use_insn ) ; } } </s>

Group float load-store instructions : la $ ra , symbol flsi $ rt , [ $ ra + offset ]


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> static bool ix86_lea_outperforms ( rtx_insn * insn , unsigned int regno0 , unsigned int regno1 , unsigned int regno2 , int split_cost , bool has_scale ) { int dist_define , dist_use ; if ( ! TARGET_BONNELL ) { if ( has_scale ) return true ; if ( split_cost < 1 ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } struct recog_data_d recog_data_save = recog_data ; dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ; dist_use = distance_agu_use ( regno0 , insn ) ; recog_data = recog_data_save ; if ( dist_define < 0 || dist_define >= LEA_MAX_STALL ) { if ( dist_use < 0 && split_cost == 0 ) return TARGET_64BIT || IX86_LEA_PRIORITY ; else return true ; } dist_define += split_cost + IX86_LEA_PRIORITY ; if ( dist_use < 0 ) return dist_define > LEA_MAX_STALL ; return dist_define >= dist_use ; } </s>

Return true if usage of lea INSN has performance advantage over a sequence of instructions . Instructions sequence has SPLIT_COST cycles higher latency than lea latency .


<s> virtual const SparcRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


" was Pass-through, is now Dirty-out.\n"


<s> bool MipsHazardSchedule :: runOnMachineFunction ( MachineFunction & MF ) { const MipsSubtarget * STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! STI -> hasMips32r6 ( ) || STI -> inMicroMipsMode ( ) ) return false ; bool Changed = false ; const MipsInstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; Iter Inst ; bool LastInstInFunction = std :: next ( I ) == FI -> end ( ) && std :: next ( FI ) == MF . end ( ) ; if ( ! LastInstInFunction ) { Inst = getNextMachineInstr ( std :: next ( I ) , & * FI ) ; } if ( LastInstInFunction || ! TII -> SafeInForbiddenSlot ( * Inst ) ) { Changed = true ; MIBundleBuilder ( & * I ) . append ( BuildMI ( MF , I -> getDebugLoc ( ) , TII -> get ( Mips :: NOP ) ) ) ; NumInsertedNops ++ ; } } } return Changed ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips::NOP


<s> static int do_reorder_for_imul ( rtx_insn * * ready , int n_ready ) { rtx_insn * insn ; rtx set , insn1 , insn2 ; sd_iterator_def sd_it ; dep_t dep ; int index = - 1 ; int i ; if ( ! TARGET_CPU_P ( BONNELL ) ) return index ; insn = ready [ n_ready - 1 ] ; set = single_set ( insn ) ; if ( ! set ) return index ; if ( ! ( GET_CODE ( SET_SRC ( set ) ) == MULT && GET_MODE ( SET_SRC ( set ) ) == SImode ) ) return index ; for ( i = n_ready - 2 ; i >= 0 ; i -- ) { insn = ready [ i ] ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; insn2 = PATTERN ( insn ) ; if ( GET_CODE ( insn2 ) == PARALLEL ) insn2 = XVECEXP ( insn2 , 0 , 0 ) ; if ( GET_CODE ( insn2 ) == SET && GET_CODE ( SET_SRC ( insn2 ) ) == MULT && GET_MODE ( SET_SRC ( insn2 ) ) == SImode ) continue ; FOR_EACH_DEP ( insn , SD_LIST_FORW , sd_it , dep ) { rtx con ; con = DEP_CON ( dep ) ; if ( ! NONDEBUG_INSN_P ( con ) ) continue ; insn1 = PATTERN ( con ) ; if ( GET_CODE ( insn1 ) == PARALLEL ) insn1 = XVECEXP ( insn1 , 0 , 0 ) ; if ( GET_CODE ( insn1 ) == SET && GET_CODE ( SET_SRC ( insn1 ) ) == MULT && GET_MODE ( SET_SRC ( insn1 ) ) == SImode ) { sd_iterator_def sd_it1 ; dep_t dep1 ; index = i ; FOR_EACH_DEP ( con , SD_LIST_BACK , sd_it1 , dep1 ) { rtx pro ; pro = DEP_PRO ( dep1 ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( pro != insn ) index = - 1 ; } if ( index >= 0 ) break ; } } if ( index >= 0 ) break ; } return index ; } </s>

Try to reorder ready list to take advantage of Atom pipelined IMUL execution . It is applied if ( 1 ) IMUL instruction is on the top of list ; ( 2 ) There exists the only producer of independent IMUL instruction in ready list . Return index of IMUL producer if it was found and -1 otherwise .


<s>
void
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI . isThumb1Only ( ) ) return false ; const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = STI . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM::tPICADD ARM::PICADD ARM ARM::PICADD


"No MachineFunctionInfo for this function!"


<s> void changeSection ( MCSection * Section , const MCExpr * Subsection ) override { LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup ( Section ) ; MCELFStreamer :: changeSection ( Section , Subsection ) ; } </s>

Update streamer for a new active section .


<s> static bool or1k_rtx_costs ( rtx x , machine_mode mode , int outer_code , int , int * total , bool ) { switch ( GET_CODE ( x ) ) { case CONST_INT : if ( x == const0_rtx ) * total = 0 ; else if ( ( outer_code == PLUS || outer_code == XOR || outer_code == MULT ) && satisfies_constraint_I ( x ) ) * total = 0 ; else if ( ( outer_code == AND || outer_code == IOR ) && satisfies_constraint_K ( x ) ) * total = 0 ; else if ( satisfies_constraint_I ( x ) || satisfies_constraint_K ( x ) || satisfies_constraint_M ( x ) ) * total = 2 ; else * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : * total = ( x == CONST0_RTX ( mode ) ? 0 : COSTS_N_INSNS ( 2 ) ) ; return true ; case HIGH : * total = 2 ; return true ; case LO_SUM : * total = ( outer_code == MEM ? 0 : 2 ) ; return true ; case CONST : case SYMBOL_REF : case LABEL_REF : if ( outer_code == LO_SUM || outer_code == HIGH ) * total = 0 ; else { * total = COSTS_N_INSNS ( 1 + ( outer_code != MEM ) ) ; } return true ; case PLUS : if ( outer_code == MEM ) * total = 0 ; break ; default : break ; } return false ; } </s>


<s> static void nds32_emit_isr_jmptbl_section ( int vector_id ) { char section_name [ 100 ] ; char symbol_name [ 100 ] ; snprintf ( section_name , sizeof ( section_name ) , ".nds32_jmptbl.%02d" , vector_id ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , "_nds32_jmptbl_%02d" , vector_id ) ; nds32_emit_section_head_template ( section_name , symbol_name , 2 , true ) ; fprintf ( asm_out_file , "\t.word\t%s\n" , nds32_isr_vectors [ vector_id ] . func_name ) ; nds32_emit_section_tail_template ( symbol_name ) ; } </s>

Function to emit isr jump table section .


"Huge values only handled before reg-alloc ."

Emit a series of instructions to load an immediate .


"getJumpOffset16OpValue expects only expressions or an immediate"

getJumpOffset16OpValue - Return binary encoding of the jump target operand .


"invalid feature modifier %qs for 'cpu' target %s"

Handle the argument CPU_STR to the cpu= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> static void record_memory_reference ( rtx_insn * insn ) { enum attr_itanium_class insn_class = ia64_safe_itanium_class ( insn ) ; switch ( insn_class ) { case ITANIUM_CLASS_FLD : case ITANIUM_CLASS_LD : mem_ops_in_group [ current_cycle % 4 ] ++ ; break ; case ITANIUM_CLASS_STF : case ITANIUM_CLASS_ST : mem_ops_in_group [ ( current_cycle + 3 ) % 4 ] ++ ; break ; default : ; } } </s>

If INSN is a memory reference , memoize it in MEM_OPS_IN_GROUP global array ( taking account for 3-cycle cache reference postponing for stores : Intel Itanium 2 Reference Manual for Software Development and Optimization , 6.7.3.1 ) .


<s> static section * rs6000_xcoff_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return read_only_private_data_section ; } </s>

Select section for constant in constant pool . On RS/6000 , all constants are in the private read-only data area . However , if this is being placed in the TOC it must be output as a toc entry .


<s> unsigned PPCAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = 0 ; break ; case MCK_1 : ImmVal = 1 ; break ; case MCK_2 : ImmVal = 2 ; break ; case MCK_3 : ImmVal = 3 ; break ; case MCK_4 : ImmVal = 4 ; break ; case MCK_5 : ImmVal = 5 ; break ; case MCK_6 : ImmVal = 6 ; break ; case MCK_7 : ImmVal = 7 ; break ; default : return Match_InvalidOperand ; } PPCOperand & Op = static_cast < PPCOperand & > ( AsmOp ) ; if ( Op . isImm ( ) && Op . getImm ( ) == ImmVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static tree make_resolver_func ( const tree default_decl , const tree dispatch_decl , basic_block * empty_bb ) { tree decl_name = clone_function_name ( default_decl , "resolver" ) ; const char * resolver_name = IDENTIFIER_POINTER ( decl_name ) ; tree type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; tree decl = build_fn_decl ( resolver_name , type ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 0 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( dispatch_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } else TREE_PUBLIC ( dispatch_decl ) = 0 ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; DECL_ATTRIBUTES ( dispatch_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( dispatch_decl ) ) ; cgraph_node :: create_same_body_alias ( dispatch_decl , decl ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s> static tree make_resolver_func ( const tree default_decl , const tree ifunc_alias_decl , basic_block * empty_bb ) { char * resolver_name ; tree decl , type , decl_name , t ; if ( TREE_PUBLIC ( default_decl ) == 0 ) { char * ifunc_name = make_unique_name ( default_decl , "ifunc" , true ) ; symtab -> change_decl_assembler_name ( ifunc_alias_decl , get_identifier ( ifunc_name ) ) ; XDELETEVEC ( ifunc_name ) ; } resolver_name = make_unique_name ( default_decl , "resolver" , false ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; decl_name = get_identifier ( resolver_name ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( ifunc_alias_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl ) ) ; cgraph_node :: create_same_body_alias ( ifunc_alias_decl , decl ) ; XDELETEVEC ( resolver_name ) ; return decl ; } </s>


<s> bool DLXInstrInfo :: optimizeCompareInstr ( MachineInstr & CmpInstr , unsigned SrcReg , unsigned SrcReg2 , int CmpMask , int CmpValue , const MachineRegisterInfo * MRI ) const { return false ; } </s>

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> bool rs6000_decl_ok_for_sibcall ( tree decl ) { if ( DEFAULT_ABI == ABI_DARWIN ) return true ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( rs6000_pcrel_p ( ) ) return true ; if ( ! decl || DECL_EXTERNAL ( decl ) || DECL_WEAK ( decl ) || ! ( * targetm . binds_local_p ) ( decl ) ) return false ; if ( rs6000_fndecl_pcrel_p ( decl ) ) return false ; return true ; } if ( DEFAULT_ABI != ABI_V4 || ( TARGET_SECURE_PLT && flag_pic && ( ! decl || ! ( ( * targetm . binds_local_p ) ( decl ) ) ) ) ) return false ; return true ; } </s>

Helper function for rs6000_function_ok_for_sibcall .


<s> static unsigned long get_csky_isr_type ( tree argument ) { const isr_attribute_entry * ptr ; const char * arg ; if ( argument == NULL_TREE ) return CSKY_FT_ISR ; if ( TREE_VALUE ( argument ) == NULL_TREE || TREE_CODE ( TREE_VALUE ( argument ) ) != STRING_CST ) return CSKY_FT_UNKNOWN ; arg = TREE_STRING_POINTER ( TREE_VALUE ( argument ) ) ; for ( ptr = isr_attribute_map ; ptr -> arg != NULL ; ptr ++ ) if ( strcmp ( arg , ptr -> arg ) == 0 ) return ptr -> return_value ; return CSKY_FT_UNKNOWN ; } </s>

Return the function type of the current function , if it has not been determined , return CSKY_FT_UNKNOWN .


<s> MCInst Thumb1InstrInfo :: getNop ( ) const { return MCInstBuilder ( ARM :: tMOVr ) . addReg ( ARM :: R8 ) . addReg ( ARM :: R8 ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ; } </s>

Return the noop instruction to use for a noop .


<s>
void
mmix_asm_output_align
(
FILE
*
stream
,
int
power
)
{
fprintf
(
stream
,
"\t.p2align %d\n"
,
power
)
;
fprintf
(
stream
,
"\tLOC @+(%d-@)&%d\n"
,
1
<<
power
,
(
1
<<
power
)
1
)
;
}
</s>


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool useLoadStackGuardNode ( ) const override { return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addReg ( 0 ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( 0U , ARM :: tGPRRegisterClass ) ; else return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , ARM :: QPRRegisterClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( 0U , ARM :: CCRRegisterClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = Subtarget . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


"\n========== quad_load_store, return %s\n"

Return true if this is a load or store quad operation . This function does not handle the atomic quad memory instructions .


<s> static void mips_legitimize_const_move ( machine_mode mode , rtx dest , rtx src ) { rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { mips_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( mips_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { emit_insn ( gen_rtx_SET ( dest , src ) ) ; return ; } if ( mips_tls_symbol_p ( src ) ) { mips_emit_move ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( ! TARGET_MIPS16 && can_create_pseudo_p ( ) ) ) ) { base = mips_force_temporary ( dest , base ) ; mips_emit_move ( dest , mips_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; mips_split_symbol ( dest , XEXP ( src , 0 ) , mode , & XEXP ( src , 0 ) ) ; mips_emit_move ( dest , src ) ; } </s>

Subroutine of mips_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = 0 ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = 0 ; } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum -> force_bnd_pass = nregs ; if ( ! nregs ) cum -> bnds_in_bt = chkp_type_bounds_count ( type ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s>
void
PPCHazardRecognizer970
::
EmitInstruction
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
Opcode
==
PPC
::
MTCTR
)
HasCTRSet
=
true
;
if
(
isStore
)
{
unsigned
ThisStoreSize
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown store instruction!"
)
;
case
PPC
::
STB
:
case
PPC
::
STB8
:
case
PPC
::
STBU
:
case
PPC
::
STBU8
:
case
PPC
::
STBX
:
case
PPC
::
STBX8
:
case
PPC
::
STVEBX
:
ThisStoreSize
=
1
;
break
;
case
PPC
::
STH
:
case
PPC
::
STH8
:
case
PPC
::
STHU
:
case
PPC
::
STHU8
:
case
PPC
::
STHX
:
case
PPC
::
STHX8
:
case
PPC
::
STVEHX
:
case
PPC
::
STHBRX
:
ThisStoreSize
=
2
;
break
;
case
PPC
::
STFS
:
case
PPC
::
STFSU
:
case
PPC
::
STFSX
:
case
PPC
::
STWX
:
case
PPC
::
STWX8
:
case
PPC
::
STWUX
:
case
PPC
::
STW
:
case
PPC
::
STW8
:
case
PPC
::
STWU
:
case
PPC
::
STWU8
:
case
PPC
::
STVEWX
:
case
PPC
::
STFIWX
:
case
PPC
::
STWBRX
:
ThisStoreSize
=
4
;
break
;
case
PPC
::
STD_32
:
case
PPC
::
STDX_32
:
case
PPC
::
STD
:
case
PPC
::
STDU
:
case
PPC
::
STFD
:
case
PPC
::
STFDX
:
case
PPC
::
STDX
:
case
PPC
::
STDUX
:
ThisStoreSize
=
8
;
break
;
case
PPC
::
STVX
:
case
PPC
::
STVXL
:
ThisStoreSize
=
16
;
break
;
}
StoreSize
[
NumStores
]
=
ThisStoreSize
;
StorePtr1
[
NumStores
]
=
Node
->
getOperand
(
1
)
;
StorePtr2
[
NumStores
]
=
Node
->
getOperand
(
2
)
;
++
NumStores
;
}
if
(
InstrType
==
PPCII
::
PPC970_BRU
||
isSingle
)
NumIssued
=
4
;
++
NumIssued
;
if
(
isCracked
)
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const uint32_t * PPCRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
,
end_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
)
;
ASM_GENERATE_INTERNAL_LABEL
(
end_lab
,
"LPSRE"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
if
(
TARGET_ARCH64
)
fputs
(
"\tbe,pn\t%xcc,"
,
asm_out_file
)
;
else
fputs
(
"\tbe\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
end_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
" add\t%0, %1, %0"
,
xops
)
;
if
(
TARGET_ARCH64
)
fputs
(
"\tba,pt\t%xcc,"
,
asm_out_file
)
;
else
fputs
(
"\tba\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
SPARC_STACK_BIAS
)
;
output_asm_insn
(
" st\t%%g0, [%0+%1]"
,
xops
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
end_lab
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> static void sh_emit_set_t_insn ( rtx insn , machine_mode mode ) { if ( TARGET_FPU_ANY && GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_CODE ( insn ) != PARALLEL ) { insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 3 , insn , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( SImode , FPSCR_STAT_REG ) ) , gen_rtx_USE ( VOIDmode , gen_rtx_REG ( SImode , FPSCR_MODES_REG ) ) ) ) ; } emit_insn ( insn ) ; } </s>

Emit INSN , possibly in a PARALLEL with an USE/CLOBBER of FPSCR bits in case of floating-point comparisons .


<s> static struct machine_function * rs6000_init_machine_status ( void ) { stack_info . reload_completed = 0 ; return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Functions to init , mark and free struct machine_function . These will be called , via pointer variables , from push_function_context and pop_function_context .


<s>
const
MCFixupKindInfo
&
OR1KAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
OR1K
::
NumTargetFixupKinds
]
=
{
{
"fixup_OR1K_NONE"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_32"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_8"
,
24
,
8
,
0
}
,
{
"fixup_OR1K_LO16_INSN"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_HI16_INSN"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_REL26"
,
6
,
26
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL16"
,
16
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL8"
,
24
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_GOTPC_HI16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_GOTPC_LO16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_GOT16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_PLT26"
,
6
,
26
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_GOTOFF_HI16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_GOTOFF_LO16"
,
16
,
16
,
0
}
,
{
"fixup_OR1K_COPY"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_GLOB_DAT"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_JMP_SLOT"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_RELATIVE"
,
0
,
32
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> const LC3RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
SparcInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
numSubRegs
=
0
;
unsigned
movOpc
=
0
;
const
unsigned
*
subRegIdx
=
nullptr
;
const
unsigned
DFP_FP_SubRegsIdx
[
]
=
{
SP
::
sub_even
,
SP
::
sub_odd
}
;
const
unsigned
QFP_DFP_SubRegsIdx
[
]
=
{
SP
::
sub_even64
,
SP
::
sub_odd64
}
;
const
unsigned
QFP_FP_SubRegsIdx
[
]
=
{
SP
::
sub_even
,
SP
::
sub_odd
,
SP
::
sub_odd64_then_sub_even
,
SP
::
sub_odd64_then_sub_odd
}
;
if
(
SP
::
IntRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
ORrr
)
,
DestReg
)
.
addReg
(
SP
::
G0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
FPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVS
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
DFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
Subtarget
.
isV9
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVD
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
subRegIdx
=
DFP_FP_SubRegsIdx
;
numSubRegs
=
2
;
movOpc
=
SP
::
FMOVS
;
}
}
else
if
(
SP
::
QFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
Subtarget
.
isV9
(
)
)
{
if
(
Subtarget
.
hasHardQuad
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVQ
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
subRegIdx
=
QFP_DFP_SubRegsIdx
;
numSubRegs
=
2
;
movOpc
=
SP
::
FMOVD
;
}
}
else
{
subRegIdx
=
QFP_FP_SubRegsIdx
;
numSubRegs
=
4
;
movOpc
=
SP
::
FMOVS
;
}
}
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
if
(
numSubRegs
==
0
||
subRegIdx
==
nullptr
||
movOpc
==
0
)
return
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineInstr
*
MovMI
=
nullptr
;
for
(
unsigned
i
=
0
;
i
!=
numSubRegs
;
++
i
)
{
unsigned
Dst
=
TRI
->
getSubReg
(
DestReg
,
subRegIdx
[
i
]
)
;
unsigned
Src
=
TRI
->
getSubReg
(
SrcReg
,
subRegIdx
[
i
]
)
;
assert
(
Dst
&&
Src
&&
"Bad sub-register"
)
;
MovMI
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
movOpc
)
,
Dst
)
.
addReg
(
Src
)
;
}
MovMI
->
addRegisterDefined
(
DestReg
,
TRI
)
;
if
(
KillSrc
)
MovMI
->
addRegisterKilled
(
SrcReg
,
TRI
)
;
}
</s>


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> bool X86TTIImpl :: prefersVectorizedAddressing ( ) const { return supportsGather ( ) ; } </s>

Return true if target does n't mind addresses in vectors .


<s>
bool
ARMTargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeSizeInBits
(
SubVecTy
)
;
bool
EltIs64Bits
=
DL
.
getTypeSizeInBits
(
EltTy
)
==
64
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
||
EltIs64Bits
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
Op0
->
getType
(
)
->
getVectorNumElements
(
)
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
arm_neon_vst2
,
Intrinsic
::
arm_neon_vst3
,
Intrinsic
::
arm_neon_vst4
}
;
SmallVector
<
Value
*
,
6
>
Ops
;
Type
*
Int8Ptr
=
Builder
.
getInt8PtrTy
(
SI
->
getPointerAddressSpace
(
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
Int8Ptr
)
)
;
Type
*
Tys
[
]
=
{
Int8Ptr
,
SubVecTy
}
;
Function
*
VstNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
getInt32
(
SI
->
getAlignment
(
)
)
)
;
Builder
.
CreateCall
(
VstNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> StackOffset VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( FuncInfo -> isLeafProc ( ) ) { FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = VE :: SX17 ; else FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> unsigned int sparc_regmode_natural_size ( machine_mode mode ) { const enum mode_class cl = GET_MODE_CLASS ( mode ) ; if ( ( cl == MODE_FLOAT || cl == MODE_VECTOR_INT ) && GET_MODE_SIZE ( mode ) <= 4 ) return 4 ; return UNITS_PER_WORD ; } </s>

On the SPARC , any mode which naturally allocates into the single float registers should return 4 here .


<s> bool LC2200PassConfig :: addPreISel ( ) { return false ; } </s>


<s> void ix86_split_simple_return_pop_internal ( rtx popc ) { struct machine_function * m = cfun -> machine ; rtx ecx = gen_rtx_REG ( SImode , CX_REG ) ; rtx_insn * insn ; gcc_assert ( ! TARGET_64BIT ) ; insn = emit_insn ( gen_pop ( ecx ) ) ; m -> fs . cfa_offset -= UNITS_PER_WORD ; m -> fs . sp_offset -= UNITS_PER_WORD ; rtx x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( ecx , pc_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , popc ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; insn = emit_insn ( x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_jump_insn ( gen_simple_return_indirect_internal ( ecx ) ) ; } </s>

Split simple return with popping POPC bytes from stack to indirect branch with stack adjustment .


<s> void F2003fRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; Offset += SPAdj ; if ( MI . getOpcode ( ) == F2003f :: ATAframe ) { Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( F2003f :: KRZrr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( F2003f :: F5 , false ) ; MI . RemoveOperand ( FIOperandNum + 1 ) ; if ( Offset == 0 ) { return ; } unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( F2003f :: ATAri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + 2 ) . isImm ( ) ) { Offset += ( int32_t ) MI . getOperand ( FIOperandNum + 2 ) . getImm ( ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( F2003f :: F5 , false ) ; MI . getOperand ( FIOperandNum + 2 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool X86AvoidSFBPass :: alias ( const MachineMemOperand & Op1 , const MachineMemOperand & Op2 ) const { if ( ! Op1 . getValue ( ) || ! Op2 . getValue ( ) ) return true ; int64_t MinOffset = std :: min ( Op1 . getOffset ( ) , Op2 . getOffset ( ) ) ; int64_t Overlapa = Op1 . getSize ( ) + Op1 . getOffset ( ) - MinOffset ; int64_t Overlapb = Op2 . getSize ( ) + Op2 . getOffset ( ) - MinOffset ; AliasResult AAResult = AA -> alias ( MemoryLocation ( Op1 . getValue ( ) , Overlapa , Op1 . getAAInfo ( ) ) , MemoryLocation ( Op2 . getValue ( ) , Overlapb , Op2 . getAAInfo ( ) ) ) ; return AAResult != NoAlias ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


<s> unsigned TOYInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> VETargetMachine :: VETargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( createTLOF ( ) ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) { initAsmInfo ( ) ; } </s>

Create an Aurora VE architecture model .


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
unsigned
StackEst
=
TFI
->
determineFrameLayout
(
MF
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
getBaseRegister
(
MF
)
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> const MCExpr * ARMElfTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_ARM_TLSLDO , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mandarin Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
auto
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
auto
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
LocSize
)
)
;
MIRBuilder
.
buildCopy
(
PhysRegToVReg
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"
"Extensions not supported"


<s> void neon_split_vcombine ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = HARD_REGNO_NREGS ( src1 , halfmode ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( VOIDmode , destlo , operands [ 1 ] ) ; rtx y = gen_rtx_SET ( VOIDmode , desthi , operands [ 2 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x , y ) ) ) ; return ; } if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; } </s>

Return true if the function can safely be outlined from .


<s> static rtx sparc_delegitimize_address ( rtx x ) { x = delegitimize_mem_from_attrs ( x ) ; if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , 1 ) ) == UNSPEC ) switch ( XINT ( XEXP ( x , 1 ) , 1 ) ) { case UNSPEC_MOVE_PIC : case UNSPEC_TLSLE : x = XVECEXP ( XEXP ( x , 1 ) , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; break ; default : break ; } if ( GET_CODE ( x ) == MINUS && sparc_pic_register_p ( XEXP ( x , 0 ) ) && GET_CODE ( XEXP ( x , 1 ) ) == LO_SUM && GET_CODE ( XEXP ( XEXP ( x , 1 ) , 1 ) ) == UNSPEC && XINT ( XEXP ( XEXP ( x , 1 ) , 1 ) , 1 ) == UNSPEC_MOVE_PIC_LABEL ) { x = XVECEXP ( XEXP ( XEXP ( x , 1 ) , 1 ) , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT ) ) ; } return x ; } </s>

Delegitimize an address that was legitimized by the above function .


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool aarch64_bitmask_imm ( HOST_WIDE_INT val , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) < 8 ) { val &= ( HOST_WIDE_INT ) 0xffffffff ; val |= val << 32 ; } return bsearch ( & val , aarch64_bitmasks , AARCH64_NUM_BITMASKS , sizeof ( aarch64_bitmasks [ 0 ] ) , aarch64_bitmasks_cmp ) != NULL ; } </s>

Return true if val is a valid bitmask immediate .


"instructions, but the target does not support ARM mode execution."

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"large return values not supported with %<-mabi=ti%> option"

"function pointers not supported with %<-mabi=ti%> option"

Check the function declaration FNTYPE for TI ABI compatibility .


<s> void PPCInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { const char * RegName = getRegisterName ( RegNo ) ; OS << RegName ; } </s>


<s> static rtx rs6000_savres_routine_sym ( rs6000_stack_t * info , int sel ) { int regno = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save - 32 : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save - FIRST_ALTIVEC_REGNO : - 1 ) ; rtx sym ; int select = sel ; gcc_assert ( FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER && select >= 0 && select <= 12 ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] ; if ( sym == NULL ) { char * name ; name = rs6000_savres_routine_name ( regno , sel ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_FUNCTION ; } return sym ; } </s>

Return an RTL SYMBOL_REF for an out-of-line register save/restore routine . We are saving/restoring GPRs if GPR is true .


<s> bool Thumb2InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , MachineBasicBlock & FMBB , unsigned NumF ) const { return NumT && NumF && NumT <= ( IfCvtDiamondLimit ) && NumF <= ( IfCvtDiamondLimit ) ; } </s>


<s> bool PPCTargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 == 64 && NumBits2 == 32 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> static unsigned int flags_from_mode ( machine_mode mode ) { switch ( mode ) { case CC_ZSmode : return CC_FLAG_S | CC_FLAG_Z ; case CC_ZSOmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O ; case CC_ZSCmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C ; case CCmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C ; case CC_Fmode : return CC_FLAG_FP ; default : gcc_unreachable ( ) ; } } </s>

Convert a CC_MODE to the set of flags that it represents .


<s> void rs6000_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( "PPC64" ) ; else d_add_builtin_version ( "PPC" ) ; if ( TARGET_HARD_FLOAT ) { d_add_builtin_version ( "PPC_HardFloat" ) ; d_add_builtin_version ( "D_HardFloat" ) ; } else if ( TARGET_SOFT_FLOAT ) { d_add_builtin_version ( "PPC_SoftFloat" ) ; d_add_builtin_version ( "D_SoftFloat" ) ; } } </s>

Implement TARGET_D_CPU_VERSIONS for PowerPC targets .


<s> unsigned getElementSize ( ) const { assert ( Predicated ) ; return ElementSize ; } </s>

Return the size of an element read or written by Inst .


<s>
const
RegisterBank
&
X86RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
if
(
X86
::
GR8RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR16RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR32RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR64RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
GPRRegBankID
)
;
llvm_unreachable
(
"Unsupported register kind yet."
)
;
}
</s>


<s> LLT AArch64TargetLowering :: getOptimalMemOpLLT ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return LLT :: vector ( 2 , 64 ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return LLT :: scalar ( 128 ) ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return LLT :: scalar ( 64 ) ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return LLT :: scalar ( 32 ) ; return LLT ( ) ; } </s>


<s> static Mnode * add_minipool_forward_ref ( Mfix * fix ) { Mnode * max_mp = NULL ; HOST_WIDE_INT max_address = fix -> address + fix -> forwards ; Mnode * mp ; if ( minipool_vector_head && fix -> address >= minipool_vector_head -> max_address - fix -> fix_size ) return NULL ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { if ( GET_CODE ( fix -> value ) == GET_CODE ( mp -> value ) && fix -> mode == mp -> mode && ( GET_CODE ( fix -> value ) != CODE_LABEL || ( CODE_LABEL_NUMBER ( fix -> value ) == CODE_LABEL_NUMBER ( mp -> value ) ) ) && rtx_equal_p ( fix -> value , mp -> value ) ) { mp -> refcount ++ ; return move_minipool_fix_forward_ref ( mp , max_mp , max_address ) ; } if ( max_mp == NULL && mp -> max_address > max_address ) max_mp = mp ; if ( ARM_DOUBLEWORD_ALIGN && max_mp == NULL && fix -> fix_size == 8 && mp -> fix_size != 8 ) { max_mp = mp ; max_address = mp -> max_address ; } } mp = xmalloc ( sizeof ( * mp ) ) ; mp -> fix_size = fix -> fix_size ; mp -> mode = fix -> mode ; mp -> value = fix -> value ; mp -> refcount = 1 ; mp -> min_address = - 65536 ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_label_rtx ( ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp = mp ; while ( mp -> prev != NULL && mp -> prev -> max_address > mp -> max_address - mp -> prev -> fix_size ) { mp -> prev -> max_address = mp -> max_address - mp -> prev -> fix_size ; mp = mp -> prev ; } return max_mp ; } </s>

Add a constant to the minipool for a forward reference . Returns the node added or NULL if the constant will not fit in this pool .


<s> static recps_type get_recps_type ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return ( gen_aarch64_frecpssf ) ; case E_V2SFmode : return ( gen_aarch64_frecpsv2sf ) ; case E_V4SFmode : return ( gen_aarch64_frecpsv4sf ) ; case E_DFmode : return ( gen_aarch64_frecpsdf ) ; case E_V2DFmode : return ( gen_aarch64_frecpsv2df ) ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal series step insn depending on machine mode .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
PrintOperand
(
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
case
'V'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
PrintPCRelImm
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


<s> static bool find_alignment_op ( rtx_insn * insn , rtx base_reg , vec < rtx_insn * > * and_insns , vec < rtx > * and_ops ) { df_ref base_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; rtx and_operation = 0 ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link ) return false ; while ( base_def_link ) { if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) return false ; rtx_insn * and_insn = DF_REF_INSN ( base_def_link -> ref ) ; and_operation = alignment_mask ( and_insn ) ; if ( ! and_operation ) return false ; and_insns -> safe_push ( and_insn ) ; and_ops -> safe_push ( and_operation ) ; base_def_link = base_def_link -> next ; } } return and_operation ; } </s>

Given INSN that 's a load or store based at BASE_REG , check if all of its feeding computations align its address on a 16-byte boundary . If so , return true and add all definition insns into AND_INSNS and their corresponding fully-expanded rtxes for the masking operations into AND_OPS .


<s> void init ( Module & M ) { InsertedThunks = false ; getDerived ( ) . doInitialization ( M ) ; } </s>

Initialize the machine model for instruction scheduling .


<s> uint64_t ARMPLT :: emit ( MemoryRegion & pRegion ) { uint64_t result = 0x0 ; iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < ARMPLT0 > ( ( * it ) ) . getValue ( ) , ARMPLT0 :: EntrySize ) ; result += ARMPLT0 :: EntrySize ; ++ it ; ARMPLT1 * plt1 = 0 ; ARMPLT :: iterator ie = end ( ) ; while ( it != ie ) { plt1 = & ( llvm :: cast < ARMPLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , ARMPLT1 :: EntrySize ) ; result += ARMPLT1 :: EntrySize ; ++ it ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .

ARM ARM 0x0 ARM ARM ARM ARM 0 ARM ARM ARM ARM


<s> static enum rtx_code ix86_prepare_fp_compare_args ( enum rtx_code code , rtx * pop0 , rtx * pop1 ) { enum machine_mode fpcmp_mode = ix86_fp_compare_mode ( code ) ; rtx op0 = * pop0 , op1 = * pop1 ; enum machine_mode op_mode = GET_MODE ( op0 ) ; int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( op_mode ) ; if ( ! is_sse && ( fpcmp_mode == CCFPUmode || ( op_mode == XFmode && ! ( standard_80387_constant_p ( op0 ) == 1 || standard_80387_constant_p ( op1 ) == 1 ) && GET_CODE ( op1 ) != FLOAT ) || ix86_use_fcomi_compare ( code ) ) ) { op0 = force_reg ( op_mode , op0 ) ; op1 = force_reg ( op_mode , op1 ) ; } else { if ( standard_80387_constant_p ( op0 ) == 0 || ( GET_CODE ( op0 ) == MEM && ! ( standard_80387_constant_p ( op1 ) == 0 || GET_CODE ( op1 ) == MEM ) ) ) { rtx tmp ; tmp = op0 , op0 = op1 , op1 = tmp ; code = swap_condition ( code ) ; } if ( GET_CODE ( op0 ) != REG ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == 0 ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == 1 ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( GET_CODE ( op1 ) == REG || ! no_new_pseudos ) ) { rtx tmp ; tmp = op0 , op0 = op1 , op1 = tmp ; code = swap_condition ( code ) ; if ( GET_CODE ( op0 ) != REG ) op0 = force_reg ( op_mode , op0 ) ; } * pop0 = op0 ; * pop1 = op1 ; return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to a fp comparison . The operands are updated in place ; the new comparsion code is returned .


<s> static int ia64_hpux_reloc_rw_mask ( void ) { return 3 ; } </s>

For HPUX , it is illegal to have relocations in shared segments .


<s> rtx function_expander :: get_nonoverlapping_reg_target ( ) { if ( possible_target && overlaps_input_p ( possible_target ) ) possible_target = NULL_RTX ; return get_reg_target ( ) ; } </s>

As for get_reg_target , but make sure that the returned REG does not overlap any inputs .


<s> const OR1KRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; if ( STI . hasV4TOps ( ) && ! STI . hasV5TOps ( ) ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool ARMAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return reasonForFixupRelaxation ( Fixup , Value ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> Value * AArch64TargetLowering :: getIRStackGuard ( IRBuilderBase & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , 0x28 ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - 0x10 ) ; return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s>
SDValue
TOYTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
MF
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_TOY
)
;
SDValue
Flag
;
if
(
MF
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
MF
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
TOYISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getRegister
(
TOY
::
LR
,
MVT
::
i32
)
,
Flag
)
;
return
DAG
.
getNode
(
TOYISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getRegister
(
TOY
::
LR
,
MVT
::
i32
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ"


<s> unsigned SparcInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: STri || MI -> getOpcode ( ) == SP :: STXri || MI -> getOpcode ( ) == SP :: STFri || MI -> getOpcode ( ) == SP :: STDFri || MI -> getOpcode ( ) == SP :: STQFri ) { if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
bool
ARMTargetLowering
::
canCombineStoreAndExtract
(
Type
*
VectorTy
,
Value
*
Idx
,
unsigned
&
Cost
)
const
{
if
(
!
Subtarget
->
hasNEON
(
)
)
return
false
;
if
(
VectorTy
->
isFPOrFPVectorTy
(
)
)
return
false
;
if
(
!
isa
<
ConstantInt
>
(
Idx
)
)
return
false
;
assert
(
VectorTy
->
isVectorTy
(
)
&&
"VectorTy is not a vector type"
)
;
unsigned
BitWidth
=
cast
<
VectorType
>
(
VectorTy
)
->
getBitWidth
(
)
;
if
(
BitWidth
==
64
||
BitWidth
==
128
)
{
Cost
=
0
;
return
true
;
}
return
false
;
}
</s>

Return true if the target can combine store ( extractelement VectorTy , Idx ) .


<s> int arm_early_store_addr_dep ( rtx producer , rtx consumer ) { return ! arm_no_early_store_addr_dep ( producer , consumer ) ; } </s>

Return nonzero if the CONSUMER instruction ( a store ) does need PRODUCER 's value to calculate the address .


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( ) const { if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; else return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

PowerPC PPC PPC PPC::G8RCRegClass PPC::GPRCRegClass


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .