<s> void mt_expand_prologue ( void ) { rtx size_rtx , insn ; unsigned int frame_size ; if ( mt_interrupt_function_p ( current_function_decl ) ) { interrupt_handler = 1 ; if ( cfun -> machine ) cfun -> machine -> interrupt_handler = 1 ; } mt_compute_frame_size ( get_frame_size ( ) ) ; if ( TARGET_DEBUG_STACK ) mt_debug_stack ( & current_frame_info ) ; frame_size = current_frame_info . total_size ; if ( CONST_OK_FOR_LETTER_P ( frame_size , 'O' ) ) size_rtx = GEN_INT ( frame_size ) ; else { gcc_assert ( ! interrupt_handler ) ; size_rtx = gen_rtx_REG ( SImode , GPR_R9 ) ; insn = emit_move_insn ( size_rtx , GEN_INT ( frame_size & 0xffff0000 ) ) ; insn = emit_insn ( gen_iorsi3 ( size_rtx , size_rtx , GEN_INT ( frame_size & 0x0000ffff ) ) ) ; } if ( frame_size ) { insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , size_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( frame_size ) ) ) , REG_NOTES ( insn ) ) ; } if ( current_frame_info . reg_size != 0 && ! CONST_OK_FOR_LETTER_P ( frame_size , 'O' ) ) emit_insn ( gen_addsi3 ( size_rtx , size_rtx , stack_pointer_rtx ) ) ; mt_emit_save_fp ( FROM_PROCESSOR_TO_MEM , current_frame_info ) ; if ( frame_pointer_needed ) { insn = emit_move_insn ( frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } mt_emit_save_regs ( FROM_PROCESSOR_TO_MEM , current_frame_info ) ; if ( profile_flag ) emit_insn ( gen_blockage ( ) ) ; } </s>


<s> TargetLowering :: ConstraintWeight OR1KTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool X86InstrInfo :: hasStoreToStackSlot ( const MachineInstr * MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { for ( MachineInstr :: mmo_iterator o = MI -> memoperands_begin ( ) , oe = MI -> memoperands_end ( ) ; o != oe ; ++ o ) { if ( ( * o ) -> isStore ( ) && ( * o ) -> getValue ( ) ) if ( const FixedStackPseudoSourceValue * Value = dyn_cast < const FixedStackPseudoSourceValue > ( ( * o ) -> getValue ( ) ) ) { FrameIndex = Value -> getFrameIndex ( ) ; MMO = * o ; return true ; } } return false ; } </s>

If the specified machine instruction has a store to a stack slot , return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference .


<s> static void free_bundle_state ( struct bundle_state * state ) { state -> next = free_bundle_state_chain ; free_bundle_state_chain = state ; } </s>

The following function frees given bundle state .


<s> unsigned getNumFixupKinds ( ) const { return ARM :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static unsigned int mips_get_compress_off_flags ( tree attributes ) { unsigned int flags = 0 ; if ( lookup_attribute ( "nocompression" , attributes ) != NULL ) flags |= MASK_MIPS16 | MASK_MICROMIPS ; if ( lookup_attribute ( "nomips16" , attributes ) != NULL ) flags |= MASK_MIPS16 ; if ( lookup_attribute ( "nomicromips" , attributes ) != NULL ) flags |= MASK_MICROMIPS ; return flags ; } </s>

Return the set of compression modes that are explicitly forbidden by the attributes in ATTRIBUTES .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { MCFixupKind Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return ; Value = adjustFixupValue ( Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
char
*
output_cbranch
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
rtx
cc_reg
=
XEXP
(
op
,
0
)
;
machine_mode
mode
=
GET_MODE
(
cc_reg
)
;
int
cc_regno
=
REGNO
(
cc_reg
)
CR0_REGNO
;
int
need_longbranch
=
label
!=
&&
get_attr_length
(
insn
)
==
8
;
int
really_reversed
=
reversed
^
need_longbranch
;
char
*
s
=
string
;
const
char
*
ccode
;
const
char
*
pred
;
rtx
note
;
validate_condition_mode
(
code
,
mode
)
;
if
(
really_reversed
)
{
if
(
mode
==
CCFPmode
)
code
=
reverse_condition_maybe_unordered
(
code
)
;
else
code
=
reverse_condition
(
code
)
;
}
switch
(
code
)
{
case
NE
:
case
LTGT
:
ccode
=
"ne"
;
break
;
case
EQ
:
case
UNEQ
:
ccode
=
"eq"
;
break
;
case
GE
:
case
GEU
:
ccode
=
"ge"
;
break
;
case
GT
:
case
GTU
:
case
UNGT
:
ccode
=
"gt"
;
break
;
case
LE
:
case
LEU
:
ccode
=
"le"
;
break
;
case
LT
:
case
LTU
:
case
UNLT
:
ccode
=
"lt"
;
break
;
case
UNORDERED
:
ccode
=
"un"
;
break
;
case
ORDERED
:
ccode
=
"nu"
;
break
;
case
UNGE
:
ccode
=
"nl"
;
break
;
case
UNLE
:
ccode
=
"ng"
;
break
;
default
:
gcc_unreachable
(
)
;
}
pred
=
""
;
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
;
if
(
note
!=
NULL_RTX
)
{
int
prob
=
profile_probability
::
from_reg_br_prob_note
(
XINT
(
note
,
0
)
)
.
to_reg_br_prob_base
(
)
REG_BR_PROB_BASE
/
2
;
if
(
rs6000_always_hint
||
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
100
*
48
&&
(
profile_status_for_fn
(
cfun
)
!=
PROFILE_GUESSED
)
&&
br_prob_note_reliable_p
(
note
)
)
)
{
if
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
20
&&
(
(
prob
>
0
)
^
need_longbranch
)
)
pred
=
"+"
;
else
pred
=
"-"
;
}
}
if
(
label
==
)
s
+=
sprintf
(
s
,
"b%slr%s "
,
ccode
,
pred
)
;
else
s
+=
sprintf
(
s
,
"b%s%s "
,
ccode
,
pred
)
;
if
(
reg_names
[
cc_regno
+
CR0_REGNO
]
[
0
]
==
'%'
)
*
s
++
=
'%'
;
s
+=
sprintf
(
s
,
"%s"
,
reg_names
[
cc_regno
+
CR0_REGNO
]
)
;
if
(
label
!=
)
{
if
(
need_longbranch
)
s
+=
sprintf
(
s
,
",$+8\n\tb %s"
,
label
)
;
else
s
+=
sprintf
(
s
,
",%s"
,
label
)
;
}
return
string
;
}
</s>

Output a conditional branch to LABEL . CODE is the comparison code . CC_MODE is the mode of the CC register . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the instruction .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createX86MachObjectWriter ( OS , true , MachO :: CPU_TYPE_X86_64 , MachO :: CPU_SUBTYPE_X86_64_ALL ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static int function_arg_advance_32 ( CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type , HOST_WIDE_INT bytes , HOST_WIDE_INT words ) { int res = 0 ; switch ( mode ) { default : break ; case BLKmode : if ( bytes < 0 ) break ; case DImode : case SImode : case HImode : case QImode : cum -> words += words ; cum -> nregs -= words ; cum -> regno += words ; if ( cum -> nregs >= 0 ) res = words ; if ( cum -> nregs <= 0 ) { cum -> nregs = 0 ; cum -> regno = 0 ; } break ; case OImode : gcc_unreachable ( ) ; case DFmode : if ( cum -> float_in_sse < 2 ) break ; case SFmode : if ( cum -> float_in_sse < 1 ) break ; case V8SFmode : case V8SImode : case V64QImode : case V32HImode : case V16SImode : case V8DImode : case V16SFmode : case V8DFmode : case V32QImode : case V16HImode : case V4DFmode : case V4DImode : case TImode : case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V4SFmode : case V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { cum -> sse_words += words ; cum -> sse_nregs -= 1 ; cum -> sse_regno += 1 ; if ( cum -> sse_nregs <= 0 ) { cum -> sse_nregs = 0 ; cum -> sse_regno = 0 ; } } break ; case V8QImode : case V4HImode : case V2SImode : case V2SFmode : case V1TImode : case V1DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { cum -> mmx_words += words ; cum -> mmx_nregs -= 1 ; cum -> mmx_regno += 1 ; if ( cum -> mmx_nregs <= 0 ) { cum -> mmx_nregs = 0 ; cum -> mmx_regno = 0 ; } } break ; } return res ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . ) Return a number of integer regsiters advanced over .


<s> uint64_t VEMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , ( MCFixupKind ) VE :: fixup_ve_pc_lo32 ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s>
void
LanaiInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
Position
,
const
DebugLoc
&
DL
,
unsigned
DestinationRegister
,
unsigned
SourceRegister
,
bool
KillSource
)
const
{
if
(
!
Lanai
::
GPRRegClass
.
contains
(
DestinationRegister
,
SourceRegister
)
)
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
Position
,
DL
,
get
(
Lanai
::
OR_I_LO
)
,
DestinationRegister
)
.
addReg
(
SourceRegister
,
getKillRegState
(
KillSource
)
)
.
addImm
(
0
)
;
}
</s>

Lanai
Lanai
Lanai::GPRRegClass
"Impossible reg-to-reg copy"
Lanai::OR_I_LO
0


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> static bool sparc_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_WIDE_INT : case CONST_DOUBLE : case CONST_VECTOR : return false ; case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return sparc_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) || sparc_cannot_force_const_mem ( mode , XEXP ( x , 1 ) ) ; case UNSPEC : return true ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) , usingPBQP ( false ) { initAsmInfo ( ) ; if ( EnablePBQP && Subtarget . isCortexA57 ( ) && OL != CodeGenOpt :: None ) { usingPBQP = true ; RegisterRegAlloc :: setDefault ( createDefaultPBQPRegisterAllocator ) ; } } </s>


<s> static int sh_pr_n_sets ( void ) { return DF_REG_DEF_COUNT ( TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ; } </s>

For use by ALLOCATE_INITIAL_VALUE . Note that sh.md contains some 'special function ' patterns ( type sfunc ) that clobber pr , but that do not look like function calls to leaf_function_p . Hence we must do this extra check .


<s> void MipsAsmPrinter :: emitEndOfAsmFile ( Module & M ) { for ( std :: map < const char * , const Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = StubsNeeded . begin ( ) ; it != StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; EmitFPCallStub ( Symbol , Signature ) ; } OutStreamer -> SwitchSection ( OutContext . getObjectFileInfo ( ) -> getTextSection ( ) ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> void DLXPassConfig :: addPreEmitPass ( ) { addPass ( createDLXDelaySlotFillerPass ( getDLXTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx ix86_expand_sse_compare ( const struct builtin_description * d , tree arglist , rtx target ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; rtx op2 ; enum machine_mode tmode = insn_data [ d -> icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum machine_mode mode1 = insn_data [ d -> icode ] . operand [ 2 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) { rtx tmp = gen_reg_rtx ( mode1 ) ; emit_move_insn ( tmp , op1 ) ; op1 = op0 ; op0 = tmp ; } if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ d -> icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ d -> icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! ( * insn_data [ d -> icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of comparison insns .


<s> void PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> unsigned getNumFixupKinds ( ) const override { return UPT :: NumTargetFixupKinds ; } </s>


<s> bool MipsTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; if ( Imm . isNegZero ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool rs6000_split_128bit_ok_p ( rtx operands [ ] ) { if ( ! reload_completed ) return false ; if ( ! gpr_or_gpr_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; if ( quad_load_store_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; return true ; } </s>

Return true if a 128-bit move needs to be split .


<s> static rtx gen_compare_reg_1 ( enum rtx_code code , rtx x , rtx y ) { machine_mode mode ; rtx cc_reg ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_CC ) return x ; mode = SELECT_CC_MODE ( code , x , y ) ; if ( TARGET_V9 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { int reg ; static int next_fcc_reg = 0 ; static rtx prev_args [ 4 ] [ 2 ] ; for ( reg = 0 ; reg < 4 ; reg ++ ) if ( prev_args [ reg ] [ 0 ] == x && prev_args [ reg ] [ 1 ] == y ) break ; if ( reg == 4 ) { reg = next_fcc_reg ; prev_args [ reg ] [ 0 ] = x ; prev_args [ reg ] [ 1 ] = y ; next_fcc_reg = ( next_fcc_reg + 1 ) & 3 ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ; } cc_reg = gen_reg_rtx ( mode ) ; else if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) cc_reg = gen_rtx_REG ( mode , SPARC_FCC_REG ) ; else cc_reg = gen_rtx_REG ( mode , SPARC_ICC_REG ) ; emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg ; } </s>

Emit the compare insn and return the CC reg for a CODE comparison with operands X and Y .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void register_svprfop ( ) { auto_vec < string_int_pair , 16 > values ; values . quick_push ( string_int_pair ( "SV_" # UPPER , VALUE ) ) ; AARCH64_FOR_SVPRFOP ( PUSH ) acle_svprfop = lang_hooks . types . simulate_enum_decl ( input_location , "svprfop" , values ) ; } </s>


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( Subtarget . hasVSX ( ) ) { if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static char nds32_byte_to_size ( int byte ) { switch ( byte ) { case 4 : return 'w' ; case 2 : return 'h' ; case 1 : return 'b' ; default : gcc_unreachable ( ) ; } } </s>

A helper function to return character based on byte size .


<s> static struct machine_function * mmix_init_machine_status ( void ) { return ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ; } </s>


<s> SDValue ARM64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case ARM64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void UPTInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( UPT :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , Align Alignment ) { if ( ! supportsGather ( ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == 1 ) return false ; if ( ST -> hasAVX512 ( ) && ( NumElts == 2 || ( NumElts == 4 && ! ST -> hasVLX ( ) ) ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> unsigned PPCFastISel :: fastEmit_i ( MVT Ty , MVT VT , unsigned Opc , uint64_t Imm ) { if ( Opc != ISD :: Constant ) return 0 ; if ( VT == MVT :: i1 && Subtarget -> useCRBits ( ) ) { unsigned ImmReg = createResultReg ( & PPC :: CRBITRCRegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == 0 ? PPC :: CRUNSET : PPC :: CRSET ) , ImmReg ) ; return ImmReg ; } if ( VT != MVT :: i64 && VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 && VT != MVT :: i1 ) return 0 ; const TargetRegisterClass * RC = ( ( VT == MVT :: i64 ) ? & PPC :: G8RCRegClass : & PPC :: GPRCRegClass ) ; if ( VT == MVT :: i64 ) return PPCMaterialize64BitInt ( Imm , RC ) ; else return PPCMaterialize32BitInt ( Imm , RC ) ; } </s>

This method is called by target-independent code to request that an instruction with the given type , opcode , and immediate operand be emitted .


<s> char * aarch64_output_sve_cnt_immediate ( const char * prefix , const char * operands , rtx x ) { poly_int64 value = rtx_to_poly_int64 ( x ) ; gcc_assert ( aarch64_sve_cnt_immediate_p ( value ) ) ; return aarch64_output_sve_cnt_immediate ( prefix , operands , value . coeffs [ 1 ] , 0 ) ; } </s>

Return the asm string for an instruction with a CNT-like vector size operand ( a vector pattern followed by a multiplier in the range [ 1 , 16 ] ) . PREFIX is the mnemonic without the size suffix and OPERANDS is the first part of the operands template ( the part that comes before the vector size itself ) . X is the value of the vector size operand , as a polynomial integer rtx .


<s> unsigned AArch64TargetLowering :: getVaListSizeInBits ( const DataLayout & DL , unsigned AS ) const { if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetWindows ( ) ) return getPointerTy ( DL , AS ) . getSizeInBits ( ) ; return 3 * getPointerTy ( DL , AS ) . getSizeInBits ( ) + 2 * 32 ; } </s>

Returns the size of the platform 's va_list object .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
if
(
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_64_SwiftError_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> bool ix86_avoid_lea_for_addr ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 , regno2 ; int split_cost ; struct ix86_address parts ; int ok ; if ( REG_P ( operands [ 1 ] ) || ( SImode_address_operand ( operands [ 1 ] , VOIDmode ) && REG_P ( XEXP ( operands [ 1 ] , 0 ) ) ) ) return false ; ok = ix86_decompose_address ( operands [ 1 ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > 1 ) < 2 ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ; if ( ! TARGET_CPU_P ( BONNELL ) && parts . scale == 1 && ( ! parts . disp || parts . disp == const0_rtx ) && ( regno0 == regno1 || regno0 == regno2 ) ) return true ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; split_cost = 0 ; if ( parts . base || parts . index ) { if ( regno1 != regno0 && regno2 != regno0 ) split_cost += 1 ; if ( parts . base && parts . index ) split_cost += 1 ; if ( parts . scale > 1 ) { if ( regno0 != regno1 ) split_cost += 1 ; else if ( regno2 == regno0 ) split_cost += 4 ; else split_cost += parts . scale ; } if ( parts . disp && parts . disp != const0_rtx ) split_cost += 1 ; split_cost -= 1 ; } return ! ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , split_cost , parts . scale > 1 ) ; } </s>

Return true if we need to split lea into a sequence of instructions to avoid AGU stalls during peephole2 .


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM_BR ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static void mips_expand_vi_constant ( machine_mode vmode , unsigned nelt , rtx target , rtx vals ) { rtvec vec = shallow_copy_rtvec ( XVEC ( vals , 0 ) ) ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) { rtx elem = RTVEC_ELT ( vec , i ) ; if ( ! mips_constant_elt_p ( elem ) ) RTVEC_ELT ( vec , i ) = CONST0_RTX ( GET_MODE ( elem ) ) ; } emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , vec ) ) ; } </s>

A subroutine of mips_expand_vec_init , replacing all of the non-constant elements of VALS with zeros , copy the constant vector to TARGET .


<s> void MipsRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjustMipsStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> hasCalls ( ) ) return ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOREORDER ) ) ; if ( isPIC && Subtarget . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPLOAD ) ) . addReg ( getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOMACRO ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( - StackSize ) ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: FP ) . addReg ( Mips :: SP ) . addReg ( Mips :: ZERO ) ; } if ( MipsFI -> needGPSaveRestore ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPRESTORE ) ) . addImm ( MipsFI -> getGPStackOffset ( ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips Mips Mips 0 Mips Mips Mips::NOREORDER Mips::CPLOAD Mips::NOMACRO Mips::ADDiu Mips::SP Mips::SP Mips::SW Mips::RA Mips::SP Mips::SW Mips::FP Mips::SP Mips::ADDu Mips::FP Mips::SP Mips::ZERO Mips Mips::CPRESTORE Mips


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetHazardRecognizer
(
const
TargetMachine
*
TM
,
const
ScheduleDAG
*
DAG
)
const
{
const
TargetInstrInfo
*
TII
=
TM
->
getInstrInfo
(
)
;
(
void
)
TII
;
assert
(
TII
&&
"No InstrInfo?"
)
;
unsigned
Directive
=
TM
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
==
PPC
::
DIR_440
)
{
const
InstrItineraryData
*
II
=
TM
->
getInstrItineraryData
(
)
;
return
new
PPCHazardRecognizer440
(
II
,
DAG
)
;
}
else
{
return
new
ScheduleHazardRecognizer
(
)
;
}
}
</s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .

PowerPC
PPC
"No InstrInfo?"
PPC
PPC::DIR_440
PPC


<s> StackOffset SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } else { FrameReg = SP :: O6 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


<s> bool isVirtualSection ( const MCSection & Section ) const { const MCSectionMachO & SMO = static_cast < const MCSectionMachO & > ( Section ) ; return ( SMO . getType ( ) == MCSectionMachO :: S_ZEROFILL || SMO . getType ( ) == MCSectionMachO :: S_GB_ZEROFILL || SMO . getType ( ) == MCSectionMachO :: S_THREAD_LOCAL_ZEROFILL ) ; } </s>

Check whether this section is `` virtual '' , that is has no actual object file contents .


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; if ( const auto * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; if ( const auto * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; if ( isa < UndefValue > ( C ) ) { unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : break ; case MVT :: f32 : if ( ! X86ScalarSSEf32 ) Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( ! X86ScalarSSEf64 ) Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : Opc = X86 :: LD_Fp080 ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { const X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CSSize = X86FI -> getCalleeSavedFrameSize ( ) ; const auto & WinEHXMMSlotInfo = X86FI -> getWinEHXMMSlotInfo ( ) ; unsigned XMMSize = WinEHXMMSlotInfo . size ( ) * TRI -> getSpillSize ( X86 :: VR128RegClass ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlign ( ) ) ; return FrameSizeMinusRBP + XMMSize - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> static bool loongarch_scalar_mode_supported_p ( scalar_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= 2 * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode ) ; } </s>


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { if ( ST -> getMcpu ( ) == PPC :: MCPU_A2 ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , SE , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static void pa_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx end_addr = gen_reg_rtx ( Pmode ) ; rtx line_length = gen_reg_rtx ( Pmode ) ; rtx r_tramp , tmp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; r_tramp = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; if ( ! TARGET_64BIT ) { tmp = adjust_address ( m_tramp , Pmode , 36 ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , 40 ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , 44 ) ; emit_move_insn ( tmp , r_tramp ) ; tmp = adjust_address ( m_tramp , Pmode , 48 ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , 19 ) ) ; emit_insn ( gen_andsi3 ( start_addr , r_tramp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , TRAMPOLINE_CODE_SIZE - 1 ) ) ; emit_insn ( gen_andsi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushsi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushsi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } else { tmp = adjust_address ( m_tramp , Pmode , 56 ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , 64 ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , 16 ) ; emit_move_insn ( tmp , force_reg ( Pmode , plus_constant ( Pmode , r_tramp , 32 ) ) ) ; tmp = adjust_address ( m_tramp , Pmode , 24 ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , 27 ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , 32 ) ) ; emit_insn ( gen_anddi3 ( start_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , tmp , TRAMPOLINE_CODE_SIZE - 1 ) ) ; emit_insn ( gen_anddi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushdi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushdi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . Move the function address to the trampoline template at offset 36 . Move the static chain value to trampoline template at offset 40 . Move the trampoline address to trampoline template at offset 44 . Move r19 to trampoline template at offset 48 . The latter two words create a plabel for the indirect call to the trampoline . A similar sequence is used for the 64-bit port but the plabel is at the beginning of the trampoline . Finally , the cache entries for the trampoline code are flushed . This is necessary to ensure that the trampoline instruction sequence is written to memory prior to any attempts at prefetching the code sequence .


<s> static bool mips_cannot_force_const_mem ( machine_mode mode , rtx x ) { enum mips_symbol_type type ; rtx base , offset ; if ( GET_CODE ( x ) == HIGH ) return true ; if ( CONST_INT_P ( x ) && mips_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( mips_symbolic_constant_p ( base , SYMBOL_CONTEXT_LEA , & type ) ) { if ( mips_use_pcrel_pool_p [ ( int ) type ] ) return false ; if ( SMALL_INT ( offset ) && mips_symbol_insns ( type , MAX_MACHINE_MODE ) > 0 ) return true ; if ( TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p ( type ) ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>

Return true if X can not be forced into a constant pool .


<s> void ARMInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case ARM :: MOVi2pieces : { RI . emitLoadConstPool ( MBB , I , dl , DestReg , SubIdx , Orig -> getOperand ( 1 ) . getImm ( ) , ( ARMCC :: CondCodes ) Orig -> getOperand ( 2 ) . getImm ( ) , Orig -> getOperand ( 3 ) . getReg ( ) ) ; MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; return ; } } return ARMBaseInstrInfo :: reMaterialize ( MBB , I , DestReg , SubIdx , Orig , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
IsAndroid
(
false
)
,
RM
(
_RM
)
,
TargetTriple
(
TT
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> static unsigned int constant_pool_broadcast ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) replace_constant_pool_with_broadcast ( insn ) ; } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>

For const vector having one duplicated value , there 's no need to put whole vector in the constant pool when target supports embedded broadcast .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? d -> nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = i * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool aarch64_return_address_signing_enabled ( void ) { gcc_assert ( cfun -> machine -> frame . laid_out ) ; if ( crtl -> calls_eh_return ) return false ; return ( aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL || ( aarch64_ra_sign_scope == AARCH64_FUNCTION_NON_LEAF && known_ge ( cfun -> machine -> frame . reg_offset [ LR_REGNUM ] , 0 ) ) ) ; } </s>

Return TRUE if return address signing should be enabled for the current function , otherwise return FALSE .


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallPtrSet < Constant * , 8 > AlreadyChecked ; for ( Instruction & I : inst_range ( & F ) ) { for ( Value * Op : I . operand_values ( ) ) { Constant * Cst = dyn_cast < Constant > ( Op ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } return LocalChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static tree fully_fold_convert ( tree type , tree expr ) { tree result = fold_convert ( type , expr ) ; bool maybe_const = true ; if ( ! c_dialect_cxx ( ) ) result = c_fully_fold ( result , false , & maybe_const ) ; return result ; } </s>

In addition to calling fold_convert for EXPR of type TYPE , also call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be hiding there ( PR47197 ) .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case 128 : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case 256 : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void ARMELFStreamer :: finishImpl ( ) { MCTargetStreamer & TS = * getTargetStreamer ( ) ; ARMTargetStreamer & ATS = static_cast < ARMTargetStreamer & > ( TS ) ; ATS . finishAttributeSection ( ) ; MCELFStreamer :: finishImpl ( ) ; } </s>


<s> static unsigned int get_csky_live_regs ( int * count ) { int reg ; unsigned int live_regs_mask = 0 ; * count = 0 ; for ( reg = 0 ; reg < CSKY_NGPR_REGS ; reg ++ ) { bool save = false ; if ( CSKY_TARGET_ARCH ( CK801 ) && reg > 8 && reg < 13 ) continue ; if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) ) && reg > 15 ) break ; if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) save = true ; else if ( frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM ) save = true ; else if ( crtl -> calls_eh_return && reg == HARD_FRAME_POINTER_REGNUM ) save = true ; else if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) && reg == CSKY_LR_REGNUM && ( ! crtl -> is_leaf || csky_far_jump_used_p ( ) ) ) save = true ; else if ( crtl -> calls_eh_return && reg >= CSKY_FIRST_EH_RETDATA_REGNUM && reg <= CSKY_LAST_EH_RETDATA_REGNUM ) save = true ; if ( reg == CSKY_STACKADJUST_REGNUM && cfun -> machine -> reg_offset > CSKY_MAX_SP_ADJUST * 2 ) save = true ; if ( save ) { ( * count ) ++ ; live_regs_mask |= ( 1 << reg ) ; } } return live_regs_mask ; } </s>

Return the mask of registers used by the current function . Set COUNT to the number of registers used .


<s>
SDValue
LEGTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

LEG
LEG
"Unimplemented operand"
ISD::GlobalAddress


<s> bool F2003fInstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool MMIXPassConfig :: addInstSelector ( ) { addPass ( createMMIXISelDag ( getMMIXTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"unknown value %qs for 'tune' target %s"

Handle the argument STR to the tune= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> static unsigned long arm_compute_save_reg0_reg12_mask ( void ) { unsigned long func_type = arm_current_func_type ( ) ; unsigned long save_reg_mask = 0 ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = 7 ; else max_reg = 12 ; for ( reg = 0 ; reg <= max_reg ; reg ++ ) if ( df_regs_ever_live_p ( reg ) || ( ! crtl -> is_leaf && call_used_regs [ reg ] ) ) save_reg_mask |= ( 1 << reg ) ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } else if ( IS_VOLATILE ( func_type ) ) { if ( frame_pointer_needed ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( ARM_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( THUMB_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= 1 << THUMB_HARD_FRAME_POINTER_REGNUM ; } else { for ( reg = 0 ; reg <= 11 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; if ( frame_pointer_needed ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && ( df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) || crtl -> uses_pic_offset_table ) ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( IS_STACKALIGN ( func_type ) ) save_reg_mask |= 1 ; } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; i ++ ) { reg = EH_RETURN_DATA_REGNO ( i ) ; if ( reg == INVALID_REGNUM ) break ; save_reg_mask |= 1 << reg ; } } return save_reg_mask ; } </s>

Compute the register save mask for registers 0 through 12 inclusive . This code is used by arm_compute_save_reg_mask .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : case vector_gather_load : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return 5 ; else if ( INTEGRAL_TYPE_P ( elem_type ) ) { if ( TARGET_P9_VECTOR ) return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 2 ; else return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 5 ; } else return 2 ; default : gcc_unreachable ( ) ; } } </s>


<s> void X86InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == X86 :: ENDBR64 || Opcode == X86 :: ENDBR32 || Opcode == X86 :: PLDTILECFGV ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> rtx nds32_expand_load_multiple ( int base_regno , int count , rtx base_addr , rtx basemem ) { int par_index ; int offset ; rtx result ; rtx new_addr , mem , reg ; result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; for ( par_index = 0 ; par_index < count ; par_index ++ ) { offset = par_index * 4 ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , 0 , par_index ) = gen_rtx_SET ( reg , mem ) ; } return result ; } </s>

Functions to expand load_multiple and store_multiple . They are auxiliary extern functions to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT VT ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void rs6000_expand_vector_extract ( rtx target , rtx vec , int elt ) { machine_mode mode = GET_MODE ( vec ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx mem ; if ( VECTOR_MEM_VSX_P ( mode ) ) { switch ( mode ) { default : break ; case V1TImode : gcc_assert ( elt == 0 && inner_mode == TImode ) ; emit_move_insn ( target , gen_lowpart ( TImode , vec ) ) ; break ; case V2DFmode : emit_insn ( gen_vsx_extract_v2df ( target , vec , GEN_INT ( elt ) ) ) ; return ; case V2DImode : emit_insn ( gen_vsx_extract_v2di ( target , vec , GEN_INT ( elt ) ) ) ; return ; case V4SFmode : emit_insn ( gen_vsx_extract_v4sf ( target , vec , GEN_INT ( elt ) ) ) ; return ; } } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , vec ) ; mem = adjust_address_nv ( mem , inner_mode , elt * GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , 0 ) ) ; } </s>

Extract field ELT from VEC into TARGET .


<s> bool SystemZLongBranch :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; MF = & F ; uint64_t Size = initMBBInfo ( ) ; if ( Size <= MaxForwardRange || ! mustRelaxABranch ( ) ) return false ; setWorstCaseAddresses ( ) ; relaxBranches ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static rtx mips16_local_alias ( rtx func ) { if ( mips16_local_aliases == NULL ) mips16_local_aliases = hash_map < nofree_string_hash , rtx > :: create_ggc ( 37 ) ; bool existed ; const char * func_name = XSTR ( func , 0 ) ; rtx * slot = & mips16_local_aliases -> get_or_insert ( func_name , & existed ) ; gcc_assert ( slot != NULL ) ; if ( ! existed ) { rtx local ; func_name = targetm . strip_name_encoding ( XSTR ( func , 0 ) ) ; const char * local_name = ACONCAT ( ( "__fn_local_" , func_name , NULL ) ) ; local = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( local_name ) ) ; SYMBOL_REF_FLAGS ( local ) = SYMBOL_REF_FLAGS ( func ) | SYMBOL_FLAG_LOCAL ; * slot = local ; } return * slot ; } </s>

FUNC is the symbol for a locally-defined hard-float MIPS16 function . Return a local alias for it , creating a new one if necessary .


<s> SDValue Cpu0TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { return DAG . getNode ( Cpu0ISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( Cpu0 :: LR , MVT :: i32 ) ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) ) { TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = 0 ; ARMCC :: CondCodes CC = llvm :: getInstrPredicate ( Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfoImpl :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


"sret virtual register not created in the entry block"


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : case ARM :: tCMPi8 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void rs6000_emit_sISEL ( machine_mode mode ATTRIBUTE_UNUSED , rtx operands [ ] ) { rs6000_emit_int_cmove ( operands [ 0 ] , operands [ 1 ] , const1_rtx , const0_rtx ) ; } </s>


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( isPositionIndependent ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
VReg
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
MF
.
getDataLayout
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeSet
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
,
ArrayRef
<
uint64_t
>
Offsets
)
{
MIRBuilder
.
buildExtract
(
Regs
,
Offsets
,
VReg
)
;
}
)
;
FuncReturnHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
RetCC_X86
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> StackOffset ARMFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return StackOffset :: getFixed ( ResolveFrameIndexReference ( MF , FI , FrameReg , 0 ) ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> const LC2200RegisterInfo * getRegisterInfo ( ) const override { return & RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> rtx rs6000_find_base_term ( rtx op ) { rtx base ; base = op ; if ( GET_CODE ( base ) == CONST ) base = XEXP ( base , 0 ) ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , 0 ) ; if ( GET_CODE ( base ) == UNSPEC ) switch ( XINT ( base , 1 ) ) { case UNSPEC_TOCREL : case UNSPEC_MACHOPIC_OFFSET : return XVECEXP ( base , 0 , 0 ) ; } return op ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < SparcSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"


<s> static bool arm_class_likely_spilled_p ( reg_class_t rclass ) { if ( ( TARGET_THUMB1 && rclass == LO_REGS ) || rclass == CC_REG ) return true ; return default_class_likely_spilled_p ( rclass ) ; } </s>

Implement TARGET_CLASS_LIKELY_SPILLED_P . We need to define this for LO_REGS on Thumb-1 . Otherwise we can end up using r0-r4 for function arguments , r7 for the stack frame and do n't have enough left over to do doubleword arithmetic . For Thumb-2 all the potentially problematic instructions accept high registers so this is not necessary . Care needs to be taken to avoid adding new Thumb-2 patterns that require many low registers .


<s> bool X86TTIImpl :: isLegalMaskedScatter ( Type * DataType , MaybeAlign Alignment ) { if ( ! ST -> hasAVX512 ( ) ) return false ; return isLegalMaskedGather ( DataType , Alignment ) ; } </s>

Return true if the target supports masked scatter .


<s> static rtx sparc_function_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { return sparc_function_arg_1 ( cum , mode , type , named , false ) ; } </s>

Handle the TARGET_FUNCTION_ARG target hook .


<s> bool sh_reg_dead_or_unused_after_insn ( const rtx_insn * i , int regno ) { return find_regno_note ( i , REG_DEAD , regno ) != NULL || find_regno_note ( i , REG_UNUSED , regno ) != NULL ; } </s>

Given an insn and a reg number , tell whether the reg dies or is unused after the insn .


<s> bool sh_vector_mode_supported_p ( enum machine_mode mode ) { if ( TARGET_FPU_ANY && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode == V2SImode ) ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> void X86WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; emitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


<s> virtual const TeeRISCRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> EVT SparcTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void sparc_profile_hook ( int labelno ) { char buf [ 32 ] ; rtx lab , fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; lab = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_FUNCTION ) ; emit_library_call ( fun , LCT_NORMAL , VOIDmode , 1 , lab , Pmode ) ; } </s>

Output rtl to increment the profiler label LABELNO for profiling a function entry .


<s> void X86PassConfig :: addPreEmitPass2 ( ) { addPass ( createX86RetpolineThunksPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: PPC32_GOT : return "PPCISD::PPC32_GOT" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool mips_symbolic_constant_p ( rtx x , enum mips_symbol_context context , enum mips_symbol_type * symbol_type ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) { * symbol_type = mips_classify_symbol ( x , context ) ; if ( * symbol_type == SYMBOL_TLS ) return false ; } else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_ABSOLUTE : case SYMBOL_64_HIGH : case SYMBOL_64_MID : case SYMBOL_64_LOW : if ( Pmode == DImode && ! ABI_HAS_64BIT_SYMBOLS ) return offset_within_block_p ( x , INTVAL ( offset ) ) ; return true ; case SYMBOL_PC_RELATIVE : if ( GET_CODE ( x ) == LABEL_REF ) return true ; case SYMBOL_GP_RELATIVE : return offset_within_block_p ( x , INTVAL ( offset ) ) ; case SYMBOL_GOT_PAGE_OFST : case SYMBOL_GOTOFF_PAGE : return SMALL_INT ( offset ) ; case SYMBOL_TPREL : case SYMBOL_DTPREL : return mips_offset_within_alignment_p ( x , INTVAL ( offset ) ) ; case SYMBOL_GOT_DISP : case SYMBOL_GOTOFF_DISP : case SYMBOL_GOTOFF_CALL : case SYMBOL_GOTOFF_LOADGP : case SYMBOL_TLSGD : case SYMBOL_TLSLDM : case SYMBOL_GOTTPREL : case SYMBOL_TLS : case SYMBOL_HALF : return false ; } gcc_unreachable ( ) ; } </s>

Return true if X is a symbolic constant that can be calculated in the same way as a bare symbol . If it is , store the type of the symbol in * SYMBOL_TYPE .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
FNEG
:
case
ISD
::
FABS
:
return
LowerF64Op
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::FNEG
ISD::FABS
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case Mips :: BPOSGE32_PSEUDO : return emitBPOSGE32 ( MI , BB ) ; case Mips :: SNZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_B ) ; case Mips :: SNZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_H ) ; case Mips :: SNZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_W ) ; case Mips :: SNZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_D ) ; case Mips :: SNZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_V ) ; case Mips :: SZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_B ) ; case Mips :: SZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_H ) ; case Mips :: SZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_W ) ; case Mips :: SZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_D ) ; case Mips :: SZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_V ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool mips_use_pic_fn_addr_reg_p ( const_rtx x ) { if ( ! TARGET_USE_PIC_FN_ADDR_REG ) return false ; if ( mips16_stub_function_p ( x ) ) return false ; if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( TARGET_ABICALLS_PIC0 ) return false ; if ( TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p ( x ) && ! SYMBOL_REF_EXTERNAL_P ( x ) ) return false ; } return true ; } </s>

Return true if calls to X might need $ 25 to be valid on entry .


<s> bool ARMTTIImpl :: isLoweredToCall ( const Function * F ) { if ( ! F -> isIntrinsic ( ) ) BaseT :: isLoweredToCall ( F ) ; if ( F -> getName ( ) . startswith ( "llvm.arm" ) ) return false ; switch ( F -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: powi : case Intrinsic :: sin : case Intrinsic :: cos : case Intrinsic :: pow : case Intrinsic :: log : case Intrinsic :: log10 : case Intrinsic :: log2 : case Intrinsic :: exp : case Intrinsic :: exp2 : return true ; case Intrinsic :: sqrt : case Intrinsic :: fabs : case Intrinsic :: copysign : case Intrinsic :: floor : case Intrinsic :: ceil : case Intrinsic :: trunc : case Intrinsic :: rint : case Intrinsic :: nearbyint : case Intrinsic :: round : case Intrinsic :: canonicalize : case Intrinsic :: lround : case Intrinsic :: llround : case Intrinsic :: lrint : case Intrinsic :: llrint : if ( F -> getReturnType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( F -> getReturnType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return ! ST -> hasFPARMv8Base ( ) && ! ST -> hasVFP2Base ( ) ; case Intrinsic :: masked_store : case Intrinsic :: masked_load : case Intrinsic :: masked_gather : case Intrinsic :: masked_scatter : return ! ST -> hasMVEIntegerOps ( ) ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: sadd_sat : case Intrinsic :: uadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: usub_sat : return false ; } return BaseT :: isLoweredToCall ( F ) ; } </s>

Test whether calls to a function lower to actual program function calls .


";; %smode fixup for i%d; addr %lu, range (%ld,%ld): "

Record INSN , which will need fixing up to load a value from the minipool . ADDRESS is the offset of the insn since the start of the function ; LOC is a pointer to the part of the insn which requires fixing ; VALUE is the constant that must be loaded , which is of type MODE .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , Alignment ) ; else OS . emitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> static HOST_WIDE_INT mmix_starting_frame_offset ( void ) { return ( - 8 + ( MMIX_CFUN_HAS_LANDING_PAD ? - 16 : ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? - 8 : 0 ) ) ) ; } </s>


<s> bool SystemZTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s>
virtual
StringRef
getPassName
(
)
const
{
return
StringRef
(
"SHUXI Assembly Printer"
)
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned int execute ( function * ) { return nds32_fp_as_gp ( ) ; } </s>


<s> const Cpu0MCExpr * Cpu0MCExpr :: create ( const MCSymbol * Symbol , Cpu0MCExpr :: Cpu0ExprKind Kind , MCContext & Ctx ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; return new ( Ctx ) Cpu0MCExpr ( Kind , MCSym ) ; } </s>


<s> void ix86_function_specific_restore ( struct gcc_options * opts , struct gcc_options * , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned HOST_WIDE_INT ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; ix86_prefetch_sse = ptr -> prefetch_sse ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; ix86_tune_cost = processor_cost_table [ ix86_tune ] ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = HOST_WIDE_INT_1U << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( opts , ix86_tune , false ) ; } </s>


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"


"use of %<long%> in AltiVec types is invalid for 64-bit code"

"use of %<long%> in AltiVec types is deprecated; use %<int%>"

"use of %<long long%> in AltiVec types is invalid"

"use of %<double%> in AltiVec types is invalid"

"use of %<long double%> in AltiVec types is invalid"

"use of boolean types in AltiVec types is invalid"

"use of %<complex%> in AltiVec types is invalid"

Handle the `` altivec '' attribute . The attribute may have arguments as follows : __attribute__ ( ( altivec ( vector__ ) ) ) __attribute__ ( ( altivec ( pixel__ ) ) ) ( always followed by 'unsigned short ' ) __attribute__ ( ( altivec ( bool__ ) ) ) ( always followed by 'unsigned ' ) and may appear more than once ( e.g. , 'vector bool char ' ) in a given declaration .


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SystemZ
::
GR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_h64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_h64
)
,
KillSrc
)
;
MachineInstrBuilder
(
*
MBB
.
getParent
(
)
,
std
::
prev
(
MBBI
)
)
.
addReg
(
SrcReg
,
RegState
::
Implicit
)
;
copyPhysReg
(
MBB
,
MBBI
,
DL
,
RI
.
getSubReg
(
DestReg
,
SystemZ
::
subreg_l64
)
,
RI
.
getSubReg
(
SrcReg
,
SystemZ
::
subreg_l64
)
,
KillSrc
)
;
MachineInstrBuilder
(
*
MBB
.
getParent
(
)
,
std
::
prev
(
MBBI
)
)
.
addReg
(
SrcReg
,
(
getKillRegState
(
KillSrc
)
|
RegState
::
Implicit
)
)
;
return
;
}
if
(
SystemZ
::
GRX32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
emitGRX32Move
(
MBB
,
MBBI
,
DL
,
DestReg
,
SrcReg
,
SystemZ
::
LR
,
32
,
KillSrc
,
false
)
;
return
;
}
unsigned
Opcode
;
if
(
SystemZ
::
GR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LGR
;
else
if
(
SystemZ
::
FP32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
STI
.
hasVector
(
)
SystemZ
::
LDR32
:
SystemZ
::
LER
;
else
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LDR
;
else
if
(
SystemZ
::
FP128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
LXR
;
else
if
(
SystemZ
::
VR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR32
;
else
if
(
SystemZ
::
VR64BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR64
;
else
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
VLR
;
else
if
(
SystemZ
::
AR32BitRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
SystemZ
::
CPYA
;
else
if
(
SystemZ
::
AR32BitRegClass
.
contains
(
DestReg
)
&&
SystemZ
::
GR32BitRegClass
.
contains
(
SrcReg
)
)
Opcode
=
SystemZ
::
SAR
;
else
if
(
SystemZ
::
GR32BitRegClass
.
contains
(
DestReg
)
&&
SystemZ
::
AR32BitRegClass
.
contains
(
SrcReg
)
)
Opcode
=
SystemZ
::
EAR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> void sh_split_tst_subregs ( rtx_insn * curr_insn , machine_mode subreg_mode , int subreg_offset , rtx operands [ ] ) { gcc_assert ( subreg_mode == QImode || subreg_mode == HImode ) ; sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg ( operands [ 0 ] , curr_insn ) ; sh_extending_set_of_reg eop1 = sh_find_extending_set_of_reg ( operands [ 1 ] , curr_insn ) ; if ( eop0 . ext_code == ZERO_EXTEND && eop0 . from_mode == subreg_mode ) { emit_insn ( gen_tstsi_t ( eop0 . use_as_extended_reg ( curr_insn ) , operands [ 1 ] ) ) ; return ; } if ( eop1 . ext_code == ZERO_EXTEND && eop1 . from_mode == subreg_mode ) { emit_insn ( gen_tstsi_t ( operands [ 0 ] , eop1 . use_as_extended_reg ( curr_insn ) ) ) ; return ; } if ( eop0 . ext_code == SIGN_EXTEND && eop1 . ext_code == SIGN_EXTEND && eop0 . from_mode == subreg_mode && eop1 . from_mode == subreg_mode ) { emit_insn ( gen_tstsi_t ( eop0 . use_as_extended_reg ( curr_insn ) , eop1 . use_as_extended_reg ( curr_insn ) ) ) ; return ; } if ( eop0 . ext_code != UNKNOWN && eop1 . ext_code == UNKNOWN ) std :: swap ( operands [ 0 ] , operands [ 1 ] ) ; rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = simplify_gen_subreg ( subreg_mode , operands [ 0 ] , GET_MODE ( operands [ 0 ] ) , subreg_offset ) ; emit_insn ( subreg_mode == QImode ? gen_zero_extendqisi2 ( tmp0 , tmp1 ) : gen_zero_extendhisi2 ( tmp0 , tmp1 ) ) ; emit_insn ( gen_tstsi_t ( tmp0 , operands [ 1 ] ) ) ; } </s>

Given the current insn , which is assumed to be the * tst < mode > _t_subregs insn , perform the necessary checks on the operands and split it accordingly .


<s> static void ix86_dependencies_evaluation_hook ( rtx_insn * head , rtx_insn * tail ) { rtx_insn * insn ; rtx_insn * first_arg = NULL ; if ( reload_completed ) return ; while ( head != tail && DEBUG_INSN_P ( head ) ) head = NEXT_INSN ( head ) ; for ( insn = tail ; insn != head ; insn = PREV_INSN ( insn ) ) if ( INSN_P ( insn ) && CALL_P ( insn ) ) { first_arg = add_parameter_dependencies ( insn , head ) ; if ( first_arg ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; int rgn = CONTAINING_RGN ( bb -> index ) ; int nr_blks = RGN_NR_BLOCKS ( rgn ) ; if ( nr_blks > 1 && BLOCK_TO_BB ( bb -> index ) != 0 ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { if ( rgn == CONTAINING_RGN ( e -> src -> index ) && BLOCK_TO_BB ( bb -> index ) > BLOCK_TO_BB ( e -> src -> index ) ) add_dependee_for_func_arg ( first_arg , e -> src ) ; } } insn = first_arg ; if ( insn == head ) break ; } } else if ( first_arg ) avoid_func_arg_motion ( first_arg , insn ) ; } </s>

Hook for pre-reload schedule - avoid motion of function arguments passed in likely spilled HW registers .


<s> static void expand_csky_stack_adjust ( int offset ) { rtx set ; rtx_insn * insn ; int size = ( offset > 0 ? offset : - offset ) ; if ( offset == 0 ) return ; if ( size > CSKY_MAX_SP_ADJUST * 2 ) { rtx tmp , dwarf ; gcc_assert ( cfun -> machine -> reg_size != 0 && ( cfun -> machine -> reg_mask & ( 1 << CSKY_STACKADJUST_REGNUM ) ) ) ; if ( ! flag_sched_prolog ) emit_insn ( gen_blockage ( ) ) ; tmp = gen_rtx_REG ( SImode , CSKY_STACKADJUST_REGNUM ) ; emit_move_insn ( tmp , GEN_INT ( size ) ) ; if ( offset > 0 ) set = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ; else set = gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ; insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; dwarf = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; if ( ! flag_sched_prolog ) emit_insn ( gen_blockage ( ) ) ; } else while ( size ) { int delta = ( size > CSKY_MAX_SP_ADJUST ? CSKY_MAX_SP_ADJUST : size ) ; if ( offset > 0 ) set = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( delta ) ) ; else set = gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( delta ) ) ; insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; size -= delta ; } } </s>

Adjust the stack pointer by OFFSET bytes . OFFSET is negative if this is in the prologue , positive if in the epilogue . This may require multiple instructions and/or use of CSKY_STACKADJUST_REGNUM as a scratch register . Emit CFA notes as appropriate .


"the ABI for returning a value containing "

"zero-width bit-fields but otherwise an aggregate "

"with only one or two floating-point fields was "

"the ABI for returning a value with C++17 empty "

"bases but otherwise an aggregate with only one or "

"two floating-point fields was changed in GCC "

Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


<s>
const
char
*
nds32_output_float_load
(
rtx
*
operands
)
{
char
buff
[
100
]
;
const
char
*
pattern
;
rtx
addr
,
addr_op0
,
addr_op1
;
int
dp
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
8
;
addr
=
XEXP
(
operands
[
1
]
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
pattern
=
"fl%ci\t%%0, %%1"
;
break
;
case
PLUS
:
addr_op0
=
XEXP
(
addr
,
0
)
;
addr_op1
=
XEXP
(
addr
,
1
)
;
if
(
REG_P
(
addr_op0
)
&&
REG_P
(
addr_op1
)
)
pattern
=
"fl%c\t%%0, %%1"
;
else
if
(
REG_P
(
addr_op0
)
&&
CONST_INT_P
(
addr_op1
)
)
pattern
=
"fl%ci\t%%0, %%1"
;
else
if
(
GET_CODE
(
addr_op0
)
==
MULT
&&
REG_P
(
addr_op1
)
&&
REG_P
(
XEXP
(
addr_op0
,
0
)
)
&&
CONST_INT_P
(
XEXP
(
addr_op0
,
1
)
)
)
pattern
=
"fl%c\t%%0, %%1"
;
else
gcc_unreachable
(
)
;
break
;
case
POST_MODIFY
:
addr_op0
=
XEXP
(
addr
,
0
)
;
addr_op1
=
XEXP
(
addr
,
1
)
;
if
(
REG_P
(
addr_op0
)
&&
GET_CODE
(
addr_op1
)
==
PLUS
&&
REG_P
(
XEXP
(
addr_op1
,
1
)
)
)
pattern
=
"fl%c.bi\t%%0, %%1"
;
else
if
(
REG_P
(
addr_op0
)
&&
GET_CODE
(
addr_op1
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
addr_op1
,
1
)
)
)
pattern
=
"fl%ci.bi\t%%0, %%1"
;
else
gcc_unreachable
(
)
;
break
;
case
POST_INC
:
if
(
REG_P
(
XEXP
(
addr
,
0
)
)
)
{
if
(
dp
)
pattern
=
"fl%ci.bi\t%%0, %%1, 8"
;
else
pattern
=
"fl%ci.bi\t%%0, %%1, 4"
;
}
else
gcc_unreachable
(
)
;
break
;
case
POST_DEC
:
if
(
REG_P
(
XEXP
(
addr
,
0
)
)
)
{
if
(
dp
)
pattern
=
"fl%ci.bi\t%%0, %%1, -8"
;
else
pattern
=
"fl%ci.bi\t%%0, %%1, -4"
;
}
else
gcc_unreachable
(
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
sprintf
(
buff
,
pattern
,
dp
'd'
:
's'
)
;
output_asm_insn
(
buff
,
operands
)
;
return
""
;
}
</s>