<s>
const
char
*
pa_output_millicode_call
(
rtx_insn
*
insn
,
rtx
call_dest
)
{
int
attr_length
=
get_attr_length
(
insn
)
;
int
seq_length
=
dbr_sequence_length
(
)
;
rtx
xoperands
[
3
]
;
xoperands
[
0
]
=
call_dest
;
xoperands
[
2
]
=
gen_rtx_REG
(
Pmode
,
TARGET_64BIT
2
:
31
)
;
if
(
!
TARGET_LONG_CALLS
&&
(
attr_length
==
8
||
(
attr_length
==
28
&&
get_attr_type
(
insn
)
==
TYPE_SH_FUNC_ADRS
)
)
)
{
output_asm_insn
(
"{bl|b,l} %0,%2"
,
xoperands
)
;
}
else
{
if
(
TARGET_64BIT
)
{
output_asm_insn
(
"b,l .+8,%%r1"
,
xoperands
)
;
if
(
TARGET_GAS
)
{
output_asm_insn
(
"addil L'%0-$PIC_pcrel$0+4,%%r1"
,
xoperands
)
;
output_asm_insn
(
"ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1"
,
xoperands
)
;
}
else
{
xoperands
[
1
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"addil L'%0-%l1,%%r1"
,
xoperands
)
;
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
xoperands
[
1
]
)
)
;
output_asm_insn
(
"ldo R'%0-%l1(%%r1),%%r1"
,
xoperands
)
;
}
output_asm_insn
(
"bve,l (%%r1),%%r2"
,
xoperands
)
;
}
else
if
(
TARGET_PORTABLE_RUNTIME
)
{
output_asm_insn
(
"ldil L'%0,%%r1"
,
xoperands
)
;
output_asm_insn
(
"ldo R'%0(%%r1),%%r1"
,
xoperands
)
;
output_asm_insn
(
"{bl|b,l} .+8,%%r31"
,
xoperands
)
;
output_asm_insn
(
"addi 8,%%r31,%%r31"
,
xoperands
)
;
output_asm_insn
(
"bv %%r0(%%r1)"
,
xoperands
)
;
}
else
if
(
!
flag_pic
)
{
output_asm_insn
(
"ldil L'%0,%%r1"
,
xoperands
)
;
if
(
TARGET_PA_20
)
output_asm_insn
(
"be,l R'%0(%%sr4,%%r1),%%sr0,%%r31"
,
xoperands
)
;
else
output_asm_insn
(
"ble R'%0(%%sr4,%%r1)"
,
xoperands
)
;
}
else
{
output_asm_insn
(
"{bl|b,l} .+8,%%r1"
,
xoperands
)
;
output_asm_insn
(
"addi 16,%%r1,%%r31"
,
xoperands
)
;
if
(
TARGET_SOM
||
!
TARGET_GAS
)
{
xoperands
[
1
]
=
gen_label_rtx
(
)
;
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
xoperands
[
1
]
)
)
;
output_asm_insn
(
"addil L'%0-%l1,%%r1"
,
xoperands
)
;
output_asm_insn
(
"ldo R'%0-%l1(%%r1),%%r1"
,
xoperands
)
;
}
else
{
output_asm_insn
(
"addil L'%0-$PIC_pcrel$0+8,%%r1"
,
xoperands
)
;
output_asm_insn
(
"ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1"
,
xoperands
)
;
}
output_asm_insn
(
"bv %%r0(%%r1)"
,
xoperands
)
;
}
}
if
(
seq_length
==
0
)
output_asm_insn
(
"nop"
,
xoperands
)
;
return
""
;
}
</s>

INSN is a function call . CALL_DEST is the routine we are calling .


<s> static section * pa_function_section ( tree decl , enum node_frequency freq , bool startup , bool exit ) { if ( ! targetm_common . have_named_sections ) return text_section ; if ( decl && DECL_SECTION_NAME ( decl ) == NULL && DECL_CONTEXT ( decl ) != NULL_TREE && TREE_CODE ( DECL_CONTEXT ( decl ) ) == FUNCTION_DECL && DECL_SECTION_NAME ( DECL_CONTEXT ( decl ) ) == NULL ) return function_section ( DECL_CONTEXT ( decl ) ) ; return default_function_section ( decl , freq , startup , exit ) ; } </s>


<s> void pa_hpux_asm_output_external ( FILE * file , tree decl , const char * name ) { extern_symbol * p = VEC_safe_push ( extern_symbol , gc , extern_symbols , NULL ) ; gcc_assert ( file == asm_out_file ) ; p -> decl = decl ; p -> name = name ; } </s>

Mark DECL ( name NAME ) as an external reference ( assembler output file FILE ) . This saves the names to output at the end of the file if actually referenced .


<s>
SDValue
MINA32TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
llvm_unreachable
(
"LowerOperation() unimplemented"
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> bool AArch64TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { if ( ! getTargetMachine ( ) . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return false ; return Subtarget -> ClassifyGlobalReference ( GA -> getGlobal ( ) , getTargetMachine ( ) ) == AArch64II :: MO_NO_FLAG ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> const MCPhysReg * CSKYRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const CSKYSubtarget & STI = MF -> getSubtarget < CSKYSubtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { if ( STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64v3_ISR_SaveList ; if ( STI . hasFPUv3SingleFloat ( ) ) return CSR_GPR_FPR32v3_ISR_SaveList ; if ( STI . hasFPUv2DoubleFloat ( ) ) return CSR_GPR_FPR64_ISR_SaveList ; if ( STI . hasFPUv2SingleFloat ( ) ) return CSR_GPR_FPR32_ISR_SaveList ; return CSR_GPR_ISR_SaveList ; } if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64_SaveList ; if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) return CSR_GPR_FPR32_SaveList ; return CSR_I32_SaveList ; } </s>


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned int UPTInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { unsigned NumInserted = 0 ; if ( ! Cond . empty ( ) ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( UPT :: Bcc ) ) . add ( Cond [ 0 ] ) . addMBB ( TBB ) ; NumInserted ++ ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( UPT :: JMP ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ; } return NumInserted ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s>
MachineBasicBlock
*
SystemZTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
,
DenseMap
<
MachineBasicBlock
*
,
MachineBasicBlock
*
>
*
EM
)
const
{
const
SystemZInstrInfo
&
TII
=
*
TM
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
SystemZ
::
Select32
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF32
||
MI
->
getOpcode
(
)
==
SystemZ
::
Select64
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF64
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
SystemZCC
::
CondCodes
CC
=
(
SystemZCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
BuildMI
(
BB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
copy1MBB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
SI
=
BB
->
succ_begin
(
)
,
SE
=
BB
->
succ_end
(
)
;
SI
!=
SE
;
++
SI
)
EM
->
insert
(
std
::
make_pair
(
*
SI
,
copy1MBB
)
)
;
copy1MBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SystemZ
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool ix86_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( BND_REGNO_P ( regno ) ) return VALID_BND_REG_MODE ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> void OR1KAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns , DoRegPressureReduce ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; if ( STI . hasLoadStoreOnCond2 ( ) && getConditionalLoadImmediate ( Opcode ) ) return true ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: Trap || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::Trap SystemZ::CallJG SystemZ::CallBR


<s> void aarch64_split_sve_subreg_move ( rtx dest , rtx ptrue , rtx src ) { machine_mode mode_with_wider_elts = aarch64_sve_int_mode ( GET_MODE ( dest ) ) ; machine_mode mode_with_narrower_elts = aarch64_sve_int_mode ( GET_MODE ( src ) ) ; if ( GET_MODE_UNIT_SIZE ( mode_with_wider_elts ) < GET_MODE_UNIT_SIZE ( mode_with_narrower_elts ) ) std :: swap ( mode_with_wider_elts , mode_with_narrower_elts ) ; unsigned int unspec = aarch64_sve_rev_unspec ( mode_with_narrower_elts ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( mode_with_wider_elts ) ; ptrue = gen_lowpart ( pred_mode , ptrue ) ; dest = aarch64_replace_reg_mode ( dest , mode_with_wider_elts ) ; src = aarch64_replace_reg_mode ( src , mode_with_wider_elts ) ; emit_insn ( gen_aarch64_pred ( unspec , mode_with_wider_elts , dest , ptrue , src ) ) ; } </s>

Split a * aarch64_sve_mov < mode > _subreg_be pattern with the given operands .


<s> bool rs6000_emit_set_const ( rtx dest , rtx source ) { machine_mode mode = GET_MODE ( dest ) ; rtx temp , set ; rtx_insn * insn ; HOST_WIDE_INT c ; gcc_checking_assert ( CONST_INT_P ( source ) ) ; c = INTVAL ( source ) ; switch ( mode ) { case E_QImode : case E_HImode : emit_insn ( gen_rtx_SET ( dest , source ) ) ; return true ; case E_SImode : temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) 0xffff ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & 0xffff ) ) ) ) ; break ; case E_DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == 0 , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != 0 , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> 32 ) ) ; c = ( ( c & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT ( c ) ) ; return true ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s> SDValue MipsSETargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Val ; switch ( N -> getOpcode ( ) ) { case ISD :: ADDE : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMULCombine ( N , DAG , DCI , this ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRA : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SRL : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: VSELECT : return performVSELECTCombine ( N , DAG ) ; case ISD :: SETCC : { Val = performSETCCCombine ( N , DAG ) ; break ; } } if ( Val . getNode ( ) ) return Val ; return MipsTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::MUL ISD::SHL ISD::SRA ISD::SRL ISD::VSELECT ISD::SETCC Mips


<s> void X86WinAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; assert ( SlotSize == 4 || SlotSize == 8 ) ; unsigned RegA = ( SlotSize == 8 ) ? X86 :: RAX : X86 :: EAX ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; break ; } unsigned AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; for ( ; ; ) { if ( ! MRI -> use_empty ( AmountReg ) ) break ; MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ; if ( ! AmountDef ) break ; if ( AmountDef -> isCopy ( ) && AmountDef -> getOperand ( 1 ) . isReg ( ) ) AmountReg = AmountDef -> getOperand ( 1 ) . isReg ( ) ; AmountDef -> eraseFromParent ( ) ; break ; } } </s>


<s> const char * rs6000_xcoff_strip_dollar ( const char * name ) { char * strip , * p ; const char * q ; size_t len ; q = ( const char * ) strchr ( name , '$' ) ; if ( q == 0 || q == name ) return name ; len = strlen ( name ) ; strip = XALLOCAVEC ( char , len + 1 ) ; strcpy ( strip , name ) ; p = strip + ( q - name ) ; while ( p ) { * p = '_' ; p = strchr ( p + 1 , '$' ) ; } return ggc_alloc_string ( strip , len ) ; } </s>

Return a GGC-allocated character string translating dollar signs in input NAME to underscores . Used by XCOFF ASM_OUTPUT_LABELREF .


<s> static int aarch64_reassociation_width ( unsigned opc ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) return aarch64_tune_params . vec_reassoc_width ; if ( INTEGRAL_MODE_P ( mode ) ) return aarch64_tune_params . int_reassoc_width ; if ( FLOAT_MODE_P ( mode ) ) return aarch64_tune_params . fp_reassoc_width ; return 1 ; } </s>

Return the reassociation width of treeop OPC with mode MODE .


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void ix86_lower_local_decl_alignment ( tree decl ) { unsigned int new_align = ix86_local_alignment ( decl , VOIDmode , DECL_ALIGN ( decl ) , true ) ; if ( new_align < DECL_ALIGN ( decl ) ) SET_DECL_ALIGN ( decl , new_align ) ; } </s>


<s> static void * rs6000_alloc_sched_context ( void ) { return xmalloc ( sizeof ( rs6000_sched_context_def ) ) ; } </s>

Allocate store for new scheduling context .


<s> static rtx function_arg_record_value ( const_tree type , machine_mode mode , int slotno , bool named , int regbase ) { HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; assign_data_t data ; int nregs ; data . slotno = slotno ; data . regbase = regbase ; data . nregs = 0 ; data . intoffset = 0 ; data . stack = false ; traverse_record_type < assign_data_t , count_registers > ( type , named , & data ) ; if ( compute_int_layout ( typesize * BITS_PER_UNIT , & data , & nregs ) ) data . nregs += nregs ; nregs = data . nregs ; if ( nregs == 0 ) { if ( typesize <= 0 ) { return gen_rtx_REG ( mode , regbase ) ; } nregs = ( typesize + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs > 0 ) ; data . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( data . stack + nregs ) ) ; if ( data . stack ) XVECEXP ( data . ret , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; data . nregs = 0 ; data . intoffset = 0 ; traverse_record_type < assign_data_t , assign_registers > ( type , named , & data ) ; assign_int_registers ( typesize * BITS_PER_UNIT , & data ) ; gcc_assert ( data . nregs == nregs ) ; return data . ret ; } </s>

Used by function_arg and sparc_function_value_1 to implement the complex conventions of the 64-bit ABI for passing and returning structures . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . MODE is the argument 's machine mode . SLOTNO is the index number of the argument 's slot in the parameter array . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . REGBASE is the regno of the base register for the parameter array .


<s> int mt_epilogue_uses ( int regno ) { if ( cfun -> machine && cfun -> machine -> interrupt_handler && reload_completed ) return 1 ; return regno == GPR_LINK ; } </s>


<s> int arm_count_ldrdstrd_insns ( rtx * operands , bool load ) { int count ; rtx ops [ 2 ] ; int regnum , memnum ; if ( load ) regnum = 0 , memnum = 1 ; else regnum = 1 , memnum = 0 ; ops [ regnum ] = gen_rtx_REG ( DImode , REGNO ( operands [ 0 ] ) ) ; ops [ memnum ] = adjust_address ( operands [ 2 ] , DImode , 0 ) ; output_move_double ( ops , false , & count ) ; return count ; } </s>

Same as above , but operands are a register/memory pair in SImode . Assumes operands has the base register in position 0 and memory in position 2 ( which is the order provided by the arm_ { ldrd , strd } patterns ) .


<s> int rs6000_trampoline_size ( ) { int ret = 0 ; switch ( DEFAULT_ABI ) { default : abort ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? 12 : 24 ; break ; case ABI_DARWIN : case ABI_V4 : case ABI_AIX_NODESC : ret = ( TARGET_32BIT ) ? 40 : 48 ; break ; } return ret ; } </s>

Length in units of the trampoline for entering a nested function .


<s> bool isMicroMips ( const MCSubtargetInfo & STI ) const { return STI . getFeatureBits ( ) & Mips :: FeatureMicroMips ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


<s> static void aarch64_emit_atomic_load_op ( enum aarch64_atomic_load_op_code code , machine_mode mode , rtx dst , rtx src , rtx mem , rtx model ) { typedef rtx ( * aarch64_atomic_load_op_fn ) ( rtx , rtx , rtx , rtx ) ; const aarch64_atomic_load_op_fn plus [ ] = { gen_aarch64_atomic_loadaddqi , gen_aarch64_atomic_loadaddhi , gen_aarch64_atomic_loadaddsi , gen_aarch64_atomic_loadadddi } ; const aarch64_atomic_load_op_fn eor [ ] = { gen_aarch64_atomic_loadeorqi , gen_aarch64_atomic_loadeorhi , gen_aarch64_atomic_loadeorsi , gen_aarch64_atomic_loadeordi } ; const aarch64_atomic_load_op_fn ior [ ] = { gen_aarch64_atomic_loadsetqi , gen_aarch64_atomic_loadsethi , gen_aarch64_atomic_loadsetsi , gen_aarch64_atomic_loadsetdi } ; const aarch64_atomic_load_op_fn bic [ ] = { gen_aarch64_atomic_loadclrqi , gen_aarch64_atomic_loadclrhi , gen_aarch64_atomic_loadclrsi , gen_aarch64_atomic_loadclrdi } ; aarch64_atomic_load_op_fn gen ; int idx = 0 ; switch ( mode ) { case QImode : idx = 0 ; break ; case HImode : idx = 1 ; break ; case SImode : idx = 2 ; break ; case DImode : idx = 3 ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case AARCH64_LDOP_PLUS : gen = plus [ idx ] ; break ; case AARCH64_LDOP_XOR : gen = eor [ idx ] ; break ; case AARCH64_LDOP_OR : gen = ior [ idx ] ; break ; case AARCH64_LDOP_BIC : gen = bic [ idx ] ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , mem , src , model ) ) ; } </s>


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
Fn
.
getTarget
(
)
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool PPCPassConfig :: addPreRegAlloc ( ) { if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoops ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
Optional
<
RegImmPair
>
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
Register
Reg
)
const
{
int
Sign
=
1
;
int64_t
Offset
=
0
;
if
(
Reg
!=
MI
.
getOperand
(
0
)
.
getReg
(
)
)
return
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
;
Offset
=
MI
.
getOperand
(
2
)
.
getImm
(
)
*
Sign
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Offset
<<
Shift
;
}
}
return
RegImmPair
{
MI
.
getOperand
(
1
)
.
getReg
(
)
,
Offset
}
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) ) ) return 0 ; OpNum = 1 ; const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isUndef ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) ) { return UndefRegClearance ; } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> static int get_some_local_dynamic_name_1 ( rtx * px , void * data ATTRIBUTE_UNUSED ) { rtx x = * px ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) { cfun -> machine -> some_ld_name = XSTR ( x , 0 ) ; return 1 ; } return 0 ; } </s>


<s> bool ARMTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { if ( Level == BeforeLegalizeTypes ) return true ; if ( Subtarget -> isThumb ( ) && Subtarget -> isThumb1Only ( ) ) return true ; if ( N -> getOpcode ( ) != ISD :: SHL ) return true ; return false ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s>
const
CallLowering
*
X86Subtarget
::
getCallLowering
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getCallLowering
(
)
;
}
</s>


<s> void ARMBaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( I , MI ) ; break ; } case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; ( * MIB ) . setMemRefs ( Orig -> memoperands_begin ( ) , Orig -> memoperands_end ( ) ) ; break ; } } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; unsigned Align = 1 << LogAlign ; return ( PO + Align - 1 ) / Align * Align ; } </s>

Compute the offset immediately following this block .


<s> int mt_initial_elimination_offset ( int from , int to ) { mt_compute_frame_size ( get_frame_size ( ) ) ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return 0 ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return current_frame_info . total_size ; else if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) return current_frame_info . total_size ; else gcc_unreachable ( ) ; } </s>


<s> static rtx rs6000_spe_function_arg ( const CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type ) { int gregno = cum -> sysv_gregno ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == TFmode || mode == DCmode || mode == TCmode ) ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( mode == DFmode ) gregno += ( 1 - gregno ) & 1 ; if ( gregno + n_words - 1 > GP_ARG_MAX_REG ) return NULL_RTX ; return spe_build_register_parallel ( mode , gregno ) ; } if ( cum -> stdarg ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( n_words == 2 && ( gregno & 1 ) == 0 ) gregno += 1 ; if ( gregno + n_words - 1 <= GP_ARG_MAX_REG ) { rtx r1 , r2 ; machine_mode m = SImode ; r1 = gen_rtx_REG ( m , gregno ) ; r1 = gen_rtx_EXPR_LIST ( m , r1 , const0_rtx ) ; r2 = gen_rtx_REG ( m , gregno + 1 ) ; r2 = gen_rtx_EXPR_LIST ( m , r2 , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } else return NULL_RTX ; } else { if ( gregno <= GP_ARG_MAX_REG ) return gen_rtx_REG ( mode , gregno ) ; else return NULL_RTX ; } } </s>

Determine where to put a SIMD argument on the SPE .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; if ( isPPC64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , 4 ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> const MMIXSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Instr doesn't have FrameIndex operand!"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool aarch64_float_const_rtx_p ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; if ( mode == VOIDmode ) return false ; unsigned HOST_WIDE_INT ival ; if ( CONST_DOUBLE_P ( x ) && SCALAR_FLOAT_MODE_P ( mode ) && aarch64_reinterpret_float_as_int ( x , & ival ) ) { scalar_int_mode imode = ( mode == HFmode ? SImode : int_mode_for_mode ( mode ) . require ( ) ) ; int num_instr = aarch64_internal_mov_immediate ( NULL_RTX , gen_int_mode ( ival , imode ) , false , imode ) ; return num_instr < 3 ; } return false ; } </s>

Return TRUE if rtx X is an immediate constant that can be moved using a single MOV ( +MOVK ) followed by an FMOV .


<s> bool ARMTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: v4f32 : case MVT :: v8f16 : return Subtarget -> hasMVEFloatOps ( ) ; case MVT :: f16 : return Subtarget -> useFPVFMx16 ( ) ; case MVT :: f32 : return Subtarget -> useFPVFMx ( ) ; case MVT :: f64 : return Subtarget -> useFPVFMx64 ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> static void rename_fma_node ( fma_forest * forest , fma_node * node ) { node -> rename ( forest ) ; } </s>

Wrapper around fma_node : :dump_info for use as parameter of function pointer type in func_fma_steering : :dfs .


<s> static inline unsigned ptr_regno_for_savres ( int sel ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) return ( sel & SAVRES_REG ) == SAVRES_FPR || ( sel & SAVRES_LR ) ? 1 : 12 ; return DEFAULT_ABI == ABI_DARWIN && ( sel & SAVRES_REG ) == SAVRES_FPR ? 1 : 11 ; } </s>

Return the register number used as a pointer by out-of-line save/restore functions .


<s> void sparc_initialize_trampoline ( rtx tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 0 ) ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , size_int ( 10 ) , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x03000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 4 ) ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , size_int ( 10 ) , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x05000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 8 ) ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x81c06000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 12 ) ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , cxt , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x8410a000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_insn ( gen_flush ( validize_mem ( gen_rtx_MEM ( SImode , tramp ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 ) emit_insn ( gen_flush ( validize_mem ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 8 ) ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , tramp , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . This takes 16 insns : 2 shifts & 2 ands ( to split up addresses ) , 4 sethi ( to load in opcodes ) , 4 iors ( to merge address and opcodes ) , and 4 writes ( to store insns ) . This is a bit excessive . Perhaps a different mechanism would be better here . Emit enough FLUSH insns to synchronize the data and instruction caches .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; recog_data_d recog_data_save = recog_data ; dup = gen_vec_duplicate ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; machine_mode innermode = GET_MODE_INNER ( mode ) ; rtx reg ; start_sequence ( ) ; reg = force_reg ( innermode , val ) ; if ( GET_MODE ( reg ) != innermode ) reg = gen_lowpart ( innermode , reg ) ; SET_SRC ( PATTERN ( insn ) ) = gen_vec_duplicate ( mode , reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } recog_data = recog_data_save ; return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s> static rtx paired_expand_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; enum rs6000_builtins fcode = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; const struct builtin_description * d ; size_t i ; * expandedp = true ; switch ( fcode ) { case PAIRED_BUILTIN_STX : return paired_expand_stv_builtin ( CODE_FOR_paired_stx , exp ) ; case PAIRED_BUILTIN_LX : return paired_expand_lv_builtin ( CODE_FOR_paired_lx , exp , target ) ; default : break ; } d = bdesc_paired_preds ; for ( i = 0 ; i < ARRAY_SIZE ( bdesc_paired_preds ) ; i ++ , d ++ ) if ( d -> code == fcode ) return paired_expand_predicate_builtin ( d -> icode , exp , target ) ; * expandedp = false ; return NULL_RTX ; } </s>

Expand the builtin in EXP and store the result in TARGET . Store true in * EXPANDEDP if we found a builtin to expand .


<s> int num_insns_constant ( rtx op , enum machine_mode mode ) { HOST_WIDE_INT low , high ; switch ( GET_CODE ( op ) ) { case CONST_INT : if ( ( INTVAL ( op ) >> 31 ) != 0 && ( INTVAL ( op ) >> 31 ) != - 1 && mask64_operand ( op , mode ) ) return 2 ; else return num_insns_constant_wide ( INTVAL ( op ) ) ; case CONST_DOUBLE : if ( mode == SFmode ) { long l ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( rv , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } if ( mode == VOIDmode || mode == DImode ) { high = CONST_DOUBLE_HIGH ( op ) ; low = CONST_DOUBLE_LOW ( op ) ; } else { long l [ 2 ] ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; REAL_VALUE_TO_TARGET_DOUBLE ( rv , l ) ; high = l [ WORDS_BIG_ENDIAN == 0 ] ; low = l [ WORDS_BIG_ENDIAN != 0 ] ; } if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ; else { if ( ( high == 0 && low >= 0 ) || ( high == - 1 && low < 0 ) ) return num_insns_constant_wide ( low ) ; else if ( mask64_operand ( op , mode ) ) return 2 ; else if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } default : gcc_unreachable ( ) ; } } </s>

Return the number of instructions it takes to form a constant in as many gprs are needed for MODE .


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> RegisterBankInfo :: InstructionMapping ARMRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & ARM :: ValueMappings [ 0 ] ; switch ( Opc ) { case G_ADD : case G_LOAD : OperandsMapping = & ARM :: ValueMappings [ 0 ] ; break ; case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & ARM :: ValueMappings [ 0 ] , nullptr } ) ; break ; default : return InstructionMapping { } ; } return InstructionMapping { DefaultMappingID , 1 , OperandsMapping , NumOperands } ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> bool sh_expand_strlen ( rtx * operands ) { rtx addr1 = operands [ 1 ] ; rtx current_addr = copy_addr_to_reg ( XEXP ( addr1 , 0 ) ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; rtx_code_label * L_return = gen_label_rtx ( ) ; rtx_code_label * L_loop_byte = gen_label_rtx ( ) ; rtx_insn * jump ; rtx_code_label * L_loop_long = gen_label_rtx ( ) ; rtx_code_label * L_end_loop_long = gen_label_rtx ( ) ; int align = INTVAL ( operands [ 3 ] ) ; emit_move_insn ( operands [ 0 ] , GEN_INT ( - 1 ) ) ; emit_move_insn ( start_addr , current_addr ) ; if ( align < 4 ) { emit_insn ( gen_tstsi_t ( current_addr , GEN_INT ( 3 ) ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_move_insn ( tmp0 , operands [ 2 ] ) ; addr1 = adjust_automodify_address ( addr1 , SImode , current_addr , 0 ) ; emit_label ( L_loop_long ) ; emit_move_insn ( tmp1 , addr1 ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 4 ) ) ; emit_insn ( gen_cmpstr_t ( tmp0 , tmp1 ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_long ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_end_loop_long ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , - 4 ) ) ; addr1 = adjust_address ( addr1 , QImode , 0 ) ; for ( int i = 0 ; i < 4 ; ++ i ) { emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 1 ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_true ( L_return ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_barrier_after ( jump ) ; emit_label ( L_loop_byte ) ; emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 1 ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_return ) ; emit_insn ( gen_addsi3 ( start_addr , start_addr , GEN_INT ( 1 ) ) ) ; emit_insn ( gen_subsi3 ( operands [ 0 ] , current_addr , start_addr ) ) ; return true ; } </s>

Emit code to perform a strlen . OPERANDS [ 0 ] is the destination . OPERANDS [ 1 ] is the string . OPERANDS [ 2 ] is the char to search . OPERANDS [ 3 ] is the alignment .


<s> static void rs6000_print_isa_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT flags ) { rs6000_print_options_internal ( file , indent , string , flags , "-m" , & rs6000_opt_masks [ 0 ] , ARRAY_SIZE ( rs6000_opt_masks ) ) ; } </s>

Helper function to print the current isa options on a line .


<s> void scalar_chain :: convert_insn_common ( rtx_insn * insn ) { for ( df_ref ref = DF_INSN_DEFS ( insn ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( bitmap_bit_p ( defs_conv , DF_REF_REGNO ( ref ) ) ) { df_link * use ; for ( use = DF_REF_CHAIN ( ref ) ; use ; use = use -> next ) if ( NONDEBUG_INSN_P ( DF_REF_INSN ( use -> ref ) ) && ( DF_REF_REG_MEM_P ( use -> ref ) || ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( use -> ref ) ) ) ) break ; if ( use ) convert_reg ( insn , DF_REF_REG ( ref ) , * defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ) ; else if ( MAY_HAVE_DEBUG_BIND_INSNS ) { auto_vec < rtx_insn * , 5 > to_reset_debug_insns ; for ( use = DF_REF_CHAIN ( ref ) ; use ; use = use -> next ) if ( DEBUG_INSN_P ( DF_REF_INSN ( use -> ref ) ) ) { rtx_insn * debug_insn = DF_REF_INSN ( use -> ref ) ; df_link * def ; for ( def = DF_REF_CHAIN ( use -> ref ) ; def ; def = def -> next ) if ( ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( def -> ref ) ) ) break ; if ( def ) to_reset_debug_insns . safe_push ( debug_insn ) ; else { * DF_REF_REAL_LOC ( use -> ref ) = * defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ; df_insn_rescan ( debug_insn ) ; } } while ( ! to_reset_debug_insns . is_empty ( ) ) { rtx_insn * debug_insn = to_reset_debug_insns . pop ( ) ; INSN_VAR_LOCATION_LOC ( debug_insn ) = gen_rtx_UNKNOWN_VAR_LOC ( ) ; df_insn_rescan_debug_internal ( debug_insn ) ; } } } for ( df_ref ref = DF_INSN_USES ( insn ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! DF_REF_REG_MEM_P ( ref ) ) if ( rtx * vreg = defs_map . get ( regno_reg_rtx [ DF_REF_REGNO ( ref ) ] ) ) { rtx note = find_reg_note ( insn , REG_DEAD , DF_REF_REG ( ref ) ) ; if ( note ) XEXP ( note , 0 ) = * vreg ; * DF_REF_REAL_LOC ( ref ) = * vreg ; } } </s>

Helper function for converting INSN to vector mode .


<s>
void
rs6000_xcoff_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
tree
decl
)
{
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
1
)
;
char
*
p
;
int
dollar_inside
=
0
;
struct
declare_alias_data
data
=
{
file
,
false
}
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
decl
)
)
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.globl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
rs6000_xcoff_visibility
(
decl
)
,
file
)
;
putc
(
'\n'
,
file
)
;
}
}
else
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.lglobl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
fputs
(
"\t.csect "
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
TARGET_32BIT
"[DS]\n"
:
"[DS],3\n"
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
fputs
(
TARGET_32BIT
"\t.long ."
:
"\t.llong ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
", TOC[tc0], 0\n"
,
file
)
;
in_section
=
;
switch_to_section
(
function_section
(
decl
)
)
;
putc
(
'.'
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
data
.
function_descriptor
=
true
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
if
(
!
DECL_IGNORED_P
(
decl
)
)
{
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
xcoffout_declare_function
(
file
,
decl
,
buffer
)
;
else
if
(
write_symbols
==
DWARF2_DEBUG
)
{
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
fprintf
(
file
,
"\t.function .%s,.%s,2,0\n"
,
name
,
name
)
;
}
}
return
;
}
</s>

This macro produces the initial definition of a function name . On the RS/6000 , we need to place an extra ' . ' in the function name and output the function descriptor . Dollar signs are converted to underscores . The csect for the function will have already been created when text_section was selected . We do have to go back to that csect , however . The third and fourth parameters to the .function pseudo-op ( 16 and 044 ) are placeholders which no longer have any use . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> void ix86_expand_rounddf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , dxa , TWO52 , tmp , half , mhalf , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , 0 , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , 0 , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , 0 , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = gen_reg_rtx ( mode ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , force_reg ( mode , operand1 ) , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing round from OPERAND1 storing into OPERAND0 . Sequence that works without relying on DImode truncation via cvttsd2siq that is only available on 64bit targets .


<s>
void
CAHPFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
unsigned
FPReg
=
getFPReg
(
)
;
unsigned
SPReg
=
getSPReg
(
)
;
DebugLoc
DL
;
determineFrameLayout
(
MF
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
adjustReg
(
MBB
,
MBBI
,
DL
,
SPReg
,
SPReg
,
StackSize
,
MachineInstr
::
FrameSetup
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
std
::
advance
(
MBBI
,
CSI
.
size
(
)
)
;
if
(
hasFP
(
MF
)
)
adjustReg
(
MBB
,
MBBI
,
DL
,
FPReg
,
SPReg
,
StackSize
,
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

CAHP
CAHP
"Shrink-wrapping not yet supported"
0


<s> HOST_WIDE_INT ix86_initial_elimination_offset ( int from , int to ) { struct ix86_frame & frame = cfun -> machine -> frame ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset - frame . frame_pointer_offset ; else { gcc_assert ( to == STACK_POINTER_REGNUM ) ; if ( from == ARG_POINTER_REGNUM ) return frame . stack_pointer_offset ; gcc_assert ( from == FRAME_POINTER_REGNUM ) ; return frame . stack_pointer_offset - frame . frame_pointer_offset ; } } </s>

Return the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
.
optForSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static bool rs6000_cannot_copy_insn_p ( rtx_insn * insn ) { return recog_memoized ( insn ) >= 0 && get_attr_cannot_copy ( insn ) ; } </s>

Return true if INSN should not be copied .


<s>
char
*
neon_output_logic_immediate
(
const
char
*
mnem
,
rtx
*
op2
,
machine_mode
mode
,
int
inverse
,
int
quad
)
{
int
width
,
is_valid
;
static
char
templ
[
40
]
;
is_valid
=
neon_immediate_valid_for_logic
(
*
op2
,
mode
,
inverse
,
op2
,
&
width
)
;
gcc_assert
(
is_valid
!=
0
)
;
if
(
quad
)
sprintf
(
templ
,
"%s.i%d\t%%q0, %%2"
,
mnem
,
width
)
;
else
sprintf
(
templ
,
"%s.i%d\t%%P0, %%2"
,
mnem
,
width
)
;
return
templ
;
}
</s>

Return a string suitable for output of Neon immediate logic operation MNEM .


<s> RegisterBankInfo :: InstructionMapping X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : return getOperandsMapping ( MI , false ) ; break ; default : return InstructionMapping { } ; } return InstructionMapping { } ; } </s>


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> bool F2003fTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_F2003f ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void ARMHazardRecognizer :: Reset ( ) { LastMI = 0 ; Stalls = 0 ; ITBlockSize = 0 ; ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> unsigned ARMRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return ( STI . useThumbBacktraces ( ) || STI . isThumb ( ) ) ? ARM :: R7 : ARM :: R11 ; else return ARM :: SP ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Partial Reduction"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s>
int
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
ValTy
,
bool
IsPairwiseForm
)
{
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s> void ARMTargetStreamer :: emitCurrentConstantPool ( ) { ConstantPools -> emitForCurrentSection ( Streamer ) ; ConstantPools -> clearCacheForCurrentSection ( Streamer ) ; } </s>

Callback used to implement the .ltorg directive .


<s> bool valid_operands_ldrd_strd ( rtx * operands , bool load ) { int nops = 2 ; HOST_WIDE_INT offsets [ 2 ] , offset , align [ 2 ] ; rtx base = NULL_RTX ; rtx cur_base , cur_offset ; int i , gap ; for ( i = 0 ; i < nops ; i ++ ) { if ( ! mem_ok_for_ldrd_strd ( operands [ nops + i ] , & cur_base , & cur_offset , & align [ i ] ) ) return false ; if ( i == 0 ) base = cur_base ; else if ( REGNO ( base ) != REGNO ( cur_base ) ) return false ; offsets [ i ] = INTVAL ( cur_offset ) ; if ( GET_CODE ( operands [ i ] ) == SUBREG ) return false ; } if ( offsets [ 0 ] > offsets [ 1 ] ) return false ; gap = offsets [ 1 ] - offsets [ 0 ] ; offset = offsets [ 0 ] ; if ( gap != GET_MODE_SIZE ( SImode ) ) return false ; if ( ! align_ok_ldrd_strd ( align [ 0 ] , offset ) ) return false ; return operands_ok_ldrd_strd ( operands [ 0 ] , operands [ 1 ] , base , offset , false , load ) ; } </s>

Return true if parallel execution of the two word-size accesses provided could be satisfied with a single LDRD/STRD instruction . Two word-size accesses are represented by the OPERANDS array , where OPERANDS [ 0,1 ] are register operands and OPERANDS [ 2,3 ] are the corresponding memory operands .


<s> int rs6000_trampoline_size ( void ) { int ret = 0 ; switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? 12 : 24 ; break ; case ABI_ELFv2 : gcc_assert ( ! TARGET_32BIT ) ; ret = 32 ; break ; case ABI_DARWIN : case ABI_V4 : ret = ( TARGET_32BIT ) ? 40 : 48 ; break ; } return ret ; } </s>

Length in units of the trampoline for entering a nested function .


<s> SDValue MipsTargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : printMemReference ( MI , OpNo , O , "H" ) ; return false ; case 'P' : printMemReference ( MI , OpNo , O , "no-rip" ) ; return false ; } } printMemReference ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void ARMTargetStreamer :: emitInst ( uint32_t Inst , char Suffix ) { } </s>

Callback used to implement the .inst directive .


<s> static bool sparc_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = XEXP ( XEXP ( x , 0 ) , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) ) return true ; return false ; } </s>

Return 1 if X contains a thread-local symbol .


<s> static bool isEqual ( const CSKYTargetStreamer :: SymbolIndex & A , const CSKYTargetStreamer :: SymbolIndex & B ) { return A . sym == B . sym && A . kind == B . kind ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> static bool ix86_legitimate_constant_p ( machine_mode , rtx x ) { if ( POINTER_BOUNDS_MODE_P ( GET_MODE ( x ) ) ) return false ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; break ; case CONST_WIDE_INT : if ( ! TARGET_64BIT && ! standard_sse_constant_p ( x ) ) return false ; break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x ) ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int mova_p ( rtx insn ) { return ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC && XINT ( SET_SRC ( PATTERN ( insn ) ) , 1 ) == UNSPEC_MOVA && GET_CODE ( XVECEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 , 0 ) ) == LABEL_REF ) ; } </s>

Return true if the specified insn is a mova insn .


Return true if sparc_output_mi_thunk would be able to output the assembler code for the thunk function specified by the arguments it is passed , and false otherwise .


<s> void PPCTargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( Subtarget . isDarwinABI ( ) ) return ; if ( ! Subtarget . isPPC64 ( ) ) return ; PPCFunctionInfo * PFI = Entry -> getParent ( ) -> getInfo < PPCFunctionInfo > ( ) ; PFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) -> getOperand ( 0 ) . getReg ( ) ; } auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 1 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static unsigned long thumb_compute_save_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) mask |= 1 << reg ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && current_function_uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( ! call_used_regs [ reg ] ) mask |= 1 << reg ; } return mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function .


<s>
SDValue
MipsTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
,
TargetLowering
::
CallLoweringInfo
&
CLI
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MipsCCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Mips
,
CLI
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
RVLocs
[
i
]
.
getLocReg
(
)
,
RVLocs
[
i
]
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
if
(
VA
.
isUpperBitsInLoc
(
)
)
{
unsigned
ValSizeInBits
=
Ins
[
i
]
.
ArgVT
.
getSizeInBits
(
)
;
unsigned
LocSizeInBits
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
unsigned
Shift
=
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExtUpper
ISD
::
SRL
:
ISD
::
SRA
;
Val
=
DAG
.
getNode
(
Shift
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getConstant
(
LocSizeInBits
ValSizeInBits
,
DL
,
VA
.
getLocVT
(
)
)
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
AExt
:
case
CCValAssign
::
AExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
case
CCValAssign
::
ZExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
case
CCValAssign
::
SExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

Mips
Mips
ISD::InputArg
16
Mips
Mips
0
"Can only return in registers!"
1
2
ISD::SRL
ISD::SRA
"Unknown loc info!"
ISD::BITCAST
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> std :: pair < unsigned , const TargetRegisterClass * > DCPU16TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & DCPU16 :: GR16RegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
static
X86Operand
CreateMem
(
unsigned
SegReg
,
MCValue
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
Res
;
Res
.
Kind
=
Memory
;
Res
.
Mem
.
SegReg
=
SegReg
;
Res
.
Mem
.
Disp
=
Disp
;
Res
.
Mem
.
BaseReg
=
BaseReg
;
Res
.
Mem
.
IndexReg
=
IndexReg
;
Res
.
Mem
.
Scale
=
Scale
;
return
Res
;
}
</s>


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LW
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
{
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
isMips1
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LDC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
MBB
.
getParent
(
)
->
getTarget
(
)
.
getRegisterInfo
(
)
;
const
unsigned
*
SubSet
=
TRI
->
getSubRegisters
(
DestReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
0
]
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
1
]
)
.
addImm
(
4
)
.
addFrameIndex
(
FI
)
;
}
}
else
llvm_unreachable
(
"Register class not handled!"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> int num_insns_constant ( rtx op , machine_mode mode ) { HOST_WIDE_INT low , high ; switch ( GET_CODE ( op ) ) { case CONST_INT : if ( ( INTVAL ( op ) >> 31 ) != 0 && ( INTVAL ( op ) >> 31 ) != - 1 && rs6000_is_valid_and_mask ( op , mode ) ) return 2 ; else return num_insns_constant_wide ( INTVAL ( op ) ) ; case CONST_WIDE_INT : { int i ; int ins = CONST_WIDE_INT_NUNITS ( op ) - 1 ; for ( i = 0 ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) ins += num_insns_constant_wide ( CONST_WIDE_INT_ELT ( op , i ) ) ; return ins ; } case CONST_DOUBLE : if ( mode == SFmode || mode == SDmode ) { long l ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL32 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } long l [ 2 ] ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL64 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; high = l [ WORDS_BIG_ENDIAN == 0 ] ; low = l [ WORDS_BIG_ENDIAN != 0 ] ; if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ; else { if ( ( high == 0 && low >= 0 ) || ( high == - 1 && low < 0 ) ) return num_insns_constant_wide ( low ) ; else if ( rs6000_is_valid_and_mask ( op , mode ) ) return 2 ; else if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } default : gcc_unreachable ( ) ; } } </s>

Return the number of instructions it takes to form a constant in as many gprs are needed for MODE .


<s> static bool sparc_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( aligned_p && size == 8 && GET_CODE ( x ) != CONST_INT ) { if ( TARGET_V9 ) { assemble_integer_with_op ( "\t.xword\t" , x ) ; return true ; } else { assemble_aligned_integer ( 4 , const0_rtx ) ; assemble_aligned_integer ( 4 , x ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The sparc version has special handling for aligned DI-mode objects .


<s> static void or1k_save_reg ( int regno , HOST_WIDE_INT offset ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit rtl to save register REGNO contents to stack memory at the given OFFSET from the current stack pointer .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MipsTargetMachine
&
Target
=
static_cast
<
MipsTargetMachine
&
>
(
const_cast
<
TargetMachine
&
>
(
MF
.
getTarget
(
)
)
)
;
JTI
=
Target
.
getJITInfo
(
)
;
II
=
Target
.
getInstrInfo
(
)
;
TD
=
Target
.
getDataLayout
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
,
Subtarget
->
isLittle
(
)
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
)
emitInstruction
(
*
I
++
,
*
MBB
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s> static bool originalTypeIsVectorFloat ( const Type * Ty ) { if ( Ty -> isVectorTy ( ) && Ty -> isFPOrFPVectorTy ( ) ) return true ; return false ; } </s>

Return true if the original type was vXfXX / vXfXX .


<s> void MipsTargetELFStreamer :: emitLabel ( MCSymbol * S ) { auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( ! isMicroMipsEnabled ( ) ) return ; getStreamer ( ) . getAssembler ( ) . registerSymbol ( * Symbol ) ; uint8_t Type = Symbol -> getType ( ) ; if ( Type != ELF :: STT_FUNC ) return ; Symbol -> setOther ( ELF :: STO_MIPS_MICROMIPS ) ; } </s>

Emit a label for Symbol into the current section .


<s>
void
xstormy16_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
switch
(
code
)
{
case
'B'
:
{
static
int
bits_set
[
8
]
=
{
0
,
1
,
1
,
2
,
1
,
2
,
2
,
3
}
;
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
GET_CODE
(
x
)
==
CONST_INT
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
if
(
bits_set
[
xx
&
7
]
<=
1
)
{
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
&=
0xff
;
else
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
&=
0xffff
;
l
=
exact_log2
(
xx
)
;
}
else
{
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xff
;
else
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xffff
;
l
=
exact_log2
(
~
xx
)
;
}
if
(
l
==
1
)
output_operand_lossage
(
"'B' operand has multiple bits set"
)
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
'C'
:
if
(
GET_CODE
(
x
)
==
SYMBOL_REF
)
assemble_name
(
file
,
XSTR
(
x
,
0
)
)
;
else
if
(
GET_CODE
(
x
)
==
LABEL_REF
)
output_asm_label
(
x
)
;
else
xstormy16_print_operand_address
(
file
,
x
)
;
return
;
case
'o'
:
case
'O'
:
{
HOST_WIDE_INT
xx
=
0
;
if
(
GET_CODE
(
x
)
==
CONST_INT
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'o' operand is not constant"
)
;
if
(
code
==
'O'
)
xx
=
xx
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
xx
1
)
;
return
;
}
case
'b'
:
{
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
GET_CODE
(
x
)
==
CONST_INT
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
l
=
7
xx
;
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
0
:
break
;
default
:
output_operand_lossage
(
"xstormy16_print_operand: unknown code"
)
;
return
;
}
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
fputs
(
reg_names
[
REGNO
(
x
)
]
,
file
)
;
break
;
case
MEM
:
xstormy16_print_operand_address
(
file
,
XEXP
(
x
,
0
)
)
;
break
;
default
:
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
output_addr_const
(
file
,
x
)
;
break
;
}
return
;
}
</s>

Print an operand to an assembler instruction .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 branch relaxation pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Should only have an r11 thunk on 64-bit targets"


<s> bool X86TTIImpl :: isFCmpOrdCheaperThanFCmpZero ( Type * Ty ) { return false ; } </s>

Return true if it is faster to check if a floating-point value is NaN ( or not-NaN ) versus a comparison against a constant FP zero value .


<s> static bool matches_type_p ( const_tree model_type , const_tree candidate ) { if ( VECTOR_TYPE_P ( model_type ) ) { if ( ! VECTOR_TYPE_P ( candidate ) || maybe_ne ( TYPE_VECTOR_SUBPARTS ( model_type ) , TYPE_VECTOR_SUBPARTS ( candidate ) ) || TYPE_MODE ( model_type ) != TYPE_MODE ( candidate ) ) return false ; model_type = TREE_TYPE ( model_type ) ; candidate = TREE_TYPE ( candidate ) ; } return ( candidate != error_mark_node && TYPE_MAIN_VARIANT ( model_type ) == TYPE_MAIN_VARIANT ( candidate ) ) ; } </s>

Return true if CANDIDATE is equivalent to MODEL_TYPE for overloading purposes .


<s> static bool loongarch_classify_address ( struct loongarch_address_info * info , rtx x , machine_mode mode , bool strict_p ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : if ( loongarch_valid_base_register_p ( XEXP ( x , 0 ) , mode , strict_p ) && loongarch_valid_index_p ( info , XEXP ( x , 1 ) , mode , strict_p ) ) { info -> reg = XEXP ( x , 0 ) ; return true ; } if ( loongarch_valid_base_register_p ( XEXP ( x , 1 ) , mode , strict_p ) && loongarch_valid_index_p ( info , XEXP ( x , 0 ) , mode , strict_p ) ) { info -> reg = XEXP ( x , 1 ) ; return true ; } info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; return ( loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) && loongarch_valid_offset_p ( info -> offset , mode ) ) ; default : return false ; } } </s>

Return true if X is a valid address for machine mode MODE . If it is , fill in INFO appropriately . STRICT_P is true if REG_OK_STRICT is in effect .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool IsLittle , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , JITInfo ( ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new ARMFrameLowering ( * this ) : ( ARMFrameLowering * ) new Thumb1FrameLowering ( * this ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM ARM ARM ARM


"Can only insert epilog into returning blocks"


<s> void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed_indeed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode ; int fp_reg_size = 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , lr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( reg , lr ) ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } if ( bitmap_bit_p ( components , 2 ) ) { rtx reg = gen_rtx_REG ( reg_mode , TOC_REGNUM ) ; rtx sp_reg = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_frame_store ( reg , sp_reg , RS6000_TOC_SAVE_SLOT ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += fp_reg_size ; } } </s>


<s> static bool mips_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( ! TARGET_SIBCALLS ) return false ; if ( mips_interrupt_type_p ( TREE_TYPE ( current_function_decl ) ) ) return false ; if ( decl && const_call_insn_operand ( XEXP ( DECL_RTL ( decl ) , 0 ) , VOIDmode ) && mips_call_may_need_jalx_p ( decl ) ) return false ; if ( decl && TARGET_CALL_SAVED_GP && ! TARGET_ABICALLS_PIC0 && ! targetm . binds_local_p ( decl ) ) return false ; return true ; } </s>

We can handle any sibcall when TARGET_SIBCALLS is true .


<s>
void
ARM64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
,
Mnemonic
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
ARM64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
ARM64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
ARM64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
ARM64InstPrinter
::
printInst
(
MI
,
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
InfosBE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24_notoc"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_pcrel34"
,
0
,
34
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
const
static
MCFixupKindInfo
InfosLE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24_notoc"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
2
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
2
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
2
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
2
,
14
,
0
}
,
{
"fixup_ppc_pcrel34"
,
0
,
34
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
(
Endian
==
support
::
little
InfosLE
:
InfosBE
)
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool isToken ( ) const override { return Kind == KindToken ; } </s>


<s> MVT :: SimpleValueType X86TargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i8 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR16_loRegClassID
:
case
AArch64
::
FPR32_with_hsub_in_FPR16_loRegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR64_loRegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
rtcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
case
AArch64
::
MatrixIndexGPR32_12_15RegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case E_V16QImode : case E_V8HImode : case E_V4SFmode : case E_V4SImode : case E_V2DFmode : case E_V2DImode : case E_V1TImode : case E_TImode : case E_TFmode : case E_KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_vsx_dform_quad ( mode ) ; break ; case E_V4HImode : case E_V2SImode : case E_V1DImode : case E_V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case E_SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s> tree function_resolver :: get_argument_type ( unsigned int i ) { tree arg = m_arglist [ i ] ; return arg == error_mark_node ? arg : TREE_TYPE ( arg ) ; } </s>

Return the type of argument I , or error_mark_node if it is n't well-formed .


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( HasSoftFloat ) HasVector = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static rtx mips_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! SMALL_OPERAND ( offset ) ) { rtx high ; if ( TARGET_MIPS16 ) { high = GEN_INT ( offset ) ; offset = 0 ; } else { high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; } high = mips_force_temporary ( temp , high ) ; reg = mips_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) ) ; } return plus_constant ( Pmode , reg , offset ) ; } </s>

Return a legitimate address for REG + OFFSET . TEMP is as for mips_force_temporary ; it is only needed when OFFSET is not a SMALL_OPERAND .


<s> bool PPCSubtarget :: useAA ( ) const { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> unsigned int ix86_regmode_natural_size ( machine_mode mode ) { if ( mode == P2HImode || mode == P2QImode ) return GET_MODE_SIZE ( mode ) / 2 ; return UNITS_PER_WORD ; } </s>

Implement REGMODE_NATURAL_SIZE ( MODE ) .


<s> void OR1KFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const OR1KInstrInfo & TII = * static_cast < const OR1KInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const OR1KRegisterInfo * TRI = static_cast < const OR1KRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool IsPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool HasRA = MFI -> adjustsStack ( ) || IsPIC ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = HasRA ? - 8 : - 4 ; int RAOffset = - 4 ; int BPOffset = FPOffset - 4 ; int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: ADDI ) , OR1K :: R1 ) . addReg ( OR1K :: R2 ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: LWZ ) , OR1K :: R2 ) . addReg ( OR1K :: R1 ) . addImm ( FPOffset ) ; } else if ( isInt < 16 > ( StackSize ) ) { if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: ADDI ) , OR1K :: R1 ) . addReg ( OR1K :: R1 ) . addImm ( StackSize ) ; } } else { unsigned ScratchReg = OR1K :: R13 ; BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: MOVHI ) , ScratchReg ) . addImm ( ( uint32_t ) StackSize >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: ORI ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( StackSize & 0xffffU ) ; BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: ADD ) , OR1K :: R1 ) . addReg ( OR1K :: R1 ) . addReg ( ScratchReg ) ; } if ( TRI -> hasBasePointer ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: LWZ ) , TRI -> getBaseRegister ( ) ) . addReg ( OR1K :: R1 ) . addImm ( BPOffset ) ; } if ( HasRA ) { BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: LWZ ) , OR1K :: R9 ) . addReg ( OR1K :: R1 ) . addImm ( RAOffset ) ; } } </s>


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) ; const MipsABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , 1 ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .