<s> void validate_condition_mode ( enum rtx_code code , machine_mode mode ) { gcc_assert ( ( GET_RTX_CLASS ( code ) == RTX_COMPARE || GET_RTX_CLASS ( code ) == RTX_COMM_COMPARE ) && GET_MODE_CLASS ( mode ) == MODE_CC ) ; gcc_assert ( ( code != GT && code != LT && code != GE && code != LE ) || mode != CCUNSmode ) ; gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCFPmode || flag_finite_math_only || ( code != LE && code != GE && code != UNEQ && code != LTGT && code != UNGT && code != UNLT ) ) ; gcc_assert ( mode != CCEQmode || code == EQ || code == NE ) ; } </s>

A validation routine : say whether CODE , a condition code , and MODE match . The other alternatives either do n't make sense or should never be generated .


<s> SDValue AArch64TargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG ) const { DEBUG ( dbgs ( ) << "AArch64TargetLowering::getAddr\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , AArch64II :: MO_PAGE ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , AArch64II :: MO_PAGEOFF | AArch64II :: MO_NC ) ; SDValue ADRP = DAG . getNode ( AArch64ISD :: ADRP , DL , Ty , Hi ) ; return DAG . getNode ( AArch64ISD :: ADDlow , DL , Ty , ADRP , Lo ) ; } </s>

Return the address accessed by this recipe .


<s> static enum reg_class rs6000_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx in ) { int regno ; if ( TARGET_ELF || ( DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT ) ) { if ( rclass != BASE_REGS && ( SYMBOL_REF_P ( in ) || GET_CODE ( in ) == HIGH || GET_CODE ( in ) == LABEL_REF || GET_CODE ( in ) == CONST ) ) return BASE_REGS ; } if ( REG_P ( in ) ) { regno = REGNO ( in ) ; if ( ! HARD_REGISTER_NUM_P ( regno ) ) { regno = true_regnum ( in ) ; if ( ! HARD_REGISTER_NUM_P ( regno ) ) regno = - 1 ; } } else if ( SUBREG_P ( in ) ) { regno = true_regnum ( in ) ; if ( ! HARD_REGISTER_NUM_P ( regno ) ) regno = - 1 ; } else regno = - 1 ; if ( TARGET_VSX && GET_MODE_SIZE ( mode ) < 16 && ! mode_supports_vmx_dform ( mode ) && ( ( ( rclass == GENERAL_REGS || rclass == BASE_REGS ) && ( regno >= 0 && ALTIVEC_REGNO_P ( regno ) ) ) || ( ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( regno >= 0 && INT_REGNO_P ( regno ) ) ) ) ) return FLOAT_REGS ; if ( rclass == GENERAL_REGS || rclass == BASE_REGS || ( regno >= 0 && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( rclass == VSX_REGS && ( regno == - 1 || VSX_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - 1 || FP_REGNO_P ( regno ) ) && ( rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS ) ) return ( mode != SDmode || lra_in_progress ) ? NO_REGS : GENERAL_REGS ; if ( ( regno == - 1 || ALTIVEC_REGNO_P ( regno ) ) && rclass == ALTIVEC_REGS ) return NO_REGS ; if ( ( rclass == CR_REGS || rclass == CR0_REGS ) && regno >= 0 && CR_REGNO_P ( regno ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the register class of a scratch register needed to copy IN into or out of a register in RCLASS in MODE . If it can be done directly , NO_REGS is returned .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NOP insertion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> mips_output_ascii ( STREAM , STRING , LEN ) { \ const char * p = STRING ; \ int size = strlen ( p ) + 1 ; \ rdata_section ( ) ; \ assemble_string ( p , size ) ; \ } </s>

Output an ASCII string , in a space-saving way . PREFIX is the string that should be written before the opening quote , such as `` \t.ascii\t '' for real string data or `` \t # `` for a comment .


<s> static void mips_emit_move_or_split ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_split_move_p ( dest , src , split_type ) ) mips_split_move ( dest , src , split_type ) ; else mips_emit_move ( dest , src ) ; } </s>

Emit a move from SRC to DEST , splitting compound moves into individual instructions . SPLIT_TYPE is the type of split to perform .


<s> bool ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static int sparc_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { bool need_memory = false ; if ( from == NO_REGS || to == NO_REGS ) return 100 ; if ( from == FPCC_REGS || to == FPCC_REGS ) need_memory = true ; else if ( ( FP_REG_CLASS_P ( from ) && general_or_i64_p ( to ) ) || ( general_or_i64_p ( from ) && FP_REG_CLASS_P ( to ) ) ) { if ( TARGET_VIS3 ) { int size = GET_MODE_SIZE ( mode ) ; if ( size == 8 || size == 4 ) { if ( ! TARGET_ARCH32 || size == 4 ) return 4 ; else return 6 ; } } need_memory = true ; } if ( need_memory ) { if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 || sparc_cpu == PROCESSOR_NIAGARA7 ) return 12 ; return 6 ; } return 2 ; } </s>


<s>
bool
AArch64TargetLowering
::
shouldFoldConstantShiftPairToMask
(
const
SDNode
*
N
,
CombineLevel
Level
)
const
{
assert
(
(
(
N
->
getOpcode
(
)
==
ISD
::
SHL
&&
N
->
getOperand
(
0
)
.
getOpcode
(
)
==
ISD
::
SRL
)
||
(
N
->
getOpcode
(
)
==
ISD
::
SRL
&&
N
->
getOperand
(
0
)
.
getOpcode
(
)
==
ISD
::
SHL
)
)
&&
"Expected shift-shift mask"
)
;
return
N
->
getOperand
(
0
)
->
hasOneUse
(
)
;
}
</s>

Return true if it is profitable to fold a pair of shifts into a mask .


<s> bool ARMSubtarget :: useFastISel ( ) const { if ( ForceFastISel ) return true ; if ( ! hasV6Ops ( ) ) return false ; return TM . Options . EnableFastISel && ( ( isTargetMachO ( ) && ! isThumb1Only ( ) ) || ( isTargetLinux ( ) && ! isThumb ( ) ) || ( isTargetNaCl ( ) && ! isThumb ( ) ) ) ; } </s>


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void ix86_expand_floorceil ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xi , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xi = gen_reg_rtx ( int_mode_for_mode ( mode ) . require ( ) ) ; expand_fix ( xi , res , 0 ) ; expand_float ( xa , xi , 0 ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , do_floor ? MINUS : PLUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) { if ( do_floor && flag_rounding_math ) tmp = ix86_expand_sse_fabs ( tmp , NULL ) ; ix86_sse_copysign_to_positive ( tmp , tmp , res , mask ) ; } emit_move_insn ( res , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


<s> static __inline float sh_media_FMAC_S ( float fg , float fh , float fq ) { return fg * fh + fq ; } </s>


<s> unsigned MMIXMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; MCFixupKind Kind = static_cast < MCFixupKind > ( MMIX :: fixup_mmix_rel_16 ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , Kind ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> int AArch64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) . getBytes ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static bool mmix_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( aligned_p ) switch ( size ) { case 1 : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = 0 ; break ; } fputs ( "\tBYTE\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'B' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 2 : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = 0 ; break ; } fputs ( "\tWYDE\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'W' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 4 : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = 0 ; break ; } fputs ( "\tTETRA\t" , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'L' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case 8 : gcc_assert ( GET_CODE ( x ) != CONST_DOUBLE ) ; assemble_integer_with_op ( "\tOCTA\t" , x ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . Use mmix_print_operand for WYDE and TETRA . Use mmix_output_octa to output 8-byte CONST_DOUBLEs .


<s> bool ARM64TargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N ) const { EVT VT = N -> getValueType ( 0 ) ; if ( N -> getOpcode ( ) == ISD :: AND && ( VT == MVT :: i32 || VT == MVT :: i64 ) && isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { uint64_t TruncMask = N -> getConstantOperandVal ( 1 ) ; if ( isMask_64 ( TruncMask ) && N -> getOperand ( 0 ) . getOpcode ( ) == ISD :: SRL && isa < ConstantSDNode > ( N -> getOperand ( 0 ) -> getOperand ( 1 ) ) ) return false ; } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
Ctx
,
IsLittleEndian
,
true
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TL = STI -> getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>


<s> static int loongarch_set_reg_reg_piece_cost ( machine_mode mode , unsigned int units ) { return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) + units - 1 ) / units ) ; } </s>

Return the cost of moving between two registers of mode MODE , assuming that the move will be in pieces of at most UNITS bytes .


<s> static rtx choose_baseaddr ( HOST_WIDE_INT cfa_offset ) { const struct machine_function * m = cfun -> machine ; rtx base_reg = NULL ; HOST_WIDE_INT base_offset = 0 ; if ( m -> use_fast_prologue_epilogue ) { if ( m -> fs . fp_valid ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( m -> fs . drap_valid ) { base_reg = crtl -> drap_reg ; base_offset = 0 - cfa_offset ; } else if ( m -> fs . sp_valid ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = 16 , tlen ; if ( m -> fs . sp_valid ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( m -> fs . drap_valid ) { toffset = 0 - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( m -> fs . fp_valid ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; len = tlen ; } } } gcc_assert ( base_reg != NULL ) ; return plus_constant ( Pmode , base_reg , base_offset ) ; } </s>

Return an RTX that points to CFA_OFFSET within the stack frame . The valid base registers are taken from CFUN- > MACHINE- > FS .


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


Remember to generate a branch island for far calls to the given function .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
.
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addOperand
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
0
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) && Subtarget -> hasNEON ( ) ) { if ( memOpAlign ( SrcAlign , DstAlign , 16 ) && Size >= 16 ) { return MVT :: v4i32 ; } else if ( memOpAlign ( SrcAlign , DstAlign , 8 ) && Size >= 8 ) { return MVT :: v2i32 ; } } if ( Size >= 4 ) { return MVT :: i32 ; } else if ( Size >= 2 ) { return MVT :: i16 ; } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool arm_can_eliminate ( const int from , const int to ) { return ( ( to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM ) ? false : ( to == STACK_POINTER_REGNUM && frame_pointer_needed ) ? false : ( to == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB ) ? false : ( to == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM ) ? false : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . All eliminations are permissible . Note that ARG_POINTER_REGNUM and HARD_FRAME_POINTER_REGNUM are in fact the same thing . If we need a frame pointer , we must eliminate FRAME_POINTER_REGNUM into HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or ARG_POINTER_REGNUM .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"getArithmeticInstrCost() called with vector type."

This is an approximation of reciprocal throughput of a math/logic op .


<s> static int mips_set_reg_reg_cost ( machine_mode mode ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_CC : return mips_set_reg_reg_piece_cost ( mode , GET_MODE_SIZE ( CCmode ) ) ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_FLOAT : if ( TARGET_HARD_FLOAT ) return mips_set_reg_reg_piece_cost ( mode , UNITS_PER_HWFPVALUE ) ; default : return mips_set_reg_reg_piece_cost ( mode , UNITS_PER_WORD ) ; } } </s>

Return the cost of moving between two registers of mode MODE .


<s> tree aarch64_general_fold_builtin ( unsigned int fcode , tree type , unsigned int n_args ATTRIBUTE_UNUSED , tree * args ) { switch ( fcode ) { BUILTIN_VDQF ( UNOP , abs , 2 , ALL ) return fold_build1 ( ABS_EXPR , type , args [ 0 ] ) ; VAR1 ( UNOP , floatv2si , 2 , ALL , v2sf ) VAR1 ( UNOP , floatv4si , 2 , ALL , v4sf ) VAR1 ( UNOP , floatv2di , 2 , ALL , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ 0 ] ) ; case AARCH64_SIMD_BUILTIN_LANE_CHECK : gcc_assert ( n_args == 3 ) ; if ( aarch64_fold_builtin_lane_check ( args [ 0 ] , args [ 1 ] , args [ 2 ] ) ) return void_node ; break ; default : break ; } return NULL_TREE ; } </s>

Try to fold a call to the built-in function with subcode FCODE . The function is passed the N_ARGS arguments in ARGS and it returns a value of type TYPE . Return the new expression on success and NULL_TREE on failure .


<s> bool hasMinSize ( ) const { return OptMinSize ; } </s>

Optimize this function for minimum size ( -Oz ) .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP , Mips :: FP , Mips :: RA } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 , Mips :: FP_64 , Mips :: RA_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegisterClass -> begin ( ) ; Reg != Mips :: AFGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegisterClass -> begin ( ) ; Reg != Mips :: CPU64RegsRegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegisterClass -> begin ( ) ; Reg != Mips :: FGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegFixed ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH ) ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool hasAndNotCompare ( SDValue V ) const override { return V . getValueType ( ) . isScalarInteger ( ) ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s>
unsigned
X86TTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
)
const
{
std
::
pair
<
unsigned
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
Ty
)
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
<
MVT
>
AVX1CostTable
[
]
=
{
{
ISD
::
MUL
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
MUL
,
MVT
::
v4i64
,
18
}
,
}
;
if
(
ST
->
hasAVX
(
)
&&
!
ST
->
hasAVX2
(
)
)
{
int
Idx
=
CostTableLookup
<
MVT
>
(
AVX1CostTable
,
array_lengthof
(
AVX1CostTable
)
,
ISD
,
LT
.
second
)
;
if
(
Idx
!=
1
)
return
LT
.
first
*
AVX1CostTable
[
Idx
]
.
Cost
;
}
static
const
CostTblEntry
<
MVT
>
CustomLowered
[
]
=
{
{
ISD
::
MUL
,
MVT
::
v2i64
,
9
}
,
{
ISD
::
MUL
,
MVT
::
v4i64
,
9
}
,
}
;
int
Idx
=
CostTableLookup
<
MVT
>
(
CustomLowered
,
array_lengthof
(
CustomLowered
)
,
ISD
,
LT
.
second
)
;
if
(
Idx
!=
1
)
return
LT
.
first
*
CustomLowered
[
Idx
]
.
Cost
;
if
(
ISD
==
ISD
::
MUL
&&
LT
.
second
==
MVT
::
v4i32
&&
ST
->
hasSSE2
(
)
&&
!
ST
->
hasSSE41
(
)
)
return
6
;
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
)
;
}
</s>


<s> static void aarch64_select_early_remat_modes ( sbitmap modes ) { for ( int i = 0 ; i < NUM_MACHINE_MODES ; ++ i ) if ( aarch64_sve_mode_p ( ( machine_mode ) i ) ) bitmap_set_bit ( modes , i ) ; } </s>


<s> bool X86TargetLowering :: ShouldShrinkFPConstant ( EVT VT ) const { return ! Subtarget . hasSSE2 ( ) || VT == MVT :: f80 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> bool prefixed_store_p ( rtx_insn * insn ) { extract_insn_cached ( insn ) ; if ( recog_data . n_operands < 2 ) return false ; rtx mem = recog_data . operand [ 0 ] ; rtx reg = recog_data . operand [ 1 ] ; if ( ! REG_P ( reg ) && ! SUBREG_P ( reg ) ) return false ; if ( ! MEM_P ( mem ) ) return false ; if ( get_attr_indexed ( insn ) == INDEXED_YES || get_attr_update ( insn ) == UPDATE_YES ) return false ; machine_mode mem_mode = GET_MODE ( mem ) ; rtx addr = XEXP ( mem , 0 ) ; enum non_prefixed_form non_prefixed = reg_to_non_prefixed ( reg , mem_mode ) ; if ( non_prefixed == NON_PREFIXED_X && is_lfs_stfs_insn ( insn ) ) return address_is_prefixed ( addr , mem_mode , NON_PREFIXED_DEFAULT ) ; else return address_is_prefixed ( addr , mem_mode , non_prefixed ) ; } </s>

Whether a store instruction is a prefixed instruction . This is called from the prefixed attribute processing .


<s> static void aarch64_emit_sve_inverted_cond ( rtx target , rtx ptrue , rtx_code code , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( ptrue ) ; rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_sve_ptrue_op ( tmp , ptrue , gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ) ; aarch64_emit_unop ( target , one_cmpl_optab , tmp ) ; } </s>

Emit the SVE equivalent of : ( set TMP ( CODE OP0 OP1 ) ) ( set TARGET ( not TMP ) ) PTRUE is an all-true predicate with the same mode as TARGET .


Return an array that contains the bitmask target flag values and their names .


<s> void or1k_expand_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , label ; machine_mode mode ; retval = operands [ 0 ] ; mem = operands [ 1 ] ; val = operands [ 2 ] ; mode = GET_MODE ( mem ) ; if ( reg_overlap_mentioned_p ( retval , val ) ) val = copy_to_reg ( val ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; emit_store_conditional ( mode , mem , val ) ; emit_unlikely_jump ( EQ , label ) ; } </s>

Expand an atomic exchange operation . Emits the RTX to perform an exchange operation . This function takes 4 RTX arguments in the OPERANDS array . The exchange operation atomically loads a value from memory ( OPERANDS [ 1 ] ) to a return value ( OPERANDS [ 0 ] ) and stores a new value ( OPERANDS [ 2 ] ) back to the memory location . Another argument ( OPERANDS [ 3 ] ) is used to indicate the memory model and is not used by OpenRISC . For OpenRISC this emits RTX which will translate to assembly using the ' l.lwa ' ( load word atomic ) and ' l.swa ' ( store word atomic ) instructions .


<s> static sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( 32 ) ; bitmap_clear ( components ) ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; if ( bitmap_bit_p ( in , LR_REGNO ) || bitmap_bit_p ( gen , LR_REGNO ) || bitmap_bit_p ( kill , LR_REGNO ) ) bitmap_set_bit ( components , 0 ) ; return components ; } </s>


<s> rtx assign_386_stack_local ( machine_mode mode , enum ix86_stack_slot n ) { struct stack_local_entry * s ; gcc_assert ( n < MAX_386_STACK_LOCALS ) ; for ( s = ix86_stack_locals ; s ; s = s -> next ) if ( s -> mode == mode && s -> n == n ) return validize_mem ( copy_rtx ( s -> rtl ) ) ; int align = 0 ; if ( mode == DImode && ! TARGET_64BIT && n == SLOT_FLOATxFDI_387 && ix86_preferred_stack_boundary < GET_MODE_ALIGNMENT ( DImode ) ) align = 32 ; s = ggc_alloc < stack_local_entry > ( ) ; s -> n = n ; s -> mode = mode ; s -> rtl = assign_stack_local ( mode , GET_MODE_SIZE ( mode ) , align ) ; s -> next = ix86_stack_locals ; ix86_stack_locals = s ; return validize_mem ( copy_rtx ( s -> rtl ) ) ; } </s>

Return a MEM corresponding to a stack slot with mode MODE . Allocate a new slot if necessary . The RTL for a function can have several slots available : N is which slot to use .


<s>
static
void
process_epilogue
(
FILE
*
out_file
,
rtx
insn
ATTRIBUTE_UNUSED
,
bool
unwind
,
bool
frame
ATTRIBUTE_UNUSED
)
{
if
(
!
last_block
)
{
if
(
unwind
)
fprintf
(
out_file
,
"\t.label_state %d\n"
,
++
cfun
->
machine
->
state_num
)
;
need_copy_state
=
true
;
}
if
(
unwind
)
fprintf
(
out_file
,
"\t.restore sp\n"
)
;
}
</s>

The function emits unwind directives for the start of an epilogue .

ia64
"\t.label_state %d\n"
"\t.restore sp\n"


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; if ( isPPC64 && ! TOC . empty ( ) ) { const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; OutStreamer . EmitTCEntry ( * S ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool LoongArchAsmParser :: processInstruction ( MCInst & Inst , SMLoc IDLoc , OperandVector & Operands , MCStreamer & Out ) { Inst . setLoc ( IDLoc ) ; Out . emitInstruction ( Inst , getSTI ( ) ) ; return false ; } </s>

Process a single instruction and collect debug info anchors .


<s> void rx_split_cbranch ( machine_mode cc_mode , enum rtx_code cmp1 , rtx c1 , rtx c2 , rtx label ) { rtx flags , x ; flags = gen_rtx_REG ( cc_mode , CC_REG ) ; x = gen_rtx_COMPARE ( cc_mode , c1 , c2 ) ; x = gen_rtx_SET ( flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( cmp1 , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label , pc_rtx ) ; x = gen_rtx_SET ( pc_rtx , x ) ; emit_jump_insn ( x ) ; } </s>

Split the conditional branch . Emit ( COMPARE C1 C2 ) into CC_REG with CC_MODE , and use that in branches based on that compare .


<s> static bool mips_strict_matching_cpu_name_p ( const char * canonical , const char * given ) { while ( * given != 0 && TOLOWER ( * given ) == TOLOWER ( * canonical ) ) given ++ , canonical ++ ; return ( ( * given == 0 && * canonical == 0 ) || ( strcmp ( canonical , "000" ) == 0 && strcasecmp ( given , "k" ) == 0 ) ) ; } </s>

Return true if GIVEN is the same as CANONICAL , or if it is CANONICAL with a final `` 000 '' replaced by `` k '' . Ignore case . Note : this function is shared between GCC and GAS .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s> virtual bool hasRawTextSupport ( ) const { return true ; } </s>

Return true if this asm streamer supports emitting unformatted text to the .s file with EmitRawText .


<s>
bool
FalkorHWPFFix
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
auto
&
ST
=
static_cast
<
const
AArch64Subtarget
&
>
(
Fn
.
getSubtarget
(
)
)
;
if
(
ST
.
getProcFamily
(
)
!=
AArch64Subtarget
::
Falkor
)
return
false
;
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
assert
(
TRI
->
trackLivenessAfterRegAlloc
(
Fn
)
&&
"Register liveness not available!"
)
;
MachineLoopInfo
&
LI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
Modified
=
false
;
for
(
MachineLoop
*
I
:
LI
)
for
(
auto
L
=
df_begin
(
I
)
,
LE
=
df_end
(
I
)
;
L
!=
LE
;
++
L
)
if
(
L
->
empty
(
)
)
runOnLoop
(
*
*
L
,
Fn
)
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
RC
->
getSize
(
)
==
32
32
:
16
;
bool
isAligned
=
(
TM
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
TM
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> void LC3FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = LC3 :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( LC3 :: SUBrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( LC3 :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( - StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> const SystemZTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: SUB64ri8 : X86 :: SUB32ri8 ) : ( Is64Bit ? X86 :: SUB64ri32 : X86 :: SUB32ri ) ) : ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: ADD64ri8 : X86 :: ADD32ri8 ) : ( Is64Bit ? X86 :: ADD64ri32 : X86 :: ADD32ri ) ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> void LoongArchAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; if ( ! lowerLoongArchMachineInstrToMCInst ( MI , TmpInst , * this ) ) EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> void ARMInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo * TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case ARM :: MOVi2pieces : { RI . emitLoadConstPool ( MBB , I , dl , DestReg , SubIdx , Orig -> getOperand ( 1 ) . getImm ( ) , ( ARMCC :: CondCodes ) Orig -> getOperand ( 2 ) . getImm ( ) , Orig -> getOperand ( 3 ) . getReg ( ) ) ; MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; return ; } } return ARMBaseInstrInfo :: reMaterialize ( MBB , I , DestReg , SubIdx , Orig , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> bool ARMRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; return ThumbRegScavenging || ! AFI -> isThumbFunction ( ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool ARMTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; bool MatchExact = ( CallerBits & ~ InlineFeatureWhitelist ) == ( CalleeBits & ~ InlineFeatureWhitelist ) ; bool MatchSubset = ( ( CallerBits & CalleeBits ) & InlineFeatureWhitelist ) == ( CalleeBits & InlineFeatureWhitelist ) ; return MatchExact && MatchSubset ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> static ds_t ia64_get_insn_checked_ds ( rtx_insn * insn ) { int code = get_insn_spec_code ( insn ) ; switch ( code ) { case UNSPEC_LDA : return BEGIN_DATA | BEGIN_CONTROL ; case UNSPEC_LDS : return BEGIN_CONTROL ; case UNSPEC_LDS_A : case UNSPEC_LDSA : return BEGIN_DATA | BEGIN_CONTROL ; default : return 0 ; } } </s>

If INSN is a speculative load return a ds with the speculation types that will be checked . Otherwise [ if INSN is a normal instruction ] return 0 .


<s> static void aarch64_emit_atomic_load_op ( enum aarch64_atomic_load_op_code code , machine_mode mode , rtx dst , rtx src , rtx mem , rtx model ) { typedef rtx ( * aarch64_atomic_load_op_fn ) ( rtx , rtx , rtx , rtx ) ; const aarch64_atomic_load_op_fn plus [ ] = { gen_aarch64_atomic_loadaddqi , gen_aarch64_atomic_loadaddhi , gen_aarch64_atomic_loadaddsi , gen_aarch64_atomic_loadadddi } ; const aarch64_atomic_load_op_fn eor [ ] = { gen_aarch64_atomic_loadeorqi , gen_aarch64_atomic_loadeorhi , gen_aarch64_atomic_loadeorsi , gen_aarch64_atomic_loadeordi } ; const aarch64_atomic_load_op_fn ior [ ] = { gen_aarch64_atomic_loadsetqi , gen_aarch64_atomic_loadsethi , gen_aarch64_atomic_loadsetsi , gen_aarch64_atomic_loadsetdi } ; const aarch64_atomic_load_op_fn bic [ ] = { gen_aarch64_atomic_loadclrqi , gen_aarch64_atomic_loadclrhi , gen_aarch64_atomic_loadclrsi , gen_aarch64_atomic_loadclrdi } ; aarch64_atomic_load_op_fn gen ; int idx = 0 ; switch ( mode ) { case E_QImode : idx = 0 ; break ; case E_HImode : idx = 1 ; break ; case E_SImode : idx = 2 ; break ; case E_DImode : idx = 3 ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case AARCH64_LDOP_PLUS : gen = plus [ idx ] ; break ; case AARCH64_LDOP_XOR : gen = eor [ idx ] ; break ; case AARCH64_LDOP_OR : gen = ior [ idx ] ; break ; case AARCH64_LDOP_BIC : gen = bic [ idx ] ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , mem , src , model ) ) ; } </s>


<s> static bool any_sibcall_could_use_r3 ( void ) { edge_iterator ei ; edge e ; if ( ! crtl -> tail_call_emit ) return false ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) if ( e -> flags & EDGE_SIBCALL ) { rtx call = BB_END ( e -> src ) ; if ( ! CALL_P ( call ) ) call = prev_nonnote_nondebug_insn ( call ) ; gcc_assert ( CALL_P ( call ) && SIBLING_CALL_P ( call ) ) ; if ( find_regno_fusage ( call , USE , 3 ) || is_indirect_tailcall_p ( call ) ) return true ; } return false ; } </s>

Return true if r3 is used by any of the tail call insns in the current function .


<s> static rtx function_arg_vector_value ( int size , enum machine_mode base_mode , int regno ) { unsigned short base_mode_size = GET_MODE_SIZE ( base_mode ) ; int nregs = size / base_mode_size , i ; rtx regs ; regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nregs ) ) ; for ( i = 0 ; i < nregs ; i ++ ) { XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( base_mode , regno ) , GEN_INT ( base_mode_size * i ) ) ; regno += base_mode_size / 4 ; } return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions for passing and returning BLKmode vectors . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the vector . REGNO is the FP hard register the vector will be passed in .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI . getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 1 , 2 ) ; } return false ; } default : bool IsIntrinOpcode ; if ( isFMA3 ( MI . getOpcode ( ) , IsIntrinOpcode ) ) return findFMA3CommutedOpIndices ( MI , IsIntrinOpcode , SrcOpIdx1 , SrcOpIdx2 ) ; return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return false ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> void ix86_expand_vector_init ( bool mmx_ok , rtx target , rtx vals ) { enum machine_mode mode = GET_MODE ( target ) ; enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONSTANT_P ( x ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( n_var == 1 ) { if ( all_const_zero && one_var == 0 && ix86_expand_vector_init_low_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target , vals ) ; } </s>

Initialize vector TARGET via VALS . Suppress the use of MMX instructions unless MMX_OK is true .


<s> int nds32_can_use_bclr_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival ) ) ; return ( TARGET_PERF_EXT && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bclr ' instruction can be used with IVAL .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( static_cast < int32_t > ( ConstExpr -> getValue ( ) ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> bool SystemZAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s>
void
pa_output_addr_vec
(
rtx
lab
,
rtx
body
)
{
int
idx
,
vlen
=
XVECLEN
(
body
,
0
)
;
if
(
!
TARGET_SOM
)
fputs
(
"\t.align 4\n"
,
asm_out_file
)
;
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
lab
)
)
;
if
(
TARGET_GAS
)
fputs
(
"\t.begin_brtab\n"
,
asm_out_file
)
;
for
(
idx
=
0
;
idx
<
vlen
;
idx
++
)
{
ASM_OUTPUT_ADDR_VEC_ELT
(
asm_out_file
,
CODE_LABEL_NUMBER
(
XEXP
(
XVECEXP
(
body
,
0
,
idx
)
,
0
)
)
)
;
}
if
(
TARGET_GAS
)
fputs
(
"\t.end_brtab\n"
,
asm_out_file
)
;
}
</s>


<s> void print ( raw_ostream & OS , const TargetMachine * TM = 0 ) const { if ( isReg ( ) ) { OS << PrintReg ( getReg ( ) ) ; } if ( isImm ( ) ) { OS << getImm ( ) ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool aarch64_sve_struct_memory_operand_p ( rtx op ) { if ( ! MEM_P ( op ) ) return false ; machine_mode mode = GET_MODE ( op ) ; struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , XEXP ( op , 0 ) , SVE_BYTE_MODE , false , ADDR_QUERY_ANY ) || addr . type != ADDRESS_REG_IMM ) return false ; poly_int64 first = addr . const_offset ; poly_int64 last = first + GET_MODE_SIZE ( mode ) - BYTES_PER_SVE_VECTOR ; return ( offset_4bit_signed_scaled_p ( SVE_BYTE_MODE , first ) && offset_4bit_signed_scaled_p ( SVE_BYTE_MODE , last ) ) ; } </s>

Return true if OP is a valid MEM operand for an SVE_STRUCT mode . We need to be able to access the individual pieces , so the range is different from LD [ 234 ] and ST [ 234 ] .


<s> static rtx sh_delegitimize_address ( rtx orig_x ) { orig_x = delegitimize_mem_from_attrs ( orig_x ) ; rtx x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == CONST ) { rtx y = XEXP ( x , 0 ) ; if ( GET_CODE ( y ) == UNSPEC ) { if ( XINT ( y , 1 ) == UNSPEC_GOT || XINT ( y , 1 ) == UNSPEC_GOTOFF || XINT ( y , 1 ) == UNSPEC_SYMOFF ) return XVECEXP ( y , 0 , 0 ) ; else if ( XINT ( y , 1 ) == UNSPEC_PCREL_SYMOFF ) { if ( GET_CODE ( XVECEXP ( y , 0 , 0 ) ) == CONST ) { rtx symplt = XEXP ( XVECEXP ( y , 0 , 0 ) , 0 ) ; if ( GET_CODE ( symplt ) == UNSPEC && ( XINT ( symplt , 1 ) == UNSPEC_PLT || XINT ( symplt , 1 ) == UNSPEC_PCREL ) ) return XVECEXP ( symplt , 0 , 0 ) ; } } } } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , Align Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == 1 ) return false ; if ( ST -> hasAVX512 ( ) && ( NumElts == 2 || ( NumElts == 4 && ! ST -> hasVLX ( ) ) ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> bool ARM64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallSet < Constant * , 8 > AlreadyChecked ; for ( auto & MBB : F ) { for ( auto & MI : MBB ) { for ( unsigned OpIdx = 0 , EndOpIdx = MI . getNumOperands ( ) ; OpIdx != EndOpIdx ; ++ OpIdx ) { Constant * Cst = dyn_cast < Constant > ( MI . getOperand ( OpIdx ) ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) ) LocalChange |= promoteConstant ( Cst ) ; } } } return LocalChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { if ( ! TargetSupported ) return false ; CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; MCSymbol * Symbol = CLI . Symbol ; if ( CC == CallingConv :: Fast ) return false ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeSupported ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; if ( ! Addr . getGlobalValue ( ) ) return false ; unsigned DestAddress ; if ( Symbol ) DestAddress = materializeExternalCallSym ( Symbol ) ; else DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function entry .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


"unknown value %qs for 'tune' target %s"

Handle the argument STR to the tune= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> void ix86_split_copysign_const ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = lowpart_subreg ( vmode , dest , mode ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is known to be a constant , and so has already been expanded into a vector constant .


<s> rtx legitimize_pe_coff_symbol ( rtx addr , bool inreg ) { if ( ! TARGET_PECOFF ) return NULL_RTX ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES ) { if ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( addr ) ) return legitimize_dllimport_symbol ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ) { rtx t = legitimize_dllimport_symbol ( XEXP ( XEXP ( addr , 0 ) , 0 ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , 0 ) , 1 ) ) ; } } if ( ix86_cmodel != CM_LARGE_PIC && ix86_cmodel != CM_MEDIUM_PIC ) return NULL_RTX ; if ( GET_CODE ( addr ) == SYMBOL_REF && ! is_imported_p ( addr ) && SYMBOL_REF_EXTERNAL_P ( addr ) && SYMBOL_REF_DECL ( addr ) ) return legitimize_pe_coff_extern_decl ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF && ! is_imported_p ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) && SYMBOL_REF_EXTERNAL_P ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) && SYMBOL_REF_DECL ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ) { rtx t = legitimize_pe_coff_extern_decl ( XEXP ( XEXP ( addr , 0 ) , 0 ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , 0 ) , 1 ) ) ; } return NULL_RTX ; } </s>

Expand SYMBOL into its corresponding dllimport or refptr symbol . WANT_REG is true if we require the result be a register .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) || ! Subtarget -> hasVFP2 ( ) ) return false ; auto & Args = F . getArgumentList ( ) ; for ( auto & Arg : Args ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : Args ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static bool mips_valid_pointer_mode ( machine_mode mode ) { return mode == SImode || ( TARGET_64BIT && mode == DImode ) ; } </s>


<s>
static
void
loongarch_print_float_branch_condition
(
FILE
*
file
,
enum
rtx_code
code
,
int
letter
)
{
switch
(
code
)
{
case
EQ
:
fputs
(
"ceqz"
,
file
)
;
break
;
case
NE
:
fputs
(
"cnez"
,
file
)
;
break
;
default
:
output_operand_lossage
(
"'%%%c' is not a valid operand prefix"
,
letter
)
;
break
;
}
}
</s>

loongarch
"ceqz"
"cnez"
"'%%%c' is not a valid operand prefix"


<s> TargetIRAnalysis AArch64TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( AArch64TTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> static bool ix86_contains_aligned_value_p ( const_tree type ) { machine_mode mode = TYPE_MODE ( type ) ; if ( mode == XFmode || mode == XCmode ) return false ; if ( TYPE_ALIGN ( type ) < 128 ) return false ; if ( AGGREGATE_TYPE_P ( type ) ) { switch ( TREE_CODE ( type ) ) { case RECORD_TYPE : case UNION_TYPE : case QUAL_UNION_TYPE : { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && ix86_contains_aligned_value_p ( TREE_TYPE ( field ) ) ) return true ; } break ; } case ARRAY_TYPE : if ( ix86_contains_aligned_value_p ( TREE_TYPE ( type ) ) ) return true ; break ; default : gcc_unreachable ( ) ; } } else return TYPE_ALIGN ( type ) >= 128 ; return false ; } </s>

Return true when TYPE should be 128bit aligned for 32bit argument passing ABI .


<s> static rtx moxie_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , MOXIE_R0 ) ; } </s>

Define how to find the value returned by a library function . We always return values in register $ r0 for moxie .


<s> void mips_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype ) { memset ( cum , 0 , sizeof ( * cum ) ) ; cum -> prototype = ( fntype && prototype_p ( fntype ) ) ; cum -> gp_reg_found = ( cum -> prototype && stdarg_p ( fntype ) ) ; } </s>

Initialize * CUM for a call to a function of type FNTYPE .


<s> int X86TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != 0 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> static rtx mips_frame_set ( rtx mem , rtx reg ) { rtx set ; set = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

Return a frame-related rtx that stores register REGNO at ( SP + OFFSET ) . The expression should only be used to store single registers .


<s> CCAssignFn * MipsTargetLowering :: CCAssignFnForCall ( ) const { return CC_Mips ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static void rs6000_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { opts -> x_rs6000_isa_flags = ptr -> x_rs6000_isa_flags ; opts -> x_rs6000_isa_flags_explicit = ptr -> x_rs6000_isa_flags_explicit ; ( void ) rs6000_option_override_internal ( false ) ; } </s>


<s> bool ix86_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class regclass ) { if ( from == to ) return false ; if ( MAYBE_FLOAT_CLASS_P ( regclass ) ) return true ; if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P ( regclass ) ) { if ( GET_MODE_SIZE ( from ) < 4 ) return true ; } return false ; } </s>

Return true if the registers in CLASS can not represent the change from modes FROM to TO .


<s> static bool is_ldr_shift_p ( HOST_WIDE_INT shift , enum rtx_code code ) { if ( code == ASHIFT ) return ( shift >= 0 && shift <= 3 ) ; else if ( code == MULT ) return ( shift == 1 || shift == 2 || shift == 4 || shift == 8 ) ; else return false ; } </s>

The instruction ldr rz , ( rx , ry < < i ) , i can be 0,1,2,3 . Check that SHIFT is valid , that the code is MULT , and that the shift is a power of 2 .


<s> static bool ix86_tieable_integer_mode_p ( machine_mode mode ) { switch ( mode ) { case HImode : case SImode : return true ; case QImode : return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case DImode : return TARGET_64BIT ; default : return false ; } } </s>

A subroutine of ix86_modes_tieable_p . Return true if MODE is a tieable integer mode .


<s> DecodeStatus SparcDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; bool isLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , isLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( STI . getFeatureBits ( ) [ Sparc :: FeatureV9 ] ) { Result = decodeInstruction ( DecoderTableSparcV932 , Instr , Insn , Address , this , STI ) ; } else { Result = decodeInstruction ( DecoderTableSparcV832 , Instr , Insn , Address , this , STI ) ; } if ( Result != MCDisassembler :: Fail ) return Result ; Result = decodeInstruction ( DecoderTableSparc32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .

Sparc Sparc Sparc::FeatureV9 Sparc Sparc Sparc 4


<s> FastISel * AArch64TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { return AArch64 :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static int ix86_save_reg ( unsigned int regno , int maybe_eh_return ) { if ( pic_offset_table_rtx && regno == REAL_PIC_OFFSET_TABLE_REGNUM && ( regs_ever_live [ REAL_PIC_OFFSET_TABLE_REGNUM ] || current_function_profile || current_function_calls_eh_return || current_function_uses_const_pool ) ) { if ( ix86_select_alt_pic_regnum ( ) != INVALID_REGNUM ) return 0 ; return 1 ; } if ( current_function_calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = 0 ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return 1 ; } } if ( cfun -> machine -> force_align_arg_pointer && regno == REGNO ( cfun -> machine -> force_align_arg_pointer ) ) return 1 ; return ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } </s>


<s> bool ARMInstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: B || Opc == ARM :: tB ) { MI -> setDesc ( get ( Opc == ARM :: B ? ARM :: Bcc : ARM :: tBcc ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ 0 ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ 1 ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> static rtx loongarch_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return loongarch_function_value_1 ( NULL_TREE , NULL_TREE , mode ) ; } </s>


<s> bool AArch64InstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const { return MF . getFunction ( ) . hasMinSize ( ) ; } </s>

Return true if the function should be outlined from by default .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86InstrInfo & TII = * TM . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * TM . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool legitimate_constant_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; break ; default : break ; } return true ; } </s>

Nonzero if the constant value X is a legitimate general operand . It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> bool ARM64InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case ARM64 :: SBFMXri : case ARM64 :: UBFMXri : if ( MI . getOperand ( 2 ) . getImm ( ) != 0 || MI . getOperand ( 3 ) . getImm ( ) != 31 ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = ARM64 :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> TargetTransformInfo LanaiTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( LanaiTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool VEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case VE :: EXTEND_STACK : { return expandExtendStackPseudo ( MI ) ; } case VE :: EXTEND_STACK_GUARD : { MI . eraseFromParent ( ) ; return true ; } case VE :: GETSTACKTOP : { return expandGetStackTopPseudo ( MI ) ; } } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( MIB ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri 0


<s> inline bool mips_lo_sum_offset_hasher :: equal ( const value_type * entry , const compare_type * value ) { return rtx_equal_p ( entry -> base , value ) ; } </s>


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) { NaClAlignAllJumpTargetsAndConstantPools ( MF ) ; } SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer . EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer . EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM ARM 1 0 ARM::tBX ARMCC::AL 0


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"Unexpected operand for inline assembly"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static bool aarch64_hard_regno_call_part_clobbered ( unsigned int abi_id , unsigned int regno , machine_mode mode ) { if ( FP_REGNUM_P ( regno ) && abi_id != ARM_PCS_SVE ) { poly_int64 per_register_size = GET_MODE_SIZE ( mode ) ; unsigned int nregs = hard_regno_nregs ( regno , mode ) ; if ( nregs > 1 ) per_register_size = exact_div ( per_register_size , nregs ) ; if ( abi_id == ARM_PCS_SIMD || abi_id == ARM_PCS_TLSDESC ) return maybe_gt ( per_register_size , 16 ) ; return maybe_gt ( per_register_size , 8 ) ; } return false ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The callee only saves the lower 64 bits of a 128-bit register . Tell the compiler the callee clobbers the top 64 bits when restoring the bottom 64 bits .


<s> static bool ix86_noce_conversion_profitable_p ( rtx_insn * seq , struct noce_if_info * if_info ) { if ( TARGET_ONE_IF_CONV_INSN && if_info -> speed_p ) { int cmov_cnt = 0 ; for ( rtx_insn * insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) { rtx set = single_set ( insn ) ; if ( ! set ) continue ; if ( GET_CODE ( SET_SRC ( set ) ) != IF_THEN_ELSE ) continue ; rtx src = SET_SRC ( set ) ; machine_mode mode = GET_MODE ( src ) ; if ( GET_MODE_CLASS ( mode ) != MODE_INT && GET_MODE_CLASS ( mode ) != MODE_FLOAT ) continue ; if ( ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) ) || ( ! REG_P ( XEXP ( src , 2 ) ) && ! MEM_P ( XEXP ( src , 2 ) ) ) ) continue ; if ( ++ cmov_cnt > 1 ) return false ; } } return default_noce_conversion_profitable_p ( seq , if_info ) ; } </s>

Return true if SEQ is a good candidate as a replacement for the if-convertible sequence described in IF_INFO .


<s> static rtx sparc_delegitimize_address ( rtx x ) { x = delegitimize_mem_from_attrs ( x ) ; if ( GET_CODE ( x ) == LO_SUM ) x = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_MOVE_PIC : case UNSPEC_TLSLE : x = XVECEXP ( x , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; break ; case UNSPEC_MOVE_GOTDATA : x = XVECEXP ( x , 0 , 2 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; break ; default : break ; } if ( GET_CODE ( x ) == MINUS && ( XEXP ( x , 0 ) == got_register_rtx || sparc_pic_register_p ( XEXP ( x , 0 ) ) ) ) { rtx y = XEXP ( x , 1 ) ; if ( GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , 1 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_MOVE_PIC_LABEL ) { x = XVECEXP ( y , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT ) ) ; } } return x ; } </s>

Delegitimize an address that was legitimized by the above function .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case E_V16QImode : case E_V8HImode : case E_V4SFmode : case E_V4SImode : case E_V2DFmode : case E_V2DImode : case E_V1TImode : case E_TImode : case E_TFmode : case E_KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_vsx_dform_quad ( mode ) ; break ; case E_V2SImode : case E_V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case E_SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s> int mems_ok_for_quad_peep ( rtx mem1 , rtx mem2 ) { rtx addr1 , addr2 ; unsigned int reg1 , reg2 ; int offset1 , offset2 ; if ( MEM_VOLATILE_P ( mem1 ) || MEM_VOLATILE_P ( mem2 ) ) return 0 ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( GET_CODE ( XEXP ( addr1 , 0 ) ) != REG ) return 0 ; else { reg1 = REGNO ( XEXP ( addr1 , 0 ) ) ; if ( GET_CODE ( XEXP ( addr1 , 1 ) ) != CONST_INT ) return 0 ; offset1 = INTVAL ( XEXP ( addr1 , 1 ) ) ; } } else if ( GET_CODE ( addr1 ) != REG ) return 0 ; else { reg1 = REGNO ( addr1 ) ; offset1 = 0 ; } if ( GET_CODE ( addr2 ) == PLUS ) { if ( GET_CODE ( XEXP ( addr2 , 0 ) ) != REG ) return 0 ; else { reg2 = REGNO ( XEXP ( addr2 , 0 ) ) ; if ( GET_CODE ( XEXP ( addr2 , 1 ) ) != CONST_INT ) return 0 ; offset2 = INTVAL ( XEXP ( addr2 , 1 ) ) ; } } else if ( GET_CODE ( addr2 ) != REG ) return 0 ; else { reg2 = REGNO ( addr2 ) ; offset2 = 0 ; } if ( reg1 != reg2 ) return 0 ; if ( offset2 != offset1 + 8 ) return 0 ; return 1 ; } </s>

Return 1 if addr1 and addr2 are suitable for lfq or stfq insn . addr1 and addr2 must be in consecutive memory locations ( addr2 == addr1 + 8 ) .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> SDValue X86TargetLowering :: getSqrtEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; UseOneConstNR = false ; return DAG . getNode ( X86ISD :: FRSQRT , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> void rs6000_emit_swrsqrt ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( src ) ; rtx x0 = gen_reg_rtx ( mode ) ; rtx y = gen_reg_rtx ( mode ) ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; REAL_VALUE_TYPE dconst3_2 ; int i ; rtx halfthree ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; real_from_integer ( & dconst3_2 , VOIDmode , 3 , SIGNED ) ; SET_REAL_EXP ( & dconst3_2 , REAL_EXP ( & dconst3_2 ) - 1 ) ; halfthree = rs6000_load_constant_and_splat ( mode , dconst3_2 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , src ) , UNSPEC_RSQRT ) ) ) ; rs6000_emit_msub ( y , src , halfthree , src ) ; for ( i = 0 ; i < passes ; i ++ ) { rtx x1 = gen_reg_rtx ( mode ) ; rtx u = gen_reg_rtx ( mode ) ; rtx v = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , x0 , x0 ) ) ; rs6000_emit_nmsub ( v , y , u , halfthree ) ; emit_insn ( gen_mul ( x1 , x0 , v ) ) ; x0 = x1 ; } emit_move_insn ( dst , x0 ) ; return ; } </s>

Newton-Raphson approximation of single/double-precision floating point rsqrt . Assumes no trapping math and finite arguments .


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const override { return NumCycles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> bool MipsMCCodeEmitter :: isMicroMips ( const MCSubtargetInfo & STI ) const { return STI . getFeatureBits ( ) & Mips :: FeatureMicroMips ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


Return a string to perform a load_multiple operation . operands [ 0 ] is the vector . operands [ 1 ] is the source address . operands [ 2 ] is the first destination register .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) . hasOptSize ( ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool isIncomingArgumentHandler ( ) const override { return true ; } </s>

Returns true if the handler is dealing with incoming arguments , i.e .


<s> void SystemZLDCleanup :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void mips_sim_wait_insn ( struct mips_sim * state , rtx insn ) { mips_sim_wait_regs ( state , insn ) ; mips_sim_wait_units ( state , insn ) ; } </s>

Advance simulation state STATE until INSN is ready to issue .


<s> TargetLowering :: ConstraintWeight AArch64TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : case 'y' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


"getBranchTarget21OpValue expects only expressions or immediates"

getBranchTarget21OpValue - Return binary encoding of the branch target operand .


<s> unsigned ARMRegisterInfo :: getRARegister ( ) const { return ARM :: LR ; } </s>

This method should return the register where the return address can be found .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s> bool arm_small_register_classes_for_mode_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return TARGET_THUMB1 ; } </s>

Implements target hook small_register_classes_for_mode_p .


<s> rtx fusion_wrap_memory_address ( rtx old_mem ) { rtx old_addr = XEXP ( old_mem , 0 ) ; rtvec v = gen_rtvec ( 1 , old_addr ) ; rtx new_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_FUSION_ADDIS ) ; return replace_equiv_address_nv ( old_mem , new_addr , false ) ; } </s>

Wrap a TOC address that can be fused to indicate that special fusion processing is needed .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; bool Promote = false ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : break ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : Promote = true ; break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && MayFoldIntoStore ( Op ) ) return false ; Promote = true ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; LLVM_FALLTHROUGH ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote = true ; } } PVT = MVT :: i32 ; return Promote ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s> void optimization_options ( int level ATTRIBUTE_UNUSED , int size ATTRIBUTE_UNUSED ) { if ( DEFAULT_ABI == ABI_DARWIN ) flag_errno_math = 0 ; set_param_value ( "max-grow-copy-bb-insns" , 16 ) ; } </s>

Change optimizations to be performed , depending on the optimization level . LEVEL is the optimization level specified ; 2 if ` -O2 ' is specified , 1 if ` -O ' is specified , and 0 if neither is specified . SIZE is nonzero if ` -Os ' is specified and zero otherwise .


<s> static int arm_address_register_rtx_p ( rtx x , int strict_p ) { int regno ; if ( GET_CODE ( x ) != REG ) return 0 ; regno = REGNO ( x ) ; if ( strict_p ) return ARM_REGNO_OK_FOR_BASE_P ( regno ) ; return ( regno <= LAST_ARM_REGNUM || regno >= FIRST_PSEUDO_REGISTER || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return nonzero if X is valid as an ARM state addressing register .


<s>
bool
CSKYInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
2
)
&&
"Invalid branch condition!"
)
;
Cond
[
0
]
.
setImm
(
getOppositeBranchOpc
(
Cond
[
0
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static unsigned ix86_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( TARGET_SILVERMONT || TARGET_INTEL ) if ( stmt_info && stmt_info -> stmt ) { tree lhs_op = gimple_get_lhs ( stmt_info -> stmt ) ; if ( lhs_op && TREE_CODE ( TREE_TYPE ( lhs_op ) ) == INTEGER_TYPE ) retval = ( retval * 17 ) / 10 ; } cost [ where ] += retval ; return retval ; } </s>


<s> unsigned AArch64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? AArch64 :: FP : AArch64 :: SP ; } </s>


<s> bool AArch64TargetLowering :: combineRepeatedFPDivisors ( unsigned NumUsers ) const { return NumUsers > 2 ; } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s>
PPC
::
Predicate
PPC
::
getSwappedPredicate
(
PPC
::
Predicate
Opcode
)
{
switch
(
Opcode
)
{
case
PPC
::
PRED_EQ
:
return
PPC
::
PRED_EQ
;
case
PPC
::
PRED_NE
:
return
PPC
::
PRED_NE
;
case
PPC
::
PRED_LT
:
return
PPC
::
PRED_GT
;
case
PPC
::
PRED_GE
:
return
PPC
::
PRED_LE
;
case
PPC
::
PRED_GT
:
return
PPC
::
PRED_LT
;
case
PPC
::
PRED_LE
:
return
PPC
::
PRED_GE
;
case
PPC
::
PRED_NU
:
return
PPC
::
PRED_NU
;
case
PPC
::
PRED_UN
:
return
PPC
::
PRED_UN
;
case
PPC
::
PRED_EQ_MINUS
:
return
PPC
::
PRED_EQ_MINUS
;
case
PPC
::
PRED_NE_MINUS
:
return
PPC
::
PRED_NE_MINUS
;
case
PPC
::
PRED_LT_MINUS
:
return
PPC
::
PRED_GT_MINUS
;
case
PPC
::
PRED_GE_MINUS
:
return
PPC
::
PRED_LE_MINUS
;
case
PPC
::
PRED_GT_MINUS
:
return
PPC
::
PRED_LT_MINUS
;
case
PPC
::
PRED_LE_MINUS
:
return
PPC
::
PRED_GE_MINUS
;
case
PPC
::
PRED_NU_MINUS
:
return
PPC
::
PRED_NU_MINUS
;
case
PPC
::
PRED_UN_MINUS
:
return
PPC
::
PRED_UN_MINUS
;
case
PPC
::
PRED_EQ_PLUS
:
return
PPC
::
PRED_EQ_PLUS
;
case
PPC
::
PRED_NE_PLUS
:
return
PPC
::
PRED_NE_PLUS
;
case
PPC
::
PRED_LT_PLUS
:
return
PPC
::
PRED_GT_PLUS
;
case
PPC
::
PRED_GE_PLUS
:
return
PPC
::
PRED_LE_PLUS
;
case
PPC
::
PRED_GT_PLUS
:
return
PPC
::
PRED_LT_PLUS
;
case
PPC
::
PRED_LE_PLUS
:
return
PPC
::
PRED_GE_PLUS
;
case
PPC
::
PRED_NU_PLUS
:
return
PPC
::
PRED_NU_PLUS
;
case
PPC
::
PRED_UN_PLUS
:
return
PPC
::
PRED_UN_PLUS
;
case
PPC
::
PRED_BIT_SET
:
case
PPC
::
PRED_BIT_UNSET
:
llvm_unreachable
(
"Invalid use of bit predicate code"
)
;
}
llvm_unreachable
(
"Unknown PPC branch opcode!"
)
;
}
</s>

This is a static version that you can use without an instruction available .


<s> SDValue Cpu0TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; Cpu0CC Cpu0CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; Cpu0CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool csky_function_value_regno_p ( const unsigned int regno ) { if ( regno == CSKY_FIRST_RET_REGNUM || ( TARGET_HARD_FLOAT_ABI && regno == CSKY_FIRST_VFP_REGNUM ) ) return true ; return false ; } </s>

Implement TARGET_FUNCTION_VALUE_REGNO_P . On C-SKY , only r0 can return results .


<s> void ARMConstantPoolValue :: print ( raw_ostream & O ) const { if ( GV ) O << GV -> getName ( ) ; else O << S ; if ( isNonLazyPointer ( ) ) O << "$non_lazy_ptr" ; else if ( isStub ( ) ) O << "$stub" ; if ( Modifier ) O << "(" << Modifier << ")" ; if ( PCAdjust != 0 ) { O << "-(LPC" << LabelId << "+" << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << "-." ; O << ")" ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> void xstormy16_expand_epilogue ( void ) { struct xstormy16_stack_layout layout ; rtx mem_pop_rtx ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_pop_rtx = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; mem_pop_rtx = gen_rtx_MEM ( HImode , mem_pop_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . locals_size ) { if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; else emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . locals_size ) ) ; } for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) emit_move_insn ( gen_rtx_REG ( HImode , regno ) , mem_pop_rtx ) ; if ( layout . stdarg_save_size ) emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . stdarg_save_size ) ) ; if ( ifun ) emit_jump_insn ( gen_return_internal_interrupt ( ) ) ; else emit_jump_insn ( gen_return_internal ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> static int scavenge_reg ( HARD_REG_SET * s ) { int r ; for ( r = FIRST_GENERAL_REG ; r <= LAST_GENERAL_REG ; r ++ ) if ( TEST_HARD_REG_BIT ( * s , r ) ) return r ; return - 1 ; } </s>

Find the number of a general purpose register in S .


<s> static bool expand_vec_perm_v4hi_5 ( struct expand_vec_perm_d * d ) { unsigned char perm2 [ 4 ] ; rtx rmask [ 4 ] ; unsigned i ; rtx t0 , t1 , mask , x ; bool ok ; if ( d -> vmode != V4HImode || d -> one_operand_p ) return false ; if ( d -> testing_p ) return true ; for ( i = 0 ; i < 4 ; ++ i ) { perm2 [ i ] = d -> perm [ i ] & 3 ; rmask [ i ] = ( d -> perm [ i ] & 4 ? const0_rtx : constm1_rtx ) ; } mask = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmask ) ) ; mask = force_reg ( V4HImode , mask ) ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; ok = expand_vselect ( t0 , d -> op0 , perm2 , 4 ) ; gcc_assert ( ok ) ; ok = expand_vselect ( t1 , d -> op1 , perm2 , 4 ) ; gcc_assert ( ok ) ; x = gen_rtx_AND ( V4HImode , mask , t0 ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_NOT ( V4HImode , mask ) ; x = gen_rtx_AND ( V4HImode , x , t1 ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; return true ; } </s>

A subroutine of ia64_expand_vec_perm_const_1 . Emit a full V4HImode constant permutation via two mux2 and a merge .


<s> static bool ia64_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '+' || code == ',' ) ; } </s>

Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P .


<s> MVT MipsTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( VT . isVector ( ) ) { if ( Subtarget . isABI_O32 ( ) ) { return MVT :: i32 ; } else { return ( VT . getSizeInBits ( ) == 32 ) ? MVT :: i32 : MVT :: i64 ; } } return MipsTargetLowering :: getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .