<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetMachO ( ) || Subtarget -> isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , & Args , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> const FeatureBitset & getFeatures ( ) const { return Features ; } </s>

Returns the vector of individual subtarget features .


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "roundl" , "sinl" , "sqrtl" , "truncl" } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < 0 ; } ; assert ( std :: is_sorted ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s> bool DLXInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Condition ) const { return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> TargetPassConfig * FPGATargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new FPGAPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
void
rs6000_target_modify_macros
(
bool
define_p
,
HOST_WIDE_INT
flags
,
HOST_WIDE_INT
bu_mask
)
{
if
(
TARGET_DEBUG_BUILTIN
||
TARGET_DEBUG_TARGET
)
fprintf
(
stderr
,
"rs6000_target_modify_macros (%s, "
HOST_WIDE_INT_PRINT_HEX
", "
HOST_WIDE_INT_PRINT_HEX
")\n"
,
(
define_p
)
"define"
:
"undef"
,
flags
,
bu_mask
)
;
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PPC"
)
;
if
(
(
flags
&
OPTION_MASK_PPC_GPOPT
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PPCSQ"
)
;
if
(
(
flags
&
OPTION_MASK_PPC_GFXOPT
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PPCGR"
)
;
if
(
(
flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PPC64"
)
;
if
(
(
flags
&
OPTION_MASK_MFCRF
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR4"
)
;
if
(
(
flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR5"
)
;
if
(
(
flags
&
OPTION_MASK_FPRND
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR5X"
)
;
if
(
(
flags
&
OPTION_MASK_CMPB
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR6"
)
;
if
(
(
flags
&
OPTION_MASK_MFPGPR
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR6X"
)
;
if
(
(
flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR7"
)
;
if
(
(
flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR8"
)
;
if
(
(
flags
&
OPTION_MASK_SOFT_FLOAT
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_SOFT_FLOAT"
)
;
if
(
(
flags
&
OPTION_MASK_RECIP_PRECISION
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__RECIP_PRECISION__"
)
;
if
(
(
flags
&
OPTION_MASK_ALTIVEC
)
!=
0
)
{
const
char
*
vec_str
=
(
define_p
)
"__VEC__=10206"
:
"__VEC__"
;
rs6000_define_or_undefine_macro
(
define_p
,
"__ALTIVEC__"
)
;
rs6000_define_or_undefine_macro
(
define_p
,
vec_str
)
;
if
(
!
flag_iso
)
rs6000_define_or_undefine_macro
(
define_p
,
"__APPLE_ALTIVEC__"
)
;
}
if
(
(
flags
&
OPTION_MASK_VSX
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__VSX__"
)
;
if
(
(
flags
&
OPTION_MASK_HTM
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__HTM__"
)
;
if
(
(
flags
&
OPTION_MASK_P8_VECTOR
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__POWER8_VECTOR__"
)
;
if
(
(
flags
&
OPTION_MASK_QUAD_MEMORY
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__QUAD_MEMORY__"
)
;
if
(
(
flags
&
OPTION_MASK_QUAD_MEMORY_ATOMIC
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__QUAD_MEMORY_ATOMIC__"
)
;
if
(
(
flags
&
OPTION_MASK_CRYPTO
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__CRYPTO__"
)
;
if
(
(
flags
&
OPTION_MASK_UPPER_REGS_DF
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__UPPER_REGS_DF__"
)
;
if
(
(
flags
&
OPTION_MASK_UPPER_REGS_SF
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__UPPER_REGS_SF__"
)
;
if
(
(
bu_mask
&
RS6000_BTM_SPE
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__SPE__"
)
;
if
(
(
bu_mask
&
RS6000_BTM_PAIRED
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__PAIRED__"
)
;
if
(
(
bu_mask
&
RS6000_BTM_CELL
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__PPU__"
)
;
}
</s>

Define or undefine macros based on the current target . If the user does # pragma GCC target , we need to adjust the macros dynamically .


<s> const char * OR1KTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case OR1KISD :: ADJDYNALLOC : return "OR1KISD::ADJDYNALLOC" ; case OR1KISD :: RET_FLAG : return "OR1KISD::RET_FLAG" ; case OR1KISD :: CALL : return "OR1KISD::CALL" ; case OR1KISD :: SELECT_CC : return "OR1KISD::SELECT_CC" ; case OR1KISD :: SET_FLAG : return "OR1KISD::SET_FLAG" ; case OR1KISD :: BR_CC : return "OR1KISD::BR_CC" ; case OR1KISD :: Wrapper : return "OR1KISD::Wrapper" ; case OR1KISD :: FF1 : return "OR1KISD::FF1" ; case OR1KISD :: FL1 : return "OR1KISD::FL1" ; case OR1KISD :: HI : return "OR1KISD::HI" ; case OR1KISD :: LO : return "OR1KISD::LO" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const PPCMCExpr * PPCMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , bool isDarwin , MCContext & Ctx ) { return new ( Ctx ) PPCMCExpr ( Kind , Expr , isDarwin ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> static unsigned HOST_WIDE_INT aarch64_replicate_bitmask_imm ( unsigned HOST_WIDE_INT val , machine_mode mode ) { unsigned int size = GET_MODE_UNIT_PRECISION ( mode ) ; while ( size < 64 ) { val &= ( HOST_WIDE_INT_1U << size ) - 1 ; val |= val << size ; size *= 2 ; } return val ; } </s>

VAL is a value with the inner mode of MODE . Replicate it to fill a 64-bit ( DImode ) integer .


<s> tree function_builder :: get_attributes ( const function_instance & instance ) { tree attrs = NULL_TREE ; if ( ! instance . modifies_global_state_p ( ) ) { if ( instance . reads_global_state_p ( ) ) attrs = add_attribute ( "pure" , attrs ) ; else attrs = add_attribute ( "const" , attrs ) ; } if ( ! flag_non_call_exceptions || ! instance . could_trap_p ( ) ) attrs = add_attribute ( "nothrow" , attrs ) ; return add_attribute ( "leaf" , attrs ) ; } </s>

Return the appropriate function attributes for INSTANCE .


<s> static reg_class_t mips_canonicalize_move_class ( reg_class_t rclass ) { if ( reg_class_subset_p ( rclass , ACC_REGS ) ) rclass = ACC_REGS ; if ( TARGET_MIPS16 && reg_class_subset_p ( rclass , M16_REGS ) ) rclass = M16_REGS ; else if ( reg_class_subset_p ( rclass , GENERAL_REGS ) ) rclass = GENERAL_REGS ; return rclass ; } </s>

RCLASS is a class involved in a REGISTER_MOVE_COST calculation . Return a `` canonical '' class to represent it in later calculations .


<s>
unsigned
ARMBaseInstrInfo
::
getPartialRegUpdateClearance
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
!
SwiftPartialUpdateClearance
||
!
(
Subtarget
.
isSwift
(
)
||
Subtarget
.
isCortexA15
(
)
)
)
return
0
;
assert
(
TRI
&&
"Need TRI instance"
)
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
if
(
MO
.
readsReg
(
)
)
return
0
;
unsigned
Reg
=
MO
.
getReg
(
)
;
int
UseOp
=
1
;
switch
(
MI
->
getOpcode
(
)
)
{
case
ARM
::
VLDRS
:
case
ARM
::
FCONSTS
:
case
ARM
::
VMOVSR
:
case
ARM
::
VMOVv8i8
:
case
ARM
::
VMOVv4i16
:
case
ARM
::
VMOVv2i32
:
case
ARM
::
VMOVv2f32
:
case
ARM
::
VMOVv1i64
:
UseOp
=
MI
->
findRegisterUseOperandIdx
(
Reg
,
false
,
TRI
)
;
break
;
case
ARM
::
VLD1LNd32
:
UseOp
=
3
;
break
;
default
:
return
0
;
}
if
(
UseOp
!=
1
&&
MI
->
getOperand
(
UseOp
)
.
readsReg
(
)
)
return
0
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
Reg
)
)
{
if
(
!
MO
.
getSubReg
(
)
||
MI
->
readsVirtualRegister
(
Reg
)
)
return
0
;
}
else
if
(
ARM
::
SPRRegClass
.
contains
(
Reg
)
)
{
unsigned
DReg
=
TRI
->
getMatchingSuperReg
(
Reg
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DReg
||
!
MI
->
definesRegister
(
DReg
,
TRI
)
)
return
0
;
}
return
SwiftPartialUpdateClearance
;
}
</s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
.
startswith
(
".dwarf_addr_size"
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
!=
"4"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
".dwarf_addr_size must be 4"
)
;
Parser
.
Lex
(
)
;
return
false
;
}
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool sh_lshrsi_clobbers_t_reg_p ( rtx shift_amount ) { gcc_assert ( CONST_INT_P ( shift_amount ) ) ; const int shift_amount_i = INTVAL ( shift_amount ) & 31 ; if ( shift_amount_i == 31 ) return true ; return ( ashl_lshr_seq [ shift_amount_i ] . clobbers_t & LSHR_CLOBBERS_T ) != 0 ; } </s>

Return true if a logical right shift consisting of 1/2/8/16 shift instructions will clobber the T bit .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = Subtarget ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex , unsigned & MemBytes ) const { if ( isFrameStoreOpcode ( MI . getOpcode ( ) , MemBytes ) ) if ( MI . getOperand ( X86 :: AddrNumOperands ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 0 , FrameIndex ) ) return MI . getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


"Arch64 does not support GOT PC rel with extra offset"

Get the target specific PC relative GOT entry relocation .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( NoFusing ) return nullptr ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) && hasPartialRegUpdate ( MI -> getOpcode ( ) ) ) return nullptr ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned Size = MFI -> getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI -> getObjectAlignment ( FrameIndex ) ; if ( ! RI . needsStackRealignment ( MF ) ) Alignment = std :: min ( Alignment , Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ) ; if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; unsigned RCSize = 0 ; switch ( MI -> getOpcode ( ) ) { default : return nullptr ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; RCSize = 1 ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri8 ; RCSize = 2 ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri8 ; RCSize = 4 ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri8 ; RCSize = 8 ; break ; } if ( Size < RCSize ) return nullptr ; MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return nullptr ; SmallVector < MachineOperand , 4 > MOs ; MOs . push_back ( MachineOperand :: CreateFI ( FrameIndex ) ) ; return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MOs , Size , Alignment , true ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
bool
ARMAsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
assert
(
MMI
)
;
DW
=
getAnalysisIfAvailable
<
DwarfWriter
>
(
)
;
assert
(
DW
&&
"Dwarf Writer is not available"
)
;
DW
->
BeginModule
(
&
M
,
MMI
,
O
,
this
,
TAI
)
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
Mang
->
setUseQuotes
(
true
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> unsigned aarch64_dbx_register_number ( unsigned regno ) { if ( GP_REGNUM_P ( regno ) ) return AARCH64_DWARF_R0 + regno - R0_REGNUM ; else if ( regno == SP_REGNUM ) return AARCH64_DWARF_SP ; else if ( FP_REGNUM_P ( regno ) ) return AARCH64_DWARF_V0 + regno - V0_REGNUM ; else if ( PR_REGNUM_P ( regno ) ) return AARCH64_DWARF_P0 + regno - P0_REGNUM ; else if ( regno == VG_REGNUM ) return AARCH64_DWARF_VG ; return DWARF_FRAME_REGISTERS ; } </s>

Provide a mapping from gcc register numbers to dwarf register numbers .


<s> static rtx vax_function_arg ( cumulative_args_t , const function_arg_info & ) { return NULL_RTX ; } </s>


<s> static unsigned long arm_isr_value ( tree argument ) { const isr_attribute_arg * ptr ; const char * arg ; if ( ! arm_arch_notm ) return ARM_FT_NORMAL | ARM_FT_STACKALIGN ; if ( argument == NULL_TREE ) return ARM_FT_ISR ; if ( TREE_VALUE ( argument ) == NULL_TREE || TREE_CODE ( TREE_VALUE ( argument ) ) != STRING_CST ) return ARM_FT_UNKNOWN ; arg = TREE_STRING_POINTER ( TREE_VALUE ( argument ) ) ; for ( ptr = isr_attribute_args ; ptr -> arg != NULL ; ptr ++ ) if ( streq ( arg , ptr -> arg ) ) return ptr -> return_value ; return ARM_FT_UNKNOWN ; } </s>

Returns the ( interrupt ) function type of the current function , or ARM_FT_UNKNOWN if the type can not be determined .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Fast Tile Register Preconfigure"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type = ARM_FT_UNKNOWN ; machine -> static_chain_stack_bytes = - 1 ; return machine ; } </s>

Functions to save and restore machine-specific function data .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createLEGELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool insn_dependent_p ( rtx x , rtx y ) { rtx tmp ; if ( ! INSN_P ( x ) || ! INSN_P ( y ) ) return 0 ; tmp = PATTERN ( y ) ; note_stores ( PATTERN ( x ) , insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX ) return true ; tmp = PATTERN ( x ) ; note_stores ( PATTERN ( y ) , insn_dependent_p_1 , & tmp ) ; return ( tmp == NULL_RTX ) ; } </s>

Return true if anything in insn X is ( anti , output , true ) dependent on anything in insn Y .


"Only register-returns should be created by PCS"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void AArch64PassConfig :: addPreSched2 ( ) { addPass ( createAArch64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorHWPFFixPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void mips_split_call ( rtx insn , rtx call_pattern ) { emit_call_insn ( call_pattern ) ; if ( ! find_reg_note ( insn , REG_NORETURN , 0 ) ) mips_restore_gp_from_cprestore_slot ( gen_rtx_REG ( Pmode , POST_CALL_TMP_REG ) ) ; } </s>

Split call instruction INSN into a $ gp-clobbering call and ( where necessary ) an instruction to restore $ gp from its save slot . CALL_PATTERN is the pattern of the new call .


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size , const bool int_registers_saved ) { const HOST_WIDE_INT probe_interval = get_probe_interval ( ) ; if ( size <= 6 * probe_interval ) { HOST_WIDE_INT i ; for ( i = probe_interval ; i < size ; i += probe_interval ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { gcc_assert ( int_registers_saved ) ; HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , probe_interval ) ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( gen_probe_stack_range ( Pmode , sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr , size , true ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static bool or1k_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( arg . aggregate_type_p ( ) ) return true ; HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return size < 0 || size > 8 ; } </s>

Worker for TARGET_PASS_BY_REFERENCE . Returns true if an argument of TYPE in MODE should be passed by reference as required by the OpenRISC ABI . On OpenRISC structures , unions and arguments larger than 64-bits are passed by reference .


<s> void build ( function_builder & b , const function_group_info & group ) const OVERRIDE { b . add_overloaded_functions ( group , MODE_none ) ; build_all ( b , "v0,vu0" , group , MODE_none ) ; } </s>

Build new chain starting from insn INSN_UID recursively adding all dependent uses and definitions . Return true if OK , false if the chain discovery was aborted .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool MINA32AsmParser :: ParseDirective ( AsmToken DirectiveID ) { MCAsmParser & Parser = getParser ( ) ; if ( DirectiveID . getString ( ) == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".end" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".set" ) { return parseDirectiveSet ( ) ; } if ( DirectiveID . getString ( ) == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"it would convert a WLS from forward to a "

Checks if loop has a backwards branching WLS , and if possible , fixes it .


<s>
void
SystemZRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
const
TargetFrameInfo
&
TFI
=
*
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SystemZMachineFunctionInfo
*
SystemZMFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
(
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
StackSize
-=
SystemZMFI
->
getCalleeSavedFrameSize
(
)
;
uint64_t
NumBytes
=
StackSize
TFI
.
getOffsetOfLocalArea
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mr
||
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mrm
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
StackSize
||
MFI
->
hasCalls
(
)
)
{
assert
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
SystemZ
::
R15D
)
&&
"Invalid stack frame calculation!"
)
;
emitSPUpdate
(
MBB
,
MBBI
,
(
int64_t
)
NumBytes
,
TII
)
;
}
if
(
hasFP
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
SystemZ
::
MOV64rr
)
,
SystemZ
::
R11D
)
.
addReg
(
SystemZ
::
R15D
)
;
for
(
MachineFunction
::
iterator
I
=
llvm
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
SystemZ
::
R11D
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Can only insert epilog into returning blocks"


<s>
const
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , TII . get ( ADDriOpc ) , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID ) const { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: MatrixIndexGPR32_12_15RegClassID : return 4 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : case AArch64 :: FPR64_loRegClassID : case AArch64 :: FPR16_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static bool use_skip_p ( rtx_insn * insn ) { rtx_insn * jump_insn = next_active_insn ( JUMP_LABEL_AS_INSN ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) break ; if ( get_attr_length ( insn ) == 4 && jump_insn == next_active_insn ( insn ) ) return TRUE ; if ( get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a forward jump insn , can use nullification to skip the following instruction . This avoids an extra cycle due to a mis-predicted branch when we fall through .


<s>
Value
*
AArch64TargetLowering
::
emitLoadLinked
(
IRBuilderBase
&
Builder
,
Type
*
ValueTy
,
Value
*
Addr
,
AtomicOrdering
Ord
)
const
{
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
bool
IsAcquire
=
isAcquireOrStronger
(
Ord
)
;
if
(
ValueTy
->
getPrimitiveSizeInBits
(
)
==
128
)
{
Intrinsic
::
ID
Int
=
IsAcquire
Intrinsic
::
aarch64_ldaxp
:
Intrinsic
::
aarch64_ldxp
;
Function
*
Ldxr
=
Intrinsic
::
getDeclaration
(
M
,
Int
)
;
Addr
=
Builder
.
CreateBitCast
(
Addr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
Ldxr
,
Addr
,
"lohi"
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValueTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValueTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValueTy
,
64
)
)
,
"val64"
)
;
}
const
DataLayout
&
DL
=
M
->
getDataLayout
(
)
;
IntegerType
*
IntEltTy
=
Builder
.
getIntNTy
(
DL
.
getTypeSizeInBits
(
ValueTy
)
)
;
if
(
ValueTy
->
isPointerTy
(
)
)
Addr
=
Builder
.
CreatePointerCast
(
Addr
,
IntEltTy
->
getPointerTo
(
Addr
->
getType
(
)
->
getPointerAddressSpace
(
)
)
)
;
Type
*
Tys
[
]
=
{
Addr
->
getType
(
)
}
;
Intrinsic
::
ID
Int
=
IsAcquire
Intrinsic
::
aarch64_ldaxr
:
Intrinsic
::
aarch64_ldxr
;
Function
*
Ldxr
=
Intrinsic
::
getDeclaration
(
M
,
Int
,
Tys
)
;
Value
*
Trunc
=
Builder
.
CreateTrunc
(
Builder
.
CreateCall
(
Ldxr
,
Addr
)
,
IntEltTy
)
;
assert
(
!
DL
.
isFatPointer
(
ValueTy
)
&&
"Should not be handled here!"
)
;
if
(
ValueTy
->
isPointerTy
(
)
)
return
Builder
.
CreateIntToPtr
(
Trunc
,
ValueTy
)
;
return
Builder
.
CreateBitCast
(
Trunc
,
ValueTy
)
;
}
</s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11L ) ; Reserved . set ( SystemZ :: R11H ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15L ) ; Reserved . set ( SystemZ :: R15H ) ; Reserved . set ( SystemZ :: R14Q ) ; Reserved . set ( SystemZ :: A0 ) ; Reserved . set ( SystemZ :: A1 ) ; Reserved . set ( SystemZ :: FPC ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


<s>
void
dump
(
)
{
errs
(
)
<<
"DCPU16ISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
0
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

Dcpu16
"DCPU16ISelAddressMode "
0
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s> void DLXFrameLowering :: emitEpilogue ( MachineFunction & , MachineBasicBlock & MBB ) const { } </s>


<s> static void mips_sim_wait_reg ( struct mips_sim * state , rtx insn , rtx reg ) { unsigned int i ; for ( i = 0 ; i < HARD_REGNO_NREGS ( REGNO ( reg ) , GET_MODE ( reg ) ) ; i ++ ) if ( state -> last_set [ REGNO ( reg ) + i ] . insn != 0 ) { unsigned int t ; t = state -> last_set [ REGNO ( reg ) + i ] . time ; t += insn_latency ( state -> last_set [ REGNO ( reg ) + i ] . insn , insn ) ; while ( state -> time < t ) mips_sim_next_cycle ( state ) ; } } </s>

Advance simulation state STATE until instruction INSN can read register REG .


<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , RegKind Kind , unsigned ElementWidth , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . ElementWidth = ElementWidth ; Op -> Reg . Kind = Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
const
TargetRegisterClass
*
TRC
=
Subtarget
->
getRegisterInfo
(
)
->
getPointerRegClass
(
*
MF
)
;
SDLoc
DL
(
Base
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
DL
,
MVT
::
i32
)
;
if
(
Base
.
getOpcode
(
)
!=
ISD
::
TargetFrameIndex
&&
Base
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Base
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Base
.
getValueType
(
)
,
Base
,
RC
)
,
0
)
;
}
if
(
Index
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Index
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Index
.
getValueType
(
)
,
Index
,
RC
)
,
0
)
;
}
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static bool find_mem_ref ( rtx pat , rtx * mem_ref ) { const char * fmt ; int i , j ; if ( tie_operand ( pat , VOIDmode ) ) return false ; if ( GET_CODE ( pat ) == MEM ) { * mem_ref = pat ; return true ; } fmt = GET_RTX_FORMAT ( GET_CODE ( pat ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( pat ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( find_mem_ref ( XEXP ( pat , i ) , mem_ref ) ) return true ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( pat , i ) - 1 ; j >= 0 ; j -- ) { if ( find_mem_ref ( XVECEXP ( pat , i , j ) , mem_ref ) ) return true ; } } return false ; } </s>

Determine if PAT refers to memory . If so , set MEM_REF to the MEM rtx and return true .


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

SystemZ SystemZ SystemZ "generic" "generic"


<s> static int rid_int128 ( void ) { int i ; for ( i = 0 ; i < NUM_INT_N_ENTS ; i ++ ) if ( int_n_enabled_p [ i ] && int_n_data [ i ] . bitsize == 128 ) return RID_INT_N_0 + i ; return RID_MAX + 1 ; } </s>

Helper function to find out which RID_INT_N_ * code is the one for __int128 , if any . Returns RID_MAX+1 if none apply , which is safe ( for our purposes , since we always expect to have __int128 ) to compare against .


<s> static rtx ix86_validate_address_register ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; if ( mode != SImode && mode != DImode ) return NULL_RTX ; if ( REG_P ( op ) ) return op ; else if ( GET_CODE ( op ) == SUBREG ) { rtx reg = SUBREG_REG ( op ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; mode = GET_MODE ( reg ) ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return NULL_RTX ; if ( register_no_elim_operand ( reg , mode ) ) return reg ; } return NULL_RTX ; } </s>

Determine if op is suitable RTX for an address register . Return naked register if a register or a register subreg is found , otherwise return NULL_RTX .


<s> static rtx ix86_function_value ( const_tree valtype , const_tree fntype_or_decl , bool ) { machine_mode mode , orig_mode ; orig_mode = TYPE_MODE ( valtype ) ; mode = type_natural_mode ( valtype , NULL , true ) ; return ix86_function_value_1 ( valtype , fntype_or_decl , orig_mode , mode ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 .


<s> void X86InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: TargetCostInfo & TCI ) const { if ( TCI . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( X86 :: RETQ ) ) ; MBB . insert ( MBB . end ( ) , retq ) ; } </s>

Insert a custom frame for outlined functions .


<s> bool VETargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = getReturnCC ( CallConv ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool MipsTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( ! Subtarget . hasMips64 ( ) ) PM . add ( createMipsEmitGPRestorePass ( * this ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - 1 ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
static
tree
lookup_sve_type_attribute
(
const_tree
type
)
{
if
(
type
==
error_mark_node
)
return
NULL_TREE
;
return
lookup_attribute
(
"SVE type"
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

If TYPE is an ABI-defined SVE type , return its attribute descriptor , otherwise return null .


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_vec_duplicate ( mode , x ) ; } </s>

If VALS is a vector constant that can be loaded into a register using DUP , generate instructions to do so and return an RTX to assign to the register . Otherwise return NULL_RTX .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; unsigned Flags = GV -> hasDLLImportStorageClass ( ) ? AArch64II :: MO_DLLIMPORT : AArch64II :: MO_NO_FLAG ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT | Flags ; if ( ( useSmallAddressing ( ) || TM . getCodeModel ( ) == CodeModel :: Tiny ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT | Flags ; return Flags ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; } addPass ( createX86WinAllocaExpander ( ) ) ; } </s>


<s>
void
TeeRISCAsmPrinter
::
emitFrameDirective
(
)
{
if
(
!
OutStreamer
.
hasRawTextSupport
(
)
)
return
;
const
TargetRegisterInfo
&
RI
=
*
TM
.
getRegisterInfo
(
)
;
unsigned
stkReg
=
RI
.
getFrameRegister
(
*
MF
)
;
unsigned
retReg
=
RI
.
getRARegister
(
)
;
unsigned
stkSze
=
MF
->
getFrameInfo
(
)
->
getStackSize
(
)
;
OutStreamer
.
EmitRawText
(
"\t.frame\t"
+
Twine
(
TeeRISCInstPrinter
::
getRegisterName
(
stkReg
)
)
+
", "
+
Twine
(
stkSze
)
+
", "
+
Twine
(
TeeRISCInstPrinter
::
getRegisterName
(
retReg
)
)
)
;
}
</s>

TeeRISC
TeeRISC
"\t.frame\t"
TeeRISC
", "
", "
TeeRISC


<s> void setKind ( BaseKind K ) { Kind = K ; } </s>


<s> void Cpu0PassConfig :: addPreEmitPass ( ) { Cpu0TargetMachine & TM = getCpu0TargetMachine ( ) ; addPass ( createCpu0LongBranchPass ( TM ) ) ; return ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned DCPU16RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? DCPU16 :: J : DCPU16 :: SP ; } </s>


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64 : case ARM :: VST1d64TPseudo : case ARM :: VST1d64QPseudo : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static rtx pru_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , FIRST_RETVAL_REGNUM ) ; } </s>


<s> bool Thumb1FrameInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool MipsPreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; MipsPreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> static inline bool address_is_prefixed ( rtx addr , machine_mode mode , enum non_prefixed_form non_prefixed ) { enum insn_form iform = address_to_insn_form ( addr , mode , non_prefixed ) ; return ( iform == INSN_FORM_PREFIXED_NUMERIC || iform == INSN_FORM_PCREL_LOCAL ) ; } </s>

Return true if the address can be used for a prefixed load , store , or add immediate instructions that can not be used with a non-prefixed instruction . For example , using a numeric offset that is not valid for the non-prefixed instruction or a PC-relative reference to a local symbol would return true , but an address with an offset of 64 would not return true . References to external PC-relative symbols are n't allowed , because GCC has to load the address into a register and then issue a separate load or store .


<s> static void do_load_for_compare ( rtx reg , rtx mem , machine_mode mode ) { switch ( GET_MODE ( reg ) ) { case E_DImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case E_SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case E_DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_SImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case E_SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case E_DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Figure out the correct instructions to generate to load data for block compare . MODE is used for the read from memory , and data is zero extended if REG is wider than MODE . If LE code is being generated , bswap loads are used . REG is the destination register to move the data into . MEM is the memory block being read . MODE is the mode of memory to use for the read .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; } </s>


<s> TargetPassConfig * CAHPTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static unsigned estimateStackSize ( MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; int Offset = 0 ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - MFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isDeadObjectIndex ( i ) ) continue ; Offset += MFI -> getObjectSize ( i ) ; unsigned Align = MFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; MaxAlign = std :: max ( Align , MaxAlign ) ; } if ( MFI -> adjustsStack ( ) && TFI -> hasReservedCallFrame ( MF ) ) Offset += MFI -> getMaxCallFrameSize ( ) ; unsigned StackAlign ; if ( MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) || ( RegInfo -> needsStackRealignment ( MF ) && MFI -> getObjectIndexEnd ( ) != 0 ) ) StackAlign = TFI -> getStackAlignment ( ) ; else StackAlign = TFI -> getTransientStackAlignment ( ) ; StackAlign = std :: max ( StackAlign , MaxAlign ) ; unsigned AlignMask = StackAlign - 1 ; Offset = ( Offset + AlignMask ) & ~ uint64_t ( AlignMask ) ; return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s>
bool
LC2200AsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
if
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
)
{
Out
.
EmitInstruction
(
Inst
,
this
->
STI
)
;
return
false
;
}
else
{
return
Error
(
IDLoc
,
"Error Parsing Instruction"
)
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> unsigned CSKYAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { CSKYOperand & Op = static_cast < CSKYOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; if ( CSKYMCRegisterClasses [ CSKY :: FPR32RegClassID ] . contains ( Reg ) ) { if ( Kind == MCK_FPR64 || Kind == MCK_sFPR64 ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; if ( Kind == MCK_sFPR64 && ( Op . Reg . RegNum < CSKY :: F0_64 || Op . Reg . RegNum > CSKY :: F15_64 ) ) return Match_InvalidRegOutOfRange ; if ( Kind == MCK_FPR64 && ( Op . Reg . RegNum < CSKY :: F0_64 || Op . Reg . RegNum > CSKY :: F31_64 ) ) return Match_InvalidRegOutOfRange ; return Match_Success ; } } if ( CSKYMCRegisterClasses [ CSKY :: GPRRegClassID ] . contains ( Reg ) ) { if ( Kind == MCK_GPRPair ) { Op . Reg . RegNum = MRI -> getEncodingValue ( Reg ) + CSKY :: R0_R1 ; return Match_Success ; } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> static unsigned int mips_machine_reorg2 ( void ) { mips_reorg_process_insns ( ) ; if ( ! TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN ) vr4130_align_insns ( ) ; if ( mips_expand_ghost_gp_insns ( ) ) mips_reorg_process_insns ( ) ; mips16_split_long_branches ( ) ; return 0 ; } </s>

We use a machine specific pass to do a second machine dependent reorg pass after delay branch scheduling .


<s> bool targetSchedulesPostRAScheduling ( ) const override { return true ; } </s>

True if subtarget inserts the final scheduling pass on its own .


<s> static void push ( struct unw_state_record * sr ) { struct unw_reg_state * rs = alloc_reg_state ( ) ; memcpy ( rs , & sr -> curr , sizeof ( * rs ) ) ; sr -> curr . next = rs ; } </s>

Output RTL to push register RN onto the stack .


<s> bool X86ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const X86Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FL = STI -> getFrameLowering ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case V16QImode : case V8HImode : case V4SFmode : case V4SImode : case V2DFmode : case V2DImode : case V1TImode : case TImode : case TFmode : case KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_vsx_dform_quad ( mode ) ; break ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s> static HOST_WIDE_INT rounded_frame_size ( int pushed ) { HOST_WIDE_INT size = get_frame_size ( ) ; HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT ; return ( ( size + pushed + align - 1 ) & - align ) - pushed ; } </s>

PUSHED is the number of bytes that are bing pushed on the stack for register saves . Return the frame size , padded appropriately so that the stack stays properly aligned .


<s> void rs6000_split_atomic_op ( enum rtx_code code , rtx mem , rtx val , rtx before , rtx after , rtx scratch ) { enum machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond = gen_rtx_REG ( CCmode , CR0_REGNO ) ; emit_insn ( gen_memory_barrier ( ) ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = scratch ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) x = gen_rtx_AND ( mode , gen_rtx_NOT ( mode , before ) , val ) ; else if ( code == AND ) x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 2 , before , val ) , UNSPEC_AND ) ; else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after != NULL_RTX ) emit_insn ( gen_rtx_SET ( VOIDmode , after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; emit_insn ( gen_isync ( ) ) ; } </s>

Expand an an atomic fetch-and-operate pattern . CODE is the binary operation to perform . MEM is the memory on which to operate . VAL is the second operand of the binary operator . BEFORE and AFTER are optional locations to return the value of MEM either before of after the operation . SCRATCH is a scratch register .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Sparc Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void X86WinAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; assert ( SlotSize == 4 || SlotSize == 8 ) ; unsigned RegA = ( SlotSize == 8 ) ? X86 :: RAX : X86 :: EAX ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; break ; } unsigned AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; for ( ; ; ) { if ( ! MRI -> use_empty ( AmountReg ) ) break ; MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ; if ( ! AmountDef ) break ; if ( AmountDef -> isCopy ( ) && AmountDef -> getOperand ( 1 ) . isReg ( ) ) AmountReg = AmountDef -> getOperand ( 1 ) . isReg ( ) ; AmountDef -> eraseFromParent ( ) ; break ; } } </s>


<s>
void
OR1KInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
OR1K
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
OR1K
::
ORI
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> bool empty ( ) const { return Edges . empty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> int iq2000_check_split ( rtx address , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) > ( unsigned ) UNITS_PER_WORD ) return 0 ; if ( ( GET_CODE ( address ) == SYMBOL_REF ) || ( GET_CODE ( address ) == CONST && GET_CODE ( XEXP ( XEXP ( address , 0 ) , 0 ) ) == SYMBOL_REF ) || GET_CODE ( address ) == LABEL_REF ) return 1 ; return 0 ; } </s>

Return nonzero if we split the address into high and low parts .


<s> AArch64Subtarget & AArch64Subtarget :: initializeSubtargetDependencies ( StringRef FS , StringRef CPUString ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , CPUString , FS ) ; initializeProperties ( ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles || ! FCycles ) return false ; const unsigned ScalingUpFactor = 1024 ; unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; return ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor <= UnpredCost ; } </s>


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; bool HasMicroMipsAttr = ! F . getFnAttribute ( "micromips" ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicroMipsAttr = ! F . getFnAttribute ( "nomicromips" ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


"instruction requires a CPU feature not currently enabled"

"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( ! EnablePPCPreinc ) return false ; SDValue Ptr ; EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { ST = ST ; Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> unsigned getLength ( ) { return CurType . Length ; } </s>

Return the number of bytes of data in this stream .


<s>
static
rtx
nds32_expand_builtin_null_ftype_reg
(
enum
insn_code
icode
,
tree
exp
,
rtx
target
)
{
struct
expand_operand
ops
[
1
]
;
tree
arg0
;
rtx
value0
;
arg0
=
CALL_EXPR_ARG
(
exp
,
0
)
;
value0
=
expand_normal
(
arg0
)
;
create_input_operand
(
&
ops
[
0
]
,
value0
,
TYPE_MODE
(
TREE_TYPE
(
arg0
)
)
)
;
if
(
!
maybe_expand_insn
(
icode
,
1
,
ops
)
)
error
(
"invalid argument to built-in function"
)
;
return
target
;
}
</s>

Function to expand builtin function for ' [ ( unspec_volatile [ ( reg ) ] ) ] ' .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : return 32 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool SystemZMCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { for ( uint64_t I = 0 ; I != Count ; ++ I ) OS << '\x7' ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void timode_scalar_chain :: mark_dual_mode_def ( df_ref ) { gcc_unreachable ( ) ; } </s>

For DImode conversion , mark register defined by DEF as requiring conversion .


<s> static void fixup_mova ( rtx_insn * mova ) { PUT_MODE ( XEXP ( MOVA_LABELREF ( mova ) , 0 ) , QImode ) ; if ( ! flag_pic ) { SET_SRC ( PATTERN ( mova ) ) = MOVA_LABELREF ( mova ) ; INSN_CODE ( mova ) = - 1 ; } else { rtx_insn * worker = mova ; rtx_code_label * lab = gen_label_rtx ( ) ; rtx wpat , wpat0 , wpat1 , wsrc , target , base , diff ; do { worker = NEXT_INSN ( worker ) ; gcc_assert ( worker && ! LABEL_P ( worker ) && ! JUMP_P ( worker ) ) ; } while ( NOTE_P ( worker ) || recog_memoized ( worker ) != CODE_FOR_casesi_worker_1 ) ; wpat = PATTERN ( worker ) ; wpat0 = XVECEXP ( wpat , 0 , 0 ) ; wpat1 = XVECEXP ( wpat , 0 , 1 ) ; wsrc = SET_SRC ( wpat0 ) ; PATTERN ( worker ) = ( gen_casesi_worker_2 ( SET_DEST ( wpat0 ) , XVECEXP ( wsrc , 0 , 1 ) , XEXP ( XVECEXP ( wsrc , 0 , 2 ) , 0 ) , lab , XEXP ( wpat1 , 0 ) ) ) ; INSN_CODE ( worker ) = - 1 ; target = XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , 0 , 0 ) ; base = gen_rtx_LABEL_REF ( Pmode , lab ) ; diff = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , target , base ) , UNSPEC_SYMOFF ) ; SET_SRC ( PATTERN ( mova ) ) = gen_rtx_CONST ( Pmode , diff ) ; INSN_CODE ( mova ) = - 1 ; } } </s>

Fix up a mova from a switch that went out of range .


<s> void fixup_addr_diff_vecs ( rtx_insn * first ) { rtx_insn * insn ; for ( insn = first ; insn ; insn = NEXT_INSN ( insn ) ) { rtx vec_lab , pat , prevpat , x , braf_label ; rtx_insn * prev ; if ( ! JUMP_TABLE_DATA_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC ) continue ; pat = PATTERN ( insn ) ; vec_lab = XEXP ( XEXP ( pat , 0 ) , 0 ) ; for ( prev = as_a < rtx_insn * > ( vec_lab ) ; ; prev = PREV_INSN ( prev ) ) { if ( ! JUMP_P ( prev ) ) continue ; prevpat = PATTERN ( prev ) ; if ( GET_CODE ( prevpat ) != PARALLEL || XVECLEN ( prevpat , 0 ) != 2 ) continue ; x = XVECEXP ( prevpat , 0 , 1 ) ; if ( GET_CODE ( x ) != USE ) continue ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == LABEL_REF && XEXP ( x , 0 ) == vec_lab ) break ; } if ( ! prev ) continue ; braf_label = XEXP ( XEXP ( SET_SRC ( XVECEXP ( prevpat , 0 , 0 ) ) , 1 ) , 0 ) ; emit_label_after ( as_a < rtx_insn * > ( braf_label ) , prev ) ; XEXP ( XEXP ( pat , 0 ) , 0 ) = braf_label ; } } </s>


<s> static void mips_legitimize_const_move ( machine_mode mode , rtx dest , rtx src ) { rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { mips_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( mips_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; return ; } if ( mips_tls_symbol_p ( src ) ) { mips_emit_move ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( ! TARGET_MIPS16 && can_create_pseudo_p ( ) ) ) ) { base = mips_force_temporary ( dest , base ) ; mips_emit_move ( dest , mips_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; mips_split_symbol ( dest , XEXP ( src , 0 ) , mode , & XEXP ( src , 0 ) ) ; mips_emit_move ( dest , src ) ; } </s>

Subroutine of mips_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s> static tree builtin_quaternary_function_type ( machine_mode mode_ret , machine_mode mode_arg0 , machine_mode mode_arg1 , machine_mode mode_arg2 , machine_mode mode_arg3 , enum rs6000_builtins builtin ) { tree function_type = NULL ; static tree v2udi_type = builtin_mode_to_type [ V2DImode ] [ 1 ] ; static tree v16uqi_type = builtin_mode_to_type [ V16QImode ] [ 1 ] ; static tree uchar_type = builtin_mode_to_type [ QImode ] [ 1 ] ; static tree xxeval_type = build_function_type_list ( v2udi_type , v2udi_type , v2udi_type , v2udi_type , uchar_type , NULL_TREE ) ; static tree xxpermx_type = build_function_type_list ( v2udi_type , v2udi_type , v2udi_type , v16uqi_type , uchar_type , NULL_TREE ) ; switch ( builtin ) { case P10V_BUILTIN_XXEVAL : gcc_assert ( ( mode_ret == V2DImode ) && ( mode_arg0 == V2DImode ) && ( mode_arg1 == V2DImode ) && ( mode_arg2 == V2DImode ) && ( mode_arg3 == QImode ) ) ; function_type = xxeval_type ; break ; case P10V_BUILTIN_VXXPERMX : gcc_assert ( ( mode_ret == V2DImode ) && ( mode_arg0 == V2DImode ) && ( mode_arg1 == V2DImode ) && ( mode_arg2 == V16QImode ) && ( mode_arg3 == QImode ) ) ; function_type = xxpermx_type ; break ; default : gcc_unreachable ( ) ; } return function_type ; } </s>

Map types for builtin functions with an explicit return type and exactly 4 arguments . Functions with fewer than 3 arguments use builtin_function_type . The number of quaternary built-in functions is very small . Handle each case specially .


<s>
bool
AArch64AsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
assert
(
MO
.
getFPImm
(
)
->
isZero
(
)
&&
"Only fp imm 0.0 is supported"
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
0.0
)
;
break
;
}
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> PPCSubtarget & PPCSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>


<s> bool X86TargetLowering :: isSplatValueForTargetNode ( SDValue Op , const APInt & DemandedElts , APInt & UndefElts , unsigned Depth ) const { unsigned NumElts = DemandedElts . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case X86ISD :: VBROADCAST : case X86ISD :: VBROADCAST_LOAD : if ( isTypeLegal ( Op . getValueType ( ) . getVectorElementType ( ) ) ) { UndefElts = APInt :: getNullValue ( NumElts ) ; return true ; } return false ; } return TargetLowering :: isSplatValueForTargetNode ( Op , DemandedElts , UndefElts , Depth ) ; } </s>

Return true if vector Op has the same value across all DemandedElts , indicating any elements which may be undef in the output UndefElts .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) PM -> add ( createThumb2SizeReductionPass ( ) ) ; addPass ( UnpackMachineBundlesID ) ; } PM -> add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void mips_conditional_register_usage ( void ) { if ( ! TARGET_DSP ) { int regno ; for ( regno = DSP_ACC_REG_FIRST ; regno <= DSP_ACC_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( ! TARGET_HARD_FLOAT ) { int regno ; for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; for ( regno = ST_REG_FIRST ; regno <= ST_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } else if ( ! ISA_HAS_8CC ) { int regno ; for ( regno = ST_REG_FIRST ; regno <= ST_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( TARGET_MIPS16 ) { fixed_regs [ 18 ] = call_used_regs [ 18 ] = 1 ; fixed_regs [ 19 ] = call_used_regs [ 19 ] = 1 ; fixed_regs [ 20 ] = call_used_regs [ 20 ] = 1 ; fixed_regs [ 21 ] = call_used_regs [ 21 ] = 1 ; fixed_regs [ 22 ] = call_used_regs [ 22 ] = 1 ; fixed_regs [ 23 ] = call_used_regs [ 23 ] = 1 ; fixed_regs [ 26 ] = call_used_regs [ 26 ] = 1 ; fixed_regs [ 27 ] = call_used_regs [ 27 ] = 1 ; fixed_regs [ 30 ] = call_used_regs [ 30 ] = 1 ; } if ( mips_abi == ABI_64 ) { int regno ; for ( regno = FP_REG_FIRST + 20 ; regno < FP_REG_FIRST + 24 ; regno ++ ) call_really_used_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( mips_abi == ABI_N32 ) { int regno ; for ( regno = FP_REG_FIRST + 21 ; regno <= FP_REG_FIRST + 31 ; regno += 2 ) call_really_used_regs [ regno ] = call_used_regs [ regno ] = 1 ; } } </s>


<s> int fp_zero_operand ( rtx op ) { REAL_VALUE_TYPE r ; if ( GET_MODE ( op ) != SFmode ) return 0 ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r , dconst0 ) && ! REAL_VALUE_MINUS_ZERO ( r ) ; } </s>

Returns true if OP is a floating point value with value 0.0 .


"Unknown fence ordering in emitLeadingFence"


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> void SystemZHazardRecognizer :: Reset ( ) { CurrGroupSize = 0 ; clearProcResCounters ( ) ; GrpCount = 0 ; LastFPdOpCycleIdx = UINT_MAX ; DEBUG ( CurGroupDbg = "" ; ) ; } </s>


<s> rtx arm_function_arg ( CUMULATIVE_ARGS * pcum , enum machine_mode mode , tree type , int named ) { int nregs ; if ( TARGET_IWMMXT_ABI && arm_vector_mode_supported_p ( mode ) && pcum -> named_count > pcum -> nargs + 1 ) { if ( pcum -> iwmmxt_nregs <= 9 ) return gen_rtx_REG ( mode , pcum -> iwmmxt_nregs + FIRST_IWMMXT_REGNUM ) ; else { pcum -> can_split = false ; return NULL_RTX ; } } if ( pcum -> nregs & 1 && ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align ( mode , type ) ) pcum -> nregs ++ ; if ( mode == VOIDmode ) return GEN_INT ( pcum -> call_cookie ) ; if ( pcum -> can_split ) nregs = 1 ; else nregs = ARM_NUM_REGS2 ( mode , type ) ; if ( ! named || pcum -> nregs + nregs > NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( mode , pcum -> nregs ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


"builtin %s only accepts a string argument"

"cpu %s is an invalid argument to builtin %s"

"hwcap %s is an invalid argument to builtin %s"

Expand the CPU builtin in FCODE and store the result in TARGET .


"********** AArch64 Conditional Compares **********\n"

runOnMachineFunction - Emit the function body .


"A single use instruction with no uses."

Return true if it is profitable to hoist instruction in the then/else to before if .


Check whether X is a VEC_SERIES-like constant that starts at 0 and has a step in the range of INDEX . Return the index expression if so , otherwise return null .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; case VEISD :: RET_FLAG : return "VEISD::RET_FLAG" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> static int mips16_insn_length ( rtx insn ) { if ( JUMP_P ( insn ) ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == ADDR_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , 0 ) ; if ( GET_CODE ( body ) == ADDR_DIFF_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , 1 ) ; } return get_attr_length ( insn ) ; } </s>


<s> static void or1k_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain ) { const unsigned movhi_r13 = ( 0x06u << 26 ) | ( 13 << 21 ) ; const unsigned movhi_r11 = ( 0x06u << 26 ) | ( 11 << 21 ) ; const unsigned ori_r13_r13 = ( 0x2a << 26 ) | ( 13 << 21 ) | ( 13 << 16 ) ; const unsigned ori_r11_r11 = ( 0x2a << 26 ) | ( 11 << 21 ) | ( 11 << 16 ) ; const unsigned jr_r13 = ( 0x11 << 26 ) | ( 13 << 11 ) ; rtx tramp [ 5 ] , fnaddr , f_hi , f_lo , c_hi , c_lo ; fnaddr = force_operand ( XEXP ( DECL_RTL ( fndecl ) , 0 ) , NULL ) ; f_hi = expand_binop ( SImode , lshr_optab , fnaddr , GEN_INT ( 16 ) , NULL , true , OPTAB_DIRECT ) ; f_lo = expand_binop ( SImode , and_optab , fnaddr , GEN_INT ( 0xffff ) , NULL , true , OPTAB_DIRECT ) ; chain = force_operand ( chain , NULL ) ; c_hi = expand_binop ( SImode , lshr_optab , chain , GEN_INT ( 16 ) , NULL , true , OPTAB_DIRECT ) ; c_lo = expand_binop ( SImode , and_optab , chain , GEN_INT ( 0xffff ) , NULL , true , OPTAB_DIRECT ) ; tramp [ 0 ] = expand_binop ( SImode , ior_optab , f_hi , gen_int_mode ( movhi_r13 , SImode ) , f_hi , true , OPTAB_DIRECT ) ; tramp [ 1 ] = expand_binop ( SImode , ior_optab , c_hi , gen_int_mode ( movhi_r11 , SImode ) , c_hi , true , OPTAB_DIRECT ) ; tramp [ 2 ] = expand_binop ( SImode , ior_optab , f_lo , gen_int_mode ( ori_r13_r13 , SImode ) , f_lo , true , OPTAB_DIRECT ) ; tramp [ 4 ] = expand_binop ( SImode , ior_optab , c_lo , gen_int_mode ( ori_r11_r11 , SImode ) , c_lo , true , OPTAB_DIRECT ) ; tramp [ 3 ] = gen_int_mode ( jr_r13 , SImode ) ; for ( int i = 0 ; i < 5 ; ++ i ) { rtx mem = adjust_address ( m_tramp , SImode , i * 4 ) ; emit_move_insn ( mem , tramp [ i ] ) ; } } </s>

Worker for TARGET_TRAMPOLINE_INIT . This is called to initialize a trampoline . The argument M_TRAMP is an RTX for the memory block to be initialized with trampoline code . The argument FNDECL contains the definition of the nested function to be called , we use this to get the function 's address . The argument CHAIN is an RTX for the static chain value to be passed to the nested function .


<s> bool AArch64TargetLowering :: isFMAFasterThanFMulAndFAdd ( const Function & F , Type * Ty ) const { switch ( Ty -> getScalarType ( ) -> getTypeID ( ) ) { case Type :: FloatTyID : case Type :: DoubleTyID : return true ; default : return false ; } } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> const TargetRegisterClass * SystemZTargetLowering :: getRepRegClassFor ( MVT VT ) const { if ( VT == MVT :: Untyped ) return & SystemZ :: ADDR128BitRegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .

SystemZ SystemZ MVT::Untyped SystemZ::ADDR128BitRegClass


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; const MCSectionCOFF * S = cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ; if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> bool AArch64TargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { N = N -> getOperand ( 0 ) . getNode ( ) ; EVT VT = N -> getValueType ( 0 ) ; if ( N -> getOpcode ( ) == ISD :: AND && ( VT == MVT :: i32 || VT == MVT :: i64 ) && isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { uint64_t TruncMask = N -> getConstantOperandVal ( 1 ) ; if ( isMask_64 ( TruncMask ) && N -> getOperand ( 0 ) . getOpcode ( ) == ISD :: SRL && isa < ConstantSDNode > ( N -> getOperand ( 0 ) -> getOperand ( 1 ) ) ) return false ; } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s> void PPCPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static void load_pic_register ( bool delay_pic_helper ) { int orig_flag_pic = flag_pic ; if ( ! pic_helper_symbol_name [ 0 ] ) { ASM_GENERATE_INTERNAL_LABEL ( pic_helper_symbol_name , "LADDPC" , 0 ) ; pic_helper_symbol = gen_rtx_SYMBOL_REF ( Pmode , pic_helper_symbol_name ) ; global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; } if ( ! delay_pic_helper && ! pic_helper_emitted_p ) emit_pic_helper ( ) ; flag_pic = 0 ; if ( TARGET_ARCH64 ) emit_insn ( gen_load_pcrel_symdi ( pic_offset_table_rtx , global_offset_table , pic_helper_symbol ) ) ; else emit_insn ( gen_load_pcrel_symsi ( pic_offset_table_rtx , global_offset_table , pic_helper_symbol ) ) ; flag_pic = orig_flag_pic ; emit_insn ( gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ) ; } </s>


<s> static rtx nds32_gen_dup_4_byte_to_word_value_aux ( rtx value , rtx value4word ) { gcc_assert ( GET_MODE ( value ) == QImode || CONST_INT_P ( value ) ) ; if ( CONST_INT_P ( value ) ) { unsigned HOST_WIDE_INT val = UINTVAL ( value ) & GET_MODE_MASK ( QImode ) ; rtx new_val = gen_int_mode ( val | ( val << 8 ) | ( val << 16 ) | ( val << 24 ) , SImode ) ; emit_move_insn ( value4word , new_val ) ; } else { if ( NDS32_EXT_DSP_P ( ) ) { rtx tmp = gen_reg_rtx ( SImode ) ; convert_move ( tmp , value , true ) ; emit_insn ( gen_insvsi_internal ( tmp , gen_int_mode ( 0x8 , SImode ) , tmp ) ) ; emit_insn ( gen_pkbbsi_1 ( value4word , tmp , tmp ) ) ; } else { rtx tmp1 , tmp2 , tmp3 , tmp4 ; tmp1 = expand_binop ( SImode , and_optab , value , gen_int_mode ( 0xff , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp2 = expand_binop ( SImode , ashl_optab , tmp1 , gen_int_mode ( 8 , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp3 = expand_binop ( SImode , ior_optab , tmp1 , tmp2 , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp4 = expand_binop ( SImode , ashl_optab , tmp3 , gen_int_mode ( 16 , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_insn ( gen_iorsi3 ( value4word , tmp3 , tmp4 ) ) ; } } return value4word ; } </s>

Auxiliary function for expand setmem pattern .


<s> inline bool registered_function_hasher :: equal ( value_type value , const compare_type & key ) { return value -> instance == key ; } </s>


<s> void LEGInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LEG :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"


<s> void PPCBranchCoalescing :: initialize ( MachineFunction & MF ) { MDT = & getAnalysis < MachineDominatorTree > ( ) ; MPDT = & getAnalysis < MachinePostDominatorTree > ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> InstructionCost X86TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; InstructionCost Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> bool X86TTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( Vector ) { if ( ST -> hasNEON ( ) ) return 16 ; if ( ST -> hasMVEIntegerOps ( ) ) return 8 ; return 0 ; } if ( ST -> isThumb1Only ( ) ) return 8 ; return 13 ; } </s>


<s> static void aarch64_parse_override_string ( const char * input_string , struct tune_params * tune ) { const char separator = ':' ; size_t string_length = strlen ( input_string ) + 1 ; char * string_root = ( char * ) xmalloc ( sizeof ( * string_root ) * string_length ) ; char * string = string_root ; strncpy ( string , input_string , string_length ) ; string [ string_length - 1 ] = '\0' ; char * ntoken = string ; while ( ( ntoken = strchr ( string , separator ) ) ) { size_t token_length = ntoken - string ; * ntoken = '\0' ; aarch64_parse_one_override_token ( string , token_length , tune ) ; string = ++ ntoken ; } aarch64_parse_one_override_token ( string , strlen ( string ) , tune ) ; free ( string_root ) ; } </s>

Parse STRING looking for options in the format : string : : option : string option : : name=substring name : : { a-z } substring : : defined by option .


<s> bool Inserter :: runOnMachineFunction ( MachineFunction & F ) { Cpu0FunctionInfo * Cpu0FI = F . getInfo < Cpu0FunctionInfo > ( ) ; const TargetSubtargetInfo * STI = TM . getSubtargetImpl ( * ( F . getFunction ( ) ) ) ; const TargetInstrInfo * TII = STI -> getInstrInfo ( ) ; if ( ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) || ( ! Cpu0FI -> globalBaseRegFixed ( ) ) ) return false ; bool Changed = false ; int FI = Cpu0FI -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isEHPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( Cpu0 :: LD ) , Cpu0 :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != Cpu0 :: JALR ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( Cpu0 :: LD ) , Cpu0 :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


Worker function for ` HARD_REGNO_RENAME_OK ' . Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegUnits . init ( * TRI ) ; UsedRegUnits . init ( * TRI ) ; DefinedInBB . init ( * TRI ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) { auto M = optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; Modified |= M ; } return Modified ; } </s>


<s> MipsSubtarget & MipsSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine * TM ) { std :: string CPUName = selectMipsCPU ( TargetTriple , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( InMips16Mode && ! TM -> Options . UseSoftFloat ) InMips16HardFloat = true ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .