<s> int ARMTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , bool IsPairwiseForm , TTI :: TargetCostKind CostKind ) { EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ValVT . isSimple ( ) || ISD != ISD :: ADD ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { ISD :: ADD , MVT :: v16i8 , 1 } , { ISD :: ADD , MVT :: v8i16 , 1 } , { ISD :: ADD , MVT :: v4i32 , 1 } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: GPR32RegClassID : case Mips :: GPR64RegClassID : case Mips :: DSPRRegClassID : { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 32 ; case Mips :: AFGR64RegClassID : return 16 ; case Mips :: FGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
case
SP
::
EH_SJLJ_SETJMP32ri
:
case
SP
::
EH_SJLJ_SETJMP32rr
:
return
emitEHSjLjSetJmp
(
MI
,
BB
)
;
case
SP
::
EH_SJLJ_LONGJMP32rr
:
case
SP
::
EH_SJLJ_LONGJMP32ri
:
return
emitEHSjLjLongJmp
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"Suitable Machine Function for outlining must track liveness"

Optional target hook that returns true if MBB is safe to outline from , and returns any target-specific information in Flags .


<s> bool TOYInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static bool sparc_function_value_regno_p ( const unsigned int regno ) { return ( regno == 8 || regno == 32 ) ; } </s>

Handle FUNCTION_VALUE_REGNO_P . On the SPARC , the first `` output '' reg is used for integer values , and the first floating point register is used for floating point values .


<s> bool mips_expand_block_move ( rtx dest , rtx src , rtx length ) { if ( ! ISA_HAS_LWL_LWR && ( MEM_ALIGN ( src ) < MIPS_MIN_MOVE_MEM_ALIGN || MEM_ALIGN ( dest ) < MIPS_MIN_MOVE_MEM_ALIGN ) ) return false ; if ( CONST_INT_P ( length ) ) { if ( INTVAL ( length ) <= MIPS_MAX_MOVE_BYTES_STRAIGHT ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) , MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } } return false ; } </s>

Expand a movmemsi instruction , which copies LENGTH bytes from memory reference SRC to memory reference DEST .


<s> void sparc_profile_hook ( int labelno ) { char buf [ 32 ] ; rtx lab , fun ; fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_FUNCTION ) ; if ( NO_PROFILE_COUNTERS ) { emit_library_call ( fun , LCT_NORMAL , VOIDmode , 0 ) ; } else { ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; lab = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; emit_library_call ( fun , LCT_NORMAL , VOIDmode , 1 , lab , Pmode ) ; } } </s>

Output rtl to increment the profiler label LABELNO for profiling a function entry .


<s> Register X86TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { assert ( ! isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) ; return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s>
bool
MipsConstantIslands
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
MCP
=
mf
.
getConstantPool
(
)
;
DEBUG
(
dbgs
(
)
<<
"constant island machine function "
<<
"\n"
)
;
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
inMips16Mode
(
)
||
!
MipsSubtarget
::
useConstantIslands
(
)
)
{
return
false
;
}
TII
=
(
const
MipsInstrInfo
*
)
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"constant island processing "
<<
"\n"
)
;
prescanForConstants
(
)
;
MF
->
getRegInfo
(
)
.
invalidateLiveness
(
)
;
MF
->
RenumberBlocks
(
)
;
std
::
vector
<
MachineInstr
*
>
CPEMIs
;
if
(
!
MCP
->
isEmpty
(
)
)
doInitialPlacement
(
CPEMIs
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
"constant island machine function "
"\n"
Mips
Mips
Mips
Mips
"constant island processing "
"\n"


<s> int ia64_ld_address_bypass_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx dest , src , reg , mem ; gcc_assert ( producer && consumer ) ; dest = ia64_single_set ( producer ) ; gcc_assert ( dest ) ; reg = SET_DEST ( dest ) ; gcc_assert ( reg ) ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; gcc_assert ( GET_CODE ( reg ) == REG ) ; src = ia64_single_set ( consumer ) ; gcc_assert ( src ) ; mem = SET_SRC ( src ) ; gcc_assert ( mem ) ; if ( GET_CODE ( mem ) == UNSPEC && XVECLEN ( mem , 0 ) > 0 ) mem = XVECEXP ( mem , 0 , 0 ) ; else if ( GET_CODE ( mem ) == IF_THEN_ELSE ) { gcc_assert ( XINT ( XEXP ( XEXP ( mem , 0 ) , 0 ) , 1 ) == UNSPEC_LDCCLR ) ; mem = XEXP ( mem , 1 ) ; } while ( GET_CODE ( mem ) == SUBREG || GET_CODE ( mem ) == ZERO_EXTEND ) mem = XEXP ( mem , 0 ) ; if ( GET_CODE ( mem ) == UNSPEC ) { int c = XINT ( mem , 1 ) ; gcc_assert ( c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A || c == UNSPEC_LDSA ) ; mem = XVECEXP ( mem , 0 , 0 ) ; } gcc_assert ( GET_CODE ( mem ) == LO_SUM || GET_CODE ( mem ) == MEM ) ; return reg_mentioned_p ( reg , mem ) ; } </s>

The following function returns TRUE if PRODUCER ( of type ilog or ld ) produces address for CONSUMER ( of type ld or fld ) .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> const unsigned * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; if ( MF ) { const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; callsEHReturn = ( MMI ? MMI -> callsEHReturn ( ) : false ) ; } static const unsigned CalleeSavedRegs32Bit [ ] = { X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs32EHRet [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs64Bit [ ] = { X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegs64EHRet [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegsWin64 [ ] = { X86 :: RBX , X86 :: RBP , X86 :: RDI , X86 :: RSI , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: XMM6 , X86 :: XMM7 , X86 :: XMM8 , X86 :: XMM9 , X86 :: XMM10 , X86 :: XMM11 , X86 :: XMM12 , X86 :: XMM13 , X86 :: XMM14 , X86 :: XMM15 , 0 } ; if ( Is64Bit ) { if ( IsWin64 ) return CalleeSavedRegsWin64 ; else return ( callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit ) ; } else { return ( callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit ) ; } } </s>


<s> bool MipsTargetMachine :: addPostRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMipsExpandPseudoPass ( * this ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool AArch64LowerHomogeneousPE :: run ( ) { bool Changed = false ; for ( auto & F : * M ) { if ( F . empty ( ) ) continue ; MachineFunction * MF = MMI -> getMachineFunction ( F ) ; if ( ! MF ) continue ; Changed |= runOnMachineFunction ( * MF ) ; } return Changed ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> unsigned getMaxSupportedInterleaveFactor ( ) const override { return 4 ; } </s>

Get the maximum supported factor for interleaved memory accesses .


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { switch ( ( Sparc :: Fixups ) Fixup . getKind ( ) ) { default : return false ; case Sparc :: fixup_sparc_wplt30 : if ( Target . getSymA ( ) -> getSymbol ( ) . isTemporary ( ) ) return false ; LLVM_FALLTHROUGH ; case Sparc :: fixup_sparc_tls_gd_hi22 : case Sparc :: fixup_sparc_tls_gd_lo10 : case Sparc :: fixup_sparc_tls_gd_add : case Sparc :: fixup_sparc_tls_gd_call : case Sparc :: fixup_sparc_tls_ldm_hi22 : case Sparc :: fixup_sparc_tls_ldm_lo10 : case Sparc :: fixup_sparc_tls_ldm_add : case Sparc :: fixup_sparc_tls_ldm_call : case Sparc :: fixup_sparc_tls_ldo_hix22 : case Sparc :: fixup_sparc_tls_ldo_lox10 : case Sparc :: fixup_sparc_tls_ldo_add : case Sparc :: fixup_sparc_tls_ie_hi22 : case Sparc :: fixup_sparc_tls_ie_lo10 : case Sparc :: fixup_sparc_tls_ie_ld : case Sparc :: fixup_sparc_tls_ie_ldx : case Sparc :: fixup_sparc_tls_ie_add : case Sparc :: fixup_sparc_tls_le_hix22 : case Sparc :: fixup_sparc_tls_le_lox10 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> int fp_high_losum_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long i ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , i ) ; return ! SPARC_SIMM13_P ( i ) && ! SPARC_SETHI_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a high/losum instruction sequence .


<s> static bool pru_can_use_doloop_p ( const widest_int & , const widest_int & iterations_max , unsigned int loop_depth , bool ) { if ( loop_depth > 1 ) return false ; if ( iterations_max == 0 || wi :: geu_p ( iterations_max , 0xffff ) ) return false ; return true ; } </s>


<s> SystemZConstantPoolValue * SystemZConstantPoolValue :: Create ( const GlobalValue * GV , SystemZCP :: SystemZCPModifier Modifier ) { return new SystemZConstantPoolValue ( GV , Modifier ) ; } </s>

Construct a unary instruction , given the opcode and an operand .

SystemZ SystemZ SystemZ SystemZCP::SystemZCPModifier SystemZ


<s> bool loongarch_12bit_offset_address_p ( rtx x , machine_mode mode ) { struct loongarch_address_info addr ; return ( loongarch_classify_address ( & addr , x , mode , false ) && ( ( addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && LARCH_12BIT_OFFSET_P ( INTVAL ( addr . offset ) ) ) || addr . type == ADDRESS_LO_SUM ) ) ; } </s>

Return true if X is a legitimate address with a 12-bit offset or addr.type is ADDRESS_LO_SUM . MODE is the mode of the value being accessed .


<s> void sparc_expand_epilogue ( bool for_eh ) { HOST_WIDE_INT size = sparc_frame_size ; if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_RESTORE ) ; if ( size == 0 || for_eh ) ; else if ( sparc_leaf_function_p ) { if ( size <= 4096 ) emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; else if ( size <= 8192 ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - 4096 ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( size ) ) ; emit_insn ( gen_stack_pointer_inc ( reg ) ) ; } } } </s>

Expand the function epilogue , either normal or part of a sibcall . We emit all the instructions except the return or the call .


<s> bool MipsFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = MF -> begin ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> TargetTransformInfo :: PopcntSupportKind getPopcntSupport ( unsigned TyWidth ) { if ( TyWidth == 32 ) return TTI :: PSK_FastHardware ; return TTI :: PSK_Software ; } </s>

Return hardware support for population count .


<s> static void mips_set_tuning_info ( void ) { if ( mips_tuning_info . initialized_p && mips_tuning_info . arch == mips_arch && mips_tuning_info . tune == mips_tune && mips_tuning_info . mips16_p == TARGET_MIPS16 ) return ; mips_tuning_info . arch = mips_arch ; mips_tuning_info . tune = mips_tune ; mips_tuning_info . mips16_p = TARGET_MIPS16 ; mips_tuning_info . initialized_p = true ; dfa_start ( ) ; struct mips_sim state ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; mips_set_fast_mult_zero_zero_p ( & state ) ; dfa_finish ( ) ; } </s>

Set up costs based on the current architecture and tuning settings .


<s> void LanaiAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( I -> isCall ( ) ) { emitCallInstruction ( & * I ) ; continue ; } customEmitInstruction ( & * I ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
Register
ARMTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r6"
,
ARM
::
R6
)
.
Case
(
"r7"
,
ARM
::
R7
)
.
Case
(
"r8"
,
ARM
::
R8
)
.
Case
(
"r9"
,
ARM
::
R9
)
.
Case
(
"r10"
,
ARM
::
R10
)
.
Case
(
"r11"
,
ARM
::
R11
)
.
Case
(
"sp"
,
ARM
::
SP
)
.
Default
(
ARM
::
NoRegister
)
;
if
(
Reg
!=
ARM
::
NoRegister
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( const MipsTargetMachine & TM , const MipsSubtarget & STI ) { return llvm :: createMipsSETargetLowering ( TM , STI ) ; } </s>


<s> MCSymbol * MipsELFStreamer :: emitCFILabel ( ) { MCSymbol * Label = getContext ( ) . createTempSymbol ( "cfi" , true ) ; MCELFStreamer :: emitLabel ( Label ) ; return Label ; } </s>

When emitting an object file , create and emit a real label .


<s> bool aarch64_bitmask_imm ( HOST_WIDE_INT val_in , machine_mode mode ) { unsigned HOST_WIDE_INT val , tmp , mask , first_one , next_one ; int bits ; val = aarch64_replicate_bitmask_imm ( val_in , mode ) ; tmp = val + ( val & - val ) ; if ( tmp == ( tmp & - tmp ) ) return ( val + 1 ) > 1 ; if ( mode == SImode ) val = ( val << 32 ) | ( val & 0xffffffff ) ; if ( val & 1 ) val = ~ val ; first_one = val & - val ; tmp = val & ( val + first_one ) ; if ( tmp == 0 ) return true ; next_one = tmp & - tmp ; bits = clz_hwi ( first_one ) - clz_hwi ( next_one ) ; mask = val ^ tmp ; if ( ( mask >> bits ) != 0 || bits != ( bits & - bits ) ) return false ; return val == mask * bitmask_imm_mul [ __builtin_clz ( bits ) - 26 ] ; } </s>

Return true if val is a valid bitmask immediate .


<s> AArch64Subtarget & AArch64Subtarget :: initializeSubtargetDependencies ( StringRef FS , StringRef CPUString , StringRef TuneCPUString ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; if ( TuneCPUString . empty ( ) ) TuneCPUString = CPUString ; ParseSubtargetFeatures ( CPUString , TuneCPUString , FS ) ; initializeProperties ( ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> int csky_compute_pushpop_length ( rtx * operands ) { rtx parallel_op = operands [ 2 ] ; unsigned indx = XVECLEN ( parallel_op , 0 ) - 1 ; unsigned first_indx = 0 ; unsigned regno = REGNO ( operands [ 1 ] ) ; if ( regno > CSKY_LR_REGNUM ) return 4 ; for ( ; indx > first_indx ; indx -- ) { regno = REGNO ( XEXP ( XVECEXP ( parallel_op , 0 , indx ) , 0 ) ) ; if ( regno > CSKY_LR_REGNUM ) return 4 ; } return 2 ; } </s>

Compute the attribute `` length '' of push or pop insn , according to the registers it uses .


<s> void buildLoad ( unsigned Val , unsigned Addr , uint64_t Size , unsigned Alignment , MachinePointerInfo & MPO ) { MachineMemOperand * MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; MIRBuilder . buildLoad ( Val , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> int ix86_attr_length_address_default ( rtx_insn * insn ) { int i ; if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) , addr ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; addr = SET_SRC ( set ) ; return memory_address_length ( addr , true ) ; } extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) { rtx op = recog_data . operand [ i ] ; if ( MEM_P ( op ) ) { constrain_operands_cached ( insn , reload_completed ) ; if ( which_alternative != - 1 ) { const char * constraints = recog_data . constraints [ i ] ; int alt = which_alternative ; while ( * constraints == '=' || * constraints == '+' ) constraints ++ ; while ( alt -- > 0 ) while ( * constraints ++ != ',' ) ; if ( * constraints == 'X' ) continue ; } int len = memory_address_length ( XEXP ( op , 0 ) , false ) ; if ( ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( op ) ) ) len ++ ; return len ; } } return 0 ; } </s>

Compute default value for `` length_address '' attribute .


<s> const SmallVectorImpl < MachineBasicBlock * > & getOrder ( ) const { return Order ; } </s>


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { if ( usePreRAHazardRecognizer ( ) ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , "pre-RA-sched" ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> int get_dest_uid ( rtx label , int max_uid ) { rtx_insn * dest = next_real_insn ( label ) ; if ( ! dest ) return 0 ; int dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return 0 ; return dest_uid ; } </s>

Return the UID of the insn that follows the specified label .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Indirect Thunks"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned MipsInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { MipsFunctionInfo * MipsFI = MF -> getInfo < MipsFunctionInfo > ( ) ; unsigned GlobalBaseReg = MipsFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( Mips :: CPURegsRegisterClass ) ; BuildMI ( FirstMBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( Mips :: GP ) ; RegInfo . addLiveIn ( Mips :: GP ) ; MipsFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips Mips Mips Mips Mips Mips 0 Mips::CPURegsRegisterClass Mips::GP Mips::GP Mips


<s> bool ARMBaseInstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Subtarget . isCortexA8 ( ) && ( DDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainVFP ) ) return true ; int Latency = getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency <= 3 ) return false ; return DDomain == ARMII :: DomainVFP || DDomain == ARMII :: DomainNEON || UDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainNEON ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .

ARM ARM ARMII::DomainMask ARMII::DomainMask ARMII::DomainVFP ARMII::DomainVFP 3 ARMII::DomainVFP ARMII::DomainNEON ARMII::DomainVFP ARMII::DomainNEON


<s> enum rtx_code arm_canonicalize_comparison ( enum rtx_code code , enum machine_mode mode , rtx * op1 ) { unsigned HOST_WIDE_INT i = INTVAL ( * op1 ) ; unsigned HOST_WIDE_INT maxval ; maxval = ( ( ( unsigned HOST_WIDE_INT ) 1 ) << ( GET_MODE_BITSIZE ( mode ) - 1 ) ) - 1 ; switch ( code ) { case EQ : case NE : return code ; case GT : case LE : if ( i != maxval && ( const_ok_for_arm ( i + 1 ) || const_ok_for_arm ( - ( i + 1 ) ) ) ) { * op1 = GEN_INT ( i + 1 ) ; return code == GT ? GE : LT ; } break ; case GE : case LT : if ( i != ~ maxval && ( const_ok_for_arm ( i - 1 ) || const_ok_for_arm ( - ( i - 1 ) ) ) ) { * op1 = GEN_INT ( i - 1 ) ; return code == GE ? GT : LE ; } break ; case GTU : case LEU : if ( i != ~ ( ( unsigned HOST_WIDE_INT ) 0 ) && ( const_ok_for_arm ( i + 1 ) || const_ok_for_arm ( - ( i + 1 ) ) ) ) { * op1 = GEN_INT ( i + 1 ) ; return code == GTU ? GEU : LTU ; } break ; case GEU : case LTU : if ( i != 0 && ( const_ok_for_arm ( i - 1 ) || const_ok_for_arm ( - ( i - 1 ) ) ) ) { * op1 = GEN_INT ( i - 1 ) ; return code == GEU ? GTU : LEU ; } break ; default : gcc_unreachable ( ) ; } return code ; } </s>

Canonicalize a comparison so that we are more likely to recognize it . This can be done for a few constant compares , where we can make the immediate value easier to load .


<s> static void aarch64_restore_callee_saves ( machine_mode mode , HOST_WIDE_INT start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { rtx base_rtx = stack_pointer_rtx ; rtx ( * gen_mem_ref ) ( machine_mode , rtx ) = ( frame_pointer_needed ? gen_frame_mem : gen_rtx_MEM ) ; unsigned regno ; unsigned regno2 ; HOST_WIDE_INT offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_mem_ref ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_mem_ref ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else emit_move_insn ( reg , mem ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfi_ops ) ; } } </s>

Emit code to restore the callee registers of mode MODE from register number START up to and including LIMIT . Restore from the stack offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true . Write the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> bool useMachineCombiner ( ) const override { return true ; } </s>

Return true when a target supports MachineCombiner .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveX86CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , IsJIT ( JIT ) { if ( TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } setMachineOutliner ( true ) ; setSupportsDebugEntryValues ( true ) ; initAsmInfo ( ) ; } </s>


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int decide_alignment ( int align , enum stringop_alg alg , int expected_size , machine_mode move_mode ) { int desired_align = 0 ; gcc_assert ( alg != no_stringop ) ; if ( alg == libcall ) return 0 ; if ( move_mode == VOIDmode ) return 0 ; desired_align = GET_MODE_SIZE ( move_mode ) ; if ( TARGET_CPU_P ( PENTIUMPRO ) && ( alg == rep_prefix_4_byte || alg == rep_prefix_1_byte ) ) desired_align = 8 ; if ( optimize_size ) desired_align = 1 ; if ( desired_align < align ) desired_align = align ; if ( expected_size != - 1 && expected_size < 4 ) desired_align = align ; return desired_align ; } </s>

Decide on alignment . We know that the operand is already aligned to ALIGN ( ALIGN can be based on profile feedback and thus it is not 100 % guaranteed ) .


<s> inline bool isKMasked ( uint64_t TSFlags ) { return ( TSFlags & X86II :: EVEX_K ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds any of k-masked opcodes .


<s>
static
void
mips_output_function_prologue
(
FILE
*
file
)
{
const
char
*
fnname
;
if
(
TARGET_MIPS16
&&
TARGET_HARD_FLOAT_ABI
&&
crtl
->
args
.
info
.
fp_code
!=
0
)
mips16_build_function_stub
(
)
;
fnname
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
mips_start_function_definition
(
fnname
,
TARGET_MIPS16
)
;
if
(
!
flag_inhibit_size_directive
)
{
const
struct
mips_frame_info
*
frame
;
frame
=
&
cfun
->
machine
->
frame
;
fprintf
(
file
,
"\t.frame\t%s,"
HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
"# vars= "
HOST_WIDE_INT_PRINT_DEC
", regs= %d/%d"
", args= "
HOST_WIDE_INT_PRINT_DEC
", gp= "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
reg_names
[
frame_pointer_needed
HARD_FRAME_POINTER_REGNUM
:
STACK_POINTER_REGNUM
]
,
(
frame_pointer_needed
frame
->
total_size
frame
->
hard_frame_pointer_offset
:
frame
->
total_size
)
,
reg_names
[
RETURN_ADDR_REGNUM
]
,
frame
->
var_size
,
frame
->
num_gp
,
frame
->
num_fp
,
frame
->
args_size
,
frame
->
cprestore_size
)
;
fprintf
(
file
,
"\t.mask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
frame
->
mask
,
frame
->
gp_save_offset
)
;
fprintf
(
file
,
"\t.fmask\t0x%08x,"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
frame
->
fmask
,
frame
->
fp_save_offset
)
;
}
if
(
mips_must_initialize_gp_p
(
)
&&
mips_current_loadgp_style
(
)
==
LOADGP_OLDABI
)
{
if
(
TARGET_MIPS16
)
{
output_asm_insn
(
"li\t$2,%%hi(_gp_disp)"
,
0
)
;
output_asm_insn
(
"addiu\t$3,$pc,%%lo(_gp_disp)"
,
0
)
;
output_asm_insn
(
"sll\t$2,16"
,
0
)
;
output_asm_insn
(
"addu\t$2,$3"
,
0
)
;
}
else
{
mips_push_asm_switch
(
&
mips_noreorder
)
;
output_asm_insn
(
".cpload\t%^"
,
0
)
;
if
(
!
cfun
->
machine
->
all_noreorder_p
)
mips_pop_asm_switch
(
&
mips_noreorder
)
;
else
mips_push_asm_switch
(
&
mips_nomacro
)
;
}
}
else
if
(
cfun
->
machine
->
all_noreorder_p
)
{
mips_push_asm_switch
(
&
mips_noreorder
)
;
mips_push_asm_switch
(
&
mips_nomacro
)
;
}
mips_output_cplocal
(
)
;
}
</s>

Set up the stack and frame ( if desired ) for the function .


<s> const ARMGNULDBackend & getTarget ( ) const { return m_Target ; } </s>

getTarget - Return the target machine this machine code is compiled with


<s> virtual const AZPRSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> int ix86_attr_length_vex_default ( rtx_insn * insn , bool has_0f_opcode , bool has_vex_w ) { int i ; if ( ! has_0f_opcode || has_vex_w ) return 3 + 1 ; if ( ! TARGET_64BIT ) return 2 + 1 ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( REG_P ( recog_data . operand [ i ] ) ) { if ( GET_MODE ( recog_data . operand [ i ] ) == DImode && GENERAL_REG_P ( recog_data . operand [ i ] ) ) return 3 + 1 ; } else { if ( MEM_P ( recog_data . operand [ i ] ) && x86_extended_reg_mentioned_p ( recog_data . operand [ i ] ) ) return 3 + 1 ; } return 2 + 1 ; } </s>

Compute default value for `` length_vex '' attribute . It includes 2 or 3 byte VEX prefix and 1 opcode byte .


<s> static bool insn_true_dependent_p ( rtx x , rtx y ) { rtx tmp ; if ( ! INSN_P ( x ) || ! INSN_P ( y ) ) return 0 ; tmp = PATTERN ( y ) ; note_stores ( PATTERN ( x ) , insn_dependent_p_1 , & tmp ) ; return ( tmp == NULL_RTX ) ; } </s>

Return true if anything in insn X is true dependent on anything in insn Y .


<s>
bool
MipsConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
4
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

Mips
Mips
4
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> const LanaiInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_SaveList : CSR_SVR32_ColdCC_SaveList ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC PPC


<s> bool LC3RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


"Mandarin DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void ix86_split_mmx_pack ( rtx operands [ ] , enum rtx_code code ) { rtx op0 = operands [ 0 ] ; rtx op1 = operands [ 1 ] ; rtx op2 = operands [ 2 ] ; machine_mode dmode = GET_MODE ( op0 ) ; machine_mode smode = GET_MODE ( op1 ) ; machine_mode inner_dmode = GET_MODE_INNER ( dmode ) ; machine_mode inner_smode = GET_MODE_INNER ( smode ) ; int nunits = 16 / GET_MODE_SIZE ( inner_dmode ) ; machine_mode sse_dmode = mode_for_vector ( GET_MODE_INNER ( dmode ) , nunits ) . require ( ) ; machine_mode sse_half_dmode = mode_for_vector ( GET_MODE_INNER ( dmode ) , nunits / 2 ) . require ( ) ; nunits = 16 / GET_MODE_SIZE ( inner_smode ) ; machine_mode sse_smode = mode_for_vector ( GET_MODE_INNER ( smode ) , nunits ) . require ( ) ; rtx dest = lowpart_subreg ( sse_dmode , op0 , GET_MODE ( op0 ) ) ; op1 = lowpart_subreg ( sse_smode , op1 , GET_MODE ( op1 ) ) ; op2 = lowpart_subreg ( sse_smode , op2 , GET_MODE ( op2 ) ) ; op1 = gen_rtx_fmt_e ( code , sse_half_dmode , op1 ) ; op2 = gen_rtx_fmt_e ( code , sse_half_dmode , op2 ) ; rtx insn = gen_rtx_SET ( dest , gen_rtx_VEC_CONCAT ( sse_dmode , op1 , op2 ) ) ; emit_insn ( insn ) ; ix86_move_vector_high_sse_to_mmx ( op0 ) ; } </s>

Split MMX pack with signed/unsigned saturation with SSE/SSE2 .


<s> unsigned MipsRegisterInfo :: getPICCallReg ( ) { return Mips :: T9 ; } </s>


<s> static void union_defs ( swap_web_entry * insn_entry , rtx insn , df_ref use ) { struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( def_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing definitions that reach USE . Detect whether USE is live-in to the current function .


<s>
void
emit_safe_across_calls
(
void
)
{
unsigned
int
rs
,
re
;
int
out_state
;
rs
=
1
;
out_state
=
0
;
while
(
1
)
{
while
(
rs
<
64
&&
call_used_regs
[
PR_REG
(
rs
)
]
)
rs
++
;
if
(
rs
>=
64
)
break
;
for
(
re
=
rs
+
1
;
re
<
64
&&
!
call_used_regs
[
PR_REG
(
re
)
]
;
re
++
)
continue
;
if
(
out_state
==
0
)
{
fputs
(
"\t.pred.safe_across_calls "
,
asm_out_file
)
;
out_state
=
1
;
}
else
fputc
(
','
,
asm_out_file
)
;
if
(
re
==
rs
+
1
)
fprintf
(
asm_out_file
,
"p%u"
,
rs
)
;
else
fprintf
(
asm_out_file
,
"p%u-p%u"
,
rs
,
re
1
)
;
rs
=
re
+
1
;
}
if
(
out_state
)
fputc
(
'\n'
,
asm_out_file
)
;
}
</s>


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
if
(
!
Value
)
return
;
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Kind
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
AArch64MCExpr
::
VariantKind
RefKind
=
static_cast
<
AArch64MCExpr
::
VariantKind
>
(
Target
.
getRefKind
(
)
)
;
if
(
AArch64MCExpr
::
getSymbolLoc
(
RefKind
)
==
AArch64MCExpr
::
VK_SABS
||
(
!
RefKind
&&
Fixup
.
getTargetKind
(
)
==
AArch64
::
fixup_aarch64_movw
)
)
{
if
(
SignedValue
<
0
)
Data
[
Offset
+
3
]
&=
~
(
1
<<
6
)
;
else
Data
[
Offset
+
3
]
|=
(
1
<<
6
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
addInst
(
MachineInstr
*
MI
,
SetVector
<
MachineInstr
*
>
&
Preds
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops: Adding predicated MI: "
<<
*
MI
)
;
if
(
!
Divergent
&&
!
set_difference
(
Preds
,
PredicateThen
->
Predicates
)
.
empty
(
)
)
{
Divergent
=
&
Insts
.
back
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" - has divergent predicate: "
<<
*
Divergent
->
MI
)
;
}
Insts
.
emplace_back
(
MI
,
Preds
)
;
assert
(
Insts
.
size
(
)
<=
4
&&
"Too many instructions in VPT block!"
)
;
}
</s>

ARM
"ARM Loops: Adding predicated MI: "
" - has divergent predicate: "
4
"Too many instructions in VPT block!"


<s> SDValue PPCTargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; return DAG . getNode ( PPCISD :: FRE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
bool
VETargetLowering
::
CanLowerReturn
(
CallingConv
::
ID
CallConv
,
MachineFunction
&
MF
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
LLVMContext
&
Context
)
const
{
assert
(
!
IsVarArg
&&
"TODO implement var args"
)
;
assert
(
Outs
.
empty
(
)
&&
"TODO implement return values"
)
;
return
true
;
}
</s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

VE
VE
ISD::OutputArg
"TODO implement var args"
"TODO implement return values"


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void rs6000_conditional_register_usage ( void ) { int i ; if ( ! TARGET_POWER ) fixed_regs [ 64 ] = 1 ; if ( TARGET_64BIT ) fixed_regs [ 13 ] = call_used_regs [ 13 ] = call_really_used_regs [ 13 ] = 1 ; if ( TARGET_SOFT_FLOAT || ! TARGET_FPRS ) for ( i = 32 ; i < 64 ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = call_really_used_regs [ i ] = 1 ; if ( DEFAULT_ABI == ABI_AIX ) call_really_used_regs [ 2 ] = 0 ; if ( DEFAULT_ABI == ABI_V4 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM && flag_pic == 2 ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( DEFAULT_ABI == ABI_V4 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM && flag_pic == 1 ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_really_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( DEFAULT_ABI == ABI_DARWIN && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_really_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( TARGET_TOC && TARGET_MINIMAL_TOC ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; if ( TARGET_ALTIVEC ) global_regs [ VSCR_REGNO ] = 1 ; if ( TARGET_SPE ) { global_regs [ SPEFSCR_REGNO ] = 1 ; fixed_regs [ FIXED_SCRATCH ] = call_used_regs [ FIXED_SCRATCH ] = call_really_used_regs [ FIXED_SCRATCH ] = 1 ; } if ( ! TARGET_ALTIVEC ) { for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ] = call_really_used_regs [ i ] = 1 ; call_really_used_regs [ VRSAVE_REGNO ] = 1 ; } if ( TARGET_ALTIVEC_ABI ) for ( i = FIRST_ALTIVEC_REGNO ; i < FIRST_ALTIVEC_REGNO + 20 ; ++ i ) call_used_regs [ i ] = call_really_used_regs [ i ] = 1 ; } </s>

Change register usage conditional on target flags .


<s> static opt_machine_mode ix86_get_mask_mode ( machine_mode data_mode ) { unsigned vector_size = GET_MODE_SIZE ( data_mode ) ; unsigned nunits = GET_MODE_NUNITS ( data_mode ) ; unsigned elem_size = vector_size / nunits ; if ( ( TARGET_AVX512F && vector_size == 64 ) || ( TARGET_AVX512VL && ( vector_size == 32 || vector_size == 16 ) ) ) { if ( elem_size == 4 || elem_size == 8 || ( TARGET_AVX512BW && ( elem_size == 1 || elem_size == 2 ) ) ) return smallest_int_mode_for_size ( nunits ) ; } scalar_int_mode elem_mode = smallest_int_mode_for_size ( elem_size * BITS_PER_UNIT ) ; gcc_assert ( elem_size * nunits == vector_size ) ; return mode_for_vector ( elem_mode , nunits ) ; } </s>

Implemenation of targetm.vectorize.get_mask_mode .


<s> TargetLowering :: ConstraintWeight ARMTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; const Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'l' : if ( type -> isIntegerTy ( ) ) { if ( Subtarget -> isThumb ( ) ) weight = CW_SpecificReg ; else weight = CW_Register ; } break ; case 'w' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void MipsELFStreamer :: emitIntValue ( uint64_t Value , unsigned Size ) { MCELFStreamer :: emitIntValue ( Value , Size ) ; Labels . clear ( ) ; } </s>

Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers .


<s> unsigned PPCRegisterInfo :: getRARegister ( ) const { return ! Subtarget . isPPC64 ( ) ? PPC :: LR : PPC :: LR8 ; } </s>

This method should return the register where the return address can be found .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI . mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> static unsigned int swap_feeds_both_load_and_store ( swap_web_entry * insn_entry ) { rtx insn = insn_entry -> insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref def , use ; struct df_link * link = 0 ; rtx_insn * load = 0 , * store = 0 ; bool fed_by_load = 0 ; bool feeds_store = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { link = DF_REF_CHAIN ( use ) ; load = DF_REF_INSN ( link -> ref ) ; if ( insn_is_load_p ( load ) && insn_is_swap_p ( load ) ) fed_by_load = 1 ; } FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { link = DF_REF_CHAIN ( def ) ; store = DF_REF_INSN ( link -> ref ) ; if ( insn_is_store_p ( store ) && insn_is_swap_p ( store ) ) feeds_store = 1 ; } return fed_by_load && feeds_store ; } </s>

Return 1 iff UID , known to reference a swap , is both fed by a load and a feeder of a store .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; if ( UseStackSafety ) AU . addRequired < StackSafetyGlobalInfoWrapperPass > ( ) ; if ( MergeInit ) AU . addRequired < AAResultsWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx safe_vector_operand ( rtx x , machine_mode mode ) { if ( x == const0_rtx ) x = CONST0_RTX ( mode ) ; return x ; } </s>

Errors in the source file can cause expand_expr to return const0_rtx where we expect a vector . To avoid crashing , use one of the vector clear instructions .


<s> int X86InstrInfo :: getSPAdjust ( const MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( MI -> getOpcode ( ) == getCallFrameSetupOpcode ( ) || MI -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { unsigned StackAlign = TFI -> getStackAlignment ( ) ; int SPAdj = ( MI -> getOperand ( 0 ) . getImm ( ) + StackAlign - 1 ) / StackAlign * StackAlign ; SPAdj -= MI -> getOperand ( 1 ) . getImm ( ) ; if ( MI -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) return SPAdj ; else return - SPAdj ; } if ( MI -> isCall ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return 0 ; return - ( I -> getOperand ( 1 ) . getImm ( ) ) ; } switch ( MI -> getOpcode ( ) ) { default : return 0 ; case X86 :: PUSH32i8 : case X86 :: PUSH32r : case X86 :: PUSH32rmm : case X86 :: PUSH32rmr : case X86 :: PUSHi32 : return 4 ; case X86 :: PUSH64i8 : case X86 :: PUSH64r : case X86 :: PUSH64rmm : case X86 :: PUSH64rmr : case X86 :: PUSH64i32 : return 8 ; } } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


<s> static bool mep_assign_save_slots ( int reg_save_size ) { bool really_need_stack_frame = false ; int di_ofs = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( mep_call_saves_register ( i ) ) { int regsize = mep_reg_size ( i ) ; if ( ( i != TP_REGNO && i != GP_REGNO && i != LP_REGNO ) || mep_reg_set_in_function ( i ) ) really_need_stack_frame = true ; if ( cfun -> machine -> reg_save_slot [ i ] ) continue ; if ( regsize < 8 ) { cfun -> machine -> reg_save_size += regsize ; cfun -> machine -> reg_save_slot [ i ] = cfun -> machine -> reg_save_size ; } else { cfun -> machine -> reg_save_slot [ i ] = reg_save_size - di_ofs ; di_ofs += 8 ; } } cfun -> machine -> frame_locked = 1 ; return really_need_stack_frame ; } </s>

Assign save slots for any register not already saved . DImode registers go at the end of the reg save area ; the rest go at the beginning . This is for alignment purposes . Returns true if a frame is really needed .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM -> getSubtargetImpl ( ) -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM 0 ARM ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> bool SparcPassConfig :: addPreEmitPass ( ) { PM . add ( createSparcFPMoverPass ( getSparcTargetMachine ( ) ) ) ; PM . add ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void MMIXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerMMIXMachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>


<s>
int
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
Type
*
ValTy
,
bool
IsPairwiseForm
)
{
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s> static void ix86_emit_leave ( void ) { struct machine_function * m = cfun -> machine ; rtx_insn * insn = emit_insn ( ix86_gen_leave ( ) ) ; ix86_add_queued_cfa_restore_notes ( insn ) ; gcc_assert ( m -> fs . fp_valid ) ; m -> fs . sp_valid = true ; m -> fs . sp_offset = m -> fs . fp_offset - UNITS_PER_WORD ; m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset ) ; } </s>

Emit code and notes for the LEAVE instruction .


"64-bit code requested on a subtarget that doesn't "

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool AArch64ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; auto UniqueRS = make_unique < RegScavenger > ( ) ; RS = UniqueRS . get ( ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>


<s> unsigned OptimizePICCall :: getReg ( const Value * Entry ) { unsigned Reg = ScopedHT . lookup ( Entry ) . second ; assert ( Reg ) ; return Reg ; } </s>

Returns the register associated with this edge .


"saturation bit range must be in the range [%wd, %wd]"

"saturation bit range must be a constant immediate"

Expand an ACLE builtin , i.e . those registered only if their respective target constraints are met . This check happens within arm_expand_builtin_args .


<s> static bool scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( GET_MODE ( src ) != DImode || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case PLUS : case MINUS : case IOR : case XOR : case AND : break ; case REG : return true ; case MEM : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ) ) return false ; if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 0 ) ) != DImode || GET_MODE ( XEXP ( src , 1 ) ) != DImode ) return false ; return true ; } </s>

Return 1 if INSN may be converted into vector instruction .


<s>
void
ARMConstantIslands
::
verify
(
)
{
BBInfoVector
&
BBInfo
=
BBUtils
->
getBBInfo
(
)
;
assert
(
is_sorted
(
*
MF
,
[
&
BBInfo
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> bool MipsTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createMipsISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> static unsigned int get_csky_live_regs ( int * count ) { int reg ; unsigned int live_regs_mask = 0 ; * count = 0 ; for ( reg = 0 ; reg < CSKY_NGPR_REGS ; reg ++ ) { bool save = false ; if ( CSKY_TARGET_ARCH ( CK801 ) && reg > 8 && reg < 13 ) continue ; if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) ) && reg > 15 ) break ; if ( df_regs_ever_live_p ( reg ) && ! call_really_used_regs [ reg ] ) save = true ; else if ( frame_pointer_needed && reg == FRAME_POINTER_REGNUM ) save = true ; else if ( crtl -> calls_eh_return && reg == FRAME_POINTER_REGNUM ) save = true ; else if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) && reg == CSKY_LR_REGNUM && ( ! crtl -> is_leaf || csky_far_jump_used_p ( ) ) ) save = true ; else if ( crtl -> calls_eh_return && reg >= CSKY_FIRST_EH_RETDATA_REGNUM && reg <= CSKY_LAST_EH_RETDATA_REGNUM ) save = true ; if ( reg == CSKY_STACKADJUST_REGNUM && cfun -> machine -> reg_offset > CSKY_MAX_SP_ADJUST * 2 ) save = true ; if ( save ) { ( * count ) ++ ; live_regs_mask |= ( 1 << reg ) ; } } return live_regs_mask ; } </s>

Return the mask of registers used by the current function . Set COUNT to the number of registers used .


<s> const SICMCExpr * SICMCExpr :: create ( const MCSymbol * Symbol , SICMCExpr :: SICExprKind Kind , MCContext & Ctx ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; return new ( Ctx ) SICMCExpr ( Kind , MCSym ) ; } </s>


<s> static void do_load_for_compare ( rtx reg , rtx mem , machine_mode mode ) { switch ( GET_MODE ( reg ) ) { case E_DImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case E_SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case E_DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_SImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case E_SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case E_DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Figure out the correct instructions to generate to load data for block compare . MODE is used for the read from memory , and data is zero extended if REG is wider than MODE . If LE code is being generated , bswap loads are used . REG is the destination register to move the data into . MEM is the memory block being read . MODE is the mode of memory to use for the read .


<s> int fpuv3_const_double_rtx ( rtx x ) { REAL_VALUE_TYPE r , m ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) || r . cl == rvc_zero ) return 0 ; int exponent ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; bool fail ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; exponent -= 1 ; if ( ! IN_RANGE ( exponent , - 4 , 11 ) ) return 0 ; if ( mantissa != 0 ) return 0 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 9 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return 0 ; return 1 ; } </s>

Check if a const_double can be used by a VFP fmovi instruction .


On AArch64 we have an ABI defined safe buffer . This constant is used to determining the probe offset for alloca .


<s> static bool iv_p ( rtx_insn * insn , rtx reg , struct loop * loop ) { df_ref ause ; unsigned regno = REGNO ( reg ) ; if ( regno == SP_REGNUM ) return false ; for ( ause = DF_REG_USE_CHAIN ( regno ) ; ause ; ause = DF_REF_NEXT_REG ( ause ) ) { if ( ! DF_REF_INSN_INFO ( ause ) || ! NONDEBUG_INSN_P ( DF_REF_INSN ( ause ) ) ) continue ; if ( insn != DF_REF_INSN ( ause ) ) continue ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref def_rec ; FOR_EACH_INSN_INFO_DEF ( def_rec , insn_info ) { rtx_insn * insn = DF_REF_INSN ( def_rec ) ; basic_block bb = BLOCK_FOR_INSN ( insn ) ; if ( dominated_by_p ( CDI_DOMINATORS , bb , loop -> header ) && bb -> loop_father == loop ) { if ( recog_memoized ( insn ) < 0 ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; rtx x = SET_SRC ( pat ) ; if ( GET_CODE ( x ) == ZERO_EXTRACT || GET_CODE ( x ) == ZERO_EXTEND || GET_CODE ( x ) == SIGN_EXTEND ) x = XEXP ( x , 0 ) ; if ( MEM_P ( x ) ) continue ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) return true ; else if ( BINARY_P ( x ) && ( CONST_INT_P ( XEXP ( x , 0 ) ) || CONST_INT_P ( XEXP ( x , 1 ) ) ) ) { rtx stride = ( CONST_INT_P ( XEXP ( x , 0 ) ) ? XEXP ( x , 0 ) : XEXP ( x , 1 ) ) ; if ( INTVAL ( stride ) < MAX_PREFETCH_STRIDE ) return true ; } } } return false ; } return false ; } </s>

Find the use def chain in which INSN exists and then see if there is a definition inside the loop and outside it . We use this as a simple approximation to determine whether the base register is an IV . The basic idea is to find INSN in the use-def chains for its base register and find all definitions that reach it . Of all these definitions , there should be at least one definition that is a simple addition of a constant value , either as a binary operation or a pre or post update . The function returns true if the base register is estimated to be an IV .


<s> unsigned PPCTTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC || ClassID == VSXRC ) ; if ( ST -> hasVSX ( ) ) { assert ( ClassID == GPRRC || ClassID == VSXRC ) ; return ClassID == GPRRC ? 32 : 64 ; } assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC ) ; return 32 ; } </s>


<s> unsigned getRsaSize ( void ) const { return 176 ; } </s>

Get the size of RSA , return address , and frame pointer as described in VEFrameLowering.cpp .


<s> void nds32_expand_epilogue_v3pop ( bool sibcall_p ) { int sp_adjust ; unsigned Rb , Re ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( ! sibcall_p ) { if ( cfun -> machine -> attr_naked_p && ! flag_ret_in_naked_func ) return ; emit_jump_insn ( gen_return_internal ( ) ) ; } return ; } Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_position = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_v3pop_fpr_callee_saved ( fpr_position ) ; } nds32_emit_stack_v3pop ( Rb , Re , sp_adjust ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - 1 * sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( 0 ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - 1 * sp_adjust ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - cfun -> machine -> callee_saved_area_gpr_padding_bytes - cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( 0 ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_stack_v3pop ( Rb , Re , fpr_space ) ; } else { nds32_emit_stack_v3pop ( Rb , Re , 0 ) ; } } emit_jump_insn ( gen_pop25return ( ) ) ; } </s>


<s> static int csky_sched_issue_rate ( void ) { if ( CSKY_TARGET_ARCH ( CK810 ) ) return 2 ; else return 1 ; } </s>

Implement TARGET_SCHED_ISSUE_RATE . Lookup the issue rate in the per-core tuning structs .


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> void rs6000_split_signbit ( rtx dest , rtx src ) { machine_mode d_mode = GET_MODE ( dest ) ; machine_mode s_mode = GET_MODE ( src ) ; rtx dest_di = ( d_mode == DImode ) ? dest : gen_lowpart ( DImode , dest ) ; rtx shift_reg = dest_di ; gcc_assert ( FLOAT128_IEEE_P ( s_mode ) && TARGET_POWERPC64 ) ; if ( MEM_P ( src ) ) { rtx mem = ( WORDS_BIG_ENDIAN ? adjust_address ( src , DImode , 0 ) : adjust_address ( src , DImode , 8 ) ) ; emit_insn ( gen_rtx_SET ( dest_di , mem ) ) ; } else { unsigned int r = reg_or_subregno ( src ) ; if ( INT_REGNO_P ( r ) ) shift_reg = gen_rtx_REG ( DImode , r + ( BYTES_BIG_ENDIAN == 0 ) ) ; else { gcc_assert ( VSX_REGNO_P ( r ) ) ; if ( s_mode == KFmode ) emit_insn ( gen_signbitkf2_dm2 ( dest_di , src ) ) ; else emit_insn ( gen_signbittf2_dm2 ( dest_di , src ) ) ; } } emit_insn ( gen_lshrdi3 ( dest_di , shift_reg , GEN_INT ( 63 ) ) ) ; return ; } </s>

Split a signbit operation on 64-bit machines with direct move . Also allow for the value to come from memory or if it is already loaded into a GPR .


<s> static unsigned int rest_of_insert_endbranch ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx cet_eb ; rtx_insn * insn ; basic_block bb ; if ( ! lookup_attribute ( "nocf_check" , TYPE_ATTRIBUTES ( TREE_TYPE ( cfun -> decl ) ) ) && ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { cet_eb = gen_nop_endbr ( ) ; bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; emit_insn_before ( cet_eb , insn ) ; } bb = 0 ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( CALL_P ( insn ) ) { if ( find_reg_note ( insn , REG_SETJMP , NULL ) == NULL ) continue ; cet_eb = gen_nop_endbr ( ) ; emit_insn_after_setloc ( cet_eb , insn , INSN_LOCATION ( insn ) ) ; continue ; } if ( JUMP_P ( insn ) && flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) continue ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table ) ) continue ; edge_iterator ei ; edge e ; basic_block dest_blk ; FOR_EACH_EDGE ( e , ei , bb -> succs ) { rtx_insn * insn ; dest_blk = e -> dest ; insn = BB_HEAD ( dest_blk ) ; gcc_assert ( LABEL_P ( insn ) ) ; cet_eb = gen_nop_endbr ( ) ; emit_insn_after ( cet_eb , insn ) ; } continue ; } if ( ( LABEL_P ( insn ) && LABEL_PRESERVE_P ( insn ) ) || ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_DELETED_LABEL ) ) { cet_eb = gen_nop_endbr ( ) ; emit_insn_after ( cet_eb , insn ) ; continue ; } } } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>


<s> rtx expand ( function_expander & e ) const OVERRIDE { return e . use_exact_insn ( CODE_FOR_aarch64_wrffr ) ; } </s>


<s> static void aarch64_emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx_insn * jump = emit_jump_insn ( insn ) ; add_int_reg_note ( jump , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , bool IsTailCall ) const { if ( IsTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: B ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return It ; } </s>

Insert a call to an outlined function into the program .


<s>
bool
AArch64InstrInfo
::
isGPRCopy
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
Register
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
GPR32RegClass
.
contains
(
DstReg
)
||
AArch64
::
GPR64RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRXrs
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ORRrs operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ADDXri
:
if
(
MI
.
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ADDXri operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename a GPR without modifying bits ?


<s> static short find_insn_regmode_weight ( rtx insn , machine_mode mode ) { rtx x = PATTERN ( insn ) ; short reg_weight = find_set_regmode_weight ( x , mode ) ; if ( GET_CODE ( x ) == PARALLEL ) { int j ; for ( j = XVECLEN ( x , 0 ) - 1 ; j >= 0 ; j -- ) { x = XVECEXP ( PATTERN ( insn ) , 0 , j ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; } } for ( x = REG_NOTES ( insn ) ; x ; x = XEXP ( x , 1 ) ) { if ( REG_NOTE_KIND ( x ) == REG_DEAD || REG_NOTE_KIND ( x ) == REG_UNUSED ) { rtx note = XEXP ( x , 0 ) ; if ( REG_P ( note ) && GET_MODE ( note ) == mode ) reg_weight -- ; } } return reg_weight ; } </s>


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; ARMGISelActualAccessor * GISel = new ARMGISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new ARMCallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new ARMLegalizerInfo ( ) ) ; auto * RBI = new ARMRegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( new ARMInstructionSelector ( * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM ARM ARM ARM ARM ARM ARM


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool PPCFunctionInfo :: isLiveInSExt ( unsigned VReg ) const { for ( const std :: pair < unsigned , ISD :: ArgFlagsTy > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isSExt ( ) ; return false ; } </s>

This function returns true if the specified vreg is a live-in register and sign-extended .


<s> bool MipsRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; unsigned FP = Subtarget . isGP32bit ( ) ? Mips :: FP : Mips :: FP_64 ; unsigned BP = Subtarget . isGP32bit ( ) ? Mips :: S7 : Mips :: S7_64 ; if ( Subtarget . inMips16Mode ( ) ) return false ; if ( ! MF . getRegInfo ( ) . canReserveReg ( FP ) ) return false ; if ( Subtarget . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MF . getRegInfo ( ) . canReserveReg ( BP ) ; } </s>

True if the stack can be realigned for the target .

Mips Mips Mips Mips Mips::FP Mips::FP_64 Mips::S7 Mips::S7_64 Mips


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned int rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; if ( TYPE_PACKED ( type ) || align >= 64 ) return align ; do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node && ( TYPE_MODE ( type ) == DFmode || TYPE_MODE ( type ) == DCmode ) ) align = MAX ( align , 64 ) ; return align ; } </s>

Darwin , AIX increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
void
SystemZTargetLowering
::
LowerOperationWrapper
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
ATOMIC_LOAD
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Untyped
,
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
N
->
getOperand
(
1
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_LOAD_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
Results
.
push_back
(
lowerGR128ToI128
(
DAG
,
Res
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
break
;
}
case
ISD
::
ATOMIC_STORE
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
2
)
)
,
N
->
getOperand
(
1
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_STORE_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
if
(
cast
<
AtomicSDNode
>
(
N
)
->
getOrdering
(
)
==
AtomicOrdering
::
SequentiallyConsistent
)
Res
=
SDValue
(
DAG
.
getMachineNode
(
SystemZ
::
Serialize
,
DL
,
MVT
::
Other
,
Res
)
,
0
)
;
Results
.
push_back
(
Res
)
;
break
;
}
case
ISD
::
ATOMIC_CMP_SWAP_WITH_SUCCESS
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Untyped
,
MVT
::
Other
,
MVT
::
Glue
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
N
->
getOperand
(
1
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
2
)
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
3
)
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_CMP_SWAP_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
SDValue
Success
=
emitSETCC
(
DAG
,
DL
,
Res
.
getValue
(
2
)
,
SystemZ
::
CCMASK_CS
,
SystemZ
::
CCMASK_CS_EQ
)
;
Success
=
DAG
.
getZExtOrTrunc
(
Success
,
DL
,
N
->
getValueType
(
1
)
)
;
Results
.
push_back
(
lowerGR128ToI128
(
DAG
,
Res
)
)
;
Results
.
push_back
(
Success
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
break
;
}
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> void aarch64_split_combinev16qi ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = REG_NREGS ( operands [ 1 ] ) ; rtx destlo , desthi ; gcc_assert ( halfmode == V16QImode ) ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) && reg_overlap_mentioned_p ( operands [ 1 ] , desthi ) ) { emit_insn ( gen_xorv16qi3 ( operands [ 1 ] , operands [ 1 ] , operands [ 2 ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ 2 ] , operands [ 1 ] , operands [ 2 ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ 1 ] , operands [ 1 ] , operands [ 2 ] ) ) ; } else if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


"getInstSizeInBytes()- Unable to determin insn size"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s>
static
void
moxie_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\tpush  $sp, $r0\n"
)
;
fprintf
(
f
,
"\tldi.l $r0, 0x0\n"
)
;
fprintf
(
f
,
"\tsto.l 0x8($fp), $r0\n"
)
;
fprintf
(
f
,
"\tpop   $sp, $r0\n"
)
;
fprintf
(
f
,
"\tjmpa  0x0\n"
)
;
}
</s>

Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE .

moxie
"\tpush  $sp, $r0\n"
"\tldi.l $r0, 0x0\n"
"\tsto.l 0x8($fp), $r0\n"
"\tpop   $sp, $r0\n"
"\tjmpa  0x0\n"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned PPCTTI :: getNumberOfRegisters ( bool Vector ) const { if ( Vector && ! ST -> hasAltivec ( ) ) return 0 ; return 32 ; } </s>


<s> EVT MipsTargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static void ix86_emit_restore_reg_using_pop ( rtx reg ) { struct machine_function * m = cfun -> machine ; rtx_insn * insn = emit_insn ( gen_pop ( reg ) ) ; ix86_add_cfa_restore_note ( insn , reg , m -> fs . sp_offset ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; if ( m -> fs . cfa_reg == crtl -> drap_reg && REGNO ( reg ) == REGNO ( crtl -> drap_reg ) ) { add_reg_note ( insn , REG_CFA_DEF_CFA , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . drap_valid = true ; return ; } if ( m -> fs . cfa_reg == stack_pointer_rtx ) { rtx x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . cfa_offset -= UNITS_PER_WORD ; } if ( reg == hard_frame_pointer_rtx ) { m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset -= UNITS_PER_WORD ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . cfa_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } </s>

Emit code to restore REG using a POP insn .


<s> int csky_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( 4 + memory_move_secondary_cost ( mode , rclass , in ) ) ; } </s>

Implement TARGET_MEMORY_MOVE_COST : compute the cost of moving data between registers and memory .


<s> static void loongarch_print_operand_reloc ( FILE * file , rtx op , bool hi64_part , bool hi_reloc ) { const char * reloc ; enum loongarch_symbol_type symbol_type = loongarch_classify_symbolic_expression ( op ) ; if ( loongarch_symbol_extreme_p ( symbol_type ) ) gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; switch ( symbol_type ) { case SYMBOL_PCREL64 : if ( hi64_part ) { reloc = hi_reloc ? "%pc64_hi12" : "%pc64_lo20" ; break ; } case SYMBOL_PCREL : reloc = hi_reloc ? "%pc_hi20" : "%pc_lo12" ; break ; case SYMBOL_GOT_DISP : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%got64_pc_hi12" : "%got64_pc_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%got_pc_hi20" : "%got_pc_lo12" ; break ; case SYMBOL_TLS_IE : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%ie64_pc_hi12" : "%ie64_pc_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%ie_pc_hi20" : "%ie_pc_lo12" ; break ; case SYMBOL_TLS_LE : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%le64_hi12" : "%le64_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%le_hi20" : "%le_lo12" ; break ; case SYMBOL_TLSGD : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%got64_pc_hi12" : "%got64_pc_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%gd_pc_hi20" : "%got_pc_lo12" ; break ; case SYMBOL_TLSLDM : if ( hi64_part ) { if ( TARGET_CMODEL_EXTREME ) reloc = hi_reloc ? "%got64_pc_hi12" : "%got64_pc_lo20" ; else gcc_unreachable ( ) ; } else reloc = hi_reloc ? "%ld_pc_hi20" : "%got_pc_lo12" ; break ; default : gcc_unreachable ( ) ; } fprintf ( file , "%s(" , reloc ) ; output_addr_const ( file , loongarch_strip_unspec_address ( op ) ) ; fputc ( ')' , file ) ; } </s>

Print symbolic operand OP , which is part of a HIGH or LO_SUM in context CONTEXT . HI_RELOC indicates a high-part reloc .


<s> TargetPassConfig * CJGTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new CJGPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ 2 ] ) { if ( reload_in_progress ) return ; if ( GET_CODE ( operands [ 0 ] ) == MEM && GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 0 ] , 0 ) , GET_MODE ( operands [ 0 ] ) , false ) ) operands [ 0 ] = replace_equiv_address ( operands [ 0 ] , copy_addr_to_reg ( XEXP ( operands [ 0 ] , 0 ) ) ) ; if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_CODE ( XEXP ( operands [ 1 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 1 ] , 0 ) , GET_MODE ( operands [ 1 ] ) , false ) ) operands [ 1 ] = replace_equiv_address ( operands [ 1 ] , copy_addr_to_reg ( XEXP ( operands [ 1 ] , 0 ) ) ) ; } </s>

Helper for the following . Get rid of [ r+r ] memory refs in cases where it wo n't work ( TImode , TFmode ) .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0


<s> static rtvec rs6000_const_vec ( machine_mode mode ) { int i , subparts ; rtvec v ; switch ( mode ) { case E_V1TImode : subparts = 1 ; break ; case E_V2DFmode : case E_V2DImode : subparts = 2 ; break ; case E_V4SFmode : case E_V4SImode : subparts = 4 ; break ; case E_V8HImode : subparts = 8 ; break ; case E_V16QImode : subparts = 16 ; break ; default : gcc_unreachable ( ) ; } v = rtvec_alloc ( subparts ) ; for ( i = 0 ; i < subparts / 2 ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i + subparts / 2 ) ; for ( i = subparts / 2 ; i < subparts ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i - subparts / 2 ) ; return v ; } </s>

Generate a vector of constants to permute MODE for a little-endian storage operation by swapping the two halves of a vector .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws"


<s> void MandarinRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MD :: R31 : MD :: R30 ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; unsigned VReg = BasePtr ; if ( Offset ) { VReg = RegInfo . createVirtualRegister ( & MD :: GenericRegsRegClass ) ; if ( Offset > 0 ) BuildMI ( MBB , II , dl , TII . get ( MD :: ADDri ) , VReg ) . addReg ( BasePtr ) . addImm ( Offset ) ; else BuildMI ( MBB , II , dl , TII . get ( MD :: SUBri ) , VReg ) . addReg ( BasePtr ) . addImm ( Offset ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VReg , false ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) <= 32 ) return std :: make_pair ( 0U , & AArch64 :: GPR32RegClass ) ; else if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64RegClass ) ; break ; case 'w' : if ( VT == MVT :: f16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; else if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; else if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; else if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: VPR64RegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; else if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: VPR128RegClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> tree ix86_builtin_reciprocal ( tree fndecl ) { enum ix86_builtins fn_code = ( enum ix86_builtins ) DECL_MD_FUNCTION_CODE ( fndecl ) ; switch ( fn_code ) { case IX86_BUILTIN_SQRTPS_NR : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR ) ; case IX86_BUILTIN_SQRTPS_NR256 : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR256 ) ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> static bool classof ( const MCStreamer * S ) { return S -> getKind ( ) == SK_ARMELFStreamer ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :