<s> void AArch64PostLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static opt_scalar_float_mode rs6000_floatn_mode ( int n , bool extended ) { if ( extended ) { switch ( n ) { case 32 : return DFmode ; case 64 : if ( TARGET_FLOAT128_TYPE ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return opt_scalar_float_mode ( ) ; case 128 : return opt_scalar_float_mode ( ) ; default : gcc_unreachable ( ) ; } } else { switch ( n ) { case 32 : return SFmode ; case 64 : return DFmode ; case 128 : if ( TARGET_FLOAT128_TYPE ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return opt_scalar_float_mode ( ) ; default : return opt_scalar_float_mode ( ) ; } } } </s>


<s> bool AArch64FastISel :: optimizeSelect ( const SelectInst * SI ) { if ( ! SI -> getType ( ) -> isIntegerTy ( 1 ) ) return false ; const Value * Src1Val , * Src2Val ; unsigned Opc = 0 ; bool NeedExtraOp = false ; if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getTrueValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getFalseValue ( ) ; Opc = AArch64 :: ORRWrr ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getFalseValue ( ) ; Src2Val = SI -> getCondition ( ) ; Opc = AArch64 :: BICWrr ; } } else if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getFalseValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ORRWrr ; NeedExtraOp = true ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ANDWrr ; } } if ( ! Opc ) return false ; unsigned Src1Reg = getRegForValue ( Src1Val ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( Src1Val ) ; unsigned Src2Reg = getRegForValue ( Src2Val ) ; if ( ! Src2Reg ) return false ; bool Src2IsKill = hasTrivialKill ( Src2Val ) ; if ( NeedExtraOp ) { Src1Reg = emitLogicalOp_ri ( ISD :: XOR , MVT :: i32 , Src1Reg , Src1IsKill , 1 ) ; Src1IsKill = true ; } unsigned ResultReg = fastEmitInst_rr ( Opc , & AArch64 :: GPR32RegClass , Src1Reg , Src1IsKill , Src2Reg , Src2IsKill ) ; updateValueMap ( SI , ResultReg ) ; return true ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool isLegalNTStore ( Type * DataType , Align Alignment ) { if ( auto * DataTypeVTy = dyn_cast < VectorType > ( DataType ) ) { unsigned NumElements = cast < FixedVectorType > ( DataTypeVTy ) -> getNumElements ( ) ; unsigned EltSize = DataTypeVTy -> getElementType ( ) -> getScalarSizeInBits ( ) ; return NumElements > 1 && isPowerOf2_64 ( NumElements ) && EltSize >= 8 && EltSize <= 128 && isPowerOf2_64 ( EltSize ) ; } return BaseT :: isLegalNTStore ( DataType , Alignment ) ; } </s>

Return true if the target supports nontemporal store .


<s> HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function ) { HOST_WIDE_INT frame_size , apparent_frame_size ; int args_size , n_global_fp_regs = 0 ; bool save_local_in_regs_p = false ; unsigned int i ; if ( leaf_function && ! cfun -> calls_alloca ) args_size = 0 ; else args_size = crtl -> outgoing_args_size + REG_PARM_STACK_SPACE ( cfun -> decl ) ; if ( TARGET_ARCH64 ) for ( i = 0 ; i < 8 ; i ++ ) if ( save_global_or_fp_reg_p ( i , 0 ) ) n_global_fp_regs += 2 ; else for ( i = 0 ; i < 8 ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( TARGET_FLAT ) for ( i = 16 ; i < 32 ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( size == 0 && n_global_fp_regs == 0 && args_size == 0 && ! save_local_in_regs_p ) frame_size = apparent_frame_size = 0 ; else { apparent_frame_size = ( size - STARTING_FRAME_OFFSET + 7 ) & - 8 ; apparent_frame_size += n_global_fp_regs * 4 ; frame_size = apparent_frame_size + ( ( args_size + 7 ) & - 8 ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size ; sparc_apparent_frame_size = apparent_frame_size ; sparc_n_global_fp_regs = n_global_fp_regs ; sparc_save_local_in_regs_p = save_local_in_regs_p ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s> static unsigned long arm_compute_save_reg_mask ( ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( frame_pointer_needed ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; if ( IS_VOLATILE ( func_type ) ) return save_reg_mask ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( regs_ever_live [ LR_REGNUM ] || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; return save_reg_mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function . This is used by arm_get_frame_offsets , which may add extra registers .


<s>
bool
PPCDarwinAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
llvm_unreachable
(
"Unknown linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
LinkerPrivateLinkage
:
case
Function
::
InternalLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
O
<<
"\t.weak_definition\t"
<<
CurrentFnName
<<
'\n'
;
break
;
}
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
)
;
O
<<
CurrentFnName
<<
":\n"
;
DW
->
BeginFunction
(
&
MF
)
;
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
;
if
(
++
I
==
MF
.
end
(
)
&&
MF
.
front
(
)
.
empty
(
)
)
O
<<
"\tnop\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
IE
=
I
->
end
(
)
;
II
!=
IE
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

PowerPC
PPC
"\n\n"
"Unknown linkage type!"
"\t.globl\t"
"\t.globl\t"
"\t.weak_definition\t"
":\n"
"\tnop\n"


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> inline bool isFPImm ( const APFloat & Val ) { uint32_t Imm8 ; return isFPImm ( Val , Imm8 ) ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> static bool i386_pe_determine_dllexport_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL && TREE_CODE ( decl ) != FUNCTION_DECL ) return false ; if ( ! TREE_PUBLIC ( decl ) ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && DECL_DECLARED_INLINE_P ( decl ) && ! flag_keep_inline_dllexport ) return false ; if ( lookup_attribute ( "dllexport" , DECL_ATTRIBUTES ( decl ) ) ) return true ; return false ; } </s>

Return true if DECL should be a dllexport 'd object .


<s> Relocator :: Result none ( Relocation & pReloc , X86_64Relocator & pParent ) { return Relocator :: OK ; } </s>

Returns true if none of the bits are set .


<s> static unsigned long arm_compute_save_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( frame_pointer_needed ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; if ( IS_VOLATILE ( func_type ) ) return save_reg_mask ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( regs_ever_live [ LR_REGNUM ] || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! current_function_calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( current_function_pretend_args_size ) ) % 2 ) != 0 ) { unsigned int reg ; for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } return save_reg_mask ; } </s>


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Cond
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
getCMovFromCond
(
(
X86
::
CondCode
)
Cond
[
0
]
.
getImm
(
)
,
MRI
.
getRegClass
(
DstReg
)
->
getSize
(
)
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Sparc Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> bool ARMExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified ; } </s>


<s> SDValue SparcTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget -> is64Bit ( ) ) return LowerCall_64 ( CLI , InVals ) ; return LowerCall_32 ( CLI , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .


<s> bool ARMTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! I -> getType ( ) -> isVectorTy ( ) ) return false ; if ( Subtarget -> hasNEON ( ) ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsSinker = [ ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : return true ; case Instruction :: Sub : return Operand == 1 ; default : return false ; } } ; int Op = 0 ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = 1 ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_Zero ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( Op ) ) ; return true ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void aarch64_expand_sve_vec_cmp_int ( rtx target , rtx_code code , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; rtx res = aarch64_sve_emit_int_cmp ( target , pred_mode , code , data_mode , op0 , op1 ) ; if ( ! rtx_equal_p ( target , res ) ) emit_move_insn ( target , res ) ; } </s>

Expand an SVE integer comparison : TARGET = CODE ( OP0 , OP1 ) .


<s> static bool compute_fp_layout ( const_tree field , int bitpos , assign_data_t * data , int * pnregs , machine_mode * pmode ) { const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( VECTOR_TYPE_P ( TREE_TYPE ( field ) ) && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = 2 ; } else nregs = 1 ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = 1 ; if ( nregs <= 0 ) return false ; } * pnregs = nregs ; * pmode = mode ; return true ; } </s>

A subroutine of function_arg_record_value . Compute the number and the mode of the FP registers to be assigned for FIELD . Return true if at least one FP register is assigned or false otherwise .


<s> unsigned int pure_scalable_type_info :: num_pr ( ) const { unsigned int res = 0 ; for ( unsigned int i = 0 ; i < pieces . length ( ) ; ++ i ) res += pieces [ i ] . num_pr ; return res ; } </s>

Return the total number of predicate registers required by the PST .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void sparc_expand_epilogue ( bool for_eh ) { HOST_WIDE_INT size = sparc_frame_size ; if ( cfun -> calls_alloca ) emit_insn ( gen_frame_blockage ( ) ) ; if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_RESTORE ) ; if ( size == 0 || for_eh ) ; else if ( sparc_leaf_function_p ) { if ( size <= 4096 ) emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; else if ( size <= 8192 ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - 4096 ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( size ) ) ; emit_insn ( gen_stack_pointer_inc ( reg ) ) ; } } } </s>

Expand the function epilogue , either normal or part of a sibcall . We emit all the instructions except the return or the call .


<s> unsigned SparcInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: LDri || MI -> getOpcode ( ) == SP :: LDXri || MI -> getOpcode ( ) == SP :: LDFri || MI -> getOpcode ( ) == SP :: LDDFri || MI -> getOpcode ( ) == SP :: LDQFri ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
unsigned
AArch64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
Ctx
.
getRegisterInfo
(
)
.
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> int ix86_constant_alignment ( tree exp , int align ) { if ( TREE_CODE ( exp ) == REAL_CST ) { if ( TYPE_MODE ( TREE_TYPE ( exp ) ) == DFmode && align < 64 ) return 64 ; else if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( exp ) ) ) && align < 128 ) return 128 ; } else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST && TREE_STRING_LENGTH ( exp ) >= 31 && align < BITS_PER_WORD ) return BITS_PER_WORD ; return align ; } </s>

Compute the alignment given to a constant that is being placed in memory . EXP is the constant and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> Optional < DestSourcePair > MipsSEInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 1 ) . getImm ( ) != ( 1 << 4 ) ) return None ; else if ( isDSPControlWrite ) { return DestSourcePair { MI . getOperand ( 2 ) , MI . getOperand ( 0 ) } ; } else { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; } } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; } return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> unsigned getNumFixupKinds ( ) const override { return CAHP :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> CCAssignFn * ARMTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC , bool isVarArg ) const { return CCAssignFnForNode ( CC , true , isVarArg ) ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool isCheapToSpeculateCtlz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


<s>
StringRef
getPassName
(
)
const
override
{
return
"AIX PPC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86FastISel :: isTypeLegal ( Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> static bool mips_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( mips_abi == ABI_EABI ) { int size ; if ( arg . mode == DImode || arg . mode == DFmode || arg . mode == DQmode || arg . mode == UDQmode || arg . mode == DAmode || arg . mode == UDAmode ) return 0 ; size = arg . type_size_in_bytes ( ) ; return size == - 1 || size > UNITS_PER_WORD ; } else { return targetm . calls . must_pass_in_stack ( arg ) ; } } </s>

Return nonzero when an argument must be passed by reference .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA15 ( ) && getARMSubtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( ) ) ; } return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void rs6000_emit_madd ( rtx target , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( target ) ; rtx dst ; dst = expand_ternary_op ( mode , fma_optab , m1 , m2 , a , target , 0 ) ; gcc_assert ( dst != NULL ) ; if ( dst != target ) emit_move_insn ( target , dst ) ; } </s>


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void LEGAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> Align getStackAlignment ( ) const { return StackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const { unsigned LblOperand = Inst . getOpcode ( ) == AArch64 :: Bcc ? 1 : 0 ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ; Target = Addr + Imm ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( ( VT == MVT :: v8i16 || VT == MVT :: v8f16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else if ( Subtarget -> hasMVEIntegerOps ( ) && ( isVMOVNMask ( M , VT , true , false ) || isVMOVNMask ( M , VT , false , false ) || isVMOVNMask ( M , VT , true , true ) ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> void rs6000_scale_v2df ( rtx tgt , rtx src , int scale ) { HOST_WIDE_INT hwi_scale ( scale ) ; REAL_VALUE_TYPE r_pow ; rtvec v = rtvec_alloc ( 2 ) ; rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = CONST_DOUBLE_FROM_REAL_VALUE ( r_pow , DFmode ) ; RTVEC_ELT ( v , 0 ) = elt ; RTVEC_ELT ( v , 1 ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt , src , scale_vec ) ) ; } </s>

Scale a V2DF vector SRC by two to the SCALE and place in TGT .


<s> static void store_reg_modify ( int base , int reg , HOST_WIDE_INT mod ) { rtx basereg , srcreg , delta ; rtx_insn * insn ; gcc_assert ( VAL_14_BITS_P ( mod ) ) ; basereg = gen_rtx_REG ( Pmode , base ) ; srcreg = gen_rtx_REG ( word_mode , reg ) ; delta = GEN_INT ( mod ) ; insn = emit_insn ( gen_post_store ( basereg , srcreg , delta ) ) ; if ( DO_FRAME_NOTES ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; } } </s>

Emit RTL to store REG at the memory location specified by BASE and then add MOD to BASE . MOD must be < = 8k .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 4 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
", "
<<
StringRef
(
RegIdx
.
Tok
.
Data
,
RegIdx
.
Tok
.
Length
)
<<
">"
;
break
;
case
k_Token
:
OS
<<
getToken
(
)
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; PM . add ( createARMExpandPseudoPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void ix86_expand_vector_init ( bool mmx_ok , rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONST_FIXED_P ( x ) ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( n_var == 1 ) { if ( all_const_zero && ix86_expand_vector_init_one_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , 0 , one_var ) , one_var ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target , vals ) ; } </s>

Initialize vector TARGET via VALS . Suppress the use of MMX instructions unless MMX_OK is true .


<s> bool mips_expand_ins_as_unaligned_store ( rtx dest , rtx src , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { rtx left , right ; machine_mode mode ; if ( ! mips_get_unaligned_mem ( dest , width , bitpos , & left , & right ) ) return false ; mode = int_mode_for_size ( width , 0 ) . require ( ) ; src = gen_lowpart ( mode , src ) ; if ( mode == DImode ) { emit_insn ( gen_mov_sdl ( dest , src , left ) ) ; emit_insn ( gen_mov_sdr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } else { emit_insn ( gen_mov_swl ( dest , src , left ) ) ; emit_insn ( gen_mov_swr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } return true ; } </s>

Try to use left/right stores to expand an `` ins '' pattern . DEST , WIDTH , BITPOS and SRC are the operands passed to the expander ; the operation is the equivalent of : ( set ( zero_extract DEST WIDTH BITPOS ) SRC ) Return true on success .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static void ix86_reorg ( void ) { compute_bb_for_insn ( ) ; if ( TARGET_SEH && current_function_has_exception_handlers ( ) ) ix86_seh_fixup_eh_fallthru ( ) ; if ( optimize && optimize_function_for_speed_p ( cfun ) ) { if ( TARGET_SSE2 ) ix86_split_stlf_stall_load ( ) ; if ( TARGET_PAD_SHORT_FUNCTION ) ix86_pad_short_function ( ) ; else if ( TARGET_PAD_RETURNS ) ix86_pad_returns ( ) ; if ( TARGET_FOUR_JUMP_LIMIT ) ix86_avoid_jump_mispredicts ( ) ; } } </s>

Implement machine specific optimizations . We implement padding of returns for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
Triple
(
TM
.
getTargetTriple
(
)
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> int neg_const_double_rtx_ok_for_fpa ( rtx x ) { REAL_VALUE_TYPE r ; int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; r = REAL_VALUE_NEGATE ( r ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( REAL_VALUES_EQUAL ( r , values_fp [ i ] ) ) return 1 ; return 0 ; } </s>

Return TRUE if rtx X is a valid immediate FPA constant .


<s> bool swiftAsyncContextIsDynamicallySet ( ) const { const Triple & TT = getTargetTriple ( ) ; unsigned Major , Minor , Micro ; TT . getOSVersion ( Major , Minor , Micro ) ; switch ( TT . getOS ( ) ) { default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < 15 ; case Triple :: WatchOS : return Major < 8 ; case Triple :: MacOSX : case Triple :: Darwin : return Major < 12 ; } } </s>

Return whether FrameLowering should always set the `` extended frame present '' bit in FP , or set it based on a symbol in the runtime .


<s> tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE ; } </s>

Target hook for early folding of built-ins , shamelessly stolen from ia64.cc .


<s>
const
char
*
mmix_data_section_asm_op
(
)
{
return
"\t.data ! mmixal:= 8H LOC 9B"
;
}
</s>


<s>
static
void
rs6000_debug_reg_print
(
int
first_regno
,
int
last_regno
,
const
char
*
reg_name
)
{
int
r
,
m
;
for
(
r
=
first_regno
;
r
<=
last_regno
;
++
r
)
{
const
char
*
comma
=
""
;
int
len
;
if
(
first_regno
==
last_regno
)
fprintf
(
stderr
,
"%s:\t"
,
reg_name
)
;
else
fprintf
(
stderr
,
"%s%d:\t"
,
reg_name
,
r
first_regno
)
;
len
=
8
;
for
(
m
=
0
;
m
<
NUM_MACHINE_MODES
;
++
m
)
if
(
rs6000_hard_regno_mode_ok_p
[
m
]
[
r
]
&&
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
if
(
rs6000_hard_regno_nregs
[
m
]
[
r
]
>
1
)
len
+=
fprintf
(
stderr
,
"%s%s/%d"
,
comma
,
GET_MODE_NAME
(
m
)
,
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
;
else
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
GET_MODE_NAME
(
m
)
)
;
comma
=
", "
;
}
if
(
call_used_or_fixed_reg_p
(
r
)
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"call-used"
)
;
comma
=
", "
;
}
if
(
fixed_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"fixed"
)
;
comma
=
", "
;
}
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%sreg-class = %s"
,
comma
,
reg_class_names
[
(
int
)
rs6000_regno_regclass
[
r
]
]
)
;
comma
=
", "
;
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
fprintf
(
stderr
,
"%sregno = %d\n"
,
comma
,
r
)
;
}
}
</s>

Print interesting facts about registers .


<s> bool SICPassConfig :: addInstSelector ( ) { addPass ( createSICISelDag ( getSICTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void ARMConstantPoolValue :: print ( raw_ostream & O ) const { if ( CVal ) O << CVal -> getName ( ) ; else O << S ; if ( Modifier ) O << "(" << Modifier << ")" ; if ( PCAdjust != 0 ) { O << "-(LPC" << LabelId << "+" << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << "-." ; O << ")" ; } } </s>


<s> rtx ix86_libcall_value ( machine_mode mode ) { return ix86_function_value_1 ( NULL , NULL , mode , mode ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> unsigned SystemZInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , SystemZII :: SimpleBDXLoad ) ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> std :: unique_ptr < PBQPRAConstraint > AArch64Subtarget :: getCustomPBQPConstraints ( ) const { return balanceFPOps ( ) ? llvm :: make_unique < A57ChainingConstraint > ( ) : nullptr ; } </s>

Return PBQPConstraint ( s ) for the target .


<s> bool PPCInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return false ; case PPC :: CMPWI : case PPC :: CMPLWI : case PPC :: CMPDI : case PPC :: CMPLDI : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; Value = MI -> getOperand ( 2 ) . getImm ( ) ; Mask = 0xFFFF ; return true ; case PPC :: CMPW : case PPC :: CMPLW : case PPC :: CMPD : case PPC :: CMPLD : case PPC :: FCMPUS : case PPC :: FCMPUD : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; return true ; } } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .

PowerPC PPC PPC::CMPWI PPC::CMPLWI PPC::CMPDI PPC::CMPLDI 1 0 2 0xFFFF PPC::CMPW PPC::CMPLW PPC::CMPD PPC::CMPLD PPC::FCMPUS PPC::FCMPUD 1 2


<s> tree function_resolver :: resolve_to ( mode_suffix_index mode , type_suffix_index type0 , type_suffix_index type1 ) { tree res = lookup_form ( mode , type0 , type1 ) ; if ( ! res ) { if ( type1 == NUM_TYPE_SUFFIXES ) return report_no_such_form ( type0 ) ; if ( type0 == type_suffix_ids [ 0 ] ) return report_no_such_form ( type1 ) ; gcc_unreachable ( ) ; } return res ; } </s>

Resolve the function to one with the mode suffix given by MODE and the type suffixes given by TYPE0 and TYPE1 . Return its function decl on success , otherwise report an error and return error_mark_node .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createSparcELFObjectWriter ( OS , Is64Bit , IsLittleEndian , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s>
void
AArch64InstrInfo
::
suppressLdStPair
(
MachineInstr
*
MI
)
const
{
if
(
MI
->
memoperands_empty
(
)
)
return
;
static_assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
,
"Too many target MO flags"
)
;
(
*
MI
->
memoperands_begin
(
)
)
->
setFlags
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
;
}
</s>

Hint that pairing the given load or store is unprofitable .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool TeeRISCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
bool
ThumbDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
const
MemoryObject
&
Region
,
uint64_t
Address
,
raw_ostream
&
os
)
const
{
unsigned
insn
=
0
;
uint16_t
insn1
=
0
;
uint8_t
bytes
[
2
]
;
if
(
Region
.
readBytes
(
Address
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
unsigned
bits15_11
=
slice
(
insn
,
15
,
11
)
;
bool
IsThumb2
=
false
;
if
(
bits15_11
==
0x1D
||
bits15_11
==
0x1E
||
bits15_11
==
0x1F
)
{
IsThumb2
=
true
;
if
(
Region
.
readBytes
(
Address
+
2
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn1
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
insn
=
(
insn
<<
16
|
insn1
)
;
}
unsigned
Opcode
=
decodeThumbSideEffect
(
IsThumb2
,
insn
)
;
if
(
Thumb2PreloadOpcodeNoPCI
(
Opcode
)
&&
slice
(
insn
,
19
,
16
)
==
15
)
Opcode
=
T2Morph2Preload2PCI
(
Opcode
)
;
ARMFormat
Format
=
ARMFormats
[
Opcode
]
;
Size
=
IsThumb2
4
:
2
;
DEBUG
(
{
errs
(
)
<<
"Opcode="
<<
Opcode
<<
" Name="
<<
ARMUtils
::
OpcodeName
(
Opcode
)
<<
" Format="
<<
stringForARMFormat
(
Format
)
<<
'('
<<
(
int
)
Format
<<
")\n"
;
showBitVector
(
errs
(
)
,
insn
)
;
}
)
;
ARMBasicMCBuilder
*
Builder
=
CreateMCBuilder
(
Opcode
,
Format
)
;
if
(
!
Builder
)
return
false
;
Builder
->
SetSession
(
const_cast
<
Session
*
>
(
&
SO
)
)
;
if
(
!
Builder
->
Build
(
MI
,
insn
)
)
return
false
;
delete
Builder
;
return
true
;
}
</s>

Returns the disassembly of a single instruction .


<s>
__inline__
static
float
sh_media_FMAC_S
(
float
fg
,
float
fh
,
float
fq
)
{
float
res
;
__asm__
(
"fmac.s	%1, %2, %0"
:
"=f"
(
res
)
:
"f"
(
fg
)
,
"f"
(
fh
)
,
"0"
(
fq
)
)
;
return
res
;
}
</s>


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"Unexpected constraint code"
)
;
SDValue
Base
,
Disp
,
Index
;
if
(
!
selectBDXAddr
(
SystemZAddressingMode
::
FormBD
,
SystemZAddressingMode
::
Disp12Only
,
Op
,
Base
,
Disp
,
Index
)
)
return
true
;
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

SystemZ
SystemZ
"Unexpected constraint code"
SystemZAddressingMode::FormBD
SystemZAddressingMode::Disp12Only


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> static void ia64_init_libfuncs ( void ) { set_optab_libfunc ( sdiv_optab , SImode , "__divsi3" ) ; set_optab_libfunc ( udiv_optab , SImode , "__udivsi3" ) ; set_optab_libfunc ( smod_optab , SImode , "__modsi3" ) ; set_optab_libfunc ( umod_optab , SImode , "__umodsi3" ) ; set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , XFmode , "_U_Qfcnvff_f80_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( trunc_optab , XFmode , TFmode , "_U_Qfcnvff_quad_to_f80" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , TImode , TFmode , "_U_Qfcnvfxt_quad_to_quad" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxut_quad_to_sgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxut_quad_to_dbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , TImode , "_U_Qfcnvxf_quad_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , "_U_Qfcnvxuf_dbl_to_quad" ) ; } </s>

Set SImode div/mod functions , init_integral_libfuncs only initializes modes of word_mode and larger . Rename the TFmode libfuncs using the HPUX conventions . __divtf3 is used for XFmode . We need to keep it for backward compatibility .


"missing feature modifier in target %s %qs"

"invalid feature modifier in target %s %qs"

Parse an architecture extensions target attribute string specified in STR . For example `` +fp+nosimd '' . Show any errors if needed . Return TRUE if successful . Update aarch64_isa_flags to reflect the ISA features modified . PRAGMA_OR_ATTR is used in potential error messages .


<s> machine_mode rs6000_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree , int for_return ATTRIBUTE_UNUSED ) { PROMOTE_MODE ( mode , * punsignedp , type ) ; return mode ; } </s>

On rs6000 , function arguments are promoted , as are function return values .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) { if ( Subtarget . isAIXABI ( ) && ! TM . getAIXExtendedAltivecABI ( ) ) return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask ; return CSR_64_AllRegs_VSX_RegMask ; } if ( Subtarget . hasAltivec ( ) ) { if ( Subtarget . isAIXABI ( ) && ! TM . getAIXExtendedAltivecABI ( ) ) return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask ; return CSR_64_AllRegs_Altivec_RegMask ; } return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isAIXABI ( ) ) { return TM . isPPC64 ( ) ? ( ( Subtarget . hasAltivec ( ) && TM . getAIXExtendedAltivecABI ( ) ) ? CSR_PPC64_Altivec_RegMask : CSR_PPC64_RegMask ) : ( ( Subtarget . hasAltivec ( ) && TM . getAIXExtendedAltivecABI ( ) ) ? CSR_AIX32_Altivec_RegMask : CSR_AIX32_RegMask ) ; } if ( CC == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR32_ColdCC_SPE_RegMask : CSR_SVR32_ColdCC_RegMask ) ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_PPC64_Altivec_RegMask : CSR_PPC64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR432_SPE_RegMask : CSR_SVR432_RegMask ) ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .

PowerPC PPC PPC PPC PPC PPC PPC PPC PPC PPC PPC


<s> bool X86FastTileConfig :: runOnMachineFunction ( MachineFunction & MFunc ) { MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; const TargetSubtargetInfo * ST = & MFunc . getSubtarget < X86Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = MFunc . getSubtarget ( ) . getInstrInfo ( ) ; X86FI = MFunc . getInfo < X86MachineFunctionInfo > ( ) ; bool Change = false ; for ( MachineBasicBlock & MBB : MFunc ) Change |= configBasicBlock ( MBB ) ; return Change ; } </s>


<s>
void
GeneralShuffle
::
add
(
SDValue
Op
,
unsigned
Elem
)
{
unsigned
BytesPerElement
=
VT
.
getVectorElementType
(
)
.
getStoreSize
(
)
;
EVT
FromVT
=
Op
.
getNode
(
)
Op
.
getValueType
(
)
:
VT
;
unsigned
FromBytesPerElement
=
FromVT
.
getVectorElementType
(
)
.
getStoreSize
(
)
;
assert
(
FromBytesPerElement
>=
BytesPerElement
&&
"Invalid EXTRACT_VECTOR_ELT"
)
;
unsigned
Byte
=
(
(
Elem
*
FromBytesPerElement
)
%
SystemZ
::
VectorBytes
+
(
FromBytesPerElement
BytesPerElement
)
)
;
while
(
Op
.
getNode
(
)
)
{
if
(
Op
.
getOpcode
(
)
==
ISD
::
BITCAST
)
Op
=
Op
.
getOperand
(
0
)
;
else
if
(
Op
.
getOpcode
(
)
==
ISD
::
VECTOR_SHUFFLE
&&
Op
.
hasOneUse
(
)
)
{
SmallVector
<
int
,
SystemZ
::
VectorBytes
>
OpBytes
;
getVPermMask
(
cast
<
ShuffleVectorSDNode
>
(
Op
)
,
OpBytes
)
;
int
NewByte
;
if
(
!
getShuffleInput
(
OpBytes
,
Byte
,
BytesPerElement
,
NewByte
)
)
break
;
if
(
NewByte
<
0
)
{
addUndef
(
)
;
return
;
}
Op
=
Op
.
getOperand
(
unsigned
(
NewByte
)
/
SystemZ
::
VectorBytes
)
;
Byte
=
unsigned
(
NewByte
)
%
SystemZ
::
VectorBytes
;
}
else
if
(
Op
.
isUndef
(
)
)
{
addUndef
(
)
;
return
;
}
else
break
;
}
unsigned
OpNo
=
0
;
for
(
;
OpNo
<
Ops
.
size
(
)
;
++
OpNo
)
if
(
Ops
[
OpNo
]
==
Op
)
break
;
if
(
OpNo
==
Ops
.
size
(
)
)
Ops
.
push_back
(
Op
)
;
unsigned
Base
=
OpNo
*
SystemZ
::
VectorBytes
+
Byte
;
for
(
unsigned
I
=
0
;
I
<
BytesPerElement
;
++
I
)
Bytes
.
push_back
(
Base
+
I
)
;
}
</s>


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool LanaiInstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { switch ( LdSt . getOpcode ( ) ) { default : return false ; case Lanai :: LDW_RI : case Lanai :: LDW_RR : case Lanai :: SW_RR : case Lanai :: SW_RI : case Lanai :: LDHs_RI : case Lanai :: LDHz_RI : case Lanai :: STH_RI : case Lanai :: LDBs_RI : case Lanai :: LDBz_RI : unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> bool AArch64InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Source , const MachineOperand * & Destination ) const { if ( MI . getOpcode ( ) == AArch64 :: ORRWrs && MI . getOperand ( 1 ) . getReg ( ) == AArch64 :: WZR && MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { Destination = & MI . getOperand ( 0 ) ; Source = & MI . getOperand ( 2 ) ; return true ; } if ( MI . getOpcode ( ) == AArch64 :: ORRXrs && MI . getOperand ( 1 ) . getReg ( ) == AArch64 :: XZR && MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { Destination = & MI . getOperand ( 0 ) ; Source = & MI . getOperand ( 2 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> void x86_order_regs_for_local_alloc ( void ) { int pos = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_BND_REG ; i <= LAST_BND_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] = 0 ; } </s>

Order the registers for register allocator .


<s> void mips_split_move ( rtx dest , rtx src , enum mips_split_type split_type ) { rtx low_dest ; gcc_checking_assert ( mips_split_move_p ( dest , src , split_type ) ) ; if ( FP_REG_RTX_P ( dest ) || FP_REG_RTX_P ( src ) ) { if ( ! TARGET_64BIT && GET_MODE ( dest ) == DImode ) emit_insn ( gen_move_doubleword_fprdi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == DFmode ) emit_insn ( gen_move_doubleword_fprdf ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V2SFmode ) emit_insn ( gen_move_doubleword_fprv2sf ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V2SImode ) emit_insn ( gen_move_doubleword_fprv2si ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V4HImode ) emit_insn ( gen_move_doubleword_fprv4hi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V8QImode ) emit_insn ( gen_move_doubleword_fprv8qi ( dest , src ) ) ; else if ( TARGET_64BIT && GET_MODE ( dest ) == TFmode ) emit_insn ( gen_move_doubleword_fprtf ( dest , src ) ) ; else gcc_unreachable ( ) ; } else if ( REG_P ( dest ) && REGNO ( dest ) == MD_REG_FIRST ) { low_dest = mips_subword ( dest , false ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthidi_ti ( dest , mips_subword ( src , true ) , low_dest ) ) ; else emit_insn ( gen_mthisi_di ( dest , mips_subword ( src , true ) , low_dest ) ) ; } else if ( REG_P ( src ) && REGNO ( src ) == MD_REG_FIRST ) { mips_emit_move ( mips_subword ( dest , false ) , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( mips_subword ( dest , true ) , src ) ) ; else emit_insn ( gen_mfhisi_di ( mips_subword ( dest , true ) , src ) ) ; } else { low_dest = mips_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; } else { mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; } } } </s>

Split a move from SRC to DEST , given that mips_split_move_p holds . SPLIT_TYPE describes the split condition .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
ResValue
=
OutVals
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
AExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
ResValue
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void arm_insert_attributes ( tree fndecl , tree * attributes ) { const char * mode ; if ( ! TARGET_FLIP_THUMB ) return ; if ( TREE_CODE ( fndecl ) != FUNCTION_DECL || DECL_EXTERNAL ( fndecl ) || DECL_BUILT_IN ( fndecl ) || DECL_ARTIFICIAL ( fndecl ) ) return ; if ( current_function_decl ) { mode = TARGET_THUMB ? "thumb" : "arm" ; add_attribute ( mode , attributes ) ; return ; } if ( lookup_attribute ( "target" , * attributes ) != NULL ) return ; mode = thumb_flipper ? "thumb" : "arm" ; add_attribute ( mode , attributes ) ; thumb_flipper = ! thumb_flipper ; } </s>

For testing . Insert thumb or arm modes alternatively on functions .

arm "thumb" "arm" "target" "thumb" "arm"


<s> static rtx hppa_builtin_saveregs ( void ) { rtx offset , dest ; tree fntype = TREE_TYPE ( current_function_decl ) ; int argadj = ( ( ! stdarg_p ( fntype ) ) ? UNITS_PER_WORD : 0 ) ; if ( argadj ) offset = plus_constant ( Pmode , crtl -> args . arg_offset_rtx , argadj ) ; else offset = crtl -> args . arg_offset_rtx ; if ( TARGET_64BIT ) { int i , off ; if ( argadj ) offset = plus_constant ( Pmode , crtl -> args . arg_offset_rtx , - argadj ) ; else offset = crtl -> args . arg_offset_rtx ; for ( i = 26 , off = - 64 ; i >= 19 ; i -- , off += 8 ) emit_move_insn ( gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , off ) ) , gen_rtx_REG ( word_mode , i ) ) ; emit_move_insn ( virtual_incoming_args_rtx , plus_constant ( Pmode , arg_pointer_rtx , - 64 ) ) ; return copy_to_reg ( expand_binop ( Pmode , add_optab , virtual_incoming_args_rtx , offset , 0 , 0 , OPTAB_LIB_WIDEN ) ) ; } dest = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , crtl -> args . internal_arg_pointer , - 16 ) ) ; set_mem_alias_set ( dest , get_varargs_alias_set ( ) ) ; set_mem_align ( dest , BITS_PER_WORD ) ; move_block_from_reg ( 23 , dest , 4 ) ; emit_insn ( gen_blockage ( ) ) ; return copy_to_reg ( expand_binop ( Pmode , add_optab , crtl -> args . internal_arg_pointer , offset , 0 , 0 , OPTAB_LIB_WIDEN ) ) ; } </s>

Do what is necessary for ` va_start ' . We look at the current function to determine if stdargs or varargs is used and fill in an initial va_list . A pointer to this constructor is returned .


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT
:
return
":got:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL
:
return
":gottprel:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s>
unsigned
PPCVSXSwapRemoval
::
lookThruCopyLike
(
unsigned
SrcReg
,
unsigned
VecIdx
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
;
if
(
MI
->
isCopy
(
)
)
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
CopySrcReg
)
)
{
SwapVector
[
VecIdx
]
.
MentionsPhysVR
=
1
;
return
CopySrcReg
;
}
return
lookThruCopyLike
(
CopySrcReg
,
VecIdx
)
;
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
unsigned
width
,
enum
simd_immediate_check
which
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
&
info
,
which
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
GET_MODE_BITSIZE
(
info
.
elt_mode
)
)
;
lane_count
=
width
/
GET_MODE_BITSIZE
(
info
.
elt_mode
)
;
if
(
GET_MODE_CLASS
(
info
.
elt_mode
)
==
MODE_FLOAT
)
{
gcc_assert
(
info
.
shift
==
0
&&
info
.
insn
==
simd_immediate_info
::
MOV
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
const
unsigned
int
buf_size
=
20
;
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
value
)
,
buf_size
,
buf_size
,
1
,
info
.
elt_mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
gcc_assert
(
CONST_INT_P
(
info
.
value
)
)
;
if
(
which
==
AARCH64_CHECK_MOV
)
{
mnemonic
=
info
.
insn
==
simd_immediate_info
::
MVN
"mvni"
:
"movi"
;
shift_op
=
info
.
modifier
==
simd_immediate_info
::
MSL
"msl"
:
"lsl"
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
value
)
)
;
else
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
shift_op
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
}
else
{
mnemonic
=
info
.
insn
==
simd_immediate_info
::
MVN
"bic"
:
"orr"
;
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, #"
HOST_WIDE_INT_PRINT_DEC
", %s #%d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
"lsl"
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, #"
HOST_WIDE_INT_PRINT_DEC
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
}
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override { if ( VT . getVectorNumElements ( ) != 1 && VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> unsigned MipsCodeEmitter :: getJumpTargetOpValue ( const MachineInstr & MI , unsigned OpNo ) const { return 0 ; } </s>

getJumpTargetOpValue - Return binary encoding of the jump target operand .


"#if defined(_ARCH_PPC64) && defined (_ARCH_PWR9)\n"

Write everything to the include file ( rs6000-vecdefines.h ) . Return 1 if successful , 0 otherwise .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned Align , bool isSrcConst , bool isSrcStr , SelectionDAG & DAG ) const { const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool NoImplicitFloatOps = F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ; if ( ! NoImplicitFloatOps && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE2 ( ) && Size >= 16 ) return MVT :: v4i32 ; if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE1 ( ) && Size >= 16 ) return MVT :: v4f32 ; } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static bool nds32_rtx_costs ( rtx x , machine_mode mode , int outer_code , int opno , int * total , bool speed ) { return nds32_rtx_costs_impl ( x , mode , outer_code , opno , total , speed ) ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , 0 ) ; if ( mode == BLKmode ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


<s> static void register_svpattern ( ) { auto_vec < string_int_pair , 32 > values ; values . quick_push ( string_int_pair ( "SV_" # UPPER , VALUE ) ) ; AARCH64_FOR_SVPATTERN ( PUSH ) acle_svpattern = lang_hooks . types . simulate_enum_decl ( input_location , "svpattern" , values ) ; } </s>


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI -> getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : SrcOpIdx1 = 1 ; SrcOpIdx2 = 2 ; return true ; } return false ; } case X86 :: VFMADDPDr231r : case X86 :: VFMADDPSr231r : case X86 :: VFMADDSDr231r : case X86 :: VFMADDSSr231r : case X86 :: VFMSUBPDr231r : case X86 :: VFMSUBPSr231r : case X86 :: VFMSUBSDr231r : case X86 :: VFMSUBSSr231r : case X86 :: VFNMADDPDr231r : case X86 :: VFNMADDPSr231r : case X86 :: VFNMADDSDr231r : case X86 :: VFNMADDSSr231r : case X86 :: VFNMSUBPDr231r : case X86 :: VFNMSUBPSr231r : case X86 :: VFNMSUBSDr231r : case X86 :: VFNMSUBSSr231r : case X86 :: VFMADDPDr231rY : case X86 :: VFMADDPSr231rY : case X86 :: VFMSUBPDr231rY : case X86 :: VFMSUBPSr231rY : case X86 :: VFNMADDPDr231rY : case X86 :: VFNMADDPSr231rY : case X86 :: VFNMSUBPDr231rY : case X86 :: VFNMSUBPSr231rY : SrcOpIdx1 = 2 ; SrcOpIdx2 = 3 ; return true ; default : return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> const char * mips_output_probe_stack_range ( rtx reg1 , rtx reg2 ) { static int labelno = 0 ; char loop_lab [ 32 ] , end_lab [ 32 ] , tmp [ 64 ] ; rtx xops [ 2 ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , "LPSRL" , labelno ) ; ASM_GENERATE_INTERNAL_LABEL ( end_lab , "LPSRE" , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ 0 ] = reg1 ; xops [ 1 ] = reg2 ; strcpy ( tmp , "%(%<beq\t%0,%1," ) ; output_asm_insn ( strcat ( tmp , & end_lab [ 1 ] ) , xops ) ; xops [ 1 ] = GEN_INT ( - PROBE_INTERVAL ) ; if ( TARGET_64BIT && TARGET_LONG64 ) output_asm_insn ( "daddiu\t%0,%0,%1" , xops ) ; else output_asm_insn ( "addiu\t%0,%0,%1" , xops ) ; fprintf ( asm_out_file , "\tb\t" ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file ) ; if ( TARGET_64BIT ) output_asm_insn ( "sd\t$0,0(%0)%)" , xops ) ; else output_asm_insn ( "sw\t$0,0(%0)%)" , xops ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , end_lab ) ; return "" ; } </s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasNEON ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetDarwin ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; const Triple & T = getTargetTriple ( ) ; SupportsTailCall = T . getOS ( ) == Triple :: IOS && ! T . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> unsigned CSKYInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case CSKY :: ST16B : case CSKY :: ST16H : case CSKY :: ST16W : case CSKY :: ST32B : case CSKY :: ST32H : case CSKY :: ST32W : case CSKY :: SPILL_CARRY : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> InstructionCost ARMTargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) { if ( Subtarget -> hasFPAO ( ) ) return AM . Scale < 0 ? 1 : 0 ; return 0 ; } return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> DecodeStatus MMIXDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = support :: endian :: read32be ( Bytes . data ( ) ) ; return decodeInstruction ( DecoderTableMMIX32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> static void arm_print_value ( FILE * f , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; return ; case CONST_DOUBLE : { char fpstr [ 20 ] ; real_to_decimal ( fpstr , CONST_DOUBLE_REAL_VALUE ( x ) , sizeof ( fpstr ) , 0 , 1 ) ; fputs ( fpstr , f ) ; } return ; case CONST_VECTOR : { int i ; fprintf ( f , "<" ) ; for ( i = 0 ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( CONST_VECTOR_ELT ( x , i ) ) ) ; if ( i < ( CONST_VECTOR_NUNITS ( x ) - 1 ) ) fputc ( ',' , f ) ; } fprintf ( f , ">" ) ; } return ; case CONST_STRING : fprintf ( f , "\"%s\"" , XSTR ( x , 0 ) ) ; return ; case SYMBOL_REF : fprintf ( f , "`%s'" , XSTR ( x , 0 ) ) ; return ; case LABEL_REF : fprintf ( f , "L%d" , INSN_UID ( XEXP ( x , 0 ) ) ) ; return ; case CONST : arm_print_value ( f , XEXP ( x , 0 ) ) ; return ; case PLUS : arm_print_value ( f , XEXP ( x , 0 ) ) ; fprintf ( f , "+" ) ; arm_print_value ( f , XEXP ( x , 1 ) ) ; return ; case PC : fprintf ( f , "pc" ) ; return ; default : fprintf ( f , "????" ) ; return ; } } </s>

Print a symbolic form of X to the debug file , F .


<s> int barrier_align ( rtx_insn * barrier_or_label ) { if ( ! barrier_or_label ) return 0 ; if ( LABEL_P ( barrier_or_label ) && NEXT_INSN ( barrier_or_label ) && JUMP_TABLE_DATA_P ( NEXT_INSN ( barrier_or_label ) ) ) return 2 ; if ( BARRIER_P ( barrier_or_label ) && PREV_INSN ( barrier_or_label ) && JUMP_TABLE_DATA_P ( PREV_INSN ( barrier_or_label ) ) ) { rtx pat = PATTERN ( PREV_INSN ( barrier_or_label ) ) ; return ( ( optimize_size || ( ( unsigned ) XVECLEN ( pat , 1 ) * GET_MODE_SIZE ( GET_MODE ( pat ) ) <= ( unsigned ) 1 << ( CACHE_LOG - 2 ) ) ) ? 1 : align_jumps_log ) ; } rtx_insn * next = next_active_insn ( barrier_or_label ) ; if ( ! next ) return 0 ; rtx pat = PATTERN ( next ) ; if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == UNSPECV_ALIGN ) return 0 ; if ( optimize_size ) return 0 ; if ( ! TARGET_SH2 || ! optimize ) return align_jumps_log ; if ( mdep_reorg_phase > SH_FIXUP_PCLOAD ) { int slot , credit ; bool jump_to_next = false ; rtx_insn * prev = prev_real_insn ( prev_active_insn ( barrier_or_label ) ) ; for ( slot = 2 , credit = ( 1 << ( CACHE_LOG - 2 ) ) + 2 ; credit >= 0 && prev && NONJUMP_INSN_P ( prev ) ; prev = prev_real_insn ( prev ) ) { jump_to_next = false ; if ( GET_CODE ( PATTERN ( prev ) ) == USE || GET_CODE ( PATTERN ( prev ) ) == CLOBBER ) continue ; if ( rtx_sequence * prev_seq = dyn_cast < rtx_sequence * > ( PATTERN ( prev ) ) ) { prev = prev_seq -> insn ( 1 ) ; if ( INSN_UID ( prev ) == INSN_UID ( next ) ) { jump_to_next = true ; continue ; } } if ( slot && get_attr_in_delay_slot ( prev ) == IN_DELAY_SLOT_YES ) slot = 0 ; credit -= get_attr_length ( prev ) ; } if ( prev && jump_to_label_p ( prev ) ) { rtx_insn * x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN ( prev ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( credit - slot >= ( GET_CODE ( SET_SRC ( pat ) ) == PC ? 2 : 0 ) ) return 0 ; } } } return align_jumps_log ; } </s>

BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following a barrier . Return the base 2 logarithm of the desired alignment .


<s> const char * KudeyarAsmPrinter :: getCurrentABIString ( ) const { { } return "abi32" ; } </s>


<s> void Reset ( ) { Ops . clear ( ) ; OpBegins . clear ( ) ; OpBegins . push_back ( 0 ) ; HasPersonality = false ; } </s>


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ 2 ] ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 0 ] , 0 ) , GET_MODE ( operands [ 0 ] ) , false ) ) operands [ 0 ] = replace_equiv_address ( operands [ 0 ] , copy_addr_to_reg ( XEXP ( operands [ 0 ] , 0 ) ) ) ; if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_CODE ( XEXP ( operands [ 1 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 1 ] , 0 ) , GET_MODE ( operands [ 1 ] ) , false ) ) operands [ 1 ] = replace_equiv_address ( operands [ 1 ] , copy_addr_to_reg ( XEXP ( operands [ 1 ] , 0 ) ) ) ; } </s>

Helper for the following . Get rid of [ r+r ] memory refs in cases where it wo n't work ( TImode , TFmode ) .


<s> HOST_WIDE_INT compute_frame_size ( HOST_WIDE_INT size , int * fregs_live ) { int freg_saved = 0 ; int i , j ; size = ( size + UNITS_PER_WORD - 1 ) & ~ ( UNITS_PER_WORD - 1 ) ; if ( size || frame_pointer_needed ) size += STARTING_FRAME_OFFSET ; if ( DO_FRAME_NOTES && current_function_calls_eh_return ) { unsigned int i ; for ( i = 0 ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; ++ i ) continue ; size += i * UNITS_PER_WORD ; } for ( i = 18 , j = frame_pointer_needed ? 4 : 3 ; i >= j ; i -- ) if ( regs_ever_live [ i ] ) size += UNITS_PER_WORD ; for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) if ( regs_ever_live [ i ] || ( ! TARGET_64BIT && regs_ever_live [ i + 1 ] ) ) { freg_saved = 1 ; size += 8 ; } if ( freg_saved ) { size = ( size + 7 ) & ~ 7 ; if ( fregs_live ) * fregs_live = 1 ; } size += current_function_outgoing_args_size ; if ( ! current_function_is_leaf || size ) size += TARGET_64BIT ? 48 : 32 ; return ( ( size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1 ) & ~ ( PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1 ) ) ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> static unsigned int mips_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; if ( FP_REG_P ( regno ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return 1 ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ; } return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


<s> void MipsGOT :: split ( ) { m_MergedLocalSymbols . clear ( ) ; m_MergedGlobalSymbols . clear ( ) ; size_t uniqueCount = 0 ; for ( SymbolUniqueMapType :: const_iterator it = m_InputGlobalSymbols . begin ( ) , end = m_InputGlobalSymbols . end ( ) ; it != end ; ++ it ) { if ( it -> second ) ++ uniqueCount ; } m_MultipartList . back ( ) . m_LocalNum -= m_InputLocalSymbols . size ( ) ; m_MultipartList . back ( ) . m_GlobalNum -= uniqueCount ; m_MultipartList . back ( ) . m_Inputs . erase ( m_pInput ) ; m_MultipartList . push_back ( GOTMultipart ( m_InputLocalSymbols . size ( ) , m_InputGlobalSymbols . size ( ) ) ) ; m_MultipartList . back ( ) . m_Inputs . insert ( m_pInput ) ; } </s>

Split into substrings around the occurrences of a separator character .


<s> virtual unsigned getISAEncoding ( ) LLVM_OVERRIDE { if ( ! Subtarget -> isTargetDarwin ( ) ) return 0 ; return Subtarget -> isThumb ( ) ? ARM :: DW_ISA_ARM_thumb : ARM :: DW_ISA_ARM_arm ; } </s>

Get the value for DW_AT_APPLE_isa . Zero if no isa encoding specified .


<s>
static
void
rs6000_elf_asm_out_constructor
(
rtx
symbol
,
int
priority
)
{
const
char
*
section
=
".ctors"
;
char
buf
[
18
]
;
if
(
priority
!=
DEFAULT_INIT_PRIORITY
)
{
sprintf
(
buf
,
".ctors.%.5u"
,
MAX_INIT_PRIORITY
priority
)
;
section
=
buf
;
}
switch_to_section
(
get_section
(
section
,
SECTION_WRITE
,
)
)
;
assemble_align
(
POINTER_SIZE
)
;
if
(
DEFAULT_ABI
==
ABI_V4
&&
(
TARGET_RELOCATABLE
||
flag_pic
>
1
)
)
{
fputs
(
"\t.long ("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
symbol
)
;
fputs
(
")@fixup\n"
,
asm_out_file
)
;
}
else
assemble_integer
(
symbol
,
POINTER_SIZE
/
BITS_PER_UNIT
,
POINTER_SIZE
,
1
)
;
}
</s>


<s> int aarch64_epilogue_uses ( int regno ) { if ( epilogue_completed ) { if ( regno == LR_REGNUM ) return 1 ; } return 0 ; } </s>

Return 1 if the register is used by the epilogue . We need to say the return register is used , but only after epilogue generation is complete . Note that in the case of sibcalls , the values `` used by the epilogue '' are considered live at the start of the called function . For SIMD functions we need to return 1 for FP registers that are saved and restored by a function but are not zero in call_used_regs . If we do not do this optimizations may remove the restore of the register .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
int
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
<<
*
Imm
.
Val
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
OS
<<
Mem
.
Base
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_Register
:
OS
<<
"Register<"
<<
Reg
.
RegNum
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void ix86_emit_i387_log1p ( rtx op0 , rtx op1 ) { rtx label1 = gen_label_rtx ( ) ; rtx label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx tmp2 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; emit_insn ( gen_cmpxf ( tmp , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( "0.29289321881345247561810596348408353" , XFmode ) , XFmode ) ) ) ; emit_jump_insn ( gen_bge ( label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xp1_xf3 ( op0 , tmp2 , op1 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( tmp , op1 , tmp ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2x_xf3 ( op0 , tmp2 , tmp ) ) ; emit_label ( label2 ) ; } </s>

Output code to perform a log1p XFmode calculation .


<s>
char
*
neon_output_shift_immediate
(
const
char
*
mnem
,
char
sign
,
rtx
*
op2
,
machine_mode
mode
,
int
quad
,
bool
isleftshift
)
{
int
width
,
is_valid
;
static
char
templ
[
40
]
;
is_valid
=
neon_immediate_valid_for_shift
(
*
op2
,
mode
,
op2
,
&
width
,
isleftshift
)
;
gcc_assert
(
is_valid
!=
0
)
;
if
(
quad
)
sprintf
(
templ
,
"%s.%c%d\t%%q0, %%q1, %%2"
,
mnem
,
sign
,
width
)
;
else
sprintf
(
templ
,
"%s.%c%d\t%%P0, %%P1, %%2"
,
mnem
,
sign
,
width
)
;
return
templ
;
}
</s>

Return a string suitable for output of Neon immediate shift operation ( VSHR or VSHL ) MNEM .


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI . getOperand ( OpNum ) . getReg ( ) ; if ( MI . killsRegister ( Reg , TRI ) ) return ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { unsigned Opc = Subtarget . hasAVX ( ) ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> void ARMTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { ARMELFStreamer & Streamer = getStreamer ( ) ; if ( ! Streamer . IsThumb ) return ; Streamer . getAssembler ( ) . registerSymbol ( * Symbol ) ; unsigned Type = cast < MCSymbolELF > ( Symbol ) -> getType ( ) ; if ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) Streamer . EmitThumbFunc ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s>
const
char
*
pa_output_millicode_call
(
rtx_insn
*
insn
,
rtx
call_dest
)
{
int
attr_length
=
get_attr_length
(
insn
)
;
int
seq_length
=
dbr_sequence_length
(
)
;
rtx
xoperands
[
4
]
;
xoperands
[
0
]
=
call_dest
;
if
(
!
TARGET_LONG_CALLS
&&
(
attr_length
==
8
||
(
attr_length
==
28
&&
get_attr_type
(
insn
)
==
TYPE_SH_FUNC_ADRS
)
)
)
{
xoperands
[
1
]
=
gen_rtx_REG
(
Pmode
,
TARGET_64BIT
2
:
31
)
;
output_asm_insn
(
"{bl|b,l} %0,%1"
,
xoperands
)
;
}
else
{
if
(
TARGET_64BIT
)
{
xoperands
[
1
]
=
gen_rtx_REG
(
Pmode
,
1
)
;
xoperands
[
2
]
=
xoperands
[
1
]
;
pa_output_pic_pcrel_sequence
(
xoperands
)
;
output_asm_insn
(
"bve,l (%%r1),%%r2"
,
xoperands
)
;
}
else
if
(
TARGET_PORTABLE_RUNTIME
)
{
output_asm_insn
(
"ldil L'%0,%%r1"
,
xoperands
)
;
output_asm_insn
(
"ldo R'%0(%%r1),%%r1"
,
xoperands
)
;
output_asm_insn
(
"{bl|b,l} .+8,%%r31"
,
xoperands
)
;
output_asm_insn
(
"addi 8,%%r31,%%r31"
,
xoperands
)
;
output_asm_insn
(
"bv %%r0(%%r1)"
,
xoperands
)
;
}
else
if
(
!
flag_pic
)
{
output_asm_insn
(
"ldil L'%0,%%r1"
,
xoperands
)
;
if
(
TARGET_PA_20
)
output_asm_insn
(
"be,l R'%0(%%sr4,%%r1),%%sr0,%%r31"
,
xoperands
)
;
else
output_asm_insn
(
"ble R'%0(%%sr4,%%r1)"
,
xoperands
)
;
}
else
{
xoperands
[
1
]
=
gen_rtx_REG
(
Pmode
,
31
)
;
xoperands
[
2
]
=
gen_rtx_REG
(
Pmode
,
1
)
;
pa_output_pic_pcrel_sequence
(
xoperands
)
;
output_asm_insn
(
"ldo {16|24}(%%r31),%%r31"
,
xoperands
)
;
output_asm_insn
(
"bv %%r0(%%r1)"
,
xoperands
)
;
}
}
if
(
seq_length
==
0
)
output_asm_insn
(
"nop"
,
xoperands
)
;
return
""
;
}
</s>

INSN is a function call . CALL_DEST is the routine we are calling .