<s> void function_builder :: add_overloaded_functions ( const function_group_info & group , mode_suffix_index mode ) { if ( m_direct_overloads ) return ; unsigned int explicit_type0 = ( * group . shape ) -> explicit_type_suffix_p ( 0 ) ; unsigned int explicit_type1 = ( * group . shape ) -> explicit_type_suffix_p ( 1 ) ; for ( unsigned int pi = 0 ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) { if ( ! explicit_type0 && ! explicit_type1 ) { function_instance instance ( group . base_name , * group . base , * group . shape , mode , types_none [ 0 ] , group . preds [ pi ] ) ; add_overloaded_function ( instance , group . required_extensions ) ; } else for ( unsigned int ti = 0 ; group . types [ ti ] [ 0 ] != NUM_TYPE_SUFFIXES ; ++ ti ) { type_suffix_pair types = { explicit_type0 ? group . types [ ti ] [ 0 ] : NUM_TYPE_SUFFIXES , explicit_type1 ? group . types [ ti ] [ 1 ] : NUM_TYPE_SUFFIXES } ; function_instance instance ( group . base_name , * group . base , * group . shape , mode , types , group . preds [ pi ] ) ; add_overloaded_function ( instance , group . required_extensions ) ; } } } </s>

If we are using manual overload resolution , add one function decl for each overloaded function in GROUP . Take the function base name from GROUP and the mode from MODE .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Dead register definitions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool isBlockAddress ( ) const { return Kind == ARMCP :: CPBlockAddress ; } </s>

isBlockAddress - Tests if this is a MO_BlockAddress operand .


<s> bool sh_attr_renesas_p ( const_tree td ) { if ( TARGET_HITACHI ) return true ; if ( td == NULL_TREE ) return false ; if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return false ; return ( lookup_attribute ( "renesas" , TYPE_ATTRIBUTES ( td ) ) != NULL_TREE ) ; } </s>

True if __attribute__ ( ( renesas ) ) or -mrenesas .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDR : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: t2LDRi12 : case ARM :: tRestore : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: FLDD : case ARM :: FLDS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> inline static bool isMem ( const MachineInstr * MI , unsigned Op ) { if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + 4 <= MI -> getNumOperands ( ) && MI -> getOperand ( Op ) . isReg ( ) && isScale ( MI -> getOperand ( Op + 1 ) ) && MI -> getOperand ( Op + 2 ) . isReg ( ) && ( MI -> getOperand ( Op + 3 ) . isImm ( ) || MI -> getOperand ( Op + 3 ) . isGlobal ( ) || MI -> getOperand ( Op + 3 ) . isCPI ( ) || MI -> getOperand ( Op + 3 ) . isJTI ( ) ) ; } </s>


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
unsigned
StackEst
=
TFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
getBaseRegister
(
MF
)
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> bool PPCTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : case Intrinsic :: ppc_vsx_lxvd2x_be : case Intrinsic :: ppc_vsx_lxvw4x_be : case Intrinsic :: ppc_vsx_lxvl : case Intrinsic :: ppc_vsx_lxvll : { Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . ReadMem = true ; Info . WriteMem = false ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : case Intrinsic :: ppc_vsx_stxvd2x_be : case Intrinsic :: ppc_vsx_stxvw4x_be : case Intrinsic :: ppc_vsx_stxvl : case Intrinsic :: ppc_vsx_stxvll : { Info . PtrVal = Inst -> getArgOperand ( 1 ) ; Info . ReadMem = false ; Info . WriteMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_XCC
:
case
SP
::
SELECT_CC_FP_XCC
:
case
SP
::
SELECT_CC_DFP_XCC
:
case
SP
::
SELECT_CC_QFP_XCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BPXCC
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
StringRef
getPassName
(
)
const
override
{
return
"DLX load / store optimization pass"
;
}
</s>

DLX
"DLX load / store optimization pass"


<s>
bool
ARM64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
assert
(
0
&&
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> unsigned PPCTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getX86TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
virtual
void
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_Token
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
k_Register
:
OS
<<
"Reg: #"
<<
getReg
(
)
<<
"\n"
;
break
;
case
k_Immediate
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
k_MemoryReg
:
OS
<<
"Mem: "
<<
getMemBase
(
)
<<
"+"
<<
getMemOffsetReg
(
)
<<
"\n"
;
break
;
case
k_MemoryImm
:
assert
(
getMemOff
(
)
!=
0
)
;
OS
<<
"Mem: "
<<
getMemBase
(
)
<<
"+"
<<
*
getMemOff
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool VESubtarget :: enableMachineScheduler ( ) const { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> const SystemZRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned SparcInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: STri || MI -> getOpcode ( ) == SP :: STXri || MI -> getOpcode ( ) == SP :: STFri || MI -> getOpcode ( ) == SP :: STDFri ) { if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> TargetPassConfig * SystemZTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SystemZPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool isReg ( ) const override { if ( isGPRAsmReg ( ) && RegIdx . Index == 0 ) return true ; return Kind == k_PhysRegister ; } </s>


<s> Optional < MCFixupKind > X86AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; if ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_X86_64_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_X86_64_8 ) . Case ( "BFD_RELOC_16" , ELF :: R_X86_64_16 ) . Case ( "BFD_RELOC_32" , ELF :: R_X86_64_32 ) . Case ( "BFD_RELOC_64" , ELF :: R_X86_64_64 ) . Default ( - 1u ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_386_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_386_8 ) . Case ( "BFD_RELOC_16" , ELF :: R_386_16 ) . Case ( "BFD_RELOC_32" , ELF :: R_386_32 ) . Default ( - 1u ) ; } if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , PPCTargetMachine & TM , bool is64Bit , CodeGenOpt :: Level OptLevel ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , IsPPC64 ( is64Bit ) , TargetTriple ( TT ) , OptLevel ( OptLevel ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , DL ( getDataLayoutString ( * this ) ) , InstrInfo ( * this ) , JITInfo ( * this ) , TLInfo ( TM ) , TSInfo ( & DL ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool use_toc_relative_ref ( rtx sym , machine_mode mode ) { return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) ) || ( TARGET_CMODEL == CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) && GET_MODE_SIZE ( mode ) <= POWERPC64_TOC_POINTER_ALIGNMENT ) ) ; } </s>

Return true iff the given SYMBOL_REF refers to a constant pool entry that we have put in the TOC , or for cmodel=medium , if the SYMBOL_REF can be addressed relative to the toc pointer .


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
)
;
case
ISD
::
SHL
:
Val
=
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips
Mips
ISD::AND
ISD::OR
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 5 - HasFP ; } case ARM :: GPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 10 - HasFP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , FK_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_CALL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_HI16 ) . Case ( "R_MIPS_CALL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_LO16 ) . Case ( "R_MIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL16 ) . Case ( "R_MIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_OFST ) . Case ( "R_MIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_DISP ) . Case ( "R_MIPS_GOT_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_HI16 ) . Case ( "R_MIPS_GOT_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_LO16 ) . Case ( "R_MIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_Mips_GOTTPREL ) . Case ( "R_MIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_HI ) . Case ( "R_MIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_LO ) . Case ( "R_MIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_Mips_TLSGD ) . Case ( "R_MIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_Mips_TLSLDM ) . Case ( "R_MIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_HI ) . Case ( "R_MIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_LO ) . Case ( "R_MICROMIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_CALL16 ) . Case ( "R_MICROMIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_DISP ) . Case ( "R_MICROMIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_PAGE ) . Case ( "R_MICROMIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_OFST ) . Case ( "R_MICROMIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT16 ) . Case ( "R_MICROMIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOTTPREL ) . Case ( "R_MICROMIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 ) . Case ( "R_MICROMIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_GD ) . Case ( "R_MICROMIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_LDM ) . Case ( "R_MICROMIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 ) . Case ( "R_MIPS_JALR" , ( MCFixupKind ) Mips :: fixup_Mips_JALR ) . Case ( "R_MICROMIPS_JALR" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_JALR ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>


<s> static tree resolve_vec_adde_sube ( resolution * res , rs6000_gen_builtins fcode , tree * args , tree * types , location_t loc ) { if ( TREE_CODE ( types [ 0 ] ) != VECTOR_TYPE || ! lang_hooks . types_compatible_p ( types [ 0 ] , types [ 1 ] ) || ! lang_hooks . types_compatible_p ( types [ 1 ] , types [ 2 ] ) ) { * res = resolved_bad ; return error_mark_node ; } switch ( TYPE_MODE ( TREE_TYPE ( types [ 0 ] ) ) ) { case E_SImode : { vec < tree , va_gc > * params = make_tree_vector ( ) ; vec_safe_push ( params , args [ 0 ] ) ; vec_safe_push ( params , args [ 1 ] ) ; tree add_sub_builtin ; if ( fcode == RS6000_OVLD_VEC_ADDE ) add_sub_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_ADD ] ; else add_sub_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_SUB ] ; tree call = altivec_resolve_overloaded_builtin ( loc , add_sub_builtin , params ) ; tree const1 = build_int_cstu ( TREE_TYPE ( types [ 0 ] ) , 1 ) ; tree ones_vector = build_vector_from_val ( types [ 0 ] , const1 ) ; tree and_expr = fold_build2_loc ( loc , BIT_AND_EXPR , types [ 0 ] , args [ 2 ] , ones_vector ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , call ) ; vec_safe_push ( params , and_expr ) ; * res = resolved ; return altivec_resolve_overloaded_builtin ( loc , add_sub_builtin , params ) ; } case E_TImode : * res = unresolved ; break ; default : * res = resolved_bad ; } return error_mark_node ; } </s>

Resolve an overloaded vec_adde or vec_sube call and return a tree expression for the resolved call if successful . ARGS contains the arguments to the call . TYPES contains their arguments . RES must be set to indicate the status of the resolution attempt . LOC contains statement location information .


<s>
bool
PPCInstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
,
AliasAnalysis
*
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static unsigned aarch64_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( stmt_info && vectype && aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) ) stmt_cost = aarch64_sve_adjust_stmt_cost ( kind , stmt_info , vectype , stmt_cost ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


<s>
bool
X86ATTAsmParser
::
ParseInstruction
(
const
StringRef
&
Name
,
MCInst
&
Inst
)
{
SmallVector
<
X86Operand
,
8
>
Operands
;
Operands
.
push_back
(
X86Operand
::
CreateToken
(
Name
)
)
;
SMLoc
Loc
=
getLexer
(
)
.
getTok
(
)
.
getLoc
(
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Star
)
)
{
getLexer
(
)
.
Lex
(
)
;
Operands
.
push_back
(
X86Operand
::
CreateToken
(
"*"
)
)
;
}
Operands
.
push_back
(
X86Operand
(
)
)
;
if
(
ParseOperand
(
Operands
.
back
(
)
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
Operands
.
push_back
(
X86Operand
(
)
)
;
if
(
ParseOperand
(
Operands
.
back
(
)
)
)
return
true
;
}
}
if
(
!
MatchInstruction
(
Operands
,
Inst
)
)
return
false
;
Error
(
Loc
,
"unrecognized instruction"
)
;
return
true
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasPerfMon ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , StrictAlign ( false ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI . getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; assert ( ! MFI . getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI . getObjectSize ( I ) , MaxAlign ) ; if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI . getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return alignTo ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Branch Coalescing"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCLoopPreIncPrepPass ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoops ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>


<s> bool isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const override { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


Return an array that contains the direct target flag values and their names .


<s>
AArch64TTI
::
PopcntSupportKind
AArch64TTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
TyWidth
==
32
||
TyWidth
==
64
)
return
PSK_FastHardware
;
return
PSK_Software
;
}
</s>

Return hardware support for population count .


<s>
TargetTransformInfo
::
PopcntSupportKind
SystemZTTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Type width must be power of 2"
)
;
if
(
ST
->
hasPopulationCount
(
)
&&
TyWidth
<=
64
)
return
TTI
::
PSK_FastHardware
;
return
TTI
::
PSK_Software
;
}
</s>

SystemZ
SystemZ
"Type width must be power of 2"
64


<s> static rtx loongarch_legitimize_tls_address ( rtx loc ) { rtx dest , tp , tmp , tmp1 , tmp2 , tmp3 ; enum tls_model model = SYMBOL_REF_TLS_MODEL ( loc ) ; rtx_insn * insn ; switch ( model ) { case TLS_MODEL_LOCAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; insn = loongarch_call_tls_get_addr ( loc , SYMBOL_TLSLDM , tmp ) ; emit_libcall_block ( insn , dest , tmp , loc ) ; break ; case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; insn = loongarch_call_tls_get_addr ( loc , SYMBOL_TLSGD , tmp ) ; emit_libcall_block ( insn , dest , tmp , loc ) ; break ; case TLS_MODEL_INITIAL_EXEC : { tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp1 = gen_reg_rtx ( Pmode ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_EXPLICIT_RELOCS ) { tmp2 = loongarch_unspec_address ( loc , SYMBOL_TLS_IE ) ; tmp3 = gen_reg_rtx ( Pmode ) ; rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( tmp2 ) ) ; high = loongarch_force_temporary ( tmp3 , high ) ; if ( TARGET_CMODEL_EXTREME ) { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; rtx tmp3 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_low ( Pmode , tmp3 , gen_rtx_REG ( Pmode , 0 ) , tmp2 ) ) ; emit_insn ( gen_lui_h_lo20 ( tmp3 , tmp3 , tmp2 ) ) ; emit_insn ( gen_lui_h_hi12 ( tmp3 , tmp3 , tmp2 ) ) ; emit_move_insn ( tmp1 , gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , high , tmp3 ) ) ) ; } else emit_insn ( gen_ld_from_got ( Pmode , tmp1 , high , tmp2 ) ) ; } else emit_insn ( loongarch_got_load_tls_ie ( tmp1 , loc ) ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; } break ; case TLS_MODEL_LOCAL_EXEC : { tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp1 = gen_reg_rtx ( Pmode ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_EXPLICIT_RELOCS ) { tmp2 = loongarch_unspec_address ( loc , SYMBOL_TLS_LE ) ; tmp3 = gen_reg_rtx ( Pmode ) ; rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( tmp2 ) ) ; high = loongarch_force_temporary ( tmp3 , high ) ; emit_insn ( gen_ori_l_lo12 ( Pmode , tmp1 , high , tmp2 ) ) ; if ( TARGET_CMODEL_EXTREME ) { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; emit_insn ( gen_lui_h_lo20 ( tmp1 , tmp1 , tmp2 ) ) ; emit_insn ( gen_lui_h_hi12 ( tmp1 , tmp1 , tmp2 ) ) ; } } else emit_insn ( loongarch_got_load_tls_le ( tmp1 , loc ) ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; } break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread-local SYMBOL_REF , and return its address . The return value will be both a valid address and a valid SET_SRC ( either a REG or a LO_SUM ) .


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADDCARRY
:
IsSelected
=
selectAddCarry
(
N
)
;
break
;
case
ISD
::
SUBCARRY
:
IsSelected
=
selectSubCarry
(
N
)
;
break
;
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

CSKY
CSKY
"== "
"\n"
1
ISD::ADDCARRY
ISD::SUBCARRY


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( ( VT == MVT :: v32i1 || VT == MVT :: v64i1 ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; int arg_size ; if ( ! TARGET_64BIT ) return 0 ; arg_size = pa_function_arg_size ( arg . mode , arg . type ) ; if ( arg_size > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + arg_size <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool X86PassConfig :: addLegalizeMachineIR ( ) { return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
Subtarget
.
hasVector
(
)
)
VerifyVectorTypes
(
Outs
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> rtx rs6000_find_base_term ( rtx op ) { rtx base ; base = op ; if ( GET_CODE ( base ) == CONST ) base = XEXP ( base , 0 ) ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , 0 ) ; if ( GET_CODE ( base ) == UNSPEC ) switch ( XINT ( base , 1 ) ) { case UNSPEC_TOCREL : case UNSPEC_MACHOPIC_OFFSET : return XVECEXP ( base , 0 , 0 ) ; } return op ; } </s>


<s> void MipsSETargetLowering :: addMSAIntType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: EXTRACT_VECTOR_ELT , Ty , Custom ) ; setOperationAction ( ISD :: INSERT_VECTOR_ELT , Ty , Legal ) ; setOperationAction ( ISD :: BUILD_VECTOR , Ty , Custom ) ; setOperationAction ( ISD :: ADD , Ty , Legal ) ; setOperationAction ( ISD :: AND , Ty , Legal ) ; setOperationAction ( ISD :: CTLZ , Ty , Legal ) ; setOperationAction ( ISD :: CTPOP , Ty , Legal ) ; setOperationAction ( ISD :: MUL , Ty , Legal ) ; setOperationAction ( ISD :: OR , Ty , Legal ) ; setOperationAction ( ISD :: SDIV , Ty , Legal ) ; setOperationAction ( ISD :: SREM , Ty , Legal ) ; setOperationAction ( ISD :: SHL , Ty , Legal ) ; setOperationAction ( ISD :: SRA , Ty , Legal ) ; setOperationAction ( ISD :: SRL , Ty , Legal ) ; setOperationAction ( ISD :: SUB , Ty , Legal ) ; setOperationAction ( ISD :: SMAX , Ty , Legal ) ; setOperationAction ( ISD :: SMIN , Ty , Legal ) ; setOperationAction ( ISD :: UDIV , Ty , Legal ) ; setOperationAction ( ISD :: UREM , Ty , Legal ) ; setOperationAction ( ISD :: UMAX , Ty , Legal ) ; setOperationAction ( ISD :: UMIN , Ty , Legal ) ; setOperationAction ( ISD :: VECTOR_SHUFFLE , Ty , Custom ) ; setOperationAction ( ISD :: VSELECT , Ty , Legal ) ; setOperationAction ( ISD :: XOR , Ty , Legal ) ; if ( Ty == MVT :: v4i32 || Ty == MVT :: v2i64 ) { setOperationAction ( ISD :: FP_TO_SINT , Ty , Legal ) ; setOperationAction ( ISD :: FP_TO_UINT , Ty , Legal ) ; setOperationAction ( ISD :: SINT_TO_FP , Ty , Legal ) ; setOperationAction ( ISD :: UINT_TO_FP , Ty , Legal ) ; } setOperationAction ( ISD :: SETCC , Ty , Legal ) ; setCondCodeAction ( ISD :: SETNE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGT , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGT , Ty , Expand ) ; } </s>

Enable MSA support for the given integer type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::BITCAST ISD::LOAD ISD::STORE ISD::EXTRACT_VECTOR_ELT ISD::INSERT_VECTOR_ELT ISD::BUILD_VECTOR ISD::ADD ISD::AND ISD::CTLZ ISD::CTPOP ISD::MUL ISD::OR ISD::SDIV ISD::SREM ISD::SHL ISD::SRA ISD::SRL ISD::SUB ISD::SMAX ISD::SMIN ISD::UDIV ISD::UREM ISD::UMAX ISD::UMIN ISD::VECTOR_SHUFFLE ISD::VSELECT ISD::XOR MVT::v4i32 MVT::v2i64 ISD::FP_TO_SINT ISD::FP_TO_UINT ISD::SINT_TO_FP ISD::UINT_TO_FP ISD::SETCC ISD::SETNE ISD::SETGE ISD::SETGT ISD::SETUGE ISD::SETUGT


<s> static void arm_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , bool acq ) { rtx ( * gen ) ( rtx , rtx ) ; if ( acq ) { switch ( mode ) { case QImode : gen = gen_arm_load_acquire_exclusiveqi ; break ; case HImode : gen = gen_arm_load_acquire_exclusivehi ; break ; case SImode : gen = gen_arm_load_acquire_exclusivesi ; break ; case DImode : gen = gen_arm_load_acquire_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case QImode : gen = gen_arm_load_exclusiveqi ; break ; case HImode : gen = gen_arm_load_exclusivehi ; break ; case SImode : gen = gen_arm_load_exclusivesi ; break ; case DImode : gen = gen_arm_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen ( rval , mem ) ) ; } </s>

Emit the load-exclusive and store-exclusive instructions . Use acquire and release versions if necessary .


<s> static void mips_get_arg_info ( struct mips_arg_info * info , const CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type , bool named ) { bool doubleword_aligned_p ; unsigned int num_bytes , num_words , max_regs ; num_bytes = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; num_words = ( num_bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; switch ( mips_abi ) { case ABI_EABI : info -> fpr_p = ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == V2SFmode ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_32 : case ABI_O64 : gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode ) ; info -> fpr_p = ( ! cum -> gp_reg_found && cum -> arg_number < 2 && ( type == 0 || SCALAR_FLOAT_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == V2SFmode ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_N32 : case ABI_64 : gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode ) ; info -> fpr_p = ( named && ( type == 0 || FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || mode == V2SFmode ) && GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; if ( info -> fpr_p && GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_UNIT_SIZE ( mode ) < UNITS_PER_FPVALUE ) { if ( cum -> num_gprs >= MAX_ARGS_IN_REGISTERS - 1 ) info -> fpr_p = false ; else num_words = 2 ; } break ; default : gcc_unreachable ( ) ; } doubleword_aligned_p = ( mips_function_arg_boundary ( mode , type ) > BITS_PER_WORD ) ; info -> reg_offset = ( mips_abi == ABI_EABI && info -> fpr_p ? cum -> num_fprs : cum -> num_gprs ) ; if ( doubleword_aligned_p ) info -> reg_offset += info -> reg_offset & 1 ; info -> stack_offset = cum -> stack_words ; if ( doubleword_aligned_p ) info -> stack_offset += info -> stack_offset & 1 ; max_regs = MAX_ARGS_IN_REGISTERS - info -> reg_offset ; info -> reg_words = MIN ( num_words , max_regs ) ; info -> stack_words = num_words - info -> reg_words ; } </s>

Fill INFO with information about a single argument . CUM is the cumulative state for earlier arguments . MODE is the mode of this argument and TYPE is its type ( if known ) . NAMED is true if this is a named ( fixed ) argument rather than a variable one .


Return an appropriate const instance of xlogue_layout based upon values in cfun- > machine and crtl .


<s> void SparcELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> void SparcRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; NumBytes += 92 ; NumBytes = ( NumBytes + 7 ) & ~ 7 ; NumBytes = - NumBytes ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( CC == CallingConv :: Cold ) return CSR_MostRegs_64_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
SDValue
SparcTargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
ConstantPoolSDNode
*
CP
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
CP
->
getConstVal
(
)
,
CP
->
getValueType
(
0
)
,
CP
->
getAlign
(
)
,
CP
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


<s> void updateDebugInfo ( MachineInstr * MI , const DILocation * Loc ) { DebugLoc DL ( Loc ) ; MI -> setDebugLoc ( DL ) ; } </s>

Called to update debug info associated with the instruction .


<s> bool X86TTIImpl :: hasDivRemOp ( Type * DataType , bool IsSigned ) { EVT VT = TLI -> getValueType ( DL , DataType ) ; return TLI -> isOperationLegal ( IsSigned ? ISD :: SDIVREM : ISD :: UDIVREM , VT ) ; } </s>

Return true if the target has a unified operation to calculate division and remainder .


<s> static void aarch64_emit_bic ( machine_mode mode , rtx dst , rtx s1 , rtx s2 , int shift ) { rtx shift_rtx = GEN_INT ( shift ) ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_SImode : gen = gen_and_one_cmpl_lshrsi3 ; break ; case E_DImode : gen = gen_and_one_cmpl_lshrdi3 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , s2 , shift_rtx , s1 ) ) ; } </s>


<s> bool X86PassConfig :: addPostRegAlloc ( ) { PM -> add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void PPCAIXAsmPrinter :: emitXXStructorList ( const DataLayout & DL , const Constant * List , bool IsCtor ) { SmallVector < Structor , 8 > Structors ; preprocessXXStructorList ( DL , List , Structors ) ; if ( Structors . empty ( ) ) return ; unsigned Index = 0 ; for ( Structor & S : Structors ) { if ( const ConstantExpr * CE = dyn_cast < ConstantExpr > ( S . Func ) ) S . Func = CE -> getOperand ( 0 ) ; llvm :: GlobalAlias :: create ( GlobalValue :: ExternalLinkage , ( IsCtor ? llvm :: Twine ( "__sinit" ) : llvm :: Twine ( "__sterm" ) ) + llvm :: Twine ( convertToSinitPriority ( S . Priority ) ) + llvm :: Twine ( "_" , FormatIndicatorAndUniqueModId ) + llvm :: Twine ( "_" , llvm :: utostr ( Index ++ ) ) , cast < Function > ( S . Func ) ) ; } } </s>

This method emits llvm.global_ctors or llvm.global_dtors list .


<s> bool ix86_check_builtin_isa_match ( unsigned int fcode , HOST_WIDE_INT * pbisa , HOST_WIDE_INT * pbisa2 ) { HOST_WIDE_INT isa = ix86_isa_flags ; HOST_WIDE_INT isa2 = ix86_isa_flags2 ; HOST_WIDE_INT bisa = ix86_builtins_isa [ fcode ] . isa ; HOST_WIDE_INT bisa2 = ix86_builtins_isa [ fcode ] . isa2 ; if ( ( ( bisa & ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) == ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) && ( isa & ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) != 0 ) isa |= ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) == ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) && ( isa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) != 0 ) isa |= ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) == ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) && ( isa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) != 0 ) isa |= ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ; if ( ( ( ( bisa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( bisa2 & OPTION_MASK_ISA2_AVXVNNI ) != 0 ) && ( ( ( isa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( isa2 & OPTION_MASK_ISA2_AVXVNNI ) != 0 ) ) { isa |= OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXVNNI ; } if ( ( ( ( bisa & ( OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ) ) || ( bisa2 & OPTION_MASK_ISA2_AVXIFMA ) != 0 ) && ( ( ( isa & ( OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ) ) || ( isa2 & OPTION_MASK_ISA2_AVXIFMA ) != 0 ) ) { isa |= OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXIFMA ; } if ( ( ( ( bisa & OPTION_MASK_ISA_AVX512VL ) != 0 && ( bisa2 & OPTION_MASK_ISA2_AVX512BF16 ) != 0 ) && ( bisa2 & OPTION_MASK_ISA2_AVXNECONVERT ) != 0 ) && ( ( ( isa & OPTION_MASK_ISA_AVX512VL ) != 0 && ( isa2 & OPTION_MASK_ISA2_AVX512BF16 ) != 0 ) || ( isa2 & OPTION_MASK_ISA2_AVXNECONVERT ) != 0 ) ) { isa |= OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16 ; } if ( ( bisa & OPTION_MASK_ISA_MMX ) && ! TARGET_MMX && TARGET_MMX_WITH_SSE && fcode != IX86_BUILTIN_MASKMOVQ ) { bisa &= ~ OPTION_MASK_ISA_MMX ; bisa |= OPTION_MASK_ISA_SSE2 ; } if ( pbisa ) * pbisa = bisa ; if ( pbisa2 ) * pbisa2 = bisa2 ; return ( bisa & isa ) == bisa && ( bisa2 & isa2 ) == bisa2 ; } </s>

Return true if the necessary isa options for this builtin exist , else false . fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ;


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> void LC2200FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const LC2200RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxStackAlign = std :: max ( StackAlign , MFI . getMaxAlignment ( ) ) ; FrameSize += ( MaxStackAlign - StackAlign ) ; StackAlign = MaxStackAlign ; } uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> int check_use_sfunc_addr ( rtx insn , rtx reg ) { while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( GET_CODE ( insn ) == CODE_LABEL || GET_CODE ( insn ) == JUMP_INSN ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ; if ( GET_CODE ( PATTERN ( insn ) ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) continue ; return rtx_equal_p ( extract_sfunc_addr ( insn ) , reg ) ; } gcc_unreachable ( ) ; } </s>

Verify that the register in use_sfunc_addr still agrees with the address used in the sfunc . This prevents fill_slots_from_thread from changing use_sfunc_addr . INSN is the use_sfunc_addr instruction , and REG is the register it guards .


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { const SystemZSubtarget & ST = F . getSubtarget < SystemZSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> const MCExpr * ARMTargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr ) { return ConstantPools -> addEntry ( Streamer , Expr ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


Return the union class of CLASS1 and CLASS2 . See the x86-64 PS ABI for details .


<s> static unsigned int aarch64_detect_scalar_stmt_subtype ( vec_info * vinfo , vect_cost_for_stmt kind , stmt_vec_info stmt_info , unsigned int stmt_cost ) { if ( kind == scalar_stmt && aarch64_extending_load_p ( vinfo , stmt_info ) ) return 0 ; return stmt_cost ; } </s>

STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost for STMT_INFO , which has cost kind KIND . If this is a scalar operation , try to subdivide the target-independent categorization provided by KIND to get a more accurate cost .


<s> bool X86TargetLowering :: isNarrowingProfitable ( EVT VT1 , EVT VT2 ) const { return ! ( VT1 == MVT :: i32 && VT2 == MVT :: i16 ) ; } </s>

Return true if it 's profitable to narrow operations of type SrcVT to DestVT .


<s> bool mips_const_vector_bitimm_clr_p ( rtx op , machine_mode mode ) { if ( GET_CODE ( op ) == CONST_VECTOR && op != CONSTM1_RTX ( mode ) ) { unsigned HOST_WIDE_INT val = ~ UINTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) ; int vlog2 = exact_log2 ( val & GET_MODE_MASK ( GET_MODE_INNER ( mode ) ) ) ; if ( vlog2 != - 1 ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) ; gcc_assert ( vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE ( mode ) - 1 ) ; return mips_const_vector_same_val_p ( op , mode ) ; } } return false ; } </s>

Return true if OP is a constant vector with the number of units in MODE , and each unit has the same bit clear .


<s> static bool mmix_rtx_costs ( rtx x ATTRIBUTE_UNUSED , int code ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return false ; } </s>


<s>
unsigned
MipsCodeEmitter
::
getBranchTarget26OpValue
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
llvm_unreachable
(
"Unimplemented function."
)
;
return
0
;
}
</s>

getBranchTarget26OpValue - Return binary encoding of the branch target operand .


<s> static unsigned int flags_from_code ( enum rtx_code code ) { switch ( code ) { case LT : case GE : return CC_FLAG_S ; case GT : case LE : return CC_FLAG_S | CC_FLAG_O | CC_FLAG_Z ; case GEU : case LTU : return CC_FLAG_C ; case GTU : case LEU : return CC_FLAG_C | CC_FLAG_Z ; case EQ : case NE : return CC_FLAG_Z ; default : gcc_unreachable ( ) ; } } </s>

Convert an RTX_CODE to the set of flags needed to implement it . This assumes an integer comparison .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> int getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const override { return PPCGenInstrInfo :: getOperandLatency ( ItinData , DefNode , DefIdx , UseNode , UseIdx ) ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s>
void
CSKYInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
CSKYMachineFunctionInfo
*
CFI
=
MF
.
getInfo
<
CSKYMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
LD32W
;
}
else
if
(
CSKY
::
CARRYRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
RESTORE_CARRY
;
CFI
->
setSpillsCR
(
)
;
}
else
{
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> char * iq2000_output_conditional_branch ( rtx insn , rtx * operands , int two_operands_p , int float_p , int inverted_p , int length ) { static char buffer [ 200 ] ; enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; int need_z_p ; const char * op1 = "%z2" ; const char * op2 = ( two_operands_p ? ",%z3" : ",%." ) ; const char * comp = ( float_p ? "%F0" : "%C0" ) ; const char * inverted_comp = ( float_p ? "%W0" : "%N0" ) ; iq2000_branch_likely = ( final_sequence && INSN_ANNULLED_BRANCH_P ( insn ) ) ; if ( ! two_operands_p ) { switch ( code ) { case GTU : code = NE ; break ; case LEU : code = EQ ; break ; case GEU : code = EQ ; op1 = "%." ; break ; case LTU : code = NE ; op1 = "%." ; break ; default : break ; } } need_z_p = ( ! float_p && code != EQ && code != NE ) ; if ( need_z_p ) op2 = "" ; buffer [ 0 ] = '\0' ; switch ( length ) { case 4 : case 8 : if ( float_p ) sprintf ( buffer , "b%s%%?\t%%Z2%%1" , inverted_p ? inverted_comp : comp ) ; else sprintf ( buffer , "b%s%s%%?\t%s%s,%%1" , inverted_p ? inverted_comp : comp , need_z_p ? "z" : "" , op1 , op2 ) ; return buffer ; case 12 : case 16 : { const char * target = ( ( iq2000_branch_likely || length == 16 ) ? ".+16" : ".+12" ) ; char * c ; c = strchr ( buffer , '\0' ) ; if ( float_p ) sprintf ( c , "b%s\t%%Z2%s" , inverted_p ? comp : inverted_comp , target ) ; else sprintf ( c , "b%s%s\t%s%s,%s" , inverted_p ? comp : inverted_comp , need_z_p ? "z" : "" , op1 , op2 , target ) ; strcat ( c , "\n\tnop\n\tj\t%1" ) ; if ( length == 16 ) strcat ( buffer , "\n\tnop" ) ; return buffer ; } default : gcc_unreachable ( ) ; } return 0 ; } </s>

Output assembly instructions to perform a conditional branch . INSN is the branch instruction . OPERANDS [ 0 ] is the condition . OPERANDS [ 1 ] is the target of the branch . OPERANDS [ 2 ] is the target of the first operand to the condition . If TWO_OPERANDS_P is nonzero the comparison takes two operands ; OPERANDS [ 3 ] will be the second operand . If INVERTED_P is nonzero we are to branch if the condition does not hold . If FLOAT_P is nonzero this is a floating-point comparison . LENGTH is the length ( in bytes ) of the sequence we are to generate . That tells us whether to generate a simple conditional branch , or a reversed conditional branch around a ` jr ' instruction .


<s> void MipsAsmPrinter :: emitFrameDirective ( MachineFunction & MF ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; O << "\t.frame\t" << '$' << LowercaseString ( RI . get ( stackReg ) . AsmName ) << ',' << stackSize << ',' << '$' << LowercaseString ( RI . get ( returnReg ) . AsmName ) << '\n' ; } </s>


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'v' : case 'Y' : case 'l' : case 'k' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'Y' : switch ( Constraint [ 1 ] ) { default : break ; case 'z' : case '0' : return C_Register ; case 'i' : case 'm' : case 'k' : case 't' : case '2' : return C_RegisterClass ; } } } else if ( parseConstraintCode ( Constraint ) != X86 :: COND_INVALID ) return C_Other ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; return STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ; } </s>

Return true if the specified instruction can be predicated .


<s> void nds32_init_expanders ( void ) { init_machine_status = nds32_init_machine_status ; } </s>

Defining Data Structures for Per-function Information .


<s> static const char * arm_identify_fpu_from_isa ( sbitmap isa ) { auto_sbitmap fpubits ( isa_num_bits ) ; auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits_internal ) ; if ( bitmap_empty_p ( fpubits ) ) return "softvfp" ; for ( unsigned int i = 0 ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ; if ( bitmap_equal_p ( fpubits , cand_fpubits ) ) return all_fpus [ i ] . name ; } gcc_unreachable ( ) ; } </s>

Match an ISA feature bitmap to a named FPU . We always use the first entry that exactly matches the feature set , so that we effectively canonicalize the FPU name for the assembler .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> int AArch64TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static inline bool save_global_or_fp_reg_p ( unsigned int regno , int leaf_function ATTRIBUTE_UNUSED ) { return ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ; } </s>

Return whether REGNO , a global or FP register , must be saved/restored .


"PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."

"PRINT_OPERAND_ADDRESS, invalid insn #2"

"PRINT_OPERAND_ADDRESS, invalid insn #1"

Print the operand address represented by the rtx addr


runOnMachineFunction - Emit the function body .


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; ProcessFunctionAfterISel ( MF ) ; return Ret ; } </s>


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; InsertNOPLoad = false ; FixFSMULD = false ; ReplaceFMULS = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , ( MCFixupKind ) Mips :: fixup_Mips_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_CALL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_HI16 ) . Case ( "R_MIPS_CALL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_LO16 ) . Case ( "R_MIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL16 ) . Case ( "R_MIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_OFST ) . Case ( "R_MIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_DISP ) . Case ( "R_MIPS_GOT_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_HI16 ) . Case ( "R_MIPS_GOT_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_LO16 ) . Case ( "R_MIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_Mips_GOTTPREL ) . Case ( "R_MIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_HI ) . Case ( "R_MIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_LO ) . Case ( "R_MIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_Mips_TLSGD ) . Case ( "R_MIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_Mips_TLSLDM ) . Case ( "R_MIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_HI ) . Case ( "R_MIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_LO ) . Case ( "R_MICROMIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_CALL16 ) . Case ( "R_MICROMIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_DISP ) . Case ( "R_MICROMIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_PAGE ) . Case ( "R_MICROMIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_OFST ) . Case ( "R_MICROMIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT16 ) . Case ( "R_MICROMIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOTTPREL ) . Case ( "R_MICROMIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 ) . Case ( "R_MICROMIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_GD ) . Case ( "R_MICROMIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_LDM ) . Case ( "R_MICROMIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( 4 - i - 1 ) * 8 ) ) & 0xff ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool Cpu0TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


"cannot use %<va_start%> in interrupt function"

Implement the stdarg/varargs va_start macro . STDARG_P is non-zero if this is stdarg.h instead of varargs.h . VALIST is the tree of the va_list variable to initialize . NEXTARG is the machine independent notion of the 'next ' argument after the variable arguments .


<s>
static
void
ix86_output_indirect_branch_via_push
(
rtx
call_op
,
const
char
*
xasm
,
bool
sibcall_p
)
{
char
thunk_name_buf
[
32
]
;
char
*
thunk_name
;
char
push_buf
[
64
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
int
regno
=
1
;
if
(
cfun
->
machine
->
indirect_branch_type
!=
indirect_branch_thunk_inline
)
{
if
(
cfun
->
machine
->
indirect_branch_type
==
indirect_branch_thunk
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
indirect_thunk_bnd_needed
=
true
;
else
indirect_thunk_needed
=
true
;
}
indirect_thunk_name
(
thunk_name_buf
,
regno
,
need_prefix
,
false
)
;
thunk_name
=
thunk_name_buf
;
}
else
thunk_name
=
;
snprintf
(
push_buf
,
sizeof
(
push_buf
)
,
"push{%c}\t%s"
,
TARGET_64BIT
'q'
:
'l'
,
xasm
)
;
if
(
sibcall_p
)
{
output_asm_insn
(
push_buf
,
&
call_op
)
;
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
}
else
{
char
indirectlabel1
[
32
]
;
char
indirectlabel2
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel1
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel2
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd jmp\t"
,
asm_out_file
)
;
else
fputs
(
"\tjmp\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel2
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel1
)
;
if
(
MEM_P
(
call_op
)
)
{
struct
ix86_address
parts
;
rtx
addr
=
XEXP
(
call_op
,
0
)
;
if
(
ix86_decompose_address
(
addr
,
&
parts
)
&&
parts
.
base
==
stack_pointer_rtx
)
{
if
(
parts
.
index
)
{
addr
=
gen_rtx_MULT
(
Pmode
,
parts
.
index
,
GEN_INT
(
parts
.
scale
)
)
;
addr
=
gen_rtx_PLUS
(
Pmode
,
stack_pointer_rtx
,
addr
)
;
}
else
addr
=
stack_pointer_rtx
;
rtx
disp
;
if
(
parts
.
disp
!=
NULL_RTX
)
disp
=
plus_constant
(
Pmode
,
parts
.
disp
,
UNITS_PER_WORD
)
;
else
disp
=
GEN_INT
(
UNITS_PER_WORD
)
;
addr
=
gen_rtx_PLUS
(
Pmode
,
addr
,
disp
)
;
call_op
=
gen_rtx_MEM
(
GET_MODE
(
call_op
)
,
addr
)
;
}
}
output_asm_insn
(
push_buf
,
&
call_op
)
;
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel2
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd call\t"
,
asm_out_file
)
;
else
fputs
(
"\tcall\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel1
)
;
fputc
(
'\n'
,
asm_out_file
)
;
}
}
</s>

Output indirect branch via a call and return thunk . CALL_OP is the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : jmp L2 L1 : push CALL_OP jmp __x86_indirect_thunk L2 : call L1 and a tail call is converted to : push CALL_OP jmp __x86_indirect_thunk


<s> static void thumb_set_frame_pointer ( arm_stack_offsets * offsets ) { HOST_WIDE_INT amount ; rtx insn , dwarf ; amount = offsets -> outgoing_args - offsets -> locals_base ; if ( amount < 1024 ) insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { emit_insn ( gen_movsi ( hard_frame_pointer_rtx , GEN_INT ( amount ) ) ) ; if ( TARGET_THUMB2 ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } else { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; } dwarf = gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , amount ) ) ; RTX_FRAME_RELATED_P ( dwarf ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Set the Thumb frame pointer from the stack pointer .


<s> static bool in_same_chain ( rtx_insn * insn , rtx_insn * cand , unsigned regno ) { struct du_chain * chain = NULL ; du_head_p head = NULL ; int i ; operand_rr_info * op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; for ( i = 0 ; i < op_info -> n_chains ; i ++ ) { if ( op_info -> heads [ i ] -> regno != regno ) continue ; head = op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; bool found_insn = false , found_cand = false ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { rtx * loc = & SET_DEST ( PATTERN ( chain -> insn ) ) ; if ( chain -> loc != loc ) continue ; if ( chain -> insn == insn ) found_insn = true ; if ( chain -> insn == cand ) found_cand = true ; if ( found_insn && found_cand ) return true ; } } return false ; } </s>

Return whether INSN and CAND are in the same def/use chain .


<s>
static
const
char
*
rs6000_invalid_within_doloop
(
rtx
insn
)
{
if
(
CALL_P
(
insn
)
)
return
"Function call in the loop."
;
if
(
JUMP_P
(
insn
)
&&
(
GET_CODE
(
PATTERN
(
insn
)
)
==
ADDR_DIFF_VEC
||
GET_CODE
(
PATTERN
(
insn
)
)
==
ADDR_VEC
)
)
return
"Computed branch in the loop."
;
return
;
}
</s>

NULL if INSN insn is valid within a low-overhead loop . Otherwise return why doloop can not be applied . PowerPC uses the COUNT register for branch on table instructions .

rs6000
"Function call in the loop."
"Computed branch in the loop."


<s> static rsqrte_type get_rsqrte_type ( machine_mode mode ) { switch ( mode ) { case E_DFmode : return gen_aarch64_rsqrtedf ; case E_SFmode : return gen_aarch64_rsqrtesf ; case E_V2DFmode : return gen_aarch64_rsqrtev2df ; case E_V2SFmode : return gen_aarch64_rsqrtev2sf ; case E_V4SFmode : return gen_aarch64_rsqrtev4sf ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root initial estimate insn depending on machine mode .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { const uint64_t SpillSize = 4 ; const int64_t SpillOffset = Subtarget . isPPC64 ( ) ? 8 : Subtarget . isAIXABI ( ) ? 4 : - 4 ; int FrameIdx = MFI . CreateFixedObject ( SpillSize , SpillOffset , true , false ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"Wasn't expecting to be able to lower this!"


<s> void LEGRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case LEG :: LDR : case LEG :: STR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) + ImmOp . getImm ( ) ; FIOp . ChangeToRegister ( LEG :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool mips_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( GET_MODE_SIZE ( from ) == 8 && GET_MODE_SIZE ( to ) == 8 && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return false ; if ( MSA_SUPPORTED_MODE_P ( from ) && MSA_SUPPORTED_MODE_P ( to ) ) return false ; return reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


<s> enum reg_class coproc_secondary_reload_class ( machine_mode mode , rtx x , bool wb ) { if ( mode == HFmode ) { if ( ! TARGET_NEON_FP16 ) return GENERAL_REGS ; if ( s_register_operand ( x , mode ) || neon_vector_mem_operand ( x , 2 , true ) ) return NO_REGS ; return GENERAL_REGS ; } if ( TARGET_NEON && ( MEM_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || VALID_NEON_STRUCT_MODE ( mode ) ) ) return NO_REGS ; if ( arm_coproc_mem_operand ( x , wb ) || s_register_operand ( x , mode ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return GENERAL_REGS if a scratch register required to reload x to/from coprocessor registers . Otherwise return NO_REGS .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAtLeastAcquire ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> static SDValue PerformIntrinsicCombine ( SDNode * N , SelectionDAG & DAG ) { unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case Intrinsic :: arm_neon_vqshifts : case Intrinsic :: arm_neon_vqshiftu : EVT VT = N -> getOperand ( 1 ) . getValueType ( ) ; int64_t Cnt ; if ( ! isVShiftLImm ( N -> getOperand ( 2 ) , VT , Cnt ) ) break ; unsigned VShiftOpc = ( IntNo == Intrinsic :: arm_neon_vqshifts ) ? AArch64ISD :: NEON_QSHLs : AArch64ISD :: NEON_QSHLu ; return DAG . getNode ( VShiftOpc , SDLoc ( N ) , N -> getValueType ( 0 ) , N -> getOperand ( 1 ) , DAG . getConstant ( Cnt , MVT :: i32 ) ) ; } return SDValue ( ) ; } </s>

PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
const
char
*
arm_output_shift
(
rtx
*
operands
,
int
set_flags
)
{
char
pattern
[
100
]
;
static
const
char
flag_chars
[
3
]
=
{
'?'
,
'.'
,
'!'
}
;
const
char
*
shift
;
HOST_WIDE_INT
val
;
char
c
;
c
=
flag_chars
[
set_flags
]
;
if
(
TARGET_UNIFIED_ASM
)
{
shift
=
shift_op
(
operands
[
3
]
,
&
val
)
;
if
(
shift
)
{
if
(
val
!=
1
)
operands
[
2
]
=
GEN_INT
(
val
)
;
sprintf
(
pattern
,
"%s%%%c\t%%0, %%1, %%2"
,
shift
,
c
)
;
}
else
sprintf
(
pattern
,
"mov%%%c\t%%0, %%1"
,
c
)
;
}
else
sprintf
(
pattern
,
"mov%%%c\t%%0, %%1%%S3"
,
c
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output assembly for a shift instruction . SET_FLAGS determines how the instruction modifies the condition codes . 0 - Do not set condition codes . 1 - Set condition codes . 2 - Use smallest instruction .


<s> bool ARM64TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) return false ; if ( Ptr != Base ) return false ; AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed_indeed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode ; int fp_reg_size = 8 ; int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> void AArch64TargetELFStreamer :: emitDirectiveVariantPCS ( MCSymbol * Symbol ) { cast < MCSymbolELF > ( Symbol ) -> setOther ( ELF :: STO_AARCH64_VARIANT_PCS ) ; } </s>

Callback used to implement the .variant_pcs directive .


<s> bool MipsAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; if ( StringRef ( constraint ) == "wc" && type -> isIntegerTy ( 1 ) ) return CW_Register ; else if ( ( StringRef ( constraint ) == "wa" || StringRef ( constraint ) == "wd" || StringRef ( constraint ) == "wf" ) && type -> isVectorTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "ws" && type -> isDoubleTy ( ) ) return CW_Register ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
void
xstormy16_asm_output_aligned_common
(
FILE
*
stream
,
tree
decl
,
const
char
*
name
,
int
size
,
int
align
,
int
global
)
{
rtx
mem
=
DECL_RTL
(
decl
)
;
rtx
symbol
;
if
(
mem
!=
NULL_RTX
&&
GET_CODE
(
mem
)
==
MEM
&&
GET_CODE
(
symbol
=
XEXP
(
mem
,
0
)
)
==
SYMBOL_REF
&&
SYMBOL_REF_FLAGS
(
symbol
)
&
SYMBOL_FLAG_XSTORMY16_BELOW100
)
{
const
char
*
name2
;
int
p2align
=
0
;
bss100_section
(
)
;
while
(
align
>
8
)
{
align
/=
2
;
p2align
++
;
}
name2
=
default_strip_name_encoding
(
name
)
;
if
(
global
)
fprintf
(
stream
,
"\t.globl\t%s\n"
,
name2
)
;
if
(
p2align
)
fprintf
(
stream
,
"\t.p2align %d\n"
,
p2align
)
;
fprintf
(
stream
,
"\t.type\t%s, @object\n"
,
name2
)
;
fprintf
(
stream
,
"\t.size\t%s, %d\n"
,
name2
,
size
)
;
fprintf
(
stream
,
"%s:\n\t.space\t%d\n"
,
name2
,
size
)
;
return
;
}
if
(
!
global
)
{
fprintf
(
stream
,
"\t.local\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
fprintf
(
stream
,
"\t.comm\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
",%u,%u\n"
,
size
,
align
/
BITS_PER_UNIT
)
;
}
</s>

The purpose of this function is to override the default behavior of BSS objects . Normally , they go into .bss or .sbss via `` .common '' directives , but we need to override that and put them in .bss_below100 . We ca n't just use a section override ( like we do for .data_below100 ) , because that makes them initialized rather than uninitialized .


<s> rtx aarch64_gen_stepped_int_parallel ( unsigned int nelts , int base , int step ) { rtvec vec = rtvec_alloc ( nelts ) ; for ( unsigned int i = 0 ; i < nelts ; ++ i ) RTVEC_ELT ( vec , i ) = gen_int_mode ( base + i * step , DImode ) ; return gen_rtx_PARALLEL ( VOIDmode , vec ) ; } </s>

Return a PARALLEL containing NELTS elements , with element I equal to BASE + I * STEP .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned MaxAlign = calculateMaxStackAlignment ( FFI ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum ) -> getAlignment ( ) ) ; FFI -> setMaxAlignment ( MaxAlign ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_ShiftExtend
:
{
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> static machine_mode rs6000_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree , int ) { PROMOTE_MODE ( mode , * punsignedp , type ) ; return mode ; } </s>

On rs6000 , function arguments are promoted , as are function return values .


<s> void rs6000_emit_sCOND ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx = rs6000_generate_compare ( operands [ 1 ] , mode ) ; rtx_code cond_code = GET_CODE ( condition_rtx ) ; if ( FLOAT_MODE_P ( mode ) && HONOR_NANS ( mode ) && ! ( FLOAT128_VECTOR_P ( mode ) && ! TARGET_FLOAT128_HW ) ) ; else if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } machine_mode op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 0 ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 1 ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( operands [ 0 ] , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , condition_rtx ) ) ; } } </s>


<s>
static
rtx
loongarch_expand_builtin_insn
(
enum
insn_code
icode
,
unsigned
int
nops
,
struct
expand_operand
*
ops
,
bool
has_target_p
)
{
if
(
!
maybe_expand_insn
(
icode
,
nops
,
ops
)
)
{
error
(
"invalid argument to built-in function"
)
;
return
has_target_p
gen_reg_rtx
(
ops
[
0
]
.
mode
)
:
const0_rtx
;
}
return
has_target_p
ops
[
0
]
.
value
:
const0_rtx
;
}
</s>

Expand instruction ICODE as part of a built-in function sequence . Use the first NOPS elements of OPS as the instruction 's operands . HAS_TARGET_P is true if operand 0 is a target ; it is false if the instruction has no target . Return the target rtx if HAS_TARGET_P , otherwise return const0_rtx .


"X86 Load Value Injection (LVI) Load Hardening (Unoptimized)"

getPassName - Return a nice clean name for a pass .


<s> static unsigned int find_drap_reg ( void ) { tree decl = cfun -> decl ; if ( TARGET_64BIT ) { if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> no_caller_saved_registers || crtl -> tail_call_emit ) return R13_REG ; return R10_REG ; } else { if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> no_caller_saved_registers || crtl -> tail_call_emit || crtl -> calls_eh_return ) return DI_REG ; if ( ix86_function_regparm ( TREE_TYPE ( decl ) , decl ) <= 2 ) { unsigned int ccvt = ix86_get_callcvt ( TREE_TYPE ( decl ) ) ; if ( ( ccvt & ( IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) == 0 ) return CX_REG ; } return DI_REG ; } } </s>

Find an available register to be used as dynamic realign argument pointer regsiter . Such a register will be written in prologue and used in begin of body , so it must not be 1. parameter passing register . 2 . GOT pointer . We reuse static-chain register if it is available . Otherwise , we use DI for i386 and R13 for x86-64 . We chose R13 since it has shorter encoding . Return : the regno of chosen register .


<s> bool VERegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const { return false ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s>
void
A57ChainingConstraint
::
apply
(
PBQPRAGraph
&
G
)
{
const
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
LiveIntervals
&
LIs
=
G
.
getMetadata
(
)
.
LIS
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
LLVM_DEBUG
(
MF
.
dump
(
)
)
;
for
(
const
auto
&
MBB
:
MF
)
{
Chains
.
clear
(
)
;
for
(
const
auto
&
MI
:
MBB
)
{
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
regJustKilledBefore
(
LIs
,
r
,
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
printReg
(
r
,
TRI
)
<<
" at "
;
MI
.
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Ra
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
break
;
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .