<s>
bool
ARMBaseInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
instr_iterator
I
=
MBB
.
instr_end
(
)
;
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugInstr
(
)
||
!
I
->
isTerminator
(
)
||
isSpeculationBarrierEndBBOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
}
if
(
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
true
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
instr_end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
if
(
isSpeculationBarrierEndBBOpcode
(
InstToDelete
.
getOpcode
(
)
)
)
continue
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
{
if
(
AllowModify
&&
!
isPredicated
(
MBB
.
back
(
)
)
&&
isUncondBranchOpcode
(
MBB
.
back
(
)
.
getOpcode
(
)
)
&&
TBB
&&
MBB
.
isLayoutSuccessor
(
TBB
)
)
removeBranch
(
MBB
)
;
return
true
;
}
if
(
I
==
MBB
.
instr_begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void function_expander :: add_input_operand ( insn_code icode , rtx x ) { unsigned int opno = m_ops . length ( ) ; const insn_operand_data & operand = insn_data [ icode ] . operand [ opno ] ; machine_mode mode = operand . mode ; if ( mode == VOIDmode ) { gcc_assert ( operand . predicate == aarch64_any_register_operand ) ; mode = GET_MODE ( x ) ; } else if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) && VECTOR_MODE_P ( mode ) ) x = expand_vector_broadcast ( mode , x ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) { gcc_assert ( GET_MODE ( x ) == VNx16BImode ) ; x = gen_lowpart ( mode , x ) ; } m_ops . safe_grow ( m_ops . length ( ) + 1 , true ) ; create_input_operand ( & m_ops . last ( ) , x , mode ) ; } </s>

Create op and add it into M_OPS and increase OPNO .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
MipsSubtarget
::
O32
:
return
"abi32"
;
case
MipsSubtarget
::
O64
:
return
"abiO64"
;
case
MipsSubtarget
::
N32
:
return
"abiN32"
;
case
MipsSubtarget
::
N64
:
return
"abi64"
;
case
MipsSubtarget
::
EABI
:
return
"eabi32"
;
default
:
break
;
}
llvm_unreachable
(
"Unknown Mips ABI"
)
;
return
;
}
</s>


<s> void setMustSaveLR ( bool U ) { MustSaveLR = U ; } </s>

MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function .


<s> void F2003fMCAsmStreamer :: reset ( ) { LabelToEmit . clear ( ) ; ExplicitCommentToEmit . clear ( ) ; CommentToEmit . clear ( ) ; Symbols . clear ( ) ; CurrentAlignmentToValue = 1 ; ValueBuffer . clear ( ) ; MCStreamer :: reset ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


"OR1K DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> unsigned int getNumFixupKinds ( ) const override { return AArch64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
const
char
*
CSKYTargetLowering
::
getTargetNodeName
(
unsigned
Opcode
)
const
{
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"unknown CSKYISD node"
)
;
case
CSKYISD
::
NIE
:
return
"CSKYISD::NIE"
;
case
CSKYISD
::
NIR
:
return
"CSKYISD::NIR"
;
case
CSKYISD
::
RET
:
return
"CSKYISD::RET"
;
case
CSKYISD
::
BITCAST_TO_LOHI
:
return
"CSKYISD::BITCAST_TO_LOHI"
;
}
}
</s>

getTargetNodeName - This method returns the name of a target specific

CSKY
CSKY
"unknown CSKYISD node"
CSKYISD::NIE
"CSKYISD::NIE"
CSKYISD::NIR
"CSKYISD::NIR"
CSKYISD::RET
"CSKYISD::RET"
CSKYISD::BITCAST_TO_LOHI
"CSKYISD::BITCAST_TO_LOHI"


<s> bool hasFP ( const MachineFunction & MF ) const override { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool ARMBaseInstrInfo :: isPredicated ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 && I -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ) return true ; } return false ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ; } </s>

Returns true if the instruction is already predicated .


Return the opcode of the special instruction to be used to load the constant X .


<s> static void emit_hard_tfmode_operation ( enum rtx_code code , rtx * operands ) { rtx op , dest ; if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) { operands [ 1 ] = force_reg ( GET_MODE ( operands [ 1 ] ) , operands [ 1 ] ) ; op = gen_rtx_fmt_e ( code , GET_MODE ( operands [ 0 ] ) , operands [ 1 ] ) ; } else { operands [ 1 ] = force_reg ( GET_MODE ( operands [ 1 ] ) , operands [ 1 ] ) ; operands [ 2 ] = force_reg ( GET_MODE ( operands [ 2 ] ) , operands [ 2 ] ) ; op = gen_rtx_fmt_ee ( code , GET_MODE ( operands [ 0 ] ) , operands [ 1 ] , operands [ 2 ] ) ; } if ( register_operand ( operands [ 0 ] , VOIDmode ) ) dest = operands [ 0 ] ; else dest = gen_reg_rtx ( GET_MODE ( operands [ 0 ] ) ) ; emit_insn ( gen_rtx_SET ( dest , op ) ) ; if ( dest != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dest ) ; } </s>

Expand a hard-float tfmode operation . All arguments must be in registers .


"Error: found feature bits in the ALL_FPU_INTERAL"

" group that are not defined by any FPU.\n"

Scan the static data tables generated by parsecpu.awk looking for potential issues with the data . Here we check for consistency between the fpu bits , in particular we check that ISA_ALL_FPU_INTERNAL does not contain a feature bit that is not defined by any FPU flag .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
IsAndroid
(
false
)
,
RM
(
_RM
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s>
unsigned
SHUXIMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
if
(
MO
.
isExpr
(
)
)
{
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Constant
)
{
return
cast
<
MCConstantExpr
>
(
Expr
)
->
getValue
(
)
;
}
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;
SHUXI
::
Fixups
FixupKind
=
SHUXI
::
Fixups
(
0
)
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_None
:
FixupKind
=
SHUXI
::
fixup_SHUXI_32
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) { PM . add ( createThumb2ITBlockPass ( ) ) ; PM . add ( createThumb2SizeReductionPass ( ) ) ; } PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void rs6000_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.long\t" , file ) ; break ; case 8 : fputs ( DOUBLE_INT_ASM_OP , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; fputs ( "@dtprel+0x8000" , file ) ; } </s>

This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> void MipsOutgoingValueHandler :: assignValueToReg ( Register ValVReg , const CCValAssign & VA , const EVT & VT ) { Register PhysReg = VA . getLocReg ( ) ; if ( VT == MVT :: f64 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; bool IsEL = STI . isLittle ( ) ; auto Unmerge = MIRBuilder . buildUnmerge ( LLT :: scalar ( 32 ) , ValVReg ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? 0 : 1 ) ) , Unmerge . getReg ( 0 ) ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? 1 : 0 ) ) , Unmerge . getReg ( 1 ) ) ; } else if ( VT == MVT :: f32 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; } else { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static bool aarch64_simd_vector_alignment_reachable ( const_tree type , bool is_packed ) { if ( is_packed ) return false ; if ( tree_int_cst_compare ( TYPE_SIZE ( type ) , bitsize_int ( BIGGEST_ALIGNMENT ) ) > 0 ) return false ; return true ; } </s>


<s> static void emit_csky_regs_pop ( unsigned long mask ) { int num_regs = 0 ; int i , j ; rtx par ; for ( i = 0 ; i < CSKY_NGPR_REGS ; i ++ ) if ( mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 12 ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; for ( i = 0 ; i < CSKY_NGPR_REGS ; i ++ ) if ( mask & ( 1 << i ) ) { rtx reg = gen_rtx_REG ( SImode , i ) ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , 4 * num_regs ) ; rtx tmp = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , addr ) ) ; XVECEXP ( par , 0 , 1 ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , tmp ) , UNSPEC_PUSHPOP_MULT ) ) ; break ; } for ( j = 2 , i ++ ; j < ( num_regs + 1 ) ; i ++ ) if ( mask & ( 1 << i ) ) { rtx reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; j ++ ; } par = emit_jump_insn ( par ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi . SAVED_REGS_MASK shows which registers need to be restored . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasISEL ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

PowerPC PPC PPC PPC 16 PPC::DIR_NONE PPC "generic" "generic"


<s> static bool mmix_rtx_costs ( rtx x ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return false ; } </s>


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> MCSymbol * DLXMCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; } </s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
.
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
const
GlobalValue
*
Global
=
MI
.
getOperand
(
0
)
.
getGlobal
(
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addGlobalAddress
(
Global
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
0
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { if ( TRI -> hasBasePointer ( MF ) ) FrameReg = TRI -> getBaseRegister ( ) ; else if ( TRI -> needsStackRealignment ( MF ) ) FrameReg = TRI -> getStackRegister ( ) ; else FrameReg = TRI -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) FrameReg = RegInfo -> getStackRegister ( ) ; else FrameReg = RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , float Probability , float Confidence ) const { return NumCyles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> bool X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream ) const { InternalInstruction internalInstr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , logger , ( void * ) & vStream , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return false ; } else { size = internalInstr . length ; return ! translateInstruction ( instr , internalInstr ) ; } } </s>

Returns the disassembly of a single instruction .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getTarget ( ) . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; bool BranchWithZeroOperand = ( I -> isBranch ( ) && ! I -> isPseudo ( ) && I -> getOperand ( 1 ) . isReg ( ) && ( I -> getOperand ( 1 ) . getReg ( ) == Mips :: ZERO || I -> getOperand ( 1 ) . getReg ( ) == Mips :: ZERO_64 ) ) ; if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; } else if ( BranchWithZeroOperand ) { MIB . addOperand ( I -> getOperand ( 0 ) ) ; for ( unsigned J = 2 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilderBase & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( Ord == AtomicOrdering :: SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; if ( isReleaseOrStronger ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; return nullptr ; } </s>


<s>
static
const
char
*
rs6000_call_template_1
(
rtx
*
operands
,
unsigned
int
funop
,
bool
sibcall
)
{
gcc_assert
(
funop
<=
MAX_RECOG_OPERANDS
)
;
char
arg
[
12
]
;
arg
[
0
]
=
0
;
if
(
GET_CODE
(
operands
[
funop
+
1
]
)
==
UNSPEC
)
{
if
(
XINT
(
operands
[
funop
+
1
]
,
1
)
==
UNSPEC_TLSGD
)
sprintf
(
arg
,
"(%%%u@tlsgd)"
,
funop
+
1
)
;
else
if
(
XINT
(
operands
[
funop
+
1
]
,
1
)
==
UNSPEC_TLSLD
)
sprintf
(
arg
,
"(%%&@tlsld)"
)
;
}
char
z
[
11
]
;
sprintf
(
z
,
"%%z%u%s"
,
funop
,
(
DEFAULT_ABI
==
ABI_V4
&&
TARGET_SECURE_PLT
&&
flag_pic
==
2
"+32768"
:
""
)
)
;
static
char
str
[
32
]
;
if
(
rs6000_pcrel_p
(
)
)
sprintf
(
str
,
"b%s %s@notoc%s"
,
sibcall
""
:
"l"
,
z
,
arg
)
;
else
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
sprintf
(
str
,
"b%s %s%s%s"
,
sibcall
""
:
"l"
,
z
,
arg
,
sibcall
""
:
"\n\tnop"
)
;
else
if
(
DEFAULT_ABI
==
ABI_V4
)
sprintf
(
str
,
"b%s %s%s%s"
,
sibcall
""
:
"l"
,
z
,
arg
,
flag_pic
"@plt"
:
""
)
;
else
if
(
DEFAULT_ABI
==
ABI_DARWIN
)
{
gcc_checking_assert
(
GET_CODE
(
operands
[
funop
+
2
]
)
==
CONST_INT
)
;
int
cookie
=
INTVAL
(
operands
[
funop
+
2
]
)
;
if
(
cookie
&
CALL_LONG
)
{
tree
funname
=
get_identifier
(
XSTR
(
operands
[
funop
]
,
0
)
)
;
tree
labelname
=
get_prev_label
(
funname
)
;
gcc_checking_assert
(
labelname
&&
!
sibcall
)
;
sprintf
(
str
,
"jbsr %%z%u,%.10s"
,
funop
,
IDENTIFIER_POINTER
(
labelname
)
)
;
}
else
sprintf
(
str
,
"b%s %s%s"
,
sibcall
""
:
"l"
,
z
,
arg
)
;
}
else
gcc_unreachable
(
)
;
return
str
;
}
</s>

Return a template string for assembly to emit when making an external call . FUNOP is the call mem argument operand number .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( AFI -> shouldSignReturnAddress ( ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( ARM :: t2PAC ) ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } if ( llvm :: any_of ( CSI , [ ] ( const CalleeSavedInfo & C ) { return C . getReg ( ) == ARM :: FPCXTNS ; } ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( ARM :: VSTR_FPCXTNS_pre ) , ARM :: SP ) . addReg ( ARM :: SP ) . addImm ( - 4 ) . add ( predOps ( ARMCC :: AL ) ) ; } emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool ix86_expand_int_vec_cmp ( rtx operands [ ] ) { rtx_code code = GET_CODE ( operands [ 1 ] ) ; bool negate = false ; rtx cmp = ix86_expand_int_sse_cmp ( operands [ 0 ] , code , operands [ 2 ] , operands [ 3 ] , NULL , NULL , & negate ) ; if ( ! cmp ) return false ; if ( negate ) cmp = ix86_expand_int_sse_cmp ( operands [ 0 ] , EQ , cmp , CONST0_RTX ( GET_MODE ( cmp ) ) , NULL , NULL , & negate ) ; gcc_assert ( ! negate ) ; if ( operands [ 0 ] != cmp ) emit_move_insn ( operands [ 0 ] , cmp ) ; return true ; } </s>


<s> unsigned getNumFixupKinds ( ) const { return Cpu0 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { enum machine_mode mode = GET_MODE ( dest ) ; rtx x ; cmp_op0 = force_reg ( mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , mode ) ) cmp_op1 = force_reg ( mode , cmp_op1 ) ; if ( optimize || reg_overlap_mentioned_p ( dest , op_true ) || reg_overlap_mentioned_p ( dest , op_false ) ) dest = gen_reg_rtx ( mode ) ; x = gen_rtx_fmt_ee ( code , mode , cmp_op0 , cmp_op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
static
void
arm_option_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
int
flags
=
ptr
->
x_target_flags
;
const
struct
arm_fpu_desc
*
fpu_desc
=
&
all_fpus
[
ptr
->
x_arm_fpu_index
]
;
fprintf
(
file
,
"%*sselected arch %s\n"
,
indent
,
""
,
TARGET_THUMB2_P
(
flags
)
"thumb2"
:
TARGET_THUMB_P
(
flags
)
"thumb1"
:
"arm"
)
;
fprintf
(
file
,
"%*sselected fpu %s\n"
,
indent
,
""
,
fpu_desc
->
name
)
;
}
</s>

arm
"%*sselected arch %s\n"
""
"thumb2"
"thumb1"
"arm"
"%*sselected fpu %s\n"
""


<s> int getIntImmCostInst ( unsigned Opc , unsigned Idx , const APInt & Imm , Type * Ty ) { return getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void aarch64_emit_sve_pred_move ( rtx dest , rtx pred , rtx src ) { expand_operand ops [ 3 ] ; machine_mode mode = GET_MODE ( dest ) ; create_output_operand ( & ops [ 0 ] , dest , mode ) ; create_input_operand ( & ops [ 1 ] , pred , GET_MODE ( pred ) ) ; create_input_operand ( & ops [ 2 ] , src , mode ) ; expand_insn ( code_for_aarch64_pred_mov ( mode ) , 3 , ops ) ; } </s>

Emit an SVE predicated move from SRC to DEST . PRED is a predicate that is known to contain PTRUE .


<s> static rtx_insn * frame_insn ( rtx x ) { rtx_insn * insn = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } </s>

Emit the specified insn and mark it as frame related . FIXME : Rename this to emit_frame_insn .


<s> static void ia64_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS next_cum = * cum ; ia64_function_arg_advance ( & next_cum , mode , type , 1 ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine -> n_varargs = n ; } } </s>

Do any needed setup for a variadic function . CUM has not been updated for the last named argument which has type TYPE and mode MODE . We generate the actual spill instructions during prologue generation .


<s> std :: unique_ptr < TargetInstrInfo :: PipelinerLoopInfo > PPCInstrInfo :: analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const { MachineBasicBlock :: iterator I = LoopBB -> getFirstTerminator ( ) ; MachineBasicBlock * Preheader = * LoopBB -> pred_begin ( ) ; if ( Preheader == LoopBB ) Preheader = * std :: next ( LoopBB -> pred_begin ( ) ) ; MachineFunction * MF = Preheader -> getParent ( ) ; if ( I != LoopBB -> end ( ) && isBDNZ ( I -> getOpcode ( ) ) ) { SmallPtrSet < MachineBasicBlock * , 8 > Visited ; if ( MachineInstr * LoopInst = findLoopInstr ( * Preheader , Visited ) ) { Register LoopCountReg = LoopInst -> getOperand ( 0 ) . getReg ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr * LoopCount = MRI . getUniqueVRegDef ( LoopCountReg ) ; return std :: make_unique < PPCPipelinerLoopInfo > ( LoopInst , & * I , LoopCount ) ; } } return nullptr ; } </s>

Analyze loop L , which must be a single-basic-block loop , and if the conditions can be understood enough produce a PipelinerLoopInfo object .


<s> bool VETargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


"CPRESTORE's operand must be an immediate."

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
unsigned
PPCTTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
OperandValueKind
Op1Info
,
OperandValueKind
Op2Info
)
const
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool isMemUseUpRegs ( ) const override { return UseUpRegs ; } </s>

isMemUseUpRegs - Is memory operand use up regs , for example , intel MS inline asm may use ARR [ baseReg + IndexReg + ... ] which may use up regs in [ ... ] expr , so ARR [ baseReg + IndexReg + ... ] can not use extra reg for ARR .


<s> virtual const SparcInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
SDNode
*
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
nullptr
;
}
std
::
pair
<
bool
,
SDNode
*
>
Ret
=
selectNode
(
Node
)
;
if
(
Ret
.
first
)
return
Ret
.
second
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
nullptr
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."
"=> "
"\n"


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
return
Error
(
NameLoc
,
"unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> static void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { isa &= ~ OPTION_MASK_ISA_64BIT ; if ( ( isa & deferred_isa_values ) == 0 && ( isa2 & deferred_isa_values2 ) == 0 ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != 0 ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; if ( ix86_builtins_isa [ i ] . pure_p ) DECL_PURE_P ( decl ) = 1 ; if ( ix86_builtins_isa [ i ] . leaf_p ) DECL_ATTRIBUTES ( decl ) = build_tree_list ( get_identifier ( "leaf" ) , NULL_TREE ) ; if ( ix86_builtins_isa [ i ] . nothrow_p ) TREE_NOTHROW ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; if ( MI -> isDebugValue ( ) ) { PrintDebugValueComment ( MI , OS ) ; return ; } MipsMCInstLower MCInstLowering ( Mang , * MF , * this ) ; unsigned Opc = MI -> getOpcode ( ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( MI , TmpInst0 ) ; if ( isUnalignedLoadStore ( Opc ) ) { MCInst Directive ; Directive . setOpcode ( Mips :: MACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; Directive . setOpcode ( Mips :: NOMACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; return ; } OutStreamer . EmitInstruction ( TmpInst0 ) ; } </s>

Mips Mips 128 Mips Mips::MACRO Mips::NOMACRO


<s> bool arm_frame_pointer_required ( void ) { if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ( ) ) return true ; if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && flag_stack_check == STATIC_BUILTIN_STACK_CHECK && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= 0 ) return false ; if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += 32 * UNITS_PER_WORD ; if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) return true ; } else return true ; } return false ; } </s>


"builtin function %qs is only valid for the cell processor"

"builtin function %qs requires the %qs option"

"builtin function %qs requires the %qs and %qs options"

"builtin function %qs requires ISA 3.0 IEEE 128-bit floating point"

"builtin function %qs requires the %qs (or newer), and "

"builtin function %qs is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> void CJGInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; BuildMI ( MBB , MI , DL , get ( CJG :: POP ) ) . addReg ( DestReg , getDefRegState ( true ) ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static short find_set_regmode_weight ( rtx x , machine_mode mode ) { if ( GET_CODE ( x ) == CLOBBER && register_operand ( SET_DEST ( x ) , mode ) ) return 1 ; if ( GET_CODE ( x ) == SET && register_operand ( SET_DEST ( x ) , mode ) ) { if ( REG_P ( SET_DEST ( x ) ) ) { if ( ! reg_mentioned_p ( SET_DEST ( x ) , SET_SRC ( x ) ) ) return 1 ; else return 0 ; } return 1 ; } return 0 ; } </s>


<s> static void ix86_emit_mode_set ( int entity , int mode , int prev_mode ATTRIBUTE_UNUSED , HARD_REG_SET regs_live ) { switch ( entity ) { case AVX_U128 : if ( mode == AVX_U128_CLEAN ) ix86_avx_emit_vzeroupper ( regs_live ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Generate one or more insns to set ENTITY to MODE . HARD_REG_LIVE is the set of hard registers live at the point where the insn ( s ) are to be inserted .


<s> static bool branch_needs_nop_p ( rtx_insn * insn ) { rtx_insn * jump_insn ; if ( dbr_sequence_length ( ) ) return FALSE ; jump_insn = next_active_insn ( JUMP_LABEL_AS_INSN ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || jump_insn == insn ) return TRUE ; if ( ! ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) && get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a forward jump insn , needs a nop in its delay slot . This occurs when INSN has an unfilled delay slot and is followed by an asm . Disaster can occur if the asm is empty and the jump branches into the delay slot . So , we add a nop in the delay slot when this occurs .


<s> const std :: string & AArch64LongBranchStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MI
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MI
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void aarch64_override_options_internal ( struct gcc_options * opts ) { aarch64_tune_flags = selected_tune -> flags ; aarch64_tune = selected_tune -> sched_core ; aarch64_tune_params = * ( selected_tune -> tune ) ; aarch64_architecture_version = selected_arch -> architecture_version ; if ( opts -> x_aarch64_override_tune_string ) aarch64_parse_override_string ( opts -> x_aarch64_override_tune_string , & aarch64_tune_params ) ; if ( opts -> x_flag_strict_volatile_bitfields < 0 && abi_version_at_least ( 2 ) ) opts -> x_flag_strict_volatile_bitfields = 1 ; initialize_aarch64_code_model ( opts ) ; initialize_aarch64_tls_size ( opts ) ; int queue_depth = 0 ; switch ( aarch64_tune_params . autoprefetcher_model ) { case tune_params :: AUTOPREFETCHER_OFF : queue_depth = - 1 ; break ; case tune_params :: AUTOPREFETCHER_WEAK : queue_depth = 0 ; break ; case tune_params :: AUTOPREFETCHER_STRONG : queue_depth = max_insn_queue_index + 1 ; break ; default : gcc_unreachable ( ) ; } maybe_set_param_value ( PARAM_SCHED_AUTOPREF_QUEUE_DEPTH , queue_depth , opts -> x_param_values , global_options_set . x_param_values ) ; if ( selected_cpu -> tune -> cache_line_size != 0 ) maybe_set_param_value ( PARAM_L1_CACHE_LINE_SIZE , selected_cpu -> tune -> cache_line_size , opts -> x_param_values , global_options_set . x_param_values ) ; aarch64_override_options_after_change_1 ( opts ) ; } </s>

'Unpack ' up the internal tuning structs and update the options in OPTS . The caller must have set up selected_tune and selected_arch as all the other target-specific codegen decisions are derived from them .


<s> static rtx ia64_function_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return ia64_function_arg_1 ( cum , arg , false ) ; } </s>

Implement TARGET_FUNCION_ARG target hook .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { const MCInstrDesc & Desc = Info -> get ( Inst . getOpcode ( ) ) ; bool FoundImm = false ; int64_t Imm ; for ( unsigned OpNum = 0 ; OpNum < Desc . getNumOperands ( ) ; ++ OpNum ) { if ( Inst . getOperand ( OpNum ) . isImm ( ) && Desc . OpInfo [ OpNum ] . OperandType == MCOI :: OPERAND_PCREL ) { Imm = Inst . getOperand ( OpNum ) . getImm ( ) ; FoundImm = true ; } } if ( ! FoundImm ) return false ; uint64_t Offset = ( ( Desc . TSFlags & ARMII :: FormMask ) == ARMII :: ThumbFrm ) ? 4 : 8 ; Target = Addr + Imm + Offset ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> SDValue getUNDEF ( EVT VT ) const { return DAG . getUNDEF ( VT ) ; } </s>

Return an UNDEF node . UNDEF does not have a useful SDLoc .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'A' : return C_Register ; case 'f' : case 'r' : case 'R' : case 'l' : case 'q' : case 'Q' : case 'x' : case 'y' : case 'Y' : return C_RegisterClass ; case 'e' : case 'Z' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool mips_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align , enum by_pieces_operation op , bool speed_p ) { if ( op == STORE_BY_PIECES ) return mips_store_by_pieces_p ( size , align ) ; if ( op == MOVE_BY_PIECES && HAVE_movmemsi ) { if ( currently_expanding_to_rtl ) return false ; if ( align < BITS_PER_WORD ) return size < UNITS_PER_WORD ; return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT ; } return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return VE :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> unsigned SystemZTTIImpl :: getMinPrefetchStride ( unsigned NumMemAccesses , unsigned NumStridedMemAccesses , unsigned NumPrefetches , bool HasCall ) const { if ( NumPrefetches > 16 ) return UINT_MAX ; if ( NumStridedMemAccesses > 32 && ! HasCall && ( NumMemAccesses - NumStridedMemAccesses ) * 32 <= NumStridedMemAccesses ) return 1 ; return ST -> hasMiscellaneousExtensions3 ( ) ? 8192 : 2048 ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> int sparc_split_reg_mem_legitimate ( rtx reg , rtx mem ) { gcc_assert ( reload_completed ) ; if ( ! offsettable_memref_p ( mem ) ) return 0 ; if ( ( REGNO ( reg ) % 2 ) == 0 && mem_min_alignment ( mem , 8 ) ) return 0 ; return 1 ; } </s>

Return 1 if REG and MEM are legitimate enough to allow the various MEM < -- > REG splits to be run .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= expandMBB ( * MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void aarch64_emit_prologue_components ( sbitmap components ) { aarch64_process_components ( components , true ) ; } </s>


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> Write8 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> Register PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TM . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s> static void vector_init_bshuffle ( rtx target , rtx elt , machine_mode mode , machine_mode inner_mode ) { rtx t1 , final_insn , sel ; int bmask ; t1 = gen_reg_rtx ( mode ) ; elt = convert_modes ( SImode , inner_mode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; switch ( mode ) { case E_V2SImode : final_insn = gen_bshufflev2si_vis ( target , t1 , t1 ) ; bmask = 0x45674567 ; break ; case E_V4HImode : final_insn = gen_bshufflev4hi_vis ( target , t1 , t1 ) ; bmask = 0x67676767 ; break ; case E_V8QImode : final_insn = gen_bshufflev8qi_vis ( target , t1 , t1 ) ; bmask = 0x77777777 ; break ; default : gcc_unreachable ( ) ; } sel = force_reg ( SImode , GEN_INT ( bmask ) ) ; emit_insn ( gen_bmasksi_vis ( gen_reg_rtx ( SImode ) , sel , const0_rtx ) ) ; emit_insn ( final_insn ) ; } </s>

Subroutine of sparc_expand_vector_init . Emit code to initialize all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn . MODE and INNER_MODE are the modes describing TARGET .


"getJumpTargetOpValue expects only expressions or an immediate"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> bool doInitialization ( Module & M ) override { SMShadowTracker . reset ( 0 ) ; SM . reset ( ) ; return AsmPrinter :: doInitialization ( M ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool ARMCodeGenPrepare :: doInitialization ( Module & M ) { Promoter = new IRPromoter ( & M ) ; return false ; } </s>


<s> void MINA32InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> bool pure_scalable_type_info :: analyze_registers ( const_tree type ) { analysis_result result = analyze ( type ) ; gcc_assert ( result != DOESNT_MATTER ) ; return result == IS_PST ; } </s>

Analyze a type that is known not to be passed or returned in memory . Return true if it has an ABI identity and is a Pure Scalable Type .


<s> enum direction ia64_hpux_function_arg_padding ( machine_mode mode , const_tree type ) { if ( type && AGGREGATE_TYPE_P ( type ) && int_size_in_bytes ( type ) < UNITS_PER_WORD ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

For the HP-UX IA64 aggregate parameters are passed stored in the most significant bits of the stack slot .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == ".arch_extension" ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"

"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


"Register sequence is not valid. 'r4-r7' expected"

Process a single instruction and collect debug info anchors .


<s> bool doInitialization ( Module & M ) override { if ( ! Triple ( M . getTargetTriple ( ) ) . isOSNaCl ( ) ) SMShadowTracker . reset ( 0 ) ; SM . reset ( ) ; return AsmPrinter :: doInitialization ( M ) ; } </s>


<s> int memory_address_length ( rtx addr , bool lea ) { struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return 0 ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == SEG_DEFAULT ) ? 0 : 1 ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ; if ( base && GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; if ( index && GET_CODE ( index ) == SUBREG ) index = SUBREG_REG ( index ) ; gcc_assert ( base == NULL_RTX || REG_P ( base ) ) ; gcc_assert ( index == NULL_RTX || REG_P ( index ) ) ; if ( base && ! index && ! disp ) { if ( base == arg_pointer_rtx || base == frame_pointer_rtx || REGNO ( base ) == SP_REG || REGNO ( base ) == BP_REG || REGNO ( base ) == R12_REG || REGNO ( base ) == R13_REG ) len ++ ; } else if ( disp && ! base && ! index ) { len += 4 ; if ( rip_relative_addr_p ( & parts ) ) len ++ ; } else { if ( disp ) { if ( base && satisfies_constraint_K ( disp ) ) len += 1 ; else len += 4 ; } else if ( base && ( REGNO ( base ) == BP_REG || REGNO ( base ) == R13_REG ) ) len ++ ; if ( index || base == arg_pointer_rtx || base == frame_pointer_rtx || ( base && ( REGNO ( base ) == SP_REG || REGNO ( base ) == R12_REG ) ) ) len ++ ; } return len ; } </s>

Calculate the length of the memory address in the instruction encoding . Does not include the one-byte modrm , opcode , or prefix .


<s> bool ix86_avoid_lea_for_addr ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 , regno2 ; int split_cost ; struct ix86_address parts ; int ok ; if ( REG_P ( operands [ 1 ] ) || ( SImode_address_operand ( operands [ 1 ] , VOIDmode ) && REG_P ( XEXP ( operands [ 1 ] , 0 ) ) ) ) return false ; ok = ix86_decompose_address ( operands [ 1 ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > 1 ) < 2 ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ; if ( ! TARGET_BONNELL && parts . scale == 1 && ( ! parts . disp || parts . disp == const0_rtx ) && ( regno0 == regno1 || regno0 == regno2 ) ) return true ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; split_cost = 0 ; if ( parts . base || parts . index ) { if ( regno1 != regno0 && regno2 != regno0 ) split_cost += 1 ; if ( parts . base && parts . index ) split_cost += 1 ; if ( parts . scale > 1 ) { if ( regno0 != regno1 ) split_cost += 1 ; else if ( regno2 == regno0 ) split_cost += 4 ; else split_cost += parts . scale ; } if ( parts . disp && parts . disp != const0_rtx ) split_cost += 1 ; split_cost -= 1 ; } return ! ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , split_cost , parts . scale > 1 ) ; } </s>

Return true if we need to split lea into a sequence of instructions to avoid AGU stalls during peephole2 .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op , Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
bool
AArch64InstrInfo
::
isGPRCopy
(
const
MachineInstr
&
MI
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
GPR32RegClass
.
contains
(
DstReg
)
||
AArch64
::
GPR64RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRXrs
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ORRrs operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ADDXri
:
if
(
MI
.
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ADDXri operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename a GPR without modifying bits ?


<s> bool PPCRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return requiresRegisterScavenging ( MF ) ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static tree resolve_vec_addec_subec ( resolution * res , rs6000_gen_builtins fcode , tree * args , tree * types , location_t loc ) { if ( TREE_CODE ( types [ 0 ] ) != VECTOR_TYPE || ! lang_hooks . types_compatible_p ( types [ 0 ] , types [ 1 ] ) || ! lang_hooks . types_compatible_p ( types [ 1 ] , types [ 2 ] ) ) { * res = resolved_bad ; return error_mark_node ; } switch ( TYPE_MODE ( TREE_TYPE ( types [ 0 ] ) ) ) { case E_SImode : { args [ 0 ] = save_expr ( args [ 0 ] ) ; args [ 1 ] = save_expr ( args [ 1 ] ) ; vec < tree , va_gc > * params = make_tree_vector ( ) ; vec_safe_push ( params , args [ 0 ] ) ; vec_safe_push ( params , args [ 1 ] ) ; tree as_c_builtin ; if ( fcode == RS6000_OVLD_VEC_ADDEC ) as_c_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_ADDC ] ; else as_c_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_SUBC ] ; tree call1 = altivec_resolve_overloaded_builtin ( loc , as_c_builtin , params ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , args [ 0 ] ) ; vec_safe_push ( params , args [ 1 ] ) ; tree as_builtin ; if ( fcode == RS6000_OVLD_VEC_ADDEC ) as_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_ADD ] ; else as_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_SUB ] ; tree call2 = altivec_resolve_overloaded_builtin ( loc , as_builtin , params ) ; tree const1 = build_int_cstu ( TREE_TYPE ( types [ 0 ] ) , 1 ) ; tree ones_vector = build_vector_from_val ( types [ 0 ] , const1 ) ; tree and_expr = fold_build2_loc ( loc , BIT_AND_EXPR , types [ 0 ] , args [ 2 ] , ones_vector ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , call2 ) ; vec_safe_push ( params , and_expr ) ; call2 = altivec_resolve_overloaded_builtin ( loc , as_c_builtin , params ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , call1 ) ; vec_safe_push ( params , call2 ) ; tree or_builtin = rs6000_builtin_decls [ RS6000_OVLD_VEC_OR ] ; * res = resolved ; return altivec_resolve_overloaded_builtin ( loc , or_builtin , params ) ; } case E_TImode : * res = unresolved ; break ; default : * res = resolved_bad ; } return error_mark_node ; } </s>

Resolve an overloaded vec_addec or vec_subec call and return a tree expression for the resolved call if successful . ARGS contains the arguments to the call . TYPES contains their types . RES must be set to indicate the status of the resolution attempt . LOC contains statement location information .


<s> bool isCtlzFast ( ) const override { return true ; } </s>

Return true if ctlz instruction is fast .


<s> unsigned int arm_dbx_register_number ( unsigned int regno ) { if ( regno < 16 ) return regno ; if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return 64 + regno - FIRST_VFP_REGNUM ; else return 256 + ( regno - FIRST_VFP_REGNUM ) / 2 ; } if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return 104 + regno - FIRST_IWMMXT_GR_REGNUM ; if ( IS_IWMMXT_REGNUM ( regno ) ) return 112 + regno - FIRST_IWMMXT_REGNUM ; return DWARF_FRAME_REGISTERS ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::BlockAddress
ISD::ConstantPool
ISD::DYNAMIC_STACKALLOC
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::LOAD
ISD::STORE
ISD::VASTART
ISD::VAARG


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16Pass ( ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloatPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void SystemZMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned I = 0 , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ; } } </s>


<s> unsigned DLXInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { return false ; } </s>

Remove the branching code at the end of the specific MBB .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Um
:
case
InlineAsm
::
Constraint_Un
:
case
InlineAsm
::
Constraint_Uq
:
case
InlineAsm
::
Constraint_Us
:
case
InlineAsm
::
Constraint_Ut
:
case
InlineAsm
::
Constraint_Uv
:
case
InlineAsm
::
Constraint_Uy
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

ARM
ARM
"Unexpected asm memory constraint"


<s> void aarch64_register_fma_steering ( ) { opt_pass * pass_fma_steering = make_pass_fma_steering ( g ) ; struct register_pass_info fma_steering_info = { pass_fma_steering , "rnreg" , 1 , PASS_POS_INSERT_AFTER } ; register_pass ( & fma_steering_info ) ; } </s>

Register the FMA steering pass to the pass manager .


<s>
void
aarch64_print_hint_for_extensions
(
const
std
::
string
&
str
)
{
auto_vec
<
const
char
*
>
candidates
;
aarch64_get_all_extension_candidates
(
&
candidates
)
;
char
*
s
;
const
char
*
hint
=
candidates_list_and_hint
(
str
.
c_str
(
)
,
s
,
candidates
)
;
if
(
hint
)
inform
(
input_location
,
"valid arguments are: %s;"
" did you mean %qs?"
,
s
,
hint
)
;
else
inform
(
input_location
,
"valid arguments are: %s;"
,
s
)
;
XDELETEVEC
(
s
)
;
}
</s>

Print a hint with a suggestion for an extension name that most closely resembles what the user passed in STR .

aarch64
"valid arguments are: %s;"
" did you mean %qs?"
"valid arguments are: %s;"


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr & MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; SmallVector < unsigned , 1 > SrcOperandIds ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) ) return nullptr ; SrcOperandIds . push_back ( i ) ; } if ( SrcOperandIds . empty ( ) ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandIds , * DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> static rtx sh_trampoline_adjust_address ( rtx tramp ) { if ( TARGET_SHMEDIA ) tramp = expand_simple_binop ( Pmode , PLUS , tramp , const1_rtx , gen_reg_rtx ( Pmode ) , 0 , OPTAB_LIB_WIDEN ) ; return tramp ; } </s>

On SH5 , trampolines are SHmedia code , so add 1 to the address .


<s> unsigned X86InstrInfo :: getFMA3OpcodeToCommuteOperands ( const MachineInstr & MI , unsigned SrcOpIdx1 , unsigned SrcOpIdx2 , const X86InstrFMA3Group & FMA3Group ) const { unsigned Opc = MI . getOpcode ( ) ; if ( SrcOpIdx1 > SrcOpIdx2 ) std :: swap ( SrcOpIdx1 , SrcOpIdx2 ) ; if ( FMA3Group . isIntrinsic ( ) && SrcOpIdx1 == 1 ) return 0 ; unsigned FMAOp1 = 1 , FMAOp2 = 2 , FMAOp3 = 3 ; if ( FMA3Group . isKMasked ( ) ) { if ( SrcOpIdx1 == 2 ) return 0 ; if ( FMA3Group . isKMergeMasked ( ) && SrcOpIdx1 == FMAOp1 ) return 0 ; FMAOp2 ++ ; FMAOp3 ++ ; } unsigned Case ; if ( SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp2 ) Case = 0 ; else if ( SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp3 ) Case = 1 ; else if ( SrcOpIdx1 == FMAOp2 && SrcOpIdx2 == FMAOp3 ) Case = 2 ; else return 0 ; const unsigned Form132Index = 0 ; const unsigned Form213Index = 1 ; const unsigned Form231Index = 2 ; static const unsigned FormMapping [ ] [ 3 ] = { { Form231Index , Form213Index , Form132Index } , { Form132Index , Form231Index , Form213Index } , { Form213Index , Form132Index , Form231Index } } ; unsigned FMAForms [ 3 ] ; if ( FMA3Group . isRegOpcodeFromGroup ( Opc ) ) { FMAForms [ 0 ] = FMA3Group . getReg132Opcode ( ) ; FMAForms [ 1 ] = FMA3Group . getReg213Opcode ( ) ; FMAForms [ 2 ] = FMA3Group . getReg231Opcode ( ) ; } else { FMAForms [ 0 ] = FMA3Group . getMem132Opcode ( ) ; FMAForms [ 1 ] = FMA3Group . getMem213Opcode ( ) ; FMAForms [ 2 ] = FMA3Group . getMem231Opcode ( ) ; } unsigned FormIndex ; for ( FormIndex = 0 ; FormIndex < 3 ; FormIndex ++ ) if ( Opc == FMAForms [ FormIndex ] ) break ; FormIndex = FormMapping [ Case ] [ FormIndex ] ; return FMAForms [ FormIndex ] ; } </s>

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted .


<s> static inline bool offset_12bit_unsigned_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , 0 , 4095 ) ) ; } </s>

Return true if OFFSET is an unsigned 12-bit value multiplied by the size of MODE .


<s> static bool arm_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { bool ret = true ; struct gcc_options func_options , func_options_set ; tree cur_tree , new_optimize ; gcc_assert ( ( fndecl != NULL_TREE ) && ( args != NULL_TREE ) ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , 0 , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( target_option_default_node ) ) ; cur_tree = arm_valid_target_attribute_tree ( args , & func_options , & func_options_set ) ; if ( cur_tree == NULL_TREE ) ret = false ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = cur_tree ; DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == 0 ) return false ; if ( ! isConditionalBranch ( Inst ) && ! isUnconditionalBranch ( Inst ) && ! isCall ( Inst ) ) return false ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ; } else { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; if ( Imm == 0 ) return false ; Target = Imm ; return true ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> unsigned PPCTargetLowering :: combineRepeatedFPDivisors ( ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : return 3 ; case PPC :: DIR_440 : case PPC :: DIR_A2 : case PPC :: DIR_E500mc : case PPC :: DIR_E5500 : return 2 ; } } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


"Only support MVT::i32 register passing"

"Can only pass arguments as either registers or via the stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> unsigned LanaiInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Lanai :: SW_RI ) if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> const std :: string & THMToARMStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
else
if
(
isSVEFunction
(
*
MF
)
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> static bool aarch64_evpc_uzp ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT odd ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( ! d -> perm [ 0 ] . is_constant ( & odd ) || ( odd != 0 && odd != 1 ) || ! d -> perm . series_p ( 0 , 1 , odd , 2 ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; emit_set_insn ( out , gen_rtx_UNSPEC ( vmode , gen_rtvec ( 2 , in0 , in1 ) , odd ? UNSPEC_UZP2 : UNSPEC_UZP1 ) ) ; return true ; } </s>

Recognize patterns suitable for the UZP instructions .


<s> std :: pair < unsigned , unsigned > AArch64InstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { const unsigned Mask = AArch64II :: MO_FRAGMENT ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> unsigned Cpu0MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = getCpu0RegisterNumbering ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; Cpu0 :: Fixups FixupKind = Cpu0 :: Fixups ( 0 ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { case MCSymbolRefExpr :: VK_Cpu0_GPREL : FixupKind = Cpu0 :: fixup_Cpu0_GPREL16 ; break ; case MCSymbolRefExpr :: VK_Cpu0_GOT_CALL : FixupKind = Cpu0 :: fixup_Cpu0_CALL24 ; break ; case MCSymbolRefExpr :: VK_Cpu0_GOT16 : FixupKind = Cpu0 :: fixup_Cpu0_GOT_Global ; break ; case MCSymbolRefExpr :: VK_Cpu0_GOT : FixupKind = Cpu0 :: fixup_Cpu0_GOT_Local ; break ; case MCSymbolRefExpr :: VK_Cpu0_ABS_HI : FixupKind = Cpu0 :: fixup_Cpu0_HI16 ; break ; case MCSymbolRefExpr :: VK_Cpu0_ABS_LO : FixupKind = Cpu0 :: fixup_Cpu0_LO16 ; break ; default : break ; } Fixups . push_back ( MCFixup :: Create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; ForCodeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) || FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; unsigned SlotSize = is64Bit ? 8 : 4 ; MachineFunction & MF = * MBB . getParent ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FI -> setCalleeSavedFrameSize ( CSI . size ( ) * SlotSize ) ; unsigned Opc = is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void aarch64_emit_approx_rsqrt ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( src ) ; gcc_assert ( mode == SFmode || mode == V2SFmode || mode == V4SFmode || mode == DFmode || mode == V2DFmode ) ; rtx xsrc = gen_reg_rtx ( mode ) ; emit_move_insn ( xsrc , src ) ; rtx x0 = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( x0 , xsrc ) ) ; bool double_mode = ( mode == DFmode || mode == V2DFmode ) ; int iterations = double_mode ? 3 : 2 ; if ( flag_mrecip_low_precision_sqrt ) iterations -- ; for ( int i = 0 ; i < iterations ; ++ i ) { rtx x1 = gen_reg_rtx ( mode ) ; rtx x2 = gen_reg_rtx ( mode ) ; rtx x3 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , x0 , x0 ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x3 , xsrc , x2 ) ) ; emit_set_insn ( x1 , gen_rtx_MULT ( mode , x0 , x3 ) ) ; x0 = x1 ; } emit_move_insn ( dst , x0 ) ; } </s>

Emit instruction sequence to compute the reciprocal square root using the Newton-Raphson series . Iterate over the series twice for SF and thrice for DF .


<s> static void pa_output_function_epilogue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { rtx_insn * insn = get_last_insn ( ) ; bool extra_nop ; if ( NOTE_P ( insn ) ) insn = prev_real_insn ( insn ) ; if ( insn && NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = as_a < rtx_sequence * > ( PATTERN ( insn ) ) -> insn ( 0 ) ; if ( insn && CALL_P ( insn ) ) { fputs ( "\tnop\n" , file ) ; extra_nop = true ; } else extra_nop = false ; fputs ( "\t.EXIT\n\t.PROCEND\n" , file ) ; if ( TARGET_SOM && TARGET_GAS ) { in_section = NULL ; cfun -> machine -> in_nsubspa = 2 ; } if ( cfun -> is_thunk ) return ; if ( INSN_ADDRESSES_SET_P ( ) ) { last_address = extra_nop ? 4 : 0 ; insn = get_last_nonnote_insn ( ) ; if ( insn ) { last_address += INSN_ADDRESSES ( INSN_UID ( insn ) ) ; if ( INSN_P ( insn ) ) last_address += insn_default_length ( insn ) ; } last_address = ( ( last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1 ) & ~ ( FUNCTION_BOUNDARY / BITS_PER_UNIT - 1 ) ) ; } else last_address = UINT_MAX ; update_total_code_bytes ( last_address ) ; } </s>

This function generates the assembly code for function exit . Args are as for output_function_prologue ( ) . The function epilogue should not depend on the current stack pointer ! It should use the frame pointer only . This is mandatory because of alloca ; we also take advantage of it to omit stack adjustments before returning .


"getBranchTargetOpValuePC10 expects only expressions or immediates"

getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand .


"Only register-returns should be created by PCS"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned ARMFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETJMP
:
return
LowerEH_SJLJ_SETJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_LONGJMP
:
return
LowerEH_SJLJ_LONGJMP
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShift
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
SHL_PARTS
:
return
LowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
case
ISD
::
SRA_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
VSETCC
:
return
LowerVSETCC
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
FLT_ROUNDS_
:
return
LowerFLT_ROUNDS_
(
Op
,
DAG
)
;
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size ; size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( mode == SDmode ) || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( TARGET_DIRECT_MOVE_128 && size == 16 && ( ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) || ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> static void ix86_output_indirect_branch ( rtx call_op , const char * xasm , bool sibcall_p ) { if ( REG_P ( call_op ) ) ix86_output_indirect_branch_via_reg ( call_op , sibcall_p ) ; else ix86_output_indirect_branch_via_push ( call_op , xasm , sibcall_p ) ; } </s>

Output indirect branch via a call and return thunk . CALL_OP is the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true .


<s> TargetPassConfig * Dcpu16TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Dcpu16PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
EVT
MipsTargetLowering
::
getOptimalMemOpType
(
const
MemOp
&
Op
,
const
AttributeList
&
FuncAttributes
)
const
{
bool
IsNonZeroMemset
=
Op
.
isMemset
(
)
&&
!
Op
.
isZeroMemset
(
)
;
Align
CapAlign
=
Subtarget
.
isCheri
(
)
Subtarget
.
getCapAlignment
(
)
:
Align
(
)
;
if
(
CapAlign
>
1
&&
Op
.
size
(
)
>=
CapAlign
.
value
(
)
&&
!
IsNonZeroMemset
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
__func__
<<
" Size="
<<
Op
.
size
(
)
<<
" DstAlign="
<<
(
Op
.
isFixedDstAlign
(
)
Op
.
getDstAlign
(
)
.
value
(
)
:
0
)
<<
" SrcAlign="
<<
(
Op
.
isMemset
(
)
0
:
Op
.
getSrcAlign
(
)
.
value
(
)
)
<<
" CapAlign="
<<
CapAlign
.
value
(
)
<<
"\n"
)
;
if
(
Op
.
isAligned
(
CapAlign
)
)
{
return
CapType
;
}
else
if
(
!
Op
.
isMemset
(
)
)
{
return
MVT
::
isVoid
;
}
if
(
Subtarget
.
isGP64bit
(
)
&&
Op
.
isAligned
(
Align
(
8
)
)
)
return
MVT
::
i64
;
if
(
Op
.
isAligned
(
Align
(
4
)
)
)
return
MVT
::
i32
;
if
(
Op
.
isAligned
(
Align
(
2
)
)
)
return
MVT
::
i16
;
return
MVT
::
i8
;
}
if
(
Subtarget
.
isGP64bit
(
)
)
return
MVT
::
i64
;
return
MVT
::
i32
;
}
</s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static base_reg_disp sh_find_base_reg_disp ( rtx_insn * insn , rtx x , disp_t disp = 0 , rtx base_reg = NULL ) { if ( REG_P ( x ) ) { if ( REGNO ( x ) == GBR_REG ) return base_reg_disp ( x , disp ) ; if ( REGNO ( x ) < FIRST_PSEUDO_REGISTER ) return base_reg_disp ( base_reg != NULL ? base_reg : x , disp ) ; rtx_insn * last_i = NULL ; rtx last_set = NULL ; for ( df_ref d = DF_REG_DEF_CHAIN ( REGNO ( x ) ) ; d != NULL ; d = DF_REF_NEXT_REG ( d ) ) { rtx set = const_cast < rtx > ( set_of ( x , DF_REF_INSN ( d ) ) ) ; if ( last_set == NULL || rtx_equal_p ( last_set , set ) ) { last_i = DF_REF_INSN ( d ) ; last_set = set ; } else { last_i = NULL ; last_set = NULL ; break ; } } if ( last_set != NULL && last_i != NULL ) return sh_find_base_reg_disp ( last_i , XEXP ( last_set , 1 ) , disp , XEXP ( last_set , 0 ) ) ; return base_reg_disp ( x , disp ) ; } else if ( GET_CODE ( x ) == PLUS ) { base_reg_disp left_val = sh_find_base_reg_disp ( insn , XEXP ( x , 0 ) ) ; base_reg_disp right_val = sh_find_base_reg_disp ( insn , XEXP ( x , 1 ) ) ; if ( left_val . is_reg ( ) && right_val . is_disp ( ) ) return base_reg_disp ( left_val . reg ( ) , left_val . disp ( ) + right_val . disp ( ) + disp ) ; else if ( right_val . is_reg ( ) && left_val . is_disp ( ) ) return base_reg_disp ( right_val . reg ( ) , right_val . disp ( ) + left_val . disp ( ) + disp ) ; else return base_reg_disp ( base_reg , disp ) ; } else if ( CONST_INT_P ( x ) ) return base_reg_disp ( NULL , disp + INTVAL ( x ) ) ; return base_reg_disp ( base_reg , disp ) ; } </s>

Find the base register and calculate the displacement for a given address rtx ' x ' .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DOUT
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
NumEmitted
++
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Execution Domain Fix"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void mep_save_register_info ( void ) { save_register_info ( ) ; } </s>

These three functions provide a bridge between the pramgas that affect register classes , and the functions that maintain them . We ca n't call those functions directly as pragma handling is part of the front end and does n't have direct access to them .


<s> static bool peek ( struct InternalInstruction * insn , uint8_t & byte ) { uint64_t offset = insn -> readerCursor - insn -> startLocation ; if ( offset >= insn -> bytes . size ( ) ) return true ; byte = insn -> bytes [ offset ] ; return false ; } </s>


<s> DecodeStatus LanaiDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & , raw_ostream & ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableLanai32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


Return true if the vector misalignment factor is supported by the target .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax_rex"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
32
,
0
}
,
{
"reloc_signed_4byte_relax"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
64
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
static
void
print_multi_reg
(
FILE
*
stream
,
const
char
*
instr
,
unsigned
reg
,
unsigned
long
mask
)
{
unsigned
i
;
bool
not_first
=
FALSE
;
fputc
(
'\t'
,
stream
)
;
asm_fprintf
(
stream
,
instr
,
reg
)
;
fputs
(
", {"
,
stream
)
;
for
(
i
=
0
;
i
<=
LAST_ARM_REGNUM
;
i
++
)
if
(
mask
&
(
1
<<
i
)
)
{
if
(
not_first
)
fprintf
(
stream
,
", "
)
;
asm_fprintf
(
stream
,
"%r"
,
i
)
;
not_first
=
TRUE
;
}
fprintf
(
stream
,
"}\n"
)
;
}
</s>

Output the operands of a LDM/STM instruction to STREAM . MASK is the ARM register set mask of which only bits 0-15 are important . REG is the base register , either the frame pointer or the stack pointer , INSTR is the possibly suffixed load or store instruction .


<s> inline hashval_t libcall_hasher :: hash ( const value_type * p1 ) { return hash_rtx ( p1 , VOIDmode , NULL , NULL , FALSE ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> bool rs6000_move_128bit_ok_p ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; return ( gpc_reg_operand ( operands [ 0 ] , mode ) || gpc_reg_operand ( operands [ 1 ] , mode ) ) ; } </s>


<s> static void ix86_conditional_register_usage ( void ) { int i , c_mask ; if ( cfun && cfun -> machine -> no_caller_saved_registers ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ! ix86_function_value_regno_p ( i ) ) call_used_regs [ i ] = 0 ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } c_mask = CALL_USED_REGISTERS_MASK ( TARGET_64BIT_MS_ABI ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_SSE ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) SSE_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) FLOAT_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } } </s>

Update register usage after having seen the compiler flags .