<s> bool SystemZTDCPass :: runOnFunction ( Function & F ) { ConvertedInsts . clear ( ) ; LogicOpsWorklist . clear ( ) ; PossibleJunk . clear ( ) ; for ( auto & I : instructions ( F ) ) { if ( I . getOpcode ( ) == Instruction :: FCmp ) convertFCmp ( cast < CmpInst > ( I ) ) ; else if ( I . getOpcode ( ) == Instruction :: ICmp ) convertICmp ( cast < CmpInst > ( I ) ) ; } if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 0 ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 1 ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , 0 ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Value * TDCFunc = Intrinsic :: getDeclaration ( & M , Intrinsic :: s390_tdc , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true ; } if ( ! MadeChange ) return false ; for ( auto * I : PossibleJunk ) if ( I -> user_empty ( ) ) I -> eraseFromParent ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void Cpu0SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; Cpu0MachineFunctionInfo * Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned FP = Cpu0 :: FP ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( Cpu0FI -> callsEhReturn ( ) ) Cpu0FI -> createEhDataRegsFI ( ) ; if ( MF . getFrameInfo ( ) . hasCalls ( ) ) setAliasRegs ( MF , SavedRegs , Cpu0 :: LR ) ; return ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; } </s>

This method must be called before any actual lowering is done .

ARM ARM ARM ARM ARM ARM ARM ARMABI::ARM_ABI_AAPCS ".ARM.attributes" ARM 0


<s> static rtx get_free_reg ( HARD_REG_SET regs_live ) { if ( ! TEST_HARD_REG_BIT ( regs_live , 1 ) ) return gen_rtx_REG ( Pmode , 1 ) ; gcc_assert ( ! TEST_HARD_REG_BIT ( regs_live , 7 ) ) ; return gen_rtx_REG ( Pmode , 7 ) ; } </s>

REGS_LIVE is the liveness information for the point for which we need this allocation . In some bare-bones exit blocks , r1 is live at the start . We can even have all of r0 .. r3 being live : __complex__ long long f ( double d ) { if ( d == 0 ) return 2 ; else return 3 ; } INSN before which new insns are placed with will clobber the register we return . If a basic block consists only of setting the return value register to a pseudo and using that register , the return value is not live before or after this block , yet we we 'll insert our insns right in the middle .


"too large function value type, needs %d registers,\ have only %d registers for this"


<s> unsigned AArch64FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < AArch64FunctionInfo > ( ) -> getCalleeSavedStackSize ( ) ; return alignTo ( CSSize + MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) , getStackAlign ( ) ) ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s>
void
mmix_asm_output_internal_label
(
FILE
*
stream
,
const
char
*
name
)
{
assemble_name_raw
(
stream
,
name
)
;
fprintf
(
stream
,
"\tIS @\n"
)
;
}
</s>


<s> static void add_compiler_branch_island ( tree label_name , tree function_name , int line_number ) { branch_island bi = { function_name , label_name , line_number } ; vec_safe_push ( branch_islands , bi ) ; } </s>

Remember to generate a branch island for far calls to the given function .


<s> bool allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = 0 , unsigned Align = 1 , bool * Fast = nullptr ) const override { if ( RequireStrictAlign ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool LanaiSetflagAluCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( DisableSetflagAluCombiner ) return false ; bool Modified = false ; MfIterator End = MF . end ( ) ; for ( MfIterator MFI = MF . begin ( ) ; MFI != End ; ++ MFI ) { Modified |= CombineSetflagAluInBasicBlock ( & MF , & * MFI ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool isPairedLdSt ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: LDPSi : case AArch64 :: LDPSWi : case AArch64 :: LDPDi : case AArch64 :: LDPQi : case AArch64 :: LDPWi : case AArch64 :: LDPXi : case AArch64 :: STPSi : case AArch64 :: STPDi : case AArch64 :: STPQi : case AArch64 :: STPWi : case AArch64 :: STPXi : case AArch64 :: STGPi : return true ; } } </s>

Returns whether the instruction is a paired load/store .


<s> static tree aarch64_general_add_builtin ( const char * name , tree type , unsigned int code , tree attrs = NULL_TREE ) { code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_GENERAL ; return add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , attrs ) ; } </s>

Wrapper around add_builtin_function . NAME is the name of the built-in function , TYPE is the function type , CODE is the function subcode ( relative to AARCH64_BUILTIN_GENERAL ) , and ATTRS is the function attributes .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? TII . getFrameSize ( * I ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || F . needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . optForMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const char * aarch64_sls_barrier ( int mitigation_required ) { return mitigation_required ? ( TARGET_SB ? "sb" : "dsb\tsy\n\tisb" ) : "" ; } </s>

Helper function for straight line speculation . Return what barrier should be emitted for straight line speculation mitigation . When not mitigating against straight line speculation this function returns an empty string . When mitigating against straight line speculation , use : * SB when the v8.5-A SB extension is enabled . * DSB+ISB otherwise .


<s> static int rs6000_compute_pressure_classes ( enum reg_class * pressure_classes ) { int n ; n = 0 ; pressure_classes [ n ++ ] = GENERAL_REGS ; if ( TARGET_VSX ) pressure_classes [ n ++ ] = VSX_REGS ; else { if ( TARGET_ALTIVEC ) pressure_classes [ n ++ ] = ALTIVEC_REGS ; if ( TARGET_HARD_FLOAT && TARGET_FPRS ) pressure_classes [ n ++ ] = FLOAT_REGS ; } pressure_classes [ n ++ ] = CR_REGS ; pressure_classes [ n ++ ] = SPECIAL_REGS ; return n ; } </s>

Compute register pressure classes . We implement the target hook to avoid IRA picking something like GEN_OR_FLOAT_REGS as a pressure class , which can lead to incorrect estimates of number of available registers and therefor increased register pressure/spill .


<s> bool isDesirableToTransformToIntegerOp ( unsigned Opc , EVT VT ) const override { if ( Opc != ISD :: LOAD && Opc != ISD :: STORE ) return false ; if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; return true ; } </s>

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const override { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= 64 ) ; return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , HOST_WIDE_INT val ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits ) ; int i ; rtx cache = GEN_INT ( val ) ; for ( i = 0 ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = cache ; return gen_rtx_CONST_VECTOR ( mode , v ) ; } </s>


<s>
bool
PPCInstrInfo
::
FoldImmediate
(
MachineInstr
&
UseMI
,
MachineInstr
&
DefMI
,
Register
Reg
,
MachineRegisterInfo
*
MRI
)
const
{
unsigned
DefOpc
=
DefMI
.
getOpcode
(
)
;
if
(
DefOpc
!=
PPC
::
LI
&&
DefOpc
!=
PPC
::
LI8
)
return
false
;
if
(
!
DefMI
.
getOperand
(
1
)
.
isImm
(
)
)
return
false
;
if
(
DefMI
.
getOperand
(
1
)
.
getImm
(
)
!=
0
)
return
false
;
const
MCInstrDesc
&
UseMCID
=
UseMI
.
getDesc
(
)
;
if
(
UseMCID
.
isPseudo
(
)
)
return
false
;
unsigned
UseIdx
;
for
(
UseIdx
=
0
;
UseIdx
<
UseMI
.
getNumOperands
(
)
;
++
UseIdx
)
if
(
UseMI
.
getOperand
(
UseIdx
)
.
isReg
(
)
&&
UseMI
.
getOperand
(
UseIdx
)
.
getReg
(
)
==
Reg
)
break
;
assert
(
UseIdx
<
UseMI
.
getNumOperands
(
)
&&
"Cannot find Reg in UseMI"
)
;
assert
(
UseIdx
<
UseMCID
.
getNumOperands
(
)
&&
"No operand description for Reg"
)
;
const
MCOperandInfo
*
UseInfo
=
&
UseMCID
.
OpInfo
[
UseIdx
]
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
if
(
UseInfo
->
RegClass
!=
1
)
return
false
;
}
else
{
if
(
UseInfo
->
RegClass
!=
PPC
::
GPRC_NOR0RegClassID
&&
UseInfo
->
RegClass
!=
PPC
::
G8RC_NOX0RegClassID
)
return
false
;
}
if
(
UseInfo
->
Constraints
!=
0
)
return
false
;
MCRegister
ZeroReg
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
ZeroReg
=
isPPC64
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
else
{
ZeroReg
=
UseInfo
->
RegClass
==
PPC
::
G8RC_NOX0RegClassID
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
bool
DeleteDef
=
MRI
->
hasOneNonDBGUse
(
Reg
)
;
UseMI
.
getOperand
(
UseIdx
)
.
setReg
(
ZeroReg
)
;
if
(
DeleteDef
)
DefMI
.
eraseFromParent
(
)
;
return
true
;
}
</s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; return ( RealignStack && ! AFI -> isThumb1OnlyFunction ( ) && ( ! MFI -> hasVarSizedObjects ( ) || EnableBasePointer ) ) ; } </s>

True if the stack can be realigned for the target .


<s> rtx dimode_scalar_chain :: replace_with_subreg ( rtx x , rtx reg , rtx new_reg ) { if ( x == reg ) return gen_rtx_SUBREG ( V2DImode , new_reg , 0 ) ; const char * fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; int i , j ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) XEXP ( x , i ) = replace_with_subreg ( XEXP ( x , i ) , reg , new_reg ) ; else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) XVECEXP ( x , i , j ) = replace_with_subreg ( XVECEXP ( x , i , j ) , reg , new_reg ) ; } return x ; } </s>

Replace REG in X with a V2DI subreg of NEW_REG .


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Lanai :: LDW_RI ) if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getSubtargetImpl
(
)
->
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
isDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> const RegisterBankInfo :: InstructionMapping & X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) || Opc == TargetOpcode :: G_PHI ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; default : getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; break ; } SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return getInvalidInstructionMapping ( ) ; return getInstructionMapping ( DefaultMappingID , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const LanaiSubtarget & Subtarget = MF . getSubtarget < LanaiSubtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


<s> static bool tryAddingSymbolicOperand ( uint64_t Address , int32_t Value , bool isBranch , uint64_t InstSize , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , ( uint32_t ) Value , Address , isBranch , 0 , InstSize ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool SystemZTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


Check OP is a legal scalar immediate for the MOVI instruction .


<s> unsigned LanaiMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; if ( MCOp . isReg ( ) || MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , static_cast < MCFixupKind > ( Lanai :: FIXUP_LANAI_25 ) ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static bool abi_v4_pass_in_fpr ( machine_mode mode ) { if ( ! TARGET_FPRS || ! TARGET_HARD_FLOAT ) return false ; if ( TARGET_SINGLE_FLOAT && mode == SFmode ) return true ; if ( TARGET_DOUBLE_FLOAT && mode == DFmode ) return true ; if ( is_complex_IBM_long_double ( mode ) ) return false ; if ( FLOAT128_2REG_P ( mode ) ) return true ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return true ; return false ; } </s>

Whether ABI_V4 passes MODE args to a function in floating point registers .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const SystemZSubtarget & Subtarget = MF -> getSubtarget < SystemZSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_SystemZ_AllRegs_Vector_SaveList : CSR_SystemZ_AllRegs_SaveList ; if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_SaveList ; return CSR_SystemZ_SaveList ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const MCExpr * SparcELFTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MachineModuleInfoELF & ELFMMI = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , ".DW.stub" , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return SparcMCExpr :: Create ( SparcMCExpr :: VK_Sparc_R_DISP32 , MCSymbolRefExpr :: Create ( SSym , Ctx ) , Ctx ) ; } return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
Subtarget
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
IndirectTlsSegRefs
=
MF
.
getFunction
(
)
.
hasFnAttribute
(
"indirect-tls-seg-refs"
)
;
OptForMinSize
=
MF
.
getFunction
(
)
.
hasMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
)
&&
"OptForMinSize implies OptForSize"
)
;
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
<<
" Scale"
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" MCSym "
;
if
(
MCSym
)
dbgs
(
)
<<
MCSym
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" MCSym "
"nul"
" JT"
" Align"


<s> static int ix86_count_insn ( basic_block bb ) { edge e ; edge_iterator ei ; int min_prev_count ; min_prev_count = 4 ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { edge prev_e ; edge_iterator prev_ei ; if ( e -> src == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) { min_prev_count = 0 ; break ; } FOR_EACH_EDGE ( prev_e , prev_ei , e -> src -> preds ) { if ( prev_e -> src == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) { int count = ix86_count_insn_bb ( e -> src ) ; if ( count < min_prev_count ) min_prev_count = count ; break ; } } } if ( min_prev_count < 4 ) min_prev_count += ix86_count_insn_bb ( bb ) ; return min_prev_count ; } </s>

Count the minimum number of instructions in code path in BB . Return 4 if the number of instructions > = 4 .


<s> X86Subtarget & X86Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"********** AArch64 Conditional Compares **********\n"


<s>
bool
AArch64AsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> TargetPassConfig * AZPRTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AZPRPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool ARMFastISel :: isTypeLegal ( const Type * Ty , EVT & VT ) { VT = TLI . getValueType ( Ty , true ) ; if ( VT == MVT :: Other || ! VT . isSimple ( ) ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> rtx mmix_eh_return_handler_rtx ( void ) { return gen_rtx_REG ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ; } </s>


<s> void sh_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl , signed int n_named_args , machine_mode mode ) { pcum -> arg_count [ ( int ) SH_ARG_FLOAT ] = 0 ; pcum -> free_single_fp_reg = 0 ; pcum -> stack_regs = 0 ; pcum -> byref_regs = 0 ; pcum -> byref = 0 ; pcum -> outgoing = ( n_named_args == - 1 ) ? 0 : 1 ; pcum -> renesas_abi = sh_attr_renesas_p ( fntype ) ? 1 : 0 ; if ( fntype ) { pcum -> force_mem = ( ( TARGET_HITACHI || pcum -> renesas_abi ) && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ) ; pcum -> prototype_p = prototype_p ( fntype ) ; pcum -> arg_count [ ( int ) SH_ARG_INT ] = TARGET_SH5 && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ; pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && pcum -> arg_count [ ( int ) SH_ARG_INT ] == 0 && ( TYPE_MODE ( TREE_TYPE ( fntype ) ) == BLKmode ? int_size_in_bytes ( TREE_TYPE ( fntype ) ) : GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) ) > 4 && ( BASE_RETURN_VALUE_REG ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) == FIRST_RET_REG ) ) ; } else { pcum -> arg_count [ ( int ) SH_ARG_INT ] = 0 ; pcum -> prototype_p = FALSE ; if ( mode != VOIDmode ) { pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && GET_MODE_SIZE ( mode ) > 4 && BASE_RETURN_VALUE_REG ( mode ) == FIRST_RET_REG ) ; pcum -> force_mem = ( TARGET_DEFAULT & MASK_HITACHI ) && ( mode == BLKmode || ( GET_MODE_SIZE ( mode ) > 4 && ! ( mode == DFmode && TARGET_FPU_DOUBLE ) ) ) ; } else { pcum -> call_cookie = 0 ; pcum -> force_mem = FALSE ; } } } </s>

Initialize the CUMULATIVE_ARGS structure .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget . is64Bit ( ) ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> const char * get_bundle_name ( int b ) { return bundle_name [ b ] ; } </s>


<s> void VEPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
bool
AArch64BranchFixup
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
OffsetBits
)
{
int64_t
BrOffset
=
getOffsetOf
(
MI
)
;
int64_t
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination BB#"
<<
DestBB
->
getNumber
(
)
<<
" from BB#"
<<
MI
->
getParent
(
)
->
getNumber
(
)
<<
" bits available="
<<
OffsetBits
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
return
isIntN
(
OffsetBits
,
DestOffset
BrOffset
)
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

AArch64
AArch64
"Branch of destination BB#"
" from BB#"
" bits available="
" from "
" to "
" offset "
"\t"


<s> bool AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && ( TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA53 ( ) || TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA57 ( ) ) && usingDefaultRegAlloc ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
const
char
*
rs6000_insn_for_shift_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
3
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
mode
==
DImode
&&
ne
==
0
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
64
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rld%I2cl. %0,%1,%2,%3"
;
return
"rld%I2cl %0,%1,%2,%3"
;
}
if
(
mode
==
DImode
&&
nb
==
63
)
{
operands
[
3
]
=
GEN_INT
(
63
ne
)
;
if
(
dot
)
return
"rld%I2cr. %0,%1,%2,%3"
;
return
"rld%I2cr %0,%1,%2,%3"
;
}
if
(
mode
==
DImode
&&
GET_CODE
(
operands
[
4
]
)
!=
LSHIFTRT
&&
CONST_INT_P
(
operands
[
2
]
)
&&
ne
==
INTVAL
(
operands
[
2
]
)
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rld%I2c. %0,%1,%2,%3"
;
return
"rld%I2c %0,%1,%2,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
32
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlw%I2nm. %0,%1,%h2,%3,%4"
;
return
"rlw%I2nm %0,%1,%h2,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for a shift with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
TM
->
getSubtargetImpl
(
)
->
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
GETtlsADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
GETtlsldADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
GETtlsADDR32
&&
MI
->
getOpcode
(
)
!=
PPC
::
GETtlsldADDR32
)
continue
;
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
*
MI
;
)
;
unsigned
OutReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
GPR3
)
.
addReg
(
InReg
)
;
MI
->
getOperand
(
0
)
.
setReg
(
GPR3
)
;
MI
->
getOperand
(
1
)
.
setReg
(
GPR3
)
;
BuildMI
(
MBB
,
++
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> void LoongArchFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode ; int fp_reg_size = 8 ; int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> static bool csky_can_use_pushpop ( unsigned int mask ) { int i ; int end_reg ; if ( ! TARGET_PUSHPOP ) return false ; if ( mask == 0 ) return false ; if ( mask & 0xeffc700f ) return false ; for ( end_reg = 0 , i = 11 ; i >= 4 ; i -- ) { if ( ! end_reg && ( mask & ( 1 << i ) ) ) end_reg = i ; if ( end_reg && ! ( mask & ( 1 << i ) ) ) return false ; } for ( end_reg = 0 , i = 17 ; i >= 16 ; i -- ) { if ( ! end_reg && ( mask & ( 1 << i ) ) ) end_reg = i ; if ( end_reg && ! ( mask & ( 1 << i ) ) ) return false ; } return true ; } </s>

Return true if push/pop can be used to save/restore all the registers indicated by MASK . We currently do n't attempt to handle situations where some of the registers could be handled by push/pop and others saved and restored individually .


<s> static int moxie_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes_left , size ; if ( * cum >= 8 ) return 0 ; if ( moxie_pass_by_reference ( cum_v , mode , type , named ) ) size = 4 ; else if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return 0 ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; bytes_left = ( 4 * 6 ) - ( ( * cum - 2 ) * 4 ) ; if ( size > bytes_left ) return bytes_left ; else return 0 ; } </s>

Some function arguments will only partially fit in the registers that hold arguments . Given a new arg , return the number of bytes that fit in argument passing registers .


<s> int mmix_data_alignment ( tree type ATTRIBUTE_UNUSED , int basic_align ) { if ( basic_align < 32 ) return 32 ; return basic_align ; } </s>

DATA_ALIGNMENT . We have trouble getting the address of stuff that is located at other than 32-bit alignments ( GETA requirements ) , so try to give everything at least 32-bit alignment .


<s> bool isReg ( RegisterKind RegKind ) const { return Kind == KindReg && Reg . Kind == RegKind ; } </s>


<s> const LoongArchSubtarget & getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> MachineBasicBlock :: iterator MipsFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . IsN64 ( ) ? Mips :: SP_64 : Mips :: SP ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips Mips::SP_64 Mips::SP 0 Mips::ADJCALLSTACKDOWN


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_Ghc_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { isa &= ~ OPTION_MASK_ISA_64BIT ; if ( ( isa & deferred_isa_values ) == 0 && ( isa2 & deferred_isa_values2 ) == 0 && ( ( deferred_isa_values & OPTION_MASK_ISA_MMX ) == 0 || ! ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) ) ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; if ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) deferred_isa_values &= ~ OPTION_MASK_ISA_MMX ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != 0 || ( ( ix86_builtins_isa [ i ] . isa & OPTION_MASK_ISA_MMX ) != 0 && TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
)
const
{
assert
(
(
(
Val
&&
!
VRegs
.
empty
(
)
)
||
(
!
Val
&&
VRegs
.
empty
(
)
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
!
VRegs
.
empty
(
)
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
ArgInfo
OrigRetInfo
(
VRegs
,
Val
->
getType
(
)
)
;
setArgFlags
(
OrigRetInfo
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
4
>
SplitRetInfos
;
splitToValueTypes
(
OrigRetInfo
,
SplitRetInfos
,
DL
,
F
.
getCallingConv
(
)
)
;
X86OutgoingValueAssigner
Assigner
(
RetCC_X86
)
;
X86OutgoingValueHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
)
;
if
(
!
determineAndHandleAssignments
(
Handler
,
Assigner
,
SplitRetInfos
,
MIRBuilder
,
F
.
getCallingConv
(
)
,
F
.
isVarArg
(
)
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> virtual const InstrItineraryData getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> int pa_adjust_insn_length ( rtx_insn * insn , int length ) { rtx pat = PATTERN ( insn ) ; if ( ( unsigned int ) length >= INT_MAX ) { if ( GET_CODE ( pat ) == SEQUENCE ) insn = as_a < rtx_insn * > ( XVECEXP ( pat , 0 , 0 ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MILLI : length = pa_attr_length_millicode_call ( insn ) ; break ; case TYPE_CALL : length = pa_attr_length_call ( insn , 0 ) ; break ; case TYPE_SIBCALL : length = pa_attr_length_call ( insn , 1 ) ; break ; case TYPE_DYNCALL : length = pa_attr_length_indirect_call ( insn ) ; break ; case TYPE_SH_FUNC_ADRS : length = pa_attr_length_millicode_call ( insn ) + 20 ; break ; default : gcc_unreachable ( ) ; } } if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == BLKmode ) length += compute_cpymem_length ( insn ) - 4 ; else if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) == const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode ) length += compute_clrmem_length ( insn ) - 4 ; else if ( JUMP_P ( insn ) && ! simplejump_p ( insn ) ) { if ( GET_CODE ( pat ) == SET && length == 4 && JUMP_LABEL ( insn ) != NULL_RTX && ! forward_branch_p ( insn ) ) length += 4 ; else if ( GET_CODE ( pat ) == PARALLEL && get_attr_type ( insn ) == TYPE_PARALLEL_BRANCH && length == 4 ) length += 4 ; else if ( GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 1 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) == REG && ! FP_REG_P ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) && length == 4 && ! forward_branch_p ( insn ) ) length += 4 ; } return length ; } </s>

Return any length adjustment needed by INSN which already has its length computed as LENGTH . Return zero if no adjustment is necessary . For the PA : function calls , millicode calls , and backwards short conditional branches with unfilled delay slots need an adjustment by +1 ( to account for the NOP which will be inserted into the instruction stream ) . Also compute the length of an inline block move here as it is too complicated to express as a length attribute in pa.md .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; unsigned Offset = getTargetMachine ( ) . Options . StackProtectorGuardOffset ; if ( Offset == ( unsigned ) - 1 ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; auto GuardReg = getTargetMachine ( ) . Options . StackProtectorGuardReg ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


getPassName - Return a nice clean name for a pass .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ; } </s>


<s> bool mayNeedRelaxation ( const MCInst & ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> HOST_WIDE_INT ia64_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; ia64_compute_frame_size ( get_frame_size ( ) ) ; switch ( from ) { case FRAME_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : if ( current_function_is_leaf ) offset = - current_frame_info . total_size ; else offset = - ( current_frame_info . total_size - current_function_outgoing_args_size - 16 ) ; break ; case STACK_POINTER_REGNUM : if ( current_function_is_leaf ) offset = 0 ; else offset = 16 + current_function_outgoing_args_size ; break ; default : gcc_unreachable ( ) ; } break ; case ARG_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : offset = 16 - current_function_pretend_args_size ; break ; case STACK_POINTER_REGNUM : offset = ( current_frame_info . total_size + 16 - current_function_pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } return offset ; } </s>

Compute the initial difference between the specified pair of registers .


<s> bool AArch64LoadStoreOpt :: isCandidateToMergeOrPair ( MachineInstr * MI ) { if ( MI -> hasOrderedMemoryRef ( ) ) return false ; if ( ! getLdStOffsetOp ( MI ) . isImm ( ) ) return false ; unsigned BaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; if ( MI -> modifiesRegister ( BaseReg , TRI ) ) return false ; if ( TII -> isLdStPairSuppressed ( MI ) ) return false ; return true ; } </s>

Return true if this is a load/store that can be potentially paired/merged .


<s> rtx ix86_build_signbit_mask ( machine_mode mode , bool vect , bool invert ) { machine_mode vec_mode , imode ; wide_int w ; rtx mask , v ; switch ( mode ) { case E_V16SImode : case E_V16SFmode : case E_V8SImode : case E_V4SImode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : vec_mode = mode ; imode = SImode ; break ; case E_V8DImode : case E_V4DImode : case E_V2DImode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : vec_mode = mode ; imode = DImode ; break ; case E_TImode : case E_TFmode : vec_mode = VOIDmode ; imode = TImode ; break ; default : gcc_unreachable ( ) ; } machine_mode inner_mode = GET_MODE_INNER ( mode ) ; w = wi :: set_bit_in_zero ( GET_MODE_BITSIZE ( inner_mode ) - 1 , GET_MODE_BITSIZE ( inner_mode ) ) ; if ( invert ) w = wi :: bit_not ( w ) ; mask = immed_wide_int_const ( w , imode ) ; mask = gen_lowpart ( inner_mode , mask ) ; if ( vec_mode == VOIDmode ) return force_reg ( inner_mode , mask ) ; v = ix86_build_const_vector ( vec_mode , vect , mask ) ; return force_reg ( vec_mode , v ) ; } </s>

A subroutine of ix86_expand_fp_absneg_operator and copysign expanders . Create a mask for the sign bit in MODE for an SSE register . If VECT is true , then replicate the mask for all elements of the vector register . If INVERT is true , then create a mask excluding the sign bit .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool MMIXFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool F2003fMCAsmInfo :: isValidUnquotedName ( StringRef Name ) const { if ( Name . empty ( ) ) return false ; if ( Name . size ( ) == 2 ) { if ( Name [ 0 ] == 'f' && Name [ 1 ] >= '0' && Name [ 1 ] <= '7' ) return false ; if ( Name . equals ( "xx" ) ) return false ; } if ( Name [ 0 ] == '\'' ) { return false ; } bool hasNonNumericChar = false ; for ( char C : Name ) { if ( ! hasNonNumericChar && ( C <= '0' || C >= '9' ) ) { hasNonNumericChar = true ; } if ( ! isAcceptableChar ( C ) ) return false ; } return hasNonNumericChar ; } </s>

Return true if the identifier Name does not need quotes to be syntactically correct .


<s> bool arm_needs_doubleword_align ( enum machine_mode mode , tree type ) { return ( GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY || ( type && TYPE_ALIGN ( type ) > PARM_BOUNDARY ) ) ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


Output the assembly for a call instruction .


<s> static rtx mips_pic_call_symbol_from_set ( df_ref def , rtx reg , bool recurse_p ) { rtx_insn * def_insn ; rtx set ; if ( DF_REF_IS_ARTIFICIAL ( def ) ) return NULL_RTX ; def_insn = DF_REF_INSN ( def ) ; set = single_set ( def_insn ) ; if ( set && rtx_equal_p ( SET_DEST ( set ) , reg ) ) { rtx note , src , symbol ; src = SET_SRC ( set ) ; if ( GET_CODE ( src ) == SYMBOL_REF ) return src ; symbol = mips_strip_unspec_call ( src ) ; if ( symbol ) { gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; return symbol ; } note = find_reg_equal_equiv_note ( def_insn ) ; if ( note && GET_CODE ( XEXP ( note , 0 ) ) == SYMBOL_REF ) return XEXP ( note , 0 ) ; if ( recurse_p && REG_P ( src ) ) return mips_find_pic_call_symbol ( def_insn , src , false ) ; } return NULL_RTX ; } </s>

REG is set in DEF . See if the definition is one of the ways we load a register with a symbol address for a mips_use_pic_fn_addr_reg_p call . If it is , return the symbol reference of the function , otherwise return NULL_RTX . If RECURSE_P is true , use mips_find_pic_call_symbol to interpret the values of source registers , otherwise treat such registers as having an unknown value .


<s> static bool ix86_eax_live_at_start_p ( void ) { return REGNO_REG_SET_P ( df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) , 0 ) ; } </s>

Return true if EAX is live at the start of the function . Used by ix86_expand_prologue to determine if we need special help before calling allocate_stack_worker .


<s>
static
void
rs6000_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
if
(
!
cfun
->
is_thunk
)
rs6000_output_savres_externs
(
file
)
;
if
(
rs6000_global_entry_point_needed_p
(
)
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
file
,
"LCF"
,
rs6000_pic_labelno
)
;
if
(
TARGET_CMODEL
!=
CMODEL_LARGE
)
{
char
buf
[
256
]
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCF"
,
rs6000_pic_labelno
)
;
fprintf
(
file
,
"0:\taddis 2,12,.TOC.-"
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"@ha\n"
)
;
fprintf
(
file
,
"\taddi 2,2,.TOC.-"
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"@l\n"
)
;
}
else
{
char
buf
[
256
]
;
fprintf
(
file
,
"\t.reloc .,R_PPC64_ENTRY\n"
)
;
fprintf
(
file
,
"\tld 2,"
)
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCL"
,
rs6000_pic_labelno
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"-"
)
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCF"
,
rs6000_pic_labelno
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"(12)\n"
)
;
fprintf
(
file
,
"\tadd 2,2,12\n"
)
;
}
fputs
(
"\t.localentry\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
",.-"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
"\n"
,
file
)
;
}
if
(
TARGET_PROFILE_KERNEL
&&
crtl
->
profile
)
{
gcc_assert
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
;
gcc_assert
(
!
TARGET_32BIT
)
;
asm_fprintf
(
file
,
"\tmflr %s\n"
,
reg_names
[
0
]
)
;
if
(
DEFAULT_ABI
!=
ABI_ELFv2
&&
cfun
->
static_chain_decl
!=
)
{
asm_fprintf
(
file
,
"\tstd %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
asm_fprintf
(
file
,
"\tld %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
}
else
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
}
rs6000_pic_labelno
++
;
}
</s>


<s> static bool pa_function_value_regno_p ( const unsigned int regno ) { if ( regno == 28 || ( ! TARGET_SOFT_FLOAT && regno == 32 ) ) return true ; return false ; } </s>

Implement the TARGET_FUNCTION_VALUE_REGNO_P hook .


<s>
void
SystemZHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCSchedClassDesc
*
SC
=
getSchedClass
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"++ HazardRecognizer emitting "
;
dumpSU
(
SU
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
LLVM_DEBUG
(
dumpCurrGroup
(
"Decode group before emission"
)
;
)
;
if
(
!
fitsIntoCurrentGroup
(
SU
)
)
nextGroup
(
)
;
LLVM_DEBUG
(
raw_string_ostream
cgd
(
CurGroupDbg
)
;
if
(
CurGroupDbg
.
length
(
)
)
cgd
<<
", "
;
dumpSU
(
SU
,
cgd
)
;
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
if
(
SU
->
isCall
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"++ Clearing state after call.\n"
;
)
;
Reset
(
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
return
;
}
for
(
TargetSchedModel
::
ProcResIter
PI
=
SchedModel
->
getWriteProcResBegin
(
SC
)
,
PE
=
SchedModel
->
getWriteProcResEnd
(
SC
)
;
PI
!=
PE
;
++
PI
)
{
if
(
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
BufferSize
==
1
)
continue
;
int
&
CurrCounter
=
ProcResourceCounters
[
PI
->
ProcResourceIdx
]
;
CurrCounter
+=
PI
->
Cycles
;
if
(
(
CurrCounter
>
ProcResCostLim
)
&&
(
CriticalResourceIdx
==
UINT_MAX
||
(
PI
->
ProcResourceIdx
!=
CriticalResourceIdx
&&
CurrCounter
>
ProcResourceCounters
[
CriticalResourceIdx
]
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"++ New critical resource: "
<<
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
Name
<<
"\n"
;
)
;
CriticalResourceIdx
=
PI
->
ProcResourceIdx
;
}
}
if
(
SU
->
isUnbuffered
)
{
LastFPdOpCycleIdx
=
getCurrCycleIdx
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"++ Last FPd cycle index: "
<<
LastFPdOpCycleIdx
<<
"\n"
;
)
;
}
CurrGroupSize
+=
getNumDecoderSlots
(
SU
)
;
assert
(
CurrGroupSize
<=
3
)
;
if
(
CurrGroupSize
==
3
||
SC
->
EndGroup
)
nextGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

SystemZ
SystemZ
"++ HazardRecognizer emitting "
"\n"
"Decode group before emission"
", "
"++ Clearing state after call.\n"
1
"++ New critical resource: "
"\n"
"++ Last FPd cycle index: "
"\n"
3
3


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
add
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
add
(
MI
.
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
NewMI
.
add
(
condCodeOp
(
)
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
add
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & Fn . getSubtarget < ARMSubtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = DistributeIncrements ( ) ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void core2i7_dfa_post_advance_cycle ( void ) { ix86_first_cycle_multipass_data_t data = ix86_first_cycle_multipass_data ; gcc_assert ( data -> ifetch_block_n_insns <= core2i7_ifetch_block_max_insns ) ; data -> ifetch_block_len = 0 ; data -> ifetch_block_n_insns = 0 ; } </s>

Advancing the cycle ; reset ifetch block counts .


"rs6000_secondary_reload_inner:%d, type = %s\n"

Better tracing for rs6000_secondary_reload_inner .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
const
ARMFunctionInfo
&
AFI
=
*
C
.
getMF
(
)
->
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveToReg
(
MBB
,
It
,
Reg
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromReg
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
if
(
!
MBB
.
isLiveIn
(
ARM
::
LR
)
)
MBB
.
addLiveIn
(
ARM
::
LR
)
;
bool
Auth
=
!
AFI
.
isLRSpilled
(
)
&&
AFI
.
shouldSignReturnAddress
(
true
)
;
saveLROnStack
(
MBB
,
It
,
!
AFI
.
isLRSpilled
(
)
,
Auth
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
restoreLRFromStack
(
MBB
,
It
,
!
AFI
.
isLRSpilled
(
)
,
Auth
)
;
It
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
ARM
ARM
0
"No callee-saved register available?"
ARM::LR
ARM::LR
ARM::LR
ARM::LR


<s>
static
void
rs6000_output_function_prologue
(
FILE
*
file
)
{
if
(
!
cfun
->
is_thunk
)
rs6000_output_savres_externs
(
file
)
;
if
(
rs6000_global_entry_point_needed_p
(
)
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
file
,
"LCF"
,
rs6000_pic_labelno
)
;
if
(
TARGET_CMODEL
!=
CMODEL_LARGE
)
{
char
buf
[
256
]
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCF"
,
rs6000_pic_labelno
)
;
fprintf
(
file
,
"0:\taddis 2,12,.TOC.-"
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"@ha\n"
)
;
fprintf
(
file
,
"\taddi 2,2,.TOC.-"
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"@l\n"
)
;
}
else
{
char
buf
[
256
]
;
fprintf
(
file
,
"\t.reloc .,R_PPC64_ENTRY\n"
)
;
fprintf
(
file
,
"\tld 2,"
)
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCL"
,
rs6000_pic_labelno
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"-"
)
;
ASM_GENERATE_INTERNAL_LABEL
(
buf
,
"LCF"
,
rs6000_pic_labelno
)
;
assemble_name
(
file
,
buf
)
;
fprintf
(
file
,
"(12)\n"
)
;
fprintf
(
file
,
"\tadd 2,2,12\n"
)
;
}
fputs
(
"\t.localentry\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
",.-"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
"\n"
,
file
)
;
}
if
(
TARGET_PROFILE_KERNEL
&&
crtl
->
profile
)
{
gcc_assert
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
;
gcc_assert
(
!
TARGET_32BIT
)
;
asm_fprintf
(
file
,
"\tmflr %s\n"
,
reg_names
[
0
]
)
;
if
(
DEFAULT_ABI
!=
ABI_ELFv2
&&
cfun
->
static_chain_decl
!=
)
{
asm_fprintf
(
file
,
"\tstd %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
asm_fprintf
(
file
,
"\tld %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
}
else
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
}
rs6000_pic_labelno
++
;
}
</s>


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
unsigned
Opcode
=
Op
.
getOpcode
(
)
;
if
(
ISD
::
isVPOpcode
(
Opcode
)
)
return
lowerToVVP
(
Op
,
DAG
)
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_SWAP
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_LONGJMP
:
return
lowerEH_SJLJ_LONGJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETJMP
:
return
lowerEH_SJLJ_SETJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETUP_DISPATCH
:
return
lowerEH_SJLJ_SETUP_DISPATCH
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
lowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
INSERT_VECTOR_ELT
:
return
lowerINSERT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
lowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
return
lowerToVVP
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
SDValue
DCPU16TargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
DebugLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
DCPU16_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> bool useAA ( ) const override { return UseAA ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


"LC2200 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static reg_class_t loongarch_canonicalize_move_class ( reg_class_t rclass ) { if ( reg_class_subset_p ( rclass , GENERAL_REGS ) ) rclass = GENERAL_REGS ; return rclass ; } </s>

RCLASS is a class involved in a REGISTER_MOVE_COST calculation . Return a `` canonical '' class to represent it in later calculations .


<s> bool X86AsmParser :: OmitRegisterFromClobberLists ( unsigned RegNo ) { return X86MCRegisterClasses [ X86 :: SEGMENT_REGRegClassID ] . contains ( RegNo ) ; } </s>

Allows targets to let registers opt out of clobber lists .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> static void flow_dependent_p_1 ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_referenced_p ( x , * pinsn ) ) * pinsn = NULL_RTX ; } </s>

A helper function for flow_dependent_p called through note_stores .


<s>
void
rs6000_xcoff_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
tree
decl
)
{
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
1
)
;
char
*
p
;
int
dollar_inside
=
0
;
struct
declare_alias_data
data
=
{
file
,
false
}
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
decl
)
)
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.globl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
rs6000_xcoff_visibility
(
decl
)
,
file
)
;
putc
(
'\n'
,
file
)
;
}
}
else
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.lglobl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
fputs
(
"\t.csect "
,
file
)
;
assemble_name
(
file
,
buffer
)
;
fputs
(
TARGET_32BIT
"\n"
:
",3\n"
,
file
)
;
ASM_OUTPUT_LABEL
(
file
,
buffer
)
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
fputs
(
TARGET_32BIT
"\t.long ."
:
"\t.llong ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
", TOC[tc0], 0\n"
,
file
)
;
in_section
=
;
switch_to_section
(
function_section
(
decl
)
)
;
putc
(
'.'
,
file
)
;
ASM_OUTPUT_LABEL
(
file
,
buffer
)
;
data
.
function_descriptor
=
true
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
if
(
!
DECL_IGNORED_P
(
decl
)
)
{
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
xcoffout_declare_function
(
file
,
decl
,
buffer
)
;
else
if
(
dwarf_debuginfo_p
(
)
)
{
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
fprintf
(
file
,
"\t.function .%s,.%s,2,0\n"
,
name
,
name
)
;
}
}
return
;
}
</s>

This macro produces the initial definition of a function name . On the RS/6000 , we need to place an extra ' . ' in the function name and output the function descriptor . Dollar signs are converted to underscores . The csect for the function will have already been created when text_section was selected . We do have to go back to that csect , however . The third and fourth parameters to the .function pseudo-op ( 16 and 044 ) are placeholders which no longer have any use . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> Register OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( Mips :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = I -> first ; if ( isPPC64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , 4 ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static bool isZero ( SDValue V ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( V ) ; return C && C -> isNullValue ( ) ; } </s>

Return true if the expression is a constant zero .


<s> static bool rs6000_expand_vec_perm_const_1 ( rtx target , rtx op0 , rtx op1 , unsigned char perm0 , unsigned char perm1 ) { rtx x ; if ( ( perm0 & 2 ) == ( perm1 & 2 ) ) { if ( perm0 & 2 ) op0 = op1 ; else op1 = op0 ; } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & 1 ; perm1 = ( perm1 & 1 ) + 2 ; } else if ( perm0 & 2 ) { if ( perm1 & 2 ) return false ; perm0 -= 2 ; perm1 += 2 ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & 2 ) == 0 ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == 2 ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , 4 ) . require ( ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( 2 , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } return true ; } </s>

Expand a Paired Single or VSX Permute Doubleword constant permutation . Return true if we match an efficient implementation .


<s> void MipsELFStreamer :: EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = 0 ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } createPendingLabelRelocs ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
SDValue
MipsTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
,
TargetLowering
::
CallLoweringInfo
&
CLI
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MipsCCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Mips
,
CLI
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
RVLocs
[
i
]
.
getLocReg
(
)
,
RVLocs
[
i
]
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
if
(
VA
.
isUpperBitsInLoc
(
)
)
{
unsigned
ValSizeInBits
=
Ins
[
i
]
.
ArgVT
.
getSizeInBits
(
)
;
unsigned
LocSizeInBits
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
unsigned
Shift
=
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExtUpper
ISD
::
SRL
:
ISD
::
SRA
;
Val
=
DAG
.
getNode
(
Shift
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getConstant
(
LocSizeInBits
ValSizeInBits
,
DL
,
VA
.
getLocVT
(
)
)
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
AExt
:
case
CCValAssign
::
AExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
case
CCValAssign
::
ZExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
case
CCValAssign
::
SExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

Mips
Mips
ISD::InputArg
16
Mips
Mips
0
"Can only return in registers!"
1
2
ISD::SRL
ISD::SRA
"Unknown loc info!"
ISD::BITCAST
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> bool SparcTargetLowering :: useLoadStackGuardNode ( ) const { if ( ! Subtarget -> isTargetLinux ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


"\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "

"opno = %d, total = %d, speed = %s, x:\n"

Debug form of r6000_rtx_costs that is selected if -mdebug=cost .


<s> StringRef getPassName ( ) const override { return AARCH64_ADVSIMD_NAME ; } </s>


<s> SDValue PPCTargetLowering :: getSqrtResultForDenormInput ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: f64 && ( ( VT != MVT :: v2f64 && VT != MVT :: v4f32 ) || ! Subtarget . hasVSX ( ) ) ) return TargetLowering :: getSqrtResultForDenormInput ( Op , DAG ) ; return DAG . getNode ( PPCISD :: FSQRT , SDLoc ( Op ) , VT , Op ) ; } </s>

Return a target-dependent result if the input operand is not suitable for use with a square root estimate calculation .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86SpeculativeLoadHardeningPass ( ) ) ; addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> TargetTransformInfo PPCTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( PPCTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static int pru_function_arg_size ( machine_mode mode , const_tree type ) { HOST_WIDE_INT param_size ; if ( mode == BLKmode ) param_size = int_size_in_bytes ( type ) ; else param_size = GET_MODE_SIZE ( mode ) ; param_size = ( UNITS_PER_WORD - 1 + param_size ) / UNITS_PER_WORD ; gcc_assert ( param_size >= 0 ) ; return param_size ; } </s>

Return the number of bytes needed for storing an argument with the given MODE and TYPE .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool sh_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P ) { rtx base , offset ; split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base , INTVAL ( offset ) ) ) return false ; } if ( TARGET_FDPIC && ( SYMBOLIC_CONST_P ( x ) || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && SYMBOLIC_CONST_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) ) ) return false ; return GET_CODE ( x ) != CONST_DOUBLE || mode == DFmode || mode == SFmode || mode == DImode || GET_MODE ( x ) == VOIDmode ; } </s>


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; PPCFunctionInfo * FI = MF -> getInfo < PPCFunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == PPC :: X2 || Reg == PPC :: R2 ) && MustSaveTOC ) continue ; if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( ! Subtarget . is32BitELFABI ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . storeRegToStackSlotNoUpd ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; else TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void rs6000_asm_output_dwarf_datarel ( FILE * file , int size , const char * label ) { fputs ( integer_asm_op ( size , FALSE ) , file ) ; assemble_name ( file , label ) ; fputs ( "-__gcc_unwind_dbase" , file ) ; } </s>

Output a symbol offset relative to the dbase for the current object . We use __gcc_unwind_dbase as an arbitrary base for dbase and assume signed offsets . __gcc_unwind_dbase is embedded in all executables/libraries through libgcc/config/rs6000/crtdbase.S .


<s> static bool aarch64_option_valid_attribute_p ( tree fndecl , tree , tree args , int ) { struct cl_target_option cur_target ; bool ret ; tree old_optimize ; tree new_target , new_optimize ; tree existing_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! existing_target && args == current_target_pragma ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_option_current_node ; return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , existing_options ) ; } else cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options ) ; if ( fndecl && ret ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret ; } </s>

Implement TARGET_OPTION_VALID_ATTRIBUTE_P . This is used to process attribute ( ( target ( `` ... '' ) ) ) .


<s> static inline bool is_float128_p ( tree t ) { return ( t == float128_type_node || ( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && t == long_double_type_node ) ) ; } </s>

Check whether the type of an argument , T , is compatible with a type ID stored into a struct altivec_builtin_types . Integer types are considered compatible ; otherwise , the language hook lang_hooks.types_compatible_p makes the decision . Also allow long double and _Float128 to be compatible if -mabi=ieeelongdouble .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; bool hasGPR = false ; unsigned FirstReg = 0 ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; if ( ! MF . protectCSRs ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else if ( ! hasGPR ) { FirstReg = Reg ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; hasGPR = true ; } else { BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MI , DL , TII . get ( X86 :: ADD64rr ) , FirstReg ) . addReg ( FirstReg ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } if ( MF . protectCSRs ( ) && hasGPR ) { assert ( FirstReg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( FirstReg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

ARM ARM ARM::SP ARM::PC ARM::FPSCR ARM::R9


"argument %d of %qE must be an integer constant"

Report that LOCATION has a call to FNDECL in which argument ARGNO was not an integer constant expression . ARGNO counts from zero .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && ! IsCCallConvention ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? DAG . getTarget ( ) . getSubtarget < AArch64Subtarget > ( ) . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * DAG . getTarget ( ) . getSubtarget < AArch64Subtarget > ( ) . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> CCAssignFn * X86FastISel :: CCAssignFnForCall ( CallingConv :: ID CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( CC == CallingConv :: GHC ) return CC_X86_64_GHC ; else if ( Subtarget -> isTargetWin64 ( ) ) return CC_X86_Win64_C ; else return CC_X86_64_C ; } if ( CC == CallingConv :: X86_FastCall ) return CC_X86_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_X86_32_FastCC ; else if ( CC == CallingConv :: GHC ) return CC_X86_32_GHC ; else return CC_X86_32_C ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool SystemZTargetLowering :: allowTruncateForTailCall ( Type * FromType , Type * ToType ) const { return isTruncateFree ( FromType , ToType ) ; } </s>

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position .


<s> bool FixAllFDIVSQRT :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < SparcSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = DebugLoc ( ) ; bool Modified = false ; for ( auto MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( MI . isInlineAsm ( ) ) { std :: string AsmString ( MI . getOperand ( InlineAsm :: MIOp_AsmString ) . getSymbolName ( ) ) ; std :: string FSQRTDOpCode ( "fsqrtd" ) ; std :: string FDIVDOpCode ( "fdivd" ) ; std :: transform ( AsmString . begin ( ) , AsmString . end ( ) , AsmString . begin ( ) , :: tolower ) ; if ( AsmString . find ( FSQRTDOpCode ) == 0 ) { Opcode = SP :: FSQRTD ; } else if ( AsmString . find ( FDIVDOpCode ) == 0 ) { Opcode = SP :: FDIVD ; } } if ( Opcode == SP :: FSQRTD || Opcode == SP :: FDIVD ) { for ( int InsertedCount = 0 ; InsertedCount < 5 ; InsertedCount ++ ) BuildMI ( MBB , MBBI , DL , TII . get ( SP :: NOP ) ) ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; for ( int InsertedCount = 0 ; InsertedCount < 28 ; InsertedCount ++ ) BuildMI ( MBB , NMBBI , DL , TII . get ( SP :: NOP ) ) ; Modified = true ; } } } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCELFStreamer & CSKYTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> BitVector Cpu0RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Cpu0 :: ZERO , Cpu0 :: AT , Cpu0 :: SP , Cpu0 :: LR , Cpu0 :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( Cpu0 :: FP ) ; } const Cpu0FunctionInfo * Cpu0FI = MF . getInfo < Cpu0FunctionInfo > ( ) ; if ( Cpu0FI -> globalBaseRegFixed ( ) ) Reserved . set ( Cpu0 :: GP ) ; return Reserved ; } </s>


<s> bool X86TargetLowering :: isLoadBitCastBeneficial ( EVT LoadVT , EVT BitcastVT ) const { if ( ! Subtarget . hasAVX512 ( ) && ! LoadVT . isVector ( ) && BitcastVT . isVector ( ) && BitcastVT . getVectorElementType ( ) == MVT :: i1 ) return false ; if ( ! Subtarget . hasDQI ( ) && BitcastVT == MVT :: v8i1 && LoadVT == MVT :: i8 ) return false ; return TargetLowering :: isLoadBitCastBeneficial ( LoadVT , BitcastVT ) ; } </s>

Return true if the following transform is beneficial : fold ( conv ( load x ) ) - > ( load ( conv * ) x ) On architectures that do n't natively support some vector loads efficiently , casting the load to a smaller vector of larger types and loading is more efficient , however , this can be undone by optimizations in dag combiner .