<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
uint64_t
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
unsigned
width
,
enum
simd_immediate_check
which
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
&
info
,
which
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
GET_MODE_BITSIZE
(
info
.
elt_mode
)
)
;
lane_count
=
width
/
GET_MODE_BITSIZE
(
info
.
elt_mode
)
;
if
(
GET_MODE_CLASS
(
info
.
elt_mode
)
==
MODE_FLOAT
)
{
gcc_assert
(
info
.
insn
==
simd_immediate_info
::
MOV
&&
info
.
u
.
mov
.
shift
==
0
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
u
.
mov
.
value
)
)
info
.
u
.
mov
.
value
=
GEN_INT
(
0
)
;
else
{
const
unsigned
int
buf_size
=
20
;
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
u
.
mov
.
value
)
,
buf_size
,
buf_size
,
1
,
info
.
elt_mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
gcc_assert
(
CONST_INT_P
(
info
.
u
.
mov
.
value
)
)
;
if
(
which
==
AARCH64_CHECK_MOV
)
{
mnemonic
=
info
.
insn
==
simd_immediate_info
::
MVN
"mvni"
:
"movi"
;
shift_op
=
(
info
.
u
.
mov
.
modifier
==
simd_immediate_info
::
MSL
"msl"
:
"lsl"
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
u
.
mov
.
value
)
)
;
else
if
(
info
.
u
.
mov
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
u
.
mov
.
value
)
,
shift_op
,
info
.
u
.
mov
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
u
.
mov
.
value
)
)
;
}
else
{
mnemonic
=
info
.
insn
==
simd_immediate_info
::
MVN
"bic"
:
"orr"
;
if
(
info
.
u
.
mov
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, #"
HOST_WIDE_INT_PRINT_DEC
", %s #%d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
u
.
mov
.
value
)
,
"lsl"
,
info
.
u
.
mov
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, #"
HOST_WIDE_INT_PRINT_DEC
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
u
.
mov
.
value
)
)
;
}
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


<s> static int ia64_reloc_rw_mask ( void ) { return flag_pic ? 3 : 2 ; } </s>

For others , relax this so that relocations to local data goes in read-only segments , but we still can not allow global relocations in read-only segments .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentAndEmitInstruction ( Inst , Operands , getContext ( ) , MII , Out , getParser ( ) . shouldPrintSchedInfo ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool offsettable_ok_by_alignment ( rtx op , HOST_WIDE_INT offset , machine_mode mode ) { tree decl ; unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( GET_CODE ( op ) != SYMBOL_REF ) return false ; if ( mode_supports_vsx_dform_quad ( mode ) ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == 0 ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == 0 ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > 32768 ) return false ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; return dalign >= dsize ; } } else gcc_unreachable ( ) ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; mask = dalign - 1 ; lsb = offset & - offset ; mask &= lsb - 1 ; dalign = mask + 1 ; return dalign >= dsize ; } </s>

Return true if a MODE sized memory accesses to OP plus OFFSET is known to not straddle a 32k boundary .


<s> MachineBasicBlock :: iterator LanaiFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const predefined_function_abi & ix86_insn_callee_abi ( const rtx_insn * insn ) { unsigned int abi_id = 0 ; rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) ) abi_id = ABI_VZEROUPPER ; return function_abis [ abi_id ] ; } </s>


<s> const char * output_branchy_insn ( enum rtx_code code , const char * templ , rtx_insn * insn , rtx * operands ) { rtx_insn * next_insn = NEXT_INSN ( insn ) ; if ( next_insn && JUMP_P ( next_insn ) && condjump_p ( next_insn ) ) { rtx src = SET_SRC ( PATTERN ( next_insn ) ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE && GET_CODE ( XEXP ( src , 0 ) ) != code ) { rtx_code_label * lab = gen_label_rtx ( ) ; emit_label_after ( lab , next_insn ) ; INSN_ADDRESSES_NEW ( lab , INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + get_attr_length ( next_insn ) ) ; operands [ 9 ] = lab ; return templ ; } else { int offset = ( branch_dest ( next_insn ) - INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + 4 ) ; if ( offset >= - 252 && offset <= 258 ) { if ( GET_CODE ( src ) == IF_THEN_ELSE ) src = XEXP ( src , 1 ) ; operands [ 9 ] = src ; return templ ; } } } rtx_code_label * lab = gen_label_rtx ( ) ; emit_label_after ( lab , insn ) ; INSN_ADDRESSES_NEW ( lab , INSN_ADDRESSES ( INSN_UID ( insn ) ) + get_attr_length ( insn ) ) ; operands [ 9 ] = lab ; return templ ; } </s>

Output a code sequence for INSN using TEMPL with OPERANDS ; but before , fill in operands 9 as a label to the successor insn . We try to use jump threading where possible . IF CODE matches the comparison in the IF_THEN_ELSE of a following jump , we assume the jump is taken . I.e . EQ means follow jmp and bf , NE means follow jmp and bt , if the address is in range .


<s> static void xstormy16_asm_out_destructor ( rtx symbol , int priority ) { const char * section = ".dtors" ; char buf [ 16 ] ; if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , ".dtors.%.5u" , MAX_INIT_PRIORITY - priority ) ; section = buf ; } named_section_flags ( section , 0 ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , POINTER_SIZE , 1 ) ; } </s>

Output constructors and destructors . Just like default_named_section_asm_out_ * but do n't set the sections writable .


"Can only put epilog before 'retl' or 'tail_call' instruction!"


<s> static rtx rs6000_mask_atomic_subword ( rtx oldval , rtx newval , rtx mask ) { rtx x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , oldval ) ) ) ; x = expand_simple_binop ( SImode , IOR , newval , x , x , 1 , OPTAB_LIB_WIDEN ) ; return x ; } </s>

A subroutine of the various atomic expanders . For sub-word operands , combine OLDVAL and NEWVAL via MASK . Returns a new pseduo .


<s> int i386_pe_dllexport_name_p ( const char * symbol ) { return ( strncmp ( DLL_EXPORT_PREFIX , symbol , strlen ( DLL_EXPORT_PREFIX ) ) == 0 ) ; } </s>

Return nonzero if SYMBOL is marked as being dllexport 'd .


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
&&
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMIo
)
return
TargetInstrInfo
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
MCOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
RegState
::
Define
|
getDeadRegState
(
Reg0IsDead
)
)
.
addReg
(
Reg2
,
getKillRegState
(
Reg2IsKill
)
)
.
addReg
(
Reg1
,
getKillRegState
(
Reg1IsKill
)
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s> bool AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) { addPass ( createAArch64AdvSIMDScalar ( ) ) ; addPass ( & PeepholeOptimizerID ) ; } return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
bool
ARM64InstrInfo
::
isLdStPairSuppressed
(
const
MachineInstr
*
MI
)
const
{
assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
&&
"Too many target MO flags"
)
;
for
(
auto
*
MM
:
MI
->
memoperands
(
)
)
{
if
(
MM
->
getFlags
(
)
&
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
)
{
return
true
;
}
}
return
false
;
}
</s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s>
scalar_chain
::
scalar_chain
(
)
{
chain_id
=
++
max_id
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Created a new instruction chain #%d\n"
,
chain_id
)
;
bitmap_obstack_initialize
(
)
;
insns
=
BITMAP_ALLOC
(
)
;
defs
=
BITMAP_ALLOC
(
)
;
defs_conv
=
BITMAP_ALLOC
(
)
;
queue
=
;
}
</s>


<s> static bool sh_legitimize_address_displacement ( rtx * offset1 , rtx * offset2 , poly_int64 orig_offset , machine_mode mode ) { if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , orig_offset ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * offset1 = adj . offset_adjust ; * offset2 = adj . mov_disp ; return true ; } return false ; } </s>

Return true if DISP can be legitimized .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s> static rtx arm_expand_binop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of binop insns .


<s> rtx mt_function_arg ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named , int incoming_p ) { int slotno , regno ; rtx reg ; slotno = mt_function_arg_slotno ( cum , mode , type , named , incoming_p , & regno ) ; if ( slotno == - 1 ) reg = NULL_RTX ; else reg = gen_rtx_REG ( mode , regno ) ; return reg ; } </s>


<s> static void expand_small_movmem_or_setmem ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int size , rtx done_label , bool issetmem ) { rtx_code_label * label = ix86_expand_aligntest ( count , size , false ) ; machine_mode mode = int_mode_for_size ( size * BITS_PER_UNIT , 1 ) . else_blk ( ) ; rtx modesize ; int n ; if ( issetmem ) { if ( ! vec_value ) { if ( GET_MODE ( value ) == VOIDmode && size > 8 ) mode = Pmode ; else if ( GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( GET_MODE ( value ) ) ) mode = GET_MODE ( value ) ; } else mode = GET_MODE ( vec_value ) , value = vec_value ; } else { if ( size >= 32 ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= 16 ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , count , 1 ) ; destmem = offset_address ( destmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; if ( ! issetmem ) { srcmem = offset_address ( srcmem , count , 1 ) ; srcmem = offset_address ( srcmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; } for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; } </s>

Test if COUNT & SIZE is nonzero and if so , expand movme or setmem sequence that is valid for SIZE .. 2 * SIZE-1 bytes and jump to DONE_LABEL .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> BitVector MMIXRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , MMIX :: r254 ) ; markSuperRegs ( Reserved , MMIX :: r253 ) ; markSuperRegs ( Reserved , MMIX :: r252 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> void mips_va_start ( tree valist , rtx nextarg ) { if ( EABI_FLOAT_VARARGS_P ) { const CUMULATIVE_ARGS * cum ; tree f_ovfl , f_gtop , f_ftop , f_goff , f_foff ; tree ovfl , gtop , ftop , goff , foff ; tree t ; int gpr_save_area_size ; int fpr_save_area_size ; int fpr_offset ; cum = & current_function_args_info ; gpr_save_area_size = ( MAX_ARGS_IN_REGISTERS - cum -> num_gprs ) * UNITS_PER_WORD ; fpr_save_area_size = ( MAX_ARGS_IN_REGISTERS - cum -> num_fprs ) * UNITS_PER_FPREG ; f_ovfl = TYPE_FIELDS ( va_list_type_node ) ; f_gtop = TREE_CHAIN ( f_ovfl ) ; f_ftop = TREE_CHAIN ( f_gtop ) ; f_goff = TREE_CHAIN ( f_ftop ) ; f_foff = TREE_CHAIN ( f_goff ) ; ovfl = build ( COMPONENT_REF , TREE_TYPE ( f_ovfl ) , valist , f_ovfl , NULL_TREE ) ; gtop = build ( COMPONENT_REF , TREE_TYPE ( f_gtop ) , valist , f_gtop , NULL_TREE ) ; ftop = build ( COMPONENT_REF , TREE_TYPE ( f_ftop ) , valist , f_ftop , NULL_TREE ) ; goff = build ( COMPONENT_REF , TREE_TYPE ( f_goff ) , valist , f_goff , NULL_TREE ) ; foff = build ( COMPONENT_REF , TREE_TYPE ( f_foff ) , valist , f_foff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( ovfl ) , virtual_incoming_args_rtx ) ; if ( cum -> stack_words > 0 ) t = build ( PLUS_EXPR , TREE_TYPE ( ovfl ) , t , build_int_cst ( NULL_TREE , cum -> stack_words * UNITS_PER_WORD ) ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( ovfl ) , ovfl , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( gtop ) , virtual_incoming_args_rtx ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( gtop ) , gtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( ftop ) , virtual_incoming_args_rtx ) ; fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1 ; fpr_offset &= ~ ( UNITS_PER_FPVALUE - 1 ) ; if ( fpr_offset ) t = build ( PLUS_EXPR , TREE_TYPE ( ftop ) , t , build_int_cst ( NULL_TREE , - fpr_offset ) ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( ftop ) , ftop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( goff ) , goff , build_int_cst ( NULL_TREE , gpr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( foff ) , foff , build_int_cst ( NULL_TREE , fpr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } else { nextarg = plus_constant ( nextarg , - cfun -> machine -> varargs_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } } </s>


<s> void X86PassConfig :: addPreEmitPass2 ( ) { addPass ( createX86RetpolineThunksPass ( ) ) ; addPass ( createSandBoxingPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> rtx mmix_eh_return_stackadj_rtx ( ) { return gen_rtx_REG ( Pmode , MMIX_EH_RETURN_STACKADJ_REGNUM ) ; } </s>


<s> static bool mips_matching_cpu_name_p ( const char * canonical , const char * given ) { if ( mips_strict_matching_cpu_name_p ( canonical , given ) ) return true ; if ( TOLOWER ( * given ) == 'r' ) given ++ ; if ( ! ISDIGIT ( * given ) ) return false ; if ( TOLOWER ( canonical [ 0 ] ) == 'v' && TOLOWER ( canonical [ 1 ] ) == 'r' ) canonical += 2 ; else if ( TOLOWER ( canonical [ 0 ] ) == 'r' && TOLOWER ( canonical [ 1 ] ) == 'm' ) canonical += 2 ; else if ( TOLOWER ( canonical [ 0 ] ) == 'r' ) canonical += 1 ; return mips_strict_matching_cpu_name_p ( canonical , given ) ; } </s>

Return true if GIVEN matches CANONICAL , where GIVEN is a user-supplied CPU name . We 've traditionally allowed a lot of variation here . Note : this function is shared between GCC and GAS .


<s>
void
dump
(
)
{
errs
(
)
<<
"KudeyarISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
0
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

Kudeyar
"KudeyarISelAddressMode "
0
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s>
void
X86AvoidSFBPass
::
buildCopy
(
MachineInstr
*
LoadInst
,
unsigned
NLoadOpcode
,
int64_t
LoadDisp
,
MachineInstr
*
StoreInst
,
unsigned
NStoreOpcode
,
int64_t
StoreDisp
,
unsigned
Size
,
int64_t
LMMOffset
,
int64_t
SMMOffset
)
{
MachineOperand
&
LoadBase
=
getBaseOperand
(
LoadInst
)
;
MachineOperand
&
StoreBase
=
getBaseOperand
(
StoreInst
)
;
MachineBasicBlock
*
MBB
=
LoadInst
->
getParent
(
)
;
MachineMemOperand
*
LMMO
=
*
LoadInst
->
memoperands_begin
(
)
;
MachineMemOperand
*
SMMO
=
*
StoreInst
->
memoperands_begin
(
)
;
Register
Reg1
=
MRI
->
createVirtualRegister
(
TII
->
getRegClass
(
TII
->
get
(
NLoadOpcode
)
,
0
,
TRI
,
*
(
MBB
->
getParent
(
)
)
)
)
;
MachineInstr
*
NewLoad
=
BuildMI
(
*
MBB
,
LoadInst
,
LoadInst
->
getDebugLoc
(
)
,
TII
->
get
(
NLoadOpcode
)
,
Reg1
)
.
add
(
LoadBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
LoadDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
LMMO
,
LMMOffset
,
Size
)
)
;
if
(
LoadBase
.
isReg
(
)
)
getBaseOperand
(
NewLoad
)
.
setIsKill
(
false
)
;
LLVM_DEBUG
(
NewLoad
->
dump
(
)
)
;
MachineInstr
*
StInst
=
StoreInst
;
auto
PrevInstrIt
=
prev_nodbg
(
MachineBasicBlock
::
instr_iterator
(
StoreInst
)
,
MBB
->
instr_begin
(
)
)
;
if
(
PrevInstrIt
.
getNodePtr
(
)
==
LoadInst
)
StInst
=
LoadInst
;
MachineInstr
*
NewStore
=
BuildMI
(
*
MBB
,
StInst
,
StInst
->
getDebugLoc
(
)
,
TII
->
get
(
NStoreOpcode
)
)
.
add
(
StoreBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
StoreDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addReg
(
Reg1
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
SMMO
,
SMMOffset
,
Size
)
)
;
if
(
StoreBase
.
isReg
(
)
)
getBaseOperand
(
NewStore
)
.
setIsKill
(
false
)
;
MachineOperand
&
StoreSrcVReg
=
StoreInst
->
getOperand
(
X86
::
AddrNumOperands
)
;
assert
(
StoreSrcVReg
.
isReg
(
)
&&
"Expected virtual register"
)
;
NewStore
->
getOperand
(
X86
::
AddrNumOperands
)
.
setIsKill
(
StoreSrcVReg
.
isKill
(
)
)
;
LLVM_DEBUG
(
NewStore
->
dump
(
)
)
;
}
</s>


"OR1K PIC Global Base Reg Initialization"


<s> unsigned constant_generates_xxspltiw ( vec_const_128bit_type * vsx_const ) { if ( ! TARGET_SPLAT_WORD_CONSTANT || ! TARGET_PREFIXED || ! TARGET_VSX ) return 0 ; if ( ! vsx_const -> all_words_same ) return 0 ; if ( vsx_const -> all_bytes_same ) return 0 ; if ( vsx_const -> all_half_words_same ) { short sign_h_word = vsx_const -> half_words [ 0 ] ; if ( EASY_VECTOR_15 ( sign_h_word ) ) return 0 ; } int sign_word = vsx_const -> words [ 0 ] ; if ( EASY_VECTOR_15 ( sign_word ) ) return 0 ; return vsx_const -> words [ 0 ] ; } </s>

Determine if a vector constant can be loaded with XXSPLTIW . Return zero if the XXSPLTIW instruction can not be used . Otherwise return the immediate value to be used with the XXSPLTIW instruction .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static bool ix86_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_VECTOR : return false ; default : break ; } return ! ix86_legitimate_constant_p ( mode , x ) ; } </s>

Determine if it 's legal to put X into the constant pool . This is not possible for the address of thread-local symbols , which is checked above .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = arg . mode ; HOST_WIDE_INT bytes , words ; int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; bytes = arg . promoted_size_in_bytes ( ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( arg . type ) mode = type_natural_mode ( arg . type , NULL , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , arg . type , words , arg . named ) ; } else nregs = function_arg_advance_32 ( cum , mode , arg . type , bytes , words ) ; if ( ! nregs ) { if ( cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; } } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void VEDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { case VEISD :: LEGALAVL : ReplaceNode ( N , N -> getOperand ( 0 ) . getNode ( ) ) ; return ; case VEISD :: VEC_BROADCAST : { MVT SplatResTy = N -> getSimpleValueType ( 0 ) ; if ( SplatResTy . getVectorElementType ( ) != MVT :: i1 ) break ; auto BConst = dyn_cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ; if ( ! BConst ) break ; bool BCTrueMask = ( BConst -> getSExtValue ( ) != 0 ) ; if ( ! BCTrueMask ) break ; SDValue New ; if ( SplatResTy . getVectorNumElements ( ) == StandardVectorWidth ) { New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( N ) , VE :: VM0 , MVT :: v256i1 ) ; } else if ( SplatResTy . getVectorNumElements ( ) == PackedVectorWidth ) { New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( N ) , VE :: VMP0 , MVT :: v512i1 ) ; } else break ; ReplaceNode ( N , New . getNode ( ) ) ; return ; } case VEISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> unsigned ARMTargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return 4 ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ; } </s>

Get the maximum supported factor for interleaved memory accesses .


"  Skipping pass: no machine model present.\n"


<s> bool SystemZXPLINKFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = 0 , E = CSI . size ( ) ; I != E ; ++ I ) { Register Reg = CSI [ I ] . getReg ( ) ; if ( SystemZ :: FP64BitRegClass . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & SystemZ :: FP64BitRegClass , TRI ) ; if ( SystemZ :: VR128BitRegClass . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & SystemZ :: VR128BitRegClass , TRI ) ; } SystemZ :: GPRRegs RestoreGPRs = ZFI -> getRestoreGPRRegs ( ) ; if ( RestoreGPRs . LowGPR ) { assert ( isInt < 20 > ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ) ; if ( RestoreGPRs . LowGPR == RestoreGPRs . HighGPR ) BuildMI ( MBB , MBBI , DL , TII -> get ( SystemZ :: LG ) , RestoreGPRs . LowGPR ) . addReg ( Regs . getStackPointerRegister ( ) ) . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) . addReg ( 0 ) ; else { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( SystemZ :: LMG ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( Regs . getStackPointerRegister ( ) ) ; MIB . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ; for ( unsigned I = 0 , E = CSI . size ( ) ; I != E ; ++ I ) { Register Reg = CSI [ I ] . getReg ( ) ; if ( Reg > RestoreGPRs . LowGPR && Reg < RestoreGPRs . HighGPR ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool PPCPassConfig :: addILPOpts ( ) { if ( getPPCSubtarget ( ) . hasISEL ( ) ) { addPass ( & EarlyIfConverterID ) ; return true ; } return false ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Delay Slot Filler"
;
}
</s>


<s>
static
void
output_restore
(
rtx
pat
)
{
rtx
operands
[
3
]
;
if
(
!
pat
)
{
fputs
(
"\t restore\n"
,
asm_out_file
)
;
return
;
}
gcc_assert
(
GET_CODE
(
pat
)
==
SET
)
;
operands
[
0
]
=
SET_DEST
(
pat
)
;
pat
=
SET_SRC
(
pat
)
;
switch
(
GET_CODE
(
pat
)
)
{
case
PLUS
:
operands
[
1
]
=
XEXP
(
pat
,
0
)
;
operands
[
2
]
=
XEXP
(
pat
,
1
)
;
output_asm_insn
(
" restore %r1, %2, %Y0"
,
operands
)
;
break
;
case
LO_SUM
:
operands
[
1
]
=
XEXP
(
pat
,
0
)
;
operands
[
2
]
=
XEXP
(
pat
,
1
)
;
output_asm_insn
(
" restore %r1, %%lo(%a2), %Y0"
,
operands
)
;
break
;
case
ASHIFT
:
operands
[
1
]
=
XEXP
(
pat
,
0
)
;
gcc_assert
(
XEXP
(
pat
,
1
)
==
const1_rtx
)
;
output_asm_insn
(
" restore %r1, %r1, %Y0"
,
operands
)
;
break
;
default
:
operands
[
1
]
=
pat
;
output_asm_insn
(
" restore %%g0, %1, %Y0"
,
operands
)
;
break
;
}
}
</s>


<s> int aarch64_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ) { int type ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : type = DW_EH_PE_sdata4 ; break ; default : type = DW_EH_PE_sdata8 ; break ; } return ( global ? DW_EH_PE_indirect : 0 ) | DW_EH_PE_pcrel | type ; } </s>

Select a format to encode pointers in exception handling data .


<s> int SystemZHazardRecognizer :: groupingCost ( SUnit * SU ) const { const MCSchedClassDesc * SC = DAG -> getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return 0 ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return 3 - CurrGroupSize ; return - 1 ; } if ( SC -> EndGroup ) { unsigned resultingGroupSize = ( CurrGroupSize + getNumDecoderSlots ( SU ) ) ; if ( resultingGroupSize < 3 ) return ( 3 - resultingGroupSize ) ; return - 1 ; } return 0 ; } </s>

Return the cost of decoder grouping for SU .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineModuleInfoWrapperPass > ( ) ; AU . addPreserved < MachineModuleInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
TargetIRAnalysis
MipsTargetMachine
::
getTargetIRAnalysis
(
)
{
return
TargetIRAnalysis
(
[
this
]
(
const
Function
&
F
)
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
BasicTTIImpl
(
this
,
F
)
)
;
}
)
;
}
</s>

Get a TargetIRAnalysis appropriate for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"


<s> static int pa_reloc_rw_mask ( void ) { if ( flag_pic || ( TARGET_SOM && ! TARGET_HPUX_11 ) ) return 3 ; return TARGET_SOM ? 2 : 0 ; } </s>


<s> bool PPCInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) != 3 ) return false ; if ( ! LdSt . getOperand ( 1 ) . isImm ( ) || ! LdSt . getOperand ( 2 ) . isReg ( ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; Offset = LdSt . getOperand ( 1 ) . getImm ( ) ; BaseReg = & LdSt . getOperand ( 2 ) ; return true ; } </s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> rtx rs6000_expand_ldst_mask ( rtx target , tree arg0 ) { int icode2 = BYTES_BIG_ENDIAN ? ( int ) CODE_FOR_altivec_lvsr_direct : ( int ) CODE_FOR_altivec_lvsl_direct ; machine_mode tmode = insn_data [ icode2 ] . operand [ 0 ] . mode ; machine_mode mode = insn_data [ icode2 ] . operand [ 1 ] . mode ; gcc_assert ( TARGET_ALTIVEC ) ; gcc_assert ( POINTER_TYPE_P ( TREE_TYPE ( arg0 ) ) ) ; rtx op = expand_expr ( arg0 , NULL_RTX , Pmode , EXPAND_NORMAL ) ; rtx addr = memory_address ( mode , op ) ; op = gen_reg_rtx ( GET_MODE ( addr ) ) ; emit_insn ( gen_rtx_SET ( op , gen_rtx_NEG ( GET_MODE ( addr ) , addr ) ) ) ; op = gen_rtx_MEM ( mode , op ) ; if ( target == 0 || GET_MODE ( target ) != tmode || ! insn_data [ icode2 ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rtx pat = GEN_FCN ( icode2 ) ( target , op ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> static bool mips_expand_vpc_loongson_pshufh ( struct expand_vec_perm_d * d ) { unsigned i , mask ; rtx rmask ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( d -> vmode != V4HImode ) return false ; if ( d -> testing_p ) return true ; for ( i = mask = 0 ; i < 4 ; i ++ ) mask |= ( d -> perm [ i ] & 3 ) << ( i * 2 ) ; rmask = force_reg ( SImode , GEN_INT ( mask ) ) ; if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ 4 ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = 0 ; i < 4 ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & 4 ? constm1_rtx : const0_rtx ) ; merge = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmerge ) ) ; merge = force_reg ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , merge , t1 ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_NOT ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , x , t0 ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; } return true ; } </s>

Recognize patterns for the Loongson PSHUFH instruction .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
4
*
8
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const { if ( MInfo . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: B ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } if ( MInfo . CallConstructionID == MachineOutlinerNoLRSave ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR , RegState :: Define ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return It ; } </s>

Insert a call to an outlined function into the program .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
&
STI
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
.
begin
(
)
,
MLI
.
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>


<s> static int sign_bit_position ( const rtx op ) { const int sz = GET_MODE_SIZE ( GET_MODE ( op ) ) ; return sz * 8 - 1 ; } </s>

Return the sign bit position for given OP 's mode .


<s> int shl_and_length ( rtx insn ) { rtx set_src , left_rtx , mask_rtx ; int attributes [ 3 ] ; set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; left_rtx = XEXP ( XEXP ( set_src , 0 ) , 1 ) ; mask_rtx = XEXP ( set_src , 1 ) ; shl_and_kind ( left_rtx , mask_rtx , attributes ) ; return attributes [ 1 ] ; } </s>

This is used in length attributes of the unnamed instructions corresponding to shl_and_kind return values of 1 and 2 .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"%qE attribute have effect only on public objects"

Handle a `` nodirect_extern_access '' attribute ; arguments as in struct attribute_spec.handler .


"Slot for FP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"LowerFormalArguments Unhandled argument type: "

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool ARM64TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( Imm . isPosZero ( ) && ( VT == MVT :: f64 || VT == MVT :: f32 ) ) return true ; if ( VT == MVT :: f64 ) return ARM64_AM :: getFP64Imm ( Imm ) != - 1 ; else if ( VT == MVT :: f32 ) return ARM64_AM :: getFP32Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> bool CJGAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool SICRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static void aarch64_parse_tune_string ( const char * tune_string , struct tune_params * tune ) { tune -> extra_tuning_flags = aarch64_parse_boolean_options ( tune_string , aarch64_tuning_flags , tune -> extra_tuning_flags , "tune=" ) ; } </s>

Support for overriding other tuning flags .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_condbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_blx"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
bool
HasAVX512
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX512
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
default
:
break
;
}
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] [ 0 ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createIndirectBrExpandPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! DefMI . getParent ( ) ) return Latency ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; Register Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( Register :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI . isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getCPUDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> TargetIRAnalysis ARMBaseTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( ARMTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( TRI -> hasBasePointer ( MF ) ) { Register BasePtr = TRI -> getBaseRegister ( ) ; if ( STI . isTarget64BitILP32 ( ) ) BasePtr = getX86SubSuperRegister ( BasePtr , 64 ) ; SavedRegs . set ( BasePtr ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: VAARG : return lowerVAARG ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: EH_DWARF_CFA : return lowerEH_DWARF_CFA ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::VAARG ISD::FCOPYSIGN ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::EH_DWARF_CFA ISD::FP_TO_SINT


"IA64 (Itanium) DAG->DAG Instruction Selector"

getPassName - Return a nice clean name for a pass .


" - nope, %%lo(sym)[reg] not splittable\n"

Be careful not to use macros that need to be compiled one way for strict , and another way for not-strict , like REG_OK_FOR_BASE_P .


<s> unsigned X86TTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( Vector && ! ST -> hasSSE1 ( ) ) return 0 ; if ( ST -> is64Bit ( ) ) { if ( Vector && ST -> hasAVX512 ( ) ) return 32 ; return 16 ; } return 8 ; } </s>


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
Op
.
getExpr
(
)
->
print
(
O
,
&
MAI
)
;
}
}
}
</s>


<s> bool LanaiInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TrueBlock , MachineBasicBlock * & FalseBlock , SmallVectorImpl < MachineOperand > & Condition , bool AllowModify ) const { MachineBasicBlock :: iterator Instruction = MBB . end ( ) ; while ( Instruction != MBB . begin ( ) ) { -- Instruction ; if ( Instruction -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * Instruction ) ) break ; if ( ! Instruction -> isBranch ( ) ) return true ; if ( Instruction -> getOpcode ( ) == Lanai :: BT ) { if ( ! AllowModify ) { TrueBlock = Instruction -> getOperand ( 0 ) . getMBB ( ) ; continue ; } while ( std :: next ( Instruction ) != MBB . end ( ) ) { std :: next ( Instruction ) -> eraseFromParent ( ) ; } Condition . clear ( ) ; FalseBlock = nullptr ; if ( MBB . isLayoutSuccessor ( Instruction -> getOperand ( 0 ) . getMBB ( ) ) ) { TrueBlock = nullptr ; Instruction -> eraseFromParent ( ) ; Instruction = MBB . end ( ) ; continue ; } TrueBlock = Instruction -> getOperand ( 0 ) . getMBB ( ) ; continue ; } unsigned Opcode = Instruction -> getOpcode ( ) ; if ( Opcode != Lanai :: BRCC ) return true ; if ( Condition . empty ( ) ) { LPCC :: CondCode BranchCond = static_cast < LPCC :: CondCode > ( Instruction -> getOperand ( 1 ) . getImm ( ) ) ; FalseBlock = TrueBlock ; TrueBlock = Instruction -> getOperand ( 0 ) . getMBB ( ) ; Condition . push_back ( MachineOperand :: CreateImm ( BranchCond ) ) ; continue ; } return true ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> int fp_high_losum_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { long i ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , i ) ; return ! SPARC_SIMM13_P ( i ) && ! SPARC_SETHI_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a high/losum instruction sequence .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
val
=
;
char
buf
[
128
]
;
FILE
*
f
=
;
bool
arch
;
const
struct
vendor_cpu
*
cpu_table
=
;
char
*
fcpu_info
=
;
if
(
argc
<
1
)
goto
not_found
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"cpu"
)
!=
0
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
goto
not_found
;
fcpu_info
=
getenv
(
"GCC_CPUINFO"
)
;
if
(
fcpu_info
)
f
=
fopen
(
fcpu_info
,
"r"
)
;
else
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
not_found
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
{
if
(
startswith
(
buf
,
"CPU implementer"
)
)
{
int
i
;
for
(
i
=
0
;
vendors_table
[
i
]
.
vendor_no
!=
;
i
++
)
if
(
strstr
(
buf
,
vendors_table
[
i
]
.
vendor_no
)
!=
)
{
cpu_table
=
vendors_table
[
i
]
.
vendor_parts
;
break
;
}
}
if
(
startswith
(
buf
,
"CPU part"
)
)
{
int
i
;
if
(
cpu_table
==
)
goto
not_found
;
for
(
i
=
0
;
cpu_table
[
i
]
.
part_no
!=
;
i
++
)
if
(
strstr
(
buf
,
cpu_table
[
i
]
.
part_no
)
!=
)
{
val
=
arch
cpu_table
[
i
]
.
arch_name
:
cpu_table
[
i
]
.
cpu_name
;
break
;
}
break
;
}
}
if
(
val
)
{
fclose
(
f
)
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
val
,
)
;
}
not_found
:
{
unsigned
int
i
;
unsigned
int
opt
;
const
char
*
search
[
]
=
{
,
"arch"
}
;
if
(
f
)
fclose
(
f
)
;
search
[
0
]
=
argv
[
0
]
;
for
(
opt
=
0
;
opt
<
ARRAY_SIZE
(
search
)
;
opt
++
)
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
configure_default_options
)
;
i
++
)
if
(
strcmp
(
configure_default_options
[
i
]
.
name
,
search
[
opt
]
)
==
0
)
return
concat
(
"-m"
,
search
[
opt
]
,
"="
,
configure_default_options
[
i
]
.
value
,
)
;
return
;
}
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> static bool aarch64_sve_cmp_operand_p ( rtx_code op_code , rtx x ) { if ( register_operand ( x , VOIDmode ) ) return true ; switch ( op_code ) { case LTU : case LEU : case GEU : case GTU : return aarch64_sve_cmp_immediate_p ( x , false ) ; case LT : case LE : case GE : case GT : case NE : case EQ : return aarch64_sve_cmp_immediate_p ( x , true ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if X is a valid second operand for the SVE instruction that implements integer comparison OP_CODE .


<s> bool AArch64RegisterInfo :: regNeedsCFI ( unsigned Reg , unsigned & RegToUseForCFI ) const { if ( AArch64 :: PPRRegClass . contains ( Reg ) ) return false ; if ( AArch64 :: ZPRRegClass . contains ( Reg ) ) { RegToUseForCFI = getSubReg ( Reg , AArch64 :: dsub ) ; for ( int I = 0 ; CSR_AArch64_AAPCS_SaveList [ I ] ; ++ I ) { if ( CSR_AArch64_AAPCS_SaveList [ I ] == RegToUseForCFI ) return true ; } return false ; } RegToUseForCFI = Reg ; return true ; } </s>

Return whether the register needs a CFI entry .


<s> static tree sparc_handle_vis_mul8x16 ( int fncode , tree inner_type , tree elts0 , tree elts1 ) { tree n_elts = NULL_TREE ; int scale ; switch ( fncode ) { case CODE_FOR_fmul8x16_vis : for ( ; elts0 && elts1 ; elts0 = TREE_CHAIN ( elts0 ) , elts1 = TREE_CHAIN ( elts1 ) ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( TREE_VALUE ( elts0 ) ) , TREE_INT_CST_LOW ( TREE_VALUE ( elts1 ) ) ) ; n_elts = tree_cons ( NULL_TREE , build_int_cst ( inner_type , val ) , n_elts ) ; } break ; case CODE_FOR_fmul8x16au_vis : scale = TREE_INT_CST_LOW ( TREE_VALUE ( elts1 ) ) ; for ( ; elts0 ; elts0 = TREE_CHAIN ( elts0 ) ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( TREE_VALUE ( elts0 ) ) , scale ) ; n_elts = tree_cons ( NULL_TREE , build_int_cst ( inner_type , val ) , n_elts ) ; } break ; case CODE_FOR_fmul8x16al_vis : scale = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_CHAIN ( elts1 ) ) ) ; for ( ; elts0 ; elts0 = TREE_CHAIN ( elts0 ) ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( TREE_VALUE ( elts0 ) ) , scale ) ; n_elts = tree_cons ( NULL_TREE , build_int_cst ( inner_type , val ) , n_elts ) ; } break ; default : gcc_unreachable ( ) ; } return nreverse ( n_elts ) ; } </s>

Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified by FNCODE . All of the elements in ELTS0 and ELTS1 lists must be integer constants . A tree list with the results of the multiplications is returned , and each element in the list is of INNER_TYPE .


<s> bool rs6000_builtin_is_supported ( enum rs6000_gen_builtins fncode ) { switch ( rs6000_builtin_info [ ( size_t ) fncode ] . enable ) { case ENB_ALWAYS : return true ; case ENB_P5 : return TARGET_POPCNTB ; case ENB_P6 : return TARGET_CMPB ; case ENB_P6_64 : return TARGET_CMPB && TARGET_POWERPC64 ; case ENB_P7 : return TARGET_POPCNTD ; case ENB_P7_64 : return TARGET_POPCNTD && TARGET_POWERPC64 ; case ENB_P8 : return TARGET_DIRECT_MOVE ; case ENB_P8V : return TARGET_P8_VECTOR ; case ENB_P9 : return TARGET_MODULO ; case ENB_P9_64 : return TARGET_MODULO && TARGET_POWERPC64 ; case ENB_P9V : return TARGET_P9_VECTOR ; case ENB_P10 : return TARGET_POWER10 ; case ENB_P10_64 : return TARGET_POWER10 && TARGET_POWERPC64 ; case ENB_ALTIVEC : return TARGET_ALTIVEC ; case ENB_VSX : return TARGET_VSX ; case ENB_CELL : return TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL ; case ENB_IEEE128_HW : return TARGET_FLOAT128_HW ; case ENB_DFP : return TARGET_DFP ; case ENB_CRYPTO : return TARGET_CRYPTO ; case ENB_HTM : return TARGET_HTM ; case ENB_MMA : return TARGET_MMA ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; } </s>

Check whether a builtin function is supported in this target configuration .


<s> static int arm_compute_static_chain_stack_bytes ( void ) { if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM && IS_NESTED ( arm_current_func_type ( ) ) && arm_r3_live_at_start_p ( ) && crtl -> args . pretend_args_size == 0 ) return 4 ; return 0 ; } </s>

Compute the number of bytes used to store the static chain register on the stack , above the stack frame . We need to know this accurately to get the alignment of the rest of the stack frame correct .


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = 0 ; if ( GET_CODE ( addr ) == CONST ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s> static bool arm_promote_prototypes ( tree t ATTRIBUTE_UNUSED ) { return ! TARGET_AAPCS_BASED ; } </s>

We ca n't rely on the caller doing the proper promotion when using APCS or ATPCS .


<s> void LEGFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = LEG :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: ADDrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>


<s>
void
PPCAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLWINM
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
MB
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
bool
useSubstituteMnemonic
=
false
;
if
(
SH
<=
31
&&
MB
==
0
&&
ME
==
(
31
SH
)
)
{
O
<<
"\tslwi "
;
useSubstituteMnemonic
=
true
;
}
if
(
SH
<=
31
&&
MB
==
(
32
SH
)
&&
ME
==
31
)
{
O
<<
"\tsrwi "
;
useSubstituteMnemonic
=
true
;
SH
=
32
SH
;
}
if
(
useSubstituteMnemonic
)
{
printOperand
(
MI
,
0
)
;
O
<<
", "
;
printOperand
(
MI
,
1
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
OutStreamer
.
AddBlankLine
(
)
;
return
;
}
}
if
(
(
MI
->
getOpcode
(
)
==
PPC
::
OR
||
MI
->
getOpcode
(
)
==
PPC
::
OR8
)
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
O
<<
"\tmr "
;
printOperand
(
MI
,
0
)
;
O
<<
", "
;
printOperand
(
MI
,
1
)
;
OutStreamer
.
AddBlankLine
(
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLDICR
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
63
SH
==
ME
)
{
O
<<
"\tsldi "
;
printOperand
(
MI
,
0
)
;
O
<<
", "
;
printOperand
(
MI
,
1
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
OutStreamer
.
AddBlankLine
(
)
;
return
;
}
}
printInstruction
(
MI
)
;
OutStreamer
.
AddBlankLine
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void MipsELFStreamer :: emitLabel ( MCSymbol * Symbol , SMLoc Loc ) { MCELFStreamer :: emitLabel ( Symbol ) ; Labels . push_back ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s> void arm_emit_speculation_barrier_function ( ) { emit_library_call ( speculation_barrier_libfunc , LCT_NORMAL , VOIDmode ) ; } </s>

Emit a speculation barrier on target architectures that do not have DSB/ISB directly . Such systems probably do n't need a barrier themselves , but if the code is ever run on a later architecture , it might become a problem .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
unsigned
getReg
(
)
const
override
{
if
(
Kind
==
k_RegisterIndex
&&
RegIdx
.
Index
==
0
&&
RegIdx
.
Kind
&
RegKind_GPR
)
return
getGPR32Reg
(
)
;
assert
(
Kind
==
k_PhysRegister
&&
"Invalid access!"
)
;
return
PhysReg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg 32 32 ISD::InputArg 32 PPC PPC PPC


<s>
static
void
arm_setup_incoming_varargs
(
cumulative_args_t
pcum_v
,
machine_mode
mode
,
tree
type
,
int
*
pretend_size
,
int
second_time
ATTRIBUTE_UNUSED
)
{
CUMULATIVE_ARGS
*
pcum
=
get_cumulative_args
(
pcum_v
)
;
int
nregs
;
cfun
->
machine
->
uses_anonymous_args
=
1
;
if
(
pcum
->
pcs_variant
<=
ARM_PCS_AAPCS_LOCAL
)
{
nregs
=
pcum
->
aapcs_ncrn
;
if
(
nregs
&
1
)
{
int
res
=
arm_needs_doubleword_align
(
mode
,
type
)
;
if
(
res
<
0
&&
warn_psabi
)
inform
(
input_location
,
"parameter passing for argument of "
"type %qT changed in GCC 7.1"
,
type
)
;
else
if
(
res
>
0
)
nregs
++
;
}
}
else
nregs
=
pcum
->
nregs
;
if
(
nregs
<
NUM_ARG_REGS
)
*
pretend_size
=
(
NUM_ARG_REGS
nregs
)
*
UNITS_PER_WORD
;
}
</s>

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> bool DCPU16InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> SDValue SICTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

SIC SIC ISD::BRCOND ISD::GlobalAddress ISD::BlockAddress ISD::JumpTable ISD::SELECT


<s> void OR1KMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned CurByte = 0 ; ++ MCNumEmitted ; unsigned Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitBEConstant ( Value , 4 , CurByte , OS ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> int iq2000_reg_mode_ok_for_base_p ( rtx reg , machine_mode mode ATTRIBUTE_UNUSED , int strict ) { return ( strict ? REGNO_MODE_OK_FOR_BASE_P ( REGNO ( reg ) , mode ) : GP_REG_OR_PSEUDO_NONSTRICT_P ( REGNO ( reg ) , mode ) ) ; } </s>

Return nonzero if REG is valid for MODE .


<s> void LanaiInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annotation , const MCSubtargetInfo & ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static void replace_swapped_aligned_store ( swap_web_entry * insn_entry , rtx_insn * store_insn ) { unsigned uid = INSN_UID ( store_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && insn_entry [ uid ] . is_store ) ; rtx body = PATTERN ( store_insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , 0 ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , 0 ) ; gcc_assert ( REG_P ( dest_address ) || rs6000_sum_of_two_registers_p ( dest_address ) ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( store_insn ) ; df_ref use ; rtx_insn * swap_insn = NULL ; unsigned uid2 = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= 128 ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_DEST ( new_body ) ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( store_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( store_insn ) ; remove_insn ( store_insn ) ; store_insn -> set_deleted ( ) ; uid2 = INSN_UID ( swap_insn ) ; mark_swaps_for_removal ( insn_entry , uid2 ) ; replace_swap_with_copy ( insn_entry , uid2 ) ; } </s>

Given that STORE_INSN represents an aligned store-with-swap of a swapped value , replace the store with an aligned store ( without swap ) and replace the swap with a copy insn .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < ARMSubtarget > ( ) ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> bool supportSwiftError ( ) const override { return true ; } </s>

Return true if the target supports swifterror attribute .


<s> static ARMOperand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { ARMOperand * Op = new ARMOperand ( Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void FISCMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void nds32_spilt_doubleword ( rtx * operands , bool load_p ) { int reg = load_p ? 0 : 1 ; int mem = load_p ? 1 : 0 ; rtx reg_rtx = load_p ? operands [ 0 ] : operands [ 1 ] ; rtx mem_rtx = load_p ? operands [ 1 ] : operands [ 0 ] ; rtx low_part [ 2 ] , high_part [ 2 ] ; rtx sub_mem = XEXP ( mem_rtx , 0 ) ; low_part [ reg ] = simplify_gen_subreg ( SImode , reg_rtx , GET_MODE ( reg_rtx ) , 0 ) ; high_part [ reg ] = simplify_gen_subreg ( SImode , reg_rtx , GET_MODE ( reg_rtx ) , 4 ) ; if ( GET_CODE ( sub_mem ) == POST_DEC ) { sub_mem = XEXP ( sub_mem , 0 ) ; low_part [ mem ] = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , sub_mem , gen_rtx_PLUS ( Pmode , sub_mem , GEN_INT ( 4 ) ) ) ) ; high_part [ mem ] = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , sub_mem , gen_rtx_PLUS ( Pmode , sub_mem , GEN_INT ( - 12 ) ) ) ) ; } else if ( GET_CODE ( sub_mem ) == POST_MODIFY ) { rtx post_mem = XEXP ( sub_mem , 0 ) ; rtx plus_op = XEXP ( sub_mem , 1 ) ; rtx post_val = XEXP ( plus_op , 1 ) ; low_part [ mem ] = gen_frame_mem ( SImode , gen_rtx_POST_MODIFY ( Pmode , post_mem , gen_rtx_PLUS ( Pmode , post_mem , post_val ) ) ) ; high_part [ mem ] = gen_frame_mem ( SImode , plus_constant ( Pmode , post_mem , 4 ) ) ; } else { low_part [ mem ] = adjust_address ( mem_rtx , SImode , 0 ) ; high_part [ mem ] = adjust_address ( mem_rtx , SImode , 4 ) ; } if ( ( load_p && reg_overlap_mentioned_p ( low_part [ 0 ] , high_part [ 1 ] ) ) || GET_CODE ( sub_mem ) == POST_MODIFY ) { operands [ 2 ] = high_part [ 0 ] ; operands [ 3 ] = high_part [ 1 ] ; operands [ 4 ] = low_part [ 0 ] ; operands [ 5 ] = low_part [ 1 ] ; } else { operands [ 2 ] = low_part [ 0 ] ; operands [ 3 ] = low_part [ 1 ] ; operands [ 4 ] = high_part [ 0 ] ; operands [ 5 ] = high_part [ 1 ] ; } } </s>

Spilt a doubleword instrucion to two single word instructions .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; ARMFunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } else { if ( ( MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> bool legitimate_constant_pool_address_p ( const_rtx x , machine_mode mode , bool strict ) { return ( toc_relative_expr_p ( x , strict ) && ( TARGET_CMODEL != CMODEL_MEDIUM || constant_pool_expr_p ( XVECEXP ( tocrel_base , 0 , 0 ) ) || mode == QImode || offsettable_ok_by_alignment ( XVECEXP ( tocrel_base , 0 , 0 ) , INTVAL ( tocrel_offset ) , mode ) ) ) ; } </s>

Return true if X is a constant pool address , and also for cmodel=medium if X is a toc-relative address known to be offsettable within MODE .


<s> static void mips_74k_agen_init ( rtx_insn * insn ) { if ( ! insn || CALL_P ( insn ) || JUMP_P ( insn ) ) mips_last_74k_agen_insn = TYPE_UNKNOWN ; else { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_LOAD || type == TYPE_STORE ) mips_last_74k_agen_insn = type ; } } </s>

Initialize mips_last_74k_agen_insn from INSN . A null argument resets to TYPE_UNKNOWN state .


<s> void ia64_split_tmode_move ( rtx operands [ ] ) { rtx in [ 2 ] , out [ 2 ] , insn ; rtx fixup [ 2 ] ; bool dead = false ; bool reversed = false ; if ( GET_CODE ( operands [ 1 ] ) == MEM && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) ) { rtx base = XEXP ( operands [ 1 ] , 0 ) ; while ( GET_CODE ( base ) != REG ) base = XEXP ( base , 0 ) ; if ( REGNO ( base ) == REGNO ( operands [ 0 ] ) ) reversed = true ; if ( refers_to_regno_p ( REGNO ( operands [ 0 ] ) , REGNO ( operands [ 0 ] ) + 2 , base , 0 ) ) dead = true ; } if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == REG && REGNO ( operands [ 0 ] ) == REGNO ( operands [ 1 ] ) + 1 ) reversed = true ; fixup [ 0 ] = ia64_split_tmode ( in , operands [ 1 ] , reversed , dead ) ; fixup [ 1 ] = ia64_split_tmode ( out , operands [ 0 ] , reversed , dead ) ; if ( GET_CODE ( EXP ) == MEM \ && ( GET_CODE ( XEXP ( EXP , 0 ) ) == POST_MODIFY \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_INC \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_DEC ) ) \ add_reg_note ( insn , REG_INC , XEXP ( XEXP ( EXP , 0 ) , 0 ) ) insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ 0 ] , in [ 0 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 0 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 0 ] ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ 1 ] , in [ 1 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 1 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 1 ] ) ; if ( fixup [ 0 ] ) emit_insn ( fixup [ 0 ] ) ; if ( fixup [ 1 ] ) emit_insn ( fixup [ 1 ] ) ; } </s>

Split a TImode or TFmode move instruction after reload . This is used by * movtf_internal and * movti_internal .


<s> static rtx pa_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode valmode ; if ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || TREE_CODE ( valtype ) == VECTOR_TYPE ) { HOST_WIDE_INT valsize = int_size_in_bytes ( valtype ) ; if ( ( valsize & ( UNITS_PER_WORD - 1 ) ) == 0 ) return gen_rtx_REG ( TYPE_MODE ( valtype ) , 28 ) ; if ( TARGET_64BIT ) { rtx loc [ 2 ] ; int i , offset = 0 ; int ub = valsize <= UNITS_PER_WORD ? 1 : 2 ; for ( i = 0 ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 + i ) , GEN_INT ( offset ) ) ; offset += 8 ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( valsize > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( 1 , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( TYPE_MODE ( valtype ) ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ; else valmode = TYPE_MODE ( valtype ) ; if ( TREE_CODE ( valtype ) == REAL_TYPE && ! AGGREGATE_TYPE_P ( valtype ) && TYPE_MODE ( valtype ) != TFmode && ! TARGET_SOFT_FLOAT ) return gen_rtx_REG ( valmode , 32 ) ; return gen_rtx_REG ( valmode , 28 ) ; } </s>

On the HP-PA the value is found in register ( s ) 28 ( -29 ) , unless the mode is SF or DF . Then the value is returned in fr4 ( 32 ) . This must perform the same promotions as PROMOTE_MODE , else promoting return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly . Small structures must be returned in a PARALLEL on PA64 in order to match the HP Compiler ABI .


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return AArch64 :: X0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> void func_fma_steering :: update_balance ( int parity ) { this -> m_fpu_balance = parity ? this -> m_fpu_balance + 1 : this -> m_fpu_balance - 1 ; } </s>

Update the current balance considering a node with the given PARITY .


<s>
static
void
aarch64_emit_probe_stack_range
(
HOST_WIDE_INT
first
,
poly_int64
poly_size
)
{
HOST_WIDE_INT
size
;
if
(
!
poly_size
.
is_constant
(
&
size
)
)
{
sorry
(
"stack probes for SVE frames"
)
;
return
;
}
rtx
reg1
=
gen_rtx_REG
(
Pmode
,
PROBE_STACK_FIRST_REGNUM
)
;
gcc_assert
(
(
first
%
ARITH_FACTOR
)
==
0
)
;
if
(
size
<=
PROBE_INTERVAL
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
size
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
(
first
+
base
)
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
base
size
)
)
;
}
else
if
(
size
<=
4
*
PROBE_INTERVAL
)
{
HOST_WIDE_INT
i
,
rem
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
(
first
+
PROBE_INTERVAL
)
)
)
;
emit_stack_probe
(
reg1
)
;
for
(
i
=
2
*
PROBE_INTERVAL
;
i
<
size
;
i
+=
PROBE_INTERVAL
)
{
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
reg1
,
PROBE_INTERVAL
)
)
;
emit_stack_probe
(
reg1
)
;
}
rem
=
size
(
i
PROBE_INTERVAL
)
;
if
(
rem
>
256
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
rem
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
reg1
,
base
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
base
rem
)
)
;
}
else
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
rem
)
)
;
}
else
{
rtx
reg2
=
gen_rtx_REG
(
Pmode
,
PROBE_STACK_SECOND_REGNUM
)
;
HOST_WIDE_INT
rounded_size
=
size
&
PROBE_INTERVAL
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
first
)
)
;
HOST_WIDE_INT
adjustment
=
(
first
+
rounded_size
)
;
if
(
!
aarch64_uimm12_shift
(
adjustment
)
)
{
aarch64_internal_mov_immediate
(
reg2
,
GEN_INT
(
adjustment
)
,
true
,
Pmode
)
;
emit_set_insn
(
reg2
,
gen_rtx_PLUS
(
Pmode
,
stack_pointer_rtx
,
reg2
)
)
;
}
else
emit_set_insn
(
reg2
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
adjustment
)
)
;
emit_insn
(
gen_probe_stack_range
(
reg1
,
reg1
,
reg2
)
)
;
if
(
size
!=
rounded_size
)
{
HOST_WIDE_INT
rem
=
size
rounded_size
;
if
(
rem
>
256
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
rem
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg2
,
plus_constant
(
Pmode
,
reg2
,
base
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg2
,
base
rem
)
)
;
}
else
emit_stack_probe
(
plus_constant
(
Pmode
,
reg2
,
rem
)
)
;
}
}
emit_insn
(
gen_blockage
(
)
)
;
}
</s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getIndirectSymViaGOTPCRel ( const GlobalValue * GV , const MCSymbol * Sym , const MCValue & MV , int64_t Offset , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { unsigned FinalOff = Offset + MV . getConstant ( ) + 4 ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Off = MCConstantExpr :: create ( FinalOff , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Off , getContext ( ) ) ; } </s>

Get the target specific PC relative GOT entry relocation .


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility guarantee"

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> FastISel * X86TargetLowering :: createFastISel ( MachineFunction & mf , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < const Instruction * , 8 > & cil ) { return X86 :: createFastISel ( mf , vm , bm , am , cil ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static inline int addsubcosts ( rtx x ) { if ( GET_MODE ( x ) == SImode ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( op0 ) == AND && XEXP ( op0 , 1 ) == const1_rtx && ( GET_CODE ( op1 ) == PLUS || ( GET_CODE ( op1 ) == MULT && XEXP ( op1 , 1 ) == const2_rtx ) ) ) return 1 ; if ( GET_CODE ( op0 ) == MULT && XEXP ( op0 , 1 ) == const2_rtx && GET_CODE ( op1 ) == LSHIFTRT && CONST_INT_P ( XEXP ( op1 , 1 ) ) && INTVAL ( XEXP ( op1 , 1 ) ) == 31 ) return 1 ; } if ( treg_set_expr ( op1 , SImode ) ) return 1 ; if ( treg_set_expr ( op0 , SImode ) ) return 1 ; } const int cost_scale = GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( REG_P ( XEXP ( x , 1 ) ) || GET_CODE ( XEXP ( x , 1 ) ) == SUBREG ) return 1 * cost_scale ; if ( CONST_INT_P ( XEXP ( x , 1 ) ) && CONST_OK_FOR_ADD ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 1 * cost_scale ; return 3 * cost_scale ; } </s>

Return the cost of an addition or a subtraction .


<s> static bool rs6000_const_not_ok_for_debug_p ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) { rtx c = get_pool_constant ( x ) ; machine_mode cmode = get_pool_mode ( x ) ; if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( c , cmode ) ) return true ; } return false ; } </s>

Return true if X should n't be emitted into the debug info . The linker does n't like .toc section references from .debug_ * sections , so reject .toc section symbols .


<s> virtual const TOYRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool LoongArchAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( Count % 4 != 0 ) return false ; for ( ; Count >= 4 ; Count -= 4 ) support :: endian :: write < uint32_t > ( OS , 0x03400000 , support :: little ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool supported_simd_type ( tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) || INTEGRAL_TYPE_P ( t ) || POINTER_TYPE_P ( t ) ) { HOST_WIDE_INT s = tree_to_shwi ( TYPE_SIZE_UNIT ( t ) ) ; return s == 1 || s == 2 || s == 4 || s == 8 ; } return false ; } </s>

Return true for types that could be supported as SIMD return or argument types .