<s> static bool rs6000_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , to ) ; unsigned from_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , from ) ; bool to_float128_vector_p = FLOAT128_VECTOR_P ( to ) ; bool from_float128_vector_p = FLOAT128_VECTOR_P ( from ) ; if ( to_float128_vector_p && from_float128_vector_p ) return true ; else if ( to_float128_vector_p || from_float128_vector_p ) return false ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return false ; if ( from_size < 8 || to_size < 8 ) return false ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return false ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return false ; return true ; } else return true ; } if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs ( FIRST_FPR_REGNO , to ) > num_regs || hard_regno_nregs ( FIRST_FPR_REGNO , from ) > num_regs ) return false ; return ( from_size == 8 || from_size == 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return false ; return true ; } </s>


<s> tree aarch64_general_builtin_rsqrt ( unsigned int fn ) { if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2df ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2DF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2SF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V4SF ] ; return NULL_TREE ; } </s>

Return builtin for reciprocal square root .


<s> int iq2000_can_use_return_insn ( void ) { if ( ! reload_completed ) return 0 ; if ( df_regs_ever_live_p ( 31 ) || profile_flag ) return 0 ; if ( cfun -> machine -> initialized ) return cfun -> machine -> total_size == 0 ; return compute_frame_size ( get_frame_size ( ) ) == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> bool ARM64PassConfig :: addPreEmitPass ( ) { addPass ( createARM64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < ARM64Subtarget > ( ) . isTargetMachO ( ) ) addPass ( createARM64CollectLOHPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return LowerMMIXMachineOperandToMCOperand ( MO , MCOp , * this ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


"cannot combine a base of type %qT with"

Require arguments ARGNO and ARGNO + 1 to form an ADR-style address , i.e . one with a vector of base addresses and a vector of displacements . The overloaded function 's mode suffix determines the units of the displacement ( bytes for `` _offset '' , elements for `` _index '' ) . Return the associated mode suffix on success , otherwise report an error and return MODE_none .


"multiversioning needs %<ifunc%> which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> void ARMConstantPoolMBB :: print ( raw_ostream & O ) const { O << printMBBReference ( * MBB ) ; ARMConstantPoolValue :: print ( O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool nds32_gw_mm_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : case TYPE_MUL : case TYPE_MAC : case TYPE_DALU64 : case TYPE_DMUL : case TYPE_DMAC : case TYPE_DALUROUND : case TYPE_DBPICK : case TYPE_DWEXT : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , 0 ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , 1 ) ) ; return ( gw_consumed_by_ex_dep_p ( consumer , def_reg1 ) || gw_consumed_by_ex_dep_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return gw_consumed_by_ex_dep_p ( consumer , def_reg ) ; } </s>


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> static rtx rs6000_adjust_atomic_subword ( rtx orig_mem , rtx * pshift , rtx * pmask ) { rtx addr , align , shift , mask , mem ; HOST_WIDE_INT shift_mask ; machine_mode mode = GET_MODE ( orig_mem ) ; shift_mask = ( mode == QImode ? 0x18 : 0x10 ) ; addr = XEXP ( orig_mem , 0 ) ; addr = force_reg ( GET_MODE ( addr ) , addr ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - 4 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; mem = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; shift = gen_reg_rtx ( SImode ) ; addr = gen_lowpart ( SImode , addr ) ; rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashlsi3 ( tmp , addr , GEN_INT ( 3 ) ) ) ; emit_insn ( gen_andsi3 ( shift , tmp , GEN_INT ( shift_mask ) ) ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_simple_binop ( SImode , XOR , shift , GEN_INT ( shift_mask ) , shift , 1 , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_simple_binop ( SImode , ASHIFT , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; * pmask = mask ; return mem ; } </s>

A subroutine of the various atomic expanders . For sub-word operations , we must adjust things to operate on SImode . Given the original MEM , return a new aligned memory . Also build and return the quantities by which to shift and mask .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::READCYCLECOUNTER


<s> static unsigned rs6000_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; if ( ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec ) || ( where == vect_body && kind == vector_stmt ) ) rs6000_vect_nonmem = true ; } return retval ; } </s>


<s> static int csky_num_arg_regs ( machine_mode mode , const_tree type , bool is_stdarg ) { int size ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( TARGET_HARD_FLOAT_ABI && ! is_stdarg ) { if ( CSKY_VREG_MODE_P ( mode ) && ! TARGET_SINGLE_FPU ) return ( ( CSKY_NUM_WORDS ( size ) + 1 ) / 2 ) ; } return CSKY_NUM_WORDS ( size ) ; } </s>

Return the number of registers ( words ) needed to pass an argument of MODE and TYPE .


"Should only have an r11 thunk on 64-bit targets"

runOnMachineFunction - Emit the function body .


<s> static void mips_sim_issue_insn ( struct mips_sim * state , rtx insn ) { state_transition ( state -> dfa_state , insn ) ; state -> insns_left -- ; mips_sim_insn = insn ; note_stores ( PATTERN ( insn ) , mips_sim_record_set , state ) ; } </s>

Issue instruction INSN in scheduler state STATE . Assume that INSN can issue immediately ( i.e. , that mips_sim_wait_insn has already been called ) .


"parameter passing for argument of type "

Lay out a function argument using the AAPCS rules . The rule numbers referred to here are those in the AAPCS .


<s> static rtx loongarch_emit_set ( rtx target , rtx src ) { emit_insn ( gen_rtx_SET ( target , src ) ) ; return target ; } </s>

Emit an instruction of the form ( set TARGET SRC ) .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getTargetTriple
(
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
getOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> static scalar_int_mode pru_unwind_word_mode ( void ) { return SImode ; } </s>

Implement TARGET_UNWIND_WORD_MODE . Since PRU is really a 32-bit CPU , the default word_mode is not suitable .


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static bool rs6000_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] ; unsigned from_nregs = hard_regno_nregs [ FIRST_FPR_REGNO ] [ from ] ; bool to_float128_vector_p = FLOAT128_VECTOR_P ( to ) ; bool from_float128_vector_p = FLOAT128_VECTOR_P ( from ) ; if ( to_float128_vector_p && from_float128_vector_p ) return false ; else if ( to_float128_vector_p || from_float128_vector_p ) return true ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return true ; if ( from_size < 8 || to_size < 8 ) return true ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return true ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return true ; return false ; } else return false ; } if ( TARGET_E500_DOUBLE && ( ( ( ( to ) == DFmode ) + ( ( from ) == DFmode ) ) == 1 || ( ( ( to ) == TFmode ) + ( ( from ) == TFmode ) ) == 1 || ( ( ( to ) == IFmode ) + ( ( from ) == IFmode ) ) == 1 || ( ( ( to ) == KFmode ) + ( ( from ) == KFmode ) ) == 1 || ( ( ( to ) == DDmode ) + ( ( from ) == DDmode ) ) == 1 || ( ( ( to ) == TDmode ) + ( ( from ) == TDmode ) ) == 1 || ( ( ( to ) == DImode ) + ( ( from ) == DImode ) ) == 1 ) ) return true ; if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] > num_regs || hard_regno_nregs [ FIRST_FPR_REGNO ] [ from ] > num_regs ) return true ; return ( from_size != 8 && from_size != 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return true ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( from ) + SPE_VECTOR_MODE ( to ) ) == 1 && reg_classes_intersect_p ( GENERAL_REGS , rclass ) ) return true ; return false ; } </s>

Return nonzero if for CLASS a mode change from FROM to TO is invalid .


<s>
static
void
adjust_xxpermdi
(
rtx_insn
*
insn
)
{
rtx
set
=
PATTERN
(
insn
)
;
rtx
select
=
XEXP
(
set
,
1
)
;
rtx
concat
=
XEXP
(
select
,
0
)
;
rtx
src0
=
XEXP
(
concat
,
0
)
;
XEXP
(
concat
,
0
)
=
XEXP
(
concat
,
1
)
;
XEXP
(
concat
,
1
)
=
src0
;
rtx
parallel
=
XEXP
(
select
,
1
)
;
int
lane0
=
INTVAL
(
XVECEXP
(
parallel
,
0
,
0
)
)
;
int
lane1
=
INTVAL
(
XVECEXP
(
parallel
,
0
,
1
)
)
;
int
new_lane0
=
3
lane1
;
int
new_lane1
=
3
lane0
;
XVECEXP
(
parallel
,
0
,
0
)
=
GEN_INT
(
new_lane0
)
;
XVECEXP
(
parallel
,
0
,
1
)
=
GEN_INT
(
new_lane1
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lanes for xxpermdi %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains an XXPERMDI operation ( that is not a doubleword swap ) , reverse the order of the source operands and adjust the indices of the source lanes to account for doubleword reversal .


<s> void handleAssemblerFlag ( MCAssemblerFlag Flag ) { switch ( Flag ) { default : break ; case MCAF_Code16 : setIsThumb ( true ) ; break ; case MCAF_Code32 : setIsThumb ( false ) ; break ; } } </s>

Handle any target-specific assembler flags . By default , do nothing .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } addPass ( createARMIndirectThunks ( ) ) ; addPass ( createARMSLSHardeningPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s> static tree aarch64_add_attribute ( const char * name , tree attrs ) { return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ; } </s>


<s> bool AArch64InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; switch ( MI . getOpcode ( ) ) { case AArch64 :: DSB : case AArch64 :: ISB : return true ; default : ; } return isSEHInstruction ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static bool ix86_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case asin_optab : case acos_optab : case log1p_optab : case exp_optab : case exp10_optab : case exp2_optab : case expm1_optab : case ldexp_optab : case scalb_optab : case round_optab : return opt_type == OPTIMIZE_FOR_SPEED ; case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_ROUND ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && TARGET_ROUND ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static const char * mmix_strip_name_encoding ( const char * name ) { for ( ; ( * name == '@' || * name == '*' ) ; name ++ ) ; return name ; } </s>


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: RESTORE_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
X86TargetMachine
::
X86TargetMachine
(
const
Target
&
T
,
const
std
::
string
&
TT
,
const
std
::
string
&
FS
,
bool
is64Bit
)
:
LLVMTargetMachine
(
T
,
TT
)
,
Subtarget
(
TT
,
FS
,
is64Bit
)
,
DataLayout
(
Subtarget
.
getDataLayout
(
)
)
,
FrameInfo
(
TargetFrameInfo
::
StackGrowsDown
,
Subtarget
.
getStackAlignment
(
)
,
(
Subtarget
.
isTargetWin64
(
)
40
:
(
Subtarget
.
is64Bit
(
)
8
:
4
)
)
)
,
InstrInfo
(
*
this
)
,
JITInfo
(
*
this
)
,
TLInfo
(
*
this
)
,
TSInfo
(
*
this
)
,
ELFWriterInfo
(
*
this
)
{
DefRelocModel
=
getRelocationModel
(
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
Default
)
{
if
(
Subtarget
.
isTargetDarwin
(
)
)
{
if
(
Subtarget
.
is64Bit
(
)
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
setRelocationModel
(
Reloc
::
DynamicNoPIC
)
;
}
else
if
(
Subtarget
.
isTargetWin64
(
)
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
setRelocationModel
(
Reloc
::
Static
)
;
}
assert
(
getRelocationModel
(
)
!=
Reloc
::
Default
&&
"Relocation mode not picked"
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
{
if
(
is64Bit
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
if
(
!
Subtarget
.
isTargetDarwin
(
)
)
setRelocationModel
(
Reloc
::
Static
)
;
}
if
(
getRelocationModel
(
)
==
Reloc
::
Static
&&
Subtarget
.
isTargetDarwin
(
)
&&
is64Bit
)
setRelocationModel
(
Reloc
::
PIC_
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
Static
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
)
;
}
else
if
(
Subtarget
.
is64Bit
(
)
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
RIPRel
)
;
}
else
if
(
Subtarget
.
isTargetCygMing
(
)
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
)
;
}
else
if
(
Subtarget
.
isTargetDarwin
(
)
)
{
if
(
getRelocationModel
(
)
==
Reloc
::
PIC_
)
Subtarget
.
setPICStyle
(
PICStyles
::
StubPIC
)
;
else
{
assert
(
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
;
Subtarget
.
setPICStyle
(
PICStyles
::
StubDynamicNoPIC
)
;
}
}
else
if
(
Subtarget
.
isTargetELF
(
)
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
GOT
)
;
}
if
(
Subtarget
.
getPICStyle
(
)
==
PICStyles
::
)
setRelocationModel
(
Reloc
::
Static
)
;
}
</s>


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; ReserveXRegister . set ( 19 ) ; ReserveXRegister . set ( 20 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static rtx_insn * nds32_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { if ( ! flag_inline_asm_r15 ) { clobbers . safe_push ( gen_rtx_REG ( SImode , TA_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , TA_REGNUM ) ; } return NULL ; } </s>


<s> void FixupLEAPass :: processInstruction ( MachineBasicBlock :: iterator & I , MachineBasicBlock & MBB ) { MachineInstr & MI = * I ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int AddrOffset = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( AddrOffset >= 0 ) { AddrOffset += X86II :: getOperandBias ( Desc ) ; MachineOperand & p = MI . getOperand ( AddrOffset + X86 :: AddrBaseReg ) ; if ( p . isReg ( ) && p . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( p , I , MBB ) ; } MachineOperand & q = MI . getOperand ( AddrOffset + X86 :: AddrIndexReg ) ; if ( q . isReg ( ) && q . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( q , I , MBB ) ; } } } </s>

Process a single instruction and collect debug info anchors .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

"Incorrect array index for MVE_VMOV_q_rr"

"Incorrect AddrMode Imm for instruction"

Perform target-specific instruction verification .


<s> static int is_dispatch_slot_restricted ( rtx insn ) { enum attr_type type ; if ( ! rs6000_sched_groups ) return 0 ; if ( ! insn || insn == NULL_RTX || GET_CODE ( insn ) == NOTE || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return 0 ; type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MFCR : case TYPE_MFCRF : case TYPE_MTCR : case TYPE_DELAYED_CR : case TYPE_CR_LOGICAL : case TYPE_MTJMPR : case TYPE_MFJMPR : return 1 ; case TYPE_IDIV : case TYPE_LDIV : return 2 ; case TYPE_LOAD_L : case TYPE_STORE_C : case TYPE_ISYNC : case TYPE_SYNC : return 4 ; default : if ( rs6000_cpu == PROCESSOR_POWER5 && is_cracked_insn ( insn ) ) return 2 ; return 0 ; } } </s>

The function returns a nonzero value if INSN can be scheduled only as the first insn in a dispatch group ( `` dispatch-slot restricted '' ) . In this case , the returned value indicates how many dispatch slots the insn occupies ( at the beginning of the group ) . Return 0 otherwise .


<s> ix86_dependencies_evaluation_hook static int ix86_reassociation_width ( unsigned int op , machine_mode mode ) { int width = 1 ; if ( VECTOR_MODE_P ( mode ) ) { int div = 1 ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == 1 ) return 1 ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return 1 ; if ( TARGET_AVX128_OPTIMAL && GET_MODE_BITSIZE ( mode ) > 128 ) div = GET_MODE_BITSIZE ( mode ) / 128 ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 64 ) div = GET_MODE_BITSIZE ( mode ) / 64 ; width = ( width + div - 1 ) / div ; } else if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_fp ; if ( ! TARGET_64BIT && width > 2 ) width = 2 ; return width ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s>
const
RegisterBankInfo
*
ARMSubtarget
::
getRegBankInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getRegBankInfo
(
)
;
}
</s>

If the information for the register banks is available , return it .

ARM
ARM
"Access to GlobalISel APIs not set"


<s> static std :: unique_ptr < ARMOperand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = make_unique < ARMOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) , false ) ; addPass ( createPPCBranchSelectionPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void get_ppc476_thunk_name ( char name [ 32 ] ) { gcc_assert ( TARGET_LINK_STACK ) ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__ppc476.get_thunk" ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LPPC476_" , 0 ) ; } </s>

Fills in the label name that should be used for a 476 link stack thunk .


<s> unsigned X86InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameLoadOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> Reloc :: Model MipsSubtarget :: getRelocationModel ( ) const { return TM -> getRelocationModel ( ) ; } </s>

Returns the code generation relocation model .


<s> void print ( raw_ostream & OS ) const { } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , 0 ) , false ) ) return true ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( TARGET_MACHO && GET_CODE ( addr ) == LO_SUM ) return darwin_rs6000_legitimate_lo_sum_const_p ( XEXP ( addr , 1 ) , mode ) ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset , extra ) ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> static unsigned HOST_WIDE_INT mips_asan_shadow_offset ( void ) { return SUBTARGET_SHADOW_OFFSET ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> static rtx rs6000_delegitimize_address ( rtx orig_x ) { rtx x , y , offset ; if ( GET_CODE ( orig_x ) == UNSPEC ) switch ( XINT ( orig_x , 1 ) ) { case UNSPEC_FUSION_GPR : case UNSPEC_PCREL_OPT_LD_ADDR : case UNSPEC_PCREL_OPT_LD_SAME_REG : case UNSPEC_PCREL_OPT_ST_ADDR : orig_x = XVECEXP ( orig_x , 0 , 0 ) ; break ; default : break ; } orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , 1 ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , 1 ) ) ) { offset = XEXP ( y , 1 ) ; y = XEXP ( y , 0 ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , 0 , 0 ) ; if ( TARGET_XCOFF && SYMBOL_REF_P ( y ) && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , 1 ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , 1 ) , 0 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP ( y , 0 , 0 ) ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> void mep_print_operand_address ( FILE * stream , rtx address ) { if ( GET_CODE ( address ) == MEM ) address = XEXP ( address , 0 ) ; else gcc_assert ( GET_CODE ( address ) == REG ) ; mep_print_operand ( stream , address , 0 ) ; } </s>


<s> bool ARMFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> int mips_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { int size ; HARD_REG_SET left ; size = 0x8000 ; COPY_HARD_REG_SET ( left , reg_class_contents [ ( int ) rclass ] ) ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) ST_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( ST_REG_FIRST , mode ) ) size = MIN ( size , 4 ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) ST_REGS ] ) ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( FP_REG_FIRST , mode ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) size = MIN ( size , UNITS_PER_MSA_REG ) ; else size = MIN ( size , UNITS_PER_FPREG ) ; } AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) FP_REGS ] ) ; } if ( ! hard_reg_set_empty_p ( left ) ) size = MIN ( size , UNITS_PER_WORD ) ; return ( GET_MODE_SIZE ( mode ) + size - 1 ) / size ; } </s>

Implement CLASS_MAX_NREGS . Usually all registers are word-sized . The only supported exception is -mgp64 -msingle-float , which has 64-bit words but 32-bit float registers . A word-based calculation is correct even in that case , since -msingle-float disallows multi-FPR values . The FP status registers are an exception to this rule . They are always 4 bytes wide as they only hold condition code modes , and CCmode is always considered to be 4 bytes wide .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } if ( getPPCTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { addPass ( & LiveVariablesID , false ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
const
char
*
nds32_output_32bit_store
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
=
XEXP
(
operands
[
0
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
GET_CODE
(
code
)
)
{
case
REG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci\t%%1, %%0"
,
size
)
;
break
;
case
SYMBOL_REF
:
case
CONST
:
operands
[
0
]
=
XEXP
(
operands
[
0
]
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci.gp\t%%1, [ + %%0]"
,
size
)
;
break
;
case
POST_INC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci.bi\t%%1, %%0, %d"
,
size
,
byte
)
;
break
;
case
POST_DEC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci.bi\t%%1, %%0, -%d"
,
size
,
byte
)
;
break
;
case
POST_MODIFY
:
switch
(
GET_CODE
(
XEXP
(
XEXP
(
code
,
1
)
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%c.bi\t%%1, %%0"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci.bi\t%%1, %%0"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
PLUS
:
switch
(
GET_CODE
(
XEXP
(
code
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%c\t%%1, %%0"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci\t%%1, %%0"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
LO_SUM
:
operands
[
2
]
=
XEXP
(
code
,
1
)
;
operands
[
0
]
=
XEXP
(
code
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci\t%%1, [%%0 + lo12(%%2)]"
,
size
)
;
break
;
default
:
abort
(
)
;
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>


<s>
void
X86InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
X86
::
GR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MOV64rr
;
else
if
(
X86
::
GR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MOV32rr
;
else
if
(
X86
::
GR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MOV16rr
;
else
if
(
X86
::
GR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
(
isHReg
(
DestReg
)
||
isHReg
(
SrcReg
)
)
&&
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
)
Opc
=
X86
::
MOV8rr_NOREX
;
else
Opc
=
X86
::
MOV8rr
;
}
else
if
(
X86
::
VR128RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MOVAPSrr
;
else
if
(
X86
::
VR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MMX_MOVQ64rr
;
else
Opc
=
CopyToFromAsymmetricReg
(
DestReg
,
SrcReg
)
;
if
(
Opc
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
if
(
SrcReg
==
X86
::
EFLAGS
)
{
if
(
X86
::
GR64RegClass
.
contains
(
DestReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
PUSHF64
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
POP64r
)
,
DestReg
)
;
return
;
}
else
if
(
X86
::
GR32RegClass
.
contains
(
DestReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
PUSHF32
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
POP32r
)
,
DestReg
)
;
return
;
}
}
if
(
DestReg
==
X86
::
EFLAGS
)
{
if
(
X86
::
GR64RegClass
.
contains
(
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
PUSH64r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
POPF64
)
)
;
return
;
}
else
if
(
X86
::
GR32RegClass
.
contains
(
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
PUSH32r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
POPF32
)
)
;
return
;
}
}
DEBUG
(
dbgs
(
)
<<
"Cannot copy "
<<
RI
.
getName
(
SrcReg
)
<<
" to "
<<
RI
.
getName
(
DestReg
)
<<
'\n'
)
;
llvm_unreachable
(
"Cannot emit physreg copy instruction"
)
;
}
</s>


<s> static void mmix_init_libfuncs ( void ) { set_optab_libfunc ( ffs_optab , SImode , "__ffsdi2" ) ; } </s>

Unfortunately , by default __builtin_ffs is expanded to ffs for targets where INT_TYPE_SIZE < BITS_PER_WORD . That together with newlib since 2017-07-04 implementing ffs as __builtin_ffs leads to ( newlib ) ffs recursively calling itself . But , because of argument promotion , and with ffs we 're counting from the least bit , the libgcc equivalent for ffsl works equally well for int arguments , so just use that .


<s> bool X86Subtarget :: isLegalToCallImmediateAddr ( ) const { if ( In64BitMode || isTargetWin32 ( ) ) return false ; return isTargetELF ( ) || TM . getRelocationModel ( ) == Reloc :: Static ; } </s>

Return true if the subtarget allows calls to immediate address .


<s> int ccr_bit ( rtx op , int scc_p ) { enum rtx_code code = GET_CODE ( op ) ; machine_mode cc_mode ; int cc_regnum ; int base_bit ; rtx reg ; if ( ! COMPARISON_P ( op ) ) return - 1 ; reg = XEXP ( op , 0 ) ; if ( ! REG_P ( reg ) || ! CR_REGNO_P ( REGNO ( reg ) ) ) return - 1 ; cc_mode = GET_MODE ( reg ) ; cc_regnum = REGNO ( reg ) ; base_bit = 4 * ( cc_regnum - CR0_REGNO ) ; validate_condition_mode ( code , cc_mode ) ; if ( scc_p ) switch ( code ) { case EQ : case GT : case LT : case UNORDERED : case GTU : case LTU : break ; default : return - 1 ; } switch ( code ) { case NE : return scc_p ? base_bit + 3 : base_bit + 2 ; case EQ : return base_bit + 2 ; case GT : case GTU : case UNLE : return base_bit + 1 ; case LT : case LTU : case UNGE : return base_bit ; case ORDERED : case UNORDERED : return base_bit + 3 ; case GE : case GEU : return scc_p ? base_bit + 3 : base_bit ; case LE : case LEU : return scc_p ? base_bit + 3 : base_bit + 1 ; default : return - 1 ; } } </s>

Given a comparison operation , return the bit number in CCR to test . We know this is a valid comparison . SCC_P is 1 if this is for an scc . That means that % D will have been used instead of % C , so the bits will be in different places . Return -1 if OP is n't a valid comparison for some reason .


<s>
static
void
csky_print_operand_address
(
FILE
*
stream
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
rtx
x
)
{
struct
csky_address
addr
;
decompose_csky_address
(
x
,
&
addr
)
;
if
(
addr
.
label
&&
addr
.
disp
&&
GET_CODE
(
addr
.
disp
)
==
CONST_INT
)
{
fprintf
(
stream
,
"["
)
;
csky_output_constpool_label
(
stream
,
addr
.
label
)
;
fprintf
(
stream
,
"+%d]"
,
(
int
)
INTVAL
(
addr
.
disp
)
)
;
}
else
if
(
addr
.
label
)
{
fprintf
(
stream
,
"["
)
;
csky_output_constpool_label
(
stream
,
addr
.
label
)
;
fprintf
(
stream
,
"]"
)
;
}
else
if
(
addr
.
symbol
&&
addr
.
disp
&&
GET_CODE
(
addr
.
disp
)
==
CONST_INT
)
{
fprintf
(
stream
,
"["
)
;
output_addr_const
(
stream
,
addr
.
symbol
)
;
fprintf
(
stream
,
"+%d]"
,
(
int
)
INTVAL
(
addr
.
disp
)
)
;
}
else
if
(
addr
.
symbol
)
{
fprintf
(
stream
,
"["
)
;
output_addr_const
(
stream
,
addr
.
symbol
)
;
fprintf
(
stream
,
"]"
)
;
}
else
if
(
addr
.
disp
&&
GET_CODE
(
addr
.
disp
)
==
CONST_INT
)
fprintf
(
stream
,
"(%s, %d)"
,
reg_names
[
REGNO
(
addr
.
base
)
]
,
(
int
)
INTVAL
(
addr
.
disp
)
)
;
else
if
(
addr
.
disp
&&
GET_CODE
(
addr
.
disp
)
==
UNSPEC
)
{
if
(
REGNO
(
addr
.
base
)
!=
CSKY_GB_REGNUM
)
fprintf
(
stream
,
"(%s, "
,
reg_names
[
REGNO
(
addr
.
base
)
]
)
;
else
fprintf
(
stream
,
"["
)
;
csky_output_pic_addr_const
(
stream
,
addr
.
disp
,
0
)
;
fprintf
(
stream
,
"%s"
,
(
REGNO
(
addr
.
base
)
!=
CSKY_GB_REGNUM
)
")"
:
"]"
)
;
}
else
if
(
addr
.
index
)
fprintf
(
stream
,
"(%s, %s << %d)"
,
reg_names
[
REGNO
(
addr
.
base
)
]
,
reg_names
[
REGNO
(
addr
.
index
)
]
,
exact_log2
(
(
int
)
(
addr
.
scale
)
)
)
;
else
fprintf
(
stream
,
"(%s, 0)"
,
reg_names
[
REGNO
(
addr
.
base
)
]
)
;
}
</s>


<s> static int loongarch_adjust_cost ( rtx_insn * , int dep_type , rtx_insn * , int cost , unsigned int ) { if ( dep_type != 0 && ( dep_type != REG_DEP_OUTPUT ) ) return 0 ; return cost ; } </s>

Implement TARGET_SCHED_ADJUST_COST . We assume that anti and output dependencies have no cost .


<s> void mips_split_move_insn ( rtx dest , rtx src , rtx insn ) { mips_split_move ( dest , src , mips_insn_split_type ( insn ) ) ; } </s>

Split a move from SRC to DEST in INSN , given that mips_split_move_insn_p holds .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( TRI -> hasBasePointer ( MF ) ) { unsigned BasePtr = TRI -> getBaseRegister ( ) ; if ( STI . isTarget64BitILP32 ( ) ) BasePtr = getX86SubSuperRegister ( BasePtr , 64 ) ; SavedRegs . set ( BasePtr ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
void
MipsInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\t.set\tpush\n"
;
O
<<
"\t.set\tmips32r2\n"
;
break
;
case
Mips
::
Save16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
SaveX16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
case
Mips
::
Restore16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
RestoreX16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
}
if
(
!
printAliasInstr
(
MI
,
O
)
&&
!
printAlias
(
*
MI
,
O
)
)
printInstruction
(
MI
,
Address
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\n\t.set\tpop"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void rs6000_live_on_entry ( bitmap regs ) { if ( flag_split_stack ) bitmap_set_bit ( regs , 12 ) ; } </s>

We may have to tell the dataflow pass that the split stack prologue is initializing a register .


<s> static bool aarch64_advsimd_ldp_stp_p ( enum vect_cost_for_stmt kind , stmt_vec_info stmt_info ) { switch ( kind ) { case vector_load : case vector_store : case unaligned_load : case unaligned_store : break ; default : return false ; } if ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS ) return false ; return is_gimple_assign ( stmt_info -> stmt ) ; } </s>

Return true if creating multiple copies of STMT_INFO for Advanced SIMD vectors would produce a series of LDP or STP operations . KIND is the kind of statement that STMT_INFO represents .


<s> static void rs6000_maybe_dead ( rtx insn ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_MAYBE_DEAD , const0_rtx , REG_NOTES ( insn ) ) ; } </s>


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool X86ATTAsmParser :: ParseInstruction ( const StringRef & Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { StringRef PatchedName = StringSwitch < StringRef > ( Name ) . Case ( "sal" , "shl" ) . Case ( "salb" , "shlb" ) . Case ( "sall" , "shll" ) . Case ( "salq" , "shlq" ) . Case ( "salw" , "shlw" ) . Case ( "repe" , "rep" ) . Case ( "repz" , "rep" ) . Case ( "repnz" , "repne" ) . Default ( Name ) ; Operands . push_back ( X86Operand :: CreateToken ( PatchedName , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( getLexer ( ) . is ( AsmToken :: Star ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( X86Operand :: CreateToken ( "*" , Loc ) ) ; Parser . Lex ( ) ; } if ( X86Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( X86Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; } } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

X86 X86 "sal" "shl" "salb" "shlb" "sall" "shll" "salq" "shlq" "salw" "shlw" "repe" "rep" "repz" "rep" "repnz" "repne" X86Operand::CreateToken X86Operand::CreateToken "*" X86 X86


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << "[" << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << "]" ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNum ) . isReg ( ) || OpNum + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNum + 1 ) . isReg ( ) ) return true ; ++ OpNum ; } } printOperand ( MI , OpNum ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static void arm_emit_multi_reg_pop ( unsigned long saved_regs_mask ) { int num_regs = 0 ; int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( 1 << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? 1 : 0 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 16 ) ; emit_update = ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ? 0 : 1 ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , 0 , 0 ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , offset_adj ) = tmp ; } for ( j = 0 , i = 0 ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; if ( ( num_regs == 1 ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( VOIDmode , reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( VOIDmode , reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( ! return_in_pc ) arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD * num_regs , stack_pointer_rtx , stack_pointer_rtx ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi . SAVED_REGS_MASK shows which registers need to be restored . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { return true ; } </s>

Helper functions for atomic operations .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) || Subtarget -> hasAVX ( ) ) ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) || Subtarget -> hasAVX ( ) ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static void mep_rewrite_mulsi3 ( rtx_insn * insn , rtx dest , rtx src1 , rtx src2 ) { rtx lo , pattern ; lo = gen_rtx_REG ( SImode , LO_REGNO ) ; if ( dest ) pattern = gen_mulsi3r ( lo , dest , copy_rtx ( dest ) , mep_mulr_source ( insn , dest , src1 , src2 ) ) ; else pattern = gen_mulsi3_lo ( lo , src1 , src2 ) ; mep_rewrite_mult ( insn , pattern ) ; } </s>

Subroutine of mep_reuse_lo_p . Rewrite instruction INSN so that it calculates SRC1 * SRC2 and stores the result in $ lo . Also make it store the result in DEST if nonnull .


<s> static void mips_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved , fp_saved ; local_cum = * get_cumulative_args ( cum ) ; mips_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; fp_saved = ( EABI_FLOAT_VARARGS_P ? MAX_ARGS_IN_REGISTERS - local_cum . num_fprs : 0 ) ; if ( ! no_rtl ) { if ( gp_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { machine_mode mode ; int off , i ; off = ROUND_DOWN ( - gp_saved * UNITS_PER_WORD , UNITS_PER_FPVALUE ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += MAX_FPRS_PER_FMT ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; mips_emit_move ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE ; } } } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = ( gp_saved * UNITS_PER_WORD + fp_saved * UNITS_PER_FPREG ) ; } </s>


"Unexpected register class in CSRsViaCopy!"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


A subroutine of expand_vec_perm_even_odd_1 . Implement extract-even and extract-odd permutations of two V32QImode and V16QImode operand with two vpshufb insns , vpor and vpermq . We should have already failed all two or three instruction sequences .


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , 0 ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ; } </s>

Locate some local-dynamic symbol still in use by this function so that we can print its name in local-dynamic base patterns .


<s> BitVector SICRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { SIC :: X , SIC :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
unsigned
ARMBaseInstrInfo
::
getNumMicroOps
(
const
InstrItineraryData
*
ItinData
,
const
MachineInstr
*
MI
)
const
{
if
(
!
ItinData
||
ItinData
->
isEmpty
(
)
)
return
1
;
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
Class
=
Desc
.
getSchedClass
(
)
;
unsigned
UOps
=
ItinData
->
Itineraries
[
Class
]
.
NumMicroOps
;
if
(
UOps
)
return
UOps
;
unsigned
Opc
=
MI
->
getOpcode
(
)
;
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Unexpected multi-uops instruction!"
)
;
break
;
case
ARM
::
VLDMQIA
:
case
ARM
::
VSTMQIA
:
return
2
;
case
ARM
::
VLDMDIA
:
case
ARM
::
VLDMDIA_UPD
:
case
ARM
::
VLDMDDB_UPD
:
case
ARM
::
VLDMSIA
:
case
ARM
::
VLDMSIA_UPD
:
case
ARM
::
VLDMSDB_UPD
:
case
ARM
::
VSTMDIA
:
case
ARM
::
VSTMDIA_UPD
:
case
ARM
::
VSTMDDB_UPD
:
case
ARM
::
VSTMSIA
:
case
ARM
::
VSTMSIA_UPD
:
case
ARM
::
VSTMSDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
;
return
(
NumRegs
/
2
)
+
(
NumRegs
%
2
)
+
1
;
}
case
ARM
::
LDMIA_RET
:
case
ARM
::
LDMIA
:
case
ARM
::
LDMDA
:
case
ARM
::
LDMDB
:
case
ARM
::
LDMIB
:
case
ARM
::
LDMIA_UPD
:
case
ARM
::
LDMDA_UPD
:
case
ARM
::
LDMDB_UPD
:
case
ARM
::
LDMIB_UPD
:
case
ARM
::
STMIA
:
case
ARM
::
STMDA
:
case
ARM
::
STMDB
:
case
ARM
::
STMIB
:
case
ARM
::
STMIA_UPD
:
case
ARM
::
STMDA_UPD
:
case
ARM
::
STMDB_UPD
:
case
ARM
::
STMIB_UPD
:
case
ARM
::
tLDMIA
:
case
ARM
::
tLDMIA_UPD
:
case
ARM
::
tSTMIA_UPD
:
case
ARM
::
tPOP_RET
:
case
ARM
::
tPOP
:
case
ARM
::
tPUSH
:
case
ARM
::
t2LDMIA_RET
:
case
ARM
::
t2LDMIA
:
case
ARM
::
t2LDMDB
:
case
ARM
::
t2LDMIA_UPD
:
case
ARM
::
t2LDMDB_UPD
:
case
ARM
::
t2STMIA
:
case
ARM
::
t2STMDB
:
case
ARM
::
t2STMIA_UPD
:
case
ARM
::
t2STMDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
+
1
;
if
(
Subtarget
.
isCortexA8
(
)
)
{
if
(
NumRegs
<
4
)
return
2
;
UOps
=
(
NumRegs
/
2
)
;
if
(
NumRegs
%
2
)
++
UOps
;
return
UOps
;
}
else
if
(
Subtarget
.
isCortexA9
(
)
)
{
UOps
=
(
NumRegs
/
2
)
;
if
(
(
NumRegs
%
2
)
||
!
MI
->
hasOneMemOperand
(
)
||
(
*
MI
->
memoperands_begin
(
)
)
->
getAlignment
(
)
<
8
)
++
UOps
;
return
UOps
;
}
else
{
return
NumRegs
;
}
}
}
}
</s>

Return the number of issue slots required for this MI .


Emit unwind opcodes for .vsave directives .


<s> static rtx mips_legitimize_tls_address ( rtx loc ) { rtx dest , insn , v0 , v1 , tmp1 , tmp2 , eqv ; enum tls_model model ; v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; v1 = gen_rtx_REG ( Pmode , GP_RETURN + 1 ) ; model = SYMBOL_REF_TLS_MODEL ( loc ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , mips_unspec_address ( loc , SYMBOL_DTPREL ) ) ; break ; case TLS_MODEL_INITIAL_EXEC : tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = mips_unspec_address ( loc , SYMBOL_GOTTPREL ) ; if ( Pmode == DImode ) { emit_insn ( gen_tls_get_tp_di ( v1 ) ) ; emit_insn ( gen_load_gotdi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; } else { emit_insn ( gen_tls_get_tp_si ( v1 ) ) ; emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; } dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , v1 ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : if ( Pmode == DImode ) emit_insn ( gen_tls_get_tp_di ( v1 ) ) ; else emit_insn ( gen_tls_get_tp_si ( v1 ) ) ; tmp1 = mips_unspec_offset_high ( NULL , v1 , loc , SYMBOL_TPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp1 , mips_unspec_address ( loc , SYMBOL_TPREL ) ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread local SYMBOL_REF . The return value will be a valid address and move_operand ( either a REG or a LO_SUM ) .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = Mang -> getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Mang , MMI , Encoding , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s>
bool
Cpu0AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
if
(
Mnemonic
==
"ret"
)
Mnemonic
=
"jr"
;
Operands
.
push_back
(
Cpu0Operand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>


<s> static bool mips_need_noat_wrapper_p ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( recog_memoized ( insn ) >= 0 ) { subrtx_iterator :: array_type array ; for ( int i = 0 ; i < noperands ; i ++ ) FOR_EACH_SUBRTX ( iter , array , opvec [ i ] , NONCONST ) if ( REG_P ( * iter ) && REGNO ( * iter ) == AT_REGNUM ) return true ; } return false ; } </s>

Return true if INSN needs to be wrapped in `` .set noat '' . INSN has NOPERANDS operands , stored in OPVEC .


<s>
bool
FISCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
int
Offset
=
0
;
if
(
ExtraCode
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
FISCInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
", "
<<
Offset
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

FISC
FISC
0
"unexpected inline asm memory operand"
"["
FISC
", "
"]"


<s> void aarch64_gen_atomic_ldop ( enum rtx_code code , rtx out_data , rtx out_result , rtx mem , rtx value , rtx model_rtx ) { machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; const bool short_mode = ( mode < SImode ) ; aarch64_atomic_load_op_code ldop_code ; rtx src ; rtx x ; if ( out_data ) out_data = gen_lowpart ( mode , out_data ) ; if ( out_result ) out_result = gen_lowpart ( mode , out_result ) ; if ( ! register_operand ( value , mode ) || code == AND || code == MINUS ) { src = out_result ? out_result : out_data ; emit_move_insn ( src , gen_lowpart ( mode , value ) ) ; } else src = value ; gcc_assert ( register_operand ( src , mode ) ) ; switch ( code ) { case SET : aarch64_emit_atomic_swap ( mode , out_data , src , mem , model_rtx ) ; return ; case MINUS : { rtx neg_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; neg_src = gen_rtx_NEG ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , neg_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } case PLUS : ldop_code = AARCH64_LDOP_PLUS ; break ; case IOR : ldop_code = AARCH64_LDOP_OR ; break ; case XOR : ldop_code = AARCH64_LDOP_XOR ; break ; case AND : { rtx not_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; not_src = gen_rtx_NOT ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , not_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } ldop_code = AARCH64_LDOP_BIC ; break ; default : gcc_unreachable ( ) ; } aarch64_emit_atomic_load_op ( ldop_code , mode , out_data , src , mem , model_rtx ) ; if ( ! out_result ) return ; if ( short_mode ) { src = gen_lowpart ( wmode , src ) ; out_data = gen_lowpart ( wmode , out_data ) ; out_result = gen_lowpart ( wmode , out_result ) ; } x = NULL_RTX ; switch ( code ) { case MINUS : case PLUS : x = gen_rtx_PLUS ( wmode , out_data , src ) ; break ; case IOR : x = gen_rtx_IOR ( wmode , out_data , src ) ; break ; case XOR : x = gen_rtx_XOR ( wmode , out_data , src ) ; break ; case AND : aarch64_emit_bic ( wmode , out_result , out_data , src , 0 ) ; return ; default : gcc_unreachable ( ) ; } emit_set_insn ( out_result , x ) ; return ; } </s>

Emit an atomic load+operate . CODE is the operation . OUT_DATA is the location to store the data read from memory . OUT_RESULT is the location to store the result of the operation . MEM is the memory location to read and modify . MODEL_RTX is the memory ordering to use . VALUE is the second operand for the operation . Either OUT_DATA or OUT_RESULT , but not both , can be NULL .


<s>
bool
AArch64AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
size_t
CondCodePos
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
substr
(
0
,
CondCodePos
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
CondCodePos
!=
StringRef
::
npos
)
{
SMLoc
S
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
CondCodePos
+
1
)
;
StringRef
CondStr
=
Name
.
substr
(
CondCodePos
+
1
,
StringRef
::
npos
)
;
A64CC
::
CondCodes
Code
;
Code
=
A64StringToCondCode
(
CondStr
)
;
if
(
Code
==
A64CC
::
Invalid
)
{
Error
(
S
,
"invalid condition code"
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
SMLoc
DotL
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
CondCodePos
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateToken
(
"."
,
DotL
)
)
;
SMLoc
E
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
CondCodePos
+
3
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateCondCode
(
Code
,
S
,
E
)
)
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
if
(
Parser
.
getTok
(
)
.
is
(
AsmToken
::
RBrac
)
)
{
SMLoc
Loc
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateToken
(
"]"
,
Loc
)
)
;
Parser
.
Lex
(
)
;
}
if
(
Parser
.
getTok
(
)
.
is
(
AsmToken
::
Exclaim
)
)
{
SMLoc
Loc
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateToken
(
"!"
,
Loc
)
)
;
Parser
.
Lex
(
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"expected comma before next operand"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; enum memmodel model ; rtx model_rtx ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; model_rtx = operands [ 5 ] ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ! is_weak && oldval == const0_rtx ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , rval , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } emit_label ( label2 ) ; if ( strong_zero_p ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , rval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( is_mm_sync ( model ) ) aarch64_emit_post_barrier ( model ) ; } </s>


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , isLittle , Options ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


"value of %<-mfixed-range%> must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> unsigned getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( 0 , 64 ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool AArch64InstrInfo :: getMemOperandWithOffset ( MachineInstr & LdSt , MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> static bool sp_valid_at ( HOST_WIDE_INT cfa_offset ) { const struct machine_frame_state & fs = cfun -> machine -> fs ; if ( fs . sp_realigned && cfa_offset <= fs . sp_realigned_offset ) { gcc_assert ( cfa_offset <= fs . sp_realigned_fp_last ) ; return false ; } return fs . sp_valid ; } </s>

Determine if the stack pointer is valid for accessing the CFA_OFFSET in the frame save area . The register is saved at CFA - CFA_OFFSET .


<s>
bool
SystemZXPLINKFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
return
true
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
SystemZMachineFunctionInfo
*
ZFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
const
SystemZSubtarget
&
Subtarget
=
MF
.
getSubtarget
<
SystemZSubtarget
>
(
)
;
const
TargetInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
auto
&
Regs
=
Subtarget
.
getSpecialRegisters
<
SystemZXPLINK64Registers
>
(
)
;
SystemZ
::
GPRRegs
SpillGPRs
=
ZFI
->
getSpillGPRRegs
(
)
;
DebugLoc
DL
;
if
(
SpillGPRs
.
LowGPR
)
{
assert
(
SpillGPRs
.
LowGPR
!=
SpillGPRs
.
HighGPR
&&
"Should be saving multiple registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
->
get
(
SystemZ
::
STMG
)
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
LowGPR
,
false
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
HighGPR
,
false
)
;
MIB
.
addReg
(
Regs
.
getStackPointerRegister
(
)
)
;
MIB
.
addImm
(
SpillGPRs
.
GPROffset
)
;
auto
&
GRRegClass
=
SystemZ
::
GR64BitRegClass
;
for
(
unsigned
I
=
0
,
E
=
CSI
.
size
(
)
;
I
!=
E
;
++
I
)
{
unsigned
Reg
=
CSI
[
I
]
.
getReg
(
)
;
if
(
GRRegClass
.
contains
(
Reg
)
)
addSavedGPR
(
MBB
,
MIB
,
Reg
,
true
)
;
}
}
for
(
unsigned
I
=
0
,
E
=
CSI
.
size
(
)
;
I
!=
E
;
++
I
)
{
unsigned
Reg
=
CSI
[
I
]
.
getReg
(
)
;
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
CSI
[
I
]
.
getFrameIdx
(
)
,
&
SystemZ
::
FP64BitRegClass
,
TRI
)
;
}
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
CSI
[
I
]
.
getFrameIdx
(
)
,
&
SystemZ
::
VR128BitRegClass
,
TRI
)
;
}
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
SDNode
*
Cpu0DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
NodeTy
=
Node
->
getValueType
(
0
)
;
unsigned
MultOpc
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
MULHS
:
case
ISD
::
MULHU
:
{
MultOpc
=
(
Opcode
==
ISD
::
MULHU
Cpu0
::
MULTu
:
Cpu0
::
MULT
)
;
return
SelectMULT
(
Node
,
MultOpc
,
dl
,
NodeTy
,
false
,
true
)
.
second
;
}
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
Constant
:
{
const
ConstantSDNode
*
CN
=
dyn_cast
<
ConstantSDNode
>
(
Node
)
;
unsigned
Size
=
CN
->
getValueSizeInBits
(
0
)
;
if
(
Size
==
32
)
break
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86SpeculativeLoadHardeningPass ( ) ) ; addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86DynAllocaExpander ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createX86PreTileConfigPass ( ) ) ; else addPass ( createX86FastPreTileConfigPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
void
CAHPInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
assert
(
CAHP
::
GPRRegClass
.
contains
(
DstReg
,
SrcReg
)
&&
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
CAHP
::
MOV
)
,
DstReg
)
.
addReg
(
SrcReg
)
;
}
</s>

CAHP
CAHP
CAHP::GPRRegClass
"Impossible reg-to-reg copy"
CAHP::MOV


<s> static void rs6000_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; if ( cost_data -> loop_info ) { rs6000_adjust_vect_cost_per_loop ( cost_data ) ; rs6000_density_test ( cost_data ) ; } if ( cost_data -> loop_info ) { loop_vec_info vec_info = loop_vec_info_for_loop ( cost_data -> loop_info ) ; if ( ! rs6000_vect_nonmem && LOOP_VINFO_VECT_FACTOR ( vec_info ) == 2 && LOOP_REQUIRES_VERSIONING ( vec_info ) ) cost_data -> cost [ vect_body ] += 10000 ; } * prologue_cost = cost_data -> cost [ vect_prologue ] ; * body_cost = cost_data -> cost [ vect_body ] ; * epilogue_cost = cost_data -> cost [ vect_epilogue ] ; } </s>


<s> const char * LC2200TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( LC2200ISD :: NodeType ) Opcode ) { case LC2200ISD :: FIRST_NUMBER : break ; case LC2200ISD :: RET : return "LC2200ISD::RET" ; case LC2200ISD :: CALL : return "LC2200ISD::CALL" ; case LC2200ISD :: JMP : return "LC2200ISD::JMP" ; case LC2200ISD :: NAND : return "LC2200ISD::NAND" ; case LC2200ISD :: CMP_SKIP : return "LC2200ISD::CMP_SKIP" ; case LC2200ISD :: CMP_JMP : return "LC2200ISD::CMP_JMP" ; case LC2200ISD :: SELECT_MOVE : return "LC2200ISD::SELECT_MOVE" ; case LC2200ISD :: CMP_SELECT_MOVE : return "LC2200ISD::CMP_SELECT_MOVE" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> SDValue ARMTargetLowering :: PerformBRCONDCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue BB = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; if ( CC == ARMCC :: NE && LHS . getOpcode ( ) == ISD :: AND && LHS -> hasOneUse ( ) && LHS -> getOperand ( 0 ) -> getOpcode ( ) == ARMISD :: CMOV && LHS -> getOperand ( 0 ) -> hasOneUse ( ) ) { auto * LHS00C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( 0 ) -> getOperand ( 0 ) ) ; auto * LHS01C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( 0 ) -> getOperand ( 1 ) ) ; auto * LHS1C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( 1 ) ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS00C && LHS00C -> getZExtValue ( ) == 0 ) && ( LHS01C && LHS01C -> getZExtValue ( ) == 1 ) && ( LHS1C && LHS1C -> getZExtValue ( ) == 1 ) && ( RHSC && RHSC -> getZExtValue ( ) == 0 ) ) { return DAG . getNode ( ARMISD :: BRCOND , dl , VT , Chain , BB , LHS -> getOperand ( 0 ) -> getOperand ( 2 ) , LHS -> getOperand ( 0 ) -> getOperand ( 3 ) , LHS -> getOperand ( 0 ) -> getOperand ( 4 ) ) ; } } return SDValue ( ) ; } </s>

PerformBRCONDCombine - Target-specific DAG combining for ARMISD : :BRCOND .


<s> bool Thumb1FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; return true ; } </s>


<s> unsigned X86TTI :: getNumberOfRegisters ( bool Vector ) const { if ( Vector && ! ST -> hasSSE1 ( ) ) return 0 ; if ( ST -> is64Bit ( ) ) { if ( Vector && ST -> hasAVX512 ( ) ) return 32 ; return 16 ; } return 8 ; } </s>


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! DefMI -> getParent ( ) ) return Latency ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } else if ( Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSFRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && Subtarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } if ( ! R . second && StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) { R . first = PPC :: CR0 ; R . second = & PPC :: CRRCRegClass ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> static void pop ( struct unw_state_record * sr ) { struct unw_reg_state * rs = sr -> curr . next ; if ( ! rs ) abort ( ) ; memcpy ( & sr -> curr , rs , sizeof ( * rs ) ) ; free_reg_state ( rs ) ; } </s>

Output RTL to pop register RN from the stack .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget -> isABI_N64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> TargetTransformInfo ARMBaseTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( ARMTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool X86TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { for ( unsigned i = 0 , e = LegalFPImmediates . size ( ) ; i != e ; ++ i ) { if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"SystemZ Local Dynamic TLS Access Clean-up"

getPassName - Return a nice clean name for a pass .


<s> rtx ix86_expand_adjust_ufix_to_sfix_si ( rtx val , rtx * xorp ) { REAL_VALUE_TYPE TWO31r ; rtx two31r , tmp [ 4 ] ; machine_mode mode = GET_MODE ( val ) ; machine_mode scalarmode = GET_MODE_INNER ( mode ) ; machine_mode intmode = GET_MODE_SIZE ( mode ) == 32 ? V8SImode : V4SImode ; rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = 0 ; i < 3 ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , 1 , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ 3 ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ 0 ] , two31r , val , tmp [ 3 ] ) ) ; tmp [ 1 ] = expand_simple_binop ( mode , AND , tmp [ 0 ] , two31r , tmp [ 1 ] , 0 , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ 0 ] ) , GEN_INT ( 31 ) , NULL_RTX , 0 , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( HOST_WIDE_INT_1U << 31 ) ; two31 = ix86_build_const_vector ( intmode , 1 , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [ 0 ] ) , two31 , NULL_RTX , 0 , OPTAB_DIRECT ) ; } return expand_simple_binop ( mode , MINUS , val , tmp [ 1 ] , tmp [ 2 ] , 0 , OPTAB_DIRECT ) ; } </s>

Adjust a V * SFmode/V * DFmode value VAL so that * sfix_trunc * resp . fix_trunc * pattern can be used on it instead of fixuns_trunc * . This is done by doing just signed conversion if < 0x1p31 , and otherwise by subtracting 0x1p31 first and xoring in 0x80000000 from * XORP afterwards .


<s> unsigned SparcMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , ( MCFixupKind ) Sparc :: fixup_sparc_br22 ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( SDValue ( N , 0 ) , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s> static tree ix86_vectorize_builtin_gather ( const_tree mem_vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX2 ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( mem_vectype ) ) { case V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DF : IX86_BUILTIN_GATHER3DIV2DF ; else code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF ; break ; case V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DF : IX86_BUILTIN_GATHER3DIV4DF ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF ; break ; case V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DI : IX86_BUILTIN_GATHER3DIV2DI ; else code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI ; break ; case V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DI : IX86_BUILTIN_GATHER3DIV4DI ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI ; break ; case V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SF : IX86_BUILTIN_GATHER3DIV4SF ; else code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF ; break ; case V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SF : IX86_BUILTIN_GATHER3ALTDIV8SF ; else code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF ; break ; case V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SI : IX86_BUILTIN_GATHER3DIV4SI ; else code = si ? IX86_BUILTIN_GATHERSIV4SI : IX86_BUILTIN_GATHERDIV4SI ; break ; case V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SI : IX86_BUILTIN_GATHER3ALTDIV8SI ; else code = si ? IX86_BUILTIN_GATHERSIV8SI : IX86_BUILTIN_GATHERALTDIV8SI ; break ; case V8DFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DF : IX86_BUILTIN_GATHER3DIV8DF ; else return NULL_TREE ; break ; case V8DImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DI : IX86_BUILTIN_GATHER3DIV8DI ; else return NULL_TREE ; break ; case V16SFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SF : IX86_BUILTIN_GATHER3ALTDIV16SF ; else return NULL_TREE ; break ; case V16SImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SI : IX86_BUILTIN_GATHER3ALTDIV16SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return ix86_get_builtin ( code ) ; } </s>

Returns a decl of a function that implements gather load with memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE . Return NULL_TREE if it is not available .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"lowerToVVP called for unexpected SDNode."


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
StringRef
Mnemonic
;
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> static bool rs6000_reg_live_or_pic_offset_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || get_pool_size ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ; } return ( ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) ) && ! call_used_regs [ reg ] ) ; } </s>

Determine whether the gp REG is really used .