<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 WinAlloca Expander"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool mips_split_move_insn_p ( rtx dest , rtx src , rtx insn ) { return mips_split_move_p ( dest , src , mips_insn_split_type ( insn ) ) ; } </s>

Return true if a move from SRC to DEST in INSN should be split .


<s> inline bool bundle_state_hasher :: equal ( const value_type * state1 , const compare_type * state2 ) { return ( state1 -> insn_num == state2 -> insn_num && memcmp ( state1 -> dfa_state , state2 -> dfa_state , dfa_state_size ) == 0 ) ; } </s>


<s> static reg_class_t aarch64_ira_change_pseudo_allocno_class ( int regno , reg_class_t allocno_class , reg_class_t best_class ) { machine_mode mode ; if ( ! reg_class_subset_p ( GENERAL_REGS , allocno_class ) || ! reg_class_subset_p ( FP_REGS , allocno_class ) ) return allocno_class ; if ( ! reg_class_subset_p ( GENERAL_REGS , best_class ) || ! reg_class_subset_p ( FP_REGS , best_class ) ) return best_class ; mode = PSEUDO_REGNO_MODE ( regno ) ; return FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ? FP_REGS : GENERAL_REGS ; } </s>

Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS . The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have the same cost even if ALL_REGS has a much larger cost . ALL_REGS is also used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory cost ( in this case the best class is the lowest cost one ) . Using ALL_REGS irrespectively of its cost results in bad allocations with many redundant int < - > FP moves which are expensive on various cores . To avoid this we do n't allow ALL_REGS as the allocno class , but force a decision between FP_REGS and GENERAL_REGS . We use the allocno class if it is n't ALL_REGS . Similarly , use the best class if it is n't ALL_REGS . Otherwise set the allocno class depending on the mode . The result of this is that it is no longer inefficient to have a higher memory move cost than the register move cost .


Given the pattern ( X & ( C l > > / < < Y ) ) ==/ ! = 0 return true if it should be transformed into : ( ( X < < /l > > Y ) & C ) ==/ ! = 0 WARNING : if ' X ' is a constant , the fold may deadlock ! FIXME : we could avoid passing XC , but we ca n't use isConstOrConstSplat ( ) here because it can end up being not linked in .


<s> static void sparc32_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , 10 , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x03000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , 10 , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x05000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x81c06000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , cxt , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x8410a000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_insn ( gen_flush ( SImode , validize_mem ( adjust_address ( m_tramp , SImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 && sparc_cpu != PROCESSOR_NIAGARA7 && sparc_cpu != PROCESSOR_M8 ) emit_insn ( gen_flush ( SImode , validize_mem ( adjust_address ( m_tramp , SImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . This takes 16 insns : 2 shifts & 2 ands ( to split up addresses ) , 4 sethi ( to load in opcodes ) , 4 iors ( to merge address and opcodes ) , and 4 writes ( to store insns ) . This is a bit excessive . Perhaps a different mechanism would be better here . Emit enough FLUSH insns to synchronize the data and instruction caches .


<s> unsigned getCPUDirective ( ) const { return CPUDirective ; } </s>

getCPUDirective - Returns the -m directive specified for the cpu .


<s> int first_fp_reg_to_save ( ) { int first_reg ; for ( first_reg = 14 + 32 ; first_reg <= 63 ; first_reg ++ ) if ( regs_ever_live [ first_reg ] ) break ; return first_reg ; } </s>


"extern const void *const __OFFLOAD_TABLE__;\n"

"extern const void *const __offload_image_intelmic_start;\n"

"extern const void *const __offload_image_intelmic_end;\n\n"

"static const void *const __offload_target_data[] = {\n"

"  &__offload_image_intelmic_start, &__offload_image_intelmic_end\n"

"void GOMP_offload_register (const void *, int, const void *);\n"

"void GOMP_offload_unregister (const void *, int, const void *);\n\n"

"  GOMP_offload_register (&__OFFLOAD_TABLE__, %d, __offload_target_data);\n"

"  GOMP_offload_unregister (&__OFFLOAD_TABLE__, %d, __offload_target_data);\n"

Generates object file with the host side descriptor .


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = "ve" ; ParseSubtargetFeatures ( CPUName , CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> static bool aarch64_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REGNUM ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


<s> static void build_vs_offset ( function_builder & b , const char * signature , const function_group_info & group , bool force_direct_overloads = false ) { build_32_64 ( b , signature , group , MODE_u32base_offset , MODE_u64base_offset , force_direct_overloads ) ; } </s>

Like build_v_base , but for functions that also take a scalar byte offset .


<s> unsigned int ix86_local_alignment ( tree exp , machine_mode mode , unsigned int align ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( ! TARGET_64BIT && align == 64 && ix86_preferred_stack_boundary < 64 && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = 32 ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , 16 ) && align < 128 ) return 128 ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> bool mips_legitimize_move ( enum machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { emit_move_insn ( dest , force_reg ( mode , src ) ) ; return true ; } if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD && REG_P ( src ) && MD_REG_P ( REGNO ( src ) ) && REG_P ( dest ) && GP_REG_P ( REGNO ( dest ) ) ) { int other_regno = REGNO ( src ) == HI_REGNUM ? LO_REGNUM : HI_REGNUM ; if ( GET_MODE_SIZE ( mode ) <= 4 ) emit_insn ( gen_mfhilo_si ( gen_rtx_REG ( SImode , REGNO ( dest ) ) , gen_rtx_REG ( SImode , REGNO ( src ) ) , gen_rtx_REG ( SImode , other_regno ) ) ) ; else emit_insn ( gen_mfhilo_di ( gen_rtx_REG ( DImode , REGNO ( dest ) ) , gen_rtx_REG ( DImode , REGNO ( src ) ) , gen_rtx_REG ( DImode , other_regno ) ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { mips_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false ; } </s>

If ( set DEST SRC ) is not a valid instruction , emit an equivalent sequence that is valid .


<s>
unsigned
SparcTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"i0"
,
SP
::
I0
)
.
Case
(
"i1"
,
SP
::
I1
)
.
Case
(
"i2"
,
SP
::
I2
)
.
Case
(
"i3"
,
SP
::
I3
)
.
Case
(
"i4"
,
SP
::
I4
)
.
Case
(
"i5"
,
SP
::
I5
)
.
Case
(
"i6"
,
SP
::
I6
)
.
Case
(
"i7"
,
SP
::
I7
)
.
Case
(
"o0"
,
SP
::
O0
)
.
Case
(
"o1"
,
SP
::
O1
)
.
Case
(
"o2"
,
SP
::
O2
)
.
Case
(
"o3"
,
SP
::
O3
)
.
Case
(
"o4"
,
SP
::
O4
)
.
Case
(
"o5"
,
SP
::
O5
)
.
Case
(
"o6"
,
SP
::
O6
)
.
Case
(
"o7"
,
SP
::
O7
)
.
Case
(
"l0"
,
SP
::
L0
)
.
Case
(
"l1"
,
SP
::
L1
)
.
Case
(
"l2"
,
SP
::
L2
)
.
Case
(
"l3"
,
SP
::
L3
)
.
Case
(
"l4"
,
SP
::
L4
)
.
Case
(
"l5"
,
SP
::
L5
)
.
Case
(
"l6"
,
SP
::
L6
)
.
Case
(
"l7"
,
SP
::
L7
)
.
Case
(
"g0"
,
SP
::
G0
)
.
Case
(
"g1"
,
SP
::
G1
)
.
Case
(
"g2"
,
SP
::
G2
)
.
Case
(
"g3"
,
SP
::
G3
)
.
Case
(
"g4"
,
SP
::
G4
)
.
Case
(
"g5"
,
SP
::
G5
)
.
Case
(
"g6"
,
SP
::
G6
)
.
Case
(
"g7"
,
SP
::
G7
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
while
(
!
vec_safe_is_empty
(
branch_islands
)
)
{
branch_island
*
bi
=
&
branch_islands
->
last
(
)
;
const
char
*
label
=
IDENTIFIER_POINTER
(
bi
->
label_name
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
bi
->
function_name
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
flag_pic
)
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\n\tlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
branch_islands
->
pop
(
)
;
}
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s>
void
mt_override_options
(
void
)
{
if
(
mt_cpu_string
!=
)
{
if
(
!
strcmp
(
mt_cpu_string
,
"ms1-64-001"
)
)
mt_cpu
=
PROCESSOR_MS1_64_001
;
else
if
(
!
strcmp
(
mt_cpu_string
,
"ms1-16-002"
)
)
mt_cpu
=
PROCESSOR_MS1_16_002
;
else
if
(
!
strcmp
(
mt_cpu_string
,
"ms1-16-003"
)
)
mt_cpu
=
PROCESSOR_MS1_16_003
;
else
if
(
!
strcmp
(
mt_cpu_string
,
"ms2"
)
)
mt_cpu
=
PROCESSOR_MS2
;
else
error
(
"bad value (%s) for -march= switch"
,
mt_cpu_string
)
;
}
else
mt_cpu
=
PROCESSOR_MS1_64_001
;
if
(
flag_exceptions
)
{
flag_omit_frame_pointer
=
0
;
flag_gcse
=
0
;
}
mt_flag_delayed_branch
=
flag_delayed_branch
;
flag_delayed_branch
=
0
;
init_machine_status
=
mt_init_machine_status
;
}
</s>


<s> void emitBasicBlockEnd ( const MachineBasicBlock & MBB ) override { AsmPrinter :: emitBasicBlockEnd ( MBB ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; } </s>

Targets can override this to emit stuff at the end of a basic block .


<s> static int first_altivec_reg_to_save ( ) { int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + 1 ; for ( i = FIRST_ALTIVEC_REGNO + 20 ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) break ; return i ; } </s>


<s> rtx legitimize_pic_address ( rtx orig , enum machine_mode mode ATTRIBUTE_UNUSED , rtx reg ) { if ( tls_symbolic_operand ( orig , Pmode ) ) return orig ; if ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( orig ) ) ) { if ( reg == 0 ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOTOFF2reg ( reg , orig ) ) ; return reg ; } else if ( GET_CODE ( orig ) == SYMBOL_REF ) { if ( reg == 0 ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOT2reg ( reg , orig ) ) ; return reg ; } return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> void vax_expand_prologue ( void ) { int regno , offset ; int mask = 0 ; HOST_WIDE_INT size ; rtx insn ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) mask |= 1 << regno ; insn = emit_insn ( gen_procedure_entry_mask ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; vax_add_reg_cfa_offset ( insn , 4 , arg_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , 8 , frame_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , 12 , pc_rtx ) ; offset = 16 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( mask & ( 1 << regno ) ) { vax_add_reg_cfa_offset ( insn , offset , gen_rtx_REG ( SImode , regno ) ) ; offset += 4 ; } add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , frame_pointer_rtx , offset ) ) ; size = get_frame_size ( ) ; size -= vax_starting_frame_offset ( ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ; emit_insn ( gen_blockage ( ) ) ; } </s>

Generate the assembly code for function entry . FILE is a stdio stream to output the code to . SIZE is an int : how many units of temporary storage to allocate . Refer to the array ` regs_ever_live ' to determine which registers to save ; ` regs_ever_live [ I ] ' is nonzero if register number I is ever used in the function . This function is responsible for knowing which registers should not be saved even if used .


<s> bool loongarch_eh_uses ( unsigned int regno ATTRIBUTE_UNUSED ) { return false ; } </s>


<s>
unsigned
FISCMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
if
(
Kind
==
MCExpr
::
Constant
)
return
cast
<
MCConstantExpr
>
(
Expr
)
->
getValue
(
)
;
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
unsigned
VKind
=
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
;
switch
(
VKind
)
{
case
MCSymbolRefExpr
::
VK_None
:
return
0
;
default
:
{
std
::
string
msg
=
"Unknown fixup kind! ("
+
std
::
to_string
(
VKind
)
+
")"
;
llvm_unreachable
(
msg
.
c_str
(
)
)
;
}
case
MCSymbolRefExpr
::
VK_FISC_Q1
:
FixupKind
=
FISC
::
fixup_fisc_mov_q1_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_Q2
:
FixupKind
=
FISC
::
fixup_fisc_mov_q2_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_Q3
:
FixupKind
=
FISC
::
fixup_fisc_mov_q3_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_Q4
:
FixupKind
=
FISC
::
fixup_fisc_mov_q4_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_CALL26
:
FixupKind
=
FISC
::
fixup_fisc_call26_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_CALL19
:
FixupKind
=
FISC
::
fixup_fisc_call19_pcrel
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_9BIT
:
FixupKind
=
FISC
::
fixup_fisc_9bit_address
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_6BIT
:
FixupKind
=
FISC
::
fixup_fisc_6bit_shamt
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_12BIT
:
FixupKind
=
FISC
::
fixup_fisc_12bit_imm
;
break
;
case
MCSymbolRefExpr
::
VK_FISC_MOVRZ
:
FixupKind
=
FISC
::
fixup_fisc_movrz_pcrel
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> static bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ) { tree fntype ; if ( decl ) fntype = TREE_TYPE ( decl ) ; else fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE && ! ( decl && decl == current_function_decl ) ) { function_args_iterator args_iter ; tree type ; int nvreg = 0 ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > 0 ) return false ; } if ( DEFAULT_ABI == ABI_DARWIN || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && decl && ! DECL_EXTERNAL ( decl ) && ( * targetm . binds_local_p ) ( decl ) ) || ( DEFAULT_ABI == ABI_V4 && ( ! TARGET_SECURE_PLT || ! flag_pic || ( decl && ( * targetm . binds_local_p ) ( decl ) ) ) ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> virtual unsigned getISAEncoding ( ) { if ( ! Subtarget -> isTargetDarwin ( ) ) return 0 ; return Subtarget -> isThumb ( ) ? llvm :: ARM :: DW_ISA_ARM_thumb : llvm :: ARM :: DW_ISA_ARM_arm ; } </s>

Get the value for DW_AT_APPLE_isa . Zero if no isa encoding specified .


<s> bool ix86_call_use_plt_p ( rtx call_op ) { if ( SYMBOL_REF_LOCAL_P ( call_op ) ) { if ( SYMBOL_REF_DECL ( call_op ) && TREE_CODE ( SYMBOL_REF_DECL ( call_op ) ) == FUNCTION_DECL ) { cgraph_node * node = cgraph_node :: get ( SYMBOL_REF_DECL ( call_op ) ) ; if ( node && node -> ifunc_resolver ) return true ; } return false ; } return true ; } </s>

Return true if the function is called via PLT .


<s> void ARMELFStreamer :: Reset ( ) { ExTab = nullptr ; FnStart = nullptr ; Personality = nullptr ; PersonalityIndex = ARM :: EHABI :: NUM_PERSONALITY_INDEX ; FPReg = ARM :: SP ; FPOffset = 0 ; SPOffset = 0 ; PendingOffset = 0 ; UsedFP = false ; CantUnwind = false ; Opcodes . clear ( ) ; UnwindOpAsm . Reset ( ) ; } </s>


<s> bool Thumb1FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { if ( ! needPopSpecialFixUp ( * MBB . getParent ( ) ) ) return true ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return emitPopSpecialFixUp ( * TmpMBB , false ) ; } </s>

Check whether or not the given MBB can be used as a epilogue for the target .


"attribute %<target%> argument not a string"

"malformed %<target()%> pragma or attribute"

"pragma or attribute %<target(\"%s\")%> is not valid"

"malformed %<target(\"%s\")%> pragma or attribute"

Parse the tree in ARGS that contains the target attribute information and update the global target options space . PRAGMA_OR_ATTR is a string to be used in error messages , specifying whether this is processing a target attribute or a target pragma .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( mode ) || FLOAT_MODE_P ( mode ) ) ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != CONST_INT ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> int rs6000_loop_align ( rtx label ) { basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops_log ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > 4 && ninsns <= 8 && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 || rs6000_cpu == PROCESSOR_POWER9 ) ) return 5 ; else return align_loops_log ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) override { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> bool CSKYAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case CSKY :: fixup_csky_got32 : case CSKY :: fixup_csky_got_imm18_scale4 : case CSKY :: fixup_csky_gotoff : case CSKY :: fixup_csky_gotpc : case CSKY :: fixup_csky_plt32 : case CSKY :: fixup_csky_plt_imm18_scale4 : case CSKY :: fixup_csky_doffset_imm18 : case CSKY :: fixup_csky_doffset_imm18_scale2 : case CSKY :: fixup_csky_doffset_imm18_scale4 : return true ; } return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static void sparc64_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , GEN_INT ( trunc_int_for_mode ( 0x83414000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , GEN_INT ( trunc_int_for_mode ( 0xca586018 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , GEN_INT ( trunc_int_for_mode ( 0x81c14000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , GEN_INT ( trunc_int_for_mode ( 0xca586010 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 16 ) , cxt ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 24 ) , fnaddr ) ; emit_insn ( gen_flushdi ( validize_mem ( adjust_address ( m_tramp , DImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 ) emit_insn ( gen_flushdi ( validize_mem ( adjust_address ( m_tramp , DImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

The 64 bit version is simpler because it makes more sense to load the values as `` immediate '' data out of the trampoline . It 's also easier since we can read the PC without clobbering a register .


<s> static enum mips_symbol_type mips_classify_symbolic_expression ( rtx x , enum mips_symbol_context context ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) return UNSPEC_ADDRESS_TYPE ( x ) ; return mips_classify_symbol ( x , context ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .


"\tARM::shouldCoalesce - Coalesced Weight: "


<s> const RegisterBankInfo * X86Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> void SystemZHazardRecognizer :: Reset ( ) { CurrGroupSize = 0 ; CurrGroupHas4RegOps = false ; clearProcResCounters ( ) ; GrpCount = 0 ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ; LLVM_DEBUG ( CurGroupDbg = "" ; ) ; } </s>


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool rs6000_aix_precompute_tls_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return tls_referenced_p ( x ) ; } </s>

Implement TARGET_PRECOMPUTE_TLS_P . On the AIX , TLS symbols are in the TOC , which is maintained in the constant pool . AIX TOC TLS symbols need to be pre-computed , but must be considered legitimate constants .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( new X86ExecutionDepsFix ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"operation not permitted on type %<bfloat16_t%>"

Return the diagnostic message string if the unary operation OP is not permitted on TYPE , NULL otherwise .


<s> static unsigned adjust_vectorization_cost ( enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info ) { if ( kind == scalar_stmt && stmt_info && stmt_info -> stmt && gimple_code ( stmt_info -> stmt ) == GIMPLE_ASSIGN ) { tree_code subcode = gimple_assign_rhs_code ( stmt_info -> stmt ) ; if ( subcode == COND_EXPR ) return 2 ; } return 0 ; } </s>

Adjust vectorization cost after calling rs6000_builtin_vectorization_cost . For some statement , we would like to further fine-grain tweak the cost on top of rs6000_builtin_vectorization_cost handling which does n't have any information on statement operation codes etc . One typical case here is COND_EXPR , it takes the same cost to simple FXU instruction when evaluating for scalar cost , but it should be priced more whatever transformed to either compare + branch or compare + isel instructions .


<s> static bool valid_perm_using_mode_p ( machine_mode vmode , struct expand_vec_perm_d * d ) { unsigned int i , j , chunk ; if ( GET_MODE_CLASS ( vmode ) != MODE_VECTOR_INT || GET_MODE_CLASS ( d -> vmode ) != MODE_VECTOR_INT || GET_MODE_SIZE ( vmode ) != GET_MODE_SIZE ( d -> vmode ) ) return false ; if ( GET_MODE_NUNITS ( vmode ) >= d -> nelt ) return true ; chunk = d -> nelt / GET_MODE_NUNITS ( vmode ) ; for ( i = 0 ; i < d -> nelt ; i += chunk ) if ( d -> perm [ i ] & ( chunk - 1 ) ) return false ; else for ( j = 1 ; j < chunk ; ++ j ) if ( d -> perm [ i ] + j != d -> perm [ i + j ] ) return false ; return true ; } </s>

Return true if permutation D can be performed as VMODE permutation instead .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'c' : break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
bool
NeedShadowCallStackProlog
=
false
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
,
NeedShadowCallStackProlog
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
if
(
NeedShadowCallStackProlog
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AArch64
::
STRXpost
)
)
.
addReg
(
AArch64
::
X18
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
X18
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MBB
.
addLiveIn
(
AArch64
::
X18
)
;
}
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
LLVM_DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
!
MRI
.
isReserved
(
Reg1
)
)
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
if
(
!
MRI
.
isReserved
(
Reg2
)
)
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static rtx gen_rx_popm_vector ( unsigned int low , unsigned int high ) { unsigned int i ; unsigned int count = ( high - low ) + 2 ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , ( count - 1 ) * UNITS_PER_WORD ) ) ; for ( i = 0 ; i < count - 1 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == 0 ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; return vector ; } </s>

Generate a PARALLEL which will satisfy the rx_load_multiple_vector predicate .


Subroutine of aarch64_sve_expand_vector_init . Works as follows : ( a ) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER . ( b ) Skip trailing elements from BUILDER , which are the same as element NELTS_REQD - 1 . ( c ) Insert earlier elements in reverse order in TARGET using insr .


<s> static tree aarch64_simd_builtin_type ( machine_mode mode , enum aarch64_type_qualifiers qualifiers ) { tree type = NULL_TREE ; if ( ( qualifiers & qualifier_pointer ) && VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( ( qualifiers & qualifier_poly ) || VECTOR_MODE_P ( mode ) ) type = aarch64_lookup_simd_type_in_table ( mode , qualifiers ) ; else type = aarch64_int_or_fp_type ( mode , qualifiers ) ; gcc_assert ( type != NULL_TREE ) ; if ( qualifiers & qualifier_const ) type = build_qualified_type ( type , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) type = build_pointer_type ( type ) ; return type ; } </s>

Return a type for an operand with specified mode and qualifiers .


<s> bool CheckReturn ( const SmallVectorImpl < ISD :: OutputArg > & ArgsFlags , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; return Return ; } </s>

CheckReturn - Analyze the return values of a function , returning true if the return can be performed without sret-demotion , and false otherwise .


<s> static void aarch64_pushwb_single_reg ( machine_mode mode , unsigned regno , HOST_WIDE_INT adjustment ) { rtx base_rtx = stack_pointer_rtx ; rtx insn , reg , mem ; reg = gen_rtx_REG ( mode , regno ) ; mem = gen_rtx_PRE_MODIFY ( Pmode , base_rtx , plus_constant ( Pmode , base_rtx , - adjustment ) ) ; mem = gen_rtx_MEM ( mode , mem ) ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push the register number REGNO of mode MODE to the stack with write-back adjusting the stack by ADJUSTMENT .


<s> void KudeyarInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; Opc = Kudeyar :: MOV_RR ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> static inline int extract_22 ( unsigned word ) { return sign_extend ( GET_FIELD ( word , 19 , 28 ) | GET_FIELD ( word , 29 , 29 ) << 10 | GET_FIELD ( word , 11 , 15 ) << 11 | GET_FIELD ( word , 6 , 10 ) << 16 | ( word & 0x1 ) << 21 , 22 ) ; } </s>

Extract a 22-bit signed constant from branch instructions .


<s> void aarch64_init_fcmla_laneq_builtins ( void ) { unsigned int i = 0 ; for ( i = 0 ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_type ( SImode , qualifier_lane_pair_index ) ; tree ftype = build_function_type_list ( argtype , argtype , argtype , quadtype , lanetype , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , d -> mode ) ; tree fndecl = aarch64_general_add_builtin ( d -> name , ftype , d -> fcode , attrs ) ; aarch64_builtin_decls [ d -> fcode ] = fndecl ; } } </s>

Due to the architecture not providing lane variant of the lane instructions for fcmla we ca n't use the standard simd builtin expansion code , but we still want the majority of the validation that would normally be done .


<s> const MCPhysReg * VERegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) . getCallingConv ( ) ) { default : return CSR_SaveList ; case CallingConv :: PreserveAll : return CSR_preserve_all_SaveList ; } } </s>


<s> int loongarch_load_store_insns ( rtx mem , rtx_insn * insn ) { machine_mode mode ; bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ; if ( might_split_p ) { set = single_set ( insn ) ; if ( set && ! loongarch_split_move_insn_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ; } return loongarch_address_insns ( XEXP ( mem , 0 ) , mode , might_split_p ) ; } </s>

Return the number of instructions needed to implement INSN , given that it loads from or stores to MEM .


Return true iff x is a uniform vector of floating-point constants , and the constant can be represented in quarter-precision form . Note , as aarch64_float_const_representable rejects both +0.0 and -0.0 , we will also reject +0.0 and -0.0 .


<s> unsigned getNumFixupKinds ( ) const override { return Cpu0 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static rtx or1k_legitimize_address ( rtx x , rtx , machine_mode ) { return or1k_legitimize_address_1 ( x , NULL_RTX ) ; } </s>

Worker for TARGET_LEGITIMIZE_ADDRESS . This delegates implementation to or1k_legitimize_address_1 .


<s> static bool isReturnBlock ( const MachineBasicBlock * MBB ) { for ( auto MI = MBB -> begin ( ) , ME = MBB -> end ( ) ; MI != ME ; MI ++ ) if ( MI -> isReturn ( ) ) return true ; return false ; } </s>

Convenience function that returns true if the block ends in a return instruction .


<s> bool bpick_ra_rb_dep_p ( rtx insn , rtx def_reg ) { rtx ior_rtx = SET_SRC ( PATTERN ( insn ) ) ; rtx and1_rtx = XEXP ( ior_rtx , 0 ) ; rtx and2_rtx = XEXP ( ior_rtx , 1 ) ; rtx reg1_0 = XEXP ( and1_rtx , 0 ) ; rtx reg1_1 = XEXP ( and1_rtx , 1 ) ; rtx reg2_0 = XEXP ( and2_rtx , 0 ) ; rtx reg2_1 = XEXP ( and2_rtx , 1 ) ; if ( GET_CODE ( reg1_0 ) == NOT ) { if ( rtx_equal_p ( reg1_0 , reg2_0 ) ) return reg_overlap_p ( def_reg , reg1_1 ) || reg_overlap_p ( def_reg , reg2_1 ) ; if ( rtx_equal_p ( reg1_0 , reg2_1 ) ) return reg_overlap_p ( def_reg , reg1_1 ) || reg_overlap_p ( def_reg , reg2_0 ) ; } if ( GET_CODE ( reg1_1 ) == NOT ) { if ( rtx_equal_p ( reg1_1 , reg2_0 ) ) return reg_overlap_p ( def_reg , reg1_0 ) || reg_overlap_p ( def_reg , reg2_1 ) ; if ( rtx_equal_p ( reg1_1 , reg2_1 ) ) return reg_overlap_p ( def_reg , reg1_0 ) || reg_overlap_p ( def_reg , reg2_0 ) ; } if ( GET_CODE ( reg2_0 ) == NOT ) { if ( rtx_equal_p ( reg2_0 , reg1_0 ) ) return reg_overlap_p ( def_reg , reg2_1 ) || reg_overlap_p ( def_reg , reg1_1 ) ; if ( rtx_equal_p ( reg2_0 , reg1_1 ) ) return reg_overlap_p ( def_reg , reg2_1 ) || reg_overlap_p ( def_reg , reg1_0 ) ; } if ( GET_CODE ( reg2_1 ) == NOT ) { if ( rtx_equal_p ( reg2_1 , reg1_0 ) ) return reg_overlap_p ( def_reg , reg2_0 ) || reg_overlap_p ( def_reg , reg1_1 ) ; if ( rtx_equal_p ( reg2_1 , reg1_1 ) ) return reg_overlap_p ( def_reg , reg2_0 ) || reg_overlap_p ( def_reg , reg1_0 ) ; } gcc_unreachable ( ) ; } </s>

Check if INSN is a bpick insn consuming DEF_REG .


<s> void expand_fusion_gpr_load ( rtx * operands ) { rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == ZERO_EXTEND || ( TARGET_P8_FUSION_SIGN && GET_CODE ( orig_mem ) == SIGN_EXTEND ) ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( ZERO_EXTEND , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_GPR ) ; emit_insn ( gen_rtx_SET ( target , new_mem ) ) ; if ( extend == SIGN_EXTEND ) { int sub_off = ( ( BYTES_BIG_ENDIAN ) ? GET_MODE_SIZE ( extend_mode ) - GET_MODE_SIZE ( target_mode ) : 0 ) ; rtx sign_reg = simplify_subreg ( target_mode , target , extend_mode , sub_off ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_SIGN_EXTEND ( extend_mode , sign_reg ) ) ) ; } return ; } </s>

During the peephole2 pass , adjust and expand the insns for a load fusion sequence . We adjust the addis register to use the target register . If the load sign extends , we adjust the code to do the zero extending load , and an explicit sign extension later since the fusion only covers zero extending loads . The operands are : operands [ 0 ] register set with addis ( to be replaced with target ) operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] .


runOnMachineFunction - Emit the function body .


<s>
static
void
rx_print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
addr
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
case
PRE_DEC
:
fprintf
(
file
,
"[-"
)
;
rx_print_operand
(
file
,
XEXP
(
addr
,
0
)
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
case
POST_INC
:
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
XEXP
(
addr
,
0
)
,
0
)
;
fprintf
(
file
,
"+]"
)
;
break
;
case
PLUS
:
{
rtx
arg1
=
XEXP
(
addr
,
0
)
;
rtx
arg2
=
XEXP
(
addr
,
1
)
;
rtx
base
,
index
;
if
(
REG_P
(
arg1
)
&&
RTX_OK_FOR_BASE
(
arg1
,
true
)
)
base
=
arg1
,
index
=
arg2
;
else
if
(
REG_P
(
arg2
)
&&
RTX_OK_FOR_BASE
(
arg2
,
true
)
)
base
=
arg2
,
index
=
arg1
;
else
{
rx_print_operand
(
file
,
arg1
,
0
)
;
fprintf
(
file
,
" + "
)
;
rx_print_operand
(
file
,
arg2
,
0
)
;
break
;
}
if
(
REG_P
(
index
)
||
GET_CODE
(
index
)
==
MULT
)
{
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
index
,
'A'
)
;
fprintf
(
file
,
","
)
;
}
else
{
rx_print_operand
(
file
,
index
,
'A'
)
;
fprintf
(
file
,
"["
)
;
}
rx_print_operand
(
file
,
base
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
}
case
CONST
:
if
(
GET_CODE
(
XEXP
(
addr
,
0
)
)
==
UNSPEC
)
{
addr
=
XEXP
(
addr
,
0
)
;
gcc_assert
(
XINT
(
addr
,
1
)
==
UNSPEC_CONST
)
;
case
UNSPEC
:
addr
=
XVECEXP
(
addr
,
0
,
0
)
;
gcc_assert
(
CONST_INT_P
(
addr
)
)
;
}
case
LABEL_REF
:
case
SYMBOL_REF
:
fprintf
(
file
,
"#"
)
;
default
:
output_addr_const
(
file
,
addr
)
;
break
;
}
}
</s>

A C compound statement to output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .


<s> virtual const SystemZRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool needAddressOf ( ) const override { return AddressOf ; } </s>

needAddressOf - Do we need to emit code to get the address of the variable/label ? Only valid when parsing MS-style inline assembly .


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , int val ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits ) ; int i ; for ( i = 0 ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( val ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; } </s>


<s> static Mfix * create_csky_fix_barrier ( Mfix * fix , Mfix * fix_next , HOST_WIDE_INT max_address ) { rtx_barrier * barrier ; rtx_insn * from = ( fix ? fix -> insn : get_insns ( ) ) ; rtx_insn * selected = NULL ; int selected_cost ; HOST_WIDE_INT selected_address = 0 ; Mfix * new_fix ; HOST_WIDE_INT count = ( fix ? fix -> address : 0 ) ; HOST_WIDE_INT max_count = max_address ; rtx_code_label * label = gen_label_rtx ( ) ; selected_cost = get_csky_barrier_cost ( from ) ; while ( from && count < max_count ) { int new_cost ; rtx_jump_table_data * table ; count += get_attr_length ( from ) ; if ( tablejump_p ( from , NULL , & table ) ) { count += get_csky_jump_table_size ( table ) ; new_cost = get_csky_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = table ; selected_cost = new_cost ; selected_address = count ; } from = NEXT_INSN ( table ) ; continue ; } new_cost = get_csky_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = from ; selected_cost = new_cost ; selected_address = count ; } from = NEXT_INSN ( from ) ; } gcc_assert ( selected ) ; from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; if ( fix ) { new_fix -> next = fix -> next ; fix -> next = new_fix ; } else new_fix -> next = fix_next ; return new_fix ; } </s>

Find the best place in the insn stream in the range ( FIX- > address , MAX_ADDRESS ) to forcibly insert a minipool barrier . Create the barrier by inserting a jump and add a new fix entry for it .


<s> static int moxie_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes_left , size ; if ( * cum >= 8 ) return 0 ; if ( moxie_pass_by_reference ( cum_v , arg ) ) size = 4 ; else if ( arg . type ) { if ( AGGREGATE_TYPE_P ( arg . type ) ) return 0 ; size = int_size_in_bytes ( arg . type ) ; } else size = GET_MODE_SIZE ( arg . mode ) ; bytes_left = ( 4 * 6 ) - ( ( * cum - 2 ) * 4 ) ; if ( size > bytes_left ) return bytes_left ; else return 0 ; } </s>

Some function arguments will only partially fit in the registers that hold arguments . Given a new arg , return the number of bytes that fit in argument passing registers .


<s> void arm_lang_object_attributes_init ( void ) { arm_lang_output_object_attributes_hook = arm_output_c_attributes ; } </s>

Setup so that common code calls arm_output_c_attributes .


<s> static bool nds32_warn_func_return ( tree decl ) { return ! nds32_naked_function_p ( decl ) ; } </s>

Determine whether we need to enable warning for function return check .


<s> static bool zero_all_mm_registers ( HARD_REG_SET need_zeroed_hardregs , unsigned int ret_mmx_regno ) { bool need_zero_all_mm = false ; for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( STACK_REGNO_P ( regno ) && TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { need_zero_all_mm = true ; break ; } if ( ! need_zero_all_mm ) return false ; rtx zero_mmx = NULL_RTX ; machine_mode mode = V4HImode ; for ( unsigned int regno = FIRST_MMX_REG ; regno <= LAST_MMX_REG ; regno ++ ) if ( regno != ret_mmx_regno ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( zero_mmx == NULL_RTX ) { zero_mmx = reg ; emit_insn ( gen_rtx_SET ( reg , CONST0_RTX ( mode ) ) ) ; } else emit_move_insn ( reg , zero_mmx ) ; } return true ; } </s>

When the routine exit in MMX mode , if any ST register needs to be zeroed , we should clear all MMX registers except the RET_MMX_REGNO that holds the return value .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static int sh_pr_n_sets ( void ) { return REG_N_SETS ( TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ; } </s>

For use by ALLOCATE_INITIAL_VALUE . Note that sh.md contains some 'special function ' patterns ( type sfunc ) that clobber pr , but that do not look like function calls to leaf_function_p . Hence we must do this extra check .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> void ix86_expand_xorsign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , vdest , op0 , op1 , mask , x , temp ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; if ( mode == HFmode ) vmode = V8HFmode ; else if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else gcc_unreachable ( ) ; temp = gen_reg_rtx ( vmode ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; op1 = lowpart_subreg ( vmode , force_reg ( mode , op1 ) , mode ) ; x = gen_rtx_AND ( vmode , op1 , mask ) ; emit_insn ( gen_rtx_SET ( temp , x ) ) ; op0 = lowpart_subreg ( vmode , force_reg ( mode , op0 ) , mode ) ; x = gen_rtx_XOR ( vmode , temp , op0 ) ; vdest = lowpart_subreg ( vmode , dest , mode ) ; if ( vdest == NULL_RTX ) vdest = gen_reg_rtx ( vmode ) ; else dest = NULL_RTX ; emit_insn ( gen_rtx_SET ( vdest , x ) ) ; if ( dest ) emit_move_insn ( dest , lowpart_subreg ( mode , vdest , vmode ) ) ; } </s>


<s> void ix86_bd_do_dispatch ( rtx_insn * insn , int mode ) { if ( mode == DISPATCH_INIT ) init_dispatch_sched ( ) ; else if ( mode == ADD_TO_DISPATCH_WINDOW ) add_to_dispatch_window ( insn ) ; } </s>

This routine is the driver of the dispatch scheduler .


<s> bool PPCFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnablePEVectorSpills || MFI . hasCalls ( ) || ! Subtarget . hasP9Vector ( ) ) return false ; BitVector BVAllocatable = TRI -> getAllocatableSet ( MF ) ; BitVector BVCalleeSaved ( TRI -> getNumRegs ( ) ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) BVCalleeSaved . set ( CSRegs [ i ] ) ; for ( unsigned Reg : BVAllocatable . set_bits ( ) ) { if ( BVCalleeSaved [ Reg ] || ! PPC :: VSRCRegClass . contains ( Reg ) || MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) BVAllocatable . reset ( Reg ) ; } bool AllSpilledToReg = true ; unsigned LastVSRUsedForSpill = 0 ; for ( auto & CS : CSI ) { if ( BVAllocatable . none ( ) ) return false ; unsigned Reg = CS . getReg ( ) ; if ( ! PPC :: G8RCRegClass . contains ( Reg ) ) { AllSpilledToReg = false ; continue ; } if ( LastVSRUsedForSpill != 0 ) { CS . setDstReg ( LastVSRUsedForSpill ) ; BVAllocatable . reset ( LastVSRUsedForSpill ) ; LastVSRUsedForSpill = 0 ; continue ; } unsigned VolatileVFReg = BVAllocatable . find_first ( ) ; if ( VolatileVFReg < BVAllocatable . size ( ) ) { CS . setDstReg ( VolatileVFReg ) ; LastVSRUsedForSpill = VolatileVFReg ; } else { AllSpilledToReg = false ; } } return AllSpilledToReg ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> int loongarch_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct loongarch_address_info addr ; int factor ; if ( ! loongarch_classify_address ( & addr , x , mode , false ) ) return 0 ; if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; else factor = 1 ; if ( loongarch_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : return factor ; case ADDRESS_REG_REG : return factor ; case ADDRESS_CONST_INT : return factor ; case ADDRESS_SYMBOLIC : return factor * loongarch_symbol_insns ( addr . symbol_type , mode ) ; } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at address X . Return 0 if X is n't valid for MODE . Assume that multiword moves may need to be split into word moves if MIGHT_SPLIT_P , otherwise assume that a single load or store is enough .


<s> void PPCVSXSwapRemoval :: initialize ( MachineFunction & MFParm ) { MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < PPCSubtarget > ( ) . getInstrInfo ( ) ; const int InitialVectorSize ( 256 ) ; SwapVector . clear ( ) ; SwapVector . reserve ( InitialVectorSize ) ; EC = new EquivalenceClasses < int > ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> virtual const MCObjectFormat & getObjectFormat ( ) const { return Format ; } </s>


<s> bool X86TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ; FeatureBitset RealCalleeBits = CalleeBits & ~ InlineFeatureIgnoreList ; if ( RealCallerBits == RealCalleeBits ) return true ; if ( ( RealCallerBits & RealCalleeBits ) != RealCalleeBits ) return false ; for ( const Instruction & I : instructions ( Callee ) ) { if ( const auto * CB = dyn_cast < CallBase > ( & I ) ) { SmallVector < Type * , 8 > Types ; for ( Value * Arg : CB -> args ( ) ) Types . push_back ( Arg -> getType ( ) ) ; if ( ! CB -> getType ( ) -> isVoidTy ( ) ) Types . push_back ( CB -> getType ( ) ) ; auto IsSimpleTy = [ ] ( Type * Ty ) { return ! Ty -> isVectorTy ( ) && ! Ty -> isAggregateType ( ) ; } ; if ( all_of ( Types , IsSimpleTy ) ) continue ; if ( Function * NestedCallee = CB -> getCalledFunction ( ) ) { if ( NestedCallee -> isIntrinsic ( ) ) continue ; if ( ! areTypesABICompatible ( Caller , NestedCallee , Types ) ) return false ; } else { return false ; } } } return true ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s>
void
ATTRIBUTE_UNUSED
ix86_debug_options
(
void
)
{
char
*
opts
=
ix86_target_string
(
ix86_isa_flags
,
target_flags
,
ix86_arch_string
,
ix86_tune_string
,
ix86_fpmath
,
true
)
;
if
(
opts
)
{
fprintf
(
stderr
,
"%s\n\n"
,
opts
)
;
free
(
opts
)
;
}
else
fputs
(
"<no options>\n\n"
,
stderr
)
;
return
;
}
</s>

Function that is callable from the debugger to print the current options .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( ( Encoding & DW_EH_PE_indirect ) && ( Encoding & DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> unsigned AArch64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return AArch64 :: X29 ; else return AArch64 :: XSP ; } </s>


"\n%s -G value = %d, Arch = %s, ISA = %d\n"


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> const TargetRegisterClass * AArch64RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & AArch64 :: GPR64spRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> void ARMPassConfig :: addCodeGenPrepare ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMCodeGenPreparePass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
char
*
aarch64_output_ptrue
(
machine_mode
mode
,
char
suffix
)
{
unsigned
int
nunits
;
static
char
buf
[
sizeof
(
"ptrue\t%0.N, vlNNNNN"
)
]
;
if
(
GET_MODE_NUNITS
(
mode
)
.
is_constant
(
&
nunits
)
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"ptrue\t%%0.%c, vl%d"
,
suffix
,
nunits
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"ptrue\t%%0.%c, all"
,
suffix
)
;
return
buf
;
}
</s>

Return the asm format for a PTRUE instruction whose destination has mode MODE . SUFFIX is the element size suffix .

aarch64
"ptrue\t%0.N, vlNNNNN"
"ptrue\t%%0.%c, vl%d"
"ptrue\t%%0.%c, all"


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , unsigned EncodingAlignment ) const { int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( 1 ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s>
static
int
rename_chain
(
tag_insn_info
*
insn_info
,
tag_map_t
&
tag_map
,
du_head_p
head
)
{
unsigned
dest_regno
=
head
->
regno
;
if
(
head
->
cannot_rename
||
head
->
renamed
)
return
1
;
HARD_REG_SET
unavailable
;
enum
reg_class
super_class
=
init_unavailable
(
insn_info
,
tag_map
,
head
,
&
unavailable
)
;
unsigned
new_regno
=
find_rename_reg
(
head
,
super_class
,
&
unavailable
,
dest_regno
,
false
)
;
if
(
new_regno
!=
dest_regno
&&
regrename_do_replace
(
head
,
new_regno
)
)
{
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
fprintf
(
dump_file
,
"\tInsn %d: Renamed %d to %d\n"
,
INSN_UID
(
insn_info
->
insn
)
,
dest_regno
,
new_regno
)
;
return
new_regno
;
}
return
1
;
}
</s>

Find a suitable and available register and rename the chain of occurrences of the register defined in the def/use chain headed by HEAD in which INSN exists . CUR_TAG , TAGS and TAG_MAP are used to determine which registers are unavailable due to a potential collision due to the rename . The routine returns the register number in case of a successful rename or -1 to indicate failure .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; Reserved . set ( ARM :: APSR_NZCV ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; TM = & TPC -> getTM < PPCTargetMachine > ( ) ; STI = TM -> getSubtargetImpl ( F ) ; TLI = STI -> getTargetLowering ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> rtx aarch64_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; int fcode = DECL_FUNCTION_CODE ( fndecl ) ; int icode ; rtx pat , op0 ; tree arg0 ; switch ( fcode ) { case AARCH64_BUILTIN_GET_FPCR : case AARCH64_BUILTIN_SET_FPCR : case AARCH64_BUILTIN_GET_FPSR : case AARCH64_BUILTIN_SET_FPSR : if ( ( fcode == AARCH64_BUILTIN_GET_FPCR ) || ( fcode == AARCH64_BUILTIN_GET_FPSR ) ) { icode = ( fcode == AARCH64_BUILTIN_GET_FPSR ) ? CODE_FOR_get_fpsr : CODE_FOR_get_fpcr ; target = gen_reg_rtx ( SImode ) ; pat = GEN_FCN ( icode ) ( target ) ; } else { target = NULL_RTX ; icode = ( fcode == AARCH64_BUILTIN_SET_FPSR ) ? CODE_FOR_set_fpsr : CODE_FOR_set_fpcr ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = force_reg ( SImode , expand_normal ( arg0 ) ) ; pat = GEN_FCN ( icode ) ( op0 ) ; } emit_insn ( pat ) ; return target ; } if ( fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX ) return aarch64_simd_expand_builtin ( fcode , exp , target ) ; else if ( fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX ) return aarch64_crc32_expand_builtin ( fcode , exp , target ) ; if ( fcode == AARCH64_BUILTIN_RSQRT_DF || fcode == AARCH64_BUILTIN_RSQRT_SF || fcode == AARCH64_BUILTIN_RSQRT_V2DF || fcode == AARCH64_BUILTIN_RSQRT_V2SF || fcode == AARCH64_BUILTIN_RSQRT_V4SF ) return aarch64_expand_builtin_rsqrt ( fcode , exp , target ) ; gcc_unreachable ( ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & F ) override { TM = & F . getTarget ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; if ( Changed ) F . getRegInfo ( ) . invalidateLiveness ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool offsettable_ok_by_alignment ( rtx op , HOST_WIDE_INT offset , machine_mode mode ) { tree decl , type ; unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( GET_CODE ( op ) != SYMBOL_REF ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == 0 ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == 0 ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > 32768 ) return false ; return dalign / BITS_PER_UNIT >= dsize ; } } else { type = TREE_TYPE ( decl ) ; dalign = TYPE_ALIGN ( type ) ; if ( CONSTANT_CLASS_P ( decl ) ) dalign = CONSTANT_ALIGNMENT ( decl , dalign ) ; else dalign = DATA_ALIGNMENT ( decl , dalign ) ; if ( dsize == 0 ) { if ( TREE_CODE ( decl ) == STRING_CST ) dsize = TREE_STRING_LENGTH ( decl ) ; else if ( TYPE_SIZE_UNIT ( type ) && tree_fits_uhwi_p ( TYPE_SIZE_UNIT ( type ) ) ) dsize = tree_to_uhwi ( TYPE_SIZE_UNIT ( type ) ) ; else return false ; if ( dsize > 32768 ) return false ; return dalign / BITS_PER_UNIT >= dsize ; } } mask = dalign / BITS_PER_UNIT - 1 ; lsb = offset & - offset ; mask &= lsb - 1 ; dalign = mask + 1 ; return dalign >= dsize ; } </s>

Return true if a MODE sized memory accesses to OP plus OFFSET is known to not straddle a 32k boundary .


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( SPE_HIGH_REGNO_P ( regno ) ) return regno - FIRST_SPE_HIGH_REGNO + 1200 ; if ( ( format == 0 && write_symbols != DWARF2_DEBUG ) || format == 2 ) return regno ; if ( regno <= 63 ) return regno ; if ( regno == LR_REGNO ) return 108 ; if ( regno == CTR_REGNO ) return 109 ; if ( format == 1 && regno == CR2_REGNO ) return 64 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 86 ; if ( regno == CA_REGNO ) return 101 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 1124 ; if ( regno == VRSAVE_REGNO ) return 356 ; if ( regno == VSCR_REGNO ) return 67 ; if ( regno == SPE_ACC_REGNO ) return 99 ; if ( regno == SPEFSCR_REGNO ) return 612 ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void LanaiTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( 0 , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == 0 ) { Result = DAG . getTargetConstant ( 0 , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < 16 > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= 31 ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < 32 > ( Val ) ) && ( ( Val & 0xffff ) == 0 ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - 33554432 ) && ( Val <= 33554431 ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; default : break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> void AArch64TargetELFStreamer :: emitDirectiveVariantPCS ( MCSymbol * Symbol ) { getStreamer ( ) . getAssembler ( ) . registerSymbol ( * Symbol ) ; cast < MCSymbolELF > ( Symbol ) -> setOther ( ELF :: STO_AARCH64_VARIANT_PCS ) ; } </s>

Callback used to implement the .variant_pcs directive .


<s>
void
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
override
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
Opcode
)
;
uint64_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
case
0
:
break
;
case
4
:
if
(
IsLittleEndian
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
break
;
case
8
:
if
(
IsLittleEndian
)
{
uint64_t
Swapped
=
(
Bits
<<
32
)
|
(
Bits
>>
32
)
;
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
Swapped
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint64_t
>
(
Bits
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid instruction size"
)
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

PowerPC
0
4
support::endian
support::little
support::endian
support::big
8
32
32
support::endian
support::little
support::endian
support::big
"Invalid instruction size"


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const MCPhysReg * RegList = ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>


<s>
void
X86AvoidSFBPass
::
buildCopy
(
MachineInstr
*
LoadInst
,
unsigned
NLoadOpcode
,
int64_t
LoadDisp
,
MachineInstr
*
StoreInst
,
unsigned
NStoreOpcode
,
int64_t
StoreDisp
,
unsigned
Size
,
int64_t
LMMOffset
,
int64_t
SMMOffset
)
{
MachineOperand
&
LoadBase
=
getBaseOperand
(
LoadInst
)
;
MachineOperand
&
StoreBase
=
getBaseOperand
(
StoreInst
)
;
MachineBasicBlock
*
MBB
=
LoadInst
->
getParent
(
)
;
MachineMemOperand
*
LMMO
=
*
LoadInst
->
memoperands_begin
(
)
;
MachineMemOperand
*
SMMO
=
*
StoreInst
->
memoperands_begin
(
)
;
Register
Reg1
=
MRI
->
createVirtualRegister
(
TII
->
getRegClass
(
TII
->
get
(
NLoadOpcode
)
,
0
,
TRI
,
*
(
MBB
->
getParent
(
)
)
)
)
;
MachineInstr
*
NewLoad
=
BuildMI
(
*
MBB
,
LoadInst
,
LoadInst
->
getDebugLoc
(
)
,
TII
->
get
(
NLoadOpcode
)
,
Reg1
)
.
add
(
LoadBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
LoadDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
LMMO
,
LMMOffset
,
Size
)
)
;
if
(
LoadBase
.
isReg
(
)
)
getBaseOperand
(
NewLoad
)
.
setIsKill
(
false
)
;
LLVM_DEBUG
(
NewLoad
->
dump
(
)
)
;
MachineInstr
*
StInst
=
StoreInst
;
auto
PrevInstrIt
=
skipDebugInstructionsBackward
(
std
::
prev
(
MachineBasicBlock
::
instr_iterator
(
StoreInst
)
)
,
MBB
->
instr_begin
(
)
)
;
if
(
PrevInstrIt
.
getNodePtr
(
)
==
LoadInst
)
StInst
=
LoadInst
;
MachineInstr
*
NewStore
=
BuildMI
(
*
MBB
,
StInst
,
StInst
->
getDebugLoc
(
)
,
TII
->
get
(
NStoreOpcode
)
)
.
add
(
StoreBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
StoreDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addReg
(
Reg1
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
SMMO
,
SMMOffset
,
Size
)
)
;
if
(
StoreBase
.
isReg
(
)
)
getBaseOperand
(
NewStore
)
.
setIsKill
(
false
)
;
MachineOperand
&
StoreSrcVReg
=
StoreInst
->
getOperand
(
X86
::
AddrNumOperands
)
;
assert
(
StoreSrcVReg
.
isReg
(
)
&&
"Expected virtual register"
)
;
NewStore
->
getOperand
(
X86
::
AddrNumOperands
)
.
setIsKill
(
StoreSrcVReg
.
isKill
(
)
)
;
LLVM_DEBUG
(
NewStore
->
dump
(
)
)
;
}
</s>


Value should be nonzero if functions must have frame pointers . Zero means the frame pointer need not be set up ( and parms may be accessed via the stack pointer ) in functions that seem suitable .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) == ARMISD :: VMOVRRD ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , 2 > Copies ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies . insert ( * UI ) ; } if ( Copies . size ( ) > 2 ) return false ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { SDValue UseChain = UI -> getOperand ( 0 ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = * UI ; else TCChain = UseChain ; } } else if ( Copy -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != ISD :: CopyToReg || ! Copy -> hasNUsesOfValue ( 1 , 0 ) ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else { return false ; } bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; if ( GET_CODE ( addr ) == CONST ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s>
static
void
output_indirect_thunk
(
unsigned
int
regno
)
{
char
indirectlabel1
[
32
]
;
char
indirectlabel2
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel1
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel2
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
fputs
(
"\tcall\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel2
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel1
)
;
fprintf
(
asm_out_file
,
"\tpause\n\tlfence\n"
)
;
fputs
(
"\tjmp\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel1
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel2
)
;
if
(
flag_asynchronous_unwind_tables
&&
dwarf2out_do_frame
(
)
)
{
if
(
!
dwarf2out_do_cfi_asm
(
)
)
{
dw_cfi_ref
xcfi
=
ggc_cleared_alloc
<
dw_cfi_node
>
(
)
;
xcfi
->
dw_cfi_opc
=
DW_CFA_advance_loc4
;
xcfi
->
dw_cfi_oprnd1
.
dw_cfi_addr
=
ggc_strdup
(
indirectlabel2
)
;
vec_safe_push
(
cfun
->
fde
->
dw_fde_cfi
,
xcfi
)
;
}
dw_cfi_ref
xcfi
=
ggc_cleared_alloc
<
dw_cfi_node
>
(
)
;
xcfi
->
dw_cfi_opc
=
DW_CFA_def_cfa_offset
;
xcfi
->
dw_cfi_oprnd1
.
dw_cfi_offset
=
2
*
UNITS_PER_WORD
;
vec_safe_push
(
cfun
->
fde
->
dw_fde_cfi
,
xcfi
)
;
dwarf2out_emit_cfi
(
xcfi
)
;
}
if
(
regno
!=
INVALID_REGNUM
)
{
rtx
xops
[
2
]
;
xops
[
0
]
=
gen_rtx_MEM
(
word_mode
,
stack_pointer_rtx
)
;
xops
[
1
]
=
gen_rtx_REG
(
word_mode
,
regno
)
;
output_asm_insn
(
"mov\t{%1, %0|%0, %1}"
,
xops
)
;
}
else
{
rtx
xops
[
2
]
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
plus_constant
(
Pmode
,
stack_pointer_rtx
,
UNITS_PER_WORD
)
;
output_asm_insn
(
"lea\t{%E1, %0|%0, %E1}"
,
xops
)
;
}
fputs
(
"\tret\n"
,
asm_out_file
)
;
if
(
(
ix86_harden_sls
&
harden_sls_return
)
)
fputs
(
"\tint3\n"
,
asm_out_file
)
;
}
</s>

Output a call and return thunk for indirect branch . If BND_P is true , the BND prefix is needed . If REGNO ! = -1 , the function address is in REGNO and the call and return thunk looks like : call L2 L1 : pause lfence jmp L1 L2 : mov % REG , ( % sp ) ret Otherwise , the function address is on the top of stack and the call and return thunk looks like : call L2 L1 : pause lfence jmp L1 L2 : lea WORD_SIZE ( % sp ) , % sp ret


<s> static rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( "no_split_stack" , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = 1 ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , 12 ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } return plus_constant ( Pmode , cfun -> machine -> split_stack_arg_pointer , FIRST_PARM_OFFSET ( current_function_decl ) ) ; } return virtual_incoming_args_rtx ; } </s>

Return the internal arg pointer used for function incoming arguments . When -fsplit-stack , the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls and suchlike . We 'd really like to use a pseudo here for the internal arg pointer but data-flow analysis is not prepared to accept pseudos as live at the beginning of a function .


<s> bool AArch64InstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { if ( Opt == "no-aliases" ) { PrintAliases = false ; return true ; } return false ; } </s>

Customize the printer according to a command line option .


<s> unsigned PPCTTI :: getNumberOfRegisters ( bool Vector ) const { if ( Vector && ! ST -> hasAltivec ( ) ) return 0 ; return ST -> hasVSX ( ) ? 64 : 32 ; } </s>


"Disqualifying LR because GPR0 is live "


<s>
static
int
getMemScale
(
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
STRBBui
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
STRHHui
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> Register X86FrameLowering :: getInitialCFARegister ( const MachineFunction & MF ) const { return TRI -> getDwarfRegNum ( StackPtr , true ) ; } </s>


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new X86PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"Only Linux target is expected to contain LOAD_STACK_GUARD"

This function is called for all pseudo instructions that remain after register allocation .


<s> static int find_gr_spill ( enum ia64_frame_regs r , int try_locals ) { int regno ; if ( emitted_frame_related_regs [ r ] != 0 ) { regno = emitted_frame_related_regs [ r ] ; if ( regno >= LOC_REG ( 0 ) && regno < LOC_REG ( 80 - frame_pointer_needed ) && current_frame_info . n_local_regs < regno - LOC_REG ( 0 ) + 1 ) current_frame_info . n_local_regs = regno - LOC_REG ( 0 ) + 1 ; else if ( crtl -> is_leaf && regno >= GR_REG ( 1 ) && regno <= GR_REG ( 31 ) ) current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } if ( crtl -> is_leaf ) { for ( regno = GR_REG ( 1 ) ; regno <= GR_REG ( 31 ) ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_used_or_fixed_reg_p ( regno ) && ! fixed_regs [ regno ] && ! global_regs [ regno ] && ( ( current_frame_info . gr_used_mask >> regno ) & 1 ) == 0 && ! is_emitted ( regno ) ) { current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } } if ( try_locals ) { regno = current_frame_info . n_local_regs ; while ( regno < ( 80 - frame_pointer_needed ) ) if ( ! is_emitted ( LOC_REG ( regno ++ ) ) ) { current_frame_info . n_local_regs = regno ; return LOC_REG ( regno - 1 ) ; } } return 0 ; } </s>

Helper function for ia64_compute_frame_size : find an appropriate general register to spill some special register to . SPECIAL_SPILL_MASK contains bits in GR0 to GR31 that have already been allocated by this routine . TRY_LOCALS is true if we should attempt to locate a local regnum .


"inconsistent dll linkage for %q+D, dllexport assumed"

Mark a DECL as being dllexport 'd . Note that we override the previous setting ( e.g . : dllimport ) .


<s> bool umips_12bit_offset_address_p ( rtx x , machine_mode mode ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && UMIPS_12BIT_OFFSET_P ( INTVAL ( addr . offset ) ) ) ; } </s>

Return true if X is a legitimate address with a 12-bit offset . MODE is the mode of the value being accessed .


<s> static void arm_output_mi_thunk ( FILE * file , tree thunk , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk ) ) ; assemble_start_function ( thunk , fnname ) ; if ( TARGET_32BIT ) arm32_output_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; else arm_thumb1_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; assemble_end_function ( thunk , fnname ) ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> unsigned SparcMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( 0 , MO . getExpr ( ) , ( MCFixupKind ) Sparc :: fixup_sparc_br22 ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


"Can only put epilog before 'retl' instruction!"


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
bool
ARMCodeGenPrepare
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
||
DisableCGP
)
return
false
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
return
false
;
const
TargetMachine
&
TM
=
TPC
->
getTM
<
TargetMachine
>
(
)
;
ST
=
&
TM
.
getSubtarget
<
ARMSubtarget
>
(
F
)
;
bool
MadeChange
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Running on "
<<
F
.
getName
(
)
<<
"\n"
)
;
for
(
BasicBlock
&
BB
:
F
)
{
auto
&
Insts
=
BB
.
getInstList
(
)
;
for
(
auto
&
I
:
Insts
)
{
if
(
AllVisited
.
count
(
&
I
)
)
continue
;
if
(
isa
<
ICmpInst
>
(
I
)
)
{
auto
&
CI
=
cast
<
ICmpInst
>
(
I
)
;
if
(
CI
.
isSigned
(
)
||
!
isa
<
IntegerType
>
(
CI
.
getOperand
(
0
)
->
getType
(
)
)
)
continue
;
for
(
auto
&
Op
:
CI
.
operands
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
Op
)
)
MadeChange
|=
TryToPromote
(
I
)
;
}
}
}
Promoter
->
Cleanup
(
)
;
LLVM_DEBUG
(
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
{
dbgs
(
)
;
report_fatal_error
(
"Broken function after type promotion"
)
;
}
)
;
}
if
(
MadeChange
)
LLVM_DEBUG
(
dbgs
(
)
<<
"After ARMCodeGenPrepare: "
<<
F
<<
"\n"
)
;
return
MadeChange
;
}
</s>

ARM
ARM
ARM
"ARM CGP: Running on "
"\n"
0
"Broken function after type promotion"
"After ARMCodeGenPrepare: "
"\n"


<s> static bool is_microcoded_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_tune == PROCESSOR_CELL ) return get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ; if ( rs6000_sched_groups && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_update ( insn ) == UPDATE_YES && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) || ( ( type == TYPE_LOAD || type == TYPE_STORE ) && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) || type == TYPE_MFCR ) return true ; } return false ; } </s>

The function returns a true if INSN is microcoded . Return false otherwise .


<s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_READ_FPCR ) return true ; return flags & ( CP_READ_MEMORY | CP_READ_FFR ) ; } </s>

Return true if calls to the function could read some form of global state .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
assert
(
MIa
&&
MIa
->
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
&&
MIb
->
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static X86Operand CreateReg ( unsigned RegNo ) { X86Operand Res ; Res . Kind = Register ; Res . Reg . RegNo = RegNo ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


A subroutine of expand_vec_perm_even_odd_1 . Implement extract-even and extract-odd permutations of two V32QImode and V16QImode operand with two vpshufb insns , vpor and vpermq . We should have already failed all two or three instruction sequences .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> TargetIRAnalysis ARMBaseTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( ARMTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


"  rs6000_builtin_decls[(int)RS6000_BIF_%s] = t\n"

"                            NULL, NULL_TREE);\n"

Write code to initialize the built-in function table .

"                            NULL, NULL_TREE);\n"


<s> const PPCRegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void mmix_setup_frame_addresses ( void ) { } </s>


<s> int is_called_in_ARM_mode ( tree func ) { gcc_assert ( TREE_CODE ( func ) == FUNCTION_DECL ) ; if ( TARGET_CALLEE_INTERWORKING && TREE_PUBLIC ( func ) ) return TRUE ; return lookup_attribute ( "interfacearm" , DECL_ATTRIBUTES ( func ) ) != NULL_TREE ; return FALSE ; } </s>

Return non-zero if FUNC must be entered in ARM mode .


<s> static int m16_check_op ( rtx op , int low , int high , int mask ) { return ( GET_CODE ( op ) == CONST_INT && INTVAL ( op ) >= low && INTVAL ( op ) <= high && ( INTVAL ( op ) & mask ) == 0 ) ; } </s>

We need a lot of little routines to check constant values on the mips16 . These are used to figure out how long the instruction will be . It would be much better to do this using constraints , but there are n't nearly enough letters available .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( Triple ( TT ) . isOSBinFormatMachO ( ) ? "e-m:o-i64:64-i128:128-n32:64-S128" : ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> bool X86TargetLowering :: isSplatValueForTargetNode ( SDValue Op , const APInt & DemandedElts , APInt & UndefElts , unsigned Depth ) const { unsigned NumElts = DemandedElts . getBitWidth ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case X86ISD :: VBROADCAST : case X86ISD :: VBROADCAST_LOAD : UndefElts = APInt :: getNullValue ( NumElts ) ; return true ; } return TargetLowering :: isSplatValueForTargetNode ( Op , DemandedElts , UndefElts , Depth ) ; } </s>

Return true if vector Op has the same value across all DemandedElts , indicating any elements which may be undef in the output UndefElts .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 Atom LEA Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> void AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && ( TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA53 ( ) || TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA57 ( ) ) && usingDefaultRegAlloc ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .