<s> const SparcSubtarget * SparcTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SparcSubtarget > ( TargetTriple , CPU , FS , * this , this -> is64Bit ) ; } return I . get ( ) ; } </s>

Sparc Sparc Sparc "target-cpu" "target-features" "use-soft-float" "+soft-float" ",+soft-float" Sparc


"value of %<-mfixed-range%> must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> static bool aarch64_evpc_sve_tbl ( struct expand_vec_perm_d * d ) { unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = mode_for_int_vector ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; aarch64_expand_sve_vec_perm ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

Try to implement D using an SVE TBL instruction .


<s> bool X86InstrInfo :: isUnconditionalTailCall ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : return true ; default : return false ; } } </s>

Returns true if MI is an unconditional tail call .


Map a target register to an equivalent SEH register number .


<s> static bool ia64_cannot_force_const_mem ( rtx x ) { return tls_symbolic_operand_type ( x ) != 0 ; } </s>

Do n't allow TLS addresses to get spilled to memory .


<s> BitVector CSKYRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const CSKYFrameLowering * TFI = getFrameLowering ( MF ) ; const CSKYSubtarget & STI = MF . getSubtarget < CSKYSubtarget > ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , CSKY :: R7 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , CSKY :: R8 ) ; if ( ! STI . hasE2 ( ) ) { for ( unsigned i = 0 ; i < 6 ; i ++ ) markSuperRegs ( Reserved , CSKY :: R8 + i ) ; } markSuperRegs ( Reserved , CSKY :: R14 ) ; markSuperRegs ( Reserved , CSKY :: R15 ) ; if ( ! STI . hasHighRegisters ( ) ) { for ( unsigned i = 0 ; i < 10 ; i ++ ) markSuperRegs ( Reserved , CSKY :: R16 + i ) ; } markSuperRegs ( Reserved , CSKY :: R26 ) ; markSuperRegs ( Reserved , CSKY :: R27 ) ; markSuperRegs ( Reserved , CSKY :: R28 ) ; markSuperRegs ( Reserved , CSKY :: R29 ) ; markSuperRegs ( Reserved , CSKY :: R30 ) ; markSuperRegs ( Reserved , CSKY :: R31 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AArch64TargetLowering :: useLoadStackGuardNode ( ) const { if ( Subtarget -> isTargetAndroid ( ) || Subtarget -> isTargetFuchsia ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; if ( first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != 0 ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) && rs6000_reg_live_or_pic_offset_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM ; if ( flag_pic && crtl -> uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


"getMemOperandWithOffset only supports base "

Return true if get the base operand , byte offset of an instruction and the memory width .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"PowerPC QPX Load Splat Simplification"
;
}
</s>

getPassName - Return a nice clean name for a pass .

PowerPC
"PowerPC QPX Load Splat Simplification"


"FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( ! Result ) return false ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> tree ix86_builtin_decl ( unsigned code , bool ) { if ( code >= IX86_BUILTIN_MAX ) return error_mark_node ; return ix86_builtins [ code ] ; } </s>


<s> Align X86TargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { if ( ML -> isInnermost ( ) && ExperimentalPrefInnermostLoopAlignment . getNumOccurrences ( ) ) return Align ( 1ULL << ExperimentalPrefInnermostLoopAlignment ) ; return TargetLowering :: getPrefLoopAlignment ( ) ; } </s>


<s> static bool unsafe_rename_p ( unsigned regno ) { if ( regno <= R8_REGNUM || ( regno >= V0_REGNUM && regno < V8_REGNUM ) ) return true ; switch ( regno ) { case LR_REGNUM : case HARD_FRAME_POINTER_REGNUM : case FRAME_POINTER_REGNUM : case STACK_POINTER_REGNUM : return true ; } return false ; } </s>

Return true if REGNO is not safe to rename .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> void PPCPassConfig :: addMachineSSAOptimization ( ) { if ( EnableBranchCoalescing && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBranchCoalescingPass ( ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( createPPCVSXSwapRemovalPass ( ) ) ; if ( ! DisableMIPeephole ) { addPass ( createPPCMIPeepholePass ( ) ) ; addPass ( & DeadMachineInstructionElimID ) ; } } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_ZQ
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
case
InlineAsm
::
Constraint_ZR
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
case
InlineAsm
::
Constraint_ZS
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_p
:
case
InlineAsm
::
Constraint_ZT
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
const
TargetRegisterClass
*
TRC
=
Subtarget
->
getRegisterInfo
(
)
->
getPointerRegClass
(
*
MF
)
;
SDLoc
DL
(
Base
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
DL
,
MVT
::
i32
)
;
if
(
Base
.
getOpcode
(
)
!=
ISD
::
TargetFrameIndex
&&
Base
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Base
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Base
.
getValueType
(
)
,
Base
,
RC
)
,
0
)
;
}
if
(
Index
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Index
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Index
.
getValueType
(
)
,
Index
,
RC
)
,
0
)
;
}
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static rtx rs6000_delegitimize_address ( rtx orig_x ) { rtx x , y , offset ; orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , 1 ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , 1 ) ) ) { offset = XEXP ( y , 1 ) ; y = XEXP ( y , 0 ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , 0 , 0 ) ; if ( TARGET_XCOFF && GET_CODE ( y ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , 1 ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , 1 ) , 0 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP ( y , 0 , 0 ) ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> void AArch64PassConfig :: addPreGlobalInstructionSelect ( ) { if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) addPass ( new Localizer ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the ( global ) instruction selection .


<s> static DItype local_fixunssfdi ( SFtype original_a ) { DFtype a = original_a ; USItype hi , lo ; hi = a / ( ( ( UDItype ) 1 ) << ( sizeof ( SItype ) * 8 ) ) ; lo = ( a - ( ( DFtype ) hi ) * ( ( ( UDItype ) 1 ) << ( sizeof ( SItype ) * 8 ) ) ) ; return ( ( UDItype ) hi << ( sizeof ( SItype ) * 8 ) ) | lo ; } </s>

This version is needed to prevent recursion ; fixunssfdi in libgcc calls fixsfdi , which in turn calls calls fixunssfdi .


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
&&
GET_CODE
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
==
MEM
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx_insn
*
and_insn
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insn
)
;
if
(
and_operation
!=
0
)
{
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
and_base
=
XEXP
(
and_operation
,
0
)
;
rtx
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
and_base
)
,
new_reg
,
XEXP
(
and_operation
,
1
)
)
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> void SparcPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


runOnMachineFunction - Emit the function body .


<s>
bool
PPCInstrInfo
::
SubsumesPredicate
(
ArrayRef
<
MachineOperand
>
Pred1
,
ArrayRef
<
MachineOperand
>
Pred2
)
const
{
assert
(
Pred1
.
size
(
)
==
2
&&
"Invalid PPC first predicate"
)
;
assert
(
Pred2
.
size
(
)
==
2
&&
"Invalid PPC second predicate"
)
;
if
(
Pred1
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Pred1
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
return
false
;
if
(
Pred2
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Pred2
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
return
false
;
if
(
Pred1
[
1
]
.
getReg
(
)
!=
Pred2
[
1
]
.
getReg
(
)
)
return
false
;
PPC
::
Predicate
P1
=
(
PPC
::
Predicate
)
Pred1
[
0
]
.
getImm
(
)
;
PPC
::
Predicate
P2
=
(
PPC
::
Predicate
)
Pred2
[
0
]
.
getImm
(
)
;
if
(
P1
==
P2
)
return
true
;
if
(
P1
==
PPC
::
PRED_LE
&&
(
P2
==
PPC
::
PRED_LT
||
P2
==
PPC
::
PRED_EQ
)
)
return
true
;
if
(
P1
==
PPC
::
PRED_GE
&&
(
P2
==
PPC
::
PRED_GT
||
P2
==
PPC
::
PRED_EQ
)
)
return
true
;
return
false
;
}
</s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> void X86InsertPrefetch :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Subtarget . isSVR4ABI ( ) && PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { if ( Subtarget . isPPC64 ( ) ) { FrameIdx = 0 ; } else if ( CRSpillFrameIdx ) { FrameIdx = CRSpillFrameIdx ; } else { MachineFrameInfo * MFI = ( const_cast < MachineFunction & > ( MF ) ) . getFrameInfo ( ) ; FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; CRSpillFrameIdx = FrameIdx ; } return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> const MCExpr * AArch64TargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr , unsigned Size , SMLoc Loc ) { return ConstantPools -> addEntry ( Streamer , Expr , Size , Loc ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s>
bool
AArch64CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
AArch64
::
RET_ReallyLR
)
;
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
bool
Success
=
true
;
if
(
VReg
)
{
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
if
(
MRI
.
getType
(
VReg
)
.
getSizeInBits
(
)
==
1
)
VReg
=
MIRBuilder
.
buildZExt
(
LLT
::
scalar
(
8
)
,
VReg
)
->
getOperand
(
0
)
.
getReg
(
)
;
const
AArch64TargetLowering
&
TLI
=
*
getTLI
<
AArch64TargetLowering
>
(
)
;
CCAssignFn
*
AssignFn
=
TLI
.
CCAssignFnForReturn
(
F
.
getCallingConv
(
)
)
;
auto
&
DL
=
F
.
getParent
(
)
->
getDataLayout
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
F
.
getCallingConv
(
)
,
[
&
]
(
unsigned
Reg
,
uint64_t
Offset
)
{
MIRBuilder
.
buildExtract
(
Reg
,
VReg
,
Offset
)
;
}
)
;
OutgoingArgHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
AssignFn
,
AssignFn
)
;
Success
=
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
Success
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool MipsSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( hasMips64 ( ) ? & Mips :: CPU64RegsRegClass : & Mips :: CPURegsRegClass ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .

Mips Mips Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass


<s> TargetPassConfig * MMIXTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MMIXPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static bool fits_dispatch_window ( rtx_insn * insn ) { dispatch_windows * window_list = dispatch_window_list ; dispatch_windows * window_list_next = dispatch_window_list -> next ; unsigned int num_restrict ; enum dispatch_group group = get_insn_group ( insn ) ; enum insn_path path = get_insn_path ( insn ) ; int sum ; if ( group == disp_jcc || group == disp_cmp ) return false ; if ( group == disp_no_group || group == disp_branch ) return true ; if ( window_list_next ) window_list = window_list_next ; if ( window_list -> window_num == 1 ) { sum = window_list -> prev -> window_size + window_list -> window_size ; if ( sum == 32 || ( ix86_min_insn_size ( insn ) + sum ) >= 48 ) return true ; } num_restrict = count_num_restricted ( insn , window_list ) ; if ( num_restrict > num_allowable_groups [ group ] ) return false ; if ( window_list -> window_num == 0 ) { if ( path == path_double && ( window_list -> num_uops + 2 ) > MAX_INSN ) return false ; else if ( path != path_single ) return false ; } return true ; } </s>

This function returns true if insn satisfies dispatch rules on the last window scheduled .


<s> bool MipsInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : ExpandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: RetRA16 : ExpandRetRA ( MBB , MI , Mips :: RET16 ) ; break ; case Mips :: BuildPairF64 : ExpandBuildPairF64 ( MBB , MI ) ; break ; case Mips :: ExtractElementF64 : ExpandExtractElementF64 ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( this , nullptr , SawStore ) ) return nullptr ; unsigned IdxEnd = ( MI -> isCommutable ( ) ) ? 2 : 1 ; for ( unsigned Idx = 0 ; Idx < IdxEnd ; Idx ++ ) { unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; SmallVector < unsigned , 8 > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } if ( Idx == 1 ) { commuteInstruction ( MI , false ) ; return nullptr ; } if ( MI -> isCommutable ( ) ) { MachineInstr * NewMI = commuteInstruction ( MI , false ) ; if ( ! NewMI ) return nullptr ; if ( NewMI != MI ) { NewMI -> eraseFromParent ( ) ; return nullptr ; } } } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> rtx function_symbol ( rtx target , const char * name , enum sh_function_kind kind ) { rtx sym ; if ( kind != FUNCTION_ORDINARY ) name = IDENTIFIER_POINTER ( get_identifier ( name ) ) ; sym = gen_rtx_SYMBOL_REF ( Pmode , name ) ; SYMBOL_REF_FLAGS ( sym ) = SYMBOL_FLAG_FUNCTION ; if ( flag_pic ) switch ( kind ) { case FUNCTION_ORDINARY : break ; case SFUNC_GOT : { rtx reg = target ? target : gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOT2reg ( reg , sym ) ) ; sym = reg ; break ; } case SFUNC_STATIC : { rtx reg = target ? target : gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOTOFF2reg ( reg , sym ) ) ; sym = reg ; break ; } } if ( target && sym != target ) { emit_move_insn ( target , sym ) ; return target ; } return sym ; } </s>

Return an RTX pair for the address and call site label of a function NAME of kind KIND , placing the result in TARGET if not NULL . For SFUNC_STATIC , if FDPIC , the LAB member of result will be set to ( const_int 0 ) if jsr should be used , or a label_ref if bsrf should be used . For FDPIC , both SFUNC_GOT and SFUNC_STATIC will return the address of the function itself , not a function descriptor , so they can only be used with functions not using the FDPIC register that are known to be called directory without a PLT entry .


<s> const SDValue & getIndex ( ) const { return getOperand ( 4 ) ; } </s>


<s> void doInitialization ( Module & M ) { } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static int mingw32_gt_pch_use_address ( void * addr , size_t size , int fd , size_t offset ) { void * mmap_addr ; static HANDLE mmap_handle ; if ( size == 0 ) return 0 ; if ( ( offset & ( va_granularity - 1 ) ) != 0 || size > pch_VA_max_size ) return - 1 ; mmap_handle = CreateFileMapping ( ( HANDLE ) _get_osfhandle ( fd ) , NULL , PAGE_WRITECOPY | SEC_COMMIT , 0 , 0 , NULL ) ; if ( mmap_handle == NULL ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "CreateFileMapping" ) ; return - 1 ; } mmap_addr = MapViewOfFileEx ( mmap_handle , FILE_MAP_COPY , 0 , offset , size , addr ) ; if ( mmap_addr != addr ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "MapViewOfFileEx" ) ; CloseHandle ( mmap_handle ) ; return - 1 ; } return 1 ; } </s>

ADDR is an address returned by gt_pch_get_address . Attempt to allocate SIZE bytes at the same address and load it with the data from FD at OFFSET . Return -1 if we could n't allocate memory at ADDR , return 0 if the memory is allocated but the data not loaded , return 1 if done .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: ERet : expandERet ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : Opc = isMicroMips ? Mips :: CVT_D32_W_MM : Mips :: CVT_D32_W ; expandCvtFPInt ( MBB , MI , Opc , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : Opc = isMicroMips ? Mips :: CVT_D64_W_MM : Mips :: CVT_D64_W ; expandCvtFPInt ( MBB , MI , Opc , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , isMicroMips , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , isMicroMips , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , isMicroMips , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , isMicroMips , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


<s> bool aarch64_sve_ld1rq_ld1ro_operand_p ( rtx op , machine_mode mode , scalar_mode elem_mode ) { struct aarch64_address_info addr ; if ( ! MEM_P ( op ) || ! aarch64_classify_address ( & addr , XEXP ( op , 0 ) , elem_mode , false ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return offset_4bit_signed_scaled_p ( mode , addr . const_offset ) ; if ( addr . type == ADDRESS_REG_REG ) return ( 1U << addr . shift ) == GET_MODE_SIZE ( elem_mode ) ; return false ; } </s>

Return true if OP is a valid MEM operand for an SVE LD1R { Q , O } instruction where the size of the read data is specified by ` mode ` and the size of the vector elements are specified by ` elem_mode ` .


<s> int avx_vperm2f128_parallel ( rtx par , machine_mode mode ) { unsigned i , nelt = GET_MODE_NUNITS ( mode ) , nelt2 = nelt / 2 ; unsigned mask = 0 ; unsigned char ipar [ 8 ] = { } ; if ( XVECLEN ( par , 0 ) != ( int ) nelt ) return 0 ; for ( i = 0 ; i < nelt ; ++ i ) { rtx er = XVECEXP ( par , 0 , i ) ; unsigned HOST_WIDE_INT ei ; if ( ! CONST_INT_P ( er ) ) return 0 ; ei = INTVAL ( er ) ; if ( ei >= 2 * nelt ) return 0 ; ipar [ i ] = ei ; } for ( i = 0 ; i < nelt2 - 1 ; ++ i ) if ( ipar [ i ] + 1 != ipar [ i + 1 ] ) return 0 ; for ( i = nelt2 ; i < nelt - 1 ; ++ i ) if ( ipar [ i ] + 1 != ipar [ i + 1 ] ) return 0 ; for ( i = 0 ; i < 2 ; ++ i ) { unsigned e = ipar [ i * nelt2 ] ; if ( e % nelt2 ) return 0 ; e /= nelt2 ; mask |= e << ( i * 4 ) ; } return mask + 1 ; } </s>

Helper for avx_vperm2f128_v4df_operand et al . This is also used by the expansion functions to turn the parallel back into a mask . The return value is 0 for no match and the imm8+1 for a match .


"missing name in %<target(\"arch=\")%> pragma or attribute"

"invalid name (\"%s\") in %<target(\"arch=\")%> pragma or attribute"

"invalid value (\"%s\") in %<target()%> pragma or attribute"

Handle the ARCH_STR argument to the arch= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


"MIPS16 PIC for ABIs other than o32 and o64"

"hard-float MIPS16 code for ABIs other than o32 and o64"

Set up the target-dependent global state for ISA mode COMPRESSION_MODE , which is either MASK_MIPS16 or MASK_MICROMIPS .


<s> bool F2003fFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( funcInfo . MF -> getTarget ( ) ) ; bool UseFastISel = TM . Options . EnableFastISel && Subtarget . hasMips32 ( ) && ! Subtarget . hasMips32r6 ( ) && ! Subtarget . inMips16Mode ( ) && ! Subtarget . inMicroMipsMode ( ) ; if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) || LargeGOT ) UseFastISel = false ; return UseFastISel ? Mips :: createFastISel ( funcInfo , libInfo ) : nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

Mips Mips Mips Mips Mips Mips Mips Mips Mips::createFastISel


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( isN64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> bool MandarinAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasISEL ( ) ) return false ; if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> void TOYMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> bool arm_coproc_builtin_available ( enum unspecv builtin ) { if ( TARGET_THUMB1 ) return false ; switch ( builtin ) { case VUNSPEC_CDP : case VUNSPEC_LDC : case VUNSPEC_LDCL : case VUNSPEC_STC : case VUNSPEC_STCL : case VUNSPEC_MCR : case VUNSPEC_MRC : if ( arm_arch4 ) return true ; break ; case VUNSPEC_CDP2 : case VUNSPEC_LDC2 : case VUNSPEC_LDC2L : case VUNSPEC_STC2 : case VUNSPEC_STC2L : case VUNSPEC_MCR2 : case VUNSPEC_MRC2 : if ( arm_arch5t ) return true ; break ; case VUNSPEC_MCRR : case VUNSPEC_MRRC : if ( arm_arch6 || arm_arch5te ) return true ; break ; case VUNSPEC_MCRR2 : case VUNSPEC_MRRC2 : if ( arm_arch6 ) return true ; break ; default : gcc_unreachable ( ) ; } return false ; } </s>

This function checks for the availability of the coprocessor builtin passed in BUILTIN for the current target . Returns true if it is available and false otherwise . If a BUILTIN is passed for which this function has not been implemented it will cause an exception .


<s> TargetPassConfig * StackPU2TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new StackPU2PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool MipsSEInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { switch ( MI . getOpcode ( ) ) { case Mips :: CheriBoundedStackPseudoImm : assert ( MI . getOperand ( 3 ) . isImm ( ) ) ; return true ; case Mips :: CIncOffsetImm : case Mips :: CMove : case Mips :: COPY : return MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == Mips :: CNULL ; case Mips :: LUi64 : { auto Flags = MI . getOperand ( 1 ) . getTargetFlags ( ) ; if ( Flags == MipsII :: MO_CAPTABLE_OFF_HI ) { return true ; } return false ; } default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { if ( Ord == AtomicOrdering :: SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; if ( isReleaseOrStronger ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; return nullptr ; } </s>


<s>
static
void
arm_unwind_emit_set
(
FILE
*
out_file
,
rtx
p
)
{
rtx
e0
;
rtx
e1
;
unsigned
reg
;
e0
=
XEXP
(
p
,
0
)
;
e1
=
XEXP
(
p
,
1
)
;
switch
(
GET_CODE
(
e0
)
)
{
case
MEM
:
if
(
GET_CODE
(
XEXP
(
e0
,
0
)
)
!=
PRE_DEC
||
!
REG_P
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
||
REGNO
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
!=
SP_REGNUM
)
abort
(
)
;
asm_fprintf
(
out_file
,
"\t.save "
)
;
if
(
IS_VFP_REGNUM
(
REGNO
(
e1
)
)
)
asm_fprintf
(
out_file
,
"{d%d}\n"
,
(
REGNO
(
e1
)
FIRST_VFP_REGNUM
)
/
2
)
;
else
asm_fprintf
(
out_file
,
"{%r}\n"
,
REGNO
(
e1
)
)
;
break
;
case
REG
:
if
(
REGNO
(
e0
)
==
SP_REGNUM
)
{
if
(
GET_CODE
(
e1
)
!=
PLUS
||
!
REG_P
(
XEXP
(
e1
,
0
)
)
||
REGNO
(
XEXP
(
e1
,
0
)
)
!=
SP_REGNUM
||
!
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
abort
(
)
;
asm_fprintf
(
out_file
,
"\t.pad #%wd\n"
,
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
REGNO
(
e0
)
==
HARD_FRAME_POINTER_REGNUM
)
{
HOST_WIDE_INT
offset
;
if
(
GET_CODE
(
e1
)
==
PLUS
)
{
if
(
!
REG_P
(
XEXP
(
e1
,
0
)
)
||
!
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
abort
(
)
;
reg
=
REGNO
(
XEXP
(
e1
,
0
)
)
;
offset
=
INTVAL
(
XEXP
(
e1
,
1
)
)
;
asm_fprintf
(
out_file
,
"\t.setfp %r, %r, #%wd\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
,
offset
)
;
}
else
if
(
REG_P
(
e1
)
)
{
reg
=
REGNO
(
e1
)
;
asm_fprintf
(
out_file
,
"\t.setfp %r, %r\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
)
;
}
else
abort
(
)
;
}
else
if
(
REG_P
(
e1
)
&&
REGNO
(
e1
)
==
SP_REGNUM
)
{
asm_fprintf
(
out_file
,
"\t.movsp %r\n"
,
REGNO
(
e0
)
)
;
}
else
if
(
GET_CODE
(
e1
)
==
PLUS
&&
REG_P
(
XEXP
(
e1
,
0
)
)
&&
REGNO
(
XEXP
(
e1
,
0
)
)
==
SP_REGNUM
&&
CONST_INT_P
(
XEXP
(
e1
,
1
)
)
)
{
asm_fprintf
(
out_file
,
"\t.movsp %r, #%d\n"
,
REGNO
(
e0
)
,
(
int
)
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
REGNO
(
e0
)
==
IP_REGNUM
&&
arm_current_function_pac_enabled_p
(
)
)
{
if
(
cfun
->
machine
->
pacspval_needed
)
asm_fprintf
(
out_file
,
"\t.pacspval\n"
)
;
}
else
abort
(
)
;
break
;
default
:
abort
(
)
;
}
}
</s>


<s> const SICInstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>


<s> bool FalkorMarkStridedAccesses :: run ( ) { bool MadeChange = false ; for ( Loop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> void sparc_expand_vcond ( machine_mode mode , rtx * operands , int ccode , int fcode ) { rtx mask , cop0 , cop1 , fcmp , cmask , bshuf , gsr ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; mask = gen_reg_rtx ( Pmode ) ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; if ( code == LT || code == GE ) { rtx t ; code = swap_condition ( code ) ; t = cop0 ; cop0 = cop1 ; cop1 = t ; } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 2 , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , operands [ 1 ] , operands [ 2 ] , gsr ) , UNSPEC_BSHUFFLE ) ; emit_insn ( gen_rtx_SET ( mask , fcmp ) ) ; emit_insn ( gen_rtx_SET ( gsr , cmask ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , bshuf ) ) ; } </s>

Emit code to conditionally move a combination of OPERANDS [ 1 ] and OPERANDS [ 2 ] into OPERANDS [ 0 ] in MODE , depending on the outcome of the comparison of OPERANDS [ 4 ] and OPERANDS [ 5 ] . OPERANDS [ 3 ] is the operator of the condition . FCODE is the machine code to be used for OPERANDS [ 3 ] and CCODE the machine code to be used for the condition mask .


<s> static bool isAssociativeAndCommutative ( unsigned Opcode ) { switch ( Opcode ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : case PPC :: QVFADD : case PPC :: QVFADDS : case PPC :: QVFADDSs : case PPC :: QVFMUL : case PPC :: QVFMULS : case PPC :: QVFMULSs : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::QVFADD PPC::QVFADDS PPC::QVFADDSs PPC::QVFMUL PPC::QVFMULS PPC::QVFMULSs


<s> bool ARMBaseInstrInfo :: produceSameValue ( const MachineInstr * MI0 , const MachineInstr * MI1 ) const { int Opcode = MI0 -> getOpcode ( ) ; if ( Opcode == ARM :: t2LDRpci || Opcode == ARM :: t2LDRpci_pic || Opcode == ARM :: tLDRpci || Opcode == ARM :: tLDRpci_pic ) { if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 -> getOperand ( 1 ) ; const MachineOperand & MO1 = MI1 -> getOperand ( 1 ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; ARMConstantPoolValue * ACPV0 = static_cast < ARMConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; ARMConstantPoolValue * ACPV1 = static_cast < ARMConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } return MI0 -> isIdenticalTo ( MI1 , MachineInstr :: IgnoreVRegDefs ) ; } </s>

Return true if two machine instructions would produce identical values .


<s> bool X86TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < 32 > ( Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


"this operation requires the SVE ISA extension"

"you can enable SVE using the command-line"

" option %<-march%>, or by using the %<target%>"

Report when we try to do something that requires SVE when SVE is disabled . This is an error of last resort and is n't very high-quality . It usually involves attempts to measure the vector length in some way .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> void MipsMCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { if ( IsLittleEndian && Size == 4 && isMicroMips ( STI ) ) { emitInstruction ( Val >> 16 , 2 , STI , OS ) ; emitInstruction ( Val , 2 , STI , OS ) ; } else { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } } </s>

Targets should implement this to emit instructions .


<s> static void release_options_strings ( char * * option_strings ) { for ( unsigned i = 0 ; i < IX86_FUNCTION_SPECIFIC_MAX ; i ++ ) free ( option_strings [ i ] ) ; } </s>


<s> bool VEFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
case
Mips
::
BEQZC_MM
:
return
Mips
::
BNEZC_MM
;
case
Mips
::
BNEZC_MM
:
return
Mips
::
BEQZC_MM
;
case
Mips
::
BEQZC
:
return
Mips
::
BNEZC
;
case
Mips
::
BNEZC
:
return
Mips
::
BEQZC
;
case
Mips
::
BEQC
:
return
Mips
::
BNEC
;
case
Mips
::
BNEC
:
return
Mips
::
BEQC
;
case
Mips
::
BGTZC
:
return
Mips
::
BLEZC
;
case
Mips
::
BGEZC
:
return
Mips
::
BLTZC
;
case
Mips
::
BLTZC
:
return
Mips
::
BGEZC
;
case
Mips
::
BLEZC
:
return
Mips
::
BGTZC
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> unsigned AArch64InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return 2 ; case AArch64 :: LDPXi : case AArch64 :: LDPDi : case AArch64 :: STPXi : case AArch64 :: STPDi : case AArch64 :: LDNPXi : case AArch64 :: LDNPDi : case AArch64 :: STNPXi : case AArch64 :: STNPDi : case AArch64 :: LDPQi : case AArch64 :: STPQi : case AArch64 :: LDNPQi : case AArch64 :: STNPQi : case AArch64 :: LDPWi : case AArch64 :: LDPSi : case AArch64 :: STPWi : case AArch64 :: STPSi : case AArch64 :: LDNPWi : case AArch64 :: LDNPSi : case AArch64 :: STNPWi : case AArch64 :: STNPSi : return 3 ; } } </s>

Returns the index for the immediate for a given instruction .


<s> bool MipsPassConfig :: addInstSelector ( ) { if ( getMipsSubtarget ( ) . allowMixed16_32 ( ) ) { addPass ( createMipsModuleISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMips16ISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMipsSEISelDag ( getMipsTargetMachine ( ) ) ) ; } else { addPass ( createMipsISelDag ( getMipsTargetMachine ( ) ) ) ; } return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> int ARMRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return ARMGenRegisterInfo :: getDwarfRegNumFull ( RegNum , 0 ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s>
void
MMIXDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
Opcode
==
ISD
::
FrameIndex
)
{
SDLoc
DL
(
Node
)
;
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
MVT
::
i64
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
MMIX
::
ADD_I
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool mips_epilogue_uses ( unsigned int regno ) { if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( TARGET_USE_GOT && ( regno ) == GOT_VERSION_REGNUM ) return true ; if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return false ; } </s>


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Mips
Mips
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


"SVE requires vector length in multiples of 128!"

"Minimum SVE vector size should not be larger than its maximum!"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void X86FrameLowering :: emitCalleeSavedFrameMovesFullCFA ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { MachineFunction & MF = * MBB . getParent ( ) ; if ( ! hasFP ( MF ) ) { emitCalleeSavedFrameMoves ( MBB , MBBI , DebugLoc { } , true ) ; return ; } const MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const Register FramePtr = TRI -> getFrameRegister ( MF ) ; const Register MachineFramePtr = STI . isTarget64BitILP32 ( ) ? Register ( getX86SubSuperRegister ( FramePtr , 64 ) ) : FramePtr ; unsigned DwarfReg = MRI -> getDwarfRegNum ( MachineFramePtr , true ) ; unsigned Offset = ( Is64Bit ? 8 : 4 ) + ( Uses64BitFramePtr ? 8 : 4 ) ; BuildCFI ( MBB , MBBI , DebugLoc { } , MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - Offset ) ) ; emitCalleeSavedFrameMoves ( MBB , MBBI , DebugLoc { } , true ) ; } </s>

Emits Dwarf Info specifying offsets of callee saved registers and frame pointer .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: PPC32_GOT : return "PPCISD::PPC32_GOT" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> tree function_resolver :: resolve_unary ( type_class_index merge_tclass , unsigned int merge_bits , bool treat_as_merge_p ) { type_suffix_index type ; if ( pred == PRED_m || treat_as_merge_p ) { if ( ! check_num_arguments ( 3 ) ) return error_mark_node ; if ( merge_tclass == SAME_TYPE_CLASS && merge_bits == SAME_SIZE ) { if ( ( type = infer_vector_type ( 0 ) ) == NUM_TYPE_SUFFIXES || ! require_vector_type ( 1 , VECTOR_TYPE_svbool_t ) || ! require_matching_vector_type ( 2 , type ) ) return error_mark_node ; } else { if ( ! require_vector_type ( 1 , VECTOR_TYPE_svbool_t ) || ( type = infer_vector_type ( 2 ) ) == NUM_TYPE_SUFFIXES || ! require_derived_vector_type ( 0 , 2 , type , merge_tclass , merge_bits ) ) return error_mark_node ; } } else { unsigned int i , nargs ; if ( ! check_gp_argument ( 1 , i , nargs ) || ( type = infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; } if ( type_suffix_ids [ 0 ] != NUM_TYPE_SUFFIXES ) return resolve_to ( mode_suffix_id , type_suffix_ids [ 0 ] , type ) ; return resolve_to ( mode_suffix_id , type ) ; } </s>

Resolve a ( possibly predicated ) unary function . If the function uses merge predication or if TREAT_AS_MERGE_P is true , there is an extra vector argument before the governing predicate that specifies the values of inactive elements . This argument has the following properties : - the type class must be the same as for active elements if MERGE_TCLASS is SAME_TYPE_CLASS , otherwise it must be MERGE_TCLASS itself . - the element size must be the same as for active elements if MERGE_BITS is SAME_TYPE_SIZE , otherwise it must be MERGE_BITS itself . Return the function decl of the resolved function on success , otherwise report a suitable error and return error_mark_node .


<s> unsigned getPrefFunctionAlignment ( ) const { return PrefFunctionAlignment ; } </s>

Return the preferred function alignment .


<s> void DLXTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { } </s>

Lower the specified operand into the Ops vector .


<s> int direct_return ( void ) { if ( reload_completed ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( info -> first_gp_reg_save == 32 && info -> first_fp_reg_save == 64 && info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 && ! info -> lr_save_p && ! info -> cr_save_p && info -> vrsave_size == 0 && ! info -> push_p ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


"%qE attribute ignored without -mcmse option."

"%qE attribute only applies to base type of a "

Called upon detection of the use of the cmse_nonsecure_call attribute , this function will check whether the attribute is allowed here and will add the attribute to the function type tree or otherwise issue a diagnostic . The reason we check this at declaration time is to only allow the use of the attribute with declarations of function pointers and not function declarations . This function checks NODE is of the expected type and issues diagnostics otherwise using NAME . If it is not of the expected type * NO_ADD_ATTRS will be set to true .


<s>
SDValue
DLXTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_src , permute_tmp ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , 0 ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source ) : source ; permute_src = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_tmp = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , permute_src ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , permute_tmp ) ) ; } </s>

Emit a little-endian store to vector memory location DEST from VSX register SOURCE in mode MODE . The store is done with two permuting insn 's that represent an xxpermdi and an stxvd2x .


<s> rtx ix86_libcall_value ( enum machine_mode mode ) { if ( TARGET_64BIT ) { switch ( mode ) { case SFmode : case SCmode : case DFmode : case DCmode : case TFmode : return gen_rtx_REG ( mode , FIRST_SSE_REG ) ; case XFmode : case XCmode : return gen_rtx_REG ( mode , FIRST_FLOAT_REG ) ; case TCmode : return NULL ; default : return gen_rtx_REG ( mode , 0 ) ; } } else return gen_rtx_REG ( mode , ix86_value_regno ( mode , NULL , NULL ) ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> const MipsSubtarget * getSubtargetImpl ( ) const override { if ( Subtarget ) return Subtarget ; return & DefaultSubtarget ; } </s>


<s> static rtx aarch64_strip_extend ( rtx x , bool strip_shift ) { scalar_int_mode mode ; rtx op = x ; if ( ! is_a < scalar_int_mode > ( GET_MODE ( op ) , & mode ) ) return op ; if ( GET_CODE ( op ) == AND && GET_CODE ( XEXP ( op , 0 ) ) == MULT && CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) && CONST_INT_P ( XEXP ( op , 1 ) ) && aarch64_uxt_size ( exact_log2 ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) , INTVAL ( XEXP ( op , 1 ) ) ) != 0 ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( strip_shift && GET_CODE ( op ) == ASHIFT && CONST_INT_P ( XEXP ( op , 1 ) ) && ( ( unsigned HOST_WIDE_INT ) INTVAL ( XEXP ( op , 1 ) ) ) <= 4 ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == ZERO_EXTEND || GET_CODE ( op ) == SIGN_EXTEND ) op = XEXP ( op , 0 ) ; if ( op != x ) return op ; return x ; } </s>

Helper function for rtx cost calculation . Strip an extend expression from X . Returns the inner operand if successful , or the original expression on failure . We deal with a number of possible canonicalization variations here .


<s> bool Thumb1FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void function_expander :: prepare_prefetch_operands ( ) { unsigned int prfop = INTVAL ( args . last ( ) ) ; args . quick_push ( GEN_INT ( ( prfop & 8 ) != 0 ) ) ; args . quick_push ( GEN_INT ( ( ( prfop >> 1 ) & 3 ) + 1 ) ) ; } </s>

The final argument is an immediate svprfop value . Add two fake arguments to represent the rw and locality operands of a PREFETCH rtx .


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void function_expander :: add_integer_operand ( HOST_WIDE_INT x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 , true ) ; create_integer_operand ( & m_ops . last ( ) , x ) ; } </s>


<s> static const char * arm_identify_fpu_from_isa ( sbitmap isa ) { auto_sbitmap fpubits ( isa_num_bits ) ; auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return "softvfp" ; for ( unsigned int i = 0 ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ; if ( bitmap_equal_p ( fpubits , cand_fpubits ) ) return all_fpus [ i ] . name ; } gcc_unreachable ( ) ; } </s>

Match an ISA feature bitmap to a named FPU . We always use the first entry that exactly matches the feature set , so that we effectively canonicalize the FPU name for the assembler .


<s> bool SystemZTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 20 > ( AM . BaseOffs ) ) return false ; return AM . Scale == 0 || AM . Scale == 1 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static unsigned int loongarch_build_integer ( struct loongarch_integer_op * codes , HOST_WIDE_INT value ) { unsigned int cost = 0 ; HOST_WIDE_INT low_part = TARGET_64BIT ? value << 32 >> 32 : value ; if ( IMM12_OPERAND ( low_part ) || IMM12_OPERAND_UNSIGNED ( low_part ) ) { codes [ 0 ] . code = UNKNOWN ; codes [ 0 ] . method = METHOD_NORMAL ; codes [ 0 ] . value = low_part ; cost ++ ; } else { codes [ 0 ] . code = UNKNOWN ; codes [ 0 ] . method = METHOD_NORMAL ; codes [ 0 ] . value = low_part & ~ ( IMM_REACH - 1 ) ; cost ++ ; HOST_WIDE_INT iorv = low_part & ( IMM_REACH - 1 ) ; if ( iorv != 0 ) { codes [ 1 ] . code = IOR ; codes [ 1 ] . method = METHOD_NORMAL ; codes [ 1 ] . value = iorv ; cost ++ ; } } if ( TARGET_64BIT ) { bool lu32i [ 2 ] = { ( value & LU32I_B ) == 0 , ( value & LU32I_B ) == LU32I_B } ; bool lu52i [ 2 ] = { ( value & LU52I_B ) == 0 , ( value & LU52I_B ) == LU52I_B } ; int sign31 = ( value & ( 1UL << 31 ) ) >> 31 ; if ( lu32i [ sign31 ] && lu52i [ sign31 ] ) return cost ; else if ( lu32i [ sign31 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = ( value >> 52 ) << 52 ; return cost + 1 ; } codes [ cost ] . method = METHOD_LU32I ; codes [ cost ] . value = ( ( value << 12 ) >> 44 ) << 32 ; cost ++ ; if ( ! lu52i [ ( value & ( 1ULL << 51 ) ) >> 51 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = ( value >> 52 ) << 52 ; cost ++ ; } } gcc_assert ( cost <= LARCH_MAX_INTEGER_OPS ) ; return cost ; } </s>

Fill CODES with a sequence of rtl operations to load VALUE . Return the number of operations needed .


"Attempting to lower call as tail call\n"

"... Cannot handle tail calls with swifterror yet.\n"

"... Calling convention cannot be tail called.\n"

"... Cannot tail call from callers with byval, "

"... Cannot tail call externally-defined function "

"Unexpected variadic calling convention"

"... Caller and callee have incompatible calling conventions.\n"

"... Call is eligible for tail call optimization.\n"

Returns true if the call can be lowered as a tail call .


<s> bool AArch64InstrInfo :: isPairableLdStInst ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: STRXui : case AArch64 :: STRWui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : case AArch64 :: LDRXui : case AArch64 :: LDRWui : case AArch64 :: LDRSWui : case AArch64 :: STURSi : case AArch64 :: STURDi : case AArch64 :: STURQi : case AArch64 :: STURWi : case AArch64 :: STURXi : case AArch64 :: LDURSi : case AArch64 :: LDURDi : case AArch64 :: LDURQi : case AArch64 :: LDURWi : case AArch64 :: LDURXi : case AArch64 :: LDURSWi : return true ; } } </s>

Return true if pairing the given load or store may be paired with another .


<s> bool isSubregFoldable ( ) const override { return true ; } </s>

Check whether the target can fold a load that feeds a subreg operand ( or a subreg operand that feeds a store ) .


<s> static inline void desc_abi ( unsigned char abi __attribute__ ( ( unused ) ) , unsigned char context __attribute__ ( ( unused ) ) , struct unw_state_record * sr __attribute__ ( ( unused ) ) ) { } </s>


"Unsupported expression operand in assembly source"

getMachineOpValue - Return binary encoding of operand .


<s> const MipsRegisterInfo & MipsSEInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static int ia64_speculate_insn ( rtx_insn * insn , ds_t ts , rtx * new_pat ) { int mode_no ; int res ; gcc_assert ( ! ( ts & ~ SPECULATIVE ) ) ; if ( ia64_spec_check_p ( insn ) ) return - 1 ; if ( ( ts & BE_IN_SPEC ) && ! insn_can_be_in_speculative_p ( insn , ts ) ) return - 1 ; mode_no = get_mode_no_for_insn ( insn ) ; if ( mode_no != SPEC_MODE_INVALID ) { if ( ia64_get_insn_spec_ds ( insn ) == ds_get_speculation_types ( ts ) ) res = 0 ; else { res = 1 ; * new_pat = ia64_gen_spec_load ( insn , ts , mode_no ) ; } } else res = - 1 ; return res ; } </s>

Implement targetm.sched.speculate_insn hook . Check if the INSN can be TS speculative . If 'no ' - return -1 . If 'yes ' - generate speculative pattern in the NEW_PAT and return 1 . If current pattern of the INSN already provides TS speculation , return 0 .


<s> void MipsRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjustMipsStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOREORDER ) ) ; if ( isPIC && Subtarget . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPLOAD ) ) . addReg ( getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOMACRO ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: FP ) . addReg ( Mips :: SP ) . addReg ( Mips :: ZERO ) ; } if ( MipsFI -> needGPSaveRestore ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPRESTORE ) ) . addImm ( MipsFI -> getGPStackOffset ( ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips Mips Mips 0 Mips Mips Mips::NOREORDER Mips::CPLOAD Mips::NOMACRO Mips::ADDiu Mips::SP Mips::SP Mips::SW Mips::RA Mips::SP Mips::SW Mips::FP Mips::SP Mips::ADDu Mips::FP Mips::SP Mips::ZERO Mips Mips::CPRESTORE Mips


<s> bool ARM64TargetLowering :: isEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( isVarArg && ! Outs . empty ( ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCAssignFn * AssignFn = CCAssignFnForCall ( CalleeCC , false ) ; CCInfo . AnalyzeCallOperands ( Outs , AssignFn ) ; if ( CCInfo . getNextStackOffset ( ) ) { for ( unsigned i = 0 , realArgIdx = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { return false ; } else if ( ! VA . isRegLoc ( ) ) { return false ; } } } } return true ; } </s>


<s> static unsigned int insn_is_swappable_p ( swap_web_entry * insn_entry , rtx insn , unsigned int * special ) { if ( GET_CODE ( insn ) == CALL_INSN ) return 0 ; rtx body = PATTERN ( insn ) ; int i = INSN_UID ( insn ) ; if ( insn_entry [ i ] . is_load ) { if ( GET_CODE ( body ) == SET ) { * special = SH_NOSWAP_LD ; return 1 ; } else return 0 ; } if ( insn_entry [ i ] . is_store ) { if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) != UNSPEC ) { * special = SH_NOSWAP_ST ; return 1 ; } else return 0 ; } return rtx_is_swappable_p ( body , special ) ; } </s>

Return 1 iff INSN is an operand that will not be affected by having vector doublewords swapped in memory ( in which case * SPECIAL is unchanged ) , or that can be modified to be correct if vector doublewords are swapped in memory ( in which case * SPECIAL is changed to a value indicating how ) .


Return true if the vector misalignment factor is supported by the target .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> int xstormy16_mode_dependent_address_p ( rtx x ) { if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , 0 ) && ! LEGITIMATE_ADDRESS_CONST_INT_P ( x , 6 ) ) return 1 ; if ( GET_CODE ( x ) == PLUS && LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , 1 ) , 0 ) && ! LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , 1 ) , 6 ) ) return 1 ; if ( GET_CODE ( x ) == PLUS ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return 1 ; return 0 ; } </s>

Return nonzero if memory address X ( an RTX ) can have different meanings depending on the machine mode of the memory reference it is used for or if the address is valid for some modes but not others . Autoincrement and autodecrement addresses typically have mode-dependent effects because the amount of the increment or decrement is the size of the operand being addressed . Some machines have other mode-dependent addresses . Many RISC machines have no mode-dependent addresses . You may assume that ADDR is a valid address for the machine . On this chip , this is true if the address is valid with an offset of 0 but not of 6 , because in that case it can not be used as an address for DImode or DFmode , or if the address is a post-increment or pre-decrement address .


<s> void moxie_print_operand_address ( FILE * file , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , "(%s)" , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST_INT : fprintf ( file , "%ld(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; break ; case SYMBOL_REF : output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; break ; case CONST : { rtx plus = XEXP ( XEXP ( x , 1 ) , 0 ) ; if ( GET_CODE ( XEXP ( plus , 0 ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( plus , 1 ) ) ) { output_addr_const ( file , XEXP ( plus , 0 ) ) ; fprintf ( file , "+%ld(%s)" , INTVAL ( XEXP ( plus , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else abort ( ) ; } break ; default : abort ( ) ; } break ; default : output_addr_const ( file , x ) ; break ; } } </s>


"insertBranch must not be told to insert a fallthrough"

"ARM branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> static bool mep_expand_setcc_1 ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { rtx tmp ; switch ( code ) { case GT : case GTU : tmp = op1 , op1 = op2 , op2 = tmp ; code = swap_condition ( code ) ; case LT : case LTU : op1 = force_reg ( SImode , op1 ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_fmt_ee ( code , SImode , op1 , op2 ) ) ) ; return true ; case EQ : if ( op2 != const0_rtx ) op1 = expand_binop ( SImode , sub_optab , op1 , op2 , NULL , 1 , OPTAB_WIDEN ) ; mep_expand_setcc_1 ( LTU , dest , op1 , const1_rtx ) ; return true ; case NE : if ( optimize_size && op2 != const0_rtx ) return false ; if ( op2 != const0_rtx ) op1 = expand_binop ( SImode , sub_optab , op1 , op2 , NULL , 1 , OPTAB_WIDEN ) ; op2 = gen_reg_rtx ( SImode ) ; mep_expand_setcc_1 ( LTU , op2 , op1 , const1_rtx ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_XOR ( SImode , op2 , const1_rtx ) ) ) ; return true ; case LE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == 0x7ffffff ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) + 1 ) ; return mep_expand_setcc_1 ( LT , dest , op1 , op2 ) ; case LEU : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == - 1 ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) + 1 , SImode ) ) ; return mep_expand_setcc_1 ( LTU , dest , op1 , op2 ) ; case GE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == trunc_int_for_mode ( 0x80000000 , SImode ) ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) - 1 ) ; return mep_expand_setcc_1 ( GT , dest , op1 , op2 ) ; case GEU : if ( GET_CODE ( op2 ) != CONST_INT || op2 == const0_rtx ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) - 1 , SImode ) ) ; return mep_expand_setcc_1 ( GTU , dest , op1 , op2 ) ; default : gcc_unreachable ( ) ; } } </s>

Emit a setcc instruction in its entirity .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> inline set_of_reg rx_find_set_of_reg ( rtx reg , rtx_insn * insn , F stepfunc , bool ignore_reg_reg_copies = false ) { set_of_reg result ; result . insn = insn ; result . set_rtx = NULL_RTX ; result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_set_p ( reg , i ) ) { if ( CALL_P ( i ) ) break ; result . insn = i ; result . set_rtx = set_of ( reg , i ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , 1 ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) { reg = SUBREG_REG ( result . set_src ) ; continue ; } break ; } } if ( result . set_src != NULL && result . set_rtx == NULL ) result . set_src = NULL ; return result ; } </s>

FIXME : Copy-pasta from SH . Move to rtl.h . Given a reg rtx and a start insn , try to find the insn that sets the specified reg by using the specified insn stepping function , such as 'prev_nonnote_nondebug_insn_bb ' . When the insn is found , try to extract the rtx of the reg set .


"Unknown architecture specific memory model"

"HLE_ACQUIRE not used with ACQUIRE or stronger memory model"

"HLE_RELEASE not used with RELEASE or stronger memory model"

Validate target specific memory model bits in VAL .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( I -> getNumUses ( ) != 1 ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; EVT VT = getValueType ( User -> getOperand ( 0 ) -> getType ( ) ) ; if ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( ISD :: FMA , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) return false ; return true ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> bool MINA32AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> unsigned getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> bool mep_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> bool targetHandlesStackFrameRounding ( ) const override { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( RealignStack && ( ! MFI -> hasVarSizedObjects ( ) || EnableBasePointer ) ) ; } </s>

True if the stack can be realigned for the target .


<s> static bool has_dispatch ( rtx_insn * insn , int action ) { if ( ( TARGET_BDVER1 || TARGET_BDVER2 || TARGET_BDVER3 || TARGET_BDVER4 ) && flag_dispatch_scheduler ) switch ( action ) { default : return false ; case IS_DISPATCH_ON : return true ; break ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ; } return false ; } </s>

Return TRUE if Dispatch Scheduling is supported .


<s> bool X86TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == MVT :: f32 ) return Subtarget . hasSSE1 ( ) ; if ( VT == MVT :: f64 ) return Subtarget . hasSSE2 ( ) ; return true ; } </s>

Returns true if it 's safe to use load / store of the specified type to expand memcpy / memset inline .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const MipsDisassemblerBase * Dis = static_cast < const MipsDisassemblerBase * > ( D ) ; return * ( Dis -> getRegInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addReg ( 0 ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_lo16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_ha16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_lo14"
,
16
,
14
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> HOST_WIDE_INT sh_disp_addr_displacement ( rtx x ) { gcc_assert ( satisfies_constraint_Sdd ( x ) ) ; return INTVAL ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ; } </s>

Return the displacement value of a displacement address .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> void rs6000_emit_sCOND ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx ; machine_mode op_mode ; enum rtx_code cond_code ; rtx result = operands [ 0 ] ; condition_rtx = rs6000_generate_compare ( operands [ 1 ] , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( FLOAT_MODE_P ( mode ) && ! TARGET_FPRS && TARGET_HARD_FLOAT ) { rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , 0 ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 0 ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 1 ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , result , condition_rtx ) ) ; } } </s>


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case SCmode : case DCmode : case TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TREE_CODE ( valtype ) == VECTOR_TYPE && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || mode == TFmode || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


<s> bool MipsPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


"internal error inserting '%s' in bifo_rbt\n"

Parse a two-line entry for a built-in function .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
SADDSAT
:
case
ISD
::
SSUBSAT
:
case
ISD
::
UADDSAT
:
case
ISD
::
USUBSAT
:
Res
=
LowerADDSUBSAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
LOAD
:
LowerLOAD
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
TRUNCATE
:
Res
=
LowerTruncate
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
LowerVectorExtend
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
FP_TO_SINT_SAT
:
case
ISD
::
FP_TO_UINT_SAT
:
Res
=
LowerFP_TO_INT_SAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool ARMBaseRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> const LEGRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . getSizeInBits ( ) == 16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; if ( VT . getSizeInBits ( ) == 32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( 2 , Size - 1 ) . getAsInteger ( 10 , RegNo ) ; if ( ! Failed && RegNo >= 0 && RegNo <= 31 ) { if ( VT != MVT :: Other && VT . getSizeInBits ( ) == 64 ) { Res . first = AArch64 :: FPR64RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR64RegClass ; } else { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } } if ( Res . second && ! Subtarget -> hasFPARMv8 ( ) && ! AArch64 :: GPR32allRegClass . hasSubClassEq ( Res . second ) && ! AArch64 :: GPR64allRegClass . hasSubClassEq ( Res . second ) ) return std :: make_pair ( 0U , nullptr ) ; return Res ; } </s>

Given a physical register constraint ( e.g .


<s> static unsigned long arm_compute_func_type ( ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; if ( TREE_CODE ( current_function_decl ) != FUNCTION_DECL ) abort ( ) ; if ( optimize > 0 && current_function_nothrow && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( current_function_needs_context ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; if ( cfun -> machine -> eh_epilogue_sp_ofs != NULL_RTX ) type |= ARM_FT_EXCEPTION_HANDLER ; else { a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; } return type ; } </s>

Computes the type of the current function .


<s> bool ix86_match_ccmode ( rtx insn , machine_mode req_mode ) { rtx set ; machine_mode set_mode ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( set ) ) == COMPARE ) ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCNOmode : if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , 1 ) != const0_rtx ) ) return false ; break ; case CCmode : if ( req_mode == CCGCmode ) return false ; case CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return false ; case CCGOCmode : if ( req_mode == CCZmode ) return false ; case CCZmode : break ; case CCAmode : case CCCmode : case CCOmode : case CCSmode : if ( set_mode != req_mode ) return false ; break ; default : gcc_unreachable ( ) ; } return GET_MODE ( SET_SRC ( set ) ) == set_mode ; } </s>

Return TRUE or FALSE depending on whether the first SET in INSN has source and destination with matching CC modes , and that the CC mode is at least as constrained as REQ_MODE .


<s> void UPTInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc = 0 , ZeroReg = 0 ; Opc = UPT :: ADDR , ZeroReg = UPT :: ZERO ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( UPT :: ADDR ) ) ; if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( ZeroReg ) MIB . addReg ( UPT :: ZERO ) ; if ( SrcReg ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>

UPT UPT 0 0 UPT::ADDR UPT::ZERO UPT::ADDR UPT::ZERO


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> virtual const ARMBaseInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


<s> bool Comet2PassConfig :: addInstSelector ( ) { addPass ( createComet2ISelDag ( getComet2TargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static inline MemOpKey getTombstoneKey ( ) { return MemOpKey ( PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) , PtrInfo :: getTombstoneKey ( ) ) ; } </s>

Difference in tombstone is that the Optional is meaningful .