<s> void function_builder :: add_overloaded_functions ( const function_group_info & group , mode_suffix_index mode ) { unsigned int explicit_type0 = ( * group . shape ) -> explicit_type_suffix_p ( 0 ) ; unsigned int explicit_type1 = ( * group . shape ) -> explicit_type_suffix_p ( 1 ) ; for ( unsigned int pi = 0 ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) { if ( ! explicit_type0 && ! explicit_type1 ) { function_instance instance ( group . base_name , * group . base , * group . shape , mode , types_none [ 0 ] , group . preds [ pi ] ) ; add_overloaded_function ( instance , group . required_extensions ) ; } else for ( unsigned int ti = 0 ; group . types [ ti ] [ 0 ] != NUM_TYPE_SUFFIXES ; ++ ti ) { type_suffix_pair types = { explicit_type0 ? group . types [ ti ] [ 0 ] : NUM_TYPE_SUFFIXES , explicit_type1 ? group . types [ ti ] [ 1 ] : NUM_TYPE_SUFFIXES } ; function_instance instance ( group . base_name , * group . base , * group . shape , mode , types , group . preds [ pi ] ) ; add_overloaded_function ( instance , group . required_extensions ) ; } } } </s>

If we are using manual overload resolution , add one function decl for each overloaded function in GROUP . Take the function base name from GROUP and the mode from MODE .


<s>
MachineBasicBlock
::
iterator
AArch64InstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
TCRETURNdi
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
.
addImm
(
0
)
)
;
return
It
;
}
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
return
It
;
}
MachineBasicBlock
::
iterator
CallPt
;
MachineInstr
*
Save
;
MachineInstr
*
Restore
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
if
(
!
MBB
.
isLiveIn
(
AArch64
::
LR
)
)
MBB
.
addLiveIn
(
AArch64
::
LR
)
;
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
Reg
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
AArch64
::
LR
)
.
addImm
(
0
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
AArch64
::
LR
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
Reg
)
.
addImm
(
0
)
;
}
else
{
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
STRXpre
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
LDRXpost
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
}
It
=
MBB
.
insert
(
It
,
Save
)
;
It
++
;
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
CallPt
=
It
;
It
++
;
It
=
MBB
.
insert
(
It
,
Restore
)
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .


<s> bool hasAndNot ( SDValue Y ) const override { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return hasAndNotCompare ( Y ) ; TypeSize TS = VT . getSizeInBits ( ) ; return ! TS . isScalable ( ) && TS . getFixedValue ( ) >= 64 ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s> void ARMELFStreamer :: EmitRegSave ( const SmallVectorImpl < unsigned > & RegList , bool IsVector ) { } </s>

Emit unwind opcodes for .save directives .


<s> bool X86TTIImpl :: isLegalMaskedCompressStore ( Type * DataTy ) { return isLegalMaskedExpandLoad ( DataTy ) ; } </s>

Return true if the target supports masked compress store .


<s> void F2003fFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const F2003fInstrInfo & TII = * static_cast < const F2003fInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize ) { BuildMI ( MBB , MBBI , DL , TII . get ( F2003f :: ATAri ) , F2003f :: F5 ) . addReg ( F2003f :: F5 ) . addImm ( StackSize ) ; } } </s>


<s> bool MipsSETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { MVT :: SimpleValueType SVT = VT . getSimpleVT ( ) . SimpleTy ; if ( Subtarget . systemSupportsUnalignedAccess ( ) ) { if ( Fast ) * Fast = true ; return true ; } switch ( SVT ) { case MVT :: i64 : case MVT :: i32 : if ( Fast ) * Fast = true ; return true ; default : return false ; } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static void register_tuple_type ( unsigned int num_vectors , vector_type_index type ) { tree tuple_type = lang_hooks . types . make_type ( RECORD_TYPE ) ; char buffer [ sizeof ( "svbfloat16x4_t" ) ] ; const char * vector_type_name = vector_types [ type ] . acle_name ; snprintf ( buffer , sizeof ( buffer ) , "%.*sx%d_t" , ( int ) strlen ( vector_type_name ) - 2 , vector_type_name , num_vectors ) ; tree vector_type = acle_vector_types [ 0 ] [ type ] ; tree array_type = build_array_type_nelts ( vector_type , num_vectors ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( array_type ) ) && TYPE_MODE_RAW ( array_type ) == TYPE_MODE ( array_type ) && TYPE_ALIGN ( array_type ) == 128 ) ; tree field = build_decl ( input_location , FIELD_DECL , get_identifier ( "__val" ) , array_type ) ; DECL_FIELD_CONTEXT ( field ) = tuple_type ; TYPE_FIELDS ( tuple_type ) = field ; add_sve_type_attribute ( tuple_type , num_vectors , 0 , NULL , buffer ) ; make_type_sizeless ( tuple_type ) ; layout_type ( tuple_type ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( tuple_type ) ) && TYPE_MODE_RAW ( tuple_type ) == TYPE_MODE ( tuple_type ) && TYPE_ALIGN ( tuple_type ) == 128 ) ; tree decl = build_decl ( input_location , TYPE_DECL , get_identifier ( buffer ) , tuple_type ) ; TYPE_NAME ( tuple_type ) = decl ; TYPE_STUB_DECL ( tuple_type ) = decl ; lang_hooks . decls . pushdecl ( decl ) ; DECL_ORIGINAL_TYPE ( decl ) = NULL_TREE ; acle_vector_types [ num_vectors - 1 ] [ type ] = tuple_type ; } </s>

Register the tuple type that contains NUM_VECTORS vectors of type TYPE .


<s> bool PPCDispatchGroupSBHazardRecognizer :: ShouldPreferAnother ( SUnit * SU ) { const MCInstrDesc * MCID = DAG -> getInstrDesc ( SU ) ; unsigned NSlots ; if ( MCID && mustComeFirst ( MCID , NSlots ) && CurSlots ) return true ; return ScoreboardHazardRecognizer :: ShouldPreferAnother ( SU ) ; } </s>

ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard .


<s> static void mips_sim_wait_units ( struct mips_sim * state , rtx_insn * insn ) { state_t tmp_state ; tmp_state = alloca ( state_size ( ) ) ; while ( state -> insns_left == 0 || ( memcpy ( tmp_state , state -> dfa_state , state_size ( ) ) , state_transition ( tmp_state , insn ) >= 0 ) ) mips_sim_next_cycle ( state ) ; } </s>

Advance simulation state STATE until the units required by instruction INSN are available .


<s> void aarch64_expand_sve_mem_move ( rtx dest , rtx src , machine_mode pred_mode ) { machine_mode mode = GET_MODE ( dest ) ; rtx ptrue = aarch64_ptrue_reg ( pred_mode ) ; if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) aarch64_emit_sve_pred_move ( tmp , ptrue , src ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } aarch64_emit_sve_pred_move ( dest , ptrue , src ) ; } </s>

Expand a pre-RA SVE data move from SRC to DEST in which at least one operand is in memory . In this case we need to use the predicated LD1 and ST1 instead of LDR and STR , both for correctness on big-endian targets and because LD1 and ST1 support a wider range of addressing modes . PRED_MODE is the mode of the predicate . See the comment at the head of aarch64-sve.md for details about the big-endian handling .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; bool isMicroMips = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: PseudoMFHI : Opc = isMicroMips ? Mips :: MFHI16_MM : Mips :: MFHI ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFLO : Opc = isMicroMips ? Mips :: MFLO16_MM : Mips :: MFLO ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool Inserter :: runOnMachineFunction ( MachineFunction & F ) { if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; bool Changed = false ; int FI = F . getInfo < MipsFunctionInfo > ( ) -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isLandingPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( Mips :: LW ) , Mips :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != Mips :: JALR ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( Mips :: LW ) , Mips :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips::LW Mips::GP 0 Mips::JALR Mips::LW Mips::GP 0


<s>
unsigned
LEGMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_LEG_LO
:
{
FixupKind
=
LEG
::
fixup_leg_mov_lo16_pcrel
;
break
;
}
case
MCSymbolRefExpr
::
VK_LEG_HI
:
{
FixupKind
=
LEG
::
fixup_leg_mov_hi16_pcrel
;
break
;
}
}
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> unsigned stackAlignment ( ) const { return 8 ; } </s>

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function .


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; if ( ! SubTarget . hasIBT ( ) ) return false ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB ) ; } for ( auto & MBB : MF ) if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB ) ; return Changed ; } </s>


<s> static bool loongarch_cannot_force_const_mem ( machine_mode mode , rtx x ) { enum loongarch_symbol_type type ; rtx base , offset ; if ( CONST_INT_P ( x ) && loongarch_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( loongarch_symbolic_constant_p ( base , & type ) ) { if ( IMM12_INT ( offset ) && loongarch_symbol_insns ( type , MAX_MACHINE_MODE ) > 0 ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>


<s> TargetPassConfig * LC2200TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LC2200PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> const AArch64InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool ix86_expand_fp_movcc ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx tmp , compare_op ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( GET_MODE ( op0 ) == BFmode && ! ix86_fp_comparison_operator ( operands [ 1 ] , VOIDmode ) ) return false ; if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) { machine_mode cmode ; cmode = GET_MODE ( op0 ) ; if ( cmode == VOIDmode ) cmode = GET_MODE ( op1 ) ; if ( cmode != mode ) return false ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & op0 , & op1 ) ; if ( code == UNKNOWN ) return false ; if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ) return true ; tmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , tmp , operands [ 2 ] , operands [ 3 ] ) ; return true ; } if ( GET_MODE ( op0 ) == TImode || ( GET_MODE ( op0 ) == DImode && ! TARGET_64BIT ) ) return false ; compare_op = ix86_expand_compare ( code , op0 , op1 ) ; if ( ! fcmov_comparison_operator ( compare_op , VOIDmode ) ) { tmp = gen_reg_rtx ( QImode ) ; ix86_expand_setcc ( tmp , code , op0 , op1 ) ; compare_op = ix86_expand_compare ( NE , tmp , const0_rtx ) ; } emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( mode , compare_op , operands [ 2 ] , operands [ 3 ] ) ) ) ; return true ; } </s>

Expand a floating-point conditional move . Return true if successful .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const ARMSubtarget & Subtarget = DAG . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; if ( ! Subtarget . isAAPCS_ABI ( ) || Subtarget . isTargetMachO ( ) || Subtarget . isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * DAG . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> void AArch64ConditionalCompares :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


A helper function to handle isr stuff at the end of asm file .


<s> bool AArch64WinCOFFObjectWriter :: recordRelocation ( const MCFixup & Fixup ) const { return true ; } </s>


<s> const Comet2Subtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
!=
PPC
::
DIR_440
&&
Directive
!=
PPC
::
DIR_A2
&&
Directive
!=
PPC
::
DIR_E500mc
&&
Directive
!=
PPC
::
DIR_E5500
)
{
const
TargetInstrInfo
*
TII
=
TM
.
getInstrInfo
(
)
;
assert
(
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
TII
)
;
}
return
new
PPCScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


"use_as_extended_reg: converting non-extending mem load in "

"use_as_extended_reg: dest reg %d of extending insn %d is "

Given a reg that is known to be sign or zero extended at some insn , take the appropriate measures so that the extended value can be used as a reg at the specified insn and return the resulting reg rtx .


<s> static const char * rs6000_xcoff_visibility ( tree decl ) { static const char * const visibility_types [ ] = { "" , ",protected" , ",hidden" , ",internal" } ; enum symbol_visibility vis = DECL_VISIBILITY ( decl ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && cgraph_node :: get ( decl ) && cgraph_node :: get ( decl ) -> instrumentation_clone && cgraph_node :: get ( decl ) -> instrumented_version ) vis = DECL_VISIBILITY ( cgraph_node :: get ( decl ) -> instrumented_version -> decl ) ; return visibility_types [ vis ] ; } </s>

Helper function to calculate visibility of a DECL and return the value as a const string .

rs6000 "" ",protected" ",hidden" ",internal"


<s>
bool
ARMBaseInstrInfo
::
getExtractSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPairAndIdx
&
InputReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isExtractSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VMOVRRD
:
const
MachineOperand
&
MOReg
=
MI
.
getOperand
(
2
)
;
InputReg
.
Reg
=
MOReg
.
getReg
(
)
;
InputReg
.
SubReg
=
MOReg
.
getSubReg
(
)
;
InputReg
.
SubIdx
=
DefIdx
==
0
ARM
::
ssub_0
:
ARM
::
ssub_1
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getExtractSubregInputs .


<s> bool ix86_expand_fp_movcc ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx tmp , compare_op ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) { machine_mode cmode ; cmode = GET_MODE ( op0 ) ; if ( cmode == VOIDmode ) cmode = GET_MODE ( op1 ) ; if ( cmode != mode ) return false ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & op0 , & op1 ) ; if ( code == UNKNOWN ) return false ; if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ) return true ; tmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , op0 , op1 , operands [ 2 ] , operands [ 3 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , tmp , operands [ 2 ] , operands [ 3 ] ) ; return true ; } if ( GET_MODE ( op0 ) == TImode || ( GET_MODE ( op0 ) == DImode && ! TARGET_64BIT ) ) return false ; compare_op = ix86_expand_compare ( code , op0 , op1 ) ; if ( ! fcmov_comparison_operator ( compare_op , VOIDmode ) ) { tmp = gen_reg_rtx ( QImode ) ; ix86_expand_setcc ( tmp , code , op0 , op1 ) ; compare_op = ix86_expand_compare ( NE , tmp , const0_rtx ) ; } emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( mode , compare_op , operands [ 2 ] , operands [ 3 ] ) ) ) ; return true ; } </s>


<s> static int loongarch_sign_extend_cost ( rtx op ) { if ( MEM_P ( op ) ) return 0 ; return COSTS_N_INSNS ( 1 ) ; } </s>

Return the cost of sign-extending OP to mode MODE , not including the cost of OP itself .


<s> bool AArch64RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MFI . hasVarSizedObjects ( ) && ! hasBasePointer ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> SDValue KudeyarTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: SIGN_EXTEND : return LowerSIGN_EXTEND ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: ExternalSymbol : return LowerExternalSymbol ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: BR_CC : return LowerBR_CC ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; default : break ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Kudeyar Kudeyar ISD::SIGN_EXTEND ISD::GlobalAddress ISD::ExternalSymbol ISD::BlockAddress ISD::JumpTable ISD::SETCC ISD::BR_CC ISD::SELECT_CC


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s>
void
SHUXIInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SHUXI
::
GPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SHUXI
::
CPYrr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>

SHUXI
SHUXI
SHUXI::GPRegsRegClass
SHUXI::CPYrr
"Impossible reg-to-reg copy"


<s> void altivec_expand_vec_perm_le ( rtx operands [ 4 ] ) { rtx notx , iorx , unspec ; rtx target = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx sel = operands [ 3 ] ; rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op0 , op1 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; } if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target , unspec ) ; } </s>

Similarly to altivec_expand_vec_perm_const_le , we must adjust the permute control vector . But here it 's not a constant , so we must generate a vector NAND or NOR to do the adjustment .


<s> bool LanaiAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << LanaiInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return true ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static rtx rs6000_savres_routine_sym ( rs6000_stack_t * info , int sel ) { int regno = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save - 32 : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save - FIRST_ALTIVEC_REGNO : - 1 ) ; rtx sym ; int select = sel ; if ( TARGET_SPE_ABI && ( sel & SAVRES_REG ) == SAVRES_GPR && info -> spe_64bit_regs_used ) select ^= SAVRES_FPR ^ SAVRES_GPR ; gcc_assert ( FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER && select >= 0 && select <= 12 ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] ; if ( sym == NULL ) { char * name ; name = rs6000_savres_routine_name ( info , regno , sel ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_FUNCTION ; } return sym ; } </s>

Return an RTL SYMBOL_REF for an out-of-line register save/restore routine . We are saving/restoring GPRs if GPR is true .


<s> bool aarch64_stepped_int_parallel_p ( rtx op , int step ) { if ( GET_CODE ( op ) != PARALLEL || ! CONST_INT_P ( XVECEXP ( op , 0 , 0 ) ) ) return false ; unsigned HOST_WIDE_INT base = UINTVAL ( XVECEXP ( op , 0 , 0 ) ) ; for ( int i = 1 ; i < XVECLEN ( op , 0 ) ; ++ i ) if ( ! CONST_INT_P ( XVECEXP ( op , 0 , i ) ) || UINTVAL ( XVECEXP ( op , 0 , i ) ) != base + i * step ) return false ; return true ; } </s>

Return true if OP is a PARALLEL of CONST_INTs that form a linear series with step STEP .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 31 ; } </s>


<s>
static
void
rs6000_elf_output_toc_section_asm_op
(
const
char
*
data
ATTRIBUTE_UNUSED
)
{
if
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_MINIMAL_TOC
)
{
if
(
!
toc_initialized
)
{
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"LCTOC"
,
0
)
;
fprintf
(
asm_out_file
,
"\t.tc "
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1[TC],"
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
else
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
}
else
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
{
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
toc_initialized
=
1
;
}
}
else
{
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
}
}
</s>

A get_unnamed_section callback , used for switching to toc_section .


<s>
SDValue
CJGTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

CJG
CJG
ISD::BR_CC
ISD::SELECT_CC
ISD::GlobalAddress
ISD::ExternalSymbol
"unimplemented operand"


<s> int paired_emit_vector_cond_expr ( rtx dest , rtx op1 , rtx op2 , rtx cond , rtx cc_op0 , rtx cc_op1 ) { enum rtx_code rcode = GET_CODE ( cond ) ; if ( ! TARGET_PAIRED_FLOAT ) return 0 ; paired_emit_vector_compare ( rcode , dest , op1 , op2 , cc_op0 , cc_op1 ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s> static reg_class_t ix86_spill_class ( reg_class_t rclass , machine_mode mode ) { if ( 0 && TARGET_GENERAL_REGS_SSE_SPILL && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC && TARGET_INTER_UNIT_MOVES_FROM_VEC && ( mode == SImode || ( TARGET_64BIT && mode == DImode ) ) && INTEGER_CLASS_P ( rclass ) ) return ALL_SSE_REGS ; return NO_REGS ; } </s>

Return class of registers which could be used for pseudo of MODE and of class RCLASS for spilling instead of memory . Return NO_REGS if it is not possible or non-profitable .


<s>
void
LanaiInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
Position
,
DebugLoc
DL
,
unsigned
DestinationRegister
,
unsigned
SourceRegister
,
bool
KillSource
)
const
{
if
(
!
Lanai
::
GPRRegClass
.
contains
(
DestinationRegister
,
SourceRegister
)
)
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
Position
,
DL
,
get
(
Lanai
::
OR_I_LO
)
,
DestinationRegister
)
.
addReg
(
SourceRegister
,
getKillRegState
(
KillSource
)
)
.
addImm
(
0
)
;
}
</s>

Lanai
Lanai
Lanai::GPRRegClass
"Impossible reg-to-reg copy"
Lanai::OR_I_LO
0


"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> unsigned SparcAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * GOp , unsigned Kind ) { SparcOperand * Op = ( SparcOperand * ) GOp ; if ( Op -> isFloatOrDoubleReg ( ) ) { switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op -> isFloatReg ( ) || SparcOperand :: MorphToDoubleReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( SparcOperand :: MorphToQuadReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Sparc Sparc Sparc Sparc SparcOperand::MorphToDoubleReg SparcOperand::MorphToQuadReg


<s> bool MipsPassConfig :: addPreSched2 ( ) { PM . add ( createMipsExpandPseudoPass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
unsigned
Encoding
,
Mangler
&
Mang
,
const
TargetMachine
&
TM
,
MachineModuleInfo
*
MMI
,
MCStreamer
&
Streamer
)
const
{
if
(
TM
.
getMCAsmInfo
(
)
->
getExceptionHandlingType
(
)
!=
ExceptionHandling
::
ARM
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Encoding
,
Mang
,
TM
,
MMI
,
Streamer
)
;
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
return
MCSymbolRefExpr
::
Create
(
TM
.
getSymbol
(
GV
,
Mang
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
ARM
"Can handle absptr encoding only"
ARM


<s> static rtx_insn * mep_make_bundle ( rtx core_insn_or_pat , rtx_insn * cop ) { rtx seq ; rtx_insn * core_insn ; rtx_insn * insn ; if ( INSN_P ( core_insn_or_pat ) ) { core_insn = as_a < rtx_insn * > ( core_insn_or_pat ) ; remove_insn ( core_insn ) ; } else core_insn = make_insn_raw ( core_insn_or_pat ) ; seq = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec ( 2 , core_insn , cop ) ) ; insn = emit_insn_after ( seq , cop ) ; remove_insn ( cop ) ; SET_PREV_INSN ( core_insn ) = PREV_INSN ( insn ) ; SET_NEXT_INSN ( core_insn ) = cop ; SET_PREV_INSN ( cop ) = core_insn ; SET_NEXT_INSN ( cop ) = NEXT_INSN ( insn ) ; PUT_MODE ( core_insn , VOIDmode ) ; PUT_MODE ( cop , BImode ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( INSN_LOCATION ( core_insn ) ? core_insn : cop ) ; INSN_LOCATION ( core_insn ) = 0 ; INSN_LOCATION ( cop ) = 0 ; return insn ; } </s>

Create a VLIW bundle from core instruction CORE and coprocessor instruction COP . COP always satisfies INSN_P , but CORE can be either a new pattern or an existing instruction . Emit the bundle in place of COP and return it .


<s> void mips_split_move ( rtx dest , rtx src , enum mips_split_type split_type ) { rtx low_dest ; gcc_checking_assert ( mips_split_move_p ( dest , src , split_type ) ) ; if ( MSA_SUPPORTED_MODE_P ( GET_MODE ( dest ) ) ) mips_split_128bit_move ( dest , src ) ; else if ( FP_REG_RTX_P ( dest ) || FP_REG_RTX_P ( src ) ) { if ( ! TARGET_64BIT && GET_MODE ( dest ) == DImode ) emit_insn ( gen_move_doubleword_fprdi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == DFmode ) emit_insn ( gen_move_doubleword_fprdf ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V2SFmode ) emit_insn ( gen_move_doubleword_fprv2sf ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V2SImode ) emit_insn ( gen_move_doubleword_fprv2si ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V4HImode ) emit_insn ( gen_move_doubleword_fprv4hi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V8QImode ) emit_insn ( gen_move_doubleword_fprv8qi ( dest , src ) ) ; else if ( TARGET_64BIT && GET_MODE ( dest ) == TFmode ) emit_insn ( gen_move_doubleword_fprtf ( dest , src ) ) ; else gcc_unreachable ( ) ; } else if ( REG_P ( dest ) && REGNO ( dest ) == MD_REG_FIRST ) { low_dest = mips_subword ( dest , false ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthidi_ti ( dest , mips_subword ( src , true ) , low_dest ) ) ; else emit_insn ( gen_mthisi_di ( dest , mips_subword ( src , true ) , low_dest ) ) ; } else if ( REG_P ( src ) && REGNO ( src ) == MD_REG_FIRST ) { mips_emit_move ( mips_subword ( dest , false ) , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( mips_subword ( dest , true ) , src ) ) ; else emit_insn ( gen_mfhisi_di ( mips_subword ( dest , true ) , src ) ) ; } else { low_dest = mips_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; } else { mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; } } } </s>

Split a move from SRC to DEST , given that mips_split_move_p holds . SPLIT_TYPE describes the split condition .


<s> static bool ix86_function_value_regno_p ( const unsigned int regno ) { switch ( regno ) { case AX_REG : return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_cfun_abi ( ) != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ; case ST0_REG : case ST1_REG : if ( TARGET_64BIT && ix86_cfun_abi ( ) == MS_ABI ) return false ; return TARGET_FLOAT_RETURNS_IN_80387 ; case XMM0_REG : case XMM1_REG : return TARGET_SSE ; case MM0_REG : if ( TARGET_MACHO || TARGET_64BIT ) return false ; return TARGET_MMX ; } return false ; } </s>

Return true if N is a possible register number of function value .


<s> void AArch64Subtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; Policy . DisableLatencyHeuristic = DisableLatencySchedHeuristic ; } </s>

Override generic scheduling policy within a region .


<s> SDValue LanaiSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> static int elf_dcachebsize ( void ) { int fd ; fd = open ( "/proc/self/auxv" , O_RDONLY ) ; if ( fd != - 1 ) { char buf [ 1024 ] ; ElfW ( auxv_t ) * av ; ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd ) ; if ( n > 0 ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_DCACHEBSIZE : return av -> a_un . a_val ; default : break ; } } } </s>

Returns AT_DCACHEBSIZE if present , otherwise generic 32 .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { if ( InstrumentSandboxingCFI ) removeCall64m ( MF ) ; addBoundChecks ( MF ) ; return 0 ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool unspec_caller_rtx_p ( rtx pat ) { rtx base , offset ; split_const ( pat , & base , & offset ) ; if ( GET_CODE ( base ) == UNSPEC ) { if ( XINT ( base , 1 ) == UNSPEC_CALLER ) return true ; for ( int i = 0 ; i < XVECLEN ( base , 0 ) ; i ++ ) if ( unspec_caller_rtx_p ( XVECEXP ( base , 0 , i ) ) ) return true ; } return false ; } </s>

Check if PAT includes UNSPEC_CALLER unspec pattern .


<s> const SDValue & getMask ( ) const { return getOperand ( 2 ) ; } </s>


<s> void X86FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const MCCFIInstruction & CFIInst ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . getMMI ( ) . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

Wraps up getting a CFI index and building a MachineInstr for it .


<s> static bool tryAddingSymbolicOperand ( uint64_t Address , int32_t Value , bool isBranch , uint64_t InstSize , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , ( uint32_t ) Value , Address , isBranch , 0 , 0 , InstSize ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> static int num_insns_constant_multi ( HOST_WIDE_INT value , machine_mode mode ) { int nregs = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int total = 0 ; while ( nregs -- > 0 ) { HOST_WIDE_INT low = sext_hwi ( value , BITS_PER_WORD ) ; int insns = num_insns_constant_gpr ( low ) ; if ( insns > 2 && rs6000_is_valid_and_mask ( GEN_INT ( low ) , DImode ) ) insns = 2 ; total += insns ; value >>= ( BITS_PER_WORD - 1 ) ; value >>= 1 ; } return total ; } </s>

Helper for num_insns_constant . Allow constants formed by the num_insns_constant_gpr sequences , plus li -1 , rldicl/rldicr/rlwinm , and handle modes that require multiple gprs .


<s> static void gen_ashift_hi ( int type , int n , rtx reg ) { if ( n < 0 ) { if ( type == ASHIFT ) type = LSHIFTRT ; else type = ASHIFT ; n = - n ; } switch ( type ) { case ASHIFTRT : case LSHIFTRT : { int offset = 0 ; if ( GET_CODE ( reg ) == SUBREG ) { offset = SUBREG_BYTE ( reg ) ; reg = SUBREG_REG ( reg ) ; } gen_ashift ( type , n , gen_rtx_SUBREG ( SImode , reg , offset ) ) ; break ; } case ASHIFT : emit_insn ( gen_ashlhi3_k ( reg , reg , GEN_INT ( n ) ) ) ; break ; } } </s>


<s>
void
AArch64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
AArch64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
STI
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
AArch64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
const
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
STI
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
AArch64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
AArch64InstPrinter
::
printInst
(
MI
,
O
,
Annot
,
STI
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool mips_find_gp_ref ( bool * cache , bool ( * pred ) ( rtx_insn * ) ) { rtx_insn * insn , * subinsn ; if ( ! * cache ) { push_topmost_sequence ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( USEFUL_INSN_P ( subinsn ) && pred ( subinsn ) ) { * cache = true ; break ; } pop_topmost_sequence ( ) ; } return * cache ; } </s>

Return true if predicate PRED is true for at least one instruction . Cache the result in * CACHE , and assume that the result is true if * CACHE is already true .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t TrueNops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; static const uint8_t AltNops [ 7 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x8d , 0x76 , 0x00 } , { 0x8d , 0x74 , 0x26 , 0x00 } , { 0x90 , 0x8d , 0x74 , 0x26 , 0x00 } , { 0x8d , 0xb6 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x8d , 0xb4 , 0x26 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; const uint8_t ( * Nops ) [ 10 ] = HasNopl ? TrueNops : AltNops ; assert ( HasNopl || MaxNopLength <= 7 ) ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
MachineInstr
*
LanaiInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
)
const
{
assert
(
MI
.
getOpcode
(
)
==
Lanai
::
SELECT
&&
"unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
1
:
2
)
;
Register
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
add
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
getOppositeCondition
(
LPCC
::
CondCode
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
copyImplicitOps
(
MI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
add
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool PPCTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! VT . isSimple ( ) || ! Subtarget . hasVSX ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: f32 : case MVT :: f64 : case MVT :: ppcf128 : return Imm . isPosZero ( ) ; } } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool PPCPassConfig :: addInstSelector ( ) { addPass ( createPPCISelDag ( getPPCTargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoopsVerify ( ) ) ; addPass ( createPPCVSXCopyPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
unsigned
ARMBaseInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
getLastNonDebugInstr
(
)
;
if
(
I
==
MBB
.
end
(
)
)
return
0
;
if
(
!
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
I
->
getOpcode
(
)
!=
ARM
::
t2LoopEnd
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
I
->
getOpcode
(
)
!=
ARM
::
t2LoopEnd
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> Register ARMTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget -> useSjLjEH ( ) ? Register ( ) : ARM :: R1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> static void arm_expand_builtin_va_start ( tree valist , rtx nextarg ) { valist = arm_extract_valist_ptr ( valist ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static rtx aarch64_expand_builtin_ls64 ( int fcode , tree exp , rtx target ) { expand_operand ops [ 3 ] ; switch ( fcode ) { case AARCH64_LS64_BUILTIN_LD64B : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; create_output_operand ( & ops [ 0 ] , target , V8DImode ) ; create_input_operand ( & ops [ 1 ] , op0 , DImode ) ; expand_insn ( CODE_FOR_ld64b , 2 , ops ) ; return ops [ 0 ] . value ; } case AARCH64_LS64_BUILTIN_ST64B : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , 1 ) ) ; create_output_operand ( & ops [ 0 ] , op0 , DImode ) ; create_input_operand ( & ops [ 1 ] , op1 , V8DImode ) ; expand_insn ( CODE_FOR_st64b , 2 , ops ) ; return const0_rtx ; } case AARCH64_LS64_BUILTIN_ST64BV : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , 1 ) ) ; create_output_operand ( & ops [ 0 ] , target , DImode ) ; create_input_operand ( & ops [ 1 ] , op0 , DImode ) ; create_input_operand ( & ops [ 2 ] , op1 , V8DImode ) ; expand_insn ( CODE_FOR_st64bv , 3 , ops ) ; return ops [ 0 ] . value ; } case AARCH64_LS64_BUILTIN_ST64BV0 : { rtx op0 = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; rtx op1 = expand_normal ( CALL_EXPR_ARG ( exp , 1 ) ) ; create_output_operand ( & ops [ 0 ] , target , DImode ) ; create_input_operand ( & ops [ 1 ] , op0 , DImode ) ; create_input_operand ( & ops [ 2 ] , op1 , V8DImode ) ; expand_insn ( CODE_FOR_st64bv0 , 3 , ops ) ; return ops [ 0 ] . value ; } } gcc_unreachable ( ) ; } </s>

Function to expand an expression EXP which calls one of the Load/Store 64 Byte extension ( LS64 ) builtins FCODE with the result going to TARGET .


<s>
void
SystemZInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32mr
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Pmr
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128mr
;
}
else
llvm_unreachable
(
"Unsupported regclass to store"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void pa_file_end ( void ) { unsigned int i ; extern_symbol * p ; if ( ! NO_DEFERRED_PROFILE_COUNTERS ) output_deferred_profile_counters ( ) ; output_deferred_plabels ( ) ; for ( i = 0 ; vec_safe_iterate ( extern_symbols , i , & p ) ; i ++ ) { tree decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , 0 ) ) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ; } vec_free ( extern_symbols ) ; if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ; } </s>

Output text required at the end of an assembler file . This includes deferred plabels and .import directives for all external symbols that were actually referenced .


<s> static void csky_conditional_register_usage ( void ) { if ( TARGET_MINI_REGISTERS ) { int i ; for ( i = ( CSKY_LAST_MINI_REGNUM + 1 ) ; i < 32 ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; call_really_used_regs [ i ] = 1 ; } } else if ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) || ! TARGET_HIGH_REGISTERS ) { int i ; for ( i = CSKY_FIRST_HIGH_REGNUM ; i <= CSKY_LAST_HIGH_REGNUM ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; call_really_used_regs [ i ] = 1 ; } } if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) { fixed_regs [ CSKY_LR_REGNUM ] = 1 ; call_used_regs [ CSKY_LR_REGNUM ] = 1 ; call_really_used_regs [ CSKY_LR_REGNUM ] = 0 ; } if ( ! TARGET_DSP ) { fixed_regs [ CSKY_HI_REGNUM ] = 1 ; call_used_regs [ CSKY_HI_REGNUM ] = 1 ; call_really_used_regs [ CSKY_HI_REGNUM ] = 1 ; fixed_regs [ CSKY_LO_REGNUM ] = 1 ; call_used_regs [ CSKY_LO_REGNUM ] = 1 ; call_really_used_regs [ CSKY_LO_REGNUM ] = 1 ; } if ( ! TARGET_HARD_FLOAT ) { int regno ; for ( regno = CSKY_FIRST_VFP_REGNUM ; regno <= CSKY_LAST_VFP_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 1 ; call_used_regs [ regno ] = 1 ; call_really_used_regs [ regno ] = 1 ; } } if ( flag_pic ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_really_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 0 ; } } </s>

Implement TARGET_CONDITIONAL_REGISTER_USAGE . Conditionally modify five variables fixed_regs , call_used_regs , global_regs , reg_names , and reg_class_contents , to take into account any dependence of these register sets on target flags . CK801 has registers r0-r8 and r13-r15 . CK802 and CK803 have registers r0-r15 ( the `` low '' registers ) . Other cpus use registers r0-r31 with -mhigh-registers , otherwise also only r0-r15 . CK801 only has 16-bit instructions , most of which can only reference r0-r7 ( the `` mini '' registers ) . So we mark regs outside that range as fixed . -msmart can be used on other arch variants to force the same behavior because it results in smaller code size . TODO : investigate whether it 's beneficial to use r8-r13 as a spill class when TARGET_MINI_REGISTERS instead of making them unusable by the register allocator .


<s> bool isMicroMips ( ) const { return STI . getFeatureBits ( ) & Mips :: FeatureMicroMips ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
asm_fprintf
(
asm_out_file
,
"\t.fpu %s\n"
,
(
TARGET_SOFT_FLOAT
"softvfp"
:
arm_identify_fpu_from_isa
(
arm_active_target
.
isa
)
)
)
;
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .


<s> const uint32_t * VERegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { default : return CSR_RegMask ; case CallingConv :: PreserveAll : return CSR_preserve_all_RegMask ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> enum aarch_parse_opt_result aarch_parse_branch_protection ( const char * const_str , char * * last_str ) { char * str_root = xstrdup ( const_str ) ; char * token_save = NULL ; char * str = strtok_r ( str_root , "+" , & token_save ) ; enum aarch_parse_opt_result res = AARCH_PARSE_OK ; if ( ! str ) res = AARCH_PARSE_MISSING_ARG ; else { char * next_str = strtok_r ( NULL , "+" , & token_save ) ; aarch_handle_no_branch_protection ( NULL , NULL ) ; while ( str && res == AARCH_PARSE_OK ) { const aarch_branch_protect_type * type = aarch_branch_protect_types ; bool found = false ; while ( type && type -> name && ! found && res == AARCH_PARSE_OK ) { if ( strcmp ( str , type -> name ) == 0 ) { found = true ; res = type -> handler ( str , next_str ) ; str = next_str ; next_str = strtok_r ( NULL , "+" , & token_save ) ; } else type ++ ; } if ( found && res == AARCH_PARSE_OK ) { bool found_subtype = true ; while ( found_subtype ) { found_subtype = false ; const aarch_branch_protect_type * subtype = type -> subtypes ; while ( str && subtype && subtype -> name && ! found_subtype && res == AARCH_PARSE_OK ) { if ( strcmp ( str , subtype -> name ) == 0 ) { found_subtype = true ; res = subtype -> handler ( str , next_str ) ; str = next_str ; next_str = strtok_r ( NULL , "+" , & token_save ) ; } else subtype ++ ; } } } else if ( ! found ) res = AARCH_PARSE_INVALID_ARG ; } } if ( last_str ) { if ( str ) strcpy ( * last_str , str ) ; else * last_str = NULL ; } if ( res == AARCH_PARSE_OK ) { if ( ! accepted_branch_protection_string ) accepted_branch_protection_string = ( char * ) xmalloc ( BRANCH_PROTECT_STR_MAX + 1 ) ; strncpy ( accepted_branch_protection_string , const_str , BRANCH_PROTECT_STR_MAX + 1 ) ; accepted_branch_protection_string [ BRANCH_PROTECT_STR_MAX ] = '\0' ; } return res ; } </s>

Parses CONST_STR for branch protection features specified in aarch64_branch_protect_types , and set any global variables required . Returns the parsing result and assigns LAST_STR to the last processed token from CONST_STR so that it can be used for error reporting .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> static rtx mips_expand_builtin_compare_1 ( enum insn_code icode , enum mips_fp_condition cond , tree exp , int nargs ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; rtx output ; int opno , argno ; gcc_assert ( nargs + 2 == insn_data [ ( int ) icode ] . n_generator_args ) ; output = mips_allocate_fcc ( insn_data [ ( int ) icode ] . operand [ 0 ] . mode ) ; opno = 0 ; create_fixed_operand ( & ops [ opno ++ ] , output ) ; for ( argno = 0 ; argno < nargs ; argno ++ ) mips_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; create_integer_operand ( & ops [ opno ++ ] , ( int ) cond ) ; return mips_expand_builtin_insn ( icode , opno , ops , true ) ; } </s>

Expand a floating-point comparison for built-in function call EXP . The first NARGS arguments are the values to be compared . ICODE is the .md pattern that does the comparison and COND is the condition that is being tested . Return an rtx for the result .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
uint64_t
ValSize
=
VA
.
getValVT
(
)
.
getFixedSizeInBits
(
)
;
uint64_t
LocSize
=
VA
.
getLocVT
(
)
.
getFixedSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MIRBuilder
.
buildCopy
(
LLT
::
scalar
(
LocSize
)
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"
"Extensions not supported"


<s> static void ix86_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) && stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( & next_cum ) ; else setup_incoming_varargs_64 ( & next_cum ) ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> static bool expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( VOIDmode , target , x ) ; rtx_insn * insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel perm ) ) ) and return true if that 's a valid instruction in the active ISA .


"MMIX Internal: %s is not a shiftable int"

Print operator suitable for doing something with a shiftable wyde . The type of operator is passed as an asm output modifier .


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> isPredicable ( ) ) return false ; if ( ( MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) { ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARMII::DomainMask ARMII::DomainNEON ARM ARM


<s> int ix86_match_ccmode ( rtx insn , enum machine_mode req_mode ) { rtx set ; enum machine_mode set_mode ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( set ) ) == COMPARE ) ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCNOmode : if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , 1 ) != const0_rtx ) ) return 0 ; break ; case CCmode : if ( req_mode == CCGCmode ) return 0 ; case CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return 0 ; case CCGOCmode : if ( req_mode == CCZmode ) return 0 ; case CCZmode : break ; default : gcc_unreachable ( ) ; } return ( GET_MODE ( SET_SRC ( set ) ) == set_mode ) ; } </s>

Return TRUE or FALSE depending on whether the first SET in INSN has source and destination with matching CC modes , and that the CC mode is at least as constrained as REQ_MODE .


<s> std :: pair < uint16_t , uint16_t > ARMBaseInstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == ARM :: VMOVD && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; if ( Subtarget . isLikeA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == ARM :: VMOVRS || MI -> getOpcode ( ) == ARM :: VMOVSR || MI -> getOpcode ( ) == ARM :: VMOVS ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; unsigned Domain = MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Domain & ARMII :: DomainNEON ) return std :: make_pair ( ExeNEON , 0 ) ; if ( ( Domain & ARMII :: DomainNEONA8 ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , 0 ) ; if ( Domain & ARMII :: DomainVFP ) return std :: make_pair ( ExeVFP , 0 ) ; return std :: make_pair ( ExeGeneric , 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> static bool sh_pass_in_reg_p ( const CUMULATIVE_ARGS & cum , machine_mode mode , const_tree type ) { return ( ( type == 0 || ( ! TREE_ADDRESSABLE ( type ) && ( ! ( TARGET_HITACHI || cum . renesas_abi ) || ! ( AGGREGATE_TYPE_P ( type ) || ( ! TARGET_FPU_ANY && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SFmode ) ) ) ) ) ) ) && ! cum . force_mem && ( TARGET_SH2E ? ( ( mode ) == BLKmode ? ( ( cum . arg_count [ ( int ) SH_ARG_INT ] * UNITS_PER_WORD + int_size_in_bytes ( type ) ) <= NPARM_REGS ( SImode ) * UNITS_PER_WORD ) : ( ( sh_round_reg ( cum , mode ) + HARD_REGNO_NREGS ( BASE_ARG_REG ( mode ) , mode ) ) <= NPARM_REGS ( mode ) ) ) : sh_round_reg ( cum , mode ) < NPARM_REGS ( mode ) ) ) ; } </s>

Return true if arg of the specified mode should be be passed in a register or false otherwise .


<s> bool XNCMInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : PrintAsmMemoryOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; return false ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & AArch64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned SparcInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == SP :: LDri || MI . getOpcode ( ) == SP :: LDXri || MI . getOpcode ( ) == SP :: LDFri || MI . getOpcode ( ) == SP :: LDDFri || MI . getOpcode ( ) == SP :: LDQFri ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void check_label_emit ( ) { if ( mvs_need_base_reload ) { mvs_need_base_reload = 0 ; mvs_page_code += 4 ; fprintf ( assembler_source , "\tL\t%d,%d(,%d)\n" , BASE_REGISTER , ( mvs_page_num - function_base_page ) * 4 , PAGE_REGISTER ) ; } } </s>

Emit reload of base register if indicated . This is to eliminate multiple reloads when several labels are generated pointing to the same place in the code . The page table is written at the end of the function . The entries in the page table look like .LPGT0 : // PGT0 EQU * .long .LPG0 // DC A ( PG0 ) .long .LPG1 // DC A ( PG1 ) while the prologue generates L r4 , =A ( .LPGT0 ) Note that this paging scheme breaks down if a single subroutine has more than about 10MB of code in it ... as long as humans write code , this should n't be a problem ...


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: tMOVr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ; } </s>


<s> unsigned postOffset ( Align Alignment = Align :: None ( ) ) const { unsigned PO = Offset + Size ; const Align PA = std :: max ( PostAlign , Alignment ) ; if ( PA == Align :: None ( ) ) return PO ; return PO + UnknownPadding ( PA , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s> static bool arm_default_short_enums ( void ) { return ARM_DEFAULT_SHORT_ENUMS ; } </s>

AAPCS based ABIs use short enums by default .


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) const { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Directive = ST -> getCPUDirective ( ) ; if ( Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 || Directive == PPC :: DIR_PWR10 || Directive == PPC :: DIR_PWR_FUTURE ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


<s>
void
A57ChainingConstraint
::
apply
(
PBQPRAGraph
&
G
)
{
const
MachineFunction
&
MF
=
G
.
getMetadata
(
)
.
MF
;
LiveIntervals
&
LIs
=
G
.
getMetadata
(
)
.
LIS
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
DEBUG
(
MF
.
dump
(
)
)
;
for
(
const
auto
&
MBB
:
MF
)
{
Chains
.
clear
(
)
;
for
(
const
auto
&
MI
:
MBB
)
{
for
(
auto
r
:
Chains
)
{
SmallVector
<
unsigned
,
8
>
toDel
;
if
(
regJustKilledBefore
(
LIs
,
r
,
MI
)
)
{
DEBUG
(
dbgs
(
)
<<
"Killing chain "
<<
PrintReg
(
r
,
TRI
)
<<
" at "
;
MI
.
print
(
dbgs
(
)
)
;
)
;
toDel
.
push_back
(
r
)
;
}
while
(
!
toDel
.
empty
(
)
)
{
Chains
.
remove
(
toDel
.
back
(
)
)
;
toDel
.
pop_back
(
)
;
}
}
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
FMSUBSrrr
:
case
AArch64
::
FMADDSrrr
:
case
AArch64
::
FNMSUBSrrr
:
case
AArch64
::
FNMADDSrrr
:
case
AArch64
::
FMSUBDrrr
:
case
AArch64
::
FMADDDrrr
:
case
AArch64
::
FNMSUBDrrr
:
case
AArch64
::
FNMADDDrrr
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Ra
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
if
(
addIntraChainConstraint
(
G
,
Rd
,
Ra
)
)
addInterChainConstraint
(
G
,
Rd
,
Ra
)
;
break
;
}
case
AArch64
::
FMLAv2f32
:
case
AArch64
::
FMLSv2f32
:
{
unsigned
Rd
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
addInterChainConstraint
(
G
,
Rd
,
Rd
)
;
break
;
}
default
:
break
;
}
}
}
}
</s>

Apply the profile inference algorithm for a given function .


<s> bool AArch64PassConfig :: addInstSelector ( ) { addPass ( createAArch64ISelDag ( getAArch64TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64CleanupLocalDynamicTLSPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void PPCHazardRecognizer970 :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugValue ( ) ) return ; unsigned Opcode = MI -> getOpcode ( ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; PPCII :: PPC970_Unit InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == PPCII :: PPC970_Pseudo ) return ; if ( Opcode == PPC :: MTCTR || Opcode == PPC :: MTCTR8 ) HasCTRSet = true ; if ( isStore && NumStores < 4 && ! MI -> memoperands_empty ( ) ) { MachineMemOperand * MO = * MI -> memoperands_begin ( ) ; StoreSize [ NumStores ] = MO -> getSize ( ) ; StoreOffset [ NumStores ] = MO -> getOffset ( ) ; StoreValue [ NumStores ] = MO -> getValue ( ) ; ++ NumStores ; } if ( InstrType == PPCII :: PPC970_BRU || isSingle ) NumIssued = 4 ; ++ NumIssued ; if ( isCracked ) ++ NumIssued ; if ( NumIssued == 5 ) EndDispatchGroup ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> Cpu0TargetLowering :: ConstraintType Cpu0TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'c' : return C_RegisterClass ; case 'R' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
bool
SparcCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SparcTargetMachine
&
Target
=
static_cast
<
SparcTargetMachine
&
>
(
const_cast
<
TargetMachine
&
>
(
MF
.
getTarget
(
)
)
)
;
JTI
=
Target
.
getJITInfo
(
)
;
II
=
Target
.
getInstrInfo
(
)
;
TD
=
Target
.
getDataLayout
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
SparcSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
)
emitInstruction
(
*
I
++
,
*
MBB
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Sparc
Sparc
Sparc
Sparc
Sparc
"JITTing function '"
"'\n"


<s> static bool aarch64_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V4HFmode || mode == V8HFmode || mode == V1DFmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s>
const
char
*
nds32_output_stack_pop
(
rtx
par_rtx
ATTRIBUTE_UNUSED
)
{
char
pattern
[
100
]
;
rtx
operands
[
3
]
;
int
rb_eh_data
=
cfun
->
machine
->
eh_return_data_first_regno
;
int
re_eh_data
=
cfun
->
machine
->
eh_return_data_last_regno
;
int
first_eh_data_regno
=
EH_RETURN_DATA_REGNO
(
0
)
;
int
rb_callee_saved
=
cfun
->
machine
->
callee_saved_first_gpr_regno
;
int
re_callee_saved
=
cfun
->
machine
->
callee_saved_last_gpr_regno
;
if
(
reg_mentioned_p
(
gen_rtx_REG
(
SImode
,
first_eh_data_regno
)
,
par_rtx
)
)
{
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_eh_data
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_eh_data
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop.s\t%s"
,
"%0, %1, { }"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
if
(
TARGET_V3PUSH
&&
!
nds32_isr_function_p
(
current_function_decl
)
&&
(
cfun
->
machine
->
va_args_size
==
0
)
)
{
int
sp_adjust
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
sp_adjust
=
cfun
->
machine
->
local_size
+
cfun
->
machine
->
out_args_size
+
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
+
cfun
->
machine
->
callee_saved_fpr_regs_size
;
if
(
satisfies_constraint_Iu08
(
GEN_INT
(
sp_adjust
)
)
&&
NDS32_DOUBLE_WORD_ALIGN_P
(
sp_adjust
)
&&
!
cfun
->
calls_alloca
)
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
else
{
if
(
cfun
->
machine
->
callee_saved_first_fpr_regno
!=
SP_REGNUM
)
{
sp_adjust
=
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
+
cfun
->
machine
->
callee_saved_fpr_regs_size
;
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
}
else
{
operands
[
1
]
=
GEN_INT
(
0
)
;
}
}
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop25\t%%0, %%1"
)
;
}
else
{
int
pop_en4_only_p
=
0
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_callee_saved
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
if
(
!
cfun
->
machine
->
fp_size
&&
!
cfun
->
machine
->
gp_size
&&
!
cfun
->
machine
->
lp_size
&&
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
{
return
""
;
}
else
{
if
(
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
pop_en4_only_p
=
1
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop.s\t%s{%s%s%s }"
,
pop_en4_only_p
""
:
"%0, %1, "
,
cfun
->
machine
->
fp_size
" $fp"
:
""
,
cfun
->
machine
->
gp_size
" $gp"
:
""
,
cfun
->
machine
->
lp_size
" $lp"
:
""
)
;
}
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Function to output stack pop operation . We need to deal with normal stack pop multiple or stack v3pop .


<s> const uint32_t * ARM64RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: AnyReg ) return CSR_ARM64_AllRegs_RegMask ; else return CSR_ARM64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static struct unw_reg_state * alloc_reg_state ( void ) { struct unw_reg_state * rs ; reg_state_alloced ++ ; rs = malloc ( sizeof ( struct unw_reg_state ) ) ; if ( ! rs ) { int n = atomic_alloc ( & emergency_reg_state_free ) ; if ( n >= 0 ) rs = & emergency_reg_state [ n ] ; } return rs ; } </s>

Allocation and deallocation of structures .


<s> bool sh_loads_bankedreg_p ( rtx insn ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { rtx op = SET_DEST ( PATTERN ( insn ) ) ; if ( REG_P ( op ) && BANKED_REGISTER_P ( REGNO ( op ) ) ) return true ; } return false ; } </s>

Return true iff INSN loads a banked register .


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( size <= 6 * PROBE_INTERVAL ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( ix86_gen_probe_stack_range ( sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s>
const
char
*
nds32_output_32bit_load
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
;
code
=
XEXP
(
operands
[
1
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
GET_CODE
(
code
)
)
{
case
REG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci\t%%0, %%1"
,
size
)
;
break
;
case
SYMBOL_REF
:
case
CONST
:
operands
[
1
]
=
XEXP
(
operands
[
1
]
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci.gp\t%%0, [ + %%1]"
,
size
)
;
break
;
case
POST_INC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci.bi\t%%0, %%1, %d"
,
size
,
byte
)
;
break
;
case
POST_DEC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci.bi\t%%0, %%1, -%d"
,
size
,
byte
)
;
break
;
case
POST_MODIFY
:
switch
(
GET_CODE
(
XEXP
(
XEXP
(
code
,
1
)
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%c.bi\t%%0, %%1"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci.bi\t%%0, %%1"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
PLUS
:
switch
(
GET_CODE
(
XEXP
(
code
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%c\t%%0, %%1"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci\t%%0, %%1"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
LO_SUM
:
operands
[
2
]
=
XEXP
(
code
,
1
)
;
operands
[
1
]
=
XEXP
(
code
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci\t%%0, [%%1 + lo12(%%2)]"
,
size
)
;
break
;
default
:
abort
(
)
;
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>


<s>
bool
AArch64InstrInfo
::
isGPRZero
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
MOVZWi
:
case
AArch64
::
MOVZXi
:
if
(
MI
.
getOperand
(
1
)
.
isImm
(
)
&&
MI
.
getOperand
(
1
)
.
getImm
(
)
==
0
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
2
)
.
getImm
(
)
==
0
&&
"invalid MOVZi operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ANDWri
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
case
AArch64
::
ANDXri
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
;
case
TargetOpcode
::
COPY
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
}
return
false
;
}
</s>

Does this instruction set its full destination register to zero ?


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> const char * mips_msa_output_shift_immediate ( const char * shift , rtx * operands ) { rtx amount = operands [ 2 ] ; machine_mode mode = amount -> mode ; unsigned val = UINTVAL ( CONST_VECTOR_ELT ( amount , 0 ) ) ; val &= GET_MODE_UNIT_BITSIZE ( mode ) - 1 ; if ( ! val ) return "" ; rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; operands [ 2 ] = gen_const_vec_duplicate ( mode , c ) ; return shift ; } </s>

Return the assembly code for MSA immediate shift instructions , which has the operands given by OPERANDS . Truncate the shift amount to make GAS happy .


<s>
void
SystemZHazardRecognizer
::
emitInstruction
(
MachineInstr
*
MI
,
bool
TakenBranch
)
{
SUnit
SU
(
MI
,
0
)
;
SU
.
isCall
=
MI
->
isCall
(
)
;
const
MCSchedClassDesc
*
SC
=
SchedModel
->
resolveSchedClass
(
MI
)
;
for
(
const
MCWriteProcResEntry
&
PRE
:
make_range
(
SchedModel
->
getWriteProcResBegin
(
SC
)
,
SchedModel
->
getWriteProcResEnd
(
SC
)
)
)
{
switch
(
SchedModel
->
getProcResource
(
PRE
.
ProcResourceIdx
)
->
BufferSize
)
{
case
0
:
SU
.
hasReservedResource
=
true
;
break
;
case
1
:
SU
.
isUnbuffered
=
true
;
break
;
default
:
break
;
}
}
unsigned
GroupSizeBeforeEmit
=
CurrGroupSize
;
EmitInstruction
(
&
SU
)
;
if
(
!
TakenBranch
&&
isBranchRetTrap
(
MI
)
)
{
if
(
GroupSizeBeforeEmit
==
1
)
nextGroup
(
)
;
}
if
(
TakenBranch
&&
CurrGroupSize
>
0
)
nextGroup
(
)
;
assert
(
(
!
MI
->
isTerminator
(
)
||
isBranchRetTrap
(
MI
)
)
&&
"Scheduler: unhandled terminator!"
)
;
}
</s>


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( X86 :: RSP ) ; for ( MCSubRegIterator I ( X86 :: RSP , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; Reserved . set ( X86 :: RIP ) ; for ( MCSubRegIterator I ( X86 :: RIP , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; for ( MCSubRegIterator I ( X86 :: RBP , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( X86 :: CS ) ; Reserved . set ( X86 :: SS ) ; Reserved . set ( X86 :: DS ) ; Reserved . set ( X86 :: ES ) ; Reserved . set ( X86 :: FS ) ; Reserved . set ( X86 :: GS ) ; Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; if ( ! Is64Bit ) { Reserved . set ( X86 :: SIL ) ; Reserved . set ( X86 :: DIL ) ; Reserved . set ( X86 :: BPL ) ; Reserved . set ( X86 :: SPL ) ; for ( unsigned n = 0 ; n != 8 ; ++ n ) { static const uint16_t GPR64 [ ] = { X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 } ; for ( MCRegAliasIterator AI ( GPR64 [ n ] , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; assert ( X86 :: XMM15 == X86 :: XMM8 + 7 ) ; for ( MCRegAliasIterator AI ( X86 :: XMM8 + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> unsigned CSKYInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 0 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return 1 ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 1 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> static ARM64Operand * CreateReg ( unsigned RegNum , bool isVector , SMLoc S , SMLoc E , MCContext & Ctx ) { ARM64Operand * Op = new ARM64Operand ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . isVector = isVector ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static rtx arm_function_value ( const_tree type , const_tree func , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsignedp ATTRIBUTE_UNUSED ; rtx r ATTRIBUTE_UNUSED ; mode = TYPE_MODE ( type ) ; if ( TARGET_AAPCS_BASED ) return aapcs_allocate_return_reg ( mode , type , func ) ; if ( INTEGRAL_TYPE_P ( type ) ) mode = arm_promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } } return arm_libcall_value_1 ( mode ) ; } </s>

Define how to find the value returned by a function .


<s> static void mips16_split_long_branches ( void ) { bool something_changed ; if ( ! TARGET_MIPS16 ) return ; do { rtx_insn * insn ; shorten_branches ( get_insns ( ) ) ; something_changed = false ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( JUMP_P ( insn ) && get_attr_length ( insn ) > 4 && ( any_condjump_p ( insn ) || any_uncondjump_p ( insn ) ) ) { rtx old_label , temp , saved_temp ; rtx_code_label * new_label ; rtx target ; rtx_insn * jump , * jump_sequence ; start_sequence ( ) ; saved_temp = gen_rtx_REG ( Pmode , AT_REGNUM ) ; temp = gen_rtx_REG ( Pmode , GP_REG_FIRST + 2 ) ; emit_move_insn ( saved_temp , temp ) ; old_label = JUMP_LABEL ( insn ) ; target = gen_rtx_LABEL_REF ( Pmode , old_label ) ; mips16_load_branch_target ( temp , target ) ; jump = emit_jump_insn ( PMODE_INSN ( gen_indirect_jump_and_restore , ( temp , temp , saved_temp ) ) ) ; JUMP_LABEL ( jump ) = old_label ; LABEL_NUSES ( old_label ) ++ ; mips16_lay_out_constants ( false ) ; if ( simplejump_p ( insn ) ) new_label = NULL ; else { new_label = gen_label_rtx ( ) ; emit_label ( new_label ) ; } jump_sequence = get_insns ( ) ; end_sequence ( ) ; emit_insn_after ( jump_sequence , insn ) ; if ( new_label ) invert_jump ( insn , new_label , false ) ; else delete_insn ( insn ) ; something_changed = true ; } } while ( something_changed ) ; } </s>

If we 're compiling a MIPS16 function , look for and split any long branches . This must be called after all other instruction modifications in mips_reorg .


<s> static void do_load_for_compare ( rtx reg , rtx mem , machine_mode mode ) { switch ( GET_MODE ( reg ) ) { case DImode : switch ( mode ) { case QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case SImode : switch ( mode ) { case QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Figure out the correct instructions to generate to load data for block compare . MODE is used for the read from memory , and data is zero extended if REG is wider than MODE . If LE code is being generated , bswap loads are used . REG is the destination register to move the data into . MEM is the memory block being read . MODE is the mode of memory to use for the read .


<s> void SparcInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! printAliasInstr ( MI , Address , STI , O ) && ! printSparcAliasInstr ( MI , STI , O ) ) printInstruction ( MI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool rs6000_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if TYPE must be passed on the stack and not in registers .