<s> void final_prescan_insn ( rtx_insn * insn , rtx opvec [ ] ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) { if ( dslots_number_nops > 0 ) { rtx pattern = PATTERN ( insn ) ; int length = get_attr_length ( insn ) ; if ( length == 0 || ( iq2000_load_reg != 0 && reg_mentioned_p ( iq2000_load_reg , pattern ) ) || ( iq2000_load_reg2 != 0 && reg_mentioned_p ( iq2000_load_reg2 , pattern ) ) || ( iq2000_load_reg3 != 0 && reg_mentioned_p ( iq2000_load_reg3 , pattern ) ) || ( iq2000_load_reg4 != 0 && reg_mentioned_p ( iq2000_load_reg4 , pattern ) ) ) fputs ( "\tnop\n" , asm_out_file ) ; else dslots_load_filled ++ ; while ( -- dslots_number_nops > 0 ) fputs ( "\tnop\n" , asm_out_file ) ; iq2000_load_reg = 0 ; iq2000_load_reg2 = 0 ; iq2000_load_reg3 = 0 ; iq2000_load_reg4 = 0 ; } if ( ( JUMP_P ( insn ) || CALL_P ( insn ) || ( GET_CODE ( PATTERN ( insn ) ) == RETURN ) ) && NEXT_INSN ( PREV_INSN ( insn ) ) == insn ) { rtx_insn * tmp = insn ; while ( NEXT_INSN ( tmp ) && NOTE_P ( NEXT_INSN ( tmp ) ) && NOTE_KIND ( NEXT_INSN ( tmp ) ) == NOTE_INSN_CALL_ARG_LOCATION ) tmp = NEXT_INSN ( tmp ) ; rtx_insn * nop_insn = emit_insn_after ( gen_nop ( ) , tmp ) ; INSN_ADDRESSES_NEW ( nop_insn , - 1 ) ; } if ( TARGET_STATS && ( JUMP_P ( insn ) || CALL_P ( insn ) ) ) dslots_jump_total ++ ; } </s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , MF . getTarget ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void SystemZPassConfig :: addPreRegAlloc ( ) { addPass ( createSystemZCopyPhysRegsPass ( getSystemZTargetMachine ( ) ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
void
ARMConstantIslands
::
verify
(
)
{
for
(
MachineFunction
::
iterator
MBBI
=
MF
->
begin
(
)
,
E
=
MF
->
end
(
)
;
MBBI
!=
E
;
++
MBBI
)
{
MachineBasicBlock
*
MBB
=
&
*
MBBI
;
unsigned
MBBId
=
MBB
->
getNumber
(
)
;
assert
(
!
MBBId
||
BBInfo
[
MBBId
1
]
.
postOffset
(
)
<=
BBInfo
[
MBBId
]
.
Offset
)
;
}
DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
1
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> enum reg_class mt_secondary_reload_class ( enum reg_class class ATTRIBUTE_UNUSED , enum machine_mode mode , rtx x ) { if ( ( mode == QImode && ( ! TARGET_BYTE_ACCESS ) ) || mode == HImode ) { if ( GET_CODE ( x ) == MEM || ( GET_CODE ( x ) == REG && true_regnum ( x ) == - 1 ) || ( GET_CODE ( x ) == SUBREG && ( GET_CODE ( SUBREG_REG ( x ) ) == MEM || ( GET_CODE ( SUBREG_REG ( x ) ) == REG && true_regnum ( SUBREG_REG ( x ) ) == - 1 ) ) ) ) return GENERAL_REGS ; } return NO_REGS ; } </s>


<s> static void mips_sim_issue_insn ( struct mips_sim * state , rtx_insn * insn ) { curr_state = state -> dfa_state ; state_transition ( curr_state , insn ) ; state -> insns_left = targetm . sched . variable_issue ( 0 , false , insn , state -> insns_left ) ; mips_sim_insn = insn ; note_stores ( PATTERN ( insn ) , mips_sim_record_set , state ) ; } </s>

Issue instruction INSN in scheduler state STATE . Assume that INSN can issue immediately ( i.e. , that mips_sim_wait_insn has already been called ) .


<s> const SparcInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> const uint32_t * Cpu0RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool aarch64_harden_sls_retbr_p ( void ) { return aarch64_sls_hardening & SLS_RETBR ; } </s>

Return whether we should mitigatate Straight Line Speculation for the RET and BR instructions .


"You cannot take the address of a nested function if you use "

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> const AArch64InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = & ARM :: DPRRegClass ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = 2 ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = & ARM :: DPRRegClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = & ARM :: DPRRegClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = & ARM :: DPRRegClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> void MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsConstantIslandPass ( TM ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> int xstormy16_below100_symbol ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) != 0 ; if ( GET_CODE ( x ) == CONST_INT ) { HOST_WIDE_INT i = INTVAL ( x ) ; if ( ( i >= 0x0000 && i <= 0x00ff ) || ( i >= 0x7f00 && i <= 0x7fff ) ) return 1 ; } return 0 ; } </s>

Predicate for symbols and addresses that reflect special 8-bit addressing .


<s> static void sparc_dwarf_handle_frame_unspec ( const char * label , rtx pattern ATTRIBUTE_UNUSED , int index ATTRIBUTE_UNUSED ) { gcc_assert ( index == UNSPECV_SAVEW ) ; dwarf2out_window_save ( label ) ; } </s>

Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook . This is called from dwarf2out.c to emit call frame instructions for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs .


<s> void i386_pe_declare_function_type ( FILE * file , const char * name , int public ) { fprintf ( file , "\t.def\t" ) ; assemble_name ( file , name ) ; fprintf ( file , ";\t.scl\t%d;\t.type\t%d;\t.endef\n" , public ? ( int ) C_EXT : ( int ) C_STAT , ( int ) DT_FCN << N_BTSHFT ) ; } </s>

Mark a function appropriately . This should only be called for functions for which we are not emitting COFF debugging information . FILE is the assembler output file , NAME is the name of the function , and PUBLIC is nonzero if the function is globally visible .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
break
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> static void tryAddingPcLoadReferenceComment ( uint64_t Address , int Value , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; Dis -> tryAddingPcLoadReferenceComment ( Value , Address ) ; } </s>

Try to add a comment on the PC-relative load .


"PPC hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


"CAHP DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> bool X86ATTAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo , "mem" , true ) ; return false ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MI -> getOperand ( OpNo ) . isReg ( ) ) return printAsmMRegister ( MI -> getOperand ( OpNo ) , ExtraCode [ 0 ] ) ; printOperand ( MI , OpNo ) ; return false ; case 'P' : printOperand ( MI , OpNo , "mem" , true ) ; return false ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
uint64_t
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void i386_pe_maybe_record_exported_symbol ( tree decl , const char * name , int is_data ) { rtx symbol ; struct export_list * p ; if ( ! decl ) return ; symbol = XEXP ( DECL_RTL ( decl ) , 0 ) ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; if ( ! SYMBOL_REF_DLLEXPORT_P ( symbol ) ) return ; gcc_assert ( TREE_PUBLIC ( decl ) ) ; p = ggc_alloc < export_list > ( ) ; p -> next = export_head ; p -> name = name ; p -> is_data = is_data ; export_head = p ; } </s>

Assemble an export symbol entry . We need to keep a list of these , so that we can output the export list at the end of the assembly . We used to output these export symbols in each function , but that causes problems with GNU ld when the sections are linkonce . Beware , DECL may be NULL if compile_file ( ) is emitting the LTO marker .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static bool spe_func_has_64bit_regs_p ( void ) { rtx_insn * insns , * insn ; if ( crtl -> calls_eh_return || cfun -> calls_setjmp || crtl -> has_nonlocal_goto ) return true ; insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == TFmode ) ) return true ; } } } return false ; } </s>

Return true if the current function uses any GPRs in 64-bit SIMD mode .


<s> static int ix86_nsaved_sseregs ( void ) { int nregs = 0 ; int regno ; if ( ! TARGET_64BIT_MS_ABI ) return 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) nregs ++ ; return nregs ; } </s>


<s> static rtx spe_synthesize_frame_save ( rtx real ) { rtx synth , offset , reg , real2 ; if ( GET_CODE ( real ) != SET || GET_MODE ( SET_SRC ( real ) ) != V2SImode ) return real ; gcc_assert ( GET_CODE ( SET_DEST ( real ) ) == MEM && GET_CODE ( XEXP ( SET_DEST ( real ) , 0 ) ) == PLUS && GET_CODE ( SET_SRC ( real ) ) == REG ) ; real2 = copy_rtx ( real ) ; PUT_MODE ( SET_DEST ( real2 ) , SImode ) ; reg = SET_SRC ( real2 ) ; real2 = replace_rtx ( real2 , reg , gen_rtx_REG ( SImode , REGNO ( reg ) ) ) ; synth = copy_rtx ( real2 ) ; if ( BYTES_BIG_ENDIAN ) { offset = XEXP ( XEXP ( SET_DEST ( real2 ) , 0 ) , 1 ) ; real2 = replace_rtx ( real2 , offset , GEN_INT ( INTVAL ( offset ) + 4 ) ) ; } reg = SET_SRC ( synth ) ; synth = replace_rtx ( synth , reg , gen_rtx_REG ( SImode , REGNO ( reg ) + 1200 ) ) ; offset = XEXP ( XEXP ( SET_DEST ( synth ) , 0 ) , 1 ) ; synth = replace_rtx ( synth , offset , GEN_INT ( INTVAL ( offset ) + ( BYTES_BIG_ENDIAN ? 0 : 4 ) ) ) ; RTX_FRAME_RELATED_P ( synth ) = 1 ; RTX_FRAME_RELATED_P ( real2 ) = 1 ; if ( BYTES_BIG_ENDIAN ) real = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , synth , real2 ) ) ; else real = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , real2 , synth ) ) ; return real ; } </s>

Given an SPE frame note , return a PARALLEL of SETs with the original note , plus a synthetic register save .


<s> static bool aarch64_legitimize_address_displacement ( rtx * disp , rtx * off , machine_mode mode ) { HOST_WIDE_INT offset = INTVAL ( * disp ) ; HOST_WIDE_INT base = offset & ~ ( GET_MODE_SIZE ( mode ) < 4 ? 0xfff : 0x3ffc ) ; if ( mode == TImode || mode == TFmode || ( offset & ( GET_MODE_SIZE ( mode ) - 1 ) ) != 0 ) base = ( offset + 0x100 ) & ~ 0x1ff ; * off = GEN_INT ( base ) ; * disp = GEN_INT ( offset - base ) ; return true ; } </s>

Split an out-of-range address displacement into a base and offset . Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise to increase opportunities for sharing the base address of different sizes . For unaligned accesses and TI/TF mode use the signed 9-bit range .


<s> static void ix86_avx256_split_vector_move_misalign ( rtx op0 , rtx op1 ) { rtx m ; rtx ( * extract ) ( rtx , rtx , rtx ) ; machine_mode mode ; if ( ( MEM_P ( op1 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_LOAD ) || ( MEM_P ( op0 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_STORE ) ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } rtx orig_op0 = NULL_RTX ; mode = GET_MODE ( op0 ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case V8SFmode : extract = gen_avx_vextractf128v8sf ; mode = V4SFmode ; break ; case V4DFmode : extract = gen_avx_vextractf128v4df ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , 0 ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , 16 ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( MEM_P ( op0 ) ) { m = adjust_address ( op0 , mode , 0 ) ; emit_insn ( extract ( m , op1 , const0_rtx ) ) ; m = adjust_address ( op0 , mode , 16 ) ; emit_insn ( extract ( m , copy_rtx ( op1 ) , const1_rtx ) ) ; } else gcc_unreachable ( ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; } </s>

Split 32-byte AVX unaligned load and store if needed .


<s> const std :: string & ARMToARMStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s> static void emitConstantPool ( MCStreamer & Streamer , const MCSection * Section , ConstantPool & CP ) { if ( ! CP . empty ( ) ) { Streamer . SwitchSection ( Section ) ; CP . emitEntries ( Streamer ) ; } } </s>

Print to the current output stream assembly representations of the constants in the constant pool MCP .


<s> bool SystemZPassConfig :: addPreEmitPass ( ) { addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool mmix_print_operand_punct_valid_p ( unsigned char code ) { return code == '+' || code == '.' || code == '!' ; } </s>


<s> static rtx ix86_builtin_setjmp_frame_value ( void ) { return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx ; } </s>

In a dynamically-aligned function , we ca n't know the offset from stack pointer to frame pointer , so we must ensure that setjmp eliminates fp against the hard fp ( % ebp ) rather than trying to index from % esp up to the top of the frame across a gap that is of unknown ( at compile-time ) size .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } return false ; } </s>


<s> static bool loongarch_print_operand_punct_valid_p ( unsigned char code ) { return loongarch_print_operand_punct [ code ] ; } </s>


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F , PromotionCacheTy & PromotionCache ) { SmallVector < UpdateRecord , 64 > Updates ; for ( Instruction & I : instructions ( & F ) ) { for ( Use & U : I . operands ( ) ) { Constant * Cst = dyn_cast < Constant > ( U ) ; if ( ! Cst || isa < GlobalValue > ( Cst ) || isa < ConstantExpr > ( Cst ) ) continue ; if ( ! shouldConvert ( * Cst , PromotionCache ) ) continue ; unsigned OpNo = & U - I . op_begin ( ) ; if ( ! shouldConvertUse ( Cst , & I , OpNo ) ) continue ; Updates . emplace_back ( Cst , & I , OpNo ) ; } } if ( Updates . empty ( ) ) return false ; promoteConstants ( F , Updates , PromotionCache ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool ARMWinCOFFObjectWriter :: recordRelocation ( const MCFixup & Fixup ) const { return static_cast < unsigned > ( Fixup . getKind ( ) ) != ARM :: fixup_t2_movt_hi16 ; } </s>


<s> bool ix86_expand_pinsr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 3 ] ; unsigned int size = INTVAL ( operands [ 1 ] ) ; unsigned int pos = INTVAL ( operands [ 2 ] ) ; if ( GET_CODE ( dst ) == SUBREG ) { pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } if ( GET_CODE ( src ) == SUBREG ) src = SUBREG_REG ( src ) ; switch ( GET_MODE ( dst ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ; srcmode = mode_for_size ( size , MODE_INT , 0 ) ; switch ( srcmode ) { case QImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V16QImode ; pinsr = gen_sse4_1_pinsrb ; break ; case HImode : if ( ! TARGET_SSE2 ) return false ; dstmode = V8HImode ; pinsr = gen_sse2_pinsrw ; break ; case SImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V4SImode ; pinsr = gen_sse4_1_pinsrd ; break ; case DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; dstmode = V2DImode ; pinsr = gen_sse4_1_pinsrq ; break ; default : return false ; } rtx d = dst ; if ( GET_MODE ( dst ) != dstmode ) d = gen_reg_rtx ( dstmode ) ; src = gen_lowpart ( srcmode , src ) ; pos /= size ; emit_insn ( pinsr ( d , gen_lowpart ( dstmode , dst ) , src , GEN_INT ( 1 << pos ) ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an insert into a vector register through pinsr insn . Return true if successful .


<s> virtual const Dcpu16InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
void
VEFrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedRegs
,
RegScavenger
*
RS
)
const
{
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedRegs
,
RS
)
;
assert
(
isLeafProc
(
MF
)
&&
"TODO implement for non-leaf procs"
)
;
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

VE
VE
"TODO implement for non-leaf procs"


<s> bool MipsTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void aarch64_asm_file_end ( ) { aarch64_sls_emit_shared_blr_thunks ( asm_out_file ) ; TARGET_ASM_FILE_END ( ) ; } </s>


<s> static int no_previous_def ( tree function_name ) { tree branch_island ; for ( branch_island = branch_island_list ; branch_island ; branch_island = TREE_CHAIN ( branch_island ) ) if ( function_name == BRANCH_ISLAND_FUNCTION_NAME ( branch_island ) ) return 0 ; return 1 ; } </s>

NO_PREVIOUS_DEF checks in the link list whether the function name is already there or not .


"Unexpected register class in CSRsViaCopy!"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SDValue X86TargetLowering :: getSqrtEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) && Reciprocal ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE2 ( ) && ! Reciprocal ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) || ( VT == MVT :: v16f32 && Subtarget . useAVX512Regs ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; UseOneConstNR = false ; unsigned Opcode = VT == MVT :: v16f32 ? X86ISD :: RSQRT14 : X86ISD :: FRSQRT ; return DAG . getNode ( Opcode , DL , VT , Op ) ; } if ( VT . getScalarType ( ) == MVT :: f16 && isTypeLegal ( VT ) && Subtarget . hasFP16 ( ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 0 ; if ( VT == MVT :: f16 ) { SDValue Zero = DAG . getIntPtrConstant ( 0 , DL ) ; SDValue Undef = DAG . getUNDEF ( MVT :: v8f16 ) ; Op = DAG . getNode ( ISD :: SCALAR_TO_VECTOR , DL , MVT :: v8f16 , Op ) ; Op = DAG . getNode ( X86ISD :: RSQRT14S , DL , MVT :: v8f16 , Undef , Op ) ; return DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , MVT :: f16 , Op , Zero ) ; } return DAG . getNode ( X86ISD :: RSQRT14 , DL , VT , Op ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> int mmix_opposite_regno ( int regno , int incoming ) { if ( incoming && regno == MMIX_OUTGOING_RETURN_VALUE_REGNUM ) return MMIX_RETURN_VALUE_REGNUM ; if ( ! incoming && regno == MMIX_RETURN_VALUE_REGNUM ) return MMIX_OUTGOING_RETURN_VALUE_REGNUM ; if ( ! mmix_function_arg_regno_p ( regno , incoming ) ) return regno ; return regno - ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM - MMIX_FIRST_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM - MMIX_FIRST_INCOMING_ARG_REGNUM ) ; } </s>

INCOMING_REGNO and OUTGOING_REGNO worker function . Those two macros must only be applied to function argument registers and the function return value register for the opposite use . FIXME : for their current use in gcc , it 'd be better with an explicit specific additional FUNCTION_INCOMING_ARG_REGNO_P a'la TARGET_FUNCTION_ARG / TARGET_FUNCTION_INCOMING_ARG instead of forcing the target to commit to a fixed mapping and for any unspecified register use . Particularly when thinking about the return-value , it is better to imagine INCOMING_REGNO and OUTGOING_REGNO as named CALLEE_TO_CALLER_REGNO and INNER_REGNO as named CALLER_TO_CALLEE_REGNO because the direction . The `` incoming '' and `` outgoing '' is from the perspective of the parameter-registers , but the same macro is ( must be , lacking an alternative like suggested above ) used to map the return-value-register from the same perspective . To make directions even more confusing , the macro MMIX_OUTGOING_RETURN_VALUE_REGNUM holds the number of the register in which to return a value , i.e . INCOMING_REGNO for the return-value- register as received from a called function ; the return-value on the way out .


<s> static bool pru_function_value_regno_p ( const unsigned int regno ) { return regno == FIRST_RETVAL_REGNUM ; } </s>


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? support :: endian :: read32le ( Bytes . data ( ) ) : support :: endian :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } else if ( STI . getFeatureBits ( ) [ PPC :: FeatureSPE ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .

PowerPC PPC 4 4 0 support::endian support::endian PPC::FeatureQPX PPC::FeatureSPE


<s> unsigned AArch64TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL , bool UseScalable ) const { unsigned VecSize = UseScalable ? Subtarget -> getMinSVEVectorSizeInBits ( ) : 128 ; return std :: max < unsigned > ( 1 , ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / VecSize ) ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


<s> static void or1k_output_mi_thunk ( FILE * file , tree thunk_fndecl , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = 1 ; epilogue_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 4 ) ; else this_rtx = gen_rtx_REG ( Pmode , 3 ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! satisfies_constraint_I ( delta_rtx ) ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; HOST_WIDE_INT lo = sext_hwi ( vcall_offset , 16 ) ; HOST_WIDE_INT hi = vcall_offset - lo ; rtx tmp ; tmp = gen_rtx_MEM ( Pmode , this_rtx ) ; emit_move_insn ( scratch , tmp ) ; if ( hi != 0 ) { rtx scratch2 = gen_rtx_REG ( Pmode , RV_REGNUM ) ; emit_move_insn ( scratch2 , GEN_INT ( hi ) ) ; emit_insn ( gen_add2_insn ( scratch , scratch2 ) ) ; } tmp = plus_constant ( Pmode , scratch , lo ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( scratch , tmp ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; gcc_assert ( SYMBOL_REF_LOCAL_P ( funexp ) ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; epilogue_completed = 0 ; } </s>

Worker for TARGET_ASM_OUTPUT_MI_THUNK . Output the assembler code for a thunk function . THUNK_DECL is the declaration for the thunk function itself , FUNCTION is the decl for the target function . DELTA is an immediate constant offset to be added to THIS . If VCALL_OFFSET is nonzero , the word at address ( * THIS + VCALL_OFFSET ) should be additionally added to THIS .


<s> static bool index_term_p ( rtx prod , machine_mode mode , bool strict ) { rtx xfoo0 , xfoo1 ; bool log_p ; if ( GET_MODE_SIZE ( mode ) == 1 ) return BASE_REGISTER_P ( prod , strict ) ; if ( ( GET_CODE ( prod ) != MULT && GET_CODE ( prod ) != ASHIFT ) || GET_MODE_SIZE ( mode ) > 8 ) return false ; log_p = GET_CODE ( prod ) == ASHIFT ; xfoo0 = XEXP ( prod , 0 ) ; xfoo1 = XEXP ( prod , 1 ) ; if ( CONST_INT_P ( xfoo0 ) && GET_MODE_SIZE ( mode ) == ( log_p ? 1 << INTVAL ( xfoo0 ) : INTVAL ( xfoo0 ) ) && INDEX_REGISTER_P ( xfoo1 , strict ) ) return true ; if ( CONST_INT_P ( xfoo1 ) && GET_MODE_SIZE ( mode ) == ( log_p ? 1 << INTVAL ( xfoo1 ) : INTVAL ( xfoo1 ) ) && INDEX_REGISTER_P ( xfoo0 , strict ) ) return true ; return false ; } </s>

1 if PROD is either a reg times size of mode MODE and MODE is less than or equal 8 bytes , or just a reg if MODE is one byte .


"64-bit code requested on a subtarget that doesn't "

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> std :: pair < unsigned , const TargetRegisterClass * > MipsTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'd' : case 'y' : case 'r' : return std :: make_pair ( 0U , Mips :: CPURegsRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , Mips :: FGR32RegisterClass ) ; if ( VT == MVT :: f64 ) if ( ( ! Subtarget -> isSingleFloat ( ) ) && ( ! Subtarget -> isFP64bit ( ) ) ) return std :: make_pair ( 0U , Mips :: AFGR64RegisterClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void aarch64_emit_store_exclusive ( machine_mode mode , rtx bval , rtx rval , rtx mem , rtx model_rtx ) { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_QImode : gen = gen_aarch64_store_exclusiveqi ; break ; case E_HImode : gen = gen_aarch64_store_exclusivehi ; break ; case E_SImode : gen = gen_aarch64_store_exclusivesi ; break ; case E_DImode : gen = gen_aarch64_store_exclusivedi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( bval , rval , mem , model_rtx ) ) ; } </s>


<s>
void
ARMBaseInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
STR
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
||
RC
==
ARM
::
DPR_VFP2RegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FSTD
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
SPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FSTS
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
{
assert
(
RC
==
ARM
::
QPRRegisterClass
&&
"Unknown regclass!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VSTRQ
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> StringRef getPassName ( ) const override { return AARCH64_DEAD_REG_DEF_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static int loongarch_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { reg_class_t dregs ; int cost1 , cost2 ; from = loongarch_canonicalize_move_class ( from ) ; to = loongarch_canonicalize_move_class ( to ) ; if ( from == FP_REGS ) { if ( to == FP_REGS && loongarch_mode_ok_for_mov_fmt_p ( mode ) ) return 4 ; } dregs = GENERAL_REGS ; if ( from == dregs ) return loongarch_move_from_gpr_cost ( to ) ; if ( to == dregs ) return loongarch_move_to_gpr_cost ( from ) ; cost1 = loongarch_move_to_gpr_cost ( from ) ; if ( cost1 != 0 ) { cost2 = loongarch_move_from_gpr_cost ( to ) ; if ( cost2 != 0 ) return cost1 + cost2 ; } return 0 ; } </s>

Implement TARGET_REGISTER_MOVE_COST . Return 0 for classes that are the maximum of the move costs for subclasses ; regclass will work out the maximum for us .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


"The destination address is not aligned to a word"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static inline bool is_fast_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , "fast_interrupt" ) ; } </s>

Returns true if the provided function has the `` fast_interrupt '' attribute .


<s> static struct mips_multi_member * mips_multi_add ( void ) { mips_multi_member empty ; return mips_multi_members . safe_push ( empty ) ; } </s>

Add a new , uninitialized member to the current multi-insn sequence .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { bool has64BitAtomicLoad ; if ( Subtarget -> isMClass ( ) ) has64BitAtomicLoad = false ; else if ( Subtarget -> isThumb ( ) ) has64BitAtomicLoad = Subtarget -> hasV7Ops ( ) ; else has64BitAtomicLoad = Subtarget -> hasV6Ops ( ) ; unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size == 64 && has64BitAtomicLoad ) ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> static void mips_annotate_pic_call_expr ( rtx call , rtx symbol ) { rtx args_size ; args_size = XEXP ( call , 1 ) ; XEXP ( call , 1 ) = gen_rtx_UNSPEC ( GET_MODE ( args_size ) , gen_rtvec ( 2 , args_size , symbol ) , UNSPEC_CALL_ATTR ) ; } </s>

Replace the args_size operand of the call expression CALL with the call-attribute UNSPEC and fill in SYMBOL as the function symbol .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createX86LowerAMXIntrinsicsPass ( ) ) ; addPass ( createX86LowerAMXTypePass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } if ( TM -> Options . JMCInstrument ) addPass ( createJMCInstrumenterPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
const
char
*
thumb2_output_casesi
(
rtx
*
operands
)
{
rtx
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
2
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
output_asm_insn
(
"cmp\t%0, %1"
,
operands
)
;
output_asm_insn
(
"bhi\t%l3"
,
operands
)
;
switch
(
GET_MODE
(
diff_vec
)
)
{
case
QImode
:
return
"tbb\t[%|pc, %0]"
;
case
HImode
:
return
"tbh\t[%|pc, %0, lsl #1]"
;
case
SImode
:
if
(
flag_pic
)
{
output_asm_insn
(
"adr\t%4, %l2"
,
operands
)
;
output_asm_insn
(
"ldr\t%5, [%4, %0, lsl #2]"
,
operands
)
;
output_asm_insn
(
"add\t%4, %4, %5"
,
operands
)
;
return
"bx\t%4"
;
}
else
{
output_asm_insn
(
"adr\t%4, %l2"
,
operands
)
;
return
"ldr\t%|pc, [%4, %0, lsl #2]"
;
}
default
:
gcc_unreachable
(
)
;
}
}
</s>


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= ExpandFPMLxInstructions ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool rs6000_is_valid_shift_mask ( rtx mask , rtx shift , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = - 1 ; if ( CONST_INT_P ( XEXP ( shift , 1 ) ) ) { sh = INTVAL ( XEXP ( shift , 1 ) ) ; if ( sh < 0 || sh >= n ) return false ; } rtx_code code = GET_CODE ( shift ) ; if ( sh == 0 ) code = ROTATE ; if ( code == ROTATE && sh >= 0 && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= 0 && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( nb == 63 || ne == 0 || ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < 32 && ne < 32 && sh < 32 ) ; if ( ne > nb ) return false ; if ( sh < 0 ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < 32 && ne < 32 && sh < 32 && ! ( code == LSHIFTRT && nb >= 32 - sh ) ) return true ; if ( code == LSHIFTRT ) sh = 64 - sh ; if ( nb == 63 || ne == 0 || ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlw [ i ] nm , rld [ i ] cl , rld [ i ] cr , or rld [ i ] c instruction , to implement an AND with shift SHIFT ( a ROTATE , ASHIFT , or LSHIFTRT ) in mode MODE .


<s> bool AArch64TargetLowering :: shouldExpandGetActiveLaneMask ( EVT ResVT , EVT OpVT ) const { if ( ! Subtarget -> hasSVE ( ) ) return true ; if ( ResVT != MVT :: nxv2i1 && ResVT != MVT :: nxv4i1 && ResVT != MVT :: nxv8i1 && ResVT != MVT :: nxv16i1 && ResVT != MVT :: v2i1 && ResVT != MVT :: v4i1 && ResVT != MVT :: v8i1 && ResVT != MVT :: v16i1 ) return true ; if ( OpVT != MVT :: i32 && OpVT != MVT :: i64 ) return true ; return false ; } </s>

Return true if the @ llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder .


"  Skipping pass: no machine model present.\n"


<s> rtx sparc_builtin_saveregs ( ) { int first_reg = current_function_args_info . words ; rtx address ; int regno ; for ( regno = first_reg ; regno < NPARM_REGS ( word_mode ) ; regno ++ ) emit_move_insn ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + ( UNITS_PER_WORD * regno ) ) ) ) , gen_rtx_REG ( word_mode , BASE_INCOMING_ARG_REG ( word_mode ) + regno ) ) ; address = gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + UNITS_PER_WORD * first_reg ) ) ; return address ; } </s>

Do what is necessary for ` va_start ' . We look at the current function to determine if stdarg or varargs is used and return the address of the first unnamed parameter .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
RM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
IsAndroid
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> static rsqrte_type get_rsqrte_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrtedf ; case SFmode : return gen_aarch64_rsqrtesf ; case V2DFmode : return gen_aarch64_rsqrtev2df ; case V2SFmode : return gen_aarch64_rsqrtev2sf ; case V4SFmode : return gen_aarch64_rsqrtev4sf ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root initial estimate insn depending on machine mode .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: LXV : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : case PPC :: SPILLTOVSR_LD : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> virtual void print ( raw_ostream & OS ) const { llvm_unreachable ( "unimplemented!" ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> void CSKYInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCInst * NewMI = MI ; if ( NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> MachineInstr * ARMBaseInstrInfo :: duplicate ( MachineInstr * Orig , MachineFunction & MF ) const { MachineInstr * MI = TargetInstrInfo :: duplicate ( Orig , MF ) ; switch ( Orig -> getOpcode ( ) ) { case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { unsigned CPI = Orig -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; Orig -> getOperand ( 1 ) . setIndex ( CPI ) ; Orig -> getOperand ( 2 ) . setImm ( PCLabelId ) ; break ; } } return MI ; } </s>

Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore .


<s> void reset ( ) { FnStartLocs = Locs ( ) ; CantUnwindLocs = Locs ( ) ; PersonalityLocs = Locs ( ) ; HandlerDataLocs = Locs ( ) ; PersonalityIndexLocs = Locs ( ) ; FPReg = ARM :: SP ; } </s>

Reset an existing scalar value for Def and a given Instance .


Function to check whether the OP is a valid load/store operation . This is a helper function for the predicates : 'nds32_load_multiple_operation ' and 'nds32_store_multiple_operation ' in predicates.md file . The OP is supposed to be a parallel rtx . For each element within this parallel rtx : ( set ( reg ) ( mem addr ) ) is the form for load operation . ( set ( mem addr ) ( reg ) ) is the form for store operation . We have to extract reg and mem of every element and check if the information is valid for multiple load/store operation .


<s> static bool mips_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; int i , nelt , which ; unsigned char orig_perm [ MAX_VECT_LEN ] ; bool ok ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( vmode ) ; d . testing_p = ! target ; memset ( orig_perm , 0 , MAX_VECT_LEN ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { int ei = sel [ i ] & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = d . op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = d . op0 ; d . one_vector_p = true ; break ; } if ( d . testing_p ) { d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ok ; } ok = mips_expand_vec_perm_const_1 ( & d ) ; if ( ! ok && which == 3 ) { d . op0 = op0 ; d . op1 = op1 ; d . one_vector_p = false ; memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; } return ok ; } </s>


<s> bool AZPRPassConfig :: addInstSelector ( ) { addPass ( createAZPRISelDag ( getAZPRTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LW
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
{
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
isMips1
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LDC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
MBB
.
getParent
(
)
->
getTarget
(
)
.
getRegisterInfo
(
)
;
const
unsigned
*
SubSet
=
TRI
->
getSubRegisters
(
DestReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
0
]
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
1
]
)
.
addImm
(
4
)
.
addFrameIndex
(
FI
)
;
}
}
else
llvm_unreachable
(
"Register class not handled!"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> MachineBasicBlock :: iterator Cpu0FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool rs6000_emit_move_si_sf_subreg ( rtx dest , rtx source , machine_mode mode ) { if ( TARGET_DIRECT_MOVE_64BIT && ! reload_in_progress && ! reload_completed && ! lra_in_progress && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ; return true ; } } return false ; } </s>

Helper function to change moves with : ( SUBREG : SF ( REG : SI ) ) and ( SUBREG : SI ( REG : SF ) ) into separate UNSPEC insns . In the PowerPC architecture , scalar SFmode values are stored as DFmode values in the VSX registers . We need to convert the bits before we can use a direct move or operate on the bits in the vector register as an integer type . Skip things like ( set ( SUBREG : SI ( ... ) ( SUBREG : SI ( ... ) ) .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } } </s>


<s>
static
void
rs6000_parse_tls_size_option
(
void
)
{
if
(
rs6000_tls_size_string
==
0
)
return
;
else
if
(
strcmp
(
rs6000_tls_size_string
,
"16"
)
==
0
)
rs6000_tls_size
=
16
;
else
if
(
strcmp
(
rs6000_tls_size_string
,
"32"
)
==
0
)
rs6000_tls_size
=
32
;
else
if
(
strcmp
(
rs6000_tls_size_string
,
"64"
)
==
0
)
rs6000_tls_size
=
64
;
else
error
(
"bad value %qs for -mtls-size switch"
,
rs6000_tls_size_string
)
;
}
</s>

Validate and record the size specified with the -mtls-size option .


<s> static sbitmap aarch64_components_for_bb ( basic_block bb ) { bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; function_abi_aggregator callee_abis ; rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( CALL_P ( insn ) ) callee_abis . note_callee_abi ( insn_callee_abi ( insn ) ) ; HARD_REG_SET extra_caller_saves = callee_abis . caller_save_regs ( * crtl -> abi ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { bitmap_set_bit ( components , regno ) ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; unsigned regno2 = multiple_p ( offset , 16 ) ? regno + 1 : regno - 1 ; if ( regno2 <= LAST_SAVED_REGNUM ) { poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( regno < regno2 ? known_eq ( offset + 8 , offset2 ) : multiple_p ( offset2 , 16 ) && known_eq ( offset2 + 8 , offset ) ) bitmap_set_bit ( components , regno2 ) ; } } return components ; } </s>


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool swiftAsyncContextIsDynamicallySet ( ) const { const Triple & TT = getTargetTriple ( ) ; unsigned Major = TT . getOSVersion ( ) . getMajor ( ) ; switch ( TT . getOS ( ) ) { default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < 15 ; case Triple :: WatchOS : return Major < 8 ; case Triple :: MacOSX : case Triple :: Darwin : return Major < 12 ; } } </s>

Return whether FrameLowering should always set the `` extended frame present '' bit in FP , or set it based on a symbol in the runtime .


<s> bool csky_label_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == LABEL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( csky_label_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && csky_label_mentioned_p ( XEXP ( x , i ) ) ) return true ; } return false ; } </s>

Return TRUE if X references a LABEL_REF .


<s> static enum aarch64_parse_opt_result aarch64_parse_tune ( const char * to_parse , const struct processor * * res ) { const struct processor * cpu ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strcmp ( cpu -> name , to_parse ) == 0 ) { * res = cpu ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) Changed |= processBasicBlock ( MF , * BB ) ; return Changed ; } </s>


<s> void ia64_expand_call ( rtx retval , rtx addr , rtx nextarg ATTRIBUTE_UNUSED , int sibcall_p ) { rtx insn , b0 ; addr = XEXP ( addr , 0 ) ; addr = convert_memory_address ( DImode , addr ) ; b0 = gen_rtx_REG ( DImode , R_BR ( 0 ) ) ; if ( TARGET_NO_PIC || TARGET_AUTO_PIC ) { if ( sibcall_p ) insn = gen_sibcall_nogp ( addr ) ; else if ( ! retval ) insn = gen_call_nogp ( addr , b0 ) ; else insn = gen_call_value_nogp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn ) ; } else { if ( sibcall_p ) insn = gen_sibcall_gp ( addr ) ; else if ( ! retval ) insn = gen_call_gp ( addr , b0 ) ; else insn = gen_call_value_gp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , pic_offset_table_rtx ) ; } if ( sibcall_p ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , b0 ) ; if ( TARGET_ABI_OPEN_VMS ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( DImode , GR_REG ( 25 ) ) ) ; } </s>

Emit the appropriate sequence for a call .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
override
{
unsigned
NumBytes
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
TargetSize
/
8
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
SDValue
OR1KTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
,
DAG
)
;
case
ISD
::
CTTZ_ZERO_UNDEF
:
return
LowerCTTZ_ZERO_UNDEF
(
Op
,
DAG
)
;
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; } </s>


<s> void fma_forest :: merge_forest ( fma_forest * other_forest ) { std :: list < fma_root_node * > * other_roots ; std :: list < fma_root_node * > :: iterator other_root_iter ; if ( this == other_forest ) return ; other_roots = other_forest -> m_roots ; for ( other_root_iter = other_roots -> begin ( ) ; other_root_iter != other_roots -> end ( ) ; other_root_iter ++ ) ( * other_root_iter ) -> set_forest ( this ) ; this -> m_globals -> remove_forest ( other_forest ) ; this -> m_roots -> splice ( this -> m_roots -> begin ( ) , * other_roots ) ; delete other_forest ; this -> m_nb_nodes += other_forest -> m_nb_nodes ; } </s>

Merge REF_FOREST and OTHER_FOREST together , making REF_FOREST the canonical fma_forest object to represent both .


<s> static void loongarch_legitimize_const_move ( machine_mode mode , rtx dest , rtx src ) { rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { loongarch_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( loongarch_tls_symbol_p ( src ) ) { loongarch_emit_move ( dest , loongarch_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( can_create_pseudo_p ( ) ) ) ) { base = loongarch_force_temporary ( dest , base ) ; loongarch_emit_move ( dest , loongarch_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; loongarch_emit_move ( dest , src ) ; } </s>

Subroutine of loongarch_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s> int ix86_compare_version_priority ( tree decl1 , tree decl2 ) { unsigned int priority1 = get_builtin_code_for_version ( decl1 , NULL ) ; unsigned int priority2 = get_builtin_code_for_version ( decl2 , NULL ) ; return ( int ) priority1 - ( int ) priority2 ; } </s>

This compares the priority of target features in function DECL1 and DECL2 . It returns positive value if DECL1 is higher priority , negative value if DECL2 is higher priority and 0 if they are the same .


"SystemZ does do not have assembler relaxation"

Relax the instruction in the given fragment to the next wider instruction .


<s> Register CSKYRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? CSKY :: R8 : CSKY :: R14 ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { initialize ( MF ) ; return simplifyCode ( ) ; } </s>


<s> static bool arm_fastmul_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB1 ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = COSTS_N_INSNS ( 2 ) ; return false ; } if ( mode == DImode ) { * total = COSTS_N_INSNS ( 5 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 8 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; return false ; } if ( mode == SImode ) { * total = COSTS_N_INSNS ( 4 ) ; return false ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( TARGET_HARD_FLOAT && ( mode == SFmode || ( mode == DFmode && ! TARGET_VFP_SINGLE ) ) ) { * total = COSTS_N_INSNS ( 1 ) ; return false ; } } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; } } </s>

RTX cost for cores with a fast multiply unit ( M variants ) .


<s> void X86AsmParser :: emitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Out . emitInstruction ( Inst , getSTI ( ) ) ; if ( LVIInlineAsmHardening ) { if ( getSTI ( ) . getFeatureBits ( ) [ X86 :: FeatureLVIControlFlowIntegrity ] && applyLVICFIMitigation ( Inst ) ) return ; if ( getSTI ( ) . getFeatureBits ( ) [ X86 :: FeatureLVILoadHardening ] ) applyLVILoadHardeningMitigation ( Inst , Out ) ; } } </s>

Targets should implement this to emit instructions .


<s> rtx ix86_function_value ( tree valtype , tree fntype_or_decl , bool outgoing ATTRIBUTE_UNUSED ) { enum machine_mode natmode = type_natural_mode ( valtype ) ; if ( TARGET_64BIT ) { rtx ret = construct_container ( natmode , TYPE_MODE ( valtype ) , valtype , 1 , REGPARM_MAX , SSE_REGPARM_MAX , x86_64_int_return_registers , 0 ) ; if ( ! ret ) ret = gen_rtx_REG ( TYPE_MODE ( valtype ) , 0 ) ; return ret ; } else { tree fn = NULL_TREE , fntype ; if ( fntype_or_decl && DECL_P ( fntype_or_decl ) ) fn = fntype_or_decl ; fntype = fn ? TREE_TYPE ( fn ) : fntype_or_decl ; return gen_rtx_REG ( TYPE_MODE ( valtype ) , ix86_value_regno ( natmode , fn , fntype ) ) ; } } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 .


<s>
SDValue
MipsDAGToDAGISel
::
getGlobalBaseReg
(
)
{
MachineFunction
*
MF
=
BB
->
getParent
(
)
;
unsigned
GP
=
0
;
for
(
MachineRegisterInfo
::
livein_iterator
ii
=
MF
->
getRegInfo
(
)
.
livein_begin
(
)
,
ee
=
MF
->
getRegInfo
(
)
.
livein_end
(
)
;
ii
!=
ee
;
++
ii
)
if
(
ii
->
first
==
Mips
::
GP
)
{
GP
=
ii
->
second
;
break
;
}
assert
(
GP
&&
"GOT PTR not in liveins"
)
;
return
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
DebugLoc
::
getUnknownLoc
(
)
,
GP
,
MVT
::
i32
)
;
}
</s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips
Mips
0
Mips::GP
"GOT PTR not in liveins"
MVT::i32


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { const X86Subtarget & Subtarget = getTargetMachine ( ) . getSubtarget < X86Subtarget > ( ) ; unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; const Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) { return nullptr ; } else if ( hasMFENCE ( Subtarget ) ) { Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence ) ; } else { return nullptr ; } LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> bool arm_is_long_call_p ( tree decl ) { tree attrs ; if ( ! decl ) return TARGET_LONG_CALLS ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( "short_call" , attrs ) ) return false ; if ( ! flag_reorder_blocks_and_partition && TREE_CODE ( decl ) == FUNCTION_DECL && arm_function_in_section_p ( decl , current_function_section ( ) ) ) return false ; if ( lookup_attribute ( "long_call" , attrs ) ) return true ; return TARGET_LONG_CALLS ; } </s>

Return nonzero if a 32-bit `` long_call '' should be generated for a call from the current function to DECL . We generate a long_call if the function : a. has an __attribute__ ( ( long call ) ) or b. is within the scope of a # pragma long_calls or c. the -mlong-calls command line switch has been specified However we do not generate a long call if the function : d. has an __attribute__ ( ( short_call ) ) or e. is inside the scope of a # pragma no_long_calls or f. is defined in the same section as the current function .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> bool X86InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { SmallVector < MachineInstr * , 4 > CondBranches ; return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond , CondBranches , AllowModify ) ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { IsFixed . resize ( Outs . size ( ) , false ) ; for ( unsigned ValNo = 0 , E = Outs . size ( ) ; ValNo != E ; ++ ValNo ) if ( Outs [ ValNo ] . IsFixed ) IsFixed . set ( ValNo ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> unsigned MipsOptimizePICCall :: getReg ( ValueType Entry ) { unsigned Reg = ScopedHT . lookup ( Entry ) . second ; assert ( Reg ) ; return Reg ; } </s>

Returns the register associated with this edge .


"not supported with %<-mabi=ti%> option"

Callback for walk_gimple_seq that checks TP tree for TI ABI compliance .


<s> static rtx mmix_function_arg ( cumulative_args_t argsp , machine_mode mode , const_tree type , bool named ) { return mmix_function_arg_1 ( argsp , mode , type , named , false ) ; } </s>

Return an rtx for a function argument to go in a register , and 0 for one that must go on stack .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint64_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableMips32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> static bool expand_vec_perm_vpshufb2_vpermq ( struct expand_vec_perm_d * d ) { rtx rperm [ 2 ] [ 32 ] , vperm , l , h , hp , op , m128 ; unsigned int i , nelt , eltsz ; if ( ! TARGET_AVX2 || ! d -> one_operand_p || ( d -> vmode != V32QImode && d -> vmode != V16HImode ) ) return false ; if ( d -> testing_p ) return true ; nelt = d -> nelt ; eltsz = GET_MODE_SIZE ( GET_MODE_INNER ( d -> vmode ) ) ; m128 = GEN_INT ( - 128 ) ; for ( i = 0 ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] & ( nelt / 2 - 1 ) ; unsigned which = ( ( d -> perm [ i ] ^ i ) & ( nelt / 2 ) ) * eltsz ; for ( j = 0 ; j < eltsz ; ++ j ) { rperm [ ! ! which ] [ ( i * eltsz + j ) ^ which ] = GEN_INT ( e * eltsz + j ) ; rperm [ ! which ] [ ( i * eltsz + j ) ^ ( which ^ 16 ) ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( 32 , rperm [ 1 ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; h = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( h , op , vperm ) ) ; hp = gen_reg_rtx ( V4DImode ) ; op = gen_lowpart ( V4DImode , h ) ; emit_insn ( gen_avx2_permv4di_1 ( hp , op , const2_rtx , GEN_INT ( 3 ) , const0_rtx , const1_rtx ) ) ; vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( 32 , rperm [ 0 ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; l = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( l , op , vperm ) ) ; op = d -> target ; if ( d -> vmode != V32QImode ) op = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_iorv32qi3 ( op , l , gen_lowpart ( V32QImode , hp ) ) ) ; if ( op != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , op ) ) ; return true ; } </s>

Implement arbitrary permutation of one V32QImode and V16QImode operand with two vpshufb insns , vpermq and vpor . We should have already failed all two or three instruction sequences .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_CCOut
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian , unsigned MinSVEVectorSizeInBitsOverride , unsigned MaxSVEVectorSizeInBitsOverride ) : AArch64GenSubtargetInfo ( TT , CPU , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , MinSVEVectorSizeInBits ( MinSVEVectorSizeInBitsOverride ) , MaxSVEVectorSizeInBits ( MaxSVEVectorSizeInBitsOverride ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>


"GCC does not currently support mixed size types "

"GCC does not currently support return type %qT "

"unsupported return type %qT for %<simd%> functions"

"GCC does not currently support argument type %qT "

"GCC does not currently support simdlen %wd for type %qT"


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: VFMADDPDr231r : case X86 :: VFMADDPSr231r : case X86 :: VFMADDSDr231r : case X86 :: VFMADDSSr231r : case X86 :: VFMSUBPDr231r : case X86 :: VFMSUBPSr231r : case X86 :: VFMSUBSDr231r : case X86 :: VFMSUBSSr231r : case X86 :: VFNMADDPDr231r : case X86 :: VFNMADDPSr231r : case X86 :: VFNMADDSDr231r : case X86 :: VFNMADDSSr231r : case X86 :: VFNMSUBPDr231r : case X86 :: VFNMSUBPSr231r : case X86 :: VFNMSUBSDr231r : case X86 :: VFNMSUBSSr231r : case X86 :: VFMADDPDr231rY : case X86 :: VFMADDPSr231rY : case X86 :: VFMSUBPDr231rY : case X86 :: VFMSUBPSr231rY : case X86 :: VFNMADDPDr231rY : case X86 :: VFNMADDPSr231rY : case X86 :: VFNMSUBPDr231rY : case X86 :: VFNMSUBPSr231rY : SrcOpIdx1 = 2 ; SrcOpIdx2 = 3 ; return true ; default : return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> unsigned getNumFixupKinds ( ) const { return X86 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> HOST_WIDE_INT iq2000_debugger_offset ( rtx addr , HOST_WIDE_INT offset ) { rtx offset2 = const0_rtx ; rtx reg = eliminate_constant_term ( addr , & offset2 ) ; if ( offset == 0 ) offset = INTVAL ( offset2 ) ; if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { HOST_WIDE_INT frame_size = ( ! cfun -> machine -> initialized ) ? compute_frame_size ( get_frame_size ( ) ) : cfun -> machine -> total_size ; offset = offset - frame_size ; } return offset ; } </s>

The arg pointer ( which is eliminated ) points to the virtual frame pointer , while the frame pointer ( which may be eliminated ) points to the stack pointer after the initial adjustments .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || ! flag_unsafe_math_optimizations ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s> const char * getPassName ( ) const override { return AARCH64_COLLECT_LOH_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
MachineOperand
&
AArch64InstrInfo
::
getMemOpBaseRegImmOfsOffsetOperand
(
MachineInstr
&
LdSt
)
const
{
assert
(
LdSt
.
mayLoadOrStore
(
)
&&
"Expected a memory operation."
)
;
MachineOperand
&
OfsOp
=
LdSt
.
getOperand
(
LdSt
.
getNumExplicitOperands
(
)
1
)
;
assert
(
OfsOp
.
isImm
(
)
&&
"Offset operand wasn't immediate."
)
;
return
OfsOp
;
}
</s>

Return the immediate offset of the base register in a load/store LdSt .


<s> machine_mode rs6000_secondary_memory_needed_mode ( machine_mode mode ) { if ( lra_in_progress && mode == SDmode ) return DDmode ; return mode ; } </s>

Return the mode to be used for memory when a secondary memory location is needed . For SDmode values we need to use DDmode , in all other cases we can use the same mode .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STR : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: t2STRi12 : case ARM :: tSpill : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VSTRD : case ARM :: VSTRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static void aarch64_process_components ( sbitmap components , bool prologue_p ) { rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; unsigned last_regno = SBITMAP_SIZE ( components ) ; unsigned regno = aarch64_get_next_set_bit ( components , R0_REGNUM ) ; rtx_insn * insn = NULL ; while ( regno != last_regno ) { machine_mode mode = GP_REGNUM_P ( regno ) ? E_DImode : E_DFmode ; rtx reg = gen_rtx_REG ( mode , regno ) ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr = plus_constant ( Pmode , ptr_reg , offset ) ; rtx mem = gen_frame_mem ( mode , addr ) ; rtx set = prologue_p ? gen_rtx_SET ( mem , reg ) : gen_rtx_SET ( reg , mem ) ; unsigned regno2 = aarch64_get_next_set_bit ( components , regno + 1 ) ; if ( regno2 == last_regno ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; break ; } poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || maybe_ne ( ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) , GET_MODE_SIZE ( mode ) ) ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; regno = regno2 ; continue ; } rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( ! frame_pointer_needed ) offset2 += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem ( mode , addr2 ) ; rtx set2 = prologue_p ? gen_rtx_SET ( mem2 , reg2 ) : gen_rtx_SET ( reg2 , mem2 ) ; if ( prologue_p ) insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; else insn = emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) { add_reg_note ( insn , REG_CFA_OFFSET , set ) ; add_reg_note ( insn , REG_CFA_OFFSET , set2 ) ; } else { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg2 ) ; } regno = aarch64_get_next_set_bit ( components , regno2 + 1 ) ; } } </s>

Do the work for aarch64_emit_prologue_components and aarch64_emit_epilogue_components . COMPONENTS is the bitmap of registers to save/restore , PROLOGUE_P indicates whether to emit the prologue sequence for these components or the epilogue sequence . That is , it determines whether we should emit stores or loads and what kind of CFA notes to attach to the insns . Otherwise the logic for the two sequences is very similar .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { bool is64 = getPointerSize ( ) == 8 ; return createPPCELFObjectWriter ( OS , is64 , isLittleEndian ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static void mips_process_load_label ( rtx target ) { rtx base , gp , intop ; HOST_WIDE_INT offset ; mips_multi_start ( ) ; switch ( mips_abi ) { case ABI_N32 : mips_multi_add_insn ( "lw\t%@,%%got_page(%0)(%+)" , target , 0 ) ; mips_multi_add_insn ( "addiu\t%@,%@,%%got_ofst(%0)" , target , 0 ) ; break ; case ABI_64 : mips_multi_add_insn ( "ld\t%@,%%got_page(%0)(%+)" , target , 0 ) ; mips_multi_add_insn ( "daddiu\t%@,%@,%%got_ofst(%0)" , target , 0 ) ; break ; default : gp = pic_offset_table_rtx ; if ( mips_cfun_has_cprestore_slot_p ( ) ) { gp = gen_rtx_REG ( Pmode , AT_REGNUM ) ; mips_get_cprestore_base_and_offset ( & base , & offset , true ) ; if ( ! SMALL_OPERAND ( offset ) ) { intop = GEN_INT ( CONST_HIGH_PART ( offset ) ) ; mips_multi_add_insn ( "lui\t%0,%1" , gp , intop , 0 ) ; mips_multi_add_insn ( "addu\t%0,%0,%1" , gp , base , 0 ) ; base = gp ; offset = CONST_LOW_PART ( offset ) ; } intop = GEN_INT ( offset ) ; if ( ISA_HAS_LOAD_DELAY ) mips_multi_add_insn ( "lw\t%0,%1(%2)%#" , gp , intop , base , 0 ) ; else mips_multi_add_insn ( "lw\t%0,%1(%2)" , gp , intop , base , 0 ) ; } if ( ISA_HAS_LOAD_DELAY ) mips_multi_add_insn ( "lw\t%@,%%got(%0)(%1)%#" , target , gp , 0 ) ; else mips_multi_add_insn ( "lw\t%@,%%got(%0)(%1)" , target , gp , 0 ) ; mips_multi_add_insn ( "addiu\t%@,%@,%%lo(%0)" , target , 0 ) ; break ; } } </s>

Build up a multi-insn sequence that loads label TARGET into $ AT .


<s> unsigned PPCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == PPC :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { StackMapOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool Cpu0PassConfig :: addInstSelector ( ) { addPass ( createCpu0ISelDag ( getCpu0TargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> bool PPCTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! VT . isSimple ( ) || ! Subtarget . hasVSX ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: f32 : case MVT :: f64 : if ( Subtarget . hasPrefixInstrs ( ) ) { APFloat APFloatOfImm = Imm ; return convertToNonDenormSingle ( APFloatOfImm ) ; } LLVM_FALLTHROUGH ; case MVT :: ppcf128 : return Imm . isPosZero ( ) ; } } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const override { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> bool convertSelectOfConstantsToMath ( ) const override { return true ; } </s>

Return true if a select of constants ( select Cond , C1 , C2 ) should be transformed into simple math ops with the condition value .


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather ) { Gathers . push_back ( II ) ; if ( isa < GetElementPtrInst > ( II -> getArgOperand ( 0 ) ) ) optimiseOffsets ( cast < Instruction > ( II -> getArgOperand ( 0 ) ) -> getOperand ( 1 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter ) { Scatters . push_back ( II ) ; if ( isa < GetElementPtrInst > ( II -> getArgOperand ( 1 ) ) ) optimiseOffsets ( cast < Instruction > ( II -> getArgOperand ( 1 ) ) -> getOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } bool Changed = false ; for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void SystemZPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && getSystemZTargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
>
I
=
df_ext_begin
(
Entry
,
Processed
)
,
E
=
df_ext_end
(
Entry
,
Processed
)
;
I
!=
E
;
++
I
)
Changed
|=
processBasicBlock
(
MF
,
*
*
I
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & MF . getSubtarget < ARMSubtarget > ( ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( MachineBasicBlock * MBB : RPOT ) Modified |= ReduceMBB ( * MBB ) ; return Modified ; } </s>