<s> const unsigned * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } static const unsigned GhcCalleeSavedRegs [ ] = { 0 } ; static const unsigned CalleeSavedRegs32Bit [ ] = { X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs32EHRet [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs64Bit [ ] = { X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegs64EHRet [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegsWin64 [ ] = { X86 :: RBX , X86 :: RBP , X86 :: RDI , X86 :: RSI , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: XMM6 , X86 :: XMM7 , X86 :: XMM8 , X86 :: XMM9 , X86 :: XMM10 , X86 :: XMM11 , X86 :: XMM12 , X86 :: XMM13 , X86 :: XMM14 , X86 :: XMM15 , 0 } ; if ( ghcCall ) { return GhcCalleeSavedRegs ; } else if ( Is64Bit ) { if ( IsWin64 ) return CalleeSavedRegsWin64 ; else return ( callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit ) ; } else { return ( callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit ) ; } } </s>


<s> bool ARMBaseInstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ 0 ] . getImm ( ) ) . addReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> static void build_sv_index64 ( function_builder & b , const char * signature , const function_group_info & group ) { build_32_64 ( b , signature , group , MODE_none , MODE_s64index ) ; build_32_64 ( b , signature , group , MODE_none , MODE_u64index ) ; } </s>

Like build_sv_index , but only handle 64-bit types .


<s> unsigned getFramePtr ( ) const { return FramePtr ; } </s>

Returns physical register used as frame pointer .


<s> ConstantPool * AssemblerConstantPools :: getConstantPool ( const MCSection * Section ) { ConstantPoolMapTy :: iterator CP = ConstantPools . find ( Section ) ; if ( CP == ConstantPools . end ( ) ) return nullptr ; return & CP -> second ; } </s>

Return a pseudo source value referencing the constant pool .


<s> void UPTMCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> SDValue SystemZTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_SystemZ ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; if ( Subtarget . isThumb2 ( ) && TBB . getParent ( ) -> getFunction ( ) . hasMinSize ( ) ) { if ( TBB . pred_size ( ) != 1 || FBB . pred_size ( ) != 1 ) return false ; } const unsigned ScalingUpFactor = 1024 ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) { unsigned NotTakenBranchCost = 1 ; unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= 1 * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > 4 ) { PredCost += ( ( TCycles + FCycles - 4 ) / 4 ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; } return PredCost <= UnpredCost ; } </s>


<s> rtx pa_legitimize_reload_address ( rtx ad , machine_mode mode , int opnum , int type , int ind_levels ATTRIBUTE_UNUSED ) { long offset , newoffset , mask ; rtx new_rtx , temp = NULL_RTX ; mask = ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && ! INT14_OK_STRICT ? 0x1f : 0x3fff ) ; if ( optimize && GET_CODE ( ad ) == PLUS ) temp = simplify_binary_operation ( PLUS , Pmode , XEXP ( ad , 0 ) , XEXP ( ad , 1 ) ) ; new_rtx = temp ? temp : ad ; if ( optimize && GET_CODE ( new_rtx ) == PLUS && GET_CODE ( XEXP ( new_rtx , 0 ) ) == REG && GET_CODE ( XEXP ( new_rtx , 1 ) ) == CONST_INT ) { offset = INTVAL ( XEXP ( ( new_rtx ) , 1 ) ) ; if ( ( offset & mask ) >= ( ( mask + 1 ) / 2 ) ) newoffset = ( offset & ~ mask ) + mask + 1 ; else newoffset = offset & ~ mask ; if ( mask == 0x3fff && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || ( TARGET_64BIT && ( mode ) == DImode ) ) ) newoffset &= ~ ( GET_MODE_SIZE ( mode ) - 1 ) ; if ( newoffset != 0 && VAL_14_BITS_P ( newoffset ) ) { temp = gen_rtx_PLUS ( Pmode , XEXP ( new_rtx , 0 ) , GEN_INT ( newoffset ) ) ; ad = gen_rtx_PLUS ( Pmode , temp , GEN_INT ( offset - newoffset ) ) ; push_reload ( XEXP ( ad , 0 ) , 0 , & XEXP ( ad , 0 ) , 0 , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return ad ; } } return NULL_RTX ; } </s>

Look for machine dependent ways to make the invalid address AD a valid address . For the PA , transform : memory ( X + < large int > ) into : if ( < large int > & mask ) > = 16 Y = ( < large int > & ~mask ) + mask + 1 Round up . else Y = ( < large int > & ~mask ) Round down . Z = X + Y memory ( Z + ( < large int > - Y ) ) ; This makes reload inheritance and reload_cse work better since Z can be reused . There may be more opportunities to improve code with this hook .


<s> bool X86Subtarget :: enableEarlyIfConversion ( ) const { return hasCMov ( ) && X86EarlyIfConv ; } </s>

Enable the use of the early if conversion pass .


<s> const MipsInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue1SImm16 - Return binary encoding of the branch target operand .


<s> void ix86_split_fp_branch ( enum rtx_code code , rtx op1 , rtx op2 , rtx target1 , rtx target2 , rtx tmp ) { rtx condition ; rtx i ; if ( target2 != pc_rtx ) { std :: swap ( target1 , target2 ) ; code = reverse_condition_maybe_unordered ( code ) ; } condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp ) ; i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( split_branch_probability >= 0 ) add_int_reg_note ( i , REG_BR_PROB , split_branch_probability ) ; } </s>

Split branch based on floating point condition .


<s> bool ARMTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { int64_t AbsImm = llvm :: abs64 ( Imm ) ; if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( AbsImm ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( AbsImm ) != - 1 ; return AbsImm >= 0 && AbsImm <= 255 ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


"rs6000_compare_version_priority (%s, %s) => %d\n"

This compares the priority of target features in function DECL1 and DECL2 . It returns positive value if DECL1 is higher priority , negative value if DECL2 is higher priority and 0 if they are the same . Note , priorities are ordered from lowest ( CLONE_DEFAULT ) to highest ( currently CLONE_ISA_3_0 ) .


<s> static int rank_for_reorder ( const void * x , const void * y ) { rtx_insn * tmp = * ( rtx_insn * const * ) y ; rtx_insn * tmp2 = * ( rtx_insn * const * ) x ; if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? 1 : - 1 ; return INSN_LUID ( tmp ) - INSN_LUID ( tmp2 ) ; } </s>

Comparison function for ready queue sorting .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
assert
(
0
&&
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .

PowerPC
0
"relaxInstruction() unimplemented"


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX512 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( Is64Bit && HasAVX512 ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( CC == CallingConv :: WebKit_JS || CC == CallingConv :: AnyReg ) return CSR_MostRegs_64_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( CC == CallingConv :: Cold ) return CSR_MostRegs_64_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool ARMTargetLowering :: isMulAddWithConstProfitable ( SDValue AddNode , SDValue ConstNode ) const { const EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) || VT . getScalarSizeInBits ( ) > 32 ) return true ; const ConstantSDNode * C0Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; const ConstantSDNode * C1Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C0 = C0Node -> getSExtValue ( ) ; APInt CA = C0Node -> getAPIntValue ( ) * C1Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C0 ) || isLegalAddImmediate ( CA . getSExtValue ( ) ) ) return true ; if ( ConstantMaterializationCost ( ( unsigned ) CA . getZExtValue ( ) , Subtarget ) > 1 ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


<s> bool MipsSETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { MVT :: SimpleValueType SVT = VT . getSimpleVT ( ) . SimpleTy ; if ( Subtarget . systemSupportsUnalignedAccess ( ) ) { if ( Fast ) * Fast = true ; return true ; } switch ( SVT ) { case MVT :: i64 : case MVT :: i32 : if ( Fast ) * Fast = true ; return true ; default : return false ; } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
void
SparcInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SP
::
IntRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
ORrr
)
,
DestReg
)
.
addReg
(
SP
::
G0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
FPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVS
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
DFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Subtarget
.
isV9
(
)
SP
::
FMOVD
:
SP
::
FpMOVD
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>

Sparc
Sparc
SP::IntRegsRegClass
SP::ORrr
SP::G0
SP::FPRegsRegClass
SP::FMOVS
SP::DFPRegsRegClass
SP::FMOVD
SP::FpMOVD
"Impossible reg-to-reg copy"


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
useSplatVFPToNeon
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
Modified
|=
runOnInstruction
(
&
MI
)
;
}
}
for
(
MachineInstr
*
MI
:
DeadInstr
)
{
MI
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) PM -> add ( createGlobalMergePass ( TM -> getTargetLowering ( ) ) ) ; return false ; } </s>


<s>
bool
ARMAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
case
'A'
:
default
:
return
true
;
case
'm'
:
if
(
!
MI
->
getOperand
(
OpNum
)
.
isReg
(
)
)
return
true
;
O
<<
ARMInstPrinter
::
getRegisterName
(
MI
->
getOperand
(
OpNum
)
.
getReg
(
)
)
;
return
false
;
}
}
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
ARMInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> llvm :: FastISel * AArch64 :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new AArch64FastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool LanaiInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Lanai :: SFSUB_F_RI_LO : case Lanai :: SFSUB_F_RI_HI : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case Lanai :: SFSUB_F_RR : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> rtx arm_gen_load_multiple ( int base_regno , int count , rtx from , int up , int write_back , rtx basemem , HOST_WIDE_INT * offsetp ) { HOST_WIDE_INT offset = * offsetp ; int i = 0 , j ; rtx result ; int sign = up ? 1 : - 1 ; rtx mem , addr ; if ( arm_tune_xscale && count <= 2 && ! optimize_size ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) { addr = plus_constant ( from , i * 4 * sign ) ; mem = adjust_automodify_address ( basemem , SImode , addr , offset ) ; emit_move_insn ( gen_rtx_REG ( SImode , base_regno + i ) , mem ) ; offset += 4 * sign ; } if ( write_back ) { emit_move_insn ( from , plus_constant ( from , count * 4 * sign ) ) ; * offsetp = offset ; } seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( write_back ? 1 : 0 ) ) ) ; if ( write_back ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( GET_MODE ( from ) , from , plus_constant ( from , count * 4 * sign ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) { addr = plus_constant ( from , j * 4 * sign ) ; mem = adjust_automodify_address_nv ( basemem , SImode , addr , offset ) ; XVECEXP ( result , 0 , i ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , base_regno + j ) , mem ) ; offset += 4 * sign ; } if ( write_back ) * offsetp = offset ; return result ; } </s>


<s> InstructionCost getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) , const Instruction * CxtI = nullptr ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

Lanai ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> int PPCTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCostInst ( Opcode , Idx , Imm , Ty , CostKind ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> bool PPCPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility "

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> bool csky_emit_compare_float ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx cc_reg = gen_rtx_REG ( CCmode , CSKY_CC_REGNUM ) ; bool invert ; machine_mode mode = GET_MODE ( op1 ) ; if ( op1 != CONST0_RTX ( mode ) ) op1 = force_reg ( mode , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; break ; case GT : case LT : case LE : if ( op1 == CONST0_RTX ( mode ) && ( CSKY_ISA_FEATURE_GET ( fpv2_sf ) || CSKY_ISA_FEATURE_GET ( fpv2_df ) || CSKY_ISA_FEATURE_GET ( fpv2_divd ) ) ) op1 = force_reg ( mode , op1 ) ; break ; case ORDERED : code = UNORDERED ; invert = true ; break ; default : break ; } emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 ) ) ) ; return invert ; } </s>

Emit a comparison insn for float values . Return true if the comparison is inverted .


<s> bool AArch64TargetLowering :: useLoadStackGuardNode ( ) const { return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> static void ix86_init_pic_reg ( void ) { edge entry_edge ; rtx_insn * seq ; if ( ! ix86_use_pseudo_pic_reg ( ) ) return ; start_sequence ( ) ; if ( TARGET_64BIT ) { if ( ix86_cmodel == CM_LARGE_PIC ) ix86_init_large_pic_reg ( R11_REG ) ; else emit_insn ( gen_set_got_rex64 ( pic_offset_table_rtx ) ) ; } else { rtx reg = crtl -> profile ? gen_rtx_REG ( Pmode , REAL_PIC_OFFSET_TABLE_REGNUM ) : pic_offset_table_rtx ; rtx insn = emit_insn ( gen_set_got ( reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( crtl -> profile ) emit_move_insn ( pic_offset_table_rtx , reg ) ; add_reg_note ( insn , REG_CFA_FLUSH_QUEUE , NULL_RTX ) ; } seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } </s>

Create and initialize PIC register if required .


<s>
StringRef
getPassName
(
)
const
override
{
return
"PowerPC QPX Load Splat Simplification"
;
}
</s>

getPassName - Return a nice clean name for a pass .

PowerPC
"PowerPC QPX Load Splat Simplification"


<s> bool xstormy16_below100_symbol ( rtx x , machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) != 0 ; if ( CONST_INT_P ( x ) ) { HOST_WIDE_INT i = INTVAL ( x ) ; if ( ( i >= 0x0000 && i <= 0x00ff ) || ( i >= 0x7f00 && i <= 0x7fff ) ) return 1 ; } return 0 ; } </s>

Predicate for symbols and addresses that reflect special 8-bit addressing .


<s> bool PPCTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget . is64BitELFABI ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; const Function * Caller = CI -> getParent ( ) -> getParent ( ) ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv ( ) ) ) return false ; return getTargetMachine ( ) . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , Callee ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


"FMA or FMUL at insn %d but destination "

"register (%s) has different parity from expected to "

"Destination register of insn %d could not be "

"renamed. Dependent FMA insns will use this parity from "

Rename the destination register of a single FMUL or FMADD/FMSUB instruction represented by FMA_NODE to a register that respect the target parity for FOREST or with same parity of the instruction represented by its parent node if it has one .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( ) ) ; addPass ( createMVETailPredicationPass ( ) ) ; } return false ; } </s>


<s> static tree aarch64_promoted_type ( const_tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) == 16 ) return float_type_node ; return NULL_TREE ; } </s>

Implement TARGET_PROMOTED_TYPE to promote __fp16 to float .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { if ( ! Subtarget . hasAVX2 ( ) ) if ( VT == MVT :: v32i8 || VT == MVT :: v16i16 ) return false ; return isShuffleMaskLegal ( Mask , VT ) ; } </s>


<s> static bool aarch64_rtx_arith_op_extract_p ( rtx x , machine_mode mode ) { if ( GET_CODE ( x ) == SIGN_EXTRACT || GET_CODE ( x ) == ZERO_EXTRACT ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; rtx op2 = XEXP ( x , 2 ) ; if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( op1 ) && op2 == const0_rtx && CONST_INT_P ( XEXP ( op0 , 1 ) ) && aarch64_is_extend_from_extract ( mode , XEXP ( op0 , 1 ) , op1 ) ) { return true ; } } else if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) return REG_P ( XEXP ( x , 0 ) ) ; return false ; } </s>

Return true if X is a zero or sign extract usable in an ADD or SUB ( extended register ) instruction .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static rtx sparc_got ( void ) { if ( ! got_symbol_rtx ) got_symbol_rtx = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; return got_symbol_rtx ; } </s>

Return the SYMBOL_REF for the Global Offset Table .


<s> int iq2000_adjust_insn_length ( rtx_insn * insn , int length ) { if ( simplejump_p ( insn ) || ( ( JUMP_P ( insn ) || CALL_P ( insn ) ) ) ) length += 4 ; return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( createPPCLowerMASSVEntriesPass ( ) ) ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> Register VERegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return VE :: SX9 ; } </s>


<s> static bool rs6000_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_mode_ok_p [ mode ] [ regno ] ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> static bool ix86_hard_regno_call_part_clobbered ( unsigned int abi_id , unsigned int regno , machine_mode mode ) { if ( abi_id == ABI_VZEROUPPER ) return ( GET_MODE_SIZE ( mode ) > 16 && ( ( TARGET_64BIT && REX_SSE_REGNO_P ( regno ) ) || LEGACY_SSE_REGNO_P ( regno ) ) ) ; return SSE_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 16 ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The only ABI that saves SSE registers across calls is Win64 ( thus no need to check the current ABI here ) , and with AVX enabled Win64 only guarantees that the low 16 bytes are saved .


<s> TargetIRAnalysis X86TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( X86TTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> int mips_regno_mode_ok_for_base_p ( int regno , machine_mode mode , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM ) return true ; if ( TARGET_MIPS16 && regno == STACK_POINTER_REGNUM ) return GET_MODE_SIZE ( mode ) == 4 || GET_MODE_SIZE ( mode ) == 8 ; return TARGET_MIPS16 ? M16_REG_P ( regno ) : GP_REG_P ( regno ) ; } </s>

This function is used to implement REG_MODE_OK_FOR_BASE_P .


"\nrs6000_legitimize_address: mode %s, old code %s, "

"\nrs6000_legitimize_address: mode %s, code %s, no change:\n"

Debug version of rs6000_legitimize_address .


<s> void VEPassConfig :: addPreEmitPass ( ) { addPass ( createLVLGenPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const MCExpr * createExprForCAPIVariantKind ( const MCExpr * SubExpr , unsigned VariantKind ) override { switch ( VariantKind ) { case LLVMDisassembler_VariantKind_ARM_HI16 : return ARMMCExpr :: CreateUpper16 ( SubExpr , Ctx ) ; case LLVMDisassembler_VariantKind_ARM_LO16 : return ARMMCExpr :: CreateLower16 ( SubExpr , Ctx ) ; default : return MCRelocationInfo :: createExprForCAPIVariantKind ( SubExpr , VariantKind ) ; } } </s>

Create an MCExpr for the target-specific VariantKind .


<s> bool ix86_expand_int_addcc ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx flags ; rtx ( * insn ) ( machine_mode , rtx , rtx , rtx , rtx , rtx ) ; rtx compare_op ; rtx val = const0_rtx ; bool fpcmp = false ; machine_mode mode ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( operands [ 3 ] != const1_rtx && operands [ 3 ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , 0 ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ 0 ] ) ; if ( ( code == LTU ) == ( operands [ 3 ] == constm1_rtx ) ) insn = gen_sub3_carry ; else insn = gen_add3_carry ; emit_insn ( insn ( mode , operands [ 0 ] , operands [ 2 ] , val , flags , compare_op ) ) ; return true ; } </s>

Expand conditional increment or decrement using adb/sbb instructions . The default case using setcc followed by the conditional move can be done by generic code .


<s> static void mep_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx addr = XEXP ( m_tramp , 0 ) ; rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__mep_trampoline_helper" ) , LCT_NORMAL , VOIDmode , 3 , addr , Pmode , fnaddr , Pmode , static_chain , Pmode ) ; } </s>


<s> unsigned X86TTI :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TCC_Basic ; return TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( ( Idx == ImmIdx ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; return X86TTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> write32 ( 0x01000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool X86TargetLowering :: isCommutativeBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: PMULUDQ : return true ; } return TargetLoweringBase :: isCommutativeBinOp ( Opcode ) ; } </s>

Returns true if the opcode is a commutative binary operation .


<s> static const char * mips_get_compress_off_name ( unsigned int flags ) { if ( flags == MASK_MIPS16 ) return "nomips16" ; if ( flags == MASK_MICROMIPS ) return "nomicromips" ; return "nocompression" ; } </s>

Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS flags FLAGS .

mips "nomips16" "nomicromips" "nocompression"


<s> void emitConstantPool ( ) override { } </s>

Print to the current output stream assembly representations of the constants in the constant pool MCP .


<s> bool PPCTTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { return LoopHasReductions ; } </s>

Do n't restrict interleaved unrolling to small loops .


<s> bool MipsFastISel :: fastSelectInstruction ( const Instruction * I ) { if ( ! TargetSupported ) return false ; switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPToSI : return selectFPToInt ( I , true ) ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ICmp : case Instruction :: FCmp : return selectCmp ( I ) ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> static char * sorted_attr_string ( tree arglist ) { tree arg ; size_t str_len_sum = 0 ; char * * args = NULL ; char * attr_str , * ret_str ; char * attr = NULL ; unsigned int argnum = 1 ; unsigned int i ; for ( arg = arglist ; arg ; arg = TREE_CHAIN ( arg ) ) { const char * str = TREE_STRING_POINTER ( TREE_VALUE ( arg ) ) ; size_t len = strlen ( str ) ; str_len_sum += len + 1 ; if ( arg != arglist ) argnum ++ ; for ( i = 0 ; i < strlen ( str ) ; i ++ ) if ( str [ i ] == ',' ) argnum ++ ; } attr_str = XNEWVEC ( char , str_len_sum ) ; str_len_sum = 0 ; for ( arg = arglist ; arg ; arg = TREE_CHAIN ( arg ) ) { const char * str = TREE_STRING_POINTER ( TREE_VALUE ( arg ) ) ; size_t len = strlen ( str ) ; memcpy ( attr_str + str_len_sum , str , len ) ; attr_str [ str_len_sum + len ] = TREE_CHAIN ( arg ) ? ',' : '\0' ; str_len_sum += len + 1 ; } for ( i = 0 ; i < strlen ( attr_str ) ; i ++ ) if ( attr_str [ i ] == '=' || attr_str [ i ] == '-' ) attr_str [ i ] = '_' ; if ( argnum == 1 ) return attr_str ; args = XNEWVEC ( char * , argnum ) ; i = 0 ; attr = strtok ( attr_str , "," ) ; while ( attr != NULL ) { args [ i ] = attr ; i ++ ; attr = strtok ( NULL , "," ) ; } qsort ( args , argnum , sizeof ( char * ) , attr_strcmp ) ; ret_str = XNEWVEC ( char , str_len_sum ) ; str_len_sum = 0 ; for ( i = 0 ; i < argnum ; i ++ ) { size_t len = strlen ( args [ i ] ) ; memcpy ( ret_str + str_len_sum , args [ i ] , len ) ; ret_str [ str_len_sum + len ] = i < argnum - 1 ? '_' : '\0' ; str_len_sum += len + 1 ; } XDELETEVEC ( args ) ; XDELETEVEC ( attr_str ) ; return ret_str ; } </s>

ARGLIST is the argument to target attribute . This function tokenizes the comma separated arguments , sorts them and returns a string which is a unique identifier for the comma separated arguments . It also replaces non-identifier characters `` = , - '' with `` _ '' .


<s>
unsigned
getPointerSize
(
)
{
if
(
is16BitMode
(
)
)
return
16
;
if
(
is32BitMode
(
)
)
return
32
;
if
(
is64BitMode
(
)
)
return
64
;
llvm_unreachable
(
"invalid mode"
)
;
}
</s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s>
void
mmix_asm_output_label
(
FILE
*
stream
,
const
char
*
name
)
{
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\tIS @\n"
)
;
}
</s>


<s> static machine_mode rs6000_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_VSX ) switch ( mode ) { case DFmode : return V2DFmode ; default : ; } if ( TARGET_ALTIVEC || TARGET_VSX ) switch ( mode ) { case SFmode : return V4SFmode ; case TImode : return V1TImode ; case DImode : return V2DImode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; default : ; } if ( TARGET_SPE ) switch ( mode ) { case SFmode : return V2SFmode ; case SImode : return V2SImode ; default : ; } if ( TARGET_PAIRED_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode ; } </s>


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> int neon_vector_mem_operand ( rtx op , int type , bool strict ) { rtx ind ; if ( strict && ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( ( type != 1 && GET_CODE ( ind ) == POST_INC ) || ( type == 0 && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( type == 2 && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , 1 ) , 1 ) ) ) return true ; if ( type == 0 && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , 0 ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , 1 ) ) && INTVAL ( XEXP ( ind , 1 ) ) > - 1024 && ( INTVAL ( XEXP ( ind , 1 ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? 1016 : 1024 ) ) && ( INTVAL ( XEXP ( ind , 1 ) ) & 3 ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a memory operand which we can load or store a vector to/from . TYPE is one of the following values : 0 - Vector load/stor ( vldr ) 1 - Core registers ( ldm ) 2 - Element/structure loads ( vld1 )


<s> bool isBlockAddress ( ) { return Kind == ARMCP :: CPBlockAddress ; } </s>

isBlockAddress - Tests if this is a MO_BlockAddress operand .


<s> void X86MCCodeEmitter :: emitPrefix ( const MCInst & MI , raw_ostream & OS , const MCSubtargetInfo & STI ) const { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t TSFlags = Desc . TSFlags ; if ( X86II :: isPseudo ( TSFlags ) ) return ; unsigned CurOp = X86II :: getOperandBias ( Desc ) ; emitPrefixImpl ( CurOp , MI , STI , OS ) ; } </s>

Append the prefixes of given instruction to the code buffer .


<s> const CallLowering * ARMSubtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s> const uint32_t * ARM64RegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID ) const { return CSR_ARM64_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool RegDefsUses :: update ( const MachineInstr & MI , unsigned Begin , unsigned End ) { BitVector NewDefs ( TRI . getNumRegs ( ) ) , NewUses ( TRI . getNumRegs ( ) ) ; bool HasHazard = false ; for ( unsigned I = Begin ; I != End ; ++ I ) { const MachineOperand & MO = MI . getOperand ( I ) ; if ( MO . isReg ( ) && MO . getReg ( ) ) HasHazard |= checkRegDefsUses ( NewDefs , NewUses , MO . getReg ( ) , MO . isDef ( ) ) ; } Defs |= NewDefs ; Uses |= NewUses ; return HasHazard ; } </s>


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static void vr4130_true_reg_dependence_p_1 ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * insn_ptr ; insn_ptr = ( rtx * ) data ; if ( REG_P ( x ) && * insn_ptr != 0 && reg_referenced_p ( x , PATTERN ( * insn_ptr ) ) ) * insn_ptr = 0 ; } </s>

A note_stores callback used by vr4130_true_reg_dependence_p . DATA points to an rtx that is initially an instruction . Nullify the rtx if the instruction uses the value of register X .


<s> void MipsTargetELFStreamer :: emitAssignment ( MCSymbol * S , const MCExpr * Value ) { auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const auto & RhsSym = cast < MCSymbolELF > ( static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ) ; if ( ! ( RhsSym . getOther ( ) & ELF :: STO_MIPS_MICROMIPS ) ) return ; Symbol -> setOther ( ELF :: STO_MIPS_MICROMIPS ) ; } </s>


<s> tree arm_resolve_overloaded_builtin ( location_t loc , tree fndecl , void * arglist ) { if ( arm_describe_resolver ( fndecl ) == arm_cde_resolver ) return arm_resolve_cde_builtin ( loc , fndecl , arglist ) ; return NULL_TREE ; } </s>

Implement TARGET_RESOLVE_OVERLOADED_BUILTIN . This is currently only used for the MVE related builtins for the CDE extension . Here we ensure the type of arguments is such that the size is correct , and then return a tree that describes the same function call but with the relevant types cast as necessary .


<s> int xstormy16_initial_elimination_offset ( int from , int to ) { struct xstormy16_stack_layout layout ; int result ; layout = xstormy16_compute_stack_layout ( ) ; if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = layout . sp_minus_fp - layout . locals_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - layout . locals_size ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = - layout . fp_minus_ap ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - ( layout . sp_minus_fp + layout . fp_minus_ap ) ; else gcc_unreachable ( ) ; return result ; } </s>

Determine how all the special registers get eliminated .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static void loongarch_restore_reg ( rtx reg , rtx mem ) { rtx insn = loongarch_emit_move ( reg , mem ) ; rtx dwarf = NULL_RTX ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; REG_NOTES ( insn ) = dwarf ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>


<s> static bool nds32_legitimate_index_p ( machine_mode outer_mode , rtx index , bool strict ) { int regno ; rtx op0 ; rtx op1 ; switch ( GET_CODE ( index ) ) { case REG : regno = REGNO ( index ) ; if ( strict ) return REGNO_OK_FOR_INDEX_P ( regno ) ; else return true ; case CONST_INT : switch ( GET_MODE_SIZE ( outer_mode ) ) { case 1 : if ( satisfies_constraint_Is15 ( index ) ) return true ; break ; case 2 : if ( satisfies_constraint_Is16 ( index ) ) { if ( ! cfun -> machine -> strict_aligned_p ) return true ; else if ( NDS32_HALF_WORD_ALIGN_P ( INTVAL ( index ) ) ) return true ; } break ; case 4 : if ( satisfies_constraint_Is17 ( index ) ) { if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) ) { if ( ! satisfies_constraint_Is14 ( index ) ) return false ; } if ( ! cfun -> machine -> strict_aligned_p ) return true ; else if ( NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( index ) ) ) return true ; } break ; case 8 : if ( satisfies_constraint_Is17 ( gen_int_mode ( INTVAL ( index ) + 4 , SImode ) ) ) { if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) ) { if ( ! satisfies_constraint_Is14 ( index ) ) return false ; } if ( ! cfun -> machine -> strict_aligned_p ) return true ; else if ( NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( index ) ) ) return true ; } break ; default : return false ; } return false ; case MULT : op0 = XEXP ( index , 0 ) ; op1 = XEXP ( index , 1 ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) ) { int multiplier ; multiplier = INTVAL ( op1 ) ; if ( multiplier != 1 && multiplier != 2 && multiplier != 4 && multiplier != 8 ) return false ; regno = REGNO ( op0 ) ; if ( strict ) return REGNO_OK_FOR_INDEX_P ( regno ) ; else return true ; } return false ; case ASHIFT : op0 = XEXP ( index , 0 ) ; op1 = XEXP ( index , 1 ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) ) { int sv ; sv = INTVAL ( op1 ) ; if ( sv != 0 && sv != 1 && sv != 2 && sv != 3 ) return false ; regno = REGNO ( op0 ) ; if ( strict ) return REGNO_OK_FOR_INDEX_P ( regno ) ; else return true ; } return false ; default : return false ; } } </s>

Function that check if 'INDEX ' is valid to be a index rtx for address . OUTER_MODE : Machine mode of outer address rtx . INDEX : Check if this rtx is valid to be a index for address . STRICT : If it is true , we are in reload pass or after reload pass .


<s> enum reg_class mips_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx x , bool ) { int regno ; if ( mips_dangerous_for_la25_p ( x ) ) return reg_class_subset_p ( rclass , LEA_REGS ) ? NO_REGS : LEA_REGS ; regno = true_regnum ( x ) ; if ( TARGET_MIPS16 ) { if ( ! reg_class_subset_p ( rclass , M16_REGS ) && ! M16_REG_P ( regno ) ) return M16_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , ACC_REGS ) ) return GP_REG_P ( regno ) ? NO_REGS : GR_REGS ; if ( ACC_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; if ( reg_class_subset_p ( rclass , FP_REGS ) ) { if ( regno < 0 || ( MEM_P ( x ) && ( GET_MODE_SIZE ( mode ) == 4 || GET_MODE_SIZE ( mode ) == 8 ) ) ) return NO_REGS ; if ( MEM_P ( x ) && MSA_SUPPORTED_MODE_P ( mode ) ) return NO_REGS ; if ( GP_REG_P ( regno ) || x == CONST0_RTX ( mode ) ) return NO_REGS ; if ( CONSTANT_P ( x ) && ! targetm . cannot_force_const_mem ( mode , x ) ) return NO_REGS ; if ( FP_REG_P ( regno ) && mips_mode_ok_for_mov_fmt_p ( mode ) ) return NO_REGS ; return GR_REGS ; } if ( FP_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; return NO_REGS ; } </s>

This function returns the register class required for a secondary register when copying between one of the registers in CLASS , and X , using MODE . If IN_P is nonzero , the copy is going from X to the register , otherwise the register is the source . A return value of NO_REGS means that no secondary register is required .


" was Pass-through, is now Dirty-out.\n"


<s>
void
X86AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
X86MCInstLower
MCInstLowering
(
Mang
,
*
MF
,
*
this
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
TargetOpcode
::
DBG_VALUE
:
if
(
isVerbose
(
)
&&
OutStreamer
.
hasRawTextSupport
(
)
)
{
std
::
string
TmpStr
;
raw_string_ostream
OS
(
TmpStr
)
;
PrintDebugValueComment
(
MI
,
OS
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
OS
.
str
(
)
)
)
;
}
return
;
case
X86
::
Int_MemBarrier
:
if
(
OutStreamer
.
hasRawTextSupport
(
)
)
OutStreamer
.
EmitRawText
(
StringRef
(
"\t#MEMBARRIER"
)
)
;
return
;
case
X86
::
EH_RETURN
:
case
X86
::
EH_RETURN64
:
{
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
OutStreamer
.
AddComment
(
StringRef
(
"eh_return, addr: %"
)
+
X86ATTInstPrinter
::
getRegisterName
(
Reg
)
)
;
break
;
}
case
X86
::
TAILJMPr
:
case
X86
::
TAILJMPd
:
case
X86
::
TAILJMPd64
:
OutStreamer
.
AddComment
(
"TAILCALL"
)
;
break
;
case
X86
::
TLS_addr32
:
case
X86
::
TLS_addr64
:
case
X86
::
TLS_base_addr32
:
case
X86
::
TLS_base_addr64
:
return
LowerTlsAddr
(
OutStreamer
,
MCInstLowering
,
*
MI
)
;
case
X86
::
MOVPC32r
:
{
MCSymbol
*
PICBase
=
MF
->
getPICBaseSymbol
(
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
getSubtarget
(
)
.
isTargetNaCl
(
)
X86
::
NACL_CALL32d
:
X86
::
CALLpcrel32
)
.
addExpr
(
MCSymbolRefExpr
::
Create
(
PICBase
,
OutContext
)
)
)
;
OutStreamer
.
EmitLabel
(
PICBase
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
POP32r
)
.
addReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
return
;
}
case
X86
::
ADD32ri
:
{
if
(
MI
->
getOperand
(
2
)
.
getTargetFlags
(
)
!=
X86II
::
MO_GOT_ABSOLUTE_ADDRESS
)
break
;
MCSymbol
*
DotSym
=
OutContext
.
CreateTempSymbol
(
)
;
OutStreamer
.
EmitLabel
(
DotSym
)
;
MCSymbol
*
OpSym
=
MCInstLowering
.
GetSymbolFromOperand
(
MI
->
getOperand
(
2
)
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
Create
(
DotSym
,
OutContext
)
;
const
MCExpr
*
PICBase
=
MCSymbolRefExpr
::
Create
(
MF
->
getPICBaseSymbol
(
)
,
OutContext
)
;
DotExpr
=
MCBinaryExpr
::
CreateSub
(
DotExpr
,
PICBase
,
OutContext
)
;
DotExpr
=
MCBinaryExpr
::
CreateAdd
(
MCSymbolRefExpr
::
Create
(
OpSym
,
OutContext
)
,
DotExpr
,
OutContext
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
ADD32ri
)
.
addReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addExpr
(
DotExpr
)
)
;
return
;
}
}
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static unsigned int aarch64_hard_regno_nregs ( unsigned regno , machine_mode mode ) { HOST_WIDE_INT lowest_size = constant_lower_bound ( GET_MODE_SIZE ( mode ) ) ; switch ( aarch64_regno_regclass ( regno ) ) { case FP_REGS : case FP_LO_REGS : case FP_LO8_REGS : { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_DATA ) return exact_div ( GET_MODE_SIZE ( mode ) , aarch64_vl_bytes ( mode , vec_flags ) ) . to_constant ( ) ; return CEIL ( lowest_size , UNITS_PER_VREG ) ; } case PR_REGS : case PR_LO_REGS : case PR_HI_REGS : case FFR_REGS : case PR_AND_FFR_REGS : return 1 ; default : return CEIL ( lowest_size , UNITS_PER_WORD ) ; } gcc_unreachable ( ) ; } </s>


<s> bool AArch64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0xd503201f ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static rtx mips_frame_set ( rtx mem , rtx reg ) { rtx set ; if ( REGNO ( reg ) == GP_REG_FIRST + 31 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31 ) reg = gen_rtx_REG ( GET_MODE ( reg ) , DWARF_FRAME_RETURN_COLUMN ) ; set = gen_rtx_SET ( VOIDmode , mem , reg ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; return set ; } </s>

Return a frame-related rtx that stores register REGNO at ( SP + OFFSET ) . The expression should only be used to store single registers .


<s> const TargetRegisterClass * AArch64RegisterInfo :: getSubClassWithSubReg ( const TargetRegisterClass * RC , unsigned Idx ) const { if ( RC == & AArch64 :: GPR32allRegClass && Idx == AArch64 :: hsub ) return & AArch64 :: FPR32RegClass ; else if ( RC == & AArch64 :: GPR64allRegClass && Idx == AArch64 :: hsub ) return & AArch64 :: FPR64RegClass ; return AArch64GenRegisterInfo :: getSubClassWithSubReg ( RC , Idx ) ; } </s>

Returns the largest legal sub-class of RC that supports the sub-register index Idx .


Return a string to perform a load_multiple operation . operands [ 0 ] is the vector . operands [ 1 ] is the source address . operands [ 2 ] is the first destination register .


<s>
void
LanaiDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
if
(
VT
==
MVT
::
i32
)
{
ConstantSDNode
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
Lanai
::
R0
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
if
(
ConstNode
->
isAllOnesValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
Lanai
::
R1
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
}
break
;
case
ISD
::
FrameIndex
:
selectFrameIndex
(
Node
)
;
return
;
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> const uint16_t * LC3RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { LC3 :: R4 , LC3 :: R5 , LC3 :: R6 , LC3 :: R7 , LC3 :: R8 , LC3 :: R9 , 0 } ; return CalleeSavedRegs ; } </s>


<s> void vax_expand_prologue ( void ) { int regno , offset ; int mask = 0 ; HOST_WIDE_INT size ; rtx insn ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) mask |= 1 << regno ; insn = emit_insn ( gen_procedure_entry_mask ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; vax_add_reg_cfa_offset ( insn , 4 , arg_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , 8 , frame_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , 12 , pc_rtx ) ; offset = 16 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( mask & ( 1 << regno ) ) { vax_add_reg_cfa_offset ( insn , offset , gen_rtx_REG ( SImode , regno ) ) ; offset += 4 ; } add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , frame_pointer_rtx , offset ) ) ; size = get_frame_size ( ) ; size -= vax_starting_frame_offset ( ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ; emit_insn ( gen_blockage ( ) ) ; } </s>

Generate the assembly code for function entry . FILE is a stdio stream to output the code to . SIZE is an int : how many units of temporary storage to allocate . Refer to the array ` regs_ever_live ' to determine which registers to save ; ` regs_ever_live [ I ] ' is nonzero if register number I is ever used in the function . This function is responsible for knowing which registers should not be saved even if used .


<s> void MipsFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned StackSize = MFI -> getStackSize ( ) ; unsigned NewReg = 0 ; int NewImm = 0 ; bool ATUsed = false ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; } if ( StackSize ) { ATUsed = expandRegLargeImmPair ( Mips :: SP , StackSize , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( NewReg ) . addImm ( NewImm ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ATMACRO ) ) ; } } </s>

Mips Mips Mips Mips 0 0 0 Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::SP Mips::ADDiu Mips::SP Mips::ATMACRO


<s> SDValue PPCTargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRSQRTES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRSQRTE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasQPX ( ) ) || ( VT == MVT :: v4f64 && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = ! Subtarget . needsTwoConstNR ( ) ; return DAG . getNode ( PPCISD :: FRSQRTE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
MF
.
getFunction
(
)
.
isPagerando
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool isMem ( ) const override { return isMemImm ( ) || isMemRegImm ( ) || isMemRegReg ( ) ; } </s>


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; TII . restoreFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips::Move32R16 Mips::SP Mips::S0 Mips::SP


<s> rtx pa_eh_return_handler_rtx ( void ) { rtx tmp ; tmp = gen_rtx_PLUS ( word_mode , hard_frame_pointer_rtx , TARGET_64BIT ? GEN_INT ( - 16 ) : GEN_INT ( - 20 ) ) ; tmp = gen_rtx_MEM ( word_mode , tmp ) ; tmp -> volatil = 1 ; return tmp ; } </s>

Implement EH_RETURN_HANDLER_RTX . The MEM needs to be volatile to prevent it from being deleted .


<s> static void nds32_conditional_register_usage ( void ) { int regno ; if ( TARGET_LINUX_ABI ) fixed_regs [ TP_REGNUM ] = 1 ; if ( TARGET_HARD_FLOAT ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 0 ; if ( regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS ) call_used_regs [ regno ] = 1 ; else if ( regno >= NDS32_FIRST_FPR_REGNUM + 22 && regno < NDS32_FIRST_FPR_REGNUM + 48 ) call_used_regs [ regno ] = 1 ; else call_used_regs [ regno ] = 0 ; } } else if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) fixed_regs [ regno ] = 0 ; } } </s>


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; TII . restoreFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; } </s>


<s> bool ARM64TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = getDataLayout ( ) -> getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( Offset >= - ( 1LL << 9 ) && Offset <= ( 1LL << 9 ) - 1 ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } if ( ! AM . Scale || AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ) return true ; return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool X86TargetLowering :: areJTsAllowed ( const Function * Fn ) const { if ( Subtarget . useRetpolineIndirectBranches ( ) ) return false ; return TargetLowering :: areJTsAllowed ( Fn ) ; } </s>

Returns true if lowering to a jump table is allowed .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , 8 , 0 ) { } </s>


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen_neon_vtrn_internal ( d -> vmode , out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
->
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> const MCSchedClassDesc * getSchedClass ( SUnit * SU ) const { if ( ! SU -> SchedClass && SchedModel -> hasInstrSchedModel ( ) ) SU -> SchedClass = SchedModel -> resolveSchedClass ( SU -> getInstr ( ) ) ; return SU -> SchedClass ; } </s>

Resolves and cache a resolved scheduling class for an SUnit .


<s> static bool sparc_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { if ( TARGET_ARCH32 ) return ( TYPE_MODE ( type ) == BLKmode || TYPE_MODE ( type ) == TFmode || ( TREE_CODE ( type ) == VECTOR_TYPE && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( TYPE_MODE ( type ) == BLKmode && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 32 ) ; } </s>

Handle the TARGET_RETURN_IN_MEMORY target hook . Specify whether to return the return value in memory .


"the %qE attribute cannot be applied to an SVE function type"

Check whether an 'aarch64_vector_pcs ' attribute is valid .


"missing architecture name in 'arch' target %s"

"unknown value %qs for 'arch' target %s"

"invalid feature modifier %qs for 'arch' target %s"

Handle the ARCH_STR argument to the arch= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> static const char * detect_processor_aix ( void ) { switch ( _system_configuration . implementation ) { case 0x0008 : return "601" ; case 0x0020 : return "603" ; case 0x0010 : return "604" ; case 0x0040 : return "620" ; case 0x0080 : return "630" ; case 0x0100 : case 0x0200 : case 0x0400 : return "rs64" ; case 0x0800 : return "power4" ; case 0x2000 : if ( _system_configuration . version == 0x0F0000 ) return "power5" ; else return "power5+" ; case 0x4000 : return "power6" ; case 0x8000 : return "power7" ; case 0x10000 : return "power8" ; case 0x20000 : return "power9" ; default : return "powerpc" ; } } </s>

Returns the processor implementation on AIX .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: VSELECT : case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: ADD : return PerformAddCombine ( N , DAG , Subtarget ) ; case ISD :: SUB : return PerformSubCombine ( N , DAG , Subtarget ) ; case X86ISD :: ADC : return PerformADCCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: AND : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: XOR : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: LOAD : return PerformLOADCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case ISD :: SINT_TO_FP : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case ISD :: FADD : return PerformFADDCombine ( N , DAG , Subtarget ) ; case ISD :: FSUB : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; case X86ISD :: SETCC : return PerformSETCCCombine ( N , DAG ) ; case X86ISD :: SHUFPS : case X86ISD :: SHUFPD : case X86ISD :: PALIGN : case X86ISD :: PUNPCKH : case X86ISD :: UNPCKHP : case X86ISD :: PUNPCKL : case X86ISD :: UNPCKLP : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case X86ISD :: VPERMILP : case X86ISD :: VPERM2X128 : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool X86FastISel :: isTypeLegal ( const Type * Ty , MVT & VT , bool AllowI1 ) { VT = TLI . getValueType ( Ty , true ) ; if ( VT == MVT :: Other || ! VT . isSimple ( ) ) return false ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> static HOST_WIDE_INT ix86_get_frame_size ( void ) { if ( cfun -> machine -> stack_frame_required ) return get_frame_size ( ) ; else return 0 ; } </s>

Return stack frame size . get_frame_size ( ) returns used stack slots during compilation , which may be optimized out later . If stack frame is needed , stack_frame_required should be true .


<s> static rtx mips_unspec_address_offset ( rtx base , rtx offset , enum mips_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , base ) , UNSPEC_ADDRESS_FIRST + symbol_type ) ; if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ; return gen_rtx_CONST ( Pmode , base ) ; } </s>

Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE , then add CONST_INT OFFSET to the result .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( AsmVariant ) { printIntelMemReference ( MI , OpNo , O ) ; return false ; } if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : printMemReference ( MI , OpNo , O , "H" ) ; return false ; case 'P' : printMemReference ( MI , OpNo , O , "no-rip" ) ; return false ; } } printMemReference ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool ARMTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { if ( ! Fast && ! DisableLdStOpti && ! Subtarget . isThumb ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( ! Fast && ! DisableIfConversion && ! Subtarget . isThumb ( ) ) PM . add ( createIfConverterPass ( ) ) ; PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static unsigned aarch64_next_callee_save ( unsigned regno , unsigned limit ) { while ( regno <= limit && ! aarch64_register_saved_on_entry ( regno ) ) regno ++ ; return regno ; } </s>

Return the next register up from REGNO up to LIMIT for the callee to save .


<s> bool X86FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || ( hasFP ( MF ) && ! TRI -> needsStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> static void iq2000_select_section ( tree decl , int reloc ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TARGET_EMBEDDED_DATA ) { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) readonly_data_section ( ) ; else data_section ( ) ; } else { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) readonly_data_section ( ) ; else data_section ( ) ; } } </s>

Choose the section to use for DECL . RELOC is true if its value contains any relocatable expression . Some of the logic used here needs to be replicated in ENCODE_SECTION_INFO in iq2000.h so that references to these symbols are done correctly .


<s> static bool expand_vec_perm_vpermi2_vpshub2 ( struct expand_vec_perm_d * d ) { if ( ! TARGET_AVX512BW || ! ( d -> vmode == V64QImode ) ) return false ; if ( d -> testing_p ) return true ; struct expand_vec_perm_d ds [ 2 ] ; rtx rperm [ 128 ] , vperm , target0 , target1 ; unsigned int i , nelt ; machine_mode vmode ; nelt = d -> nelt ; vmode = V64QImode ; for ( i = 0 ; i < 2 ; i ++ ) { ds [ i ] = * d ; ds [ i ] . vmode = V32HImode ; ds [ i ] . nelt = 32 ; ds [ i ] . target = gen_reg_rtx ( V32HImode ) ; ds [ i ] . op0 = gen_lowpart ( V32HImode , d -> op0 ) ; ds [ i ] . op1 = gen_lowpart ( V32HImode , d -> op1 ) ; } for ( i = 0 ; i < nelt ; i ++ ) { ds [ i & 1 ] . perm [ i / 2 ] = d -> perm [ i ] / 2 ; if ( i & 1 ) { rperm [ i ] = constm1_rtx ; rperm [ i + 64 ] = GEN_INT ( ( i & 14 ) + ( d -> perm [ i ] & 1 ) ) ; } else { rperm [ i ] = GEN_INT ( ( i & 14 ) + ( d -> perm [ i ] & 1 ) ) ; rperm [ i + 64 ] = constm1_rtx ; } } bool ok = expand_vec_perm_1 ( & ds [ 0 ] ) ; gcc_assert ( ok ) ; ds [ 0 ] . target = gen_lowpart ( V64QImode , ds [ 0 ] . target ) ; ok = expand_vec_perm_1 ( & ds [ 1 ] ) ; gcc_assert ( ok ) ; ds [ 1 ] . target = gen_lowpart ( V64QImode , ds [ 1 ] . target ) ; vperm = gen_rtx_CONST_VECTOR ( V64QImode , gen_rtvec_v ( 64 , rperm ) ) ; vperm = force_reg ( vmode , vperm ) ; target0 = gen_reg_rtx ( V64QImode ) ; emit_insn ( gen_avx512bw_pshufbv64qi3 ( target0 , ds [ 0 ] . target , vperm ) ) ; vperm = gen_rtx_CONST_VECTOR ( V64QImode , gen_rtvec_v ( 64 , rperm + 64 ) ) ; vperm = force_reg ( vmode , vperm ) ; target1 = gen_reg_rtx ( V64QImode ) ; emit_insn ( gen_avx512bw_pshufbv64qi3 ( target1 , ds [ 1 ] . target , vperm ) ) ; emit_insn ( gen_iorv64qi3 ( d -> target , target0 , target1 ) ) ; return true ; } </s>

Implement arbitrary permutations of two V64QImode operands will 2 vpermi2w , 2 vpshufb and one vpor instruction .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> X86GenInstrInfo :: MachineOutlinerInstrType X86InstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MIT , unsigned Flags ) const { MachineInstr & MI = * MIT ; if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( MI . isKill ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> int loongarch_split_const_insns ( rtx x ) { unsigned int low , high ; low = loongarch_const_insns ( loongarch_subword ( x , false ) ) ; high = loongarch_const_insns ( loongarch_subword ( x , true ) ) ; gcc_assert ( low > 0 && high > 0 ) ; return low + high ; } </s>

X is a doubleword constant that can be handled by splitting it into two words and loading each word separately . Return the number of instructions required to do this .


<s> const char * mips_output_sync ( void ) { mips_start_ll_sc_sync_block ( ) ; output_asm_insn ( "sync" , 0 ) ; mips_end_ll_sc_sync_block ( ) ; return "" ; } </s>

Output and/or return the asm template for a sync instruction .


<s> DecodeStatus SystemZDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { Size = 0 ; if ( Bytes . size ( ) < 2 ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ 0 ] < 0x40 ) { Size = 2 ; Table = DecoderTable16 ; } else if ( Bytes [ 0 ] < 0xc0 ) { Size = 4 ; Table = DecoderTable32 ; } else { Size = 6 ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) { Size = Bytes . size ( ) ; return MCDisassembler :: Fail ; } uint64_t Inst = 0 ; for ( uint64_t I = 0 ; I < Size ; ++ I ) Inst = ( Inst << 8 ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> bool isPPC64 ( ) const { Triple TT ( getTargetTriple ( ) ) ; return ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) ; } </s>

Tests whether the target is 64-bit PowerPC ( little and big endian ) .


<s> MMIXSubtarget & MMIXSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic-mmix" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"Should be loading %r15 and something else"


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + 1 ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ 0 ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( 2 , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = 1 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_or_fixed_reg_p ( i ) ) clobs [ nclobs ++ ] = gen_hard_reg_clobber ( V4SImode , i ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( 1 , reg ) , 27 ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = 0 ; i < nclobs ; ++ i ) XVECEXP ( insn , 0 , i ) = clobs [ i ] ; return insn ; } </s>

Returns an insn that has a vrsave set operation with the appropriate CLOBBERs .


<s> bool Cpu0TargetObjectFile :: IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) || Kind . isReadOnly ( ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static int ix86_fp_cmp_code_to_pcmp_immediate ( enum rtx_code code ) { switch ( code ) { case EQ : return 0x08 ; case NE : return 0x04 ; case GT : return 0x16 ; case LE : return 0x1a ; case GE : return 0x15 ; case LT : return 0x19 ; default : gcc_unreachable ( ) ; } } </s>

Helper for ix86_cmp_code_to_pcmp_immediate for fp modes .


<s> const MipsMCExpr * MipsMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) MipsMCExpr ( Kind , Expr ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> bool Mips16InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA16 : ExpandRetRA16 ( MBB , MI , Mips :: JrcRa16 ) ; break ; } MBB . erase ( MI . getIterator ( ) ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; if ( Subtarget . isTargetNaCl ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr : return selectGetElementPtr ( I ) ; case Instruction :: AtomicCmpXchg : return selectAtomicCmpXchg ( cast < AtomicCmpXchgInst > ( I ) ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; ( void ) & CC_AArch64_DarwinPCS_VarArg ; ( void ) & CC_AArch64_Win64_VarArg ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


"rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n"

A C expressions returning the cost of moving data of MODE from a register to or from memory .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( N ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC