<s>
void
ARMBaseInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
bool
GPRDest
=
ARM
::
GPRRegClass
.
contains
(
DestReg
)
;
bool
GPRSrc
=
ARM
::
GPRRegClass
.
contains
(
SrcReg
)
;
if
(
GPRDest
&&
GPRSrc
)
{
AddDefaultCC
(
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
MOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
)
;
return
;
}
bool
SPRDest
=
ARM
::
SPRRegClass
.
contains
(
DestReg
)
;
bool
SPRSrc
=
ARM
::
SPRRegClass
.
contains
(
SrcReg
)
;
unsigned
Opc
=
0
;
if
(
SPRDest
&&
SPRSrc
)
Opc
=
ARM
::
VMOVS
;
else
if
(
GPRDest
&&
SPRSrc
)
Opc
=
ARM
::
VMOVRS
;
else
if
(
SPRDest
&&
GPRSrc
)
Opc
=
ARM
::
VMOVSR
;
else
if
(
ARM
::
DPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
ARM
::
VMOVD
;
else
if
(
ARM
::
QPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
ARM
::
VORRq
;
if
(
Opc
)
{
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
;
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
if
(
Opc
==
ARM
::
VORRq
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
AddDefaultPred
(
MIB
)
;
return
;
}
if
(
ARM
::
QQPRRegClass
.
contains
(
DestReg
,
SrcReg
)
||
ARM
::
QQQQPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
assert
(
ARM
::
qsub_0
+
3
==
ARM
::
qsub_3
&&
"Expected contiguous enum."
)
;
unsigned
EndSubReg
=
ARM
::
QQPRRegClass
.
contains
(
DestReg
,
SrcReg
)
ARM
::
qsub_1
:
ARM
::
qsub_3
;
for
(
unsigned
i
=
ARM
::
qsub_0
,
e
=
EndSubReg
+
1
;
i
!=
e
;
++
i
)
{
unsigned
Dst
=
TRI
->
getSubReg
(
DestReg
,
i
)
;
unsigned
Src
=
TRI
->
getSubReg
(
SrcReg
,
i
)
;
MachineInstrBuilder
Mov
=
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
get
(
ARM
::
VORRq
)
)
.
addReg
(
Dst
,
RegState
::
Define
)
.
addReg
(
Src
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
Src
,
getKillRegState
(
KillSrc
)
)
)
;
if
(
i
==
EndSubReg
)
{
Mov
->
addRegisterDefined
(
DestReg
,
TRI
)
;
if
(
KillSrc
)
Mov
->
addRegisterKilled
(
SrcReg
,
TRI
)
;
}
}
return
;
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>

ARM
ARM
ARM::GPRRegClass
ARM::GPRRegClass
ARM::MOVr
ARM::SPRRegClass
ARM::SPRRegClass
0
ARM::VMOVS
ARM::VMOVRS
ARM::VMOVSR
ARM::DPRRegClass
ARM::VMOVD
ARM::QPRRegClass
ARM::VORRq
ARM::VORRq
ARM::QQPRRegClass
ARM::QQQQPRRegClass
ARM::qsub_0
3
ARM::qsub_3
"Expected contiguous enum."
ARM::QQPRRegClass
ARM::qsub_1
ARM::qsub_3
ARM::qsub_0
1
ARM::VORRq
"Impossible reg-to-reg copy"


<s> static bool aarch64_simd_call_p ( rtx_insn * insn ) { rtx symbol ; rtx call ; tree fndecl ; gcc_assert ( CALL_P ( insn ) ) ; call = get_call_rtx_from ( insn ) ; symbol = XEXP ( XEXP ( call , 0 ) , 0 ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return false ; fndecl = SYMBOL_REF_DECL ( symbol ) ; if ( ! fndecl ) return false ; return aarch64_simd_decl_p ( fndecl ) ; } </s>

Return true if the instruction is a call to a SIMD function , false if it is not a SIMD function or if we do not know anything about the function .


<s> static unsigned int mips_mult_zero_zero_cost ( struct mips_sim * state , bool setting ) { mips_tuning_info . fast_mult_zero_zero_p = setting ; start_sequence ( ) ; machine_mode dword_mode = TARGET_64BIT ? TImode : DImode ; rtx hilo = gen_rtx_REG ( dword_mode , MD_REG_FIRST ) ; mips_emit_move_or_split ( hilo , const0_rtx , SPLIT_FOR_SPEED ) ; if ( dword_mode == DImode && HAVE_maddsidi4 ) { rtx gpr = gen_rtx_REG ( SImode , GP_REG_FIRST + 4 ) ; emit_insn ( gen_maddsidi4 ( hilo , gpr , gpr , hilo ) ) ; } unsigned int time = mips_seq_time ( state , get_insns ( ) ) ; end_sequence ( ) ; return time ; } </s>

Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p setting SETTING , using STATE to simulate instruction sequences .


"Expected one implicit def for call instruction"

Initialize the machine model for instruction scheduling .


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new X86PassConfig ( this , PM , Subtarget . is64Bit ( ) ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool AArch64TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; return ( CallerBits & CalleeBits ) == CalleeBits ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> void X86FlagsCopyLoweringPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void mt_emit_save_fp ( enum save_direction direction , struct mt_frame_info info ) { rtx base_reg ; int reg_mask = info . reg_mask & ~ ( FP_MASK | LINK_MASK ) ; int offset = info . total_size ; int stack_offset = info . total_size ; if ( ! info . save_fp && ! info . save_lr && ! reg_mask ) return ; if ( CONST_OK_FOR_LETTER_P ( offset , 'O' ) ) base_reg = stack_pointer_rtx ; else { base_reg = gen_rtx_REG ( SImode , GPR_R9 ) ; offset = 0 ; } if ( info . save_fp ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , GPR_FP ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) ) ) , stack_offset ) ; } } </s>

Emit code to save the frame pointer in the prologue and restore frame pointer in epilogue .


<s> bool AArch64InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MBBI ) const { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case AArch64 :: TLSDESC_BLRx : { MachineInstr * NewMI = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , get ( AArch64 :: TLSDESCCALL ) ) . addOperand ( MI . getOperand ( 1 ) ) ; MI . setDesc ( get ( AArch64 :: BLRx ) ) ; llvm :: finalizeBundle ( MBB , NewMI , * ++ MBBI ) ; return true ; } default : return false ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static bool arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_VFP_BASE && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( IS_VPR_REGNUM ( regno ) ) return VALID_MVE_PRED_MODE ( mode ) ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_VFP_BASE && IS_VFP_REGNUM ( regno ) ) { if ( mode == DFmode || mode == DImode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode || mode == BFmode || mode == HImode || mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; if ( TARGET_HAVE_MVE ) return ( ( VALID_MVE_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ) ; return false ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return false ; if ( TARGET_THUMB2 && ! ( TARGET_HAVE_MVE || TARGET_CDE ) ) return true ; return ! ( ( TARGET_LDRD || TARGET_CDE ) && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return false ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> void ix86_split_fp_branch ( enum rtx_code code , rtx op1 , rtx op2 , rtx target1 , rtx target2 , rtx tmp ) { rtx condition ; rtx_insn * i ; if ( target2 != pc_rtx ) { std :: swap ( target1 , target2 ) ; code = reverse_condition_maybe_unordered ( code ) ; } condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp ) ; i = emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( split_branch_probability >= 0 ) add_int_reg_note ( i , REG_BR_PROB , split_branch_probability ) ; } </s>

Split branch based on floating point condition .


<s> static bool spe_func_has_64bit_regs_p ( void ) { rtx_insn * insns , * insn ; if ( crtl -> calls_eh_return || cfun -> calls_setjmp || crtl -> has_nonlocal_goto ) return true ; insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || FLOAT128_2REG_P ( mode ) ) ) return true ; } } } return false ; } </s>

Return true if the current function uses any GPRs in 64-bit SIMD mode .


"%<__builtin_mffsl%> not supported with %<-msoft-float%>"

Expand an expression EXP that calls a builtin without arguments .


<s> static void aarch64_emit_sve_fp_cond ( rtx target , rtx_code code , rtx pred , bool known_ptrue_p , rtx op0 , rtx op1 ) { rtx flag = gen_int_mode ( known_ptrue_p , SImode ) ; rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( pred ) , gen_rtvec ( 4 , pred , flag , op0 , op1 ) , aarch64_unspec_cond_code ( code ) ) ; emit_set_insn ( target , unspec ) ; } </s>

Emit : ( set TARGET ( unspec [ PRED KNOWN_PTRUE_P OP0 OP1 ] UNSPEC_COND_ < X > ) ) where < X > is the operation associated with comparison CODE . KNOWN_PTRUE_P is true if PRED is known to be a PTRUE .


<s> const char * mips_output_probe_stack_range ( rtx reg1 , rtx reg2 ) { static int labelno = 0 ; char loop_lab [ 32 ] , tmp [ 64 ] ; rtx xops [ 2 ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , "LPSRL" , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ 0 ] = reg1 ; xops [ 1 ] = GEN_INT ( - PROBE_INTERVAL ) ; if ( TARGET_64BIT && TARGET_LONG64 ) output_asm_insn ( "daddiu\t%0,%0,%1" , xops ) ; else output_asm_insn ( "addiu\t%0,%0,%1" , xops ) ; xops [ 1 ] = reg2 ; strcpy ( tmp , "%(%<bne\t%0,%1," ) ; output_asm_insn ( strcat ( tmp , & loop_lab [ 1 ] ) , xops ) ; if ( TARGET_64BIT ) output_asm_insn ( "sd\t$0,0(%0)%)" , xops ) ; else output_asm_insn ( "sw\t$0,0(%0)%)" , xops ) ; return "" ; } </s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> bool X86TargetLowering :: areJTsAllowed ( const Function * Fn ) const { if ( Subtarget . useIndirectThunkBranches ( ) ) return false ; return TargetLowering :: areJTsAllowed ( Fn ) ; } </s>

Returns true if lowering to a jump table is allowed .


<s> void x86_order_regs_for_local_alloc ( void ) { int pos = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] = 0 ; } </s>

Order the registers for register allocator .


<s> static bool arm_legitimate_constant_p_1 ( machine_mode , rtx x ) { if ( GET_CODE ( x ) == CONST_VECTOR && ! neon_make_constant ( x , false ) ) return false ; return flag_pic || ! label_mentioned_p ( x ) ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . On the ARM , allow any integer ( invalid ones are removed later by insn patterns ) , nice doubles and symbol_refs which refer to the function 's constant pool XXX . When generating pic allow anything .


<s> static rtx rs6000_mixed_function_arg ( enum machine_mode mode , tree type , int align_words ) { int n_units ; int i , k ; rtx rvec [ GP_ARG_NUM_REG + 1 ] ; if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; n_units = rs6000_arg_size ( mode , type ) ; if ( n_units == 0 || ( n_units == 1 && mode != BLKmode ) ) return gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; k = 0 ; if ( align_words + n_units > GP_ARG_NUM_REG ) rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; i = 0 ; do { rtx r = gen_rtx_REG ( SImode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * 4 ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_units != 0 ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( k , rvec ) ) ; } </s>

Determine where to place an argument in 64-bit mode with 32-bit ABI .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool AArch64TargetLowering :: isLegalInterleavedAccessType ( VectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 && ElSize != 64 ) return false ; return VecSize == 64 || VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


"********** AArch64 Conditional Branch Tuning  **********\n"

runOnMachineFunction - Emit the function body .


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
XOR32rr
)
)
;
case
X86
::
MOV32r1
:
return
expandMOV32r1
(
MIB
,
*
this
,
false
)
;
case
X86
::
MOV32r_1
:
return
expandMOV32r1
(
MIB
,
*
this
,
true
)
;
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
MOV32ri64
:
MI
->
setDesc
(
get
(
X86
::
MOV32ri
)
)
;
return
true
;
case
X86
::
KSET0B
:
case
X86
::
KSET0W
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORWrr
)
,
X86
::
K0
)
;
case
X86
::
KSET0D
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORDrr
)
,
X86
::
K0
)
;
case
X86
::
KSET0Q
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORQrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORWrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1D
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORDrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1Q
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORQrr
)
,
X86
::
K0
)
;
case
TargetOpcode
::
LOAD_STACK_GUARD
:
expandLoadStackGuard
(
MIB
,
*
this
)
;
return
true
;
}
return
false
;
}
</s>


<s>
unsigned
char
X86Subtarget
::
ClassifyGlobalReference
(
const
GlobalValue
*
GV
,
const
TargetMachine
&
TM
)
const
{
if
(
GV
->
hasDLLImportLinkage
(
)
)
return
X86II
::
MO_DLLIMPORT
;
bool
isDecl
=
GV
->
isDeclaration
(
)
&&
!
GV
->
isMaterializable
(
)
;
if
(
isPICStyleRIPRel
(
)
)
{
if
(
TM
.
getCodeModel
(
)
==
CodeModel
::
Large
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
->
hasDefaultVisibility
(
)
&&
(
isDecl
||
GV
->
isWeakForLinker
(
)
)
)
return
X86II
::
MO_GOTPCREL
;
}
else
{
assert
(
isTargetELF
(
)
&&
"Unknown rip-relative target"
)
;
if
(
!
GV
->
hasLocalLinkage
(
)
&&
GV
->
hasDefaultVisibility
(
)
)
return
X86II
::
MO_GOTPCREL
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isPICStyleGOT
(
)
)
{
if
(
GV
->
hasLocalLinkage
(
)
||
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_GOTOFF
;
return
X86II
::
MO_GOT
;
}
if
(
isPICStyleStubPIC
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_PIC_BASE_OFFSET
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
;
}
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
if
(
isPICStyleStubNoDynamic
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY
;
return
X86II
::
MO_NO_FLAG
;
}
return
X86II
::
MO_NO_FLAG
;
}
</s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == 0 ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Windows 32-bit x86 EH state insertion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void ix86_expand_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx set , dst , src ; bool use_sse = false ; bool vector_mode = VECTOR_MODE_P ( mode ) ; machine_mode vmode = mode ; rtvec par ; if ( vector_mode || mode == TFmode || mode == HFmode ) { use_sse = true ; if ( mode == HFmode ) vmode = V8HFmode ; } else if ( TARGET_SSE_MATH ) { use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; } dst = operands [ 0 ] ; src = operands [ 1 ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( dst , set ) ; if ( use_sse ) { rtx mask , use , clob ; mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode || mode == TFmode ) par = gen_rtvec ( 2 , set , use ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 3 , set , use , clob ) ; } } else { rtx clob ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 2 , set , clob ) ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } </s>

Generate code for floating point ABS or NEG .


"No ISEL instructions in this function\n"


<s>
bool
ARMBaseInstrInfo
::
getExtractSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPairAndIdx
&
InputReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isExtractSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VMOVRRD
:
const
MachineOperand
&
MOReg
=
MI
.
getOperand
(
2
)
;
if
(
MOReg
.
isUndef
(
)
)
return
false
;
InputReg
.
Reg
=
MOReg
.
getReg
(
)
;
InputReg
.
SubReg
=
MOReg
.
getSubReg
(
)
;
InputReg
.
SubIdx
=
DefIdx
==
0
ARM
::
ssub_0
:
ARM
::
ssub_1
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getExtractSubregInputs .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Compress Jump Tables"
;
}
</s>


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> const SystemZInstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> static bool classof ( const AArch64MCExpr * E ) { return E -> getKind ( ) == VK_AUTH || E -> getKind ( ) == VK_AUTHADDR ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


Relax the instruction in the given fragment to the next wider instruction .


<s> static bool Check ( DecodeStatus & Out , DecodeStatus In ) { switch ( In ) { case MCDisassembler :: Success : return true ; case MCDisassembler :: SoftFail : Out = In ; return true ; case MCDisassembler :: Fail : Out = In ; return false ; } return false ; } </s>

Matches check string and its `` not strings '' and/or `` dag strings '' .


<s> bool ARM64PassConfig :: addPreSched2 ( ) { addPass ( createARM64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoadStoreOpt ) addPass ( createARM64LoadStoreOptimizationPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> virtual const X86InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static unsigned int rx_function_arg_size ( machine_mode mode , const_tree type ) { unsigned int num_bytes ; num_bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; return rx_round_up ( num_bytes , UNITS_PER_WORD ) ; } </s>

Return the number of bytes in the argument registers occupied by an argument of type TYPE and mode MODE .


<s> bool isFPVectorizationPotentiallyUnsafe ( ) { return ! ST -> isTargetDarwin ( ) && ! ST -> hasMVEFloatOps ( ) ; } </s>

Indicate that it is potentially unsafe to automatically vectorize floating-point operations because the semantics of vector and scalar floating-point semantics may differ .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> uint64_t PPCFrameLowering :: determineFrameLayoutAndUpdate ( MachineFunction & MF , bool UseEstimate ) const { unsigned NewMaxCallFrameSize = 0 ; uint64_t FrameSize = determineFrameLayout ( MF , UseEstimate , & NewMaxCallFrameSize ) ; MF . getFrameInfo ( ) . setStackSize ( FrameSize ) ; MF . getFrameInfo ( ) . setMaxCallFrameSize ( NewMaxCallFrameSize ) ; return FrameSize ; } </s>

Determine the frame layout and update the machine function .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || ! flag_unsafe_math_optimizations ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s> int arm_address_offset_is_imm ( rtx_insn * insn ) { rtx mem , addr ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ 0 ] ) ) return 0 ; mem = recog_data . operand [ 0 ] ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , 0 ) ; if ( REG_P ( addr ) || ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , 0 ) ) && CONST_INT_P ( XEXP ( addr , 1 ) ) ) ) return 1 ; else return 0 ; } </s>

Return nonzero if the offset in the address is an immediate . Otherwise , return zero .


<s> bool ix86_check_movabs ( rtx insn , int opnum ) { rtx set , mem ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; mem = XEXP ( set , opnum ) ; while ( GET_CODE ( mem ) == SUBREG ) mem = SUBREG_REG ( mem ) ; gcc_assert ( MEM_P ( mem ) ) ; return volatile_ok || ! MEM_VOLATILE_P ( mem ) ; } </s>

Return nonzero if OPNUM 's MEM should be matched in movabs * patterns .


<s> bool LanaiRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool isLegalNTStore ( Type * DataType , Align Alignment ) { if ( auto * DataTypeVTy = dyn_cast < VectorType > ( DataType ) ) { unsigned NumElements = DataTypeVTy -> getNumElements ( ) ; unsigned EltSize = DataTypeVTy -> getElementType ( ) -> getScalarSizeInBits ( ) ; return NumElements > 1 && isPowerOf2_64 ( NumElements ) && EltSize >= 8 && EltSize <= 128 && isPowerOf2_64 ( EltSize ) ; } return BaseT :: isLegalNTStore ( DataType , Alignment ) ; } </s>

Return true if the target supports nontemporal store .


<s> static bool pa_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( from == to ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return true ; if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return TARGET_64BIT && from == DImode && to == SImode ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return false ; return true ; } </s>


"Expected a reg or frame index operand."

Return true if this is a load/store that can be potentially paired/merged .


<s>
const
char
*
output_parallel_addb
(
rtx
*
operands
,
int
length
)
{
if
(
operands
[
0
]
==
operands
[
1
]
)
operands
[
1
]
=
operands
[
2
]
;
if
(
length
==
4
)
return
"add%I1b,tr %1,%0,%3"
;
if
(
dbr_sequence_length
(
)
==
0
)
{
return
"b %3\n\tadd%I1 %1,%0,%0"
;
}
else
{
return
"add%I1 %1,%0,%0\n\tb %3"
;
}
}
</s>

Output an unconditional add and branch insn .


Targets may add passes immediately before machine code is emitted in this callback .


<s> Bucket ( const SCEV * B , Instruction * I ) : BaseSCEV ( B ) , Elements ( 1 , BucketElement ( I ) ) { ChainSize = 0 ; } </s>

The bucket assigned by balanced partitioning .


<s> bool ARMBaseInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , isKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int attr_length_save_restore_dltp ( rtx insn ) { if ( find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) return 0 ; return 8 ; } </s>

Return the total length of the save and restore instructions needed for the data linkage table pointer ( i.e. , the PIC register ) across the call instruction INSN . No-return calls do not require a save and restore . In addition , we may be able to avoid the save and restore for calls within the same translation unit .


<s>
void
OpenRISCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
OpenRISC
::
GR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
OpenRISC
::
OR32rr
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s>
void
assignValueToReg
(
unsigned
ValVReg
,
unsigned
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
assert
(
VA
.
getValVT
(
)
.
getSizeInBits
(
)
<=
64
&&
"Unsupported value size"
)
;
assert
(
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"


runOnMachineFunction - Emit the function body .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( Triple ( TT ) ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; this -> Options . Reciprocals . setDefaults ( "all" , false , 1 ) ; initAsmInfo ( ) ; } </s>


<s> unsigned MipsFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? 0 : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return materializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static int ix86_mode_needed ( int entity , rtx_insn * insn ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_needed ( insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return ix86_i387_mode_needed ( entity , insn ) ; default : gcc_unreachable ( ) ; } return 0 ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 1 ) . getImm ( ) ; return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( MI -> getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( ) == 8 ; return createMachObjectWriter ( OS , is64 , ( is64 ? object :: mach :: CTM_PowerPC64 : object :: mach :: CTM_PowerPC ) , object :: mach :: CSPPC_ALL , false ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( SYMBOL_REF_P ( x ) || LABEL_REF_P ( x ) ) ) { if ( ! arm_pic_data_is_text_relative || ( SYMBOL_REF_P ( x ) && ( ! SYMBOL_REF_LOCAL_P ( x ) || ( SYMBOL_REF_DECL ( x ) ? DECL_WEAK ( SYMBOL_REF_DECL ( x ) ) : 0 ) || ( SYMBOL_REF_FUNCTION_P ( x ) && ! arm_fdpic_local_funcdesc_p ( x ) ) ) ) ) { if ( TARGET_FDPIC && SYMBOL_REF_FUNCTION_P ( x ) ) fputs ( "(GOTFUNCDESC)" , asm_out_file ) ; else fputs ( "(GOT)" , asm_out_file ) ; } else { if ( TARGET_FDPIC && SYMBOL_REF_FUNCTION_P ( x ) ) fputs ( "(GOTOFFFUNCDESC)" , asm_out_file ) ; else { bool is_readonly ; if ( ! TARGET_FDPIC || arm_is_segment_info_known ( x , & is_readonly ) ) fputs ( "(GOTOFF)" , asm_out_file ) ; else fputs ( "(GOT)" , asm_out_file ) ; } } } if ( TARGET_FDPIC && ! making_const_table && SYMBOL_REF_P ( x ) && SYMBOL_REF_FUNCTION_P ( x ) ) fputs ( "(FUNCDESC)" , asm_out_file ) ; fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , as_a < scalar_float_mode > ( GET_MODE_INNER ( mode ) ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> bool X86MCInstrAnalysis :: isDependencyBreaking ( const MCSubtargetInfo & STI , const MCInst & Inst ) const { if ( STI . getCPU ( ) == "btver2" ) { switch ( Inst . getOpcode ( ) ) { default : return false ; case X86 :: SUB32rr : case X86 :: SUB64rr : case X86 :: SBB32rr : case X86 :: SBB64rr : case X86 :: XOR32rr : case X86 :: XOR64rr : case X86 :: XORPSrr : case X86 :: XORPDrr : case X86 :: VXORPSrr : case X86 :: VXORPDrr : case X86 :: ANDNPSrr : case X86 :: VANDNPSrr : case X86 :: ANDNPDrr : case X86 :: VANDNPDrr : case X86 :: PXORrr : case X86 :: VPXORrr : case X86 :: PANDNrr : case X86 :: VPANDNrr : case X86 :: PSUBBrr : case X86 :: PSUBWrr : case X86 :: PSUBDrr : case X86 :: PSUBQrr : case X86 :: VPSUBBrr : case X86 :: VPSUBWrr : case X86 :: VPSUBDrr : case X86 :: VPSUBQrr : case X86 :: PCMPEQBrr : case X86 :: PCMPEQWrr : case X86 :: PCMPEQDrr : case X86 :: PCMPEQQrr : case X86 :: VPCMPEQBrr : case X86 :: VPCMPEQWrr : case X86 :: VPCMPEQDrr : case X86 :: VPCMPEQQrr : case X86 :: PCMPGTBrr : case X86 :: PCMPGTWrr : case X86 :: PCMPGTDrr : case X86 :: PCMPGTQrr : case X86 :: VPCMPGTBrr : case X86 :: VPCMPGTWrr : case X86 :: VPCMPGTDrr : case X86 :: VPCMPGTQrr : case X86 :: MMX_PXORirr : case X86 :: MMX_PANDNirr : case X86 :: MMX_PSUBBirr : case X86 :: MMX_PSUBDirr : case X86 :: MMX_PSUBQirr : case X86 :: MMX_PSUBWirr : case X86 :: MMX_PCMPGTBirr : case X86 :: MMX_PCMPGTDirr : case X86 :: MMX_PCMPGTWirr : case X86 :: MMX_PCMPEQBirr : case X86 :: MMX_PCMPEQDirr : case X86 :: MMX_PCMPEQWirr : return Inst . getOperand ( 1 ) . getReg ( ) == Inst . getOperand ( 2 ) . getReg ( ) ; case X86 :: CMP32rr : case X86 :: CMP64rr : return Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ; } } return false ; } </s>

Returns true if MI is a dependency breaking instruction for the subtarget .


<s> static bool aarch64_valid_floating_const ( machine_mode mode , rtx x ) { if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( ! ( mode == SFmode || mode == DFmode ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; return aarch64_float_const_representable_p ( x ) ; } </s>

Return true if X holds either a quarter-precision or floating-point +0.0 constant .


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_PREL_G3
:
return
":prel_g3:"
;
case
VK_PREL_G2
:
return
":prel_g2:"
;
case
VK_PREL_G2_NC
:
return
":prel_g2_nc:"
;
case
VK_PREL_G1
:
return
":prel_g1:"
;
case
VK_PREL_G1_NC
:
return
":prel_g1_nc:"
;
case
VK_PREL_G0
:
return
":prel_g0:"
;
case
VK_PREL_G0_NC
:
return
":prel_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT
:
return
":got:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL
:
return
":gottprel:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> static unsigned int aarch64_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment = aarch64_function_arg_alignment ( mode , type ) ; return MIN ( MAX ( alignment , PARM_BOUNDARY ) , STACK_BOUNDARY ) ; } </s>

Implement FUNCTION_ARG_BOUNDARY . Every parameter gets at least PARM_BOUNDARY bits of alignment , but will be given anything up to STACK_BOUNDARY bits if the type requires it . This makes sure that both before and after the layout of each argument , the Next Stacked Argument Address ( NSAA ) will have a minimum alignment of 8 bytes .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsConstantIslandPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool arm_pad_reg_upward ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type , int first ATTRIBUTE_UNUSED ) { if ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE ) && int_size_in_bytes ( type ) <= 4 ) return true ; return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . For non-AAPCS , return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does . For AAPCS , small aggregates and small complex types are always padded upwards .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { PM . add ( createMipsDelaySlotFillerPass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
;
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARM::tPUSH
ARM::tPOP


<s> WidenVector ( SelectionDAG & DAG ) : DAG ( DAG ) { } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool AArch64InstrInfo :: isPTestLikeOpcode ( unsigned Opc ) const { return get ( Opc ) . TSFlags & AArch64 :: InstrFlagIsPTestLike ; } </s>

Returns true if the opcode is for an SVE instruction that sets the condition codes as if it 's results had been fed to a PTEST instruction along with the same general predicate .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: SExt : return X86SelectSExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: UIToFP : return X86SelectUIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; Register Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; MVT SrcVT , DstVT ; if ( ! isTypeLegal ( I -> getOperand ( 0 ) -> getType ( ) , SrcVT ) || ! isTypeLegal ( I -> getType ( ) , DstVT ) ) return false ; if ( ! SrcVT . isVector ( ) || ! DstVT . isVector ( ) || SrcVT . getVectorElementType ( ) == MVT :: i1 || DstVT . getVectorElementType ( ) == MVT :: i1 ) return false ; Register Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> const ARMInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> unsigned X86FastISel :: fastMaterializeFloatZero ( const ConstantFP * CF ) { MVT VT ; if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return 0 ; bool HasAVX512 = Subtarget -> hasAVX512 ( ) ; unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : return 0 ; case MVT :: f32 : if ( X86ScalarSSEf32 ) Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SS : X86 :: FsFLD0SS ; else Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( X86ScalarSSEf64 ) Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SD : X86 :: FsFLD0SD ; else Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : return 0 ; } Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } </s>

Emit the floating-point constant +0.0 in a register using target- specific logic .


<s> rtx xlogue_layout :: get_stub_rtx ( enum xlogue_stub stub ) { const unsigned n_extra_regs = cfun -> machine -> call_ms2sysv_extra_regs ; gcc_checking_assert ( n_extra_regs <= MAX_EXTRA_REGS ) ; gcc_assert ( stub < XLOGUE_STUB_COUNT ) ; gcc_assert ( crtl -> stack_realign_finalized ) ; return gen_rtx_SYMBOL_REF ( Pmode , get_stub_name ( stub , n_extra_regs ) ) ; } </s>

Return rtx of a symbol ref for the entry point ( based upon cfun- > machine- > call_ms2sysv_extra_regs ) of the specified stub .


<s> static unsigned getTOCSaveOffset ( void ) { return 40 ; } </s>

getTOCSaveOffset - Return the previous frame offset to save the TOC register � ? 64-bit SVR4 ABI only .


<s> rtx function_expander :: use_unpred_insn ( insn_code icode ) { gcc_assert ( pred == PRED_x || pred == PRED_none ) ; unsigned int nops = insn_data [ icode ] . n_operands - 1 ; unsigned int bias = ( pred == PRED_x ? 1 : 0 ) ; unsigned int i = 0 ; add_output_operand ( icode ) ; for ( ; i < nops ; ++ i ) add_input_operand ( icode , args [ i + bias ] ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , which does not use a governing predicate . We must therefore drop the GP from an _x call .


<s> bool ARMBaseInstrInfo :: isSwiftFastImmShift ( const MachineInstr * MI ) const { if ( MI -> getNumOperands ( ) < 4 ) return true ; unsigned ShOpVal = MI -> getOperand ( 3 ) . getImm ( ) ; unsigned ShImm = ARM_AM :: getSORegOffset ( ShOpVal ) ; if ( ( ShImm == 1 && ARM_AM :: getSORegShOp ( ShOpVal ) == ARM_AM :: lsr ) || ( ( ShImm == 1 || ShImm == 2 ) && ARM_AM :: getSORegShOp ( ShOpVal ) == ARM_AM :: lsl ) ) return true ; return false ; } </s>

Returns true if the instruction has a shift by immediate that can be executed in one cycle less .


<s> EVT AArch64TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; if ( VT . isScalableVector ( ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool X86AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO ) ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO ) ; else printOperand ( MI , OpNo ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] ) ; printOperand ( MI , OpNo ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case V2DFmode : case V2DImode : case V2SFmode : case V2SImode : return false ; case V4DImode : if ( ! TARGET_64BIT ) return false ; case V4DFmode : case V8SFmode : case V8SImode : case V16HImode : case V32QImode : case V4SFmode : case V4SImode : case V8HImode : case V4HImode : break ; case V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( INTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


<s> bool X86ATTAsmPrinter :: doInitialization ( Module & M ) { bool Result = AsmPrinter :: doInitialization ( M ) ; if ( TAI -> doesSupportDebugInformation ( ) ) { MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; DW -> BeginModule ( & M , MMI , O , this , TAI ) ; } if ( Subtarget -> isTargetDarwin ( ) ) Mang -> setUseQuotes ( true ) ; return Result ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void PPCOperand :: print ( raw_ostream & OS ) const { switch ( Kind ) { case Token : OS << "'" << getToken ( ) << "'" ; break ; case Immediate : case ContextImmediate : OS << getImm ( ) ; break ; case Expression : getExpr ( ) -> print ( OS ) ; break ; case TLSRegister : getTLSReg ( ) -> print ( OS ) ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
(
PseudoSourceValue
::
getFixedStack
(
FI
)
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tLDRspi
0


<s>
void
ARMELFStreamer
::
EmitRegSave
(
const
SmallVectorImpl
<
unsigned
>
&
RegList
,
bool
IsVector
)
{
unsigned
Count
=
0
;
uint32_t
Mask
=
0
;
const
MCRegisterInfo
*
MRI
=
getContext
(
)
.
getRegisterInfo
(
)
;
for
(
size_t
i
=
0
;
i
<
RegList
.
size
(
)
;
++
i
)
{
unsigned
Reg
=
MRI
->
getEncodingValue
(
RegList
[
i
]
)
;
assert
(
Reg
<
(
IsVector
32U
:
16U
)
&&
"Register out of range"
)
;
unsigned
Bit
=
(
1u
<<
Reg
)
;
if
(
(
Mask
&
Bit
)
==
0
)
{
Mask
|=
Bit
;
++
Count
;
}
}
SPOffset
-=
Count
*
(
IsVector
8
:
4
)
;
FlushPendingOffset
(
)
;
if
(
IsVector
)
UnwindOpAsm
.
EmitVFPRegSave
(
Mask
)
;
else
UnwindOpAsm
.
EmitRegSave
(
Mask
)
;
}
</s>

Emit unwind opcodes for .save directives .


<s> void TOYPassConfig :: addPreEmitPass ( ) { return ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool AArch64TargetLowering :: isLegalInterleavedAccessType ( VectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 && ElSize != 64 ) return false ; return VecSize == 64 || VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> void mips_split_msa_fill_d ( rtx dest , rtx src ) { gcc_assert ( ( GET_MODE ( dest ) == V2DImode && ( GET_MODE ( src ) == DImode || src == const0_rtx ) ) || ( GET_MODE ( dest ) == V2DFmode && GET_MODE ( src ) == DFmode ) ) ; rtx low , high ; if ( src == const0_rtx ) { low = src ; high = src ; } else { low = mips_subword ( src , false ) ; high = mips_subword ( src , true ) ; } rtx new_dest = simplify_gen_subreg ( V4SImode , dest , GET_MODE ( dest ) , 0 ) ; emit_insn ( gen_msa_fill_w ( new_dest , low ) ) ; emit_insn ( gen_msa_insert_w ( new_dest , high , new_dest , GEN_INT ( 1 << 1 ) ) ) ; emit_insn ( gen_msa_insert_w ( new_dest , high , new_dest , GEN_INT ( 1 << 3 ) ) ) ; } </s>


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MF . setHasWinCFI ( false ) ; const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> const PPCRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
Mono
:
if
(
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_Mono_DarwinPCS
;
else
if
(
Subtarget
->
isTargetWindows
(
)
)
report_fatal_error
(
"Unsupported calling convention."
)
;
else
return
CC_AArch64_Mono_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static bool aarch64_evpc_sve_tbl ( struct expand_vec_perm_d * d ) { unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = related_int_vector_mode ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; if ( d -> one_vector_p ) emit_unspec2 ( d -> target , UNSPEC_TBL , d -> op0 , force_reg ( sel_mode , sel ) ) ; else aarch64_expand_sve_vec_perm ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

Try to implement D using an SVE TBL instruction .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createARMIndirectThunks ( ) ) ; addPass ( createARMSLSHardeningPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s> static rtx mem_ref ( rtx x ) { if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) x = XEXP ( x , 0 ) ; if ( MEM_P ( x ) ) return x ; return NULL_RTX ; } </s>

Return the memory reference contained in X if any , zero otherwise .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" PPC


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveSparcCodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( ) ; } </s>


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>


<s> int mips_const_insns ( rtx x ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; enum mips_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case HIGH : if ( ! mips_symbolic_constant_p ( XEXP ( x , 0 ) , SYMBOL_CONTEXT_LEA , & symbol_type ) || ! mips_split_p [ symbol_type ] ) return 0 ; return TARGET_MIPS16 ? 4 : 1 ; case CONST_INT : if ( TARGET_MIPS16 ) return ( IN_RANGE ( INTVAL ( x ) , 0 , 255 ) ? 1 : SMALL_OPERAND_UNSIGNED ( INTVAL ( x ) ) ? 2 : IN_RANGE ( - INTVAL ( x ) , 0 , 255 ) ? 2 : SMALL_OPERAND_UNSIGNED ( - INTVAL ( x ) ) ? 3 : 0 ) ; return mips_build_integer ( codes , INTVAL ( x ) ) ; case CONST_VECTOR : if ( MSA_SUPPORTED_MODE_P ( GET_MODE ( x ) ) && mips_const_vector_same_int_p ( x , GET_MODE ( x ) , - 512 , 511 ) ) return 1 ; case CONST_DOUBLE : return ! TARGET_MIPS16 && x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( CONST_GP_P ( x ) ) return 1 ; if ( mips_symbolic_constant_p ( x , SYMBOL_CONTEXT_LEA , & symbol_type ) ) return mips_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = mips_const_insns ( x ) ; if ( n != 0 ) { if ( SMALL_INT ( offset ) ) return n + 1 ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + 1 + mips_build_integer ( codes , INTVAL ( offset ) ) ; } } return 0 ; case SYMBOL_REF : case LABEL_REF : return mips_symbol_insns ( mips_classify_symbol ( x , SYMBOL_CONTEXT_LEA ) , MAX_MACHINE_MODE ) ; default : return 0 ; } } </s>


<s> static bool rs6000_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || constant_pool_empty_p ( ) : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . For the RS/6000 , if frame pointer elimination is being done , we would like to convert ap into fp , not sp . We need r30 if -mminimal-toc was specified , and there are constant pool references .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( TID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: Latency ; return Sched :: RegPressure ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void sparc_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { if ( ! TARGET_FLAT ) gcc_assert ( sparc_leaf_function_p == crtl -> uses_only_leaf_regs ) ; sparc_output_scratch_registers ( file ) ; } </s>

This function generates the assembly code for function entry , which boils down to emitting the necessary .register directives .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isCyclone ( ) || VT . getStoreSize ( ) != 16 || Align <= 2 || VT == MVT :: v2i64 ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool Thumb1InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = 0 ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; ++ NumRegs ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned TeeRISCMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO ) const { if ( MO . isReg ( ) ) return getTeeRISCRegisterNumbering ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isExpr ( ) ) return 0 ; errs ( ) << MO ; llvm_unreachable ( 0 ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , 0 ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static void computeKnownBits ( SelectionDAG & DAG , SDValue Op , APInt & KnownZero , APInt & KnownOne ) { if ( Op . getOpcode ( ) == ARMISD :: BFI ) { computeKnownBits ( DAG , Op . getOperand ( 0 ) , KnownZero , KnownOne ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; KnownZero &= Mask ; KnownOne &= Mask ; return ; } if ( Op . getOpcode ( ) == ARMISD :: CMOV ) { APInt KZ2 ( KnownZero . getBitWidth ( ) , 0 ) ; APInt KO2 ( KnownOne . getBitWidth ( ) , 0 ) ; computeKnownBits ( DAG , Op . getOperand ( 1 ) , KnownZero , KnownOne ) ; computeKnownBits ( DAG , Op . getOperand ( 2 ) , KZ2 , KO2 ) ; KnownZero &= KZ2 ; KnownOne &= KO2 ; return ; } return DAG . computeKnownBits ( Op , KnownZero , KnownOne ) ; } </s>

Determine which bits of Op are known to be either zero or one and return them in Known .


<s> void FISCInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( FISC :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void mmix_conditional_register_usage ( void ) { int i ; if ( TARGET_ABI_GNU ) { static const int gnu_abi_reg_alloc_order [ ] = MMIX_GNU_ABI_REG_ALLOC_ORDER ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = gnu_abi_reg_alloc_order [ i ] ; for ( i = 15 ; i <= 30 ; i ++ ) call_used_regs [ i ] = 0 ; for ( i = MMIX_RESERVED_GNU_ARG_0_REGNUM ; i < MMIX_RESERVED_GNU_ARG_0_REGNUM + MMIX_MAX_ARGS_IN_REGS ; i ++ ) fixed_regs [ i ] = 0 ; } if ( ! TARGET_TOPLEVEL_SYMBOLS ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( reg_names [ i ] [ 0 ] == ':' ) reg_names [ i ] ++ ; } </s>


<s> bool Inserter :: runOnMachineFunction ( MachineFunction & F ) { Cpu0FunctionInfo * Cpu0FI = F . getInfo < Cpu0FunctionInfo > ( ) ; if ( ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) || ( ! Cpu0FI -> globalBaseRegFixed ( ) ) ) return false ; bool Changed = false ; int FI = Cpu0FI -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isLandingPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( Cpu0 :: LD ) , Cpu0 :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != Cpu0 :: JALR ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( Cpu0 :: LD ) , Cpu0 :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } } return Changed ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Byte/Word Instruction Fixup"
;
}
</s>


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> virtual bool isConditionalBranch ( const MCInst & Inst ) const { if ( Inst . getOpcode ( ) == ARM :: Bcc && Inst . getOperand ( 1 ) . getImm ( ) == ARMCC :: AL ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s>
const
char
*
LC3bAsmPrinter
::
getCurrentABIString
(
)
const
{
llvm_unreachable
(
"Unknown LC3b ABI"
)
;
;
}
</s>


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
->
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
->
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
(
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
||
N
->
getOpcode
(
)
==
X86ISD
::
CPS_CALL
)
&&
!
Subtarget
->
callRegIndirect
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
||
N
->
getOpcode
(
)
==
X86ISD
::
CPS_CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void ARMBaseRegisterInfo :: updateRegAllocHint ( Register Reg , Register NewReg , MachineFunction & MF ) const { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; std :: pair < Register , Register > Hint = MRI -> getRegAllocationHint ( Reg ) ; if ( ( Hint . first == ARMRI :: RegPairOdd || Hint . first == ARMRI :: RegPairEven ) && Hint . second . isVirtual ( ) ) { Register OtherReg = Hint . second ; Hint = MRI -> getRegAllocationHint ( OtherReg ) ; if ( Hint . second == Reg ) { MRI -> setRegAllocationHint ( OtherReg , Hint . first , NewReg ) ; if ( Register :: isVirtualRegister ( NewReg ) ) MRI -> setRegAllocationHint ( NewReg , Hint . first == ARMRI :: RegPairOdd ? ARMRI :: RegPairEven : ARMRI :: RegPairOdd , OtherReg ) ; } } } </s>

A callback to allow target a chance to update register allocation hints when a register is `` changed '' ( e.g .

ARM ARM ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd


<s> static rtx emit_memset ( rtx destmem , rtx destptr , rtx promoted_val , HOST_WIDE_INT size_to_move ) { rtx dst = destmem , adjust ; enum insn_code code ; machine_mode move_mode ; int piece_size , i ; move_mode = GET_MODE ( promoted_val ) ; if ( move_mode == VOIDmode ) move_mode = QImode ; if ( size_to_move < GET_MODE_SIZE ( move_mode ) ) { move_mode = mode_for_size ( size_to_move * BITS_PER_UNIT , MODE_INT , 0 ) ; promoted_val = gen_lowpart ( move_mode , promoted_val ) ; } piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; gcc_assert ( code != CODE_FOR_nothing && promoted_val != NULL_RTX ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , 0 ) ; gcc_assert ( size_to_move % piece_size == 0 ) ; adjust = GEN_INT ( piece_size ) ; for ( i = 0 ; i < size_to_move ; i += piece_size ) { if ( piece_size <= GET_MODE_SIZE ( word_mode ) ) { emit_insn ( gen_strset ( destptr , dst , promoted_val ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; continue ; } emit_insn ( GEN_FCN ( code ) ( dst , promoted_val ) ) ; emit_move_insn ( destptr , gen_rtx_PLUS ( Pmode , copy_rtx ( destptr ) , adjust ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; } return dst ; } </s>

This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM with value PROMOTED_VAL . SRC is passed by pointer to be updated on return . Return value is updated DST .


<s> static void arm_setup_incoming_varargs ( cumulative_args_t pcum_v , machine_mode mode , tree type , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int nregs ; cfun -> machine -> uses_anonymous_args = 1 ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { nregs = pcum -> aapcs_ncrn ; if ( ( nregs & 1 ) && arm_needs_doubleword_align ( mode , type ) ) nregs ++ ; } else nregs = pcum -> nregs ; if ( nregs < NUM_ARG_REGS ) * pretend_size = ( NUM_ARG_REGS - nregs ) * UNITS_PER_WORD ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> static void do_isel ( rtx dest , rtx cmp , rtx src_t , rtx src_f , rtx cr ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_isel_cc_di ( dest , cmp , src_t , src_f , cr ) ) ; else emit_insn ( gen_isel_cc_si ( dest , cmp , src_t , src_f , cr ) ) ; } </s>

Emit an isel of the proper mode for DEST . DEST is the isel destination register . SRC1 is the isel source if CR is true . SRC2 is the isel source if CR is false . CR is the condition for the isel .


<s> bool sh_in_recog_treg_set_expr ( void ) { return sh_recog_treg_set_expr_reent_count > 0 ; } </s>

Returns true when recog of a 'treg_set_expr ' is currently in progress . This can be used as a condition for insn/split patterns to allow certain T bit setting patters only to be matched as sub expressions of other patterns .


<s> unsigned DLXInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return 1 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"loadRegFromStackSlot didn't insert any code!"


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createX86MachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object :: mach :: CSX86_ALL ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool MipsAsmBackend :: isMicroMips ( const MCSymbol * Sym ) const { if ( const auto * ElfSym = dyn_cast < const MCSymbolELF > ( Sym ) ) { if ( ElfSym -> getOther ( ) & ELF :: STO_MIPS_MICROMIPS ) return true ; } return false ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


"  Copied r%d to a scalar register r%d for insn %d\n"

Convert all definitions of register REGNO and fix its uses . Scalar copies may be created in case register is used in not convertible insn .


<s> size_t Mips64GOT :: getEntrySize ( ) const { return Mips64GOTEntry :: EntrySize ; } </s>

getEntrySize - Return the size of each entry in the jump table .


<s> bool isImm ( ) const { return Kind == Immediate ; } </s>


<s> bool X86TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . classifyGlobalReference ( AM . BaseGV ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool aarch64_sve_bitmask_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && aarch64_bitmask_imm ( INTVAL ( elt ) , GET_MODE_INNER ( GET_MODE ( x ) ) ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE logical instruction such as AND .


<s> static bool store_insn_p ( rtx_insn * insn ) { if ( GET_CODE ( PATTERN ( insn ) ) != SET ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_STORE : case TYPE_FPSTORE : return true ; default : return false ; } } </s>


<s> bool canMergeStoresTo ( EVT MemVT ) const override { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> void MipsSETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue >> & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


"internal error: builtin function %qs already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> void MipsAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void sparc_trampoline_init ( rtx m_tramp , tree fndecl , rtx cxt ) { rtx fnaddr = force_reg ( Pmode , XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; cxt = force_reg ( Pmode , cxt ) ; if ( TARGET_ARCH64 ) sparc64_initialize_trampoline ( m_tramp , fnaddr , cxt ) ; else sparc32_initialize_trampoline ( m_tramp , fnaddr , cxt ) ; } </s>


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: GPRCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: G8RCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
unsigned
AArch64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : if ( OpSize == 32 ) { switch ( GenericOpc ) { case TargetOpcode :: G_SHL : return AArch64 :: LSLVWr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVWr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVWr ; default : return GenericOpc ; } } else if ( OpSize == 64 ) { switch ( GenericOpc ) { case TargetOpcode :: G_GEP : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SHL : return AArch64 :: LSLVXr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVXr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVXr ; default : return GenericOpc ; } } break ; case AArch64 :: FPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDSrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBSrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULSrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVSrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDDrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBDrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULDrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVDrr ; case TargetOpcode :: G_OR : return AArch64 :: ORRv8i8 ; default : return GenericOpc ; } } break ; } return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> enum reg_class secondary_reload_class ( enum reg_class class , enum machine_mode mode ATTRIBUTE_UNUSED , rtx in ) { int regno ; if ( TARGET_ELF || ( DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT ) ) { if ( class != BASE_REGS && ( GET_CODE ( in ) == SYMBOL_REF || GET_CODE ( in ) == HIGH || GET_CODE ( in ) == LABEL_REF || GET_CODE ( in ) == CONST ) ) return BASE_REGS ; } if ( GET_CODE ( in ) == REG ) { regno = REGNO ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } } else if ( GET_CODE ( in ) == SUBREG ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } else regno = - 1 ; if ( class == GENERAL_REGS || class == BASE_REGS || ( regno >= 0 && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - 1 || FP_REGNO_P ( regno ) ) && ( class == FLOAT_REGS || class == NON_SPECIAL_REGS ) ) return NO_REGS ; if ( ( regno == - 1 || ALTIVEC_REGNO_P ( regno ) ) && class == ALTIVEC_REGS ) return NO_REGS ; if ( ( class == CR_REGS || class == CR0_REGS ) && regno >= 0 && CR_REGNO_P ( regno ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the class of any secondary reload register that is needed to move IN into a register in class CLASS using mode MODE . Profiling has showed this routine and its descendants account for a significant amount of compile time ( ~7 % ) . So it has been optimized to reduce redundant computations and eliminate useless function calls . It might be worthwhile to try and make this a leaf function too .