<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
else
return
CSR_64_AllRegs_SaveList
;
}
else
{
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
else
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s>
const
MCExpr
*
getExpr
(
)
const
{
assert
(
Kind
==
Expression
&&
"Invalid access!"
)
;
return
Expr
.
Val
;
}
</s>

Implementation of the SCEVPredicate interface .


<s> bool X86InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV32rm : case X86 :: MOV64rm : case X86 :: LD_Fp64m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MOVAPSrm : case X86 :: MOVUPSrm : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: VMOVSSrm : case X86 :: VMOVSDrm : case X86 :: VMOVAPSrm : case X86 :: VMOVUPSrm : case X86 :: VMOVAPDrm : case X86 :: VMOVDQArm : case X86 :: VMOVAPSYrm : case X86 :: VMOVUPSYrm : case X86 :: VMOVAPDYrm : case X86 :: VMOVDQAYrm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : case X86 :: FsVMOVAPSrm : case X86 :: FsVMOVAPDrm : case X86 :: FsMOVAPSrm : case X86 :: FsMOVAPDrm : { if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 3 ) . getReg ( ) == 0 && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( BaseReg == 0 || BaseReg == X86 :: RIP ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( 4 ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case X86 :: LEA32r : case X86 :: LEA64r : { if ( MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 3 ) . getReg ( ) == 0 && ! MI -> getOperand ( 4 ) . isReg ( ) ) { if ( ! MI -> getOperand ( 1 ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( BaseReg == 0 ) return true ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } } return true ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return Subtarget . inMips16Mode ( ) ? 0 : & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
static
rtx
arm_expand_mve_builtin
(
int
fcode
,
tree
exp
,
rtx
target
)
{
if
(
fcode
>=
ARM_BUILTIN_MVE_BASE
&&
!
TARGET_HAVE_MVE
)
{
fatal_error
(
input_location
,
"You must enable MVE instructions"
" to use these intrinsics"
)
;
return
const0_rtx
;
}
arm_builtin_datum
*
d
=
&
mve_builtin_data
[
fcode
ARM_BUILTIN_MVE_PATTERN_START
]
;
return
arm_expand_builtin_1
(
fcode
,
exp
,
target
,
d
)
;
}
</s>

Expand an MVE builtin , i.e . those registered only if their respective target constraints are met . This check happens within arm_expand_builtin .

arm
"You must enable MVE instructions"
" to use these intrinsics"


<s> void MipsInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( Mips :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> static void compute_zdepwi_operands ( unsigned HOST_WIDE_INT imm , unsigned * op ) { int lsb , len ; for ( lsb = 0 ; lsb < 32 ; lsb ++ ) { if ( ( imm & 1 ) != 0 ) break ; imm >>= 1 ; } if ( ( imm & 0x10 ) == 0 ) len = ( lsb <= 28 ) ? 4 : 32 - lsb ; else { for ( len = 5 ; len < 32 - lsb ; len ++ ) { if ( ( imm & ( ( unsigned HOST_WIDE_INT ) 1 << len ) ) == 0 ) break ; } imm = ( imm & 0xf ) - 0x10 ; } op [ 0 ] = imm ; op [ 1 ] = 31 - lsb ; op [ 2 ] = len ; } </s>

Compute position ( in OP [ 1 ] ) and width ( in OP [ 2 ] ) useful for copying IMM to a register using the zdepi instructions . Store the immediate value to insert in OP [ 0 ] .


<s> static bool arm_output_ttype ( rtx x ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( GET_CODE ( x ) != CONST_INT ) fputs ( "(TARGET2)" , asm_out_file ) ; fputc ( '\n' , asm_out_file ) ; return TRUE ; } </s>

Output a reference from a function exception table to the type_info object X . The EABI specifies that the symbol should be relocated by an R_ARM_TARGET2 relocation .


"Only support MVT::i16 register passing"

"Can only pass arguments as either registers or via the stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static int thumb1_extra_regs_pushed ( arm_stack_offsets * offsets , bool for_prologue ) { HOST_WIDE_INT amount ; unsigned long live_regs_mask = offsets -> saved_regs_mask ; unsigned long l_mask = live_regs_mask & ( for_prologue ? 0x40ff : 0xff ) ; unsigned long high_regs_pushed = bit_count ( live_regs_mask & 0x0f00 ) ; int n_free , reg_base , size ; if ( ! for_prologue && frame_pointer_needed ) amount = offsets -> locals_base - offsets -> saved_regs ; else amount = offsets -> outgoing_args - offsets -> saved_regs ; if ( ! optimize_size && amount != 512 ) return 0 ; if ( high_regs_pushed != 0 ) return 0 ; if ( l_mask == 0 && ( for_prologue || TARGET_BACKTRACE || ( live_regs_mask & 1 << LR_REGNUM ) == 0 || TARGET_INTERWORK || crtl -> args . pretend_args_size != 0 ) ) return 0 ; if ( for_prologue && ( ( flag_pic && arm_pic_register != INVALID_REGNUM ) || ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) ) ) return 0 ; reg_base = 0 ; n_free = 0 ; if ( ! for_prologue ) { size = arm_size_return_regs ( ) ; reg_base = ARM_NUM_INTS ( size ) ; live_regs_mask >>= reg_base ; } while ( reg_base + n_free < 8 && ! ( live_regs_mask & 1 ) && ( for_prologue || call_used_or_fixed_reg_p ( reg_base + n_free ) ) ) { live_regs_mask >>= 1 ; n_free ++ ; } if ( n_free == 0 ) return 0 ; gcc_assert ( amount / 4 * 4 == amount ) ; if ( amount >= 512 && ( amount - n_free * 4 ) < 512 ) return ( amount - 508 ) / 4 ; if ( amount <= n_free * 4 ) return amount / 4 ; return 0 ; } </s>

Given the stack offsets and register mask in OFFSETS , decide how many additional registers to push instead of subtracting a constant from SP . For epilogues the principle is the same except we use pop . FOR_PROLOGUE indicates which we 're generating .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void load_got_register ( void ) { rtx insn ; if ( TARGET_VXWORKS_RTP ) { if ( ! got_register_rtx ) got_register_rtx = pic_offset_table_rtx ; insn = gen_vxworks_load_got ( ) ; } else { if ( ! got_register_rtx ) got_register_rtx = gen_rtx_REG ( Pmode , GLOBAL_OFFSET_TABLE_REGNUM ) ; if ( ! got_helper_rtx ) { char name [ 32 ] ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__sparc_get_pc_thunk.%s" , reg_names [ REGNO ( got_register_rtx ) ] + 1 ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LADDPC" , REGNO ( got_register_rtx ) ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; } const int orig_flag_pic = flag_pic ; flag_pic = 0 ; insn = gen_load_pcrel_sym ( Pmode , got_register_rtx , sparc_got ( ) , got_helper_rtx , GEN_INT ( GLOBAL_OFFSET_TABLE_REGNUM ) ) ; flag_pic = orig_flag_pic ; } emit_insn ( insn ) ; } </s>


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
TargetInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
break
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> bool MipsAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> bool FPGATTIImpl :: isSourceOfDivergence ( const Value * V ) { if ( const Argument * Arg = dyn_cast < Argument > ( V ) ) return ! IsKernelFunction ( * Arg -> getParent ( ) ) ; if ( const Instruction * I = dyn_cast < Instruction > ( V ) ) { if ( const LoadInst * LI = dyn_cast < LoadInst > ( I ) ) { unsigned AS = LI -> getPointerAddressSpace ( ) ; return AS == 0 ; } if ( const AllocaInst * AI = dyn_cast < AllocaInst > ( I ) ) { unsigned AS = AI -> getType ( ) -> getPointerAddressSpace ( ) ; return AS == 0 ; } if ( I -> isAtomic ( ) ) return true ; if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( readsLocalId ( II ) ) return true ; if ( readWorkgroupInvariant ( II ) ) return false ; if ( isPureFunction ( II ) ) return false ; } if ( isa < CallInst > ( I ) ) return true ; } return false ; } </s>

Returns whether V is a source of divergence .


"value of -mfixed-range must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != NULL ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"variables in %<__regio_symbol%> address space "

"pointers to %<__regio_symbol%> address space are prohibited"

Implement ` TARGET_INSERT_ATTRIBUTES ' . For PRU it 's used as a hook to provide better diagnostics for some invalid usages of the __regio_symbol address space . Any escapes of the following checks are supposed to be caught during the `` mov < mode > '' pattern expansion .


<s> void ARMPassConfig :: addPreEmitPass2 ( ) { addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> bool X86TargetLowering :: isZExtFree ( const Type * Ty1 , const Type * Ty2 ) const { return Ty1 -> isIntegerTy ( 32 ) && Ty2 -> isIntegerTy ( 64 ) && Subtarget -> is64Bit ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


"/* Automatically generated by the program '%s'\n"

"   from the files '%s' and '%s'.  */\n\n"

Write a comment at the top of FILE about how the code was generated .

"   from the files '%s' and '%s'.  */\n\n"


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { if ( usePreRAHazardRecognizer ( ) ) { const InstrItineraryData * II = & static_cast < const ARMSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , "pre-RA-sched" ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> void ARMBaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo * TRI ) const { if ( SubIdx && TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) { DestReg = TRI -> getSubReg ( DestReg , SubIdx ) ; SubIdx = 0 ; } unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; break ; } case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; ( * MIB ) . setMemRefs ( Orig -> memoperands_begin ( ) , Orig -> memoperands_end ( ) ) ; break ; } } MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> int expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; bool constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return 0 ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return 1 ; if ( TARGET_ALTIVEC && ( align >= 128 || TARGET_EFFICIENT_UNALIGNED_VSX ) ) clear_step = 16 ; else if ( TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) clear_step = 8 ; else clear_step = 4 ; if ( optimize_size && bytes > 3 * clear_step ) return 0 ; if ( ! optimize_size && bytes > 8 * clear_step ) return 0 ; for ( offset = 0 ; bytes > 0 ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= 16 && TARGET_ALTIVEC && ( align >= 128 || TARGET_EFFICIENT_UNALIGNED_VSX ) ) { clear_bytes = 16 ; mode = V4SImode ; } else if ( bytes >= 8 && TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 8 ; mode = DImode ; if ( offset == 0 && align < 64 ) { rtx addr ; addr = XEXP ( orig_dest , 0 ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , 1 ) ) & 3 ) != 0 ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= 4 && ( align >= 32 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 4 ; mode = SImode ; } else if ( bytes >= 2 && ( align >= 16 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 2 ; mode = HImode ; } else { clear_bytes = 1 ; mode = QImode ; } dest = adjust_address ( orig_dest , mode , offset ) ; emit_move_insn ( dest , CONST0_RTX ( mode ) ) ; } return 1 ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> int easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return 0 ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ? 8 : 0 ; else if ( mode == V2DImode ) { if ( ! CONST_INT_P ( CONST_VECTOR_ELT ( op , 0 ) ) || ! CONST_INT_P ( CONST_VECTOR_ELT ( op , 1 ) ) ) return 0 ; if ( zero_constant ( op , mode ) ) return 8 ; if ( INTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) == - 1 && INTVAL ( CONST_VECTOR_ELT ( op , 1 ) ) == - 1 ) return 8 ; return 0 ; } else if ( mode == V1TImode ) return 0 ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return 4 ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return 2 ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return 1 ; if ( vspltis_shifted ( op ) != 0 ) return GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; return 0 ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


<s> static rtx or1k_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { if ( arg . end_marker_p ( ) ) return NULL_RTX ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int nreg = CEIL ( GET_MODE_SIZE ( arg . mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= 2 ) ; if ( arg . named && * cum + nreg <= 6 ) return gen_rtx_REG ( arg . mode , * cum + 3 ) ; else return NULL_RTX ; } </s>

Worker for TARGET_FUNCTION_ARG . Return the next register to be used to hold a function argument or NULL_RTX if there 's no more space . Arugment CUM_V represents the current argument offset , zero for the first function argument . OpenRISC function arguments maybe be passed in registers r3 to r8 .


<s> static bool aarch64_pragma_target_parse ( tree args , tree pop_target ) { if ( args ) { if ( ! aarch64_process_target_attr ( args ) ) return false ; aarch64_override_options_internal ( & global_options ) ; } else { pop_target = pop_target ? pop_target : target_option_default_node ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( pop_target ) ) ; } target_option_current_node = build_target_option_node ( & global_options , & global_options_set ) ; aarch64_reset_previous_fndecl ( ) ; cpp_options * cpp_opts = cpp_get_options ( parse_in ) ; unsigned char saved_warn_unused_macros = cpp_opts -> warn_unused_macros ; cpp_opts -> warn_unused_macros = 0 ; cpp_force_token_locations ( parse_in , BUILTINS_LOCATION ) ; aarch64_update_cpp_builtins ( parse_in ) ; cpp_stop_forcing_token_locations ( parse_in ) ; cpp_opts -> warn_unused_macros = saved_warn_unused_macros ; if ( pop_target ) aarch64_save_restore_target_globals ( pop_target ) ; return true ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 speculative load hardening"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) { } </s>


<s> unsigned X86TargetLowering :: getJumpTableEncoding ( ) const { if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget . isPICStyleGOT ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static bool arm_memory_load_p ( rtx insn ) { rtx body , lhs , rhs ; ; if ( insn == NULL_RTX || GET_CODE ( insn ) != INSN ) return false ; body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET ) return false ; lhs = XEXP ( body , 0 ) ; rhs = XEXP ( body , 1 ) ; lhs = REG_OR_SUBREG_RTX ( lhs ) ; if ( GET_CODE ( lhs ) != REG || REGNO_REG_CLASS ( REGNO ( lhs ) ) != GENERAL_REGS ) return false ; return ( GET_CODE ( rhs ) == MEM || GET_CODE ( rhs ) == SYMBOL_REF || note_invalid_constants ( insn , - 1 , false ) ) ; } </s>

Returns TRUE if INSN is an `` LDR REG , ADDR '' instruction . Use by the Cirrus Maverick code which has to workaround a hardware bug triggered by such instructions .


<s> static bool rs6000_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || constant_pool_empty_p ( ) : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . For the RS/6000 , if frame pointer elimination is being done , we would like to convert ap into fp , not sp . We need r30 if -mminimal-toc was specified , and there are constant pool references .


<s> tree xstormy16_build_va_list ( ) { tree f_1 , f_2 , record , type_decl ; record = make_lang_type ( RECORD_TYPE ) ; type_decl = build_decl ( TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_1 = build_decl ( FIELD_DECL , get_identifier ( "base" ) , ptr_type_node ) ; f_2 = build_decl ( FIELD_DECL , get_identifier ( "count" ) , unsigned_type_node ) ; DECL_FIELD_CONTEXT ( f_1 ) = record ; DECL_FIELD_CONTEXT ( f_2 ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_1 ; TREE_CHAIN ( f_1 ) = f_2 ; layout_type ( record ) ; return record ; } </s>

Build the va_list type . For this chip , va_list is a record containing a counter and a pointer . The counter is of type 'int ' and indicates how many bytes have been used to date . The pointer indicates the stack position for arguments that have not been passed in registers . To keep the layout nice , the pointer is first in the structure .


<s> static int ia64_mode_to_int ( machine_mode mode ) { switch ( mode ) { case BImode : return 0 ; case QImode : return 1 ; case HImode : return 2 ; case SImode : return 3 ; case DImode : return 4 ; case SFmode : return 5 ; case DFmode : return 6 ; case XFmode : return 7 ; case TImode : return SPEC_MODE_INVALID ; default : return SPEC_MODE_INVALID ; } } </s>


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , IsPPC64 ( is64Bit ) , TargetTriple ( TT ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> unsigned int darwin_rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; if ( TYPE_PACKED ( type ) ) return align ; do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return align ; } </s>

Darwin increases record alignment to the natural alignment of the first field .


<s> bool PPCInstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned OpC = MI -> getOpcode ( ) ; switch ( OpC ) { default : return false ; case PPC :: B : case PPC :: BLR : case PPC :: BLR8 : case PPC :: BCTR : case PPC :: BCTR8 : case PPC :: BCTRL : case PPC :: BCTRL8 : return true ; } } </s>

Return true if the specified instruction can be predicated .

PowerPC PPC PPC::B PPC::BLR PPC::BLR8 PPC::BCTR PPC::BCTR8 PPC::BCTRL PPC::BCTRL8


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static bool aarch64_symbol_binds_local_p ( const_rtx x ) { return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

Return true if SYMBOL_REF X binds locally .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> const uint32_t * LEGRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool fp_one_operand ( rtx op ) { if ( GET_MODE ( op ) != SFmode ) return false ; return real_equal ( CONST_DOUBLE_REAL_VALUE ( op ) , & dconst1 ) ; } </s>

Nonzero if OP is a floating point value with value 1.0 .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


"parameter passing for argument of type "

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> void aarch64_expand_prologue ( void ) { aarch64_layout_frame ( ) ; HOST_WIDE_INT frame_size = cfun -> machine -> frame . frame_size ; HOST_WIDE_INT initial_adjust = cfun -> machine -> frame . initial_adjust ; HOST_WIDE_INT callee_adjust = cfun -> machine -> frame . callee_adjust ; HOST_WIDE_INT final_adjust = cfun -> machine -> frame . final_adjust ; HOST_WIDE_INT callee_offset = cfun -> machine -> frame . callee_offset ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; rtx_insn * insn ; if ( aarch64_return_address_signing_enabled ( ) ) { insn = emit_insn ( gen_pacisp ( ) ) ; add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( flag_stack_usage_info ) current_function_static_stack_size = frame_size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( frame_size > PROBE_INTERVAL && frame_size > STACK_CHECK_PROTECT ) aarch64_emit_probe_stack_range ( STACK_CHECK_PROTECT , frame_size - STACK_CHECK_PROTECT ) ; } else if ( frame_size > 0 ) aarch64_emit_probe_stack_range ( STACK_CHECK_PROTECT , frame_size ) ; } aarch64_sub_sp ( IP0_REGNUM , initial_adjust , true ) ; if ( callee_adjust != 0 ) aarch64_push_regs ( reg1 , reg2 , callee_adjust ) ; if ( frame_pointer_needed ) { if ( callee_adjust == 0 ) aarch64_save_callee_saves ( DImode , callee_offset , R29_REGNUM , R30_REGNUM , false ) ; insn = emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( callee_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_stack_tie ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } aarch64_save_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != 0 || frame_pointer_needed ) ; aarch64_save_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != 0 || frame_pointer_needed ) ; aarch64_sub_sp ( IP1_REGNUM , final_adjust , ! frame_pointer_needed ) ; } </s>

Generate the prologue instructions for entry into a function . Establish the stack frame by decreasing the stack pointer with a properly calculated size and , if necessary , create a frame record filled with the values of LR and previous frame pointer . The current FP is also set up if it is in use .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> void X86FrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = 0 ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? X86 :: MOV64ri : X86 :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; else MI -> setFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; continue ; } } MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( isSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


"\t.word\t0x00000000\t\t# <static chain value>\n"


<s> void function_expander :: add_output_operand ( insn_code icode ) { unsigned int opno = m_ops . length ( ) ; machine_mode mode = insn_data [ icode ] . operand [ opno ] . mode ; m_ops . safe_grow ( opno + 1 ) ; create_output_operand ( & m_ops . last ( ) , possible_target , mode ) ; } </s>

Create output and add it into M_OPS and increase OPNO .


<s> bool movd44_insn_p ( rtx_insn * insn ) { if ( get_attr_type ( insn ) == TYPE_ALU && ( INSN_CODE ( insn ) == CODE_FOR_move_di || INSN_CODE ( insn ) == CODE_FOR_move_df ) ) { rtx body = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( body ) == SET ) ; rtx src = SET_SRC ( body ) ; rtx dest = SET_DEST ( body ) ; if ( ( REG_P ( src ) || GET_CODE ( src ) == SUBREG ) && ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ) return true ; return false ; } return false ; } </s>


<s> void SystemZPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createSystemZPostRewritePass ( getSystemZTargetMachine ( ) ) ) ; addPass ( createSystemZExpandPseudoPass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; if ( Created ) Created -> push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> static bool ix86_dep_by_shift_count_body ( const_rtx set_body , const_rtx use_body ) { rtx set_dest ; rtx shift_rtx ; int i ; switch ( GET_CODE ( set_body ) ) { case SET : set_dest = SET_DEST ( set_body ) ; if ( ! set_dest || ! REG_P ( set_dest ) ) return false ; break ; case PARALLEL : for ( i = XVECLEN ( set_body , 0 ) - 1 ; i >= 0 ; i -- ) if ( ix86_dep_by_shift_count_body ( XVECEXP ( set_body , 0 , i ) , use_body ) ) return true ; default : return false ; break ; } switch ( GET_CODE ( use_body ) ) { case SET : shift_rtx = XEXP ( use_body , 1 ) ; break ; case PARALLEL : for ( i = XVECLEN ( use_body , 0 ) - 1 ; i >= 0 ; i -- ) if ( ix86_dep_by_shift_count_body ( set_body , XVECEXP ( use_body , 0 , i ) ) ) return true ; default : return false ; break ; } if ( shift_rtx && ( GET_CODE ( shift_rtx ) == ASHIFT || GET_CODE ( shift_rtx ) == LSHIFTRT || GET_CODE ( shift_rtx ) == ASHIFTRT || GET_CODE ( shift_rtx ) == ROTATE || GET_CODE ( shift_rtx ) == ROTATERT ) ) { rtx shift_count = XEXP ( shift_rtx , 1 ) ; if ( REG_P ( shift_count ) ) { if ( reload_completed && true_regnum ( set_dest ) == true_regnum ( shift_count ) ) return true ; else if ( REGNO ( set_dest ) == REGNO ( shift_count ) ) return true ; } } return false ; } </s>

Return true if destination reg of SET_BODY is shift count of USE_BODY .


<s> LLT AArch64TargetLowering :: getOptimalMemOpLLT ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttr ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , Align ( 16 ) ) ) return LLT :: fixed_vector ( 2 , 64 ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return LLT :: scalar ( 128 ) ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return LLT :: scalar ( 64 ) ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return LLT :: scalar ( 32 ) ; return LLT ( ) ; } </s>


<s> bool OR1KRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static reg_class_t ix86_preferred_output_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; mode = GET_MODE ( x ) ; if ( TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( mode ) ) return MAYBE_SSE_CLASS_P ( regclass ) ? ALL_SSE_REGS : NO_REGS ; if ( X87_FLOAT_MODE_P ( mode ) ) { if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ; else if ( regclass == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; else return FLOAT_CLASS_P ( regclass ) ? regclass : NO_REGS ; } return regclass ; } </s>

Discourage putting floating-point values in SSE registers unless SSE math is being used , and likewise for the 387 registers .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; PPCFunctionInfo * FI = MF -> getInfo < PPCFunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == PPC :: X2 || Reg == PPC :: R2 ) && MustSaveTOC ) continue ; if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool SystemZTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 20 > ( AM . BaseOffs ) ) return false ; return AM . Scale == 0 || AM . Scale == 1 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> unsigned stackAlignment ( ) const { return 8 ; } </s>

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function .


<s> bool m16_based_address_p ( rtx x , machine_mode mode , insn_operand_predicate_fn offset_predicate ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && M16_REG_P ( REGNO ( addr . reg ) ) && offset_predicate ( addr . offset , mode ) ) ; } </s>

Return true if X is legitimate for accessing values of mode MODE , if it is based on a MIPS16 register , and if the offset satisfies OFFSET_PREDICATE .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: LXVX : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"No ISEL instructions in this function\n"

runOnMachineFunction - Emit the function body .


<s> bool ix86_expand_int_addcc ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx flags ; rtx ( * insn ) ( rtx , rtx , rtx , rtx , rtx ) ; rtx compare_op ; rtx val = const0_rtx ; bool fpcmp = false ; machine_mode mode ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( operands [ 3 ] != const1_rtx && operands [ 3 ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , 0 ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ 0 ] ) ; if ( ( code == LTU ) == ( operands [ 3 ] == constm1_rtx ) ) { switch ( mode ) { case E_QImode : insn = gen_subqi3_carry ; break ; case E_HImode : insn = gen_subhi3_carry ; break ; case E_SImode : insn = gen_subsi3_carry ; break ; case E_DImode : insn = gen_subdi3_carry ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : insn = gen_addqi3_carry ; break ; case E_HImode : insn = gen_addhi3_carry ; break ; case E_SImode : insn = gen_addsi3_carry ; break ; case E_DImode : insn = gen_adddi3_carry ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( insn ( operands [ 0 ] , operands [ 2 ] , val , flags , compare_op ) ) ; return true ; } </s>

Expand conditional increment or decrement using adb/sbb instructions . The default case using setcc followed by the conditional move can be done by generic code .


<s> void MipsOutgoingValueHandler :: assignValueToAddress ( Register ValVReg , const CCValAssign & VA ) { MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> bool hasStandaloneRem ( EVT ) const override { return false ; } </s>

Return true if the target can handle a standalone remainder operation .


Write the extra assembler code needed to declare a function properly .


<s> bool runOnModule ( Module & M ) override { DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; bool Changed = false ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


"No space allowed between comma that separates operand entries"

ParseInstruction - Parse one assembly instruction .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


"Expected a reg or frame index operand."

Return true if this is a load/store that can be potentially paired/merged .


<s> static void union_uses ( swap_web_entry * insn_entry , rtx insn , df_ref def ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( use_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing uses reached from DEF . Detect whether DEF is live-out from the current function .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> bool X86TTIImpl :: isLegalMaskedExpandLoad ( Type * DataTy ) { if ( ! isa < VectorType > ( DataTy ) ) return false ; if ( ! ST -> hasAVX512 ( ) ) return false ; if ( DataTy -> getVectorNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getVectorElementType ( ) ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasVBMI2 ( ) ) ; } </s>

Return true if the target supports masked expand load .


<s> void aarch64_expand_epilogue ( bool for_sibcall ) { aarch64_layout_frame ( ) ; poly_int64 initial_adjust = cfun -> machine -> frame . initial_adjust ; HOST_WIDE_INT callee_adjust = cfun -> machine -> frame . callee_adjust ; poly_int64 final_adjust = cfun -> machine -> frame . final_adjust ; poly_int64 callee_offset = cfun -> machine -> frame . callee_offset ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; rtx cfi_ops = NULL ; rtx_insn * insn ; bool can_inherit_p = ( initial_adjust . is_constant ( ) && final_adjust . is_constant ( ) && ! flag_stack_clash_protection ) ; bool need_barrier_p = maybe_ne ( get_frame_size ( ) + cfun -> machine -> frame . saved_varargs_size , 0 ) ; if ( maybe_gt ( final_adjust , crtl -> outgoing_args_size ) || cfun -> calls_alloca || crtl -> calls_eh_return ) { emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; need_barrier_p = false ; } rtx ip0_rtx = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; rtx ip1_rtx = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; if ( frame_pointer_needed && ( maybe_ne ( final_adjust , 0 ) || cfun -> calls_alloca ) ) aarch64_add_offset ( Pmode , stack_pointer_rtx , hard_frame_pointer_rtx , - callee_offset , ip1_rtx , ip0_rtx , callee_adjust == 0 ) ; else aarch64_add_sp ( ip1_rtx , ip0_rtx , final_adjust , ! can_inherit_p || df_regs_ever_live_p ( IP1_REGNUM ) ) ; aarch64_restore_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != 0 , & cfi_ops ) ; aarch64_restore_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != 0 , & cfi_ops ) ; if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != 0 ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != 0 || maybe_gt ( initial_adjust , 65536 ) ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; cfi_ops = NULL ; } aarch64_add_sp ( ip0_rtx , ip1_rtx , initial_adjust , ! can_inherit_p || df_regs_ever_live_p ( IP0_REGNUM ) ) ; if ( cfi_ops ) { insn = get_last_insn ( ) ; cfi_ops = alloc_reg_note ( REG_CFA_DEF_CFA , stack_pointer_rtx , cfi_ops ) ; REG_NOTES ( insn ) = cfi_ops ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( aarch64_return_address_signing_enabled ( ) && ( for_sibcall || ! TARGET_ARMV8_3 || crtl -> calls_eh_return ) ) { insn = emit_insn ( gen_autisp ( ) ) ; add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( crtl -> calls_eh_return ) { emit_insn ( gen_add2_insn ( stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; } emit_use ( gen_rtx_REG ( DImode , LR_REGNUM ) ) ; if ( ! for_sibcall ) emit_jump_insn ( ret_rtx ) ; } </s>

Generate the epilogue instructions for returning from a function .


" was Pass-through, is now Dirty-out.\n"


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN


<s> static void mips_end_function_definition ( const char * name ) { if ( ! flag_inhibit_size_directive ) { fputs ( "\t.end\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( "\n" , asm_out_file ) ; } } </s>

End a function definition started by mips_start_function_definition .


<s> void PPCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { return MBB . erase ( MI ) ; } </s>


<s> void Initialize ( MCContext & Ctx , const TargetMachine & TM ) override { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createHardwareLoopsPass ( ) ) ; return false ; } </s>


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + 1 ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ 0 ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( 2 , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = 1 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_hard_reg_clobber ( V4SImode , i ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( 1 , reg ) , 27 ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = 0 ; i < nclobs ; ++ i ) XVECEXP ( insn , 0 , i ) = clobs [ i ] ; return insn ; } </s>

Returns an insn that has a vrsave set operation with the appropriate CLOBBERs .


<s> virtual const LC3bRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool X86FixupSetCCPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 4 > ToErase ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( ! isSetCCr ( MI . getOpcode ( ) ) ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( 0 ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == X86 :: MOVZX32rr8 ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ; if ( ! FlagsDefMI ) continue ; if ( impUsesFlags ( FlagsDefMI ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? & X86 :: GR32RegClass : & X86 :: GR32_ABCDRegClass ; unsigned ZeroReg = MRI -> createVirtualRegister ( RC ) ; unsigned InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( X86 :: MOV32r0 ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( X86 :: INSERT_SUBREG ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) ) . addImm ( X86 :: sub_8bit ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( 0 ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> bool usesFunctionDescriptors ( ) const { return isAIXABI ( ) || ( is64BitELFABI ( ) && ! isELFv2ABI ( ) ) ; } </s>


<s> uint64_t AArch64InstrInfo :: getElementSizeForOpcode ( unsigned Opc ) const { return get ( Opc ) . TSFlags & AArch64 :: ElementSizeMask ; } </s>

Returns the vector element size ( B , H , S or D ) of an SVE opcode .


<s>
const
char
*
nds32_output_stack_pop
(
rtx
par_rtx
ATTRIBUTE_UNUSED
)
{
char
pattern
[
100
]
;
rtx
operands
[
3
]
;
int
rb_callee_saved
=
cfun
->
machine
->
callee_saved_first_gpr_regno
;
int
re_callee_saved
=
cfun
->
machine
->
callee_saved_last_gpr_regno
;
if
(
TARGET_V3PUSH
&&
!
nds32_isr_function_p
(
current_function_decl
)
&&
(
cfun
->
machine
->
va_args_size
==
0
)
)
{
int
sp_adjust
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
sp_adjust
=
cfun
->
machine
->
local_size
+
cfun
->
machine
->
out_args_size
+
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
;
if
(
satisfies_constraint_Iu08
(
GEN_INT
(
sp_adjust
)
)
&&
NDS32_DOUBLE_WORD_ALIGN_P
(
sp_adjust
)
&&
!
cfun
->
calls_alloca
)
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
else
operands
[
1
]
=
GEN_INT
(
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop25\t%%0, %%1"
)
;
}
else
{
int
pop_en4_only_p
=
0
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
rb_callee_saved
)
;
operands
[
1
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
if
(
!
cfun
->
machine
->
fp_size
&&
!
cfun
->
machine
->
gp_size
&&
!
cfun
->
machine
->
lp_size
&&
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
{
return
""
;
}
else
{
if
(
REGNO
(
operands
[
0
]
)
==
SP_REGNUM
&&
REGNO
(
operands
[
1
]
)
==
SP_REGNUM
)
pop_en4_only_p
=
1
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop.s\t%s{%s%s%s }"
,
pop_en4_only_p
""
:
"%0, %1, "
,
cfun
->
machine
->
fp_size
" $fp"
:
""
,
cfun
->
machine
->
gp_size
" $gp"
:
""
,
cfun
->
machine
->
lp_size
" $lp"
:
""
)
;
}
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Function to output stack pop operation . We need to deal with normal stack pop multiple or stack v3pop .


<s> void ARMPassConfig :: addPreEmitPass2 ( ) { addPass ( createARMFixCortexA57AES1742098Pass ( ) ) ; addPass ( createARMBranchTargetsPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> static void aarch64_init_fp16_types ( void ) { aarch64_fp16_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( aarch64_fp16_type_node ) = 16 ; layout_type ( aarch64_fp16_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( aarch64_fp16_type_node , "__fp16" ) ; aarch64_fp16_ptr_type_node = build_pointer_type ( aarch64_fp16_type_node ) ; } </s>

Initialize the backend types that support the user-visible __fp16 type , also initialize a pointer to that type , to be used when forming HFAs .


<s> void relaxInstruction ( const MCInst & , const MCSubtargetInfo & , MCInst & ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
StringRef
CSKYMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_CSKY_None
:
case
VK_CSKY_ADDR
:
return
""
;
case
VK_CSKY_ADDR_HI16
:
return
"@HI16"
;
case
VK_CSKY_ADDR_LO16
:
return
"@LO16"
;
case
VK_CSKY_GOT_IMM18_BY4
:
case
VK_CSKY_GOT
:
return
"@GOT"
;
case
VK_CSKY_GOTPC
:
return
"@GOTPC"
;
case
VK_CSKY_GOTOFF
:
return
"@GOTOFF"
;
case
VK_CSKY_PLT_IMM18_BY4
:
case
VK_CSKY_PLT
:
return
"@PLT"
;
case
VK_CSKY_TLSLE
:
return
"@TPOFF"
;
case
VK_CSKY_TLSIE
:
return
"@GOTTPOFF"
;
case
VK_CSKY_TLSGD
:
return
"@TLSGD32"
;
case
VK_CSKY_TLSLDO
:
return
"@TLSLDO32"
;
case
VK_CSKY_TLSLDM
:
return
"@TLSLDM32"
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s>
static
void
emit_insn_group_barriers
(
FILE
*
dump
)
{
rtx_insn
*
insn
;
rtx_insn
*
last_label
=
0
;
int
insns_since_last_label
=
0
;
init_insn_group_barriers
(
)
;
for
(
insn
=
get_insns
(
)
;
insn
;
insn
=
NEXT_INSN
(
insn
)
)
{
if
(
LABEL_P
(
insn
)
)
{
if
(
insns_since_last_label
)
last_label
=
insn
;
insns_since_last_label
=
0
;
}
else
if
(
NOTE_P
(
insn
)
&&
NOTE_KIND
(
insn
)
==
NOTE_INSN_BASIC_BLOCK
)
{
if
(
insns_since_last_label
)
last_label
=
insn
;
insns_since_last_label
=
0
;
}
else
if
(
NONJUMP_INSN_P
(
insn
)
&&
GET_CODE
(
PATTERN
(
insn
)
)
==
UNSPEC_VOLATILE
&&
XINT
(
PATTERN
(
insn
)
,
1
)
==
UNSPECV_INSN_GROUP_BARRIER
)
{
init_insn_group_barriers
(
)
;
last_label
=
0
;
}
else
if
(
NONDEBUG_INSN_P
(
insn
)
)
{
insns_since_last_label
=
1
;
if
(
group_barrier_needed
(
insn
)
)
{
if
(
last_label
)
{
if
(
dump
)
fprintf
(
dump
,
"Emitting stop before label %d\n"
,
INSN_UID
(
last_label
)
)
;
emit_insn_before
(
gen_insn_group_barrier
(
GEN_INT
(
3
)
)
,
last_label
)
;
insn
=
last_label
;
init_insn_group_barriers
(
)
;
last_label
=
0
;
}
}
}
}
}
</s>

INSNS is an chain of instructions . Scan the chain , and insert stop bits as necessary to eliminate dependendencies . This function assumes that a final instruction scheduling pass has been run which has already inserted most of the necessary stop bits . This function only inserts new ones at basic block boundaries , since these are invisible to the scheduler .


<s> virtual const MandarinRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s>
SDNode
*
SystemZDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
0
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
SDNode
*
ResNode
=
0
;
switch
(
Opcode
)
{
case
ISD
::
OR
:
case
ISD
::
XOR
:
if
(
Node
->
getValueType
(
0
)
==
MVT
::
i64
)
if
(
ConstantSDNode
*
Op1
=
dyn_cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
1
)
)
)
{
uint64_t
Val
=
Op1
->
getZExtValue
(
)
;
if
(
!
SystemZ
::
isImmLF
(
Val
)
&&
!
SystemZ
::
isImmHF
(
Val
)
)
Node
=
splitLargeImmediate
(
Opcode
,
Node
,
Node
->
getOperand
(
0
)
,
Val
uint32_t
(
Val
)
,
uint32_t
(
Val
)
)
;
}
break
;
case
ISD
::
AND
:
ResNode
=
tryRISBGForAND
(
Node
)
;
break
;
case
ISD
::
Constant
:
if
(
Node
->
getValueType
(
0
)
==
MVT
::
i64
)
{
uint64_t
Val
=
cast
<
ConstantSDNode
>
(
Node
)
->
getZExtValue
(
)
;
if
(
!
SystemZ
::
isImmLF
(
Val
)
&&
!
SystemZ
::
isImmHF
(
Val
)
&&
!
isInt
<
32
>
(
Val
)
)
Node
=
splitLargeImmediate
(
ISD
::
OR
,
Node
,
SDValue
(
)
,
Val
uint32_t
(
Val
)
,
uint32_t
(
Val
)
)
;
}
break
;
case
ISD
::
ATOMIC_LOAD_SUB
:
if
(
ConstantSDNode
*
Op2
=
dyn_cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
2
)
)
)
{
uint64_t
Value
=
Op2
->
getZExtValue
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
if
(
VT
==
MVT
::
i32
||
isInt
<
32
>
(
Value
)
)
{
SDValue
Ops
[
]
=
{
Node
->
getOperand
(
0
)
,
Node
->
getOperand
(
1
)
,
CurDAG
->
getConstant
(
int32_t
(
Value
)
,
VT
)
}
;
Node
=
CurDAG
->
MorphNodeTo
(
Node
,
ISD
::
ATOMIC_LOAD_ADD
,
Node
->
getVTList
(
)
,
Ops
,
array_lengthof
(
Ops
)
)
;
}
}
break
;
}
if
(
!
ResNode
)
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
;
if
(
ResNode
==
||
ResNode
==
Node
)
Node
->
dump
(
CurDAG
)
;
else
ResNode
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
;
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> int mmix_use_simple_return ( void ) { int regno ; int stack_space_to_allocate = ( current_function_outgoing_args_size + current_function_pretend_args_size + get_frame_size ( ) + 7 ) & ~ 7 ; if ( ! TARGET_USE_RETURN_INSN || ! reload_completed ) return 0 ; for ( regno = 255 ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return 0 ; if ( frame_pointer_needed ) stack_space_to_allocate += 8 ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_allocate += 16 ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_allocate += 8 ; return stack_space_to_allocate == 0 ; } </s>

Nonzero when the function epilogue is simple enough that a single `` POP % d,0 '' should be used even within the function .


<s> rtx mmix_dynamic_chain_address ( rtx frame ) { return plus_constant ( frame , - 8 ) ; } </s>


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) LoopSize += TII -> GetInstSizeInBytes ( J ) ; if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> bool SparcFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static unsigned rs6000_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; if ( ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec ) || ( where == vect_body && kind == vector_stmt ) ) rs6000_vect_nonmem = true ; } return retval ; } </s>


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int XMMFrameSlotOrigin ; int SEHFrameOffset = X86FI -> getCalleeSavedXMMFrameInfo ( XMMFrameSlotOrigin ) + MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is64Bit ( ) ) { if ( X86 :: VR128RegClass . contains ( Reg ) ) { int Offset = ( CSI [ i ] . getFrameIdx ( ) - XMMFrameSlotOrigin - 1 ) * 16 ; addRegOffset ( BuildMI ( MBB , MI , DL , TII . get ( getXMMAlignedLoadStoreOp ( true ) ) , Reg ) , X86 :: RSP , true , SEHFrameOffset + Offset ) ; } } else { if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void MipsAsmPrinter :: emitInlineAsmStart ( ) const { MipsTargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetPush ( ) ; TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; OutStreamer . AddBlankLine ( ) ; } </s>

Let the target do anything it needs to do before emitting inlineasm .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { if ( ! ( Subtarget -> hasFMA ( ) || Subtarget -> hasFMA4 ( ) ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDR : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: t2LDRi12 : case ARM :: tRestore : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDRD : case ARM :: VLDRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void nds32_cpu_cpp_builtins ( struct cpp_reader * pfile ) { builtin_define ( "__nds32__" ) ; builtin_define ( "__NDS32__" ) ; if ( TARGET_HARD_FLOAT ) builtin_define ( "__NDS32_ABI_2FP_PLUS__" ) ; else builtin_define ( "__NDS32_ABI_2__" ) ; if ( TARGET_ISA_V2 ) builtin_define ( "__NDS32_ISA_V2__" ) ; if ( TARGET_ISA_V3 ) builtin_define ( "__NDS32_ISA_V3__" ) ; if ( TARGET_ISA_V3M ) builtin_define ( "__NDS32_ISA_V3M__" ) ; if ( TARGET_FPU_SINGLE ) builtin_define ( "__NDS32_EXT_FPU_SP__" ) ; if ( TARGET_FPU_DOUBLE ) builtin_define ( "__NDS32_EXT_FPU_DP__" ) ; if ( TARGET_EXT_FPU_FMA ) builtin_define ( "__NDS32_EXT_FPU_FMA__" ) ; if ( NDS32_EXT_FPU_DOT_E ) builtin_define ( "__NDS32_EXT_FPU_DOT_E__" ) ; if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { switch ( nds32_fp_regnum ) { case 0 : case 4 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_0__" ) ; break ; case 1 : case 5 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_1__" ) ; break ; case 2 : case 6 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_2__" ) ; break ; case 3 : case 7 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_3__" ) ; break ; default : abort ( ) ; } } if ( TARGET_BIG_ENDIAN ) builtin_define ( "__NDS32_EB__" ) ; else builtin_define ( "__NDS32_EL__" ) ; if ( TARGET_REDUCED_REGS ) builtin_define ( "__NDS32_REDUCED_REGS__" ) ; if ( TARGET_CMOV ) builtin_define ( "__NDS32_CMOV__" ) ; if ( TARGET_EXT_PERF ) builtin_define ( "__NDS32_EXT_PERF__" ) ; if ( TARGET_EXT_PERF2 ) builtin_define ( "__NDS32_EXT_PERF2__" ) ; if ( TARGET_EXT_STRING ) builtin_define ( "__NDS32_EXT_STRING__" ) ; if ( TARGET_16_BIT ) builtin_define ( "__NDS32_16_BIT__" ) ; if ( TARGET_GP_DIRECT ) builtin_define ( "__NDS32_GP_DIRECT__" ) ; if ( TARGET_VH ) builtin_define ( "__NDS32_VH__" ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( "__big_endian__" ) ; builtin_assert ( "cpu=nds32" ) ; builtin_assert ( "machine=nds32" ) ; if ( TARGET_HARD_FLOAT ) builtin_define ( "__NDS32_ABI_2FP_PLUS" ) ; else builtin_define ( "__NDS32_ABI_2" ) ; } </s>


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( IsConstantInSmallSection ( C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> void MipsELFStreamer :: createPendingLabelRelocs ( ) { MipsTargetELFStreamer * ELFTargetStreamer = static_cast < MipsTargetELFStreamer * > ( getTargetStreamer ( ) ) ; if ( ELFTargetStreamer -> isMicroMipsEnabled ( ) ) { for ( auto * L : Labels ) { auto * Label = cast < MCSymbolELF > ( L ) ; getAssembler ( ) . registerSymbol ( * Label ) ; Label -> setOther ( ELF :: STO_MIPS_MICROMIPS ) ; } } Labels . clear ( ) ; } </s>

Mark labels as microMIPS , if necessary for the subtarget .


<s> const MCPhysReg * SHUXIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList ; } </s>


<s> bool vax_acceptable_pic_operand_p ( rtx x ATTRIBUTE_UNUSED , bool local_p ATTRIBUTE_UNUSED , bool symbol_p ATTRIBUTE_UNUSED ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { x = XEXP ( XEXP ( x , 0 ) , 0 ) ; local_p = true ; } switch ( GET_CODE ( x ) ) { case SYMBOL_REF : return symbol_p && ! ( local_p && ! SYMBOL_REF_LOCAL_P ( x ) ) ; case LABEL_REF : return symbol_p && ! ( local_p && LABEL_REF_NONLOCAL_P ( x ) ) ; default : break ; } return true ; } </s>

With ELF we do not support GOT entries for external ` symbol+offset ' references , so do not accept external symbol references if an offset is to be added . Do not accept external symbol references at all if LOCAL_P is set . This is for cases where making a reference indirect would make it invalid . Do not accept any kind of symbols if SYMBOL_P is clear . This is for situations where the a reference is used as an immediate value for operations other than address loads ( MOVA/PUSHA ) , as those operations do not support PC-relative immediates .


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( ( format == 0 && dwarf_debuginfo_p ( ) ) || format == 1 ) { if ( regno <= 31 ) return regno ; if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + 32 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 1124 ; if ( regno == LR_REGNO ) return 108 ; if ( regno == CTR_REGNO ) return 109 ; if ( regno == CA_REGNO ) return 101 ; if ( format == 1 && regno == CR2_REGNO ) return 64 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 86 ; if ( regno == VRSAVE_REGNO ) return 356 ; if ( regno == VSCR_REGNO ) return 67 ; if ( regno == FRAME_POINTER_REGNUM ) return 111 ; if ( regno == ARG_POINTER_REGNUM ) return 67 ; if ( regno == 64 ) return 100 ; gcc_unreachable ( ) ; } if ( regno <= 31 ) return regno ; if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + 32 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 77 ; if ( regno == LR_REGNO ) return 65 ; if ( regno == CTR_REGNO ) return 66 ; if ( regno == CA_REGNO ) return 76 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 68 ; if ( regno == VRSAVE_REGNO ) return 109 ; if ( regno == VSCR_REGNO ) return 110 ; if ( regno == FRAME_POINTER_REGNUM ) return 111 ; if ( regno == ARG_POINTER_REGNUM ) return 67 ; if ( regno == 64 ) return 64 ; gcc_unreachable ( ) ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
const
Function
&
F
=
MF
->
getFunction
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
CallingConv
::
ID
CC
=
F
.
getCallingConv
(
)
;
if
(
MF
->
getFunction
(
)
.
hasFnAttribute
(
"no_caller_saved_registers"
)
)
CC
=
CallingConv
::
X86_INTR
;
switch
(
CC
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_64_AllRegs_SaveList
;
return
CSR_64_AllRegs_NoSSE_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
bool
IsSwiftCC
=
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
F
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
;
if
(
IsSwiftCC
)
return
IsWin64
CSR_Win64_SwiftError_SaveList
:
CSR_64_SwiftError_SaveList
;
if
(
IsWin64
)
return
HasSSE
CSR_Win64_SaveList
:
CSR_Win64_NoSSE_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
return
CallsEHReturn
CSR_32EHRet_SaveList
:
CSR_32_SaveList
;
}
</s>


<s> static int sh_address_cost ( rtx X ) { return ( GET_CODE ( X ) == PLUS && ! CONSTANT_P ( XEXP ( X , 1 ) ) && ! TARGET_SHMEDIA ? 1 : 0 ) ; } </s>

Compute the cost of an address . For the SH , all valid addresses are the same cost . Use a slightly higher cost for reg + reg addressing , since it increases pressure on r0 .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool ix86_can_use_return_insn_p ( void ) { if ( ix86_function_ms_hook_prologue ( current_function_decl ) ) return false ; if ( ix86_function_naked ( current_function_decl ) ) return false ; if ( ! reload_completed || frame_pointer_needed || cfun -> machine -> func_type != TYPE_NORMAL ) return 0 ; if ( crtl -> args . pops_args && crtl -> args . size >= 32768 ) return 0 ; struct ix86_frame & frame = cfun -> machine -> frame ; return ( frame . stack_pointer_offset == UNITS_PER_WORD && ( frame . nregs + frame . nsseregs ) == 0 ) ; } </s>

Return 1 if it is appropriate to emit ` ret ' instructions in the body of a function . Do this only if the epilogue is simple , needing a couple of insns . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then . Return 0 if there is no frame marker to de-allocate .


<s> static bool aarch64_hard_regno_mode_ok ( unsigned regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return regno == CC_REGNUM ; if ( regno == VG_REGNUM ) return mode == DImode ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return PR_REGNUM_P ( regno ) ; if ( PR_REGNUM_P ( regno ) ) return 0 ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) ) { if ( known_le ( GET_MODE_SIZE ( mode ) , 8 ) ) return true ; else if ( known_le ( GET_MODE_SIZE ( mode ) , 16 ) ) return ( regno & 1 ) == 0 ; } else if ( FP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_STRUCT ) return end_hard_regno ( mode , regno ) - 1 <= V31_REGNUM ; else return ! VECTOR_MODE_P ( mode ) || vec_flags != 0 ; } return false ; } </s>


<s> static void mips_expand_vi_constant ( machine_mode vmode , unsigned nelt , rtx target , rtx vals ) { rtvec vec = shallow_copy_rtvec ( XVEC ( vals , 0 ) ) ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) { if ( ! mips_constant_elt_p ( RTVEC_ELT ( vec , i ) ) ) RTVEC_ELT ( vec , i ) = const0_rtx ; } emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , vec ) ) ; } </s>

A subroutine of mips_expand_vec_init , replacing all of the non-constant elements of VALS with zeros , copy the constant vector to TARGET .


<s> void F2003fAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { F2003fMCInstLower MCInstLowering ( OutContext , * this ) ; MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; MCInstLowering . Lower ( & * I , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( F . hasAddressTaken ( ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> static unsigned long arm_compute_save_core_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; unsigned int reg ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % 2 ) != 0 ) { for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == 0 ) { reg = thumb_find_work_register ( 1 << 4 ) ; if ( ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; } return save_reg_mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function . This is used by arm_compute_frame_layout , which may add extra registers .