<s> int mips_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { int size ; HARD_REG_SET left ; size = 0x8000 ; COPY_HARD_REG_SET ( left , reg_class_contents [ ( int ) rclass ] ) ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) ST_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( ST_REG_FIRST , mode ) ) size = MIN ( size , 4 ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) ST_REGS ] ) ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( FP_REG_FIRST , mode ) ) size = MIN ( size , UNITS_PER_FPREG ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) FP_REGS ] ) ; } if ( ! hard_reg_set_empty_p ( left ) ) size = MIN ( size , UNITS_PER_WORD ) ; return ( GET_MODE_SIZE ( mode ) + size - 1 ) / size ; } </s>

Implement CLASS_MAX_NREGS . Usually all registers are word-sized . The only supported exception is -mgp64 -msingle-float , which has 64-bit words but 32-bit float registers . A word-based calculation is correct even in that case , since -msingle-float disallows multi-FPR values . The FP status registers are an exception to this rule . They are always 4 bytes wide as they only hold condition code modes , and CCmode is always considered to be 4 bytes wide .


<s> bool MipsFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> bool Cpu0SETargetLowering :: isEligibleForTailCallOptimization ( const Cpu0CC & Cpu0CCInfo , unsigned NextStackOffset , const Cpu0MachineFunctionInfo & FI ) const { if ( ! EnableCpu0TailCalls ) return false ; if ( Cpu0CCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s> Register PPCTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return Subtarget . isPPC64 ( ) ? PPC :: X3 : PPC :: R3 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const PPCSubtarget & ST = C -> MF -> getSubtarget < PPCSubtarget > ( ) ; if ( ST . usePPCPostRASchedStrategy ( ) ) return createPPCPostMachineScheduler ( C ) ; return nullptr ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> unsigned OR1KRegisterInfo :: getRARegister ( ) const { return OR1K :: R9 ; } </s>

This method should return the register where the return address can be found .


<s> bool arm_const_double_by_parts ( rtx val ) { enum machine_mode mode = GET_MODE ( val ) ; rtx part ; if ( optimize_size || arm_ld_sched ) return true ; if ( mode == VOIDmode ) mode = DImode ; part = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; return false ; } </s>

Return true if it is worthwhile to split a 64-bit constant into two 32-bit operations . This is the case if optimizing for size , or if we have load delay slots , or if one 32-bit part can be done with a single data operation .


<s> void ix86_expand_copysign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , op1 , mask , nmask ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; if ( CONST_DOUBLE_P ( op0 ) ) { rtx ( * copysign_insn ) ( rtx , rtx , rtx , rtx ) ; if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op0 ) ) ) op0 = simplify_unary_operation ( ABS , mode , op0 , mode ) ; if ( mode == SFmode || mode == DFmode ) { if ( op0 == CONST0_RTX ( mode ) ) op0 = CONST0_RTX ( vmode ) ; else { rtx v = ix86_build_const_vector ( vmode , false , op0 ) ; op0 = force_reg ( vmode , v ) ; } } else if ( op0 != CONST0_RTX ( mode ) ) op0 = force_reg ( mode , op0 ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; if ( mode == SFmode ) copysign_insn = gen_copysignsf3_const ; else if ( mode == DFmode ) copysign_insn = gen_copysigndf3_const ; else copysign_insn = gen_copysigntf3_const ; emit_insn ( copysign_insn ( dest , op0 , op1 , mask ) ) ; } else { rtx ( * copysign_insn ) ( rtx , rtx , rtx , rtx , rtx , rtx ) ; nmask = ix86_build_signbit_mask ( vmode , 0 , 1 ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; if ( mode == SFmode ) copysign_insn = gen_copysignsf3_var ; else if ( mode == DFmode ) copysign_insn = gen_copysigndf3_var ; else copysign_insn = gen_copysigntf3_var ; emit_insn ( copysign_insn ( dest , NULL_RTX , op0 , op1 , nmask , mask ) ) ; } } </s>

Expand a copysign operation . Special case operand 0 being a constant .


<s> bool aarch64_mov128_immediate ( rtx imm ) { if ( CONST_INT_P ( imm ) ) return true ; gcc_assert ( CONST_WIDE_INT_NUNITS ( imm ) == 2 ) ; rtx lo = GEN_INT ( CONST_WIDE_INT_ELT ( imm , 0 ) ) ; rtx hi = GEN_INT ( CONST_WIDE_INT_ELT ( imm , 1 ) ) ; return aarch64_internal_mov_immediate ( NULL_RTX , lo , false , DImode ) + aarch64_internal_mov_immediate ( NULL_RTX , hi , false , DImode ) <= 4 ; } </s>

Return whether imm is a 128-bit immediate which is simple enough to expand inline .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { MCFixupKind Kind = Fixup . getKind ( ) ; switch ( ( unsigned ) Kind ) { default : return Kind >= FirstLiteralRelocationKind ; case PPC :: fixup_ppc_br24 : case PPC :: fixup_ppc_br24abs : case PPC :: fixup_ppc_br24_notoc : if ( const MCSymbolRefExpr * A = Target . getSymA ( ) ) { if ( const auto * S = dyn_cast < MCSymbolELF > ( & A -> getSymbol ( ) ) ) { unsigned Other = S -> getOther ( ) << 2 ; if ( ( Other & ELF :: STO_PPC64_LOCAL_MASK ) != 0 ) return true ; } } return false ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> unsigned FISCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool ix86_function_arg_regno_p ( int regno ) { int i ; const int * parm_regs ; if ( TARGET_MPX && BND_REGNO_P ( regno ) ) return true ; if ( ! TARGET_64BIT ) { if ( TARGET_MACHO ) return ( regno < REGPARM_MAX || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ! fixed_regs [ regno ] ) ) ; else return ( regno < REGPARM_MAX || ( TARGET_MMX && MMX_REGNO_P ( regno ) && ( regno < FIRST_MMX_REG + MMX_REGPARM_MAX ) ) || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) ) ; } if ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) return true ; if ( ix86_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( ix86_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; for ( i = 0 ; i < ( ix86_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX ) ; i ++ ) if ( regno == parm_regs [ i ] ) return true ; return false ; } </s>

Return true when register may be used to pass function parameters .


<s> static bool mips_valid_base_register_p ( rtx x , machine_mode mode , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && mips_regno_mode_ok_for_base_p ( REGNO ( x ) , mode , strict_p ) ) ; } </s>

Return true if X is a valid base register for the given mode . Allow only hard registers if STRICT .


<s>
SDValue
SystemZTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
unsigned
CallConv
,
bool
isVarArg
,
bool
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

SystemZ
SystemZ
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> static void sh_print_operand_address ( FILE * stream , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : fprintf ( stream , "@%s" , reg_names [ true_regnum ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "@(%d,%s)" , ( int ) INTVAL ( index ) , reg_names [ true_regnum ( base ) ] ) ; break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; fprintf ( stream , "@(r0,%s)" , reg_names [ MAX ( base_num , index_num ) ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case PRE_DEC : fprintf ( stream , "@-%s" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( stream , "@%s+" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; default : x = mark_constant_pool_use ( x ) ; output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address in x to the stream .


<s> unsigned LanaiMCCodeEmitter :: getMachineOpValue ( const MCInst & Inst , const MCOperand & MCOp , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { if ( MCOp . isReg ( ) ) return getLanaiRegisterNumbering ( MCOp . getReg ( ) ) ; if ( MCOp . isImm ( ) ) < unsigned > ( MCOp . getImm ( ) ) ; assert ( MCOp . isExpr ( ) ) ; const MCExpr * Expr = MCOp . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * BinaryExpr = static_cast < const MCBinaryExpr * > ( Expr ) ; Expr = BinaryExpr -> getLHS ( ) ; } assert ( isa < LanaiMCExpr > ( Expr ) || Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , MCFixupKind ( FixupKind ( Expr ) ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool MipsHazardSchedule :: runOnMachineFunction ( MachineFunction & MF ) { const MipsSubtarget * STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! STI -> hasMips32r6 ( ) || STI -> inMicroMipsMode ( ) ) return false ; bool Changed = false ; const MipsInstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; bool InsertNop = false ; if ( std :: next ( I ) != FI -> end ( ) && ! TII -> SafeInForbiddenSlot ( * getNextMachineInstr ( std :: next ( I ) ) ) ) { InsertNop = true ; } else { for ( auto * Succ : FI -> successors ( ) ) { if ( FI -> isLayoutSuccessor ( Succ ) && getNextMachineInstr ( Succ -> begin ( ) ) != Succ -> end ( ) && ! TII -> SafeInForbiddenSlot ( * getNextMachineInstr ( Succ -> begin ( ) ) ) ) { InsertNop = true ; break ; } } } if ( InsertNop ) { Changed = true ; MIBundleBuilder ( I ) . append ( BuildMI ( MF , I -> getDebugLoc ( ) , TII -> get ( Mips :: NOP ) ) ) ; NumInsertedNops ++ ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips::NOP


<s> unsigned PPCAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = 0 ; break ; case MCK_1 : ImmVal = 1 ; break ; case MCK_2 : ImmVal = 2 ; break ; case MCK_3 : ImmVal = 3 ; break ; case MCK_4 : ImmVal = 4 ; break ; case MCK_5 : ImmVal = 5 ; break ; case MCK_6 : ImmVal = 6 ; break ; case MCK_7 : ImmVal = 7 ; break ; default : return Match_InvalidOperand ; } PPCOperand & Op = static_cast < PPCOperand & > ( AsmOp ) ; if ( Op . isU3Imm ( ) && Op . getImm ( ) == ImmVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static tree rs6000_stack_protect_fail ( void ) { return ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) ? default_hidden_stack_protect_fail ( ) : default_external_stack_protect_fail ( ) ; } </s>

For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register setup by using __stack_chk_fail_local hidden function instead of calling __stack_chk_fail directly . Otherwise it is better to call __stack_chk_fail directly .


"multiversioning needs ifunc which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; OutStreamer . EmitRawText ( "\t.frame\t$" + Twine ( LowercaseString ( getRegisterName ( stackReg ) ) ) + "," + Twine ( stackSize ) + ",$" + Twine ( LowercaseString ( getRegisterName ( returnReg ) ) ) ) ; } </s>


"%qs is only valid for the cell processor"

"%qs requires ISA 3.0 IEEE 128-bit floating point"

"%qs requires the %qs (or newer), and %qs or %qs options"

"%qs is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s>
bool
AArch64FrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
const
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterInfo
*
RegInfo
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
assert
(
!
RegInfo
->
needsStackRealignment
(
MF
)
&&
"No stack realignment on AArch64!"
)
;
return
(
MFI
->
hasCalls
(
)
||
MFI
->
hasVarSizedObjects
(
)
||
MFI
->
isFrameAddressTaken
(
)
)
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void rs6000_expand_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , cond ; machine_mode mode ; enum memmodel model ; rtx label , x , mask , shift ; retval = operands [ 0 ] ; mem = operands [ 1 ] ; val = operands [ 2 ] ; model = memmodel_base ( INTVAL ( operands [ 3 ] ) ) ; mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( ! TARGET_SYNC_HI_QI && ( mode == QImode || mode == HImode ) ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; val = convert_modes ( SImode , mode , val , 1 ) ; val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; x = val ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , val , mask ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; rs6000_post_atomic_barrier ( model ) ; if ( shift ) rs6000_finish_atomic_subword ( operands [ 0 ] , retval , shift ) ; } </s>


<s> static void pru_reorg ( void ) { rtx_insn * insns = get_insns ( ) ; compute_bb_for_insn ( ) ; df_analyze ( ) ; shorten_branches ( get_insns ( ) ) ; pru_reorg_loop ( insns ) ; df_finish_pass ( false ) ; } </s>


<s> EVT X86TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ! FuncAttributes . hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Op . size ( ) >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || Op . isAligned ( Align ( 16 ) ) ) ) { if ( Op . size ( ) >= 64 && Subtarget . hasAVX512 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 512 ) ) { return Subtarget . hasBWI ( ) ? MVT :: v64i8 : MVT :: v16i32 ; } if ( Op . size ( ) >= 32 && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 256 ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v4f32 ; } else if ( ( ( Op . isMemcpy ( ) && ! Op . isMemcpyStrSrc ( ) ) || Op . isZeroMemset ( ) ) && Op . size ( ) >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Op . size ( ) >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void Initialize ( const MachineFunction & MF , bool isPIC , bool isLittleEndian ) { IsPIC = isPIC ; IsLittleEndian = isLittleEndian ; } </s>

This method must be called before any actual lowering is done .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : if ( VT == MVT :: i32 ) return std :: make_pair ( 0U , SystemZ :: GR32RegisterClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , SystemZ :: GR128RegisterClass ) ; return std :: make_pair ( 0U , SystemZ :: GR64RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void ix86_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned HOST_WIDE_INT ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_cost_table [ ix86_tune ] ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = HOST_WIDE_INT_1U << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( ix86_tune , false ) ; } </s>


<s> const char * loongarch_output_probe_stack_range ( rtx reg1 , rtx reg2 , rtx reg3 ) { static int labelno = 0 ; char loop_lab [ 32 ] , tmp [ 64 ] ; rtx xops [ 3 ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , "LPSRL" , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ 0 ] = reg1 ; xops [ 1 ] = GEN_INT ( - PROBE_INTERVAL ) ; xops [ 2 ] = reg3 ; if ( TARGET_64BIT ) output_asm_insn ( "sub.d\t%0,%0,%2" , xops ) ; else output_asm_insn ( "sub.w\t%0,%0,%2" , xops ) ; xops [ 1 ] = reg2 ; strcpy ( tmp , "bne\t%0,%1," ) ; if ( TARGET_64BIT ) output_asm_insn ( "st.d\t$r0,%0,0" , xops ) ; else output_asm_insn ( "st.w\t$r0,%0,0" , xops ) ; output_asm_insn ( strcat ( tmp , & loop_lab [ 1 ] ) , xops ) ; return "" ; } </s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> Optional < unsigned > AArch64InstrInfo :: getUnscaledLdSt ( unsigned Opc ) { switch ( Opc ) { default : return { } ; case AArch64 :: PRFMui : return AArch64 :: PRFUMi ; case AArch64 :: LDRXui : return AArch64 :: LDURXi ; case AArch64 :: LDRWui : return AArch64 :: LDURWi ; case AArch64 :: LDRBui : return AArch64 :: LDURBi ; case AArch64 :: LDRHui : return AArch64 :: LDURHi ; case AArch64 :: LDRSui : return AArch64 :: LDURSi ; case AArch64 :: LDRDui : return AArch64 :: LDURDi ; case AArch64 :: LDRQui : return AArch64 :: LDURQi ; case AArch64 :: LDRBBui : return AArch64 :: LDURBBi ; case AArch64 :: LDRHHui : return AArch64 :: LDURHHi ; case AArch64 :: LDRSBXui : return AArch64 :: LDURSBXi ; case AArch64 :: LDRSBWui : return AArch64 :: LDURSBWi ; case AArch64 :: LDRSHXui : return AArch64 :: LDURSHXi ; case AArch64 :: LDRSHWui : return AArch64 :: LDURSHWi ; case AArch64 :: LDRSWui : return AArch64 :: LDURSWi ; case AArch64 :: STRXui : return AArch64 :: STURXi ; case AArch64 :: STRWui : return AArch64 :: STURWi ; case AArch64 :: STRBui : return AArch64 :: STURBi ; case AArch64 :: STRHui : return AArch64 :: STURHi ; case AArch64 :: STRSui : return AArch64 :: STURSi ; case AArch64 :: STRDui : return AArch64 :: STURDi ; case AArch64 :: STRQui : return AArch64 :: STURQi ; case AArch64 :: STRBBui : return AArch64 :: STURBBi ; case AArch64 :: STRHHui : return AArch64 :: STURHHi ; } } </s>

Returns the unscaled load/store for the scaled load/store opcode , if there is a corresponding unscaled variant available .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? Mips :: FP : Mips :: SP ; } </s>


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { switch ( ( PPC :: Fixups ) Fixup . getKind ( ) ) { default : return false ; case PPC :: fixup_ppc_br24 : case PPC :: fixup_ppc_br24abs : if ( const MCSymbolRefExpr * A = Target . getSymA ( ) ) { if ( const auto * S = dyn_cast < MCSymbolELF > ( & A -> getSymbol ( ) ) ) { unsigned Other = S -> getOther ( ) << 2 ; if ( ( Other & ELF :: STO_PPC64_LOCAL_MASK ) != 0 ) return true ; } } return false ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> BitVector FISCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( FISC :: SP ) ; Reserved . set ( FISC :: LR ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> unsigned size ( ) const { return AllValues . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> void pru_expand_epilogue ( bool sibcall_p ) { int total_frame_size ; int sp_adjust , save_offset ; int regno_start ; if ( ! sibcall_p && pru_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } emit_insn ( gen_blockage ( ) ) ; total_frame_size = cfun -> machine -> total_size ; if ( frame_pointer_needed ) { pru_add3_frame_adjust ( stack_pointer_rtx , hard_frame_pointer_rtx , - cfun -> machine -> save_reg_size , REG_CFA_ADJUST_CFA ) ; save_offset = 0 ; sp_adjust = total_frame_size - cfun -> machine -> save_regs_offset ; } else if ( ! UBYTE_INT ( total_frame_size ) ) { pru_add_to_sp ( cfun -> machine -> save_regs_offset , REG_CFA_ADJUST_CFA ) ; save_offset = 0 ; sp_adjust = total_frame_size - cfun -> machine -> save_regs_offset ; } else { save_offset = cfun -> machine -> save_regs_offset ; sp_adjust = total_frame_size ; } regno_start = 0 ; do regno_start = xbbo_next_reg_cluster ( regno_start , & save_offset , false ) ; while ( regno_start >= 0 ) ; emit_insn ( gen_blockage ( ) ) ; if ( sp_adjust ) pru_add_to_sp ( sp_adjust , REG_CFA_ADJUST_CFA ) ; if ( ! sibcall_p ) emit_jump_insn ( gen_simple_return ( ) ) ; } </s>


<s> bool AArch64TargetLowering :: hasPairedLoad ( EVT LoadedType , unsigned & RequiredAligment ) const { if ( ! LoadedType . isSimple ( ) || ( ! LoadedType . isInteger ( ) && ! LoadedType . isFloatingPoint ( ) ) ) return false ; RequiredAligment = 0 ; unsigned NumBits = LoadedType . getSizeInBits ( ) ; return NumBits == 32 || NumBits == 64 ; } </s>

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory .


<s> void emitBytes ( StringRef Data ) override { emitDataMappingSymbol ( ) ; MCELFStreamer :: emitBytes ( Data ) ; } </s>

Emit the bytes in Data into the output .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ARMBaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createARMGlobalMergePass ( getTargetLowering ( ) ) ) ; return false ; } </s>


<s> SDValue DLXSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & , const SDLoc & , SDValue , SDValue , SDValue , SDValue Size , unsigned , bool , bool , MachinePointerInfo , MachinePointerInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> bool aarch64_use_pseudo_pic_reg ( void ) { return aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ; } </s>

Return 1 if pseudo register should be created and used to hold GOT address for PIC code .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { if ( ! Subtarget . isPPC64 ( ) ) return hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s>
static
void
mmix_asm_trampoline_template
(
FILE
*
stream
)
{
fprintf
(
stream
,
"\tGETA $255,1F\n\t"
)
;
fprintf
(
stream
,
"LDOU %s,$255,0\n\t"
,
reg_names
[
MMIX_STATIC_CHAIN_REGNUM
]
)
;
fprintf
(
stream
,
"LDOU $255,$255,8\n\t"
)
;
fprintf
(
stream
,
"GO $255,$255,0\n"
)
;
fprintf
(
stream
,
"1H\tOCTA 0\n\t"
)
;
fprintf
(
stream
,
"OCTA 0\n"
)
;
}
</s>


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LDC1 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
static
HOST_WIDE_INT
rs6000_disable_incompatible_switches
(
void
)
{
HOST_WIDE_INT
ignore_masks
=
rs6000_isa_flags_explicit
;
size_t
i
,
j
;
static
const
struct
{
const
HOST_WIDE_INT
no_flag
;
const
HOST_WIDE_INT
dep_flags
;
const
char
*
const
name
;
}
flags
[
]
=
{
{
OPTION_MASK_P9_VECTOR
,
OTHER_P9_VECTOR_MASKS
,
"power9-vector"
}
,
{
OPTION_MASK_P8_VECTOR
,
OTHER_P8_VECTOR_MASKS
,
"power8-vector"
}
,
{
OPTION_MASK_VSX
,
OTHER_VSX_VECTOR_MASKS
,
"vsx"
}
,
}
;
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
flags
)
;
i
++
)
{
HOST_WIDE_INT
no_flag
=
flags
[
i
]
.
no_flag
;
if
(
(
rs6000_isa_flags
&
no_flag
)
==
0
&&
(
rs6000_isa_flags_explicit
&
no_flag
)
!=
0
)
{
HOST_WIDE_INT
dep_flags
=
flags
[
i
]
.
dep_flags
;
HOST_WIDE_INT
set_flags
=
(
rs6000_isa_flags_explicit
&
rs6000_isa_flags
&
dep_flags
)
;
if
(
set_flags
)
{
for
(
j
=
0
;
j
<
ARRAY_SIZE
(
rs6000_opt_masks
)
;
j
++
)
if
(
(
set_flags
&
rs6000_opt_masks
[
j
]
.
mask
)
!=
0
)
{
set_flags
&=
~
rs6000_opt_masks
[
j
]
.
mask
;
error
(
"%<-mno-%s%> turns off %<-m%s%>"
,
flags
[
i
]
.
name
,
rs6000_opt_masks
[
j
]
.
name
)
;
}
gcc_assert
(
!
set_flags
)
;
}
rs6000_isa_flags
&=
~
dep_flags
;
ignore_masks
|=
no_flag
|
dep_flags
;
}
}
return
ignore_masks
;
}
</s>

If the user used -mno-vsx , we need turn off all of the implicit ISA 2.06 , 2.07 , and 3.0 options that relate to the vector unit ( -mdirect-move , -mupper-regs-df , etc. ) . If the user used -mno-power8-vector , we need to turn off all of the implicit ISA 2.07 and 3.0 options that relate to the vector unit . If the user used -mno-power9-vector , we need to turn off all of the implicit ISA 3.0 options that relate to the vector unit . This function does not handle explicit options such as the user specifying -mdirect-move . These are handled in rs6000_option_override_internal , and the appropriate error is given if needed . We return a mask of all of the implicit options that should not be enabled by default .


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> static bool loongarch_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( ! loongarch_mode_ok_for_mov_fmt_p ( mode1 ) && ! loongarch_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ; } </s>


<s>
uint32_t
AArch64MCCodeEmitter
::
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected ADR target type!"
)
;
MCFixupKind
Kind
=
MI
.
getOpcode
(
)
==
AArch64
::
BL
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_call26
)
:
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_branch26
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
Kind
,
MI
.
getLoc
(
)
)
)
;
++
MCNumFixups
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
mf
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
RDA
=
&
getAnalysis
<
ReachingDefAnalysis
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
*
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


Constant pools are per function only when PC relative literal loads are true or we are in the large memory model .


<s>
void
UPTDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
LLVM_DEBUG
(
outs
(
)
<<
"Selecting: "
;
N
->
dump
(
CurDAG
)
;
outs
(
)
<<
"\n"
)
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
Constant
:
if
(
SelectMoveImmediate
(
N
)
)
return
;
break
;
case
ISD
::
BR_CC
:
if
(
SelectConditionalBranch
(
N
)
)
return
;
break
;
}
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

UPT
UPT
"Selecting: "
"\n"
ISD::Constant
ISD::BR_CC


<s>
void
SystemZPostRASchedStrategy
::
leaveMBB
(
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Leaving "
<<
printMBBReference
(
*
MBB
)
<<
"\n"
;
)
;
advanceTo
(
MBB
->
getFirstTerminator
(
)
)
;
}
</s>

Tell the strategy that current MBB is done .


<s> MachineBasicBlock :: iterator end ( ) const { return ++ MachineBasicBlock :: iterator ( KillInst ? KillInst : LastInst ) ; } </s>

Get a const_iterator to the end of the symbol table .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> static rtx mmix_function_arg_1 ( const cumulative_args_t argsp_v , const function_arg_info & arg , bool incoming ) { CUMULATIVE_ARGS * argsp = get_cumulative_args ( argsp_v ) ; machine_mode mode = arg . mode == VOIDmode ? DImode : arg . mode ; if ( arg . end_marker_p ( ) ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS && ! targetm . calls . must_pass_in_stack ( arg ) && ( GET_MODE_BITSIZE ( mode ) <= 64 || argsp -> lib || TARGET_LIBFUNC ) ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; } </s>

Helper function for mmix_function_arg and mmix_function_incoming_arg .


<s> void ARMPassConfig :: addCodeGenPrepare ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createTypePromotionPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : { if ( tryInlineAsm ( N ) ) return ; break ; } case SPISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; return ; } } SelectCode ( N ) ; } </s>


<s>
bool
ARMTargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeAllocSizeInBits
(
SubVecTy
)
;
bool
EltIs64Bits
=
DL
.
getTypeAllocSizeInBits
(
EltTy
)
==
64
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
||
EltIs64Bits
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
Op0
->
getType
(
)
->
getVectorNumElements
(
)
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
static
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
arm_neon_vst2
,
Intrinsic
::
arm_neon_vst3
,
Intrinsic
::
arm_neon_vst4
}
;
SmallVector
<
Value
*
,
6
>
Ops
;
Type
*
Int8Ptr
=
Builder
.
getInt8PtrTy
(
SI
->
getPointerAddressSpace
(
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
Int8Ptr
)
)
;
Type
*
Tys
[
]
=
{
Int8Ptr
,
SubVecTy
}
;
Function
*
VstNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
getInt32
(
SI
->
getAlignment
(
)
)
)
;
Builder
.
CreateCall
(
VstNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < TOYSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> int AArch64TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( IID >= Intrinsic :: aarch64_addg && IID <= Intrinsic :: aarch64_udiv ) return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> unsigned SparcRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return SP :: I6 ; } </s>


<s>
SDNode
*
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
nullptr
;
}
std
::
pair
<
bool
,
SDNode
*
>
Ret
=
selectNode
(
Node
)
;
if
(
Ret
.
first
)
return
Ret
.
second
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
nullptr
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."
"=> "
"\n"


<s> static void scan_record_type ( const_tree type , int * intregs_p , int * fpregs_p , int * packed_p ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) scan_record_type ( TREE_TYPE ( field ) , intregs_p , fpregs_p , 0 ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU ) * fpregs_p = 1 ; else * intregs_p = 1 ; if ( packed_p && DECL_PACKED ( field ) ) * packed_p = 1 ; } } } </s>

Scan the record type TYPE and return the following predicates : - INTREGS_P : the record contains at least one field or sub-field that is eligible for promotion in integer registers . - FP_REGS_P : the record contains at least one field or sub-field that is eligible for promotion in floating-point registers . - PACKED_P : the record contains at least one field that is packed . Sub-fields are not taken into account for the PACKED_P predicate .


<s> const MINA32RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static int ix86_mode_exit ( int entity ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_exit ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function exit .


<s> static bool nds32_ict_const_p ( rtx x ) { if ( GET_CODE ( x ) == CONST ) { x = XEXP ( x , 0 ) ; return nds32_indirect_call_referenced_p ( x ) ; } return FALSE ; } </s>

Return true if x is const and the referance is ict symbol .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s> static bool ix86_swap_binary_operands_p ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src1 = operands [ 1 ] ; rtx src2 = operands [ 2 ] ; if ( GET_RTX_CLASS ( code ) != RTX_COMM_ARITH && GET_RTX_CLASS ( code ) != RTX_COMM_COMPARE ) return false ; if ( rtx_equal_p ( dst , src1 ) ) return false ; if ( rtx_equal_p ( dst , src2 ) ) return true ; if ( immediate_operand ( src2 , mode ) ) return false ; if ( immediate_operand ( src1 , mode ) ) return true ; if ( MEM_P ( src2 ) ) return false ; if ( MEM_P ( src1 ) ) return true ; return false ; } </s>

Helper function of ix86_fixup_binary_operands to canonicalize operand order . Returns true if the operands should be swapped .


<s> MCSection * LanaiTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s>
bool
ThumbDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
const
MemoryObject
&
Region
,
uint64_t
Address
,
raw_ostream
&
os
)
const
{
unsigned
insn
=
0
;
uint16_t
insn1
=
0
;
uint8_t
bytes
[
2
]
;
if
(
Region
.
readBytes
(
Address
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
unsigned
bits15_11
=
slice
(
insn
,
15
,
11
)
;
bool
IsThumb2
=
false
;
if
(
bits15_11
==
0x1D
||
bits15_11
==
0x1E
||
bits15_11
==
0x1F
)
{
IsThumb2
=
true
;
if
(
Region
.
readBytes
(
Address
+
2
,
2
,
(
uint8_t
*
)
bytes
,
)
==
1
)
return
false
;
insn1
=
(
bytes
[
1
]
<<
8
)
|
bytes
[
0
]
;
insn
=
(
insn
<<
16
|
insn1
)
;
}
unsigned
Opcode
=
decodeThumbSideEffect
(
IsThumb2
,
insn
)
;
ARMFormat
Format
=
ARMFormats
[
Opcode
]
;
Size
=
IsThumb2
4
:
2
;
DEBUG
(
{
errs
(
)
<<
"Opcode="
<<
Opcode
<<
" Name="
<<
ARMUtils
::
OpcodeName
(
Opcode
)
<<
" Format="
<<
stringForARMFormat
(
Format
)
<<
'('
<<
(
int
)
Format
<<
")\n"
;
showBitVector
(
errs
(
)
,
insn
)
;
}
)
;
ARMBasicMCBuilder
*
Builder
=
CreateMCBuilder
(
Opcode
,
Format
)
;
if
(
!
Builder
)
return
false
;
Builder
->
SetSession
(
const_cast
<
Session
*
>
(
&
SO
)
)
;
if
(
!
Builder
->
Build
(
MI
,
insn
)
)
return
false
;
delete
Builder
;
return
true
;
}
</s>

Returns the disassembly of a single instruction .


<s> static void make_cpu_type_builtin ( const char * name , int code , enum ix86_builtin_func_type ftype , bool is_const ) { tree decl ; tree type ; type = ix86_get_builtin_func_type ( ftype ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; gcc_assert ( decl != NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; TREE_READONLY ( decl ) = is_const ; } </s>

Make builtins to detect cpu type and features supported . NAME is the builtin name , CODE is the builtin code , and FTYPE is the function type of the builtin .


<s> bool NEONMoveFixPass :: runOnMachineFunction ( MachineFunction & Fn ) { ARMFunctionInfo * AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; const TargetMachine & TM = Fn . getTarget ( ) ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; TRI = TM . getRegisterInfo ( ) ; TII = static_cast < const ARMBaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= InsertMoves ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static void ia64_add_bundle_selector_before ( int template0 , rtx_insn * insn ) { rtx b = gen_bundle_selector ( GEN_INT ( template0 ) ) ; ia64_emit_insn_before ( b , insn ) ; if ( ( template0 == 4 || template0 == 5 ) && ia64_except_unwind_info ( & global_options ) == UI_TARGET ) { int i ; rtx note = NULL_RTX ; insn = PREV_INSN ( insn ) ; for ( i = 0 ; i < 3 ; i ++ ) { do insn = next_active_insn ( insn ) ; while ( NONJUMP_INSN_P ( insn ) && get_attr_empty ( insn ) == EMPTY_YES ) ; if ( CALL_P ( insn ) ) note = find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ; else if ( note ) { int code ; gcc_assert ( ( code = recog_memoized ( insn ) ) == CODE_FOR_nop || code == CODE_FOR_nop_b ) ; if ( find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ) note = NULL_RTX ; else add_reg_note ( insn , REG_EH_REGION , XEXP ( note , 0 ) ) ; } } } } </s>

Add a bundle selector TEMPLATE0 before INSN .


<s> static rtx mips16e_build_save_restore ( bool restore_p , unsigned int * mask_ptr , HOST_WIDE_INT * offset_ptr , unsigned int nargs , HOST_WIDE_INT size ) { rtx pattern , set ; HOST_WIDE_INT offset , top_offset ; unsigned int i , regno ; int n ; gcc_assert ( cfun -> machine -> frame . num_fp == 0 ) ; n = 1 + nargs ; for ( i = 0 ; i < ARRAY_SIZE ( mips16e_save_restore_regs ) ; i ++ ) if ( BITSET_P ( * mask_ptr , mips16e_save_restore_regs [ i ] ) ) n ++ ; pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( n ) ) ; n = 0 ; set = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , restore_p ? size : - size ) ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; XVECEXP ( pattern , 0 , n ++ ) = set ; top_offset = restore_p ? size : 0 ; for ( i = 0 ; i < nargs ; i ++ ) { offset = top_offset + i * UNITS_PER_WORD ; set = mips16e_save_restore_reg ( restore_p , true , offset , GP_ARG_FIRST + i ) ; XVECEXP ( pattern , 0 , n ++ ) = set ; } offset = top_offset ; for ( i = 0 ; i < ARRAY_SIZE ( mips16e_save_restore_regs ) ; i ++ ) { regno = mips16e_save_restore_regs [ i ] ; if ( BITSET_P ( * mask_ptr , regno ) ) { offset -= UNITS_PER_WORD ; set = mips16e_save_restore_reg ( restore_p , false , offset , regno ) ; XVECEXP ( pattern , 0 , n ++ ) = set ; * mask_ptr &= ~ ( 1 << regno ) ; } } * offset_ptr = size + ( offset - top_offset ) ; gcc_assert ( n == XVECLEN ( pattern , 0 ) ) ; return pattern ; } </s>

Return RTL for a MIPS16e SAVE or RESTORE instruction ; RESTORE_P says which . The instruction must : - Allocate or deallocate SIZE bytes in total ; SIZE is known to be nonzero . - Save or restore as many registers in * MASK_PTR as possible . The instruction saves the first registers at the top of the allocated area , with the other registers below it . - Save NARGS argument registers above the allocated area . ( NARGS is always zero if RESTORE_P . ) The SAVE and RESTORE instructions can not save and restore all general registers , so there may be some registers left over for the caller to handle . Destructively modify * MASK_PTR so that it contains the registers that still need to be saved or restored . The caller can save these registers in the memory immediately below * OFFSET_PTR , which is a byte offset from the bottom of the allocated stack area .


<s> void PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = TM . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

PowerPC PPC PPC PPC::ADDI8 PPC::ADDI PPC PPC 0


"getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates"

getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch target operand .


<s> void SystemZAsmPrinter :: emitEndOfAsmFile ( Module & M ) { emitStackMaps ( SM ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> enum reg_class aarch64_regno_regclass ( unsigned regno ) { if ( GP_REGNUM_P ( regno ) ) return GENERAL_REGS ; if ( regno == SP_REGNUM ) return STACK_REG ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno ) ? PR_LO_REGS : PR_HI_REGS ; return NO_REGS ; } </s>


<s> static void rs6000_emit_move_from_cr ( rtx reg ) { if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ 8 ] , count = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == 1 ) { rtvec p = rtvec_alloc ( 1 ) ; rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ 0 ] ) ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - cr_reg [ 0 ] ) ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_SET ( VOIDmode , reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ; } } emit_insn ( gen_movesi_from_cr ( reg ) ) ; } </s>

Emit code to store CR fields that need to be saved into REG .


<s> bool clear_operation_p ( rtx op , bool vfp ) { unsigned regno ; unsigned last_regno = INVALID_REGNUM ; rtx elt , reg , zero ; int count = XVECLEN ( op , 0 ) ; int first_set = vfp ? 1 : 0 ; machine_mode expected_mode = vfp ? E_SFmode : E_SImode ; for ( int i = first_set ; i < count ; i ++ ) { elt = XVECEXP ( op , 0 , i ) ; if ( ! vfp && GET_CODE ( elt ) == UNSPEC_VOLATILE ) { if ( XINT ( elt , 1 ) != VUNSPEC_CLRM_APSR || XVECLEN ( elt , 0 ) != 1 || XVECEXP ( elt , 0 , 0 ) != CONST0_RTX ( SImode ) || i != count - 2 ) return false ; continue ; } if ( GET_CODE ( elt ) == CLOBBER ) continue ; if ( GET_CODE ( elt ) != SET ) return false ; reg = SET_DEST ( elt ) ; zero = SET_SRC ( elt ) ; if ( ! REG_P ( reg ) || GET_MODE ( reg ) != expected_mode || zero != CONST0_RTX ( SImode ) ) return false ; regno = REGNO ( reg ) ; if ( vfp ) { if ( i != first_set && regno != last_regno + 1 ) return false ; } else { if ( regno == SP_REGNUM || regno == PC_REGNUM ) return false ; if ( i != first_set && regno <= last_regno ) return false ; } last_regno = regno ; } return true ; } </s>

Checks whether OP is a valid parallel pattern for a CLRM ( if VFP is false ) or VSCCLRM ( otherwise ) insn . To be a valid CLRM pattern , OP must have the following form : [ ( set ( reg : SI < N > ) ( const_int 0 ) ) ( set ( reg : SI < M > ) ( const_int 0 ) ) ... ( unspec_volatile [ ( const_int 0 ) ] VUNSPEC_CLRM_APSR ) ( clobber ( reg : CC CC_REGNUM ) ) ] Any number ( including 0 ) of set expressions is valid , the volatile unspec is optional . All registers but SP and PC are allowed and registers must be in strict increasing order . To be a valid VSCCLRM pattern , OP must have the following form : [ ( unspec_volatile [ ( const_int 0 ) ] VUNSPEC_VSCCLRM_VPR ) ( set ( reg : SF < N > ) ( const_int 0 ) ) ( set ( reg : SF < M > ) ( const_int 0 ) ) ... ] As with CLRM , any number ( including 0 ) of set expressions is valid , however the volatile unspec is mandatory here . Any VFP single-precision register is accepted but all registers must be consecutive and in increasing order .


<s> bool X86TargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return hasAndNotCompare ( Y ) ; if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < 128 ) return false ; if ( VT == MVT :: v4i32 ) return true ; return Subtarget . hasSSE2 ( ) ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s>
void
VEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
IsAliasOfSX
(
SrcReg
)
&&
IsAliasOfSX
(
DestReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
ORri
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
else
if
(
VE
::
V64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
Register
TmpReg
=
VE
::
SX16
;
Register
SubTmp
=
TRI
->
getSubReg
(
TmpReg
,
VE
::
sub_i32
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
LEAzii
)
,
TmpReg
)
.
addImm
(
0
)
.
addImm
(
0
)
.
addImm
(
256
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
VORmvl
)
,
DestReg
)
.
addImm
(
M1
(
0
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SubTmp
,
getKillRegState
(
true
)
)
;
MIB
.
getInstr
(
)
->
addRegisterKilled
(
TmpReg
,
TRI
,
true
)
;
}
else
if
(
VE
::
F128RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
unsigned
SubRegIdx
[
]
=
{
VE
::
sub_even
,
VE
::
sub_odd
}
;
unsigned
int
NumSubRegs
=
2
;
copyPhysSubRegs
(
MBB
,
I
,
DL
,
DestReg
,
SrcReg
,
KillSrc
,
get
(
VE
::
ORri
)
,
NumSubRegs
,
SubRegIdx
,
&
getRegisterInfo
(
)
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
dbgs
(
)
<<
"Impossible reg-to-reg copy from "
<<
printReg
(
SrcReg
,
TRI
)
<<
" to "
<<
printReg
(
DestReg
,
TRI
)
<<
"\n"
;
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>


<s> static enum rtx_code ix86_prepare_sse_fp_compare_args ( rtx dest , enum rtx_code code , rtx * pop0 , rtx * pop1 ) { switch ( code ) { case LTGT : case UNEQ : if ( TARGET_AVX ) break ; return UNKNOWN ; case LT : case LE : case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED : case ORDERED : if ( TARGET_AVX ) break ; if ( ! dest || ! rtx_equal_p ( dest , * pop1 ) ) break ; case GE : case GT : case UNLE : case UNLT : std :: swap ( * pop0 , * pop1 ) ; code = swap_condition ( code ) ; break ; default : gcc_unreachable ( ) ; } return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to an sse comparison with a mask result . Thus we differ a bit from ix86_prepare_fp_compare_args which expects to produce a flags result . The DEST operand exists to help determine whether to commute commutative operators . The POP0/POP1 operands are updated in place . The new comparison code is returned , or UNKNOWN if not implementable .


<s> static bool mips_near_type_p ( const_tree type ) { return ( lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( type ) ) != NULL || lookup_attribute ( "near" , TYPE_ATTRIBUTES ( type ) ) != NULL ) ; } </s>

Predicates to test for presence of `` near '' and `` far '' / '' long_call '' attributes on the given TYPE .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> unsigned Mips16InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool AArch64TargetLowering :: shouldLocalize ( const MachineInstr & MI , const TargetTransformInfo * TTI ) const { if ( MI . getOpcode ( ) == TargetOpcode :: G_GLOBAL_VALUE ) { const GlobalValue & GV = * MI . getOperand ( 1 ) . getGlobal ( ) ; if ( GV . isThreadLocal ( ) && Subtarget -> isTargetMachO ( ) ) return false ; } return TargetLoweringBase :: shouldLocalize ( MI , TTI ) ; } </s>

Check whether or not MI needs to be moved close to its uses .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , UseNEONForSinglePrecisionFP ( false ) , UseMulOps ( UseFusedMulOps ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasHardwareDivideInARM ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , AvoidMOVsShifterOperand ( false ) , HasRAS ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TT . find ( "eabi" ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> void aarch64_split_128bit_move ( rtx dst , rtx src ) { rtx dst_lo , dst_hi ; rtx src_lo , src_hi ; machine_mode mode = GET_MODE ( dst ) ; gcc_assert ( mode == TImode || mode == TFmode ) ; gcc_assert ( ! ( side_effects_p ( src ) || side_effects_p ( dst ) ) ) ; gcc_assert ( mode == GET_MODE ( src ) || GET_MODE ( src ) == VOIDmode ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { int src_regno = REGNO ( src ) ; int dst_regno = REGNO ( dst ) ; if ( FP_REGNUM_P ( dst_regno ) && GP_REGNUM_P ( src_regno ) ) { src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart ( word_mode , src ) ; if ( mode == TImode ) { emit_insn ( gen_aarch64_movtilow_di ( dst , src_lo ) ) ; emit_insn ( gen_aarch64_movtihigh_di ( dst , src_hi ) ) ; } else { emit_insn ( gen_aarch64_movtflow_di ( dst , src_lo ) ) ; emit_insn ( gen_aarch64_movtfhigh_di ( dst , src_hi ) ) ; } return ; } else if ( GP_REGNUM_P ( dst_regno ) && FP_REGNUM_P ( src_regno ) ) { dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; if ( mode == TImode ) { emit_insn ( gen_aarch64_movdi_tilow ( dst_lo , src ) ) ; emit_insn ( gen_aarch64_movdi_tihigh ( dst_hi , src ) ) ; } else { emit_insn ( gen_aarch64_movdi_tflow ( dst_lo , src ) ) ; emit_insn ( gen_aarch64_movdi_tfhigh ( dst_hi , src ) ) ; } return ; } } dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart_mode ( word_mode , mode , src ) ; if ( reg_overlap_mentioned_p ( dst_lo , src_hi ) ) { aarch64_emit_move ( dst_hi , src_hi ) ; aarch64_emit_move ( dst_lo , src_lo ) ; } else { aarch64_emit_move ( dst_lo , src_lo ) ; aarch64_emit_move ( dst_hi , src_hi ) ; } } </s>

Split a 128-bit move operation into two 64-bit move operations , taking care to handle partial overlap of register to register copies . Special cases are needed when moving between GP regs and FP regs . SRC can be a register , constant or memory ; DST a register or memory . If either operand is memory it must not have any side effects .


<s> bool PPCInstrInfo :: isPredicated ( const MachineInstr & MI ) const { return false ; } </s>

Returns true if the instruction is already predicated .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > ( ) ; AsmPrinter :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const MipsInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> static bool needs_frame_header_p ( function * fn ) { tree t ; if ( fn -> decl == NULL ) return true ; if ( fn -> stdarg ) return true ; for ( t = DECL_ARGUMENTS ( fn -> decl ) ; t ; t = TREE_CHAIN ( t ) ) { if ( ! use_register_for_decl ( t ) ) return true ; if ( DECL_MODE ( t ) != SImode ) return true ; } return false ; } </s>

Return true if this function will use the stack space allocated by its caller or if we can not determine for certain that it does not .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , SP :: IntRegsRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
bool
X86TargetLowering
::
isNoopAddrSpaceCast
(
unsigned
SrcAS
,
unsigned
DestAS
)
const
{
assert
(
SrcAS
!=
DestAS
&&
"Expected different address spaces!"
)
;
const
TargetMachine
&
TM
=
getTargetMachine
(
)
;
if
(
TM
.
getPointerSize
(
SrcAS
)
!=
TM
.
getPointerSize
(
DestAS
)
)
return
false
;
return
SrcAS
<
256
&&
DestAS
<
256
;
}
</s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> static bool rx_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : case POST_INC : return true ; case MINUS : case PLUS : if ( ! REG_P ( XEXP ( addr , 0 ) ) ) return true ; addr = XEXP ( addr , 1 ) ; switch ( GET_CODE ( addr ) ) { case REG : return true ; case CONST_INT : if ( ( ( INTVAL ( addr ) & 3 ) == 0 ) && IN_RANGE ( INTVAL ( addr ) , 4 , 0xfffc ) ) return false ; return true ; case SYMBOL_REF : case LABEL_REF : return true ; case MULT : gcc_assert ( REG_P ( XEXP ( addr , 0 ) ) ) ; gcc_assert ( CONST_INT_P ( XEXP ( addr , 1 ) ) ) ; return true ; default : return true ; } case CONST_INT : case SYMBOL_REF : case LABEL_REF : case REG : return false ; default : return true ; } } </s>


<s> bool X86TTIImpl :: forceScalarizeMaskedGather ( VectorType * VTy , Align Alignment ) { unsigned NumElts = cast < FixedVectorType > ( VTy ) -> getNumElements ( ) ; return NumElts == 1 || ( ST -> hasAVX512 ( ) && ( NumElts == 2 || ( NumElts == 4 && ! ST -> hasVLX ( ) ) ) ) ; } </s>

Return true if the target forces scalarizing of llvm.masked.gather intrinsics .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_fadd : return instCombineSVEVectorFAdd ( IC , II ) ; case Intrinsic :: aarch64_sve_fsub : return instCombineSVEVectorBinOp ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1_gather_index : return instCombineLD1GatherIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_st1_scatter_index : return instCombineST1ScatterIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1 : return instCombineSVELD1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_st1 : return instCombineSVEST1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_sdiv : return instCombineSVESDIV ( IC , II ) ; case Intrinsic :: aarch64_sve_sel : return instCombineSVESel ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> bool MipsInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { MachineBasicBlock & MBB = * I . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; } if ( selectImpl ( I , CoverageInfo ) ) { return true ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
.
isDarwin
(
)
)
RegName
=
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static section * iq2000_select_section ( tree decl , int reloc ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TARGET_EMBEDDED_DATA ) { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) return readonly_data_section ; else return data_section ; } else { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) return readonly_data_section ; else return data_section ; } } </s>

Choose the section to use for DECL . RELOC is true if its value contains any relocatable expression . Some of the logic used here needs to be replicated in ENCODE_SECTION_INFO in iq2000.h so that references to these symbols are done correctly .


<s> static void rs6000_emit_nmsub ( rtx dst , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( dst ) ; rtx r ; gcc_assert ( optab_handler ( fma_optab , mode ) != CODE_FOR_nothing ) ; r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1 , m2 , r ) ; r = gen_rtx_NEG ( mode , r ) ; emit_insn ( gen_rtx_SET ( dst , r ) ) ; } </s>

Generate a FNMSUB instruction : dst = -fma ( m1 , m2 , -a ) .


<s> static bool ix86_can_eliminate ( const int from , const int to ) { if ( stack_realign_fp ) return ( ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) || ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) ) ; else return to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . If stack alignment is needed , we can only replace argument pointer with hard frame pointer , or replace frame pointer with stack pointer . Otherwise , frame pointer elimination is automatically handled and all other eliminations are valid .


"dynamic alloca in the static alloca map?"

Emit an alloca address in a register using target-specific logic .


<s> TargetPassConfig * SystemZTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SystemZPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool LEGPassConfig :: addPreISel ( ) { return false ; } </s>


<s> bool SystemZAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { SystemZInstPrinter :: printAddress ( MAI , MI -> getOperand ( OpNo ) . getReg ( ) , MCOperand :: createImm ( MI -> getOperand ( OpNo + 1 ) . getImm ( ) ) , MI -> getOperand ( OpNo + 2 ) . getReg ( ) , OS ) ; return false ; } </s>


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createX86MacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static inline unsigned long * ia64_rse_rnat_addr ( unsigned long * slot_addr ) { return ( unsigned long * ) ( ( unsigned long ) slot_addr | ( 0x3f << 3 ) ) ; } </s>

Returns the address of the RNAT slot that covers the slot at address SLOT_ADDR .


"The Delta should always be zero or negative"

"Slot for EBP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { if ( Subtarget . hasQPX ( ) && Size >= 32 && ( ! IsMemset || Size >= 64 ) && ( ! SrcAlign || SrcAlign >= 32 ) && ( ! DstAlign || DstAlign >= 32 ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return MVT :: v4f64 ; } if ( Subtarget . hasAltivec ( ) && Size >= 16 && ( ( ( ! SrcAlign || SrcAlign >= 16 ) && ( ! DstAlign || DstAlign >= 16 ) ) || ( ( IsMemset && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return MVT :: v4i32 ; } if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } setSupportsDebugEntryValues ( true ) ; initAsmInfo ( ) ; } </s>


<s> static std :: unique_ptr < SparcOperand > CreateReg ( unsigned RegNum , unsigned Kind , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < SparcOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = ( SparcOperand :: RegisterKind ) Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .

Sparc Sparc Sparc SparcOperand::RegisterKind


<s> bool X86PartialReduction :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < X86TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * EE = dyn_cast < ExtractElementInst > ( & I ) ; if ( ! EE ) continue ; bool ReduceInOneBB ; Value * Root = matchAddReduction ( * EE , ReduceInOneBB ) ; if ( ! Root ) continue ; SmallVector < Instruction * , 8 > Leaves ; collectLeaves ( Root , Leaves ) ; for ( Instruction * I : Leaves ) { if ( tryMAddReplacement ( I , ReduceInOneBB ) ) { MadeChange = true ; continue ; } if ( I != Root && trySADReplacement ( I ) ) MadeChange = true ; } } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const char * i386_pe_strip_name_encoding ( const char * str ) { if ( strncmp ( str , DLL_IMPORT_PREFIX , strlen ( DLL_IMPORT_PREFIX ) ) == 0 ) str += strlen ( DLL_IMPORT_PREFIX ) ; else if ( strncmp ( str , DLL_EXPORT_PREFIX , strlen ( DLL_EXPORT_PREFIX ) ) == 0 ) str += strlen ( DLL_EXPORT_PREFIX ) ; if ( * str == '*' ) str += 1 ; return str ; } </s>

Strip only the leading encoding , leaving the stdcall suffix and fastcall prefix if it exists .


<s> bool PPCRegisterInfo :: isCallerPreservedPhysReg ( MCRegister PhysReg , const MachineFunction & MF ) const { assert ( Register :: isPhysicalRegister ( PhysReg ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! Subtarget . is64BitELFABI ( ) && ! Subtarget . isAIXABI ( ) ) return false ; if ( PhysReg == Subtarget . getTOCPointerRegister ( ) ) return ( getReservedRegs ( MF ) . test ( PhysReg ) ) ; if ( StackPtrConst && PhysReg == Subtarget . getStackPointerRegister ( ) && ! MFI . hasVarSizedObjects ( ) && ! MFI . hasOpaqueSPAdjustment ( ) ) return true ; return false ; } </s>

Physical registers that may be modified within a function but are guaranteed to be restored before any uses .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMipsELFObjectWriter ( OS , OSType , IsLittle , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s> bool nds32_expand_strlen ( rtx result , rtx str , rtx target_char , rtx align ATTRIBUTE_UNUSED ) { rtx base_reg , backup_base_reg ; rtx ffb_result ; rtx target_char_ptr , length ; rtx loop_label , tmp ; if ( optimize_size || optimize < 3 ) return false ; gcc_assert ( MEM_P ( str ) ) ; gcc_assert ( CONST_INT_P ( target_char ) || REG_P ( target_char ) ) ; base_reg = copy_to_mode_reg ( SImode , XEXP ( str , 0 ) ) ; loop_label = gen_label_rtx ( ) ; ffb_result = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( SImode ) ; backup_base_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( backup_base_reg , base_reg ) ; emit_label ( loop_label ) ; emit_insn ( gen_unaligned_load_update_base_w ( base_reg , tmp , base_reg ) ) ; emit_insn ( gen_unspec_ffb ( ffb_result , tmp , target_char ) ) ; emit_cmp_and_jump_insns ( ffb_result , const0_rtx , EQ , NULL , SImode , 1 , loop_label ) ; target_char_ptr = expand_binop ( Pmode , add_optab , base_reg , ffb_result , NULL_RTX , 0 , OPTAB_WIDEN ) ; length = expand_binop ( Pmode , sub_optab , target_char_ptr , backup_base_reg , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_move_insn ( result , length ) ; return true ; } </s>

Auxiliary function for expand strlen pattern .


<s> std :: unique_ptr < PBQPRAConstraint > AArch64Subtarget :: getCustomPBQPConstraints ( ) const { return balanceFPOps ( ) ? std :: make_unique < A57ChainingConstraint > ( ) : nullptr ; } </s>

Return PBQPConstraint ( s ) for the target .


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op_true , rtx op_false , rtx cond , rtx cc_op0 , rtx cc_op1 ) { machine_mode dest_mode = GET_MODE ( dest ) ; machine_mode mask_mode = GET_MODE ( cc_op0 ) ; enum rtx_code rcode = GET_CODE ( cond ) ; rtx mask ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return 0 ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return 0 ; break ; case GE : case LE : if ( GET_MODE_CLASS ( mask_mode ) == MODE_VECTOR_INT ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; case GTU : case GEU : case LTU : case LEU : if ( rcode == GEU || rcode == LEU ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return 0 ; if ( mask_mode != dest_mode ) mask = simplify_gen_subreg ( dest_mode , mask , mask_mode , 0 ) ; if ( invert_move ) std :: swap ( op_true , op_false ) ; if ( GET_MODE_CLASS ( dest_mode ) == MODE_VECTOR_INT && ( GET_CODE ( op_true ) == CONST_VECTOR || GET_CODE ( op_false ) == CONST_VECTOR ) ) { rtx constant_0 = CONST0_RTX ( dest_mode ) ; rtx constant_m1 = CONSTM1_RTX ( dest_mode ) ; if ( op_true == constant_m1 && op_false == constant_0 ) { emit_move_insn ( dest , mask ) ; return 1 ; } else if ( op_true == constant_0 && op_false == constant_m1 ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_NOT ( dest_mode , mask ) ) ) ; return 1 ; } if ( op_true == constant_m1 ) op_true = mask ; if ( op_false == constant_0 ) op_false = mask ; } if ( ! REG_P ( op_true ) && ! SUBREG_P ( op_true ) ) op_true = force_reg ( dest_mode , op_true ) ; if ( ! REG_P ( op_false ) && ! SUBREG_P ( op_false ) ) op_false = force_reg ( dest_mode , op_false ) ; rtx tmp = gen_rtx_IOR ( dest_mode , gen_rtx_AND ( dest_mode , gen_rtx_NOT ( dest_mode , mask ) , op_false ) , gen_rtx_AND ( dest_mode , mask , op_true ) ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s> static inline bool is_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , "interrupt" ) ; } </s>

Returns true if the provided function has the `` interrupt '' attribute .


<s> static const char * ix86_get_multilib_abi_name ( void ) { if ( ! ( TARGET_64BIT_P ( ix86_isa_flags ) ) ) return "i386" ; else if ( TARGET_X32_P ( ix86_isa_flags ) ) return "x32" ; else return "x86_64" ; } </s>

This hook returns name of multilib ABI .


"getBranchTarget21OpValueMM expects only expressions or immediates"

getBranchTarget21OpValueMM - Return binary encoding of the branch target operand for microMIPS .


<s> const MipsInstrInfo * MipsInstrInfo :: create ( MipsSubtarget & STI ) { return llvm :: createMipsSEInstrInfo ( STI ) ; } </s>


<s> void crx_init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libfunc ATTRIBUTE_UNUSED ) { tree param , next_param ; cum -> ints = 0 ; for ( param = ( fntype ) ? TYPE_ARG_TYPES ( fntype ) : 0 ; param != ( tree ) 0 ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( next_param == ( tree ) 0 && TREE_VALUE ( param ) != void_type_node ) { cum -> ints = - 1 ; return ; } } } </s>

Implements the macro INIT_CUMULATIVE_ARGS defined in crx.h .


<s> static inline tree def_builtin_const ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin ( mask , name , tcode , code ) ; if ( decl ) TREE_READONLY ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . const_p = true ; return decl ; } </s>

Likewise , but also marks the function as `` const '' .


<s> void rs6000_split_v4si_init ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; if ( REG_P ( dest ) || SUBREG_P ( dest ) ) { int d_regno = regno_or_subregno ( dest ) ; rtx scalar1 = operands [ 1 ] ; rtx scalar2 = operands [ 2 ] ; rtx scalar3 = operands [ 3 ] ; rtx scalar4 = operands [ 4 ] ; rtx tmp1 = operands [ 5 ] ; rtx tmp2 = operands [ 6 ] ; if ( BYTES_BIG_ENDIAN ) { rtx di_lo = gen_rtx_REG ( DImode , d_regno ) ; rtx di_hi = gen_rtx_REG ( DImode , d_regno + 1 ) ; rs6000_split_v4si_init_di_reg ( di_lo , scalar1 , scalar2 , tmp1 ) ; rs6000_split_v4si_init_di_reg ( di_hi , scalar3 , scalar4 , tmp2 ) ; } else { rtx di_lo = gen_rtx_REG ( DImode , d_regno + 1 ) ; rtx di_hi = gen_rtx_REG ( DImode , d_regno ) ; gcc_assert ( ! VECTOR_ELT_ORDER_BIG ) ; rs6000_split_v4si_init_di_reg ( di_lo , scalar4 , scalar3 , tmp1 ) ; rs6000_split_v4si_init_di_reg ( di_hi , scalar2 , scalar1 , tmp2 ) ; } return ; } else gcc_unreachable ( ) ; } </s>


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static unsigned int mips_get_compress_on_flags ( tree attributes ) { unsigned int flags = 0 ; if ( lookup_attribute ( "mips16" , attributes ) != NULL ) flags |= MASK_MIPS16 ; if ( lookup_attribute ( "micromips" , attributes ) != NULL ) flags |= MASK_MICROMIPS ; return flags ; } </s>

Return the set of compression modes that are explicitly required by the attributes in ATTRIBUTES .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 AT&T-Style Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool SystemZInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Pred , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! STI . hasLoadStoreOnCond ( ) ) return false ; if ( Pred . size ( ) != 2 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && SystemZ :: GRX32BitRegClass . hasSubClassEq ( RC ) ) || SystemZ :: GR32BitRegClass . hasSubClassEq ( RC ) || SystemZ :: GR64BitRegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static bool quad_aligned_load_p ( swap_web_entry * insn_entry , rtx_insn * insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; return ( ( REG_P ( base_reg ) || rs6000_sum_of_two_registers_p ( base_reg ) ) && MEM_ALIGN ( mem ) >= 128 ) ? true : false ; } </s>

Return TRUE if INSN represents a swap of a swapped load from memory and the memory address is quad-word aligned .


<s> static int rs6000_loop_align_max_skip ( rtx_insn * label ) { return ( 1 << rs6000_loop_align ( label ) ) - 1 ; } </s>


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( Subtarget -> isTargetNaCl ( ) || ! EnableARMAEABIFunctions || ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> unsigned X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const X86FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> static rtx_insn * rs6000_emit_allocate_stack_1 ( HOST_WIDE_INT size_int , rtx orig_sp ) { rtx_insn * insn ; rtx size_rtx = GEN_INT ( - size_int ) ; if ( size_int > 32767 ) { rtx tmp_reg = gen_rtx_REG ( Pmode , 0 ) ; if ( get_last_insn ( ) == NULL_RTX ) emit_note ( NOTE_INSN_DELETED ) ; insn = emit_move_insn ( tmp_reg , size_rtx ) ; try_split ( PATTERN ( insn ) , insn , 0 ) ; size_rtx = tmp_reg ; } if ( TARGET_32BIT ) insn = emit_insn ( gen_movsi_update_stack ( stack_pointer_rtx , stack_pointer_rtx , size_rtx , orig_sp ) ) ; else insn = emit_insn ( gen_movdi_update_stack ( stack_pointer_rtx , stack_pointer_rtx , size_rtx , orig_sp ) ) ; rtx par = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( par ) == PARALLEL ) ; rtx set = XVECEXP ( par , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; rtx mem = SET_DEST ( set ) ; gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } return insn ; } </s>

Allocate SIZE_INT bytes on the stack using a store with update style insn and set the appropriate attributes for the generated insn . Return the first insn which adjusts the stack pointer or the last insn before the stack adjustment loop . SIZE_INT is used to create the CFI note for the allocation . SIZE_RTX is an rtx containing the size of the adjustment . Note that since stacks grow to lower addresses its runtime value is -SIZE_INT . ORIG_SP contains the backchain value that must be stored at * sp .


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , machine_mode omode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = omode ; HOST_WIDE_INT bytes , words ; rtx arg ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) arg = NULL ; else if ( cum -> bnd_regno <= LAST_BND_REG ) arg = gen_rtx_REG ( BNDmode , cum -> bnd_regno ) ; else arg = GEN_INT ( cum -> bnd_regno - LAST_BND_REG - 1 ) ; return arg ; } if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else arg = function_arg_64 ( cum , mode , omode , type , named ) ; } else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ; return arg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .