<s>
bool
MipsSEDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Base
,
Offset
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_R
:
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_ZC
:
if
(
Subtarget
->
inMicroMipsMode
(
)
)
{
if
(
selectAddrRegImm12
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
Subtarget
->
hasMips32r6
(
)
)
{
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool X86CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const X86TargetLowering & TLI = * getTLI < X86TargetLowering > ( ) ; LLVMContext & Context = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( OrigArg . Ty -> isVoidTy ( ) ) return true ; EVT VT = SplitVTs [ 0 ] ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return true ; } SmallVector < unsigned , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; SplitRegs . push_back ( Info . Reg ) ; } PerformArgSplit ( SplitRegs ) ; return true ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> bool mips_expand_block_move ( rtx dest , rtx src , rtx length ) { if ( GET_CODE ( length ) == CONST_INT ) { if ( INTVAL ( length ) <= 2 * MAX_MOVE_BYTES ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) ) ; return true ; } } return false ; } </s>

Expand a movmemsi instruction , which copies LENGTH bytes from memory reference SRC to memory reference DEST .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"IA64 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> EVT PPCTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return new MachObjectWriter ( OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> TargetLowering :: ConstraintWeight LanaiTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & Info , const char * Constraint ) const { ConstraintWeight Weight = CW_Invalid ; Value * CallOperandVal = Info . CallOperandVal ; if ( CallOperandVal == nullptr ) return CW_Default ; switch ( * Constraint ) { case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ; break ; } return Weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static bool aarch64_pass_by_reference_1 ( CUMULATIVE_ARGS * pcum , const function_arg_info & arg ) { HOST_WIDE_INT size ; machine_mode dummymode ; int nregs ; if ( arg . mode == BLKmode && arg . type ) size = int_size_in_bytes ( arg . type ) ; else size = GET_MODE_SIZE ( arg . mode ) . to_constant ( ) ; if ( arg . aggregate_type_p ( ) ) size = int_size_in_bytes ( arg . type ) ; if ( size < 0 ) return true ; if ( aarch64_vfp_is_call_or_return_candidate ( arg . mode , arg . type , & dummymode , & nregs , NULL , ! pcum || pcum -> silent_p ) ) return false ; return size > 2 * UNITS_PER_WORD ; } </s>

Subroutine of aarch64_pass_by_reference for arguments that are not passed in SVE registers .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2Base
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2Base
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
case
CallingConv
::
SwiftTail
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
report_fatal_error
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
case
CallingConv
::
CFGuard_Check
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_Win32_CFGuard_Check
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM
ARM
ARM


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegClass . begin ( ) , EReg = Mips :: CPU64RegsRegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPCtrl ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool isConditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == AArch64 :: Bcc && Inst . getOperand ( 0 ) . getImm ( ) == A64CC :: AL ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> static const __EIT_entry * search_EIT_table ( const __EIT_entry * table , int nrec , _uw return_address ) { _uw next_fn ; _uw this_fn ; int n , left , right ; if ( nrec == 0 ) return ( __EIT_entry * ) 0 ; left = 0 ; right = nrec - 1 ; while ( 1 ) { n = ( left + right ) / 2 ; this_fn = selfrel_offset31 ( & table [ n ] . fnoffset ) ; if ( n != nrec - 1 ) next_fn = selfrel_offset31 ( & table [ n + 1 ] . fnoffset ) - 1 ; else next_fn = ( _uw ) 0 - 1 ; if ( return_address < this_fn ) { if ( n == left ) return ( __EIT_entry * ) 0 ; right = n - 1 ; } else if ( return_address <= next_fn ) return & table [ n ] ; else left = n + 1 ; } } </s>

Perform a binary search for RETURN_ADDRESS in TABLE . The table contains NREC entries .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAArch64ELFObjectWriter ( OS , OSABI , IsLittleEndian ) ; } </s>


<s> int typemap_cmp ( const void * key , const void * entry ) { return strcmp ( ( const char * ) key , ( ( const typemap * ) entry ) -> key ) ; } </s>

Comparator for bsearch on the type map .


<s> bool aarch64_sve_scalar_inc_dec_immediate_p ( rtx x ) { poly_int64 value ; return ( poly_int_rtx_p ( x , & value ) && ( aarch64_sve_cnt_immediate_p ( value ) || aarch64_sve_cnt_immediate_p ( - value ) ) ) ; } </s>

Return true if we can add X using a single SVE INC or DEC instruction .


<s> unsigned Mips16InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool IA64TargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createIA64BundlingPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
void
arm_print_asm_arch_directives
(
)
{
const
arch_option
*
arch
=
arm_parse_arch_option_name
(
all_architectures
,
"-march"
,
arm_active_target
.
arch_name
)
;
auto_sbitmap
opt_bits
(
isa_num_bits
)
;
gcc_assert
(
arch
)
;
asm_fprintf
(
asm_out_file
,
"\t.arch %s\n"
,
arm_active_target
.
arch_name
)
;
arm_last_printed_arch_string
=
arm_active_target
.
arch_name
;
if
(
!
arch
->
common
.
extensions
)
return
;
for
(
const
struct
cpu_arch_extension
*
opt
=
arch
->
common
.
extensions
;
opt
->
name
!=
;
opt
++
)
{
if
(
!
opt
->
remove
)
{
arm_initialize_isa
(
opt_bits
,
opt
->
isa_bits
)
;
if
(
bitmap_subset_p
(
opt_bits
,
arm_active_target
.
isa
)
&&
!
bitmap_subset_p
(
opt_bits
,
isa_all_fpubits
)
)
asm_fprintf
(
asm_out_file
,
"\t.arch_extension %s\n"
,
opt
->
name
)
;
}
}
}
</s>

Print .arch and .arch_extension directives corresponding to the current architecture configuration .

arm
"-march"
"\t.arch %s\n"
"\t.arch_extension %s\n"


<s>
static
void
rs6000_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
if
(
!
cfun
->
is_thunk
)
rs6000_output_savres_externs
(
file
)
;
if
(
DEFAULT_ABI
==
ABI_ELFv2
&&
cfun
->
machine
->
r2_setup_needed
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
fprintf
(
file
,
"0:\taddis 2,12,.TOC.-0b@ha\n"
)
;
fprintf
(
file
,
"\taddi 2,2,.TOC.-0b@l\n"
)
;
fputs
(
"\t.localentry\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
",.-"
,
file
)
;
assemble_name
(
file
,
name
)
;
fputs
(
"\n"
,
file
)
;
}
if
(
TARGET_PROFILE_KERNEL
&&
crtl
->
profile
)
{
gcc_assert
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
;
gcc_assert
(
!
TARGET_32BIT
)
;
asm_fprintf
(
file
,
"\tmflr %s\n"
,
reg_names
[
0
]
)
;
asm_fprintf
(
file
,
"\tstd %s,16(%s)\n"
,
reg_names
[
0
]
,
reg_names
[
1
]
)
;
if
(
DEFAULT_ABI
!=
ABI_ELFv2
&&
cfun
->
static_chain_decl
!=
)
{
asm_fprintf
(
file
,
"\tstd %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
asm_fprintf
(
file
,
"\tld %s,24(%s)\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
,
reg_names
[
1
]
)
;
}
else
fprintf
(
file
,
"\tbl %s\n"
,
RS6000_MCOUNT
)
;
}
rs6000_pic_labelno
++
;
}
</s>


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return TargetLowering :: shouldFormOverflowOp ( Opcode , VT , true ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static bool canonicalize_vector_int_perm ( const struct expand_vec_perm_d * d , struct expand_vec_perm_d * nd ) { int i ; machine_mode mode = VOIDmode ; switch ( d -> vmode ) { case E_V8QImode : mode = V4HImode ; break ; case E_V16QImode : mode = V8HImode ; break ; case E_V32QImode : mode = V16HImode ; break ; case E_V64QImode : mode = V32HImode ; break ; case E_V4HImode : mode = V2SImode ; break ; case E_V8HImode : mode = V4SImode ; break ; case E_V16HImode : mode = V8SImode ; break ; case E_V32HImode : mode = V16SImode ; break ; case E_V4SImode : mode = V2DImode ; break ; case E_V8SImode : mode = V4DImode ; break ; case E_V16SImode : mode = V8DImode ; break ; default : return false ; } for ( i = 0 ; i < d -> nelt ; i += 2 ) if ( ( d -> perm [ i ] & 1 ) || d -> perm [ i + 1 ] != d -> perm [ i ] + 1 ) return false ; nd -> vmode = mode ; nd -> nelt = d -> nelt / 2 ; for ( i = 0 ; i < nd -> nelt ; i ++ ) nd -> perm [ i ] = d -> perm [ 2 * i ] / 2 ; if ( GET_MODE_INNER ( mode ) != DImode ) canonicalize_vector_int_perm ( nd , nd ) ; if ( nd != d ) { nd -> one_operand_p = d -> one_operand_p ; nd -> testing_p = d -> testing_p ; if ( d -> op0 == d -> op1 ) nd -> op0 = nd -> op1 = gen_lowpart ( nd -> vmode , d -> op0 ) ; else { nd -> op0 = gen_lowpart ( nd -> vmode , d -> op0 ) ; nd -> op1 = gen_lowpart ( nd -> vmode , d -> op1 ) ; } if ( d -> testing_p ) nd -> target = gen_raw_REG ( nd -> vmode , LAST_VIRTUAL_REGISTER + 1 ) ; else nd -> target = gen_reg_rtx ( nd -> vmode ) ; } return true ; } </s>

For V * [ QHS ] Imode permutations , check if the same permutation ca n't be performed in a 2x , 4x or 8x wider inner mode .


<s> static void free_state_stack ( struct unw_reg_state * rs ) { struct unw_reg_state * p , * next ; for ( p = rs -> next ; p != NULL ; p = next ) { next = p -> next ; free_reg_state ( p ) ; } rs -> next = NULL ; } </s>

Free all stacked register states ( but not RS itself ) .


<s> MVT :: SimpleValueType PPCTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .

PowerPC MVT::SimpleValueType PPC MVT::i32


<s> bool X86TargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && Subtarget . hasSSE2 ( ) ) { PM . add ( createSSEDomainFixPass ( ) ) ; return true ; } return false ; } </s>


<s> bool FalkorHWPFFix :: runOnMachineFunction ( MachineFunction & Fn ) { auto & ST = Fn . getSubtarget < AArch64Subtarget > ( ) ; if ( ST . getProcFamily ( ) != AArch64Subtarget :: Falkor ) return false ; if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; Modified = false ; for ( MachineLoop * I : LI ) for ( MachineLoop * L : depth_first ( I ) ) if ( L -> isInnermost ( ) ) runOnLoop ( * L , Fn ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned OpId ; switch ( Inst . getOpcode ( ) ) { default : OpId = 0 ; break ; case ARM :: MVE_WLSTP_8 : case ARM :: MVE_WLSTP_16 : case ARM :: MVE_WLSTP_32 : case ARM :: MVE_WLSTP_64 : case ARM :: t2WLS : case ARM :: MVE_LETP : case ARM :: t2LEUpdate : OpId = 2 ; break ; case ARM :: t2LE : OpId = 1 ; break ; } if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( OpId ) . getImm ( ) + 4 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> void MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsExpandPseudoPass ( TM ) ) ; } </s>


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; add_int_reg_note ( x , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> void ARMAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { const bool WasThumb = isThumb ( StartInfo ) ; if ( ! EndInfo || WasThumb != isThumb ( * EndInfo ) ) { OutStreamer -> emitAssemblerFlag ( WasThumb ? MCAF_Code16 : MCAF_Code32 ) ; } } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) { } </s>


<s> bool SparcAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".byte" ) return parseDirectiveWord ( 1 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".half" ) return parseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".nword" ) return parseDirectiveWord ( is64Bit ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( is64Bit ( ) && IDVal == ".xword" ) return parseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".register" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".proc" ) { Parser . eatToEndOfStatement ( ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"Atomic inst not expanded when it should be?"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoRedZone ) ) { const X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( ! X86FI || X86FI -> getUsesRedZone ( ) ) return false ; } if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> bool AArch64TargetLowering :: enableAggressiveFMAFusion ( EVT VT ) const { return Subtarget -> hasAggressiveFMA ( ) && VT . isFloatingPoint ( ) ; } </s>

Return true if target always benefits from combining into FMA for a given value type .


<s> static bool expand_vec_perm_movs ( struct expand_vec_perm_d * d ) { machine_mode vmode = d -> vmode ; unsigned i , nelt = d -> nelt ; rtx x ; if ( d -> one_operand_p ) return false ; if ( ! ( TARGET_SSE && vmode == V4SFmode ) && ! ( TARGET_MMX_WITH_SSE && vmode == V2SFmode ) && ! ( TARGET_SSE2 && vmode == V2DFmode ) ) return false ; if ( d -> perm [ 0 ] != nelt && d -> perm [ 0 ] != 0 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i + nelt - d -> perm [ 0 ] ) return false ; if ( d -> testing_p ) return true ; if ( d -> perm [ 0 ] == nelt ) x = gen_rtx_VEC_MERGE ( vmode , d -> op1 , d -> op0 , GEN_INT ( 1 ) ) ; else x = gen_rtx_VEC_MERGE ( vmode , d -> op0 , d -> op1 , GEN_INT ( 1 ) ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement D using movss or movsd .


<s> void i386_pe_seh_unwind_emit ( FILE * asm_out_file , rtx_insn * insn ) { rtx note , pat ; bool handled_one = false ; struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( seh == NULL ) return ; if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , 1 ) ) { switch ( REG_NOTE_KIND ( note ) ) { case REG_FRAME_RELATED_EXPR : pat = XEXP ( note , 0 ) ; goto found ; case REG_CFA_DEF_CFA : case REG_CFA_EXPRESSION : gcc_unreachable ( ) ; break ; case REG_CFA_REGISTER : gcc_unreachable ( ) ; case REG_CFA_ADJUST_CFA : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; } seh_cfa_adjust_cfa ( asm_out_file , seh , pat ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) pat = single_set ( insn ) ; seh_cfa_offset ( asm_out_file , seh , pat ) ; handled_one = true ; break ; default : break ; } } if ( handled_one ) return ; pat = PATTERN ( insn ) ; found : seh_frame_related_expr ( asm_out_file , seh , pat ) ; } </s>

This function looks at a single insn and emits any SEH directives required for unwind of this insn .


<s> bool isLegalMaskedLoad ( Type * DataType , MaybeAlign Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked load .


<s> MachineInstr * DLXInstrInfo :: optimizeSelect ( MachineInstr & MI , SmallPtrSetImpl < MachineInstr * > & SeenMIs , bool PreferFalse ) const { return nullptr ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) . optForSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>


<s> SDValue SparcTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: BITCAST : return PerformBITCASTCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static void rs6000_assemble_visibility ( tree decl , int vis ) { if ( DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS && TREE_CODE ( decl ) == FUNCTION_DECL ) { static const char * const visibility_types [ ] = { NULL , "internal" , "hidden" , "protected" } ; const char * name , * type ; name = ( ( * targetm . strip_name_encoding ) ( IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ) ; type = visibility_types [ vis ] ; fprintf ( asm_out_file , "\t.%s\t%s\n" , type , name ) ; fprintf ( asm_out_file , "\t.%s\t.%s\n" , type , name ) ; } else default_assemble_visibility ( decl , vis ) ; } </s>

Emit an assembler directive to set symbol visibility for DECL to VISIBILITY_TYPE .


"emitPrologue doesn't support framepointer-less functions"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void aarch64_update_cpp_builtins ( cpp_reader * pfile ) { aarch64_def_or_undef ( flag_unsafe_math_optimizations , "__ARM_FP_FAST" , pfile ) ; builtin_define_with_int_value ( "__ARM_ARCH" , aarch64_architecture_version ) ; builtin_define_with_int_value ( "__ARM_SIZEOF_MINIMAL_ENUM" , flag_short_enums ? 1 : 4 ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__AARCH64EB__" , pfile ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__ARM_BIG_ENDIAN" , pfile ) ; aarch64_def_or_undef ( ! TARGET_BIG_END , "__AARCH64EL__" , pfile ) ; aarch64_def_or_undef ( TARGET_FLOAT , "__ARM_FEATURE_FMA" , pfile ) ; if ( TARGET_FLOAT || TARGET_SIMD ) { builtin_define_with_int_value ( "__ARM_FP" , 0x0E ) ; builtin_define ( "__ARM_FP16_FORMAT_IEEE" ) ; builtin_define ( "__ARM_FP16_ARGS" ) ; } else cpp_undef ( pfile , "__ARM_FP" ) ; aarch64_def_or_undef ( TARGET_FP_F16INST , "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_F16INST , "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_FEATURE_NUMERIC_MAXMIN" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_NEON" , pfile ) ; aarch64_def_or_undef ( TARGET_CRC32 , "__ARM_FEATURE_CRC32" , pfile ) ; aarch64_def_or_undef ( TARGET_DOTPROD , "__ARM_FEATURE_DOTPROD" , pfile ) ; aarch64_def_or_undef ( TARGET_COMPLEX , "__ARM_FEATURE_COMPLEX" , pfile ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_TINY__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_SMALL__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_LARGE__" ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : builtin_define ( "__AARCH64_CMODEL_TINY__" ) ; break ; case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : builtin_define ( "__AARCH64_CMODEL_SMALL__" ) ; break ; case AARCH64_CMODEL_LARGE : builtin_define ( "__AARCH64_CMODEL_LARGE__" ) ; break ; default : break ; } aarch64_def_or_undef ( TARGET_ILP32 , "_ILP32" , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , "__ILP32__" , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , "__ARM_FEATURE_CRYPTO" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , "__ARM_FEATURE_QRDMX" , pfile ) ; aarch64_def_or_undef ( TARGET_SVE , "__ARM_FEATURE_SVE" , pfile ) ; cpp_undef ( pfile , "__ARM_FEATURE_SVE_BITS" ) ; if ( TARGET_SVE ) { int bits ; if ( ! BITS_PER_SVE_VECTOR . is_constant ( & bits ) ) bits = 0 ; builtin_define_with_int_value ( "__ARM_FEATURE_SVE_BITS" , bits ) ; } aarch64_def_or_undef ( TARGET_LSE , "__ARM_FEATURE_ATOMICS" , pfile ) ; aarch64_def_or_undef ( TARGET_AES , "__ARM_FEATURE_AES" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA2 , "__ARM_FEATURE_SHA2" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , "__ARM_FEATURE_SHA3" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , "__ARM_FEATURE_SHA512" , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , "__ARM_FEATURE_SM3" , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , "__ARM_FEATURE_SM4" , pfile ) ; aarch64_def_or_undef ( TARGET_F16FML , "__ARM_FEATURE_FP16_FML" , pfile ) ; cpp_undef ( pfile , "__FLT_EVAL_METHOD__" ) ; builtin_define_with_int_value ( "__FLT_EVAL_METHOD__" , c_flt_eval_method ( true ) ) ; cpp_undef ( pfile , "__FLT_EVAL_METHOD_C99__" ) ; builtin_define_with_int_value ( "__FLT_EVAL_METHOD_C99__" , c_flt_eval_method ( false ) ) ; } </s>

Undefine/redefine macros that depend on the current backend state and may need to change when a target pragma modifies the backend state .


<s> const Cpu0Subtarget * getSubtargetImpl ( const llvm :: Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"insertBranch must not be told to insert a fallthrough"

"VE branch conditions should have three component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool isToken ( ) const override { return Kind == KindTy :: Token ; } </s>


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
while
(
!
vec_safe_is_empty
(
branch_islands
)
)
{
branch_island
*
bi
=
&
branch_islands
->
last
(
)
;
const
char
*
label
=
IDENTIFIER_POINTER
(
bi
->
label_name
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
bi
->
function_name
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
if
(
flag_pic
)
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\n\tlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
branch_islands
->
pop
(
)
;
}
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2Base
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2Base
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
report_fatal_error
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
case
CallingConv
::
CFGuard_Check
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_Win32_CFGuard_Check
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
void
ARMConstantIslands
::
verify
(
)
{
BBInfoVector
&
BBInfo
=
BBUtils
->
getBBInfo
(
)
;
assert
(
std
::
is_sorted
(
MF
->
begin
(
)
,
MF
->
end
(
)
,
[
&
BBInfo
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> int insvdi_rshift_rlwimi_p ( rtx sizeop , rtx startop , rtx shiftop ) { if ( INTVAL ( startop ) < 64 && INTVAL ( startop ) > 32 && ( INTVAL ( sizeop ) + INTVAL ( startop ) < 64 ) && ( INTVAL ( sizeop ) + INTVAL ( startop ) > 33 ) && ( INTVAL ( sizeop ) + INTVAL ( startop ) + INTVAL ( shiftop ) < 96 ) && ( INTVAL ( sizeop ) + INTVAL ( startop ) + INTVAL ( shiftop ) >= 64 ) && ( 64 - ( INTVAL ( shiftop ) & 63 ) ) >= INTVAL ( sizeop ) ) return 1 ; return 0 ; } </s>

Return 1 if operands will generate a valid arguments to rlwimiinstruction for insert with right shift in 64-bit mode . The mask maynot start on the first bit or stop on the last bit because wrap-aroundeffects of instruction do not correspond to semantics of RTL insn .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createShadowCallStackPass ( ) ) ; addPass ( createX86IndirectBranchTrackingPass ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const X86_64GNULDBackend & getTarget ( ) const { return m_Target ; } </s>

getTarget - Return the target machine this machine code is compiled with


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
)
return
TargetInstrInfoImpl
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
TOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
true
,
false
,
false
,
Reg0IsDead
)
.
addReg
(
Reg2
,
false
,
false
,
Reg2IsKill
)
.
addReg
(
Reg1
,
false
,
false
,
Reg1IsKill
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { if ( NoFusing ) return NULL ; unsigned Alignment = 0 ; if ( LoadMI -> hasOneMemOperand ( ) ) Alignment = LoadMI -> memoperands_begin ( ) -> getAlignment ( ) ; else if ( LoadMI -> getOpcode ( ) == X86 :: V_SET0 || LoadMI -> getOpcode ( ) == X86 :: V_SETALLONES ) Alignment = 16 ; if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri32 ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return NULL ; SmallVector < MachineOperand , X86AddrNumOperands > MOs ; if ( LoadMI -> getOpcode ( ) == X86 :: V_SET0 || LoadMI -> getOpcode ( ) == X86 :: V_SETALLONES ) { unsigned PICBase = 0 ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) PICBase = X86 :: RIP ; else return false ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const VectorType * Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , 4 ) ; Constant * C = LoadMI -> getOpcode ( ) == X86 :: V_SET0 ? Constant :: getNullValue ( Ty ) : Constant :: getAllOnesValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , 16 ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( 1 ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( 0 , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , 0 ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( 0 , false ) ) ; } else { unsigned NumOps = LoadMI -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - X86AddrNumOperands ; i != NumOps ; ++ i ) MOs . push_back ( LoadMI -> getOperand ( i ) ) ; } return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MOs , Alignment ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


Return an array that contains the direct target flag values and their names .


<s> static const char * rs6000_get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , rs6000_get_some_local_dynamic_name_1 , 0 ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ; } </s>

Locate some local-dynamic symbol still in use by this function so that we can print its name in some tls_ld pattern .


"The Prefetches vector should contain at least a value if "

"Unexpected change in X86 operand offset order."

runOnMachineFunction - Emit the function body .


<s> unsigned LoongArchAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { LoongArchOperand & Op = static_cast < LoongArchOperand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; if ( LoongArchMCRegisterClasses [ LoongArch :: FPR32RegClassID ] . contains ( Reg ) && Kind == MCK_FPR64 ) { Op . setReg ( convertFPR32ToFPR64 ( Reg ) ) ; return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

LoongArch LoongArch LoongArch LoongArch LoongArch LoongArch::FPR32RegClassID


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


<s>
virtual
const
ARMBaseInstrInfo
*
getInstrInfo
(
)
const
{
llvm_unreachable
(
"getInstrInfo not implemented"
)
;
}
</s>


<s> void aarch64_expand_subvti ( rtx op0 , rtx low_dest , rtx low_in1 , rtx low_in2 , rtx high_dest , rtx high_in1 , rtx high_in2 , bool unsigned_p ) { if ( low_in2 == const0_rtx ) { low_dest = low_in1 ; high_in2 = force_reg ( DImode , high_in2 ) ; if ( unsigned_p ) emit_insn ( gen_subdi3_compare1 ( high_dest , high_in1 , high_in2 ) ) ; else emit_insn ( gen_subvdi_insn ( high_dest , high_in1 , high_in2 ) ) ; } else { if ( aarch64_plus_immediate ( low_in2 , DImode ) ) emit_insn ( gen_subdi3_compare1_imm ( low_dest , low_in1 , low_in2 , GEN_INT ( - INTVAL ( low_in2 ) ) ) ) ; else { low_in2 = force_reg ( DImode , low_in2 ) ; emit_insn ( gen_subdi3_compare1 ( low_dest , low_in1 , low_in2 ) ) ; } high_in2 = force_reg ( DImode , high_in2 ) ; if ( unsigned_p ) emit_insn ( gen_usubdi3_carryinC ( high_dest , high_in1 , high_in2 ) ) ; else emit_insn ( gen_subdi3_carryinV ( high_dest , high_in1 , high_in2 ) ) ; } emit_move_insn ( gen_lowpart ( DImode , op0 ) , low_dest ) ; emit_move_insn ( gen_highpart ( DImode , op0 ) , high_dest ) ; } </s>

Generate RTL for 128-bit ( TImode ) subtraction with overflow . OP0 represents the TImode destination operand 0 LOW_DEST represents the low half ( DImode ) of TImode operand 0 LOW_IN1 represents the low half ( DImode ) of TImode operand 1 LOW_IN2 represents the low half ( DImode ) of TImode operand 2 HIGH_DEST represents the high half ( DImode ) of TImode operand 0 HIGH_IN1 represents the high half ( DImode ) of TImode operand 1 HIGH_IN2 represents the high half ( DImode ) of TImode operand 2 UNSIGNED_P is true if the operation is being performed on unsigned values .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: VSELECT : return PerformVSelectCombine ( N , DCI . DAG ) ; case ISD :: SIGN_EXTEND : return PerformSignExtendCombine ( N , DCI . DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case AArch64ISD :: NEON_VDUPLANE : return CombineVLDDUP ( N , DCI ) ; case AArch64ISD :: NEON_LD2DUP : case AArch64ISD :: NEON_LD3DUP : case AArch64ISD :: NEON_LD4DUP : return CombineBaseUpdate ( N , DCI ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : case Intrinsic :: aarch64_neon_vld1x2 : case Intrinsic :: aarch64_neon_vld1x3 : case Intrinsic :: aarch64_neon_vld1x4 : case Intrinsic :: aarch64_neon_vst1x2 : case Intrinsic :: aarch64_neon_vst1x3 : case Intrinsic :: aarch64_neon_vst1x4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : return CombineBaseUpdate ( N , DCI ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x01000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> virtual bool check ( function_checker & ) const { return true ; } </s>

Perform semantic checks on the call . Return true if the call is valid , otherwise report a suitable error .


<s> insn_code function_expander :: direct_optab_handler ( optab op , unsigned int suffix_i ) { return :: direct_optab_handler ( op , vector_mode ( suffix_i ) ) ; } </s>

Return the handler of direct optab OP for type suffix SUFFIX_I .


<s> static rtx rs6000_emit_vector_compare ( enum rtx_code rcode , rtx op0 , rtx op1 , machine_mode dmode ) { rtx mask ; bool swap_operands = false ; bool try_again = false ; gcc_assert ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( dmode ) ) ; gcc_assert ( GET_MODE ( op0 ) == GET_MODE ( op1 ) ) ; mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; switch ( rcode ) { case LT : rcode = GT ; swap_operands = true ; try_again = true ; break ; case LTU : rcode = GTU ; swap_operands = true ; try_again = true ; break ; case NE : case UNLE : case UNLT : case UNGE : case UNGT : { enum rtx_code rev_code ; enum insn_code nor_code ; rtx mask2 ; rev_code = reverse_condition_maybe_unordered ( rcode ) ; if ( rev_code == UNKNOWN ) return NULL_RTX ; nor_code = optab_handler ( one_cmpl_optab , dmode ) ; if ( nor_code == CODE_FOR_nothing ) return NULL_RTX ; mask2 = rs6000_emit_vector_compare ( rev_code , op0 , op1 , dmode ) ; if ( ! mask2 ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( nor_code ) ( mask , mask2 ) ) ; return mask ; } break ; case GE : case GEU : case LE : case LEU : { rtx c_rtx , eq_rtx ; enum insn_code ior_code ; enum rtx_code new_code ; switch ( rcode ) { case GE : new_code = GT ; break ; case GEU : new_code = GTU ; break ; case LE : new_code = LT ; break ; case LEU : new_code = LTU ; break ; default : gcc_unreachable ( ) ; } ior_code = optab_handler ( ior_optab , dmode ) ; if ( ior_code == CODE_FOR_nothing ) return NULL_RTX ; c_rtx = rs6000_emit_vector_compare ( new_code , op0 , op1 , dmode ) ; if ( ! c_rtx ) return NULL_RTX ; eq_rtx = rs6000_emit_vector_compare ( EQ , op0 , op1 , dmode ) ; if ( ! eq_rtx ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( ior_code ) ( mask , c_rtx , eq_rtx ) ) ; return mask ; } break ; default : return NULL_RTX ; } if ( try_again ) { if ( swap_operands ) std :: swap ( op0 , op1 ) ; mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; } return NULL_RTX ; } </s>

Emit vector compare for operands OP0 and OP1 using code RCODE . DMODE is expected destination mode . This is a recursive function .


<s> bool AArch64TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { return ExtVal . getValueType ( ) . isScalableVector ( ) ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> int registers_ok_for_quad_peep ( rtx reg1 , rtx reg2 ) { if ( ! REG_P ( reg1 ) || ! REG_P ( reg2 ) ) return 0 ; if ( ! FP_REGNO_P ( REGNO ( reg1 ) ) || ! FP_REGNO_P ( REGNO ( reg2 ) ) ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) == REGNO ( reg2 ) - 1 making them candidates for lfq and stfq insns . Note reg1 and reg2 * must * be hard registers . To be sure we will abort if we are passed pseudo registers .


<s> static rtx or1k_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree , bool named ) { if ( mode == VOIDmode ) return NULL_RTX ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int nreg = CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= 2 ) ; if ( named && * cum + nreg <= 6 ) return gen_rtx_REG ( mode , * cum + 3 ) ; else return NULL_RTX ; } </s>

Worker for TARGET_FUNCTION_ARG . Return the next register to be used to hold a function argument or NULL_RTX if there 's no more space . Arugment CUM_V represents the current argument offset , zero for the first function argument . OpenRISC function arguments maybe be passed in registers r3 to r8 .


<s>
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsCheriPureCap
(
)
)
return
makeArrayRef
(
CheriCapArgRegs
)
;
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


<s> void MipsAsmPrinter :: emitFunctionBodyStart ( ) { MipsTargetStreamer & TS = getTargetStreamer ( ) ; MCInstLowering . Initialize ( & MF -> getContext ( ) ) ; bool IsNakedFunction = MF -> getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; if ( ! Subtarget -> inMips16Mode ( ) ) { TS . emitDirectiveSetNoReorder ( ) ; TS . emitDirectiveSetNoMacro ( ) ; TS . emitDirectiveSetNoAt ( ) ; } } </s>

Targets can override this to emit stuff before the first basic block in the function .


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s> unsigned ARMInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDR : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: FLDD : case ARM :: FLDS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: tRestore : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool pa_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && x != CONST0_RTX ( mode ) ) return false ; if ( ! NEW_HP_ASSEMBLER && ! TARGET_GAS && GET_CODE ( x ) == LABEL_REF ) return false ; if ( tls_referenced_p ( x ) ) return false ; if ( TARGET_64BIT && GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( TARGET_64BIT && HOST_BITS_PER_WIDE_INT > 32 && GET_CODE ( x ) == CONST_INT && ! reload_in_progress && ! reload_completed && ! LEGITIMATE_64BIT_CONST_INT_P ( INTVAL ( x ) ) && ! pa_cint_ok_for_move ( UINTVAL ( x ) ) ) return false ; if ( function_label_operand ( x , mode ) ) return false ; return true ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . In 64-bit mode , we reject CONST_DOUBLES . We also reject CONST_INTS that need more than three instructions to load prior to reload . This limit is somewhat arbitrary . It takes three instructions to load a CONST_INT from memory but two are memory accesses . It may be better to increase the allowed range for CONST_INTS . We may also be able to handle CONST_DOUBLES .


<s> const char * output_branchy_insn ( enum rtx_code code , const char * template , rtx insn , rtx * operands ) { rtx next_insn = NEXT_INSN ( insn ) ; if ( next_insn && GET_CODE ( next_insn ) == JUMP_INSN && condjump_p ( next_insn ) ) { rtx src = SET_SRC ( PATTERN ( next_insn ) ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE && GET_CODE ( XEXP ( src , 0 ) ) != code ) { operands [ 9 ] = gen_label_rtx ( ) ; emit_label_after ( operands [ 9 ] , next_insn ) ; INSN_ADDRESSES_NEW ( operands [ 9 ] , INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + get_attr_length ( next_insn ) ) ; return template ; } else { int offset = ( branch_dest ( next_insn ) - INSN_ADDRESSES ( INSN_UID ( next_insn ) ) + 4 ) ; if ( offset >= - 252 && offset <= 258 ) { if ( GET_CODE ( src ) == IF_THEN_ELSE ) src = XEXP ( src , 1 ) ; operands [ 9 ] = src ; return template ; } } } operands [ 9 ] = gen_label_rtx ( ) ; emit_label_after ( operands [ 9 ] , insn ) ; INSN_ADDRESSES_NEW ( operands [ 9 ] , INSN_ADDRESSES ( INSN_UID ( insn ) ) + get_attr_length ( insn ) ) ; return template ; } </s>

Output a code sequence for INSN using TEMPL with OPERANDS ; but before , fill in operands 9 as a label to the successor insn . We try to use jump threading where possible . IF CODE matches the comparison in the IF_THEN_ELSE of a following jump , we assume the jump is taken . I.e . EQ means follow jmp and bf , NE means follow jmp and bt , if the address is in range .


<s>
bool
ARMBaseInstrInfo
::
getInsertSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPair
&
BaseReg
,
RegSubRegPairAndIdx
&
InsertedReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isInsertSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VSETLNi32
:
const
MachineOperand
&
MOBaseReg
=
MI
.
getOperand
(
1
)
;
const
MachineOperand
&
MOInsertedReg
=
MI
.
getOperand
(
2
)
;
const
MachineOperand
&
MOIndex
=
MI
.
getOperand
(
3
)
;
BaseReg
.
Reg
=
MOBaseReg
.
getReg
(
)
;
BaseReg
.
SubReg
=
MOBaseReg
.
getSubReg
(
)
;
InsertedReg
.
Reg
=
MOInsertedReg
.
getReg
(
)
;
InsertedReg
.
SubReg
=
MOInsertedReg
.
getSubReg
(
)
;
InsertedReg
.
SubIdx
=
MOIndex
.
getImm
(
)
==
0
ARM
::
ssub_0
:
ARM
::
ssub_1
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getInsertSubregInputs .


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11L ) ; Reserved . set ( SystemZ :: R11H ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15L ) ; Reserved . set ( SystemZ :: R15H ) ; Reserved . set ( SystemZ :: R14Q ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; return false ; } </s>


<s> static void ia64_asm_emit_except_personality ( rtx personality ) { fputs ( "\t.personality\t" , asm_out_file ) ; output_addr_const ( asm_out_file , personality ) ; fputc ( '\n' , asm_out_file ) ; } </s>


<s> static bool aarch64_register_saved_on_entry ( int regno ) { return known_ge ( cfun -> machine -> frame . reg_offset [ regno ] , 0 ) ; } </s>

Return true if the register REGNO is saved on entry to the current function .


<s> static rtx is_jump_table ( rtx insn ) { rtx table ; if ( GET_CODE ( insn ) == JUMP_INSN && JUMP_LABEL ( insn ) != NULL && ( ( table = next_real_insn ( JUMP_LABEL ( insn ) ) ) == next_real_insn ( insn ) ) && table != NULL && GET_CODE ( table ) == JUMP_INSN && ( GET_CODE ( PATTERN ( table ) ) == ADDR_VEC || GET_CODE ( PATTERN ( table ) ) == ADDR_DIFF_VEC ) ) return table ; return NULL_RTX ; } </s>

Determines if INSN is the start of a jump table . Returns the end of the TABLE or NULL_RTX .


<s> rtx get_deferred_plabel ( rtx symbol ) { const char * fname = XSTR ( symbol , 0 ) ; size_t i ; for ( i = 0 ; i < n_deferred_plabels ; i ++ ) if ( strcmp ( fname , XSTR ( deferred_plabels [ i ] . symbol , 0 ) ) == 0 ) break ; if ( deferred_plabels == NULL || i == n_deferred_plabels ) { tree id ; if ( deferred_plabels == 0 ) deferred_plabels = ( struct deferred_plabel * ) ggc_alloc ( sizeof ( struct deferred_plabel ) ) ; else deferred_plabels = ( struct deferred_plabel * ) ggc_realloc ( deferred_plabels , ( ( n_deferred_plabels + 1 ) * sizeof ( struct deferred_plabel ) ) ) ; i = n_deferred_plabels ++ ; deferred_plabels [ i ] . internal_label = gen_label_rtx ( ) ; deferred_plabels [ i ] . symbol = symbol ; id = maybe_get_identifier ( targetm . strip_name_encoding ( fname ) ) ; if ( id ) mark_referenced ( id ) ; } return deferred_plabels [ i ] . internal_label ; } </s>

Search the deferred plabel list for SYMBOL and return its internal label . If an entry for SYMBOL is not found , a new entry is created .


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { struct cl_target_option cl_opts ; if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; cl_target_option_save ( & cl_opts , opts , opts_set ) ; arm_configure_build_target ( & arm_active_target , & cl_opts , opts_set , false ) ; arm_option_check_internal ( opts ) ; arm_option_reconfigure_globals ( ) ; arm_options_perform_arch_sanity_checks ( ) ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts , opts_set ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s> static bool mips_keep_interrupts_masked_p ( tree type ) { return lookup_attribute ( "keep_interrupts_masked" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Check if the attribute to keep interrupts masked is set for a function .


<s> static int mips_fp_mult_cost ( machine_mode mode ) { return mode == DFmode ? mips_cost -> fp_mult_df : mips_cost -> fp_mult_sf ; } </s>

Return the cost of floating-point multiplications of mode MODE .


<s> static sbitmap aarch64_get_separate_components ( void ) { aarch64_layout_frame ( ) ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg2 ) ; if ( reg1 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg1 ) ; bitmap_clear_bit ( components , LR_REGNUM ) ; bitmap_clear_bit ( components , SP_REGNUM ) ; return components ; } </s>


<s> unsigned PPCTargetLowering :: combineRepeatedFPDivisors ( ) const { switch ( Subtarget . getMcpu ( ) ) { default : return 3 ; case PPC :: MCPU_440 : case PPC :: MCPU_A2 : case PPC :: MCPU_E500 : case PPC :: MCPU_E500mc : case PPC :: MCPU_E5500 : return 2 ; } } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> static void ia64_copy_rbs ( struct _Unwind_Context * info , unsigned long dst , unsigned long src , long len , unsigned long dst_rnat ) { long count ; unsigned long src_rnat ; unsigned long shift1 , shift2 ; len <<= 3 ; dst_rnat &= ( 1UL << ( ( dst >> 3 ) & 0x3f ) ) - 1 ; src_rnat = src >= info -> regstk_top ? info -> rnat : * ( unsigned long * ) ( src | 0x1f8 ) ; src_rnat &= ~ ( ( 1UL << ( ( src >> 3 ) & 0x3f ) ) - 1 ) ; src_rnat &= ~ ( 1UL << 63 ) ; shift1 = ( ( dst - src ) >> 3 ) & 0x3f ; if ( ( dst & 0x1f8 ) < ( src & 0x1f8 ) ) shift1 -- ; shift2 = 0x3f - shift1 ; if ( ( dst & 0x1f8 ) >= ( src & 0x1f8 ) ) { count = ~ dst & 0x1f8 ; goto first ; } count = ~ src & 0x1f8 ; goto second ; while ( len > 0 ) { src_rnat = src >= info -> regstk_top ? info -> rnat : * ( unsigned long * ) ( src | 0x1f8 ) ; src_rnat &= ~ ( 1UL << 63 ) ; count = shift2 << 3 ; first : if ( count > len ) count = len ; memcpy ( ( char * ) dst , ( char * ) src , count ) ; dst += count ; src += count ; len -= count ; dst_rnat |= ( src_rnat << shift1 ) & ~ ( 1UL << 63 ) ; if ( len <= 0 ) break ; * ( long * ) dst = dst_rnat ; dst += 8 ; dst_rnat = 0 ; count = shift1 << 3 ; second : if ( count > len ) count = len ; memcpy ( ( char * ) dst , ( char * ) src , count ) ; dst += count ; src += count + 8 ; len -= count + 8 ; dst_rnat |= ( src_rnat >> shift2 ) ; } if ( ( dst & 0x1f8 ) == 0x1f8 ) { * ( long * ) dst = dst_rnat ; dst += 8 ; dst_rnat = 0 ; } info -> regstk_top = dst & ~ 0x1ffUL ; info -> rnat = dst_rnat ; } </s>

Copy register backing store from SRC to DST , LEN words ( which include both saved registers and nat collections ) . DST_RNAT is a partial nat collection for DST . SRC and DST do n't have to be equal modulo 64 slots , so it can not be done with a simple memcpy as the nat collections will be at different relative offsets and need to be combined together .


<s> void mips_output_ascii ( FILE * stream , const char * string_param , size_t len , const char * prefix ) { size_t i ; int cur_pos = 17 ; register const unsigned char * string = ( const unsigned char * ) string_param ; fprintf ( stream , "%s\"" , prefix ) ; for ( i = 0 ; i < len ; i ++ ) { register int c = string [ i ] ; if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; cur_pos ++ ; } putc ( c , stream ) ; cur_pos ++ ; } else { fprintf ( stream , "\\%03o" , c ) ; cur_pos += 4 ; } if ( cur_pos > 72 && i + 1 < len ) { cur_pos = 17 ; fprintf ( stream , "\"\n%s\"" , prefix ) ; } } fprintf ( stream , "\"\n" ) ; } </s>

Output an ASCII string , in a space-saving way . PREFIX is the string that should be written before the opening quote , such as `` \t.ascii\t '' for real string data or `` \t # `` for a comment .


<s>
unsigned
SparcRegisterInfo
::
getFrameRegister
(
MachineFunction
&
MF
)
const
{
assert
(
0
&&
"What is the frame register"
)
;
return
SP
::
G1
;
}
</s>


<s> unsigned postKnownBits ( Align Align = Align :: None ( ) ) const { return std :: max ( Log2 ( std :: max ( PostAlign , Align ) ) , internalKnownBits ( ) ) ; } </s>

Compute the number of known low bits of postOffset .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } initAsmInfo ( ) ; } </s>


<s> bool mips_split_128bit_move_p ( rtx dest , rtx src ) { if ( FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; if ( FP_REG_RTX_P ( dest ) && mips_const_vector_same_int_p ( src , GET_MODE ( src ) , - 512 , 511 ) ) return false ; if ( FP_REG_RTX_P ( dest ) && src == CONST0_RTX ( GET_MODE ( src ) ) ) return false ; return true ; } </s>

Return true if a 128-bit move from SRC to DEST should be split .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicCmpXchgIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicCmpXchgInst
*
CI
,
Value
*
AlignedAddr
,
Value
*
CmpVal
,
Value
*
NewVal
,
Value
*
Mask
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
AlignedAddr
->
getType
(
)
->
getPointerElementType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
IntCmpXchg
=
Intrinsic
::
getDeclaration
(
M
,
Intrinsic
::
ppc_cmpxchg_i128
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
CmpLo
=
Builder
.
CreateTrunc
(
CmpVal
,
Int64Ty
,
"cmp_lo"
)
;
Value
*
CmpHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
CmpVal
,
64
)
,
Int64Ty
,
"cmp_hi"
)
;
Value
*
NewLo
=
Builder
.
CreateTrunc
(
NewVal
,
Int64Ty
,
"new_lo"
)
;
Value
*
NewHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
NewVal
,
64
)
,
Int64Ty
,
"new_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
emitLeadingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
IntCmpXchg
,
{
Addr
,
CmpLo
,
CmpHi
,
NewLo
,
NewHi
}
)
;
emitTrailingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> int AArch64TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> bool rs6000_is_valid_insert_mask ( rtx mask , rtx shift , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = INTVAL ( XEXP ( shift , 1 ) ) ; if ( sh < 0 || sh >= n ) return false ; rtx_code code = GET_CODE ( shift ) ; if ( sh == 0 ) code = ROTATE ; if ( code == ROTATE && sh >= 0 && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= 0 && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < 32 && ne < 32 && sh < 32 ) ; if ( ne > nb ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < 32 && ne < 32 && sh < 32 && ! ( code == LSHIFTRT && nb >= 32 - sh ) ) return true ; if ( code == LSHIFTRT ) sh = 64 - sh ; if ( ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwimi or rldimi instruction , to implement an insert with shift SHIFT ( a ROTATE , ASHIFT , or LSHIFTRT ) in mode MODE .


<s> static void init_vselect_insn ( void ) { unsigned i ; rtx x ; x = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( MAX_VECT_LEN ) ) ; for ( i = 0 ; i < MAX_VECT_LEN ; ++ i ) XVECEXP ( x , 0 , i ) = const0_rtx ; x = gen_rtx_VEC_SELECT ( V2DFmode , gen_rtx_VEC_CONCAT ( V4DFmode , const0_rtx , const0_rtx ) , x ) ; x = gen_rtx_SET ( const0_rtx , x ) ; start_sequence ( ) ; vselect_insn = emit_insn ( x ) ; end_sequence ( ) ; } </s>


<s> int ccr_bit ( rtx op , int scc_p ) { enum rtx_code code = GET_CODE ( op ) ; machine_mode cc_mode ; int cc_regnum ; int base_bit ; rtx reg ; if ( ! COMPARISON_P ( op ) ) return - 1 ; reg = XEXP ( op , 0 ) ; gcc_assert ( GET_CODE ( reg ) == REG && CR_REGNO_P ( REGNO ( reg ) ) ) ; cc_mode = GET_MODE ( reg ) ; cc_regnum = REGNO ( reg ) ; base_bit = 4 * ( cc_regnum - CR0_REGNO ) ; validate_condition_mode ( code , cc_mode ) ; gcc_assert ( ! scc_p || code == EQ || code == GT || code == LT || code == UNORDERED || code == GTU || code == LTU ) ; switch ( code ) { case NE : return scc_p ? base_bit + 3 : base_bit + 2 ; case EQ : return base_bit + 2 ; case GT : case GTU : case UNLE : return base_bit + 1 ; case LT : case LTU : case UNGE : return base_bit ; case ORDERED : case UNORDERED : return base_bit + 3 ; case GE : case GEU : return scc_p ? base_bit + 3 : base_bit ; case LE : case LEU : return scc_p ? base_bit + 3 : base_bit + 1 ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison operation , return the bit number in CCR to test . We know this is a valid comparison . SCC_P is 1 if this is for an scc . That means that % D will have been used instead of % C , so the bits will be in different places . Return -1 if OP is n't a valid comparison for some reason .


<s> bool ARMFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) return false ; return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget . is64Bit ( ) ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v16i16 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : case MVT :: v64i8 : case MVT :: v32i16 : case MVT :: v16i32 : case MVT :: v8i64 : case MVT :: v16f32 : case MVT :: v8f64 : RRC = & X86 :: VR128XRegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s>
static
void
or1k_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
'#'
:
if
(
final_sequence
==
)
fputs
(
"\n\t l.nop\n"
,
file
)
;
break
;
case
'r'
:
if
(
REG_P
(
x
)
)
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
else
if
(
x
==
CONST0_RTX
(
GET_MODE
(
x
)
)
)
fprintf
(
file
,
"r0"
)
;
else
output_operand_lossage
(
"invalid %%r value"
)
;
break
;
case
'H'
:
if
(
REG_P
(
x
)
)
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
+
1
]
)
;
else
output_operand_lossage
(
"invalid %%H value"
)
;
break
;
case
'd'
:
if
(
REG_P
(
x
)
)
{
if
(
GET_MODE
(
x
)
==
DFmode
||
GET_MODE
(
x
)
==
DImode
)
fprintf
(
file
,
"%s,%s"
,
reg_names
[
REGNO
(
operand
)
]
,
reg_names
[
REGNO
(
operand
)
+
1
]
)
;
else
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
}
else
output_operand_lossage
(
"invalid %%d value"
)
;
break
;
case
'h'
:
print_reloc
(
file
,
x
,
0
,
RKIND_HI
)
;
break
;
case
'L'
:
print_reloc
(
file
,
x
,
0
,
RKIND_LO
)
;
break
;
case
'P'
:
if
(
!
flag_pic
||
SYMBOL_REF_LOCAL_P
(
x
)
)
output_addr_const
(
file
,
x
)
;
else
output_addr_reloc
(
file
,
x
,
0
,
"plt"
)
;
break
;
case
0
:
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
if
(
REGNO
(
operand
)
>
31
)
internal_error
(
"internal error: bad register: %d"
,
REGNO
(
operand
)
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
break
;
case
MEM
:
output_address
(
GET_MODE
(
XEXP
(
operand
,
0
)
)
,
XEXP
(
operand
,
0
)
)
;
break
;
case
CODE_LABEL
:
case
LABEL_REF
:
output_asm_label
(
operand
)
;
break
;
default
:
if
(
CONSTANT_P
(
operand
)
)
output_addr_const
(
file
,
operand
)
;
else
internal_error
(
"unexpected operand: %d"
,
GET_CODE
(
operand
)
)
;
break
;
}
break
;
default
:
output_operand_lossage
(
"unknown operand letter: '%c'"
,
code
)
;
break
;
}
}
</s>

Worker for TARGET_PRINT_OPERAND . Print operand X , an RTX , to the file FILE . The output is formed as expected by the OpenRISC assember . CODE is the letter following a ' % ' in an instrunction template used to control the RTX output . Example ( s ) : CODE RTX OUTPUT COMMENT 0 ( reg : SI 3 ) r3 output an operand r ( reg : SI 3 ) r3 output a register or const zero H ( reg : SI 3 ) r4 output the high pair register h ( symbol_ref : SI ( `` x '' ) ) ha ( x ) output a signed high relocation L ( symbol_ref : SI ( `` x '' ) ) lo ( x ) output a low relocation Note , ' # ' is a special code used to fill the branch delay slot with an l.nop instruction . The l.nop ( no-op ) instruction is only outputted when the delay slot has not been filled .


<s> char * function_builder :: get_name ( const function_instance & instance , bool overloaded_p ) { append_name ( instance . base_name ) ; if ( overloaded_p ) switch ( instance . displacement_units ( ) ) { case UNITS_none : break ; case UNITS_bytes : append_name ( "_offset" ) ; break ; case UNITS_elements : append_name ( "_index" ) ; break ; case UNITS_vectors : append_name ( "_vnum" ) ; break ; } else append_name ( instance . mode_suffix ( ) . string ) ; for ( unsigned int i = 0 ; i < 2 ; ++ i ) if ( ! overloaded_p || instance . shape -> explicit_type_suffix_p ( i ) ) append_name ( instance . type_suffix ( i ) . string ) ; append_name ( pred_suffixes [ instance . pred ] ) ; return finish_name ( ) ; } </s>

Return the overloaded or full function name for INSTANCE ; OVERLOADED_P selects which . Allocate the string on m_string_obstack ; the caller must use obstack_free to free it after use .


Return the function that is used to expand the < u > mulsidi3 pattern . EXT_CODE is the code of the extension used . Return NULL if widening multiplication should n't be used .


<s> static std :: unique_ptr < X86Operand > CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) , StringRef SymName = StringRef ( ) , void * OpDecl = nullptr ) { auto Res = llvm :: make_unique < X86Operand > ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> int aarch64_hard_regno_mode_ok ( unsigned regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return regno == CC_REGNUM ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) && ! aarch64_vect_struct_mode_p ( mode ) ) return 1 ; if ( FP_REGNUM_P ( regno ) ) { if ( aarch64_vect_struct_mode_p ( mode ) ) return ( regno + aarch64_hard_regno_nregs ( regno , mode ) - 1 ) <= V31_REGNUM ; else return 1 ; } return 0 ; } </s>


"No idea how to print this kind of operand"

print - Print a debug representation of the operand to the given stream .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ 2 ] , & Constraint [ Size - 1 ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= 0 && RegNo <= 31 ) { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> void thumb_expand_movmemqi ( rtx * operands ) { rtx out = copy_to_mode_reg ( SImode , XEXP ( operands [ 0 ] , 0 ) ) ; rtx in = copy_to_mode_reg ( SImode , XEXP ( operands [ 1 ] , 0 ) ) ; HOST_WIDE_INT len = INTVAL ( operands [ 2 ] ) ; HOST_WIDE_INT offset = 0 ; while ( len >= 12 ) { emit_insn ( gen_movmem12b ( out , in , out , in ) ) ; len -= 12 ; } if ( len >= 8 ) { emit_insn ( gen_movmem8b ( out , in , out , in ) ) ; len -= 8 ; } if ( len >= 4 ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= 4 ; offset += 4 ; } if ( len >= 2 ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movhi ( gen_rtx_MEM ( HImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; len -= 2 ; offset += 2 ; } if ( len ) { rtx reg = gen_reg_rtx ( QImode ) ; emit_insn ( gen_movqi ( reg , gen_rtx_MEM ( QImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; } } </s>


<s> Align getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { const Align ABIAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ArgTy -> isVectorTy ( ) ) return std :: min ( ABIAlign , Align ( 8 ) ) ; return ABIAlign ; } </s>

Return the correct alignment for the current calling convention .


<s> static HARD_REG_SET sparc_zero_call_used_regs ( HARD_REG_SET need_zeroed_hardregs ) { for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { if ( regno >= SPARC_FCC_REG || ( regno >= SPARC_FIRST_FP_REG && ! TARGET_VIS ) ) CLEAR_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ; else if ( regno >= SPARC_FIRST_V9_FP_REG && ( regno & 1 ) ) ; else { machine_mode mode ; rtx reg ; if ( regno < SPARC_FIRST_FP_REG ) { reg = regno_reg_rtx [ regno ] ; mode = GET_MODE ( reg ) ; } else { mode = regno < SPARC_FIRST_V9_FP_REG ? SFmode : DFmode ; reg = gen_raw_REG ( mode , regno ) ; } emit_move_insn ( reg , CONST0_RTX ( mode ) ) ; } } return need_zeroed_hardregs ; } </s>

Implement TARGET_ZERO_CALL_USED_REGS . Generate a sequence of instructions that zero registers specified by NEED_ZEROED_HARDREGS . Return the ZEROED_HARDREGS that are actually zeroed .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


"lowerToVVP called for unexpected SDNode."


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int ix86_reg_parm_stack_space ( const_tree fndecl ) { enum calling_abi call_abi = SYSV_ABI ; if ( fndecl != NULL_TREE && TREE_CODE ( fndecl ) == FUNCTION_DECL ) call_abi = ix86_function_abi ( fndecl ) ; else call_abi = ix86_function_type_abi ( fndecl ) ; if ( TARGET_64BIT && call_abi == MS_ABI ) return 32 ; return 0 ; } </s>

It returns the size , in bytes , of the area reserved for arguments passed in registers for the function represented by fndecl dependent to the used abi format .


<s> virtual bool isToken ( ) const LLVM_OVERRIDE { return Kind == KindToken ; } </s>


<s> void mips16_expand_get_fcsr ( rtx target ) { if ( ! mips16_get_fcsr_stub ) mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ( ) ; rtx fn = mips16_stub_call_address ( mips16_get_fcsr_stub ) ; emit_insn ( PMODE_INSN ( gen_mips_get_fcsr_mips16 , ( fn ) ) ) ; emit_move_insn ( target , gen_rtx_REG ( SImode , GET_FCSR_REGNUM ) ) ; } </s>

Implement `` TARGET = __builtin_mips_get_fcsr ( ) '' for MIPS16 , using a stub .


Return the string to output a compare and branch instruction to DEST . DEST is the destination insn ( i.e . the label ) , INSN is the source , and OP is the conditional expression .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDNode
*
XNCMDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
)
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

XNCM
XNCM
"Selecting: "
"\n"
"== "
"\n"
"=> "
"\n"


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( Subtarget . isSVR4ABI ( ) && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { const uint64_t SpillSize = 4 ; const int64_t SpillOffset = Subtarget . isPPC64 ( ) ? 8 : - 4 ; int FrameIdx = MFI . CreateFixedObject ( SpillSize , SpillOffset , true , false ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


"Only Linux target is expected to contain LOAD_STACK_GUARD"

"Invalid D-Form Pseudo-ops on non-P9 target."

This function is called for all pseudo instructions that remain after register allocation .


<s> bool loongarch_split_move_insn_p ( rtx dest , rtx src ) { return loongarch_split_move_p ( dest , src ) ; } </s>

Return true if a move from SRC to DEST in INSN should be split .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; const Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static rtx rs6000_emit_vector_compare ( enum rtx_code rcode , rtx op0 , rtx op1 , machine_mode dmode ) { rtx mask ; bool swap_operands = false ; bool try_again = false ; gcc_assert ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( dmode ) ) ; gcc_assert ( GET_MODE ( op0 ) == GET_MODE ( op1 ) ) ; mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; switch ( rcode ) { case LT : rcode = GT ; swap_operands = true ; try_again = true ; break ; case LTU : rcode = GTU ; swap_operands = true ; try_again = true ; break ; case NE : case UNLE : case UNLT : case UNGE : case UNGT : { enum rtx_code rev_code ; enum insn_code nor_code ; rtx mask2 ; rev_code = reverse_condition_maybe_unordered ( rcode ) ; if ( rev_code == UNKNOWN ) return NULL_RTX ; nor_code = optab_handler ( one_cmpl_optab , dmode ) ; if ( nor_code == CODE_FOR_nothing ) return NULL_RTX ; mask2 = rs6000_emit_vector_compare ( rev_code , op0 , op1 , dmode ) ; if ( ! mask2 ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( nor_code ) ( mask , mask2 ) ) ; return mask ; } break ; case GE : case GEU : case LE : case LEU : { rtx c_rtx , eq_rtx ; enum insn_code ior_code ; enum rtx_code new_code ; switch ( rcode ) { case GE : new_code = GT ; break ; case GEU : new_code = GTU ; break ; case LE : new_code = LT ; break ; case LEU : new_code = LTU ; break ; default : gcc_unreachable ( ) ; } ior_code = optab_handler ( ior_optab , dmode ) ; if ( ior_code == CODE_FOR_nothing ) return NULL_RTX ; c_rtx = rs6000_emit_vector_compare ( new_code , op0 , op1 , dmode ) ; if ( ! c_rtx ) return NULL_RTX ; eq_rtx = rs6000_emit_vector_compare ( EQ , op0 , op1 , dmode ) ; if ( ! eq_rtx ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( ior_code ) ( mask , c_rtx , eq_rtx ) ) ; return mask ; } break ; default : return NULL_RTX ; } if ( try_again ) { if ( swap_operands ) std :: swap ( op0 , op1 ) ; mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; } return NULL_RTX ; } </s>

Emit vector compare for operands OP0 and OP1 using code RCODE . DMODE is expected destination mode . This is a recursive function .


<s>
bool
ARMConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
isThumb
4
:
8
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

ARM
ARM
4
8
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> static _Unwind_Reason_Code get_eit_entry ( _Unwind_Control_Block * ucbp , _uw return_address ) { const __EIT_entry * eitp ; int nrec ; return_address -= 2 ; if ( __gnu_Unwind_Find_exidx ) { eitp = ( const __EIT_entry * ) __gnu_Unwind_Find_exidx ( return_address , & nrec ) ; if ( ! eitp ) { UCB_PR_ADDR ( ucbp ) = 0 ; return _URC_FAILURE ; } } else { eitp = & __exidx_start ; nrec = & __exidx_end - & __exidx_start ; } eitp = search_EIT_table ( eitp , nrec , return_address ) ; if ( ! eitp ) { UCB_PR_ADDR ( ucbp ) = 0 ; return _URC_FAILURE ; } ucbp -> pr_cache . fnstart = selfrel_offset31 ( & eitp -> fnoffset ) ; if ( eitp -> content == EXIDX_CANTUNWIND ) { UCB_PR_ADDR ( ucbp ) = 0 ; return _URC_END_OF_STACK ; } if ( eitp -> content & uint32_highbit ) { ucbp -> pr_cache . ehtp = ( _Unwind_EHT_Header * ) & eitp -> content ; ucbp -> pr_cache . additional = 1 ; } else { ucbp -> pr_cache . ehtp = ( _Unwind_EHT_Header * ) selfrel_offset31 ( & eitp -> content ) ; ucbp -> pr_cache . additional = 0 ; } if ( * ucbp -> pr_cache . ehtp & ( 1u << 31 ) ) { _uw idx = ( * ( _uw * ) ucbp -> pr_cache . ehtp >> 24 ) & 0xf ; if ( idx == 0 ) UCB_PR_ADDR ( ucbp ) = ( _uw ) & __aeabi_unwind_cpp_pr0 ; else if ( idx == 1 ) UCB_PR_ADDR ( ucbp ) = ( _uw ) & __aeabi_unwind_cpp_pr1 ; else if ( idx == 2 ) UCB_PR_ADDR ( ucbp ) = ( _uw ) & __aeabi_unwind_cpp_pr2 ; else { UCB_PR_ADDR ( ucbp ) = 0 ; return _URC_FAILURE ; } } else { UCB_PR_ADDR ( ucbp ) = selfrel_offset31 ( ucbp -> pr_cache . ehtp ) ; } return _URC_OK ; } </s>

Find the exception index table eintry for the given address . Fill in the relevant fields of the UCB . Returns _URC_FAILURE if an error occurred , _URC_OK on success .