<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dest , SDValue Src , MachinePointerInfo DestPtrInfo , MachinePointerInfo SrcPtrInfo , bool isStpcpy ) const { SDVTList VTs = DAG . getVTList ( Dest . getValueType ( ) , MVT :: Other ) ; SDValue EndDest = DAG . getNode ( SystemZISD :: STPCPY , DL , VTs , Chain , Dest , Src , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; return std :: make_pair ( isStpcpy ? EndDest : Dest , EndDest . getValue ( 1 ) ) ; } </s>

Emit target-specific code that performs a strcpy or stpcpy , in cases where that is faster than a libcall .


<s> unsigned Cpu0AsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> int pa_attr_length_call ( rtx_insn * insn , int sibcall ) { int local_call ; rtx call , call_dest ; tree call_decl ; int length = 0 ; rtx pat = PATTERN ( insn ) ; unsigned long distance = - 1 ; gcc_assert ( CALL_P ( insn ) ) ; if ( INSN_ADDRESSES_SET_P ( ) ) { unsigned long total ; total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; call = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; gcc_assert ( GET_CODE ( call ) == CALL ) ; call_dest = XEXP ( XEXP ( call , 0 ) , 0 ) ; call_decl = SYMBOL_REF_DECL ( call_dest ) ; local_call = call_decl && targetm . binds_local_p ( call_decl ) ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! sibcall && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) length += 8 ; else if ( TARGET_64BIT && ! local_call ) length += 24 ; else if ( ( TARGET_LONG_ABS_CALL || local_call ) && ! flag_pic ) length += 12 ; else if ( TARGET_LONG_PIC_SDIFF_CALL || ( TARGET_GAS && ! TARGET_SOM && local_call ) ) { length += 20 ; if ( ! TARGET_PA_20 && ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += 8 ; } else { length += 32 ; if ( TARGET_SOM ) length += length_fp_args ( insn ) ; if ( flag_pic ) length += 4 ; if ( ! TARGET_PA_20 ) { if ( ! sibcall ) length += 8 ; if ( ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += 8 ; } } return length ; } </s>

Return the attribute length of the call instruction INSN . The SIBCALL flag indicates whether INSN is a regular call or a sibling call . The length returned must be longer than the code actually generated by pa_output_call . Since branch shortening is done before delay branch sequencing , there is no way to determine whether or not the delay slot will be filled during branch shortening . Even when the delay slot is filled , we may have to add a nop if the delay slot contains a branch that ca n't reach its target . Thus , we always have to include the delay slot in the length estimate . This used to be done in pa_adjust_insn_length but we do it here now as some sequences always fill the delay slot and we can save four bytes in the estimate for these sequences .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> int nds32_can_use_btgl_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'btgl ' instruction can be used with IVAL .


<s>
bool
scalar_chain
::
add_insn
(
bitmap
candidates
,
unsigned
int
insn_uid
,
bitmap
disallowed
)
{
if
(
!
bitmap_set_bit
(
insns
,
insn_uid
)
)
return
true
;
if
(
dump_file
)
fprintf
(
dump_file
,
"  Adding insn %d to chain #%d\n"
,
insn_uid
,
chain_id
)
;
rtx_insn
*
insn
=
DF_INSN_UID_GET
(
insn_uid
)
->
insn
;
rtx
def_set
=
single_set
(
insn
)
;
if
(
def_set
&&
REG_P
(
SET_DEST
(
def_set
)
)
&&
!
HARD_REGISTER_P
(
SET_DEST
(
def_set
)
)
)
bitmap_set_bit
(
defs
,
REGNO
(
SET_DEST
(
def_set
)
)
)
;
df_ref
ref
;
for
(
ref
=
DF_INSN_UID_DEFS
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
HARD_REGISTER_P
(
DF_REF_REG
(
ref
)
)
)
if
(
!
analyze_register_chain
(
candidates
,
ref
,
disallowed
)
)
return
false
;
if
(
def_set
&&
GET_CODE
(
SET_SRC
(
def_set
)
)
==
VEC_SELECT
)
return
true
;
for
(
ref
=
DF_INSN_UID_USES
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
DF_REF_REG_MEM_P
(
ref
)
)
if
(
!
analyze_register_chain
(
candidates
,
ref
,
disallowed
)
)
return
false
;
return
true
;
}
</s>

Add instruction into a chain . Return true if OK , false if the search was aborted .


<s> Register AArch64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? AArch64 :: FP : AArch64 :: SP ; } </s>


<s> static unsigned int pa_function_arg_boundary ( machine_mode mode , const_tree type ) { bool singleword = ( type ? ( integer_zerop ( TYPE_SIZE ( type ) ) || ! TREE_CONSTANT ( TYPE_SIZE ( type ) ) || int_size_in_bytes ( type ) <= UNITS_PER_WORD ) : GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) ; return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY ; } </s>

Arguments larger than one word are double word aligned .


Return an array that contains the bitmask target flag values and their names .


<s> static int uses_TOC ( void ) { rtx_insn * insn ; int ret = 1 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) { rtx sub = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , 0 ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , 1 ) == UNSPEC_TOC ) return ret ; } } } else if ( crtl -> has_bb_partition && NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) ret = 2 ; } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


<s>
Register
OutgoingValueHandler
::
extendRegister
(
Register
ValReg
,
const
CCValAssign
&
VA
)
{
LLT
LocTy
{
VA
.
getLocVT
(
)
}
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
SExt
:
{
return
MIRBuilder
.
buildSExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
ZExt
:
{
return
MIRBuilder
.
buildZExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
AExt
:
{
return
MIRBuilder
.
buildAnyExt
(
LocTy
,
ValReg
)
.
getReg
(
0
)
;
}
case
CCValAssign
::
Full
:
return
ValReg
;
default
:
break
;
}
llvm_unreachable
(
"unable to extend register"
)
;
}
</s>

Extend a register to the location type given in VA , capped at extending to at most MaxSize bits .


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const MCPhysReg RegList [ ] = { FISC :: X10 , FISC :: X11 , FISC :: X12 , FISC :: X13 , FISC :: X14 , FISC :: X15 , FISC :: X26 , FISC :: X27 , FISC :: X18 } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; if ( State . isVarArg ( ) ) { unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; for ( unsigned j = 0 ; j < ArgsParts [ i ] ; j ++ ) { if ( i == 0 && j == 0 ) State . addLoc ( CCValAssign :: getCustomMem ( ValNo ++ , ArgVT , State . AllocateStack ( 8 , 8 ) , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo ++ , ArgVT , State . AllocateStack ( 8 , 8 ) , LocVT , LocInfo ) ) ; } } return ; } unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 8 , 8 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } SmallVectorImpl < CCValAssign > :: iterator B = ArgLocs . begin ( ) + FirstVal ; std :: reverse ( B , B + Parts ) ; } else { UseStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) CC_FISC ( ValNo ++ , ArgVT , LocVT , LocInfo , ArgFlags , State ) ; } } } </s>

The function will invoke AnalyzeCallOperands .


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) ) . addReg ( StackReg ) . addReg ( StackReg ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void ARMConstantPoolValue :: print ( raw_ostream & O ) const { if ( CVal ) O << CVal -> getName ( ) ; else O << S ; if ( Modifier ) O << "(" << getModifierText ( ) << ")" ; if ( PCAdjust != 0 ) { O << "-(LPC" << LabelId << "+" << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << "-." ; O << ")" ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> static inline built_in_function complex_multiply_builtin_code ( machine_mode mode ) { gcc_assert ( IN_RANGE ( mode , MIN_MODE_COMPLEX_FLOAT , MAX_MODE_COMPLEX_FLOAT ) ) ; int func = BUILT_IN_COMPLEX_MUL_MIN + mode - MIN_MODE_COMPLEX_FLOAT ; return ( built_in_function ) func ; } </s>

Internal function to return the built-in function id for the complex multiply operation for a given mode .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static rtx expand_set_or_movmem_prologue ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int align , int desired_alignment , bool issetmem ) { int i ; for ( i = 1 ; i < desired_alignment ; i <<= 1 ) { if ( align <= i ) { rtx_code_label * label = ix86_expand_aligntest ( destptr , i , false ) ; if ( issetmem ) { if ( vec_value && i > GET_MODE_SIZE ( GET_MODE ( value ) ) ) destmem = emit_memset ( destmem , destptr , vec_value , i ) ; else destmem = emit_memset ( destmem , destptr , value , i ) ; } else destmem = emit_memmov ( destmem , & srcmem , destptr , srcptr , i ) ; ix86_adjust_counter ( count , i ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; set_mem_align ( destmem , i * 2 * BITS_PER_UNIT ) ; } } return destmem ; } </s>

Depending on ISSETMEM , copy enough from SRCMEM to DESTMEM or set enough to DESTMEM to align it to DESIRED_ALIGNMENT . Original alignment is ALIGN . Depending on ISSETMEM , either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are ignored . Return value is updated DESTMEM .


<s>
static
void
add_sve_type_attribute
(
tree
type
,
unsigned
int
num_zr
,
unsigned
int
num_pr
,
const
char
*
mangled_name
,
const
char
*
acle_name
)
{
tree
mangled_name_tree
=
(
mangled_name
get_identifier
(
mangled_name
)
:
NULL_TREE
)
;
tree
value
=
tree_cons
(
NULL_TREE
,
get_identifier
(
acle_name
)
,
NULL_TREE
)
;
value
=
tree_cons
(
NULL_TREE
,
mangled_name_tree
,
value
)
;
value
=
tree_cons
(
NULL_TREE
,
size_int
(
num_pr
)
,
value
)
;
value
=
tree_cons
(
NULL_TREE
,
size_int
(
num_zr
)
,
value
)
;
TYPE_ATTRIBUTES
(
type
)
=
tree_cons
(
get_identifier
(
"SVE type"
)
,
value
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

Record that TYPE is an ABI-defined SVE type that contains NUM_ZR SVE vectors and NUM_PR SVE predicates . MANGLED_NAME , if nonnull , is the ABI-defined mangling of the type . ACLE_NAME is the < arm_sve.h > name of the type .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool any_sibcall_could_use_r3 ( void ) { edge_iterator ei ; edge e ; if ( ! crtl -> tail_call_emit ) return false ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) if ( e -> flags & EDGE_SIBCALL ) { rtx_insn * call = BB_END ( e -> src ) ; if ( ! CALL_P ( call ) ) call = prev_nonnote_nondebug_insn ( call ) ; gcc_assert ( CALL_P ( call ) && SIBLING_CALL_P ( call ) ) ; if ( find_regno_fusage ( call , USE , 3 ) || is_indirect_tailcall_p ( call ) ) return true ; } return false ; } </s>

Return true if r3 is used by any of the tail call insns in the current function .


<s> static section * pa_som_tm_clone_table_section ( void ) { return som_tm_clone_table_section ; } </s>


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & TM ; } </s>

This method must be called before any actual lowering is done .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be some form of pointer , without being specific about its target type . Return true if the argument has the right form , otherwise report an appropriate error .


<s> bool X86IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return runTIs ( MMI , MF , TIs ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; if ( ! OnlyOptimizeForSize ) MergeExternalByDefault = false ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } return false ; } </s>


<s>
void
SystemZInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
SystemZ
::
GR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
SystemZ
::
MOV64rr
;
else
if
(
SystemZ
::
GR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
SystemZ
::
MOV32rr
;
else
if
(
SystemZ
::
GR64PRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
SystemZ
::
MOV64rrP
;
else
if
(
SystemZ
::
GR128RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
SystemZ
::
MOV128rr
;
else
if
(
SystemZ
::
FP32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
SystemZ
::
FMOV32rr
;
else
if
(
SystemZ
::
FP64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
SystemZ
::
FMOV64rr
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static rtx iq2000_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { int reg = GP_RETURN ; machine_mode mode = TYPE_MODE ( valtype ) ; int unsignedp = TYPE_UNSIGNED ( valtype ) ; const_tree func = fn_decl_or_type ; if ( fn_decl_or_type && ! DECL_P ( fn_decl_or_type ) ) fn_decl_or_type = NULL ; mode = promote_function_mode ( valtype , mode , & unsignedp , func , 1 ) ; return gen_rtx_REG ( mode , reg ) ; } </s>

Return register to use for a function return value with VALTYPE for function FUNC .


<s>
int
SparcRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .

Sparc
Sparc
"What is the dwarf register number"
1


<s> static void rs6000_assemble_visibility ( tree decl , int vis ) { if ( TARGET_XCOFF ) return ; if ( DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS && TREE_CODE ( decl ) == FUNCTION_DECL ) { static const char * const visibility_types [ ] = { NULL , "internal" , "hidden" , "protected" } ; const char * name , * type ; name = ( ( * targetm . strip_name_encoding ) ( IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ) ; type = visibility_types [ vis ] ; fprintf ( asm_out_file , "\t.%s\t%s\n" , type , name ) ; fprintf ( asm_out_file , "\t.%s\t.%s\n" , type , name ) ; } else default_assemble_visibility ( decl , vis ) ; } </s>

Emit an assembler directive to set symbol visibility for DECL to VISIBILITY_TYPE .


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static unsigned int mips_build_shift ( struct mips_integer_op * codes , HOST_WIDE_INT value ) { unsigned int i , shift ; shift = 0 ; while ( ( value & 1 ) == 0 ) value /= 2 , shift ++ ; i = mips_build_integer ( codes , value ) ; codes [ i ] . code = ASHIFT ; codes [ i ] . value = shift ; return i + 1 ; } </s>

Subroutine of mips_build_integer ( with the same interface ) . Assume that the final action in the sequence should be a left shift .


<s> bool ia64_expand_load_address ( rtx dest , rtx src ) { gcc_assert ( GET_CODE ( dest ) == REG ) ; if ( GET_MODE ( dest ) != Pmode ) dest = gen_rtx_REG_offset ( dest , Pmode , REGNO ( dest ) , byte_lowpart_offset ( Pmode , GET_MODE ( dest ) ) ) ; if ( TARGET_NO_PIC ) return false ; if ( small_addr_symbolic_operand ( src , VOIDmode ) ) return false ; if ( TARGET_AUTO_PIC ) emit_insn ( gen_load_gprel64 ( dest , src ) ) ; else if ( GET_CODE ( src ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( src ) ) emit_insn ( gen_load_fptr ( dest , src ) ) ; else if ( sdata_symbolic_operand ( src , VOIDmode ) ) emit_insn ( gen_load_gprel ( dest , src ) ) ; else { HOST_WIDE_INT addend = 0 ; rtx tmp ; if ( GET_CODE ( src ) == CONST ) { HOST_WIDE_INT hi , lo ; hi = INTVAL ( XEXP ( XEXP ( src , 0 ) , 1 ) ) ; lo = ( ( hi & 0x3fff ) ^ 0x2000 ) - 0x2000 ; hi = hi - lo ; if ( lo != 0 ) { addend = lo ; src = plus_constant ( Pmode , XEXP ( XEXP ( src , 0 ) , 0 ) , hi ) ; } } tmp = gen_rtx_HIGH ( Pmode , src ) ; tmp = gen_rtx_PLUS ( Pmode , tmp , pic_offset_table_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; tmp = gen_rtx_LO_SUM ( Pmode , gen_const_mem ( Pmode , dest ) , src ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; if ( addend ) { tmp = gen_rtx_PLUS ( Pmode , dest , GEN_INT ( addend ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; } } return true ; } </s>


<s>
bool
X86AsmParser
::
processInstruction
(
MCInst
&
Inst
,
const
OperandVector
&
Ops
)
{
const
MCRegisterInfo
*
MRI
=
getContext
(
)
.
getRegisterInfo
(
)
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
return
false
;
case
X86
::
VMOVZPQILo2PQIrr
:
case
X86
::
VMOVAPDrr
:
case
X86
::
VMOVAPDYrr
:
case
X86
::
VMOVAPSrr
:
case
X86
::
VMOVAPSYrr
:
case
X86
::
VMOVDQArr
:
case
X86
::
VMOVDQAYrr
:
case
X86
::
VMOVDQUrr
:
case
X86
::
VMOVDQUYrr
:
case
X86
::
VMOVUPDrr
:
case
X86
::
VMOVUPDYrr
:
case
X86
::
VMOVUPSrr
:
case
X86
::
VMOVUPSYrr
:
{
if
(
ForcedVEXEncoding
==
VEXEncoding_VEX3
||
MRI
->
getEncodingValue
(
Inst
.
getOperand
(
0
)
.
getReg
(
)
)
>=
8
||
MRI
->
getEncodingValue
(
Inst
.
getOperand
(
1
)
.
getReg
(
)
)
<
8
)
return
false
;
unsigned
NewOpc
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Invalid opcode"
)
;
case
X86
::
VMOVZPQILo2PQIrr
:
NewOpc
=
X86
::
VMOVPQI2QIrr
;
break
;
case
X86
::
VMOVAPDrr
:
NewOpc
=
X86
::
VMOVAPDrr_REV
;
break
;
case
X86
::
VMOVAPDYrr
:
NewOpc
=
X86
::
VMOVAPDYrr_REV
;
break
;
case
X86
::
VMOVAPSrr
:
NewOpc
=
X86
::
VMOVAPSrr_REV
;
break
;
case
X86
::
VMOVAPSYrr
:
NewOpc
=
X86
::
VMOVAPSYrr_REV
;
break
;
case
X86
::
VMOVDQArr
:
NewOpc
=
X86
::
VMOVDQArr_REV
;
break
;
case
X86
::
VMOVDQAYrr
:
NewOpc
=
X86
::
VMOVDQAYrr_REV
;
break
;
case
X86
::
VMOVDQUrr
:
NewOpc
=
X86
::
VMOVDQUrr_REV
;
break
;
case
X86
::
VMOVDQUYrr
:
NewOpc
=
X86
::
VMOVDQUYrr_REV
;
break
;
case
X86
::
VMOVUPDrr
:
NewOpc
=
X86
::
VMOVUPDrr_REV
;
break
;
case
X86
::
VMOVUPDYrr
:
NewOpc
=
X86
::
VMOVUPDYrr_REV
;
break
;
case
X86
::
VMOVUPSrr
:
NewOpc
=
X86
::
VMOVUPSrr_REV
;
break
;
case
X86
::
VMOVUPSYrr
:
NewOpc
=
X86
::
VMOVUPSYrr_REV
;
break
;
}
Inst
.
setOpcode
(
NewOpc
)
;
return
true
;
}
case
X86
::
VMOVSDrr
:
case
X86
::
VMOVSSrr
:
{
if
(
ForcedVEXEncoding
==
VEXEncoding_VEX3
||
MRI
->
getEncodingValue
(
Inst
.
getOperand
(
0
)
.
getReg
(
)
)
>=
8
||
MRI
->
getEncodingValue
(
Inst
.
getOperand
(
2
)
.
getReg
(
)
)
<
8
)
return
false
;
unsigned
NewOpc
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Invalid opcode"
)
;
case
X86
::
VMOVSDrr
:
NewOpc
=
X86
::
VMOVSDrr_REV
;
break
;
case
X86
::
VMOVSSrr
:
NewOpc
=
X86
::
VMOVSSrr_REV
;
break
;
}
Inst
.
setOpcode
(
NewOpc
)
;
return
true
;
}
}
}
</s>

Process a single instruction and collect debug info anchors .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"TeeRISC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
optForSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
static
bool
ix86_function_ok_for_sibcall
(
tree
decl
,
tree
exp
)
{
tree
type
,
decl_or_type
;
rtx
a
,
b
;
bool
bind_global
=
decl
&&
!
targetm
.
binds_local_p
(
decl
)
;
if
(
ix86_function_naked
(
current_function_decl
)
)
return
false
;
if
(
cfun
->
machine
->
no_caller_saved_registers
)
return
false
;
if
(
!
TARGET_MACHO
&&
!
TARGET_64BIT
&&
flag_pic
&&
flag_plt
&&
bind_global
)
return
false
;
if
(
ix86_minimum_incoming_stack_boundary
(
true
)
<
PREFERRED_STACK_BOUNDARY
)
return
false
;
if
(
decl
)
{
decl_or_type
=
decl
;
type
=
TREE_TYPE
(
decl
)
;
}
else
{
type
=
CALL_EXPR_FN
(
exp
)
;
type
=
TREE_TYPE
(
type
)
;
type
=
TREE_TYPE
(
type
)
;
decl_or_type
=
type
;
}
if
(
(
OUTGOING_REG_PARM_STACK_SPACE
(
type
)
!=
OUTGOING_REG_PARM_STACK_SPACE
(
TREE_TYPE
(
current_function_decl
)
)
)
||
(
REG_PARM_STACK_SPACE
(
decl_or_type
)
!=
REG_PARM_STACK_SPACE
(
current_function_decl
)
)
)
{
maybe_complain_about_tail_call
(
exp
,
"inconsistent size of stack space"
" allocated for arguments which are"
" passed in registers"
)
;
return
false
;
}
a
=
ix86_function_value
(
TREE_TYPE
(
exp
)
,
decl_or_type
,
false
)
;
b
=
ix86_function_value
(
TREE_TYPE
(
DECL_RESULT
(
cfun
->
decl
)
)
,
cfun
->
decl
,
false
)
;
if
(
STACK_REG_P
(
a
)
||
STACK_REG_P
(
b
)
)
{
if
(
!
rtx_equal_p
(
a
,
b
)
)
return
false
;
}
else
if
(
VOID_TYPE_P
(
TREE_TYPE
(
DECL_RESULT
(
cfun
->
decl
)
)
)
)
;
else
if
(
!
rtx_equal_p
(
a
,
b
)
)
return
false
;
if
(
TARGET_64BIT
)
{
if
(
cfun
->
machine
->
call_abi
==
MS_ABI
&&
ix86_function_type_abi
(
type
)
==
SYSV_ABI
)
return
false
;
}
else
{
if
(
!
decl
||
(
bind_global
&&
flag_pic
&&
!
flag_plt
)
||
(
TARGET_DLLIMPORT_DECL_ATTRIBUTES
&&
DECL_DLLIMPORT_P
(
decl
)
)
||
flag_force_indirect_call
)
{
if
(
ix86_function_regparm
(
type
,
decl
)
>=
3
&&
!
cfun
->
machine
->
arg_reg_available
)
return
false
;
}
}
if
(
decl
&&
ix86_use_pseudo_pic_reg
(
)
)
{
cgraph_node
*
node
=
cgraph_node
::
get
(
decl
)
;
if
(
node
&&
node
->
ifunc_resolver
)
return
false
;
}
if
(
(
(
flag_cf_protection
&
(
CF_RETURN
|
CF_BRANCH
)
)
==
(
CF_RETURN
|
CF_BRANCH
)
)
&&
lookup_attribute
(
"indirect_return"
,
TYPE_ATTRIBUTES
(
type
)
)
&&
!
lookup_attribute
(
"indirect_return"
,
TYPE_ATTRIBUTES
(
TREE_TYPE
(
cfun
->
decl
)
)
)
)
return
false
;
return
true
;
}
</s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


"Can only insert epilog into returning blocks"


<s>
static
void
rs6000_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
rs6000_print_isa_options
(
file
,
indent
,
"Isa options set"
,
ptr
->
x_rs6000_isa_flags
)
;
rs6000_print_isa_options
(
file
,
indent
,
"Isa options explicit"
,
ptr
->
x_rs6000_isa_flags_explicit
)
;
}
</s>

rs6000
"Isa options set"
"Isa options explicit"


"JIT relocation model must be set to static or default!"


<s> static section * ia64_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( GET_MODE_SIZE ( mode ) > 0 && GET_MODE_SIZE ( mode ) <= ia64_section_threshold && ! TARGET_NO_SDATA ) return sdata_section ; else return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Switch to the section to which we should output X . The only thing special we do here is to honor small data .


<s> static rtx rs6000_complex_function_value ( machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_UNIT_SIZE ( mode ) ; if ( TARGET_FLOAT128_TYPE && ( mode == KCmode || ( mode == TCmode && TARGET_IEEEQUAD ) ) ) regno = ALTIVEC_ARG_RETURN ; else if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= 4 ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= 8 ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + 1 ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } </s>

Return an RTX representing where to find the function value of a function returning MODE .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( usesGlobalOffsetTable ( ) ) return DAG . getGLOBAL_OFFSET_TABLE ( getPointerTy ( ) ) ; if ( ! Subtarget -> isPICStyleRIPRel ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> static bool darwin_local_data_pic ( rtx disp ) { return ( GET_CODE ( disp ) == UNSPEC && XINT ( disp , 1 ) == UNSPEC_MACHOPIC_OFFSET ) ; } </s>

Allow { LABEL | SYMBOL } _REF - SYMBOL_REF-FOR-PICBASE for Mach-O as this is used for to form addresses to local data when -fPIC is in use .


<s> virtual bool isFMAFasterThanFMulAndFAdd ( EVT VT ) const { return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> int ix86_omp_device_kind_arch_isa ( enum omp_device_kind_arch_isa trait , const char * name ) { switch ( trait ) { case omp_device_kind : return strcmp ( name , "cpu" ) == 0 ; case omp_device_arch : if ( strcmp ( name , "intel_mic" ) == 0 ) return 1 ; if ( strcmp ( name , "x86" ) == 0 ) return 1 ; if ( TARGET_64BIT ) { if ( TARGET_X32 ) return strcmp ( name , "x32" ) == 0 ; else return strcmp ( name , "x86_64" ) == 0 ; } if ( strcmp ( name , "ia32" ) == 0 || strcmp ( name , "i386" ) == 0 ) return 1 ; if ( strcmp ( name , "i486" ) == 0 ) return ix86_arch != PROCESSOR_I386 ? 1 : - 1 ; if ( strcmp ( name , "i586" ) == 0 ) return ( ix86_arch != PROCESSOR_I386 && ix86_arch != PROCESSOR_I486 ) ? 1 : - 1 ; if ( strcmp ( name , "i686" ) == 0 ) return ( ix86_arch != PROCESSOR_I386 && ix86_arch != PROCESSOR_I486 && ix86_arch != PROCESSOR_LAKEMONT && ix86_arch != PROCESSOR_PENTIUM ) ? 1 : - 1 ; return 0 ; case omp_device_isa : for ( int i = 0 ; i < 2 ; i ++ ) { struct ix86_target_opts * opts = i ? isa2_opts : isa_opts ; size_t nopts = i ? ARRAY_SIZE ( isa2_opts ) : ARRAY_SIZE ( isa_opts ) ; HOST_WIDE_INT mask = i ? ix86_isa_flags2 : ix86_isa_flags ; for ( size_t n = 0 ; n < nopts ; n ++ ) { if ( opts [ n ] . mask == OPTION_MASK_ISA_SSE4_2 ) { if ( strcmp ( name , "sse4" ) == 0 ) return ( mask & opts [ n ] . mask ) != 0 ? 1 : - 1 ; } if ( strcmp ( name , opts [ n ] . option + 2 ) == 0 ) return ( mask & opts [ n ] . mask ) != 0 ? 1 : - 1 ; } } return 0 ; default : gcc_unreachable ( ) ; } } </s>

Return 1 if TRAIT NAME is present in the OpenMP context 's device trait set , return 0 if not present in any OpenMP context in the whole translation unit , or -1 if not present in the current OpenMP context but might be present in another OpenMP context in the same TU .


<s> bool MipsInstrInfo :: HasLoadDelaySlot ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case Mips :: LB : case Mips :: LBu : case Mips :: LH : case Mips :: LHu : case Mips :: LW : case Mips :: LWR : case Mips :: LWL : return true ; default : return false ; } } </s>

Predicate to determine if an instruction has a load delay slot .

Mips Mips Mips::LB Mips::LBu Mips::LH Mips::LHu Mips::LW Mips::LWR Mips::LWL


<s> bool PPCFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( MF . getInfo < PPCFunctionInfo > ( ) -> shrinkWrapDisabled ( ) ) return false ; return ( MF . getSubtarget < PPCSubtarget > ( ) . isSVR4ABI ( ) && MF . getSubtarget < PPCSubtarget > ( ) . isPPC64 ( ) ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return NumRegisters ; } if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static bool classof ( const MCStreamer * S ) { return S -> getKind ( ) == SK_AsmStreamer ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ; DataSection . setAlignment ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ; BSSSection . setAlignment ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ; const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( EFlags & ELF :: EF_MIPS_CPIC && getABI ( ) . IsN64 ( ) ) EFlags |= ELF :: EF_MIPS_PIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . is64Bit ( ) ) { unsigned TyAlign = DL . getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> static int reg_encoded_number ( rtx reg ) { unsigned regno = REGNO ( reg ) ; switch ( regno ) { case AX_REG : return 0 ; case CX_REG : return 1 ; case DX_REG : return 2 ; case BX_REG : return 3 ; case SP_REG : return 4 ; case BP_REG : return 5 ; case SI_REG : return 6 ; case DI_REG : return 7 ; default : break ; } if ( IN_RANGE ( regno , FIRST_STACK_REG , LAST_STACK_REG ) ) return regno - FIRST_STACK_REG ; if ( IN_RANGE ( regno , FIRST_SSE_REG , LAST_SSE_REG ) ) return regno - FIRST_SSE_REG ; if ( IN_RANGE ( regno , FIRST_MMX_REG , LAST_MMX_REG ) ) return regno - FIRST_MMX_REG ; if ( IN_RANGE ( regno , FIRST_REX_SSE_REG , LAST_REX_SSE_REG ) ) return regno - FIRST_REX_SSE_REG ; if ( IN_RANGE ( regno , FIRST_REX_INT_REG , LAST_REX_INT_REG ) ) return regno - FIRST_REX_INT_REG ; if ( IN_RANGE ( regno , FIRST_MASK_REG , LAST_MASK_REG ) ) return regno - FIRST_MASK_REG ; if ( IN_RANGE ( regno , FIRST_BND_REG , LAST_BND_REG ) ) return regno - FIRST_BND_REG ; return - 1 ; } </s>

Return the number used for encoding REG , in the range 0 .. 7 .


<s> void ia64_expand_widen_sum ( rtx operands [ 3 ] , bool unsignedp ) { rtx l , h , x , s ; enum machine_mode wmode , mode ; rtx ( * unpack_l ) ( rtx , rtx , rtx ) ; rtx ( * unpack_h ) ( rtx , rtx , rtx ) ; rtx ( * plus ) ( rtx , rtx , rtx ) ; wmode = GET_MODE ( operands [ 0 ] ) ; mode = GET_MODE ( operands [ 1 ] ) ; switch ( mode ) { case V8QImode : unpack_l = gen_unpack1_l ; unpack_h = gen_unpack1_h ; plus = gen_addv4hi3 ; break ; case V4HImode : unpack_l = gen_unpack2_l ; unpack_h = gen_unpack2_h ; plus = gen_addv2si3 ; break ; default : gcc_unreachable ( ) ; } if ( unsignedp ) x = CONST0_RTX ( mode ) ; else { bool neg ; x = gen_reg_rtx ( mode ) ; neg = ia64_expand_vecint_compare ( LT , mode , x , operands [ 1 ] , CONST0_RTX ( mode ) ) ; gcc_assert ( ! neg ) ; } l = gen_reg_rtx ( wmode ) ; h = gen_reg_rtx ( wmode ) ; s = gen_reg_rtx ( wmode ) ; emit_insn ( unpack_l ( gen_lowpart ( mode , l ) , operands [ 1 ] , x ) ) ; emit_insn ( unpack_h ( gen_lowpart ( mode , h ) , operands [ 1 ] , x ) ) ; emit_insn ( plus ( s , l , operands [ 2 ] ) ) ; emit_insn ( plus ( operands [ 0 ] , h , s ) ) ; } </s>

Emit an integral vector widening sum operations .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == 64 ) { cmp_mode = mode_for_size ( GET_MODE_NUNITS ( cmp_ops_mode ) , MODE_INT , 0 ) ; gcc_assert ( cmp_mode != BLKmode ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


<s> static int mips_multipass_dfa_lookahead ( void ) { if ( mips_tune == PROCESSOR_SB1 ) return 4 ; return 0 ; } </s>


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: CALL : return LowerCALL ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FORMAL_ARGUMENTS : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: RET : return LowerRET ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::CALL ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FORMAL_ARGUMENTS ISD::FP_TO_SINT ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::RET ISD::SELECT ISD::SETCC


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < MipsSubtarget > ( ) . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 2 4 Mips 2 16 4 0


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
char
Letter
,
bool
hasMemory
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
unsigned
Value
=
CST
->
getZExtValue
(
)
;
switch
(
Letter
)
{
default
:
assert
(
0
&&
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'J'
:
case
'L'
:
if
(
(
short
)
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'K'
:
if
(
(
Value
>>
16
)
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'N'
:
if
(
(
int
)
Value
>
0
&&
isPowerOf2_32
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'P'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Letter
,
hasMemory
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> static bool or1k_function_value_regno_p ( const unsigned int regno ) { return ( regno == RV_REGNUM ) ; } </s>

Worker for TARGET_FUNCTION_VALUE_REGNO_P . Returns true if REGNO is a valid register for storing a function return value .


<s> void TOYInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> void aarch64_simd_emit_reg_reg_move ( rtx * operands , machine_mode mode , unsigned int count ) { unsigned int i ; int rdest = REGNO ( operands [ 0 ] ) ; int rsrc = REGNO ( operands [ 1 ] ) ; if ( ! reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) || rdest < rsrc ) for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + i ) , gen_rtx_REG ( mode , rsrc + i ) ) ; else for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + count - i - 1 ) , gen_rtx_REG ( mode , rsrc + count - i - 1 ) ) ; } </s>

Emit a register copy from operand to operand , taking care not to early-clobber source registers in the process . COUNT is the number of components into which the copy needs to be decomposed .


"unknown flag passed in %<-moverride=%s%> (%s)"

Parse TOKEN , which has length LENGTH to see if it is an option described in FLAG . If it is , return the index bit for that fusion type . If not , error ( printing OPTION_NAME ) and return zero .


<s> rtx ix86_expand_adjust_ufix_to_sfix_si ( rtx val , rtx * xorp ) { REAL_VALUE_TYPE TWO31r ; rtx two31r , tmp [ 4 ] ; machine_mode mode = GET_MODE ( val ) ; machine_mode scalarmode = GET_MODE_INNER ( mode ) ; machine_mode intmode = GET_MODE_SIZE ( mode ) == 32 ? V8SImode : V4SImode ; rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = 0 ; i < 3 ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , 1 , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case E_V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case E_V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case E_V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case E_V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ 3 ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ 0 ] , two31r , val , tmp [ 3 ] ) ) ; tmp [ 1 ] = expand_simple_binop ( mode , AND , tmp [ 0 ] , two31r , tmp [ 1 ] , 0 , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ 0 ] ) , GEN_INT ( 31 ) , NULL_RTX , 0 , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( HOST_WIDE_INT_1U << 31 ) ; two31 = ix86_build_const_vector ( intmode , 1 , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [ 0 ] ) , two31 , NULL_RTX , 0 , OPTAB_DIRECT ) ; } return expand_simple_binop ( mode , MINUS , val , tmp [ 1 ] , tmp [ 2 ] , 0 , OPTAB_DIRECT ) ; } </s>

Adjust a V * SFmode/V * DFmode value VAL so that * sfix_trunc * resp . fix_trunc * pattern can be used on it instead of fixuns_trunc * . This is done by doing just signed conversion if < 0x1p31 , and otherwise by subtracting 0x1p31 first and xoring in 0x80000000 from * XORP afterwards .


<s> bool AArch64CompressJumpTables :: runOnMachineFunction ( MachineFunction & MFIn ) { bool Changed = false ; MF = & MFIn ; const auto & ST = MF -> getSubtarget < AArch64Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ST . force32BitJumpTables ( ) && ! MF -> getFunction ( ) . hasMinSize ( ) ) return false ; scanFunction ( ) ; for ( MachineBasicBlock & MBB : * MF ) { int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes ( MI ) ; } } return Changed ; } </s>


<s> static struct bundle_state * get_free_bundle_state ( void ) { struct bundle_state * result ; if ( free_bundle_state_chain != NULL ) { result = free_bundle_state_chain ; free_bundle_state_chain = result -> next ; } else { result = XNEW ( struct bundle_state ) ; result -> dfa_state = xmalloc ( dfa_state_size ) ; result -> allocated_states_chain = allocated_bundle_states_chain ; allocated_bundle_states_chain = result ; } result -> unique_num = bundle_states_num ++ ; return result ; } </s>

The following function returns a free bundle state .


<s> static tree resolve_vec_cmpne ( resolution * res , tree * args , tree * types , location_t loc ) { if ( TREE_CODE ( types [ 0 ] ) != VECTOR_TYPE || ! lang_hooks . types_compatible_p ( types [ 0 ] , types [ 1 ] ) ) { * res = resolved_bad ; return error_mark_node ; } machine_mode arg0_elt_mode = TYPE_MODE ( TREE_TYPE ( types [ 0 ] ) ) ; if ( ! TARGET_P9_VECTOR || arg0_elt_mode == DImode || arg0_elt_mode == TImode || arg0_elt_mode == SFmode || arg0_elt_mode == DFmode ) { switch ( arg0_elt_mode ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : case E_SFmode : case E_DFmode : { vec < tree , va_gc > * params = make_tree_vector ( ) ; vec_safe_push ( params , args [ 0 ] ) ; vec_safe_push ( params , args [ 1 ] ) ; tree decl = rs6000_builtin_decls [ RS6000_OVLD_VEC_CMPEQ ] ; tree call = altivec_resolve_overloaded_builtin ( loc , decl , params ) ; call = save_expr ( call ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , call ) ; vec_safe_push ( params , call ) ; decl = rs6000_builtin_decls [ RS6000_OVLD_VEC_NOR ] ; * res = resolved ; return altivec_resolve_overloaded_builtin ( loc , decl , params ) ; } default : * res = resolved_bad ; return error_mark_node ; } } * res = unresolved ; return error_mark_node ; } </s>

Resolve an overloaded vec_cmpne call and return a tree expression for the resolved call if successful . ARGS contains the arguments to the call . TYPES contains their types . RES must be set to indicate the status of the resolution attempt . LOC contains statement location information .


<s> static void sh_setup_incoming_varargs ( cumulative_args_t ca , const function_arg_info & arg , int * pretend_arg_size , int second_time ATTRIBUTE_UNUSED ) { gcc_assert ( cfun -> stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs , anon_parm_regs ; named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , arg . mode ) + CEIL ( arg . promoted_size_in_bytes ( ) , UNITS_PER_WORD ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > 0 ) * pretend_arg_size = anon_parm_regs * 4 ; } } </s>

We actually emit the code in sh_expand_prologue . We used to use a static variable to flag that we need to emit this code , but that does n't when inlining , when functions are deferred and then emitted later . Fortunately , we already have two flags that are part of struct function that tell if a function uses varargs or stdarg .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < 16 > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: RestoreRaF16 ) ) . addImm ( StackSize ) ; } </s>

Mips Mips Mips Mips 16 Mips::RestoreRaF16


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
APInt
&
KnownZero
,
APInt
&
KnownOne
,
const
APInt
&
DemandedElts
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
APInt
KnownZero2
,
KnownOne2
;
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
KnownZero
,
KnownOne
,
Depth
+
1
)
;
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
KnownZero2
,
KnownOne2
,
Depth
+
1
)
;
KnownZero
&=
KnownZero2
;
KnownOne
&=
KnownOne2
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
KnownOne
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
KnownZero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
KnownZero
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
KnownZero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
KnownZero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


Wrapper around the output_probe_stack_range routines .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"constant arithmetic operand out of range"

Detect and error out on out-of-range constants for addhi and subhi .


<s> static rtx aarch64_gen_storewb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case E_DImode : return gen_storewb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; case E_DFmode : return gen_storewb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; case E_TFmode : return gen_storewb_pairtf_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_VREG - adjustment ) ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return an instruction to store the pair of registers REG and REG2 of mode MODE to location BASE with write-back adjusting the stack location BASE by ADJUSTMENT .


<s>
void
ARM64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
TargetFrameLowering
*
TFI
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
;
const
ARM64InstrInfo
*
TII
=
static_cast
<
const
ARM64InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
MachineInstr
*
Old
=
I
;
DebugLoc
DL
=
Old
->
getDebugLoc
(
)
;
unsigned
Amount
=
Old
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
unsigned
Align
=
TFI
->
getStackAlignment
(
)
;
Amount
=
(
Amount
+
Align
1
)
/
Align
*
Align
;
unsigned
Opc
=
Old
->
getOpcode
(
)
;
if
(
Opc
==
ARM64
::
ADJCALLSTACKDOWN
)
{
emitFrameOffset
(
MBB
,
I
,
DL
,
ARM64
::
SP
,
ARM64
::
SP
,
Amount
,
TII
)
;
}
else
{
assert
(
Opc
==
ARM64
::
ADJCALLSTACKUP
&&
"expected ADJCALLSTACKUP"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
ARM64
::
SP
,
ARM64
::
SP
,
Amount
,
TII
)
;
}
}
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


Return an array that contains the bitmask target flag values and their names .


<s> void SystemZCopyPhysRegs :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( ( TSFlags & X86II :: NOTRACK ) || ( Flags & X86 :: IP_HAS_NOTRACK ) ) OS << "\tnotrack\t" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII , getRegisterName ) ; } </s>


<s> static void aarch64_option_restore ( struct gcc_options * opts , struct gcc_options * , struct cl_target_option * ptr ) { opts -> x_explicit_arch = ptr -> x_explicit_arch ; selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ; opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; if ( opts -> x_explicit_tune_core == aarch64_none && opts -> x_explicit_arch != aarch64_no_arch ) selected_tune = & all_cores [ selected_arch -> ident ] ; else selected_tune = aarch64_get_tune_cpu ( ptr -> x_explicit_tune_core ) ; opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ; opts -> x_aarch64_branch_protection_string = ptr -> x_aarch64_branch_protection_string ; if ( opts -> x_aarch64_branch_protection_string ) { aarch64_parse_branch_protection ( opts -> x_aarch64_branch_protection_string , NULL ) ; } aarch64_override_options_internal ( opts ) ; } </s>

Implements TARGET_OPTION_RESTORE . Restore the backend codegen decisions using the information saved in PTR .


<s> bool mergeStoresAfterLegalization ( EVT VT ) const override { return ! useSVEForFixedLengthVectors ( ) ; } </s>

Do not merge vector stores after legalization because that may conflict with x86-specific store splitting optimizations .


<s> void applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void AArch64AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerAArch64MachineInstrToMCInst ( MI , TmpInst , * this ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void PrintSpecial ( const MCInst * MI , const char * Kind ) { } </s>

Print information related to the specified machine instr that is independent of the operand , and may be independent of the instr itself .


<s> static int aarch64_rtx_mult_cost ( rtx x , int code , int outer , bool speed ) { rtx op0 , op1 ; const struct cpu_cost_table * extra_cost = aarch64_tune_params -> insn_extra_cost ; int cost = 0 ; bool maybe_fma = ( outer == PLUS || outer == MINUS ) ; machine_mode mode = GET_MODE ( x ) ; gcc_checking_assert ( code == MULT ) ; op0 = XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; if ( VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( CONST_INT_P ( op1 ) && exact_log2 ( INTVAL ( op1 ) ) > 0 ) { if ( speed ) { if ( maybe_fma ) cost += extra_cost -> alu . arith_shift ; else cost += extra_cost -> alu . shift ; } cost += rtx_cost ( op0 , GET_CODE ( op0 ) , 0 , speed ) ; return cost ; } if ( ( GET_CODE ( op0 ) == ZERO_EXTEND && GET_CODE ( op1 ) == ZERO_EXTEND ) || ( GET_CODE ( op0 ) == SIGN_EXTEND && GET_CODE ( op1 ) == SIGN_EXTEND ) ) { cost += rtx_cost ( XEXP ( op0 , 0 ) , MULT , 0 , speed ) + rtx_cost ( XEXP ( op1 , 0 ) , MULT , 1 , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ 0 ] . extend_add ; else cost += extra_cost -> mult [ 0 ] . extend ; } return cost ; } cost += rtx_cost ( op0 , MULT , 0 , speed ) + rtx_cost ( op1 , MULT , 1 , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ mode == DImode ] . add ; else cost += extra_cost -> mult [ mode == DImode ] . simple ; } return cost ; } else { if ( speed ) { if ( GET_CODE ( op0 ) == NEG ) op0 = XEXP ( op0 , 0 ) ; if ( GET_CODE ( op1 ) == NEG ) op1 = XEXP ( op1 , 0 ) ; if ( maybe_fma ) cost += extra_cost -> fp [ mode == DFmode ] . fma ; else cost += extra_cost -> fp [ mode == DFmode ] . mult ; } cost += rtx_cost ( op0 , MULT , 0 , speed ) + rtx_cost ( op1 , MULT , 1 , speed ) ; return cost ; } } </s>

Helper function for rtx cost calculation . Calculate the cost of a MULT , which may be part of a multiply-accumulate rtx . Return the calculated cost of the expression , recursing manually in to operands where needed .


Prepare for a new round of multipass lookahead scheduling .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , bool IsLP64 , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( IsLP64 ) ; else Opc = isSub ? getSUBriOpcode ( IsLP64 , Offset ) : getADDriOpcode ( IsLP64 , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = NULL ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Lanai Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static rtx ix86_expand_sse_ptest ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , 0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ 1 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , SET_DEST ( pat ) , const0_rtx ) ) ) ; return SUBREG_REG ( target ) ; } </s>

Subroutine of ix86_expand_builtin to take care of ptest insns .


<s> SMLoc getOffsetOfLoc ( ) const override { return OffsetOfLoc ; } </s>

getOffsetOfLoc - Get the location of the offset operator .


<s> bool isTarget64BitLP64 ( ) const { return In64BitMode && ( ! TargetTriple . isX32 ( ) && ! TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


"You cannot take the address of a nested function if you use "

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; EmitXRayTable ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { if ( Subtarget . isThumb2 ( ) && ! Subtarget . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool aarch64_evpc_rev_global ( struct expand_vec_perm_d * d ) { poly_uint64 nelt = d -> perm . length ( ) ; if ( ! d -> one_vector_p || d -> vec_flags == VEC_ADVSIMD ) return false ; if ( ! d -> perm . series_p ( 0 , 1 , nelt - 1 , - 1 ) ) return false ; if ( d -> testing_p ) return true ; rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , UNSPEC_REV ) ; emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV insn , which reverses elements within a full vector .


<s> bool LanaiAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; Register Reg = MO . getReg ( ) ; O << LanaiInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"invalid instruction when using jump guards!"

Perform target-specific instruction verification .


<s>
void
ARMBaseRegisterInfo
::
emitLoadConstPool
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
MBBI
,
DebugLoc
dl
,
unsigned
DestReg
,
unsigned
SubIdx
,
int
Val
,
ARMCC
::
CondCodes
Pred
,
unsigned
PredReg
,
unsigned
MIFlags
)
const
{
assert
(
!
FlagSfiDisableCP
&&
"unexpected call to emitLoadConstPool"
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineConstantPool
*
ConstantPool
=
MF
.
getConstantPool
(
)
;
const
Constant
*
C
=
ConstantInt
::
get
(
Type
::
getInt32Ty
(
MF
.
getFunction
(
)
->
getContext
(
)
)
,
Val
)
;
unsigned
Idx
=
ConstantPool
->
getConstantPoolIndex
(
C
,
4
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
ARM
::
LDRcp
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
,
SubIdx
)
.
addConstantPoolIndex
(
Idx
)
.
addImm
(
0
)
.
addImm
(
Pred
)
.
addReg
(
PredReg
)
.
setMIFlags
(
MIFlags
)
;
}
</s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .

ARM
ARM
ARMCC::CondCodes
"unexpected call to emitLoadConstPool"
4
ARM::LDRcp
0


<s> bool AArch64FastISel :: optimizeSelect ( const SelectInst * SI ) { if ( ! SI -> getType ( ) -> isIntegerTy ( 1 ) ) return false ; const Value * Src1Val , * Src2Val ; unsigned Opc = 0 ; bool NeedExtraOp = false ; if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getTrueValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getFalseValue ( ) ; Opc = AArch64 :: ORRWrr ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getFalseValue ( ) ; Src2Val = SI -> getCondition ( ) ; Opc = AArch64 :: BICWrr ; } } else if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getFalseValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ORRWrr ; NeedExtraOp = true ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ANDWrr ; } } if ( ! Opc ) return false ; unsigned Src1Reg = getRegForValue ( Src1Val ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( Src1Val ) ; unsigned Src2Reg = getRegForValue ( Src2Val ) ; if ( ! Src2Reg ) return false ; bool Src2IsKill = hasTrivialKill ( Src2Val ) ; if ( NeedExtraOp ) { Src1Reg = emitLogicalOp_ri ( ISD :: XOR , MVT :: i32 , Src1Reg , Src1IsKill , 1 ) ; Src1IsKill = true ; } unsigned ResultReg = fastEmitInst_rr ( Opc , & AArch64 :: GPR32spRegClass , Src1Reg , Src1IsKill , Src2Reg , Src2IsKill ) ; updateValueMap ( SI , ResultReg ) ; return true ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool SystemZTDCPass :: runOnFunction ( Function & F ) { ConvertedInsts . clear ( ) ; LogicOpsWorklist . clear ( ) ; PossibleJunk . clear ( ) ; for ( auto & I : instructions ( F ) ) { if ( I . getOpcode ( ) == Instruction :: FCmp ) convertFCmp ( cast < CmpInst > ( I ) ) ; else if ( I . getOpcode ( ) == Instruction :: ICmp ) convertICmp ( cast < CmpInst > ( I ) ) ; } if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 0 ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 1 ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , 0 ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Function * TDCFunc = Intrinsic :: getDeclaration ( & M , Intrinsic :: s390_tdc , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true ; } if ( ! MadeChange ) return false ; for ( auto * I : PossibleJunk ) if ( I -> user_empty ( ) ) I -> eraseFromParent ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> enum reg_class mips_preferred_reload_class ( rtx x , enum reg_class class ) { if ( mips_dangerous_for_la25_p ( x ) && reg_class_subset_p ( LEA_REGS , class ) ) return LEA_REGS ; if ( TARGET_HARD_FLOAT && FLOAT_MODE_P ( GET_MODE ( x ) ) && reg_class_subset_p ( FP_REGS , class ) ) return FP_REGS ; if ( reg_class_subset_p ( GR_REGS , class ) ) class = GR_REGS ; if ( TARGET_MIPS16 && reg_class_subset_p ( M16_REGS , class ) ) class = M16_REGS ; return class ; } </s>


<s> SDValue AArch64TargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps ) const { if ( Enabled == ReciprocalEstimate :: Enabled ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRECPE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( AArch64ISD :: FRECPS , DL , VT , Operand , Estimate , & Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , & Flags ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> rtx mips_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , GP_REG_FIRST + 31 ) ; } </s>

Implement RETURN_ADDR_RTX . Note , we do not support moving back to a previous frame .


<s>
bool
ARMTargetLowering
::
ExpandInlineAsm
(
CallInst
*
CI
)
const
{
if
(
!
Subtarget
->
hasV6Ops
(
)
)
return
false
;
InlineAsm
*
IA
=
cast
<
InlineAsm
>
(
CI
->
getCalledValue
(
)
)
;
std
::
string
AsmStr
=
IA
->
getAsmString
(
)
;
SmallVector
<
StringRef
,
4
>
AsmPieces
;
SplitString
(
AsmStr
,
AsmPieces
,
";\n"
)
;
switch
(
AsmPieces
.
size
(
)
)
{
default
:
return
false
;
case
1
:
AsmStr
=
AsmPieces
[
0
]
;
AsmPieces
.
clear
(
)
;
SplitString
(
AsmStr
,
AsmPieces
,
" \t,"
)
;
if
(
AsmPieces
.
size
(
)
==
3
&&
AsmPieces
[
0
]
==
"rev"
&&
AsmPieces
[
1
]
==
"$0"
&&
AsmPieces
[
2
]
==
"$1"
&&
IA
->
getConstraintString
(
)
.
compare
(
0
,
4
,
"=l,l"
)
==
0
)
{
const
IntegerType
*
Ty
=
dyn_cast
<
IntegerType
>
(
CI
->
getType
(
)
)
;
if
(
Ty
&&
Ty
->
getBitWidth
(
)
==
32
)
return
IntrinsicLowering
::
LowerToByteSwap
(
CI
)
;
}
break
;
}
return
false
;
}
</s>

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstruction ( MachineInstr * MI , bool NewMI ) const { switch ( MI -> getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return NULL ; MI = TargetInstrInfoImpl :: commuteInstruction ( MI , NewMI ) ; if ( ! MI ) return NULL ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return MI ; } } return TargetInstrInfoImpl :: commuteInstruction ( MI , NewMI ) ; } </s>

This method commutes the operands of the given machine instruction MI .

ARM ARM ARM::MOVCCr ARM::t2MOVCCr 0 ARMCC::CondCodes ARMCC::AL ARM::CPSR ARMCC::getOppositeCondition


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> StringRef X86IntelInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s> unsigned AArch64FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < AArch64FunctionInfo > ( ) -> getCalleeSavedStackSize ( ) ; return alignTo ( CSSize + MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) , getStackAlignment ( ) ) ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s>
static
void
pru_option_override
(
void
)
{
SUBTARGET_OVERRIDE_OPTIONS
;
if
(
flag_pic
==
1
)
warning
(
OPT_fpic
,
"%<-fpic%> is not supported"
)
;
if
(
flag_pic
==
2
)
warning
(
OPT_fPIC
,
"%<-fPIC%> is not supported"
)
;
if
(
flag_pie
==
1
)
warning
(
OPT_fpie
,
"%<-fpie%> is not supported"
)
;
if
(
flag_pie
==
2
)
warning
(
OPT_fPIE
,
"%<-fPIE%> is not supported"
)
;
if
(
flag_reorder_blocks_and_partition
)
{
inform
(
input_location
,
"%<-freorder-blocks-and-partition%> "
"not supported on this architecture"
)
;
flag_reorder_blocks_and_partition
=
0
;
flag_reorder_blocks
=
1
;
}
init_machine_status
=
&
pru_init_machine_status
;
target_option_default_node
=
target_option_current_node
=
build_target_option_node
(
&
global_options
,
&
global_options_set
)
;
pru_register_abicheck_pass
(
)
;
}
</s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createARMMachObjectWriter ( OS , false , MachO :: CPU_TYPE_ARM , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret ; } </s>


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
->
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
->
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
slowTwoMemOps
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> unsigned int aarch64_widest_sve_pred_elt_size ( rtx_vector_builder & builder ) { unsigned int mask = GET_MODE_SIZE ( DImode ) ; mask |= builder . npatterns ( ) ; unsigned int nelts = builder . encoded_nelts ( ) ; for ( unsigned int i = 1 ; i < nelts ; ++ i ) if ( INTVAL ( builder . elt ( i ) ) != 0 ) { if ( i & 1 ) return 1 ; mask |= i ; } return mask & - mask ; } </s>

BUILDER contains a predicate constant of mode VNx16BI . Return the widest predicate element size it can have ( that is , the largest size for which each element would still be 0 or 1 ) .


"Slot for FP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> const MCExpr * CSKYTargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr , SMLoc Loc , const MCExpr * AdjustExpr ) { auto ELFRefKind = CSKYMCExpr :: VK_CSKY_Invalid ; ConstantCounter ++ ; const MCExpr * OrigExpr = Expr ; if ( const CSKYMCExpr * CE = dyn_cast < CSKYMCExpr > ( Expr ) ) { Expr = CE -> getSubExpr ( ) ; ELFRefKind = CE -> getKind ( ) ; } if ( const MCSymbolRefExpr * SymExpr = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { const MCSymbol * Sym = & SymExpr -> getSymbol ( ) ; SymbolIndex Index = { Sym , ELFRefKind } ; if ( ConstantMap . find ( Index ) == ConstantMap . end ( ) ) { ConstantMap [ Index ] = ConstantPool -> addEntry ( getStreamer ( ) , OrigExpr , 4 , Loc , AdjustExpr ) ; } return ConstantMap [ Index ] ; } return ConstantPool -> addEntry ( getStreamer ( ) , Expr , 4 , Loc , AdjustExpr ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s> void aarch64_asm_output_alias ( FILE * stream , const tree decl , const tree target ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , 0 ) , 0 ) ; const char * value = IDENTIFIER_POINTER ( target ) ; aarch64_asm_output_variant_pcs ( stream , decl , name ) ; ASM_OUTPUT_DEF ( stream , name , value ) ; } </s>

Implement ASM_OUTPUT_DEF_FROM_DECLS . Output .variant_pcs for aliases .


"PrintAsmOperand not implemented yet!\n"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const MCExpr * PPCAIXAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const Function * F = dyn_cast < Function > ( CV ) ) { MCSymbolXCOFF * FSym = cast < MCSymbolXCOFF > ( getSymbol ( F ) ) ; if ( ! FSym -> hasContainingCsect ( ) ) { MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( F -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( F , TM ) : getObjFileLowering ( ) . getSectionForFunctionDescriptor ( FSym ) ) ; FSym -> setContainingCsect ( Csect ) ; } return MCSymbolRefExpr :: create ( FSym -> getContainingCsect ( ) -> getQualNameSymbol ( ) , OutContext ) ; } return PPCAsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> unsigned AArch64InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: LDRWui : case AArch64 :: LDRXui : case AArch64 :: LDRBui : case AArch64 :: LDRHui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static ARMCC :: CondCodes getPredicate ( const MCInst & Inst , const MCInstrInfo & Info , unsigned & PredReg ) { const MCInstrDesc & Desc = Info . get ( Inst . getOpcode ( ) ) ; int PIdx = Desc . findFirstPredOperandIdx ( ) ; if ( PIdx == - 1 ) { PredReg = 0 ; return ARMCC :: AL ; } PredReg = Inst . getOperand ( PIdx + 1 ) . getReg ( ) ; return static_cast < ARMCC :: CondCodes > ( Inst . getOperand ( PIdx ) . getImm ( ) ) ; } </s>

Returns the comparison predicate underlying the intrinsic .


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
ModeSize
,
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
,
unsigned
FrontendSize
=
0
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
std
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
ModeSize
=
ModeSize
;
Res
->
Mem
.
FrontendSize
=
FrontendSize
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; if ( Subtarget . hasAVX512 ( ) ) { const unsigned NumElts = VT . getVectorNumElements ( ) ; EVT LegalVT = VT ; while ( getTypeAction ( Context , LegalVT ) != TypeLegal ) LegalVT = getTypeToTransformTo ( Context , LegalVT ) ; if ( LegalVT . getSimpleVT ( ) . is512BitVector ( ) ) return EVT :: getVectorVT ( Context , MVT :: i1 , NumElts ) ; if ( LegalVT . getSimpleVT ( ) . isVector ( ) && Subtarget . hasVLX ( ) ) { MVT EltVT = LegalVT . getSimpleVT ( ) . getVectorElementType ( ) ; if ( Subtarget . hasBWI ( ) || EltVT . getSizeInBits ( ) >= 32 ) return EVT :: getVectorVT ( Context , MVT :: i1 , NumElts ) ; } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> unsigned getNumFixupKinds ( ) const override { return TOY :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> Optional < DestSourcePair > ARMBaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , int64_t & Offset ) const { int Sign = 1 ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == ARM :: SUBri ) Sign = - 1 ; else if ( Opcode != ARM :: ADDri ) return None ; if ( ! MI . getOperand ( 0 ) . isReg ( ) || ! MI . getOperand ( 1 ) . isReg ( ) || ! MI . getOperand ( 2 ) . isImm ( ) ) return None ; Offset = MI . getOperand ( 2 ) . getImm ( ) * Sign ; return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
void
mmix_asm_output_aligned_local
(
FILE
*
stream
,
const
char
*
name
,
int
size
,
int
align
)
{
switch_to_section
(
data_section
)
;
ASM_OUTPUT_ALIGN
(
stream
,
exact_log2
(
align
/
BITS_PER_UNIT
)
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\tLOC @+%d\n"
,
size
)
;
}
</s>


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return SP :: I0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; Subtarget = & F . getSubtarget < SparcSubtarget > ( ) ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> virtual const X86Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FJ != FE ; ++ FI , ++ FJ ) { Changed |= runOnMachineBasicBlock ( * FI , * FJ ) ; } } return Changed ; } </s>


<s> void thumb1_gen_const_int_rtl ( rtx dst , HOST_WIDE_INT op1 ) { thumb1_const_rtl t ( dst ) ; thumb1_gen_const_int_1 ( t , op1 ) ; } </s>

Proxies for thumb1.md , since the thumb1_const_print and thumb1_const_rtl classes are not exported .


<s> static void vector_init_bshuffle ( rtx target , rtx elt , machine_mode mode , machine_mode inner_mode ) { rtx t1 , final_insn , sel ; int bmask ; t1 = gen_reg_rtx ( mode ) ; elt = convert_modes ( SImode , inner_mode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; switch ( mode ) { case V2SImode : final_insn = gen_bshufflev2si_vis ( target , t1 , t1 ) ; bmask = 0x45674567 ; break ; case V4HImode : final_insn = gen_bshufflev4hi_vis ( target , t1 , t1 ) ; bmask = 0x67676767 ; break ; case V8QImode : final_insn = gen_bshufflev8qi_vis ( target , t1 , t1 ) ; bmask = 0x77777777 ; break ; default : gcc_unreachable ( ) ; } sel = force_reg ( SImode , GEN_INT ( bmask ) ) ; emit_insn ( gen_bmasksi_vis ( gen_rtx_REG ( SImode , 0 ) , sel , const0_rtx ) ) ; emit_insn ( final_insn ) ; } </s>

Subroutine of sparc_expand_vector_init . Emit code to initialize all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn . MODE and INNER_MODE are the modes describing TARGET .


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static rtx pru_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { rtx return_rtx = NULL_RTX ; int regi = pru_function_arg_regi ( cum_v , arg . mode , arg . type , arg . named ) ; if ( regi >= 0 ) return_rtx = gen_rtx_REG ( arg . mode , regi ) ; return return_rtx ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . ARG is a description of the argument .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilderBase & Builder , Type * ValueTy , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValueTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , ValueTy ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> static bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) return true ; return false ; } </s>


<s> void AArch64PassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createAArch64PreLegalizerCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .