<s> static unsigned int aarch64_in_loop_reduction_latency ( vec_info * vinfo , stmt_vec_info stmt_info , tree vectype , unsigned int vec_flags ) { const cpu_vector_cost * vec_costs = aarch64_tune_params . vec_costs ; const sve_vec_cost * sve_costs = nullptr ; if ( vec_flags & VEC_ANY_SVE ) sve_costs = aarch64_tune_params . vec_costs -> sve ; if ( sve_costs ) { unsigned int latency = aarch64_sve_in_loop_reduction_latency ( vinfo , stmt_info , vectype , sve_costs ) ; if ( latency ) return latency ; } if ( vec_flags == 0 ) { if ( FLOAT_TYPE_P ( vectype ) ) return vec_costs -> scalar_fp_stmt_cost ; return vec_costs -> scalar_int_stmt_cost ; } const simd_vec_cost * simd_costs = aarch64_simd_vec_costs_for_flags ( vec_flags ) ; if ( FLOAT_TYPE_P ( vectype ) ) return simd_costs -> fp_stmt_cost ; return simd_costs -> int_stmt_cost ; } </s>

STMT_INFO describes a loop-carried operation in the original scalar code that we are considering implementing as a reduction . Return one of the following values , depending on VEC_FLAGS : - If VEC_FLAGS is zero , return the loop carry latency of the original scalar operation . - If VEC_FLAGS & VEC_ADVSIMD , return the loop carry latency of the the Advanced SIMD implementation . - If VEC_FLAGS & VEC_ANY_SVE , return the loop carry latency of the SVE implementation . VECTYPE is the type of vector that the vectorizer is considering using for STMT_INFO , which might be different from the type of vector described by VEC_FLAGS .


<s> static int rs6000_cpu_name_lookup ( const char * name ) { size_t i ; if ( name != NULL ) { for ( i = 0 ; i < ARRAY_SIZE ( processor_target_table ) ; i ++ ) if ( ! strcmp ( name , processor_target_table [ i ] . name ) ) return ( int ) i ; } return - 1 ; } </s>

Look up a processor name for -mcpu=xxx and -mtune=xxx . Return -1 if the name is invalid .


<s> char * aarch64_output_sve_vector_inc_dec ( const char * operands , rtx x ) { int factor ; unsigned int nelts_per_vq ; if ( ! aarch64_sve_vector_inc_dec_immediate_p ( x , & factor , & nelts_per_vq ) ) gcc_unreachable ( ) ; if ( factor < 0 ) return aarch64_output_sve_cnt_immediate ( "dec" , operands , AARCH64_SV_ALL , - factor , nelts_per_vq ) ; else return aarch64_output_sve_cnt_immediate ( "inc" , operands , AARCH64_SV_ALL , factor , nelts_per_vq ) ; } </s>

Return the asm template for an SVE vector INC or DEC instruction . OPERANDS gives the operands before the vector count and X is the value of the vector count operand itself .


<s> bool ARM64TargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Ptr . getNode ( ) , Base , Offset , AM , IsInc , DAG ) ) return false ; AM = IsInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s>
bool
MipsConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
4
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

Mips
Mips
4
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> bool rx_fuse_in_memory_bitop ( rtx * operands , rtx_insn * curr_insn , rtx ( * gen_insn ) ( rtx , rtx ) ) { rtx op2_reg = SUBREG_P ( operands [ 2 ] ) ? SUBREG_REG ( operands [ 2 ] ) : operands [ 2 ] ; set_of_reg op2_def = rx_find_set_of_reg ( op2_reg , curr_insn , prev_nonnote_nondebug_insn_bb ) ; if ( op2_def . set_src == NULL_RTX || ! MEM_P ( op2_def . set_src ) || GET_MODE ( op2_def . set_src ) != QImode || ! rx_is_restricted_memory_address ( XEXP ( op2_def . set_src , 0 ) , GET_MODE ( op2_def . set_src ) ) || reg_used_between_p ( operands [ 2 ] , op2_def . insn , curr_insn ) || ! rx_reg_dead_or_unused_after_insn ( curr_insn , REGNO ( op2_reg ) ) ) return false ; rtx mem = op2_def . set_src ; if ( GET_CODE ( XEXP ( mem , 0 ) ) == POST_INC || GET_CODE ( XEXP ( mem , 0 ) ) == PRE_INC || GET_CODE ( XEXP ( mem , 0 ) ) == POST_DEC || GET_CODE ( XEXP ( mem , 0 ) ) == PRE_DEC ) return false ; rtx_insn * op0_use = rx_find_use_of_reg ( operands [ 0 ] , curr_insn , next_nonnote_nondebug_insn_bb ) ; if ( op0_use == NULL || ! ( GET_CODE ( PATTERN ( op0_use ) ) == SET && RX_REG_P ( XEXP ( PATTERN ( op0_use ) , 1 ) ) && reg_overlap_mentioned_p ( operands [ 0 ] , XEXP ( PATTERN ( op0_use ) , 1 ) ) && rtx_equal_p ( mem , XEXP ( PATTERN ( op0_use ) , 0 ) ) ) || ! rx_reg_dead_or_unused_after_insn ( op0_use , REGNO ( operands [ 0 ] ) ) || reg_set_between_p ( operands [ 2 ] , curr_insn , op0_use ) ) return false ; for ( rtx_insn * i = next_nonnote_nondebug_insn_bb ( op2_def . insn ) ; i != NULL && i != op0_use ; i = next_nonnote_nondebug_insn_bb ( i ) ) if ( volatile_insn_p ( PATTERN ( i ) ) || CALL_P ( i ) ) return false ; emit_insn ( gen_insn ( mem , gen_lowpart ( QImode , operands [ 1 ] ) ) ) ; set_insn_deleted ( op2_def . insn ) ; set_insn_deleted ( op0_use ) ; return true ; } </s>

Try to fuse the current bit-operation insn with the surrounding memory load and store .


<s> unsigned getNumFixupKinds ( ) const override { return Sparc :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


"-fsplit-stack does not support fastcall with "

"-fsplit-stack does not support 2 register "

"-fsplit-stack does not support 3 register parameters"

Return a scratch register to use in the split stack prologue . The split stack prologue is used for -fsplit-stack . It is the first instructions in the function , even before the regular prologue . The scratch register can be any caller-saved register which is not used for parameters or for the static chain .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
void
dump
(
)
{
cerr
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
cerr
<<
"Base.Reg "
;
if
(
Base
.
Reg
.
getNode
(
)
!=
0
)
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
cerr
<<
" Scale"
<<
Scale
<<
'\n'
;
cerr
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" Disp "
<<
Disp
<<
'\n'
;
cerr
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
'\n'
;
cerr
<<
"ES "
;
if
(
ES
)
cerr
<<
ES
;
else
cerr
<<
"nul"
;
cerr
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base.Reg "
0
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
0
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" JT"
" Align"


"const void *const __offload_funcs_end[0]\n"

"__attribute__ ((__used__, visibility (\"hidden\"),\n"

"section (\".gnu.offload_funcs\"))) = { };\n\n"

"const void *const __offload_vars_end[0]\n"

"section (\".gnu.offload_vars\"))) = { };\n"

Generates object file with __offload_ * _end symbols for the target library .


<s> rtx rs6000_address_for_fpconvert ( rtx x ) { rtx addr ; gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , 0 ) ; if ( can_create_pseudo_p ( ) && ! legitimate_indirect_address_p ( addr , reload_completed ) && ! legitimate_indexed_address_p ( addr , reload_completed ) ) { if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , copy_addr_to_reg ( addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX that only take reg+reg addressing .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Lower Tile Copy"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool isReg ( ) const override { return Kind == k_Register && ! Reg . isVector ; } </s>


<s> void PPCPassConfig :: addPreEmitPass2 ( ) { addPass ( createPPCExpandAtomicPseudoPass ( ) ) ; addPass ( createPPCBranchSelectionPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> tree builtin_decl ( unsigned int code , bool ) { if ( code >= vec_safe_length ( registered_functions ) ) return error_mark_node ; return ( * registered_functions ) [ code ] -> decl ; } </s>

Return the function decl with RVV function subcode CODE , or error_mark_node if no such function exists .


<s> static rtx arm_gen_load_multiple_1 ( int count , int * regs , rtx * mems , rtx basereg , HOST_WIDE_INT wback_offset ) { int i = 0 , j ; rtx result ; if ( ! multiple_operation_profitable_p ( false , count , 0 ) ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( SImode , regs [ i ] ) , mems [ i ] ) ; if ( wback_offset != 0 ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != 0 ? 1 : 0 ) ) ) ; if ( wback_offset != 0 ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( VOIDmode , basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) XVECEXP ( result , 0 , i ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regs [ j ] ) , mems [ j ] ) ; return result ; } </s>

Generate a load-multiple instruction . COUNT is the number of loads in the instruction ; REGS and MEMS are arrays containing the operands . BASEREG is the base register to be used in addressing the memory operands . WBACK_OFFSET is nonzero if the instruction should update the base register .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> unsigned SHUXIRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return SHUXI :: SP ; } </s>


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
const
SmallVectorImpl
<
MachineOperand
>
&
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
TM
.
getSubtargetImpl
(
)
->
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
->
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
;
return
true
;
}
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> int eligible_for_sibcall_delay ( rtx_insn * trial ) { rtx pat ; if ( get_attr_in_branch_delay ( trial ) == IN_BRANCH_DELAY_FALSE ) return 0 ; if ( ! NONJUMP_INSN_P ( trial ) ) return 0 ; pat = PATTERN ( trial ) ; if ( sparc_leaf_function_p || TARGET_FLAT ) { if ( LEAF_SIBCALL_SLOT_RESERVED_P ) return 0 ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , 1 ) , pat ) ) return 0 ; return 1 ; } if ( GET_CODE ( pat ) != SET ) return 0 ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= 8 && REGNO ( SET_DEST ( pat ) ) < 24 ) || ! SPARC_INT_REG_P ( REGNO ( SET_DEST ( pat ) ) ) ) return 0 ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , 15 ) , pat ) ) return 0 ; return eligible_for_restore_insn ( trial , false ) ; } </s>

Return nonzero if TRIAL can go into the sibling call 's delay slot .


"Unable to create a unique discriminator in "

". This is likely due to a large macro expansion.\n"

runOnMachineFunction - Emit the function body .


<s> bool invalid_e500_subreg ( rtx op , machine_mode mode ) { if ( TARGET_E500_DOUBLE ) { if ( GET_CODE ( op ) == SUBREG && ( mode == SImode || mode == DImode || mode == TImode || mode == DDmode || mode == TDmode || mode == PTImode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DFmode || GET_MODE ( SUBREG_REG ( op ) ) == TFmode ) ) return true ; if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ; } if ( TARGET_SPE && GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && SPE_VECTOR_MODE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) return true ; return false ; } </s>

Return TRUE if OP is an invalid SUBREG operation on the e500 .


<s> bool ix86_expand_int_addcc ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx flags ; rtx ( * insn ) ( rtx , rtx , rtx , rtx , rtx ) ; rtx compare_op ; rtx val = const0_rtx ; bool fpcmp = false ; machine_mode mode ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( operands [ 3 ] != const1_rtx && operands [ 3 ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , 0 ) ; if ( GET_MODE ( flags ) == CCFPmode || GET_MODE ( flags ) == CCFPUmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ 0 ] ) ; if ( ( code == LTU ) == ( operands [ 3 ] == constm1_rtx ) ) { switch ( mode ) { case QImode : insn = gen_subqi3_carry ; break ; case HImode : insn = gen_subhi3_carry ; break ; case SImode : insn = gen_subsi3_carry ; break ; case DImode : insn = gen_subdi3_carry ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case QImode : insn = gen_addqi3_carry ; break ; case HImode : insn = gen_addhi3_carry ; break ; case SImode : insn = gen_addsi3_carry ; break ; case DImode : insn = gen_adddi3_carry ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( insn ( operands [ 0 ] , operands [ 2 ] , val , flags , compare_op ) ) ; return true ; } </s>

Expand conditional increment or decrement using adb/sbb instructions . The default case using setcc followed by the conditional move can be done by generic code .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> void finish ( ) override { for ( auto * Sym : UpdateOther ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> void MipsTargetStreamer :: emitLoadWithImmOffset ( unsigned Opcode , unsigned DstReg , unsigned BaseReg , int64_t Offset , unsigned TmpReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { if ( isInt < 16 > ( Offset ) ) { emitRRI ( Opcode , DstReg , BaseReg , Offset , IDLoc , STI ) ; return ; } unsigned LoOffset = Offset & 0x0000ffff ; unsigned HiOffset = ( Offset & 0xffff0000 ) >> 16 ; if ( LoOffset & 0x8000 ) HiOffset ++ ; emitRI ( Mips :: LUi , TmpReg , HiOffset , IDLoc , STI ) ; if ( BaseReg != Mips :: ZERO ) emitRRR ( Mips :: ADDu , TmpReg , TmpReg , BaseReg , IDLoc , STI ) ; emitRRI ( Opcode , DstReg , TmpReg , LoOffset , IDLoc , STI ) ; } </s>

Emit a load instruction with an immediate offset .


<s> static bool rx_small_data_operand ( rtx op ) { if ( rx_small_data_limit == 0 ) return false ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_SMALL_P ( op ) ; return false ; } </s>

Return true if OP is a reference to an object in a small data area .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> static bool ix86_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) return true ; if ( ( TARGET_MMX || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE ( mode ) ) return true ; if ( ( TARGET_3DNOW || TARGET_MMX_WITH_SSE ) && VALID_MMX_REG_MODE_3DNOW ( mode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> bool MipsTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; MipsCCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Mips ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = aarch64_reg_save_mode ( cfun -> decl , regno1 ) ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 2 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push registers numbered REGNO1 and REGNO2 to the stack , adjusting the stack pointer by ADJUSTMENT .


<s> Register OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( Mips :: SP ) ) ; unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return combineVECTOR_SHUFFLE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool prefixed_load_p ( rtx_insn * insn ) { extract_insn_cached ( insn ) ; if ( recog_data . n_operands < 2 ) return false ; rtx reg = recog_data . operand [ 0 ] ; rtx mem = recog_data . operand [ 1 ] ; if ( ! REG_P ( reg ) && ! SUBREG_P ( reg ) ) return false ; if ( ! MEM_P ( mem ) ) return false ; if ( get_attr_indexed ( insn ) == INDEXED_YES || get_attr_update ( insn ) == UPDATE_YES ) return false ; enum non_prefixed_form non_prefixed ; machine_mode reg_mode = GET_MODE ( reg ) ; machine_mode mem_mode = GET_MODE ( mem ) ; if ( mem_mode == SImode && reg_mode == DImode && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) non_prefixed = NON_PREFIXED_DS ; else non_prefixed = reg_to_non_prefixed ( reg , mem_mode ) ; if ( non_prefixed == NON_PREFIXED_X && is_lfs_stfs_insn ( insn ) ) return address_is_prefixed ( XEXP ( mem , 0 ) , mem_mode , NON_PREFIXED_DEFAULT ) ; else return address_is_prefixed ( XEXP ( mem , 0 ) , mem_mode , non_prefixed ) ; } </s>

Whether a load instruction is a prefixed instruction . This is called from the prefixed attribute processing .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: Writer < support :: little > ( OS ) . write < uint32_t > ( Binary ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge && ! getARMSubtarget ( ) . isTargetNaCl ( ) ) addPass ( createGlobalMergePass ( TM -> getTargetLowering ( ) ) ) ; return false ; } </s>


"The function works only with LEA instructions"


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> static void mips_block_move_loop ( rtx dest , rtx src , HOST_WIDE_INT length , HOST_WIDE_INT bytes_per_iter ) { rtx_code_label * label ; rtx src_reg , dest_reg , final_src , test ; HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; mips_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; mips_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; mips_block_move_straight ( dest , src , bytes_per_iter ) ; mips_emit_move ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; mips_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test , src_reg , final_src , label ) ) ; else emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; if ( leftover ) mips_block_move_straight ( dest , src , leftover ) ; } </s>

Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES per iteration . LENGTH must be at least MAX_MOVE_BYTES . Assume that the memory regions do not overlap .


<s> void AArch64MacroFusion :: apply ( ScheduleDAGInstrs * DAGInstrs ) { ScheduleDAGMI * DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; for ( SUnit & ASU : DAG -> SUnits ) scheduleAdjacentImpl ( DAG , & ASU , ASU . Succs , false ) ; scheduleAdjacentImpl ( DAG , & DAG -> ExitSU , DAG -> ExitSU . Preds , true ) ; } </s>

Apply the profile inference algorithm for a given function .


<s> bool GeneralShuffle :: add ( SDValue Op , unsigned Elem ) { unsigned BytesPerElement = VT . getVectorElementType ( ) . getStoreSize ( ) ; EVT FromVT = Op . getNode ( ) ? Op . getValueType ( ) : VT ; unsigned FromBytesPerElement = FromVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( FromBytesPerElement < BytesPerElement ) return false ; unsigned Byte = ( ( Elem * FromBytesPerElement ) % SystemZ :: VectorBytes + ( FromBytesPerElement - BytesPerElement ) ) ; while ( Op . getNode ( ) ) { if ( Op . getOpcode ( ) == ISD :: BITCAST ) Op = Op . getOperand ( 0 ) ; else if ( Op . getOpcode ( ) == ISD :: VECTOR_SHUFFLE && Op . hasOneUse ( ) ) { SmallVector < int , SystemZ :: VectorBytes > OpBytes ; if ( ! getVPermMask ( Op , OpBytes ) ) break ; int NewByte ; if ( ! getShuffleInput ( OpBytes , Byte , BytesPerElement , NewByte ) ) break ; if ( NewByte < 0 ) { addUndef ( ) ; return true ; } Op = Op . getOperand ( unsigned ( NewByte ) / SystemZ :: VectorBytes ) ; Byte = unsigned ( NewByte ) % SystemZ :: VectorBytes ; } else if ( Op . isUndef ( ) ) { addUndef ( ) ; return true ; } else break ; } unsigned OpNo = 0 ; for ( ; OpNo < Ops . size ( ) ; ++ OpNo ) if ( Ops [ OpNo ] == Op ) break ; if ( OpNo == Ops . size ( ) ) Ops . push_back ( Op ) ; unsigned Base = OpNo * SystemZ :: VectorBytes + Byte ; for ( unsigned I = 0 ; I < BytesPerElement ; ++ I ) Bytes . push_back ( Base + I ) ; return true ; } </s>


<s> void mips_expand_before_return ( void ) { if ( TARGET_CALL_CLOBBERED_GP ) emit_clobber ( pic_offset_table_rtx ) ; } </s>

Emit any instructions needed before a return .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool LanaiRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : nullptr ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const LC3RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool X86TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; if ( ResVT . getVectorElementType ( ) == MVT :: i1 ) return Index == 0 || ( ( ResVT . getSizeInBits ( ) == SrcVT . getSizeInBits ( ) * 2 ) && ( Index == ResVT . getVectorNumElements ( ) ) ) ; return ( Index % ResVT . getVectorNumElements ( ) ) == 0 ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } if ( MI . getOpcode ( ) == AArch64 :: CompilerBarrier || MI . getOpcode ( ) == AArch64 :: SPACE || MI . getOpcode ( ) == AArch64 :: EH_SjLj_Setup ) { return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint32_t > ( OS , Binary , support :: little ) ; ++ MCNumEmitted ; } </s>


<s> void clear ( ) { TagStores . clear ( ) ; } </s>


<s> void ia64_expand_compare ( rtx * expr , rtx * op0 , rtx * op1 ) { enum rtx_code code = GET_CODE ( * expr ) ; rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = 1 , QCMP_UNORD = 2 , QCMP_EQ = 4 , QCMP_LT = 8 , QCMP_GT = 16 } ; int magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , 0 , LCT_CONST , DImode , 3 , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code = NE ; } * expr = gen_rtx_fmt_ee ( code , VOIDmode , cmp , const0_rtx ) ; * op0 = cmp ; * op1 = const0_rtx ; } </s>

Emit comparison instruction if necessary , returning the expression that holds the compare result in the proper mode .


<s> static rtx sh_delegitimize_address ( rtx orig_x ) { rtx x , y ; orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == CONST ) { y = XEXP ( x , 0 ) ; if ( GET_CODE ( y ) == UNSPEC ) { if ( XINT ( y , 1 ) == UNSPEC_GOT || XINT ( y , 1 ) == UNSPEC_GOTOFF || XINT ( y , 1 ) == UNSPEC_SYMOFF ) return XVECEXP ( y , 0 , 0 ) ; else if ( XINT ( y , 1 ) == UNSPEC_PCREL_SYMOFF ) { if ( GET_CODE ( XVECEXP ( y , 0 , 0 ) ) == CONST ) { rtx symplt = XEXP ( XVECEXP ( y , 0 , 0 ) , 0 ) ; if ( GET_CODE ( symplt ) == UNSPEC && ( XINT ( symplt , 1 ) == UNSPEC_PLT || XINT ( symplt , 1 ) == UNSPEC_PCREL ) ) return XVECEXP ( symplt , 0 , 0 ) ; } } else if ( TARGET_SHMEDIA && ( XINT ( y , 1 ) == UNSPEC_EXTRACT_S16 || XINT ( y , 1 ) == UNSPEC_EXTRACT_U16 ) ) { rtx offset = XVECEXP ( y , 0 , 1 ) ; x = gen_rtx_PLUS ( Pmode , XVECEXP ( y , 0 , 0 ) , offset ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } } } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s>
static
void
thumb_pop
(
FILE
*
f
,
unsigned
long
mask
)
{
int
regno
;
int
lo_mask
=
mask
&
0xFF
;
int
pushed_words
=
0
;
gcc_assert
(
mask
)
;
if
(
lo_mask
==
0
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
thumb_exit
(
f
,
1
)
;
return
;
}
fprintf
(
f
,
"\tpop\t{"
)
;
for
(
regno
=
0
;
regno
<=
LAST_LO_REGNUM
;
regno
++
,
lo_mask
>>=
1
)
{
if
(
lo_mask
&
1
)
{
asm_fprintf
(
f
,
"%r"
,
regno
)
;
if
(
(
lo_mask
&
~
1
)
!=
0
)
fprintf
(
f
,
", "
)
;
pushed_words
++
;
}
}
if
(
mask
&
(
1
<<
PC_REGNUM
)
)
{
if
(
TARGET_INTERWORK
||
TARGET_BACKTRACE
||
crtl
->
calls_eh_return
||
IS_CMSE_ENTRY
(
arm_current_func_type
(
)
)
)
{
fprintf
(
f
,
"}\n"
)
;
thumb_exit
(
f
,
1
)
;
return
;
}
else
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
PC_REGNUM
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
}
</s>

Emit code to push or pop registers to or from the stack . F is the assembly file . MASK is the registers to pop .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
RM
(
_RM
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> void MipsRegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { MachineInstr & MI = OpdMapper . getMI ( ) ; InstListTy NewInstrs ; MachineFunction * MF = MI . getMF ( ) ; MachineRegisterInfo & MRI = OpdMapper . getMRI ( ) ; const LegalizerInfo & LegInfo = * MF -> getSubtarget ( ) . getLegalizerInfo ( ) ; InstManager NewInstrObserver ( NewInstrs ) ; MachineIRBuilder B ( MI , NewInstrObserver ) ; LegalizerHelper Helper ( * MF , NewInstrObserver , B ) ; LegalizationArtifactCombiner ArtCombiner ( B , MF -> getRegInfo ( ) , LegInfo ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_PHI : case TargetOpcode :: G_SELECT : case TargetOpcode :: G_IMPLICIT_DEF : { Helper . narrowScalar ( MI , 0 , LLT :: scalar ( 32 ) ) ; while ( ! NewInstrs . empty ( ) ) { MachineInstr * NewMI = NewInstrs . pop_back_val ( ) ; if ( auto * Unmerge = dyn_cast < GUnmerge > ( NewMI ) ) combineAwayG_UNMERGE_VALUES ( ArtCombiner , * Unmerge , NewInstrObserver ) ; else if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) continue ; else setRegBank ( * NewMI , MRI ) ; } return ; } case TargetOpcode :: G_UNMERGE_VALUES : combineAwayG_UNMERGE_VALUES ( ArtCombiner , cast < GUnmerge > ( MI ) , NewInstrObserver ) ; return ; default : break ; } return applyDefaultMapping ( OpdMapper ) ; } </s>


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr ) const override { return true ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> static bool or1k_return_in_memory ( const_tree type , const_tree ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > ( 2 * UNITS_PER_WORD ) ) ; } </s>

worker function for TARGET_RETURN_IN_MEMORY . Returns true if the argument of TYPE should be returned in memory . On OpenRISC this is any value larger than 64-bits .


<s> static rtx aarch64_strip_shift ( rtx x ) { rtx op = x ; if ( ( GET_CODE ( op ) == ASHIFT || GET_CODE ( op ) == ASHIFTRT || GET_CODE ( op ) == LSHIFTRT || GET_CODE ( op ) == ROTATERT || GET_CODE ( op ) == ROTATE ) && CONST_INT_P ( XEXP ( op , 1 ) ) ) return XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == MULT && CONST_INT_P ( XEXP ( op , 1 ) ) && ( ( unsigned ) exact_log2 ( INTVAL ( XEXP ( op , 1 ) ) ) ) < 64 ) return XEXP ( op , 0 ) ; return x ; } </s>

Helper function for rtx cost calculation . Strip a shift expression from X . Returns the inner operand if successful , or the original expression on failure .


<s> TargetPassConfig * LEGTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LEGPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
std
::
unique_ptr
<
DLXOperand
>
DLXAsmParser
::
parseIdentifier
(
)
{
SMLoc
Start
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
SMLoc
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
const
MCExpr
*
Res
,
*
RHS
=
nullptr
;
DLXMCExpr
::
VariantKind
Kind
=
DLXMCExpr
::
VK_DLX_None
;
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
Identifier
)
return
nullptr
;
StringRef
Identifier
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
if
(
Identifier
.
equals_lower
(
"hi"
)
)
Kind
=
DLXMCExpr
::
VK_DLX_ABS_HI
;
else
if
(
Identifier
.
equals_lower
(
"lo"
)
)
Kind
=
DLXMCExpr
::
VK_DLX_ABS_LO
;
if
(
Kind
!=
DLXMCExpr
::
VK_DLX_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
LParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected '('"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
}
if
(
Lexer
.
getKind
(
)
==
AsmToken
::
Plus
&&
Parser
.
parseExpression
(
RHS
)
)
return
nullptr
;
if
(
Kind
!=
DLXMCExpr
::
VK_DLX_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
RParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected ')'"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
}
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
MCSymbol
*
Sym
=
getContext
(
)
.
getOrCreateSymbol
(
Identifier
)
;
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Sym
,
getContext
(
)
)
;
Res
=
DLXMCExpr
::
create
(
Kind
,
Expr
,
getContext
(
)
)
;
if
(
RHS
)
Res
=
MCBinaryExpr
::
createAdd
(
Res
,
RHS
,
getContext
(
)
)
;
return
DLXOperand
::
createImm
(
Res
,
Start
,
End
)
;
}
</s>

Parse an identifier or string ( as a quoted identifier ) and set Res to the identifier contents .

DLX
DLX
DLX
1
DLX
DLX
DLX
"hi"
DLX
DLX
"lo"
DLX
DLX
DLX
DLX
"Expected '('"
DLX
DLX
"Expected ')'"
1
DLX
DLXOperand::createImm


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static void sparc_asm_function_epilogue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { rtx insn , last_real_insn ; insn = get_last_insn ( ) ; last_real_insn = prev_real_insn ( insn ) ; if ( last_real_insn && GET_CODE ( last_real_insn ) == INSN && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE ) last_real_insn = XVECEXP ( PATTERN ( last_real_insn ) , 0 , 0 ) ; if ( last_real_insn && GET_CODE ( last_real_insn ) == CALL_INSN ) fputs ( "\tnop\n" , file ) ; sparc_output_deferred_case_vectors ( ) ; } </s>

This function generates the assembly code for function exit .


<s> static int thumb1_extra_regs_pushed ( arm_stack_offsets * offsets , bool for_prologue ) { HOST_WIDE_INT amount ; unsigned long live_regs_mask = offsets -> saved_regs_mask ; unsigned long l_mask = live_regs_mask & ( for_prologue ? 0x40ff : 0xff ) ; unsigned long high_regs_pushed = bit_count ( live_regs_mask & 0x0f00 ) ; int n_free , reg_base , size ; if ( ! for_prologue && frame_pointer_needed ) amount = offsets -> locals_base - offsets -> saved_regs ; else amount = offsets -> outgoing_args - offsets -> saved_regs ; if ( ! optimize_size && amount != 512 ) return 0 ; if ( high_regs_pushed != 0 ) return 0 ; if ( l_mask == 0 && ( for_prologue || TARGET_BACKTRACE || ( live_regs_mask & 1 << LR_REGNUM ) == 0 || TARGET_INTERWORK || crtl -> args . pretend_args_size != 0 ) ) return 0 ; if ( for_prologue && ( ( flag_pic && arm_pic_register != INVALID_REGNUM ) || ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) ) ) return 0 ; reg_base = 0 ; n_free = 0 ; if ( ! for_prologue ) { size = arm_size_return_regs ( ) ; reg_base = ARM_NUM_INTS ( size ) ; live_regs_mask >>= reg_base ; } while ( reg_base + n_free < 8 && ! ( live_regs_mask & 1 ) && ( for_prologue || call_used_regs [ reg_base + n_free ] ) ) { live_regs_mask >>= 1 ; n_free ++ ; } if ( n_free == 0 ) return 0 ; gcc_assert ( amount / 4 * 4 == amount ) ; if ( amount >= 512 && ( amount - n_free * 4 ) < 512 ) return ( amount - 508 ) / 4 ; if ( amount <= n_free * 4 ) return amount / 4 ; return 0 ; } </s>

Given the stack offsets and register mask in OFFSETS , decide how many additional registers to push instead of subtracting a constant from SP . For epilogues the principle is the same except we use pop . FOR_PROLOGUE indicates which we 're generating .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static bool save_local_or_in_reg_p ( unsigned int regno , int leaf_function ) { if ( ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( got_register_rtx && regno == REGNO ( got_register_rtx ) ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM ) ) return true ; return false ; } </s>

Return whether REGNO , a local or in register , must be saved/restored .


<s> void SystemZMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize ( ) ; unsigned ShiftValue = ( Size * 8 ) - 8 ; for ( unsigned I = 0 ; I != Size ; ++ I ) { OS << uint8_t ( Bits >> ShiftValue ) ; ShiftValue -= 8 ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> unsigned getNumFixupKinds ( ) const { return OR1K :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
TargetCostKind
CostKind
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
if
(
CostKind
!=
TTI
::
TCK_RecipThroughput
)
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
,
Args
,
CxtI
)
;
int
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> unsigned int nds32_debugger_regno ( unsigned int regno ) { if ( NDS32_IS_FPR_REGNUM ( regno ) ) return regno + 4 ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MF . setHasWinCFI ( false ) ; const Function & F = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( F . getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static bool crx_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { if ( TYPE_MODE ( type ) == BLKmode ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 8 ) ; } else return false ; } </s>

Implements hook TARGET_RETURN_IN_MEMORY .


"%Klane index must be a constant immediate"

"%Ktotal size and element size must be a non-zero constant immediate"

Expand an AArch64 AdvSIMD builtin ( intrinsic ) .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( MipsTargetMachine & TM ) { if ( TM . getSubtargetImpl ( ) -> inMips16Mode ( ) ) return llvm :: createMips16TargetLowering ( TM ) ; return llvm :: createMipsSETargetLowering ( TM ) ; } </s>


<s> EVT ARMTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == MVT :: v2i64 || VT == MVT :: v4i32 || VT == MVT :: v8i16 || VT == MVT :: v16i8 ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT == MVT :: v2f64 || VT == MVT :: v4f32 || VT == MVT :: v8f16 ) ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool X86Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; CriticalPathRCs . clear ( ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s>
bool
ARMCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
)
const
{
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
auto
const
&
ST
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
;
unsigned
Opcode
=
ST
.
getReturnOpcode
(
)
;
auto
Ret
=
MIRBuilder
.
buildInstrNoInsert
(
Opcode
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
if
(
!
lowerReturnVal
(
MIRBuilder
,
Val
,
VRegs
,
Ret
)
)
return
false
;
MIRBuilder
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

ARM
ARM
"Return value without a vreg"
ARM
ARMCC::AL


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SystemZMCInstLower Lower ( Mang , MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; switch ( MI -> getOpcode ( ) ) { case SystemZ :: Return : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R14D ) ; break ; case SystemZ :: CallBRASL : LoweredMI = MCInstBuilder ( SystemZ :: BRASL ) . addReg ( SystemZ :: R14D ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBASR : LoweredMI = MCInstBuilder ( SystemZ :: BASR ) . addReg ( SystemZ :: R14D ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; break ; case SystemZ :: CallJG : LoweredMI = MCInstBuilder ( SystemZ :: JG ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBR : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R1D ) ; break ; case SystemZ :: IILF64 : LoweredMI = MCInstBuilder ( SystemZ :: IILF ) . addReg ( SystemZMC :: getRegAsGR32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: IIHF64 : LoweredMI = MCInstBuilder ( SystemZ :: IIHF ) . addReg ( SystemZMC :: getRegAsGRH32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: RISBHH : case SystemZ :: RISBHL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBHG ) ; break ; case SystemZ :: RISBLH : case SystemZ :: RISBLL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBLG ) ; break ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRILow ( MI , SystemZ :: NAME ) ; break LOWER_LOW ( IILL ) ; LOWER_LOW ( IILH ) ; LOWER_LOW ( NILL ) ; LOWER_LOW ( NILH ) ; LOWER_LOW ( NILF ) ; LOWER_LOW ( OILL ) ; LOWER_LOW ( OILH ) ; LOWER_LOW ( OILF ) ; LOWER_LOW ( XILF ) ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRIHigh ( MI , SystemZ :: NAME ) ; break LOWER_HIGH ( IIHL ) ; LOWER_HIGH ( IIHH ) ; LOWER_HIGH ( NIHL ) ; LOWER_HIGH ( NIHH ) ; LOWER_HIGH ( NIHF ) ; LOWER_HIGH ( OIHL ) ; LOWER_HIGH ( OIHH ) ; LOWER_HIGH ( OIHF ) ; LOWER_HIGH ( XIHF ) ; default : Lower . lower ( MI , LoweredMI ) ; break ; } OutStreamer . EmitInstruction ( LoweredMI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAddressTypePromotion ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


<s> static void aarch64_emit_epilogue_components ( sbitmap components ) { aarch64_process_components ( components , false ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"FISC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void Cpu0PassConfig :: addPreRegAlloc ( ) { if ( ! Cpu0ReserveGP ) { addPass ( createCpu0EmitGPRestorePass ( getCpu0TargetMachine ( ) ) ) ; } return ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> int arm_legitimate_address_outer_p ( machine_mode mode , rtx x , RTX_CODE outer , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; if ( use_ldrd && GET_CODE ( x ) == POST_MODIFY && REG_P ( addend ) ) return 0 ; return ( ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) && arm_legitimate_index_p ( mode , addend , outer , strict_p ) ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( ( CONST_INT_P ( xop1 ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && arm_legitimate_index_p ( mode , xop0 , outer , strict_p ) ) ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( arm_address_register_rtx_p ( xop0 , strict_p ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid ARM state address operand .


<s> bool VETargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { return VT == MVT :: f32 || VT == MVT :: f64 ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static scalar_int_mode aarch64_sve_container_int_mode ( machine_mode mode ) { return int_mode_for_size ( aarch64_sve_container_bits ( mode ) , 0 ) . require ( ) ; } </s>

Return an integer element mode that contains exactly aarch64_sve_container_bits ( MODE ) bits . This is wider than aarch64_sve_element_int_mode if MODE is a partial vector , otherwise it 's the same .


<s> Align PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getCPUDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : case PPC :: DIR_PWR_FUTURE : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > 1 && ML -> getSubLoops ( ) . empty ( ) ) return Align ( 32 ) ; } const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return Align ( 32 ) ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
const
TargetRegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i64
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { bool fp = false ; machine_mode mode = TImode ; int index ; if ( vectype != NULL ) { fp = FLOAT_TYPE_P ( vectype ) ; mode = TYPE_MODE ( vectype ) ; } switch ( type_of_cost ) { case scalar_stmt : return fp ? ix86_cost -> addss : COSTS_N_INSNS ( 1 ) ; case scalar_load : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_load [ 0 ] : ix86_cost -> int_load [ 2 ] ) / 2 ; case scalar_store : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_store [ 0 ] : ix86_cost -> int_store [ 2 ] ) / 2 ; case vector_stmt : return ix86_vec_cost ( mode , fp ? ix86_cost -> addss : ix86_cost -> sse_op ) ; case vector_load : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return COSTS_N_INSNS ( ix86_cost -> sse_load [ index ] ) / 2 ; case vector_store : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return COSTS_N_INSNS ( ix86_cost -> sse_store [ index ] ) / 2 ; case vec_to_scalar : case scalar_to_vec : return ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; case unaligned_load : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return COSTS_N_INSNS ( ix86_cost -> sse_unaligned_load [ index ] ) / 2 ; case unaligned_store : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return COSTS_N_INSNS ( ix86_cost -> sse_unaligned_store [ index ] ) / 2 ; case vector_gather_load : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> gather_static + ix86_cost -> gather_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / 2 ) ; case vector_scatter_store : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> scatter_static + ix86_cost -> scatter_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / 2 ) ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; case vec_construct : { int n = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( GET_MODE_BITSIZE ( mode ) <= 128 ) return ( n - 1 ) * ix86_cost -> sse_op ; else if ( GET_MODE_BITSIZE ( mode ) == 256 ) return ( ( n - 2 ) * ix86_cost -> sse_op + ix86_vec_cost ( mode , ix86_cost -> addss ) ) ; else if ( GET_MODE_BITSIZE ( mode ) == 512 ) return ( ( n - 4 ) * ix86_cost -> sse_op + 3 * ix86_vec_cost ( mode , ix86_cost -> addss ) ) ; gcc_unreachable ( ) ; } default : gcc_unreachable ( ) ; } } </s>


<s> static tree ix86_stack_protect_guard ( void ) { if ( TARGET_SSP_TLS_GUARD ) { tree type_node = lang_hooks . types . type_for_mode ( ptr_mode , 1 ) ; int qual = ENCODE_QUAL_ADDR_SPACE ( ix86_stack_protector_guard_reg ) ; tree type = build_qualified_type ( type_node , qual ) ; tree t ; if ( global_options_set . x_ix86_stack_protector_guard_symbol_str ) { t = ix86_tls_stack_chk_guard_decl ; if ( t == NULL ) { rtx x ; t = build_decl ( UNKNOWN_LOCATION , VAR_DECL , get_identifier ( ix86_stack_protector_guard_symbol_str ) , type ) ; TREE_STATIC ( t ) = 1 ; TREE_PUBLIC ( t ) = 1 ; DECL_EXTERNAL ( t ) = 1 ; TREE_USED ( t ) = 1 ; TREE_THIS_VOLATILE ( t ) = 1 ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; x = DECL_RTL ( t ) ; RTX_FLAG ( x , used ) = 1 ; ix86_tls_stack_chk_guard_decl = t ; } } else { tree asptrtype = build_pointer_type ( type ) ; t = build_int_cst ( asptrtype , ix86_stack_protector_guard_offset ) ; t = build2 ( MEM_REF , asptrtype , t , build_int_cst ( asptrtype , 0 ) ) ; } return t ; } return default_stack_protect_guard ( ) ; } </s>

If using TLS guards , do n't waste time creating and expanding __stack_chk_guard decl and MEM as we are going to ignore it .


<s> int mmix_use_simple_return ( void ) { int regno ; int stack_space_to_allocate = ( crtl -> outgoing_args_size + crtl -> args . pretend_args_size + get_frame_size ( ) + 7 ) & ~ 7 ; if ( ! TARGET_USE_RETURN_INSN || ! reload_completed ) return 0 ; for ( regno = 255 ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return 0 ; if ( frame_pointer_needed ) stack_space_to_allocate += 8 ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_allocate += 16 ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_allocate += 8 ; return stack_space_to_allocate == 0 ; } </s>

Nonzero when the function epilogue is simple enough that a single `` POP % d,0 '' should be used even within the function .


<s> static bool rs6000_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > 4 && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 && ! FLOAT128_2REG_P ( mode ) ) return true ; return false ; } </s>


<s> static rtx arm_trampoline_adjust_address ( rtx addr ) { if ( TARGET_THUMB && ! TARGET_FDPIC ) addr = expand_simple_binop ( Pmode , IOR , addr , const1_rtx , NULL , 0 , OPTAB_LIB_WIDEN ) ; return addr ; } </s>

Thumb trampolines should be entered in thumb mode , so set the bottom bit of the address .


<s> StackOffset ( const StackOffset & Other ) : Bytes ( Other . Bytes ) { } </s>


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


<s> bool ARM64TargetLowering :: isLegalAddImmediate ( int64_t Immed ) const { if ( ( Immed >> 12 ) == 0 || ( ( Immed & 0xfff ) == 0 && Immed >> 24 == 0 ) ) return true ; return false ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> StringRef AArch64NamedImmMapper :: toString ( uint32_t Value , uint64_t FeatureBits , bool & Valid ) const { for ( unsigned i = 0 ; i < NumMappings ; ++ i ) { if ( Mappings [ i ] . isValueEqual ( Value , FeatureBits ) ) { Valid = true ; return Mappings [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s> TargetPassConfig * OpenRISCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new OpenRISCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_operation ( pat , VOIDmode ) || vzeroall_operation ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_upper_reg_found = false ; note_stores ( pat , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return mode ; } </s>

Calculate mode of upper 128bit AVX registers after the insn .


"Should be handled target independently"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void expand_small_cpymem_or_setmem ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int size , rtx done_label , bool issetmem ) { rtx_code_label * label = ix86_expand_aligntest ( count , size , false ) ; machine_mode mode = int_mode_for_size ( size * BITS_PER_UNIT , 1 ) . else_blk ( ) ; rtx modesize ; int n ; if ( issetmem ) { if ( ! vec_value ) { if ( GET_MODE ( value ) == VOIDmode && size > 8 ) mode = Pmode ; else if ( GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( GET_MODE ( value ) ) ) mode = GET_MODE ( value ) ; } else mode = GET_MODE ( vec_value ) , value = vec_value ; } else { if ( size >= 32 ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= 16 ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , count , 1 ) ; destmem = offset_address ( destmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; if ( ! issetmem ) { srcmem = offset_address ( srcmem , count , 1 ) ; srcmem = offset_address ( srcmem , GEN_INT ( - 2 * size ) , GET_MODE_SIZE ( mode ) ) ; } for ( n = 0 ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ; srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ; } destmem = offset_address ( destmem , modesize , GET_MODE_SIZE ( mode ) ) ; } emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; } </s>

Test if COUNT & SIZE is nonzero and if so , expand movme or setmem sequence that is valid for SIZE .. 2 * SIZE-1 bytes and jump to DONE_LABEL .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_tune ) { case PROCESSOR_RS64A : case PROCESSOR_PPC601 : case PROCESSOR_PPC7450 : return 3 ; case PROCESSOR_PPC440 : case PROCESSOR_PPC603 : case PROCESSOR_PPC750 : case PROCESSOR_PPC7400 : case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : case PROCESSOR_CELL : case PROCESSOR_PPCE300C2 : case PROCESSOR_PPCE300C3 : case PROCESSOR_PPCE500MC : case PROCESSOR_PPCE500MC64 : case PROCESSOR_PPCE5500 : case PROCESSOR_PPCE6500 : case PROCESSOR_TITAN : return 2 ; case PROCESSOR_PPC476 : case PROCESSOR_PPC604 : case PROCESSOR_PPC604e : case PROCESSOR_PPC620 : case PROCESSOR_PPC630 : return 4 ; case PROCESSOR_POWER4 : case PROCESSOR_POWER5 : case PROCESSOR_POWER6 : case PROCESSOR_POWER7 : return 5 ; case PROCESSOR_POWER8 : return 7 ; case PROCESSOR_POWER9 : return 6 ; case PROCESSOR_POWER10 : return 8 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static bool mips_expand_ghost_gp_insns ( void ) { if ( ! TARGET_USE_GOT || cfun -> machine -> global_pointer == INVALID_REGNUM || mips_must_initialize_gp_p ( ) ) return false ; if ( ! mips_has_long_branch_p ( ) ) return false ; cfun -> machine -> must_initialize_gp_p = true ; split_all_insns_noflow ( ) ; return true ; } </s>

If we are using a GOT , but have not decided to use a global pointer yet , see whether we need one to implement long branches . Convert the ghost global-pointer instructions into real ones if so .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlign ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } llvm :: stable_sort ( SortingObjects , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> hasStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> rtx rs6000_libcall_value ( enum machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) { return gen_rtx_PARALLEL ( DImode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 1 ) , GEN_INT ( 4 ) ) ) ) ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> TargetPassConfig * PPCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { TargetPassConfig * PassConfig = new PPCPassConfig ( this , PM ) ; PassConfig -> setEnableTailMerge ( false ) ; return PassConfig ; } </s>


<s> int direct_return ( ) { if ( reload_completed ) { d30v_stack_t * info = d30v_stack_info ( ) ; if ( info -> total_size == 0 ) return 1 ; if ( info -> total_size == info -> vars_size && IN_RANGE_P ( info -> total_size , 1 , 31 ) ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> BitVector LanaiRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Lanai :: R0 ) ; Reserved . set ( Lanai :: R1 ) ; Reserved . set ( Lanai :: PC ) ; Reserved . set ( Lanai :: R2 ) ; Reserved . set ( Lanai :: SP ) ; Reserved . set ( Lanai :: R4 ) ; Reserved . set ( Lanai :: FP ) ; Reserved . set ( Lanai :: R5 ) ; Reserved . set ( Lanai :: RR1 ) ; Reserved . set ( Lanai :: R10 ) ; Reserved . set ( Lanai :: RR2 ) ; Reserved . set ( Lanai :: R11 ) ; Reserved . set ( Lanai :: RCA ) ; Reserved . set ( Lanai :: R15 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( getBaseRegister ( ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void ix86_register_pragmas ( void ) { targetm . target_option . pragma_parse = ix86_pragma_target_parse ; c_register_addr_space ( "__seg_fs" , ADDR_SPACE_SEG_FS ) ; c_register_addr_space ( "__seg_gs" , ADDR_SPACE_SEG_GS ) ; REGISTER_SUBTARGET_PRAGMAS ( ) ; } </s>

Register target pragmas . We need to add the hook for parsing # pragma GCC option here rather than in i386.cc since it will pull in various preprocessor functions , and those are not present in languages like fortran without a preprocessor .


"Unable to generate load/store offset for fusion"

Emit a D-form load or store instruction that is the second instruction of a fusion sequence .


<s> static unsigned long thumb1_compute_save_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void LoongArchAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> Value * ARM64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm64_ldaxp : Intrinsic :: arm64_ldxp ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm64_ldaxr : Intrinsic :: arm64_ldxr ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> void X86WinAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; bool Is64BitAlloca = MI -> getOpcode ( ) == X86 :: WIN_ALLOCA_64 ; assert ( SlotSize == 4 || SlotSize == 8 ) ; switch ( L ) { case TouchAndSub : { assert ( Amount >= SlotSize ) ; unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; } case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64BitAlloca , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64BitAlloca ? X86 :: SUB64rr : X86 :: SUB32rr ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; } break ; } Register AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; if ( MRI -> use_empty ( AmountReg ) ) if ( MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ) AmountDef -> eraseFromParent ( ) ; } </s>


<s> bool ARMBaseTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createARMISelDag ( * this , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableSVEPostVec ) addPass ( createSVEPostVectorizePass ( ) ) ; if ( TM -> getTargetFeatureString ( ) . count ( "sve" ) ) addPass ( createSVEExpandLibCallPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && LowerGatherScatterToInterleaved ) { addPass ( createEarlyCSEPass ( ) ) ; addPass ( createInterleavedGatherScatterPass ( TM ) ) ; addPass ( createInstructionCombiningPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
RC
->
getSize
(
)
,
16
)
;
bool
isAligned
=
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> LanaiSubtarget & LanaiSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static rtx ix86_function_value_bounds ( const_tree valtype , const_tree fntype_or_decl ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { rtx res = NULL_RTX ; if ( BOUNDED_TYPE_P ( valtype ) ) res = gen_rtx_REG ( BNDmode , FIRST_BND_REG ) ; else if ( chkp_type_has_pointer ( valtype ) ) { bitmap slots ; rtx bounds [ 2 ] ; bitmap_iterator bi ; unsigned i , bnd_no = 0 ; bitmap_obstack_initialize ( NULL ) ; slots = BITMAP_ALLOC ( NULL ) ; chkp_find_bound_slots ( valtype , slots ) ; EXECUTE_IF_SET_IN_BITMAP ( slots , 0 , i , bi ) { rtx reg = gen_rtx_REG ( BNDmode , FIRST_BND_REG + bnd_no ) ; rtx offs = GEN_INT ( i * POINTER_SIZE / BITS_PER_UNIT ) ; gcc_assert ( bnd_no < 2 ) ; bounds [ bnd_no ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , offs ) ; } res = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( bnd_no , bounds ) ) ; BITMAP_FREE ( slots ) ; bitmap_obstack_release ( NULL ) ; } else res = NULL_RTX ; return res ; } </s>

Return an RTX representing a place where a function returns or recieves pointer bounds or NULL if no bounds are returned . VALTYPE is a data type of a value returned by the function . FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL or FUNCTION_TYPE of the function . If OUTGOING is false , return a place in which the caller will see the return value . Otherwise , return a place where a function returns a value .


<s> void buildLoad ( Register Val , Register Addr , uint64_t Size , unsigned Alignment , MachinePointerInfo & MPO ) { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; MIRBuilder . buildLoad ( Val , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .