<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , RegKind Kind , SMLoc S , SMLoc E , MCContext & Ctx , RegConstraintEqualityTy EqTy = RegConstraintEqualityTy :: EqualsReg , AArch64_AM :: ShiftExtendType ExtTy = AArch64_AM :: LSL , unsigned ShiftAmount = 0 , unsigned HasExplicitAmount = false ) { auto Op = std :: make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = Kind ; Op -> Reg . ElementWidth = 0 ; Op -> Reg . EqualityTy = EqTy ; Op -> Reg . ShiftExtend . Type = ExtTy ; Op -> Reg . ShiftExtend . Amount = ShiftAmount ; Op -> Reg . ShiftExtend . HasExplicitAmount = HasExplicitAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( NeedsWinCFI ) std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "required-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "required-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",required-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool X86TargetMachine :: addPostRegAlloc ( PassManagerBase & PM , bool Fast ) { PM . add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool SystemZAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && * ExtraCode == 'n' ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return true ; OS << - int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; } else { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; SystemZInstPrinter :: printOperand ( MO , OS ) ; } return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> void sparc_emit_membar_for_model ( enum memmodel model , int load_store , int before_after ) { const int LoadLoad = 1 ; const int StoreLoad = 2 ; const int LoadStore = 4 ; const int StoreStore = 8 ; int mm = 0 , implied = 0 ; switch ( sparc_memory_model ) { case SMM_SC : implied = LoadLoad | StoreLoad | LoadStore | StoreStore ; break ; case SMM_TSO : implied |= StoreStore ; if ( load_store == 3 && before_after == 1 ) implied |= StoreLoad ; case SMM_PSO : implied |= LoadLoad | LoadStore ; if ( load_store == 3 && before_after == 2 ) implied |= StoreLoad | StoreStore ; case SMM_RMO : break ; default : gcc_unreachable ( ) ; } if ( before_after & 1 ) { if ( model == MEMMODEL_RELEASE || model == MEMMODEL_ACQ_REL || model == MEMMODEL_SEQ_CST ) { if ( load_store & 1 ) mm |= LoadLoad | StoreLoad ; if ( load_store & 2 ) mm |= LoadStore | StoreStore ; } } if ( before_after & 2 ) { if ( model == MEMMODEL_ACQUIRE || model == MEMMODEL_ACQ_REL || model == MEMMODEL_SEQ_CST ) { if ( load_store & 1 ) mm |= LoadLoad | LoadStore ; if ( load_store & 2 ) mm |= StoreLoad | StoreStore ; } } mm &= ~ implied ; if ( mm || before_after == 3 ) emit_insn ( gen_membar ( GEN_INT ( mm ) ) ) ; } </s>

Expand a membar instruction for various use cases . Both the LOAD_STORE and BEFORE_AFTER arguments of the form X_Y . They are two-bit masks where bit 0 indicates that X is true , and bit 1 indicates Y is true .


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ) { unsigned long func_type ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && decl && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_APCS_FRAME && TARGET_ARM && TARGET_HARD_FLOAT && decl && arm_is_long_call_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) return false ; if ( TREE_CODE ( exp ) == CALL_EXPR ) { tree fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( lookup_attribute ( "cmse_nonsecure_call" , TYPE_ATTRIBUTES ( fntype ) ) ) return false ; } if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) ) return false ; if ( ! decl && CALL_EXPR_BY_DESCRIPTOR ( exp ) && ! flag_trampolines ) { tree fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; CUMULATIVE_ARGS cum ; cumulative_args_t cum_v ; arm_init_cumulative_args ( & cum , fntype , NULL_RTX , NULL_TREE ) ; cum_v = pack_cumulative_args ( & cum ) ; for ( tree t = TYPE_ARG_TYPES ( fntype ) ; t ; t = TREE_CHAIN ( t ) ) { tree type = TREE_VALUE ( t ) ; if ( ! VOID_TYPE_P ( type ) ) arm_function_arg_advance ( cum_v , TYPE_MODE ( type ) , type , true ) ; } if ( ! arm_function_arg ( cum_v , SImode , integer_type_node , true ) ) return false ; } return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static rtx nds32_expand_triop_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; rtx op2 = nds32_read_argument ( exp , 2 ) ; int op0_num = return_p ? 1 : 0 ; int op1_num = return_p ? 2 : 1 ; int op2_num = return_p ? 3 : 2 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; op2 = nds32_legitimize_argument ( icode , op2_num , op2 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 , op2 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take three operands .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; bool HasMicroMipsAttr = ! F . getFnAttribute ( "micromips" ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicroMipsAttr = ! F . getFnAttribute ( "nomicromips" ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; Reserved . set ( SP :: G1 ) ; if ( ReserveAppRegisters ) { Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; Reserved . set ( SP :: G0_G1 ) ; if ( ReserveAppRegisters ) Reserved . set ( SP :: G2_G3 ) ; if ( ReserveAppRegisters || ! Subtarget . is64Bit ( ) ) Reserved . set ( SP :: G4_G5 ) ; Reserved . set ( SP :: O6_O7 ) ; Reserved . set ( SP :: I6_I7 ) ; Reserved . set ( SP :: G6_G7 ) ; if ( ! Subtarget . isV9 ( ) ) { for ( unsigned n = 0 ; n != 16 ; ++ n ) { for ( MCRegAliasIterator AI ( SP :: D16 + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } for ( unsigned n = 0 ; n < 31 ; n ++ ) Reserved . set ( SP :: ASR1 + n ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static std :: unique_ptr < MipsOperand > CreateReg ( unsigned Index , StringRef Str , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , MipsAsmParser & Parser , unsigned RealRegister = Mips :: NoRegister ) { auto Op = std :: make_unique < MipsOperand > ( k_RegisterIndex , Parser ) ; Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> RegIdx . Tok . Data = Str . data ( ) ; Op -> RegIdx . Tok . Length = Str . size ( ) ; Op -> RegIdx . RealRegister = RealRegister ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Promote Constant"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: ADDE : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::SDIVREM ISD::UDIVREM ISD::SELECT ISD::AND ISD::OR ISD::ADD


<s> bool LanaiRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = arg . mode ; HOST_WIDE_INT bytes , words ; rtx reg ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) { gcc_assert ( arg . type != NULL_TREE ) ; if ( POINTER_TYPE_P ( arg . type ) ) { gcc_assert ( TYPE_MODE ( arg . type ) == ptr_mode ) ; reg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( arg . type ) == INTEGER_TYPE && TYPE_MODE ( arg . type ) == word_mode ) ; reg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , - 2 * UNITS_PER_WORD ) ) ; } return reg ; } bytes = arg . promoted_size_in_bytes ( ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( arg . type && TREE_CODE ( arg . type ) == VECTOR_TYPE ) mode = type_natural_mode ( arg . type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) reg = function_arg_ms_64 ( cum , mode , arg . mode , arg . named , arg . type , bytes ) ; else reg = function_arg_64 ( cum , mode , arg . mode , arg . type , arg . named ) ; } else reg = function_arg_32 ( cum , mode , arg . mode , arg . type , bytes , words ) ; if ( reg == NULL_RTX && cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; return reg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE


<s> void AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && usingDefaultRegAlloc ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; } </s>


<s> int fmpysuboperands ( rtx * operands ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( ! ( mode == GET_MODE ( operands [ 1 ] ) && mode == GET_MODE ( operands [ 2 ] ) && mode == GET_MODE ( operands [ 3 ] ) && mode == GET_MODE ( operands [ 4 ] ) && mode == GET_MODE ( operands [ 5 ] ) ) ) return 0 ; if ( ! ( GET_CODE ( operands [ 1 ] ) == REG && GET_CODE ( operands [ 2 ] ) == REG && GET_CODE ( operands [ 3 ] ) == REG && GET_CODE ( operands [ 4 ] ) == REG && GET_CODE ( operands [ 5 ] ) == REG ) ) return 0 ; if ( ! rtx_equal_p ( operands [ 3 ] , operands [ 4 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 5 ] , operands [ 0 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 3 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 1 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 2 ] ) ) return 0 ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ 0 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 1 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 2 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 3 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 4 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 5 ] ) ) != FPUPPER_REGS ) ) return 0 ; return 1 ; } </s>

Returns 1 if the 6 operands specified in OPERANDS are suitable for use in fmpysub instructions .


<s> void sh_pr_interrupt ( struct cpp_reader * pfile ATTRIBUTE_UNUSED ) { sh_add_function_attribute ( "interrupt_handler" ) ; } </s>

Handle machine specific pragmas to be semi-compatible with Hitachi compiler .


Write the extra assembler code needed to declare a function properly .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; const TargetRegisterClass * RC = Subtarget . isPPC64 ( ) ? G8RC : GPRC ; unsigned Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; if ( ! MI . getOperand ( 0 ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCR ) , Reg ) ; else BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCR ) , Reg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) , false , true , true ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( PPC :: RLWINM ) , Reg ) . addReg ( Reg , false , false , true ) . addImm ( PPCRegisterInfo :: getRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( PPC :: STW ) ) . addReg ( Reg , false , false , MI . getOperand ( 1 ) . getImm ( ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
(
PseudoSourceValue
::
getFixedStack
(
FI
)
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tSTRspi
0


<s> bool isConstantSplat ( SDValue Op , APInt & SplatVal , bool AllowPartialUndefs ) { APInt UndefElts ; SmallVector < APInt , 16 > EltBits ; if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , AllowPartialUndefs ) ) { int SplatIndex = - 1 ; for ( int i = 0 , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) continue ; if ( 0 <= SplatIndex && EltBits [ i ] != EltBits [ SplatIndex ] ) { SplatIndex = - 1 ; break ; } SplatIndex = i ; } if ( 0 <= SplatIndex ) { SplatVal = EltBits [ SplatIndex ] ; return true ; } } return false ; } </s>

Check if this is a constant splat , and if so , find the smallest element size that splats the vector .


<s> static void mips_promote_ready ( rtx * ready , int lower , int higher ) { rtx new_head ; int i ; new_head = ready [ lower ] ; for ( i = lower ; i < higher ; i ++ ) ready [ i ] = ready [ i + 1 ] ; ready [ i ] = new_head ; } </s>

Remove the instruction at index LOWER from ready queue READY and reinsert it in front of the instruction at index HIGHER . LOWER must be < = HIGHER .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { PrintIntelMemReference ( MI , OpNo , O ) ; return false ; } if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : PrintMemReference ( MI , OpNo , O , "H" ) ; return false ; case 'P' : PrintMemReference ( MI , OpNo , O , "no-rip" ) ; return false ; } } PrintMemReference ( MI , OpNo , O , nullptr ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getTarget ( ) . getTargetData ( ) ; TII = Fn . getTarget ( ) . getInstrInfo ( ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool save_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( crtl -> calls_eh_return && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return true ; if ( TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) return true ; if ( DEFAULT_ABI == ABI_V4 && ( flag_pic == 1 || ( flag_pic && TARGET_SECURE_PLT ) ) && df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) return true ; if ( DEFAULT_ABI == ABI_DARWIN && flag_pic && crtl -> uses_pic_offset_table ) return true ; } return ! call_used_or_fixed_reg_p ( reg ) && df_regs_ever_live_p ( reg ) ; } </s>

Determine whether the REG is really used .


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : case 'c' : printOperand ( MI , OpNo , "no_hash" ) ; return false ; case 'P' : printOperand ( MI , OpNo ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool MipsConstantIslands :: runOnMachineFunction ( MachineFunction & F ) { return true ; } </s>


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; bool genExecuteOnly = ARM_TM . getMCSubtargetInfo ( ) -> hasFeature ( ARM :: FeatureExecuteOnly ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_ARM_PURECODE ; TextSection = Ctx . getELFSection ( ".text" , Type , Flags , 0 , "" , 0U ) ; } } </s>

This method must be called before any actual lowering is done .

ARM ARM ARM ARM ARM ARM ARM ARMABI::ARM_ABI_AAPCS ARM ARM::FeatureExecuteOnly ARM ".text" 0 "" 0U


<s> const uint32_t * VERegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB ) ; } for ( auto & MBB : MF ) if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB ) ; return Changed ; } </s>


<s> static void arm_reorg ( void ) { rtx insn ; HOST_WIDE_INT address = 0 ; Mfix * fix ; minipool_fix_head = minipool_fix_tail = NULL ; insn = get_insns ( ) ; gcc_assert ( GET_CODE ( insn ) == NOTE ) ; for ( insn = next_nonnote_insn ( insn ) ; insn ; insn = next_nonnote_insn ( insn ) ) { if ( TARGET_CIRRUS_FIX_INVALID_INSNS && ( arm_cirrus_insn_p ( insn ) || GET_CODE ( insn ) == JUMP_INSN || arm_memory_load_p ( insn ) ) ) cirrus_reorg ( insn ) ; if ( GET_CODE ( insn ) == BARRIER ) push_minipool_barrier ( insn , address ) ; else if ( INSN_P ( insn ) ) { rtx table ; note_invalid_constants ( insn , address , true ) ; address += get_attr_length ( insn ) ; if ( ( table = is_jump_table ( insn ) ) != NULL ) { address += get_jump_table_size ( table ) ; insn = table ; } } } fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * fdel ; Mfix * last_added_fix ; Mfix * last_barrier = NULL ; Mfix * this_fix ; while ( fix && GET_CODE ( fix -> insn ) == BARRIER ) fix = fix -> next ; if ( fix == NULL ) break ; last_added_fix = NULL ; for ( ftmp = fix ; ftmp ; ftmp = ftmp -> next ) { if ( GET_CODE ( ftmp -> insn ) == BARRIER ) { if ( ftmp -> address >= minipool_vector_head -> max_address ) break ; last_barrier = ftmp ; } else if ( ( ftmp -> minipool = add_minipool_forward_ref ( ftmp ) ) == NULL ) break ; last_added_fix = ftmp ; } if ( last_barrier != NULL ) { for ( fdel = last_barrier -> next ; fdel && fdel != ftmp ; fdel = fdel -> next ) { fdel -> minipool -> refcount -- ; fdel -> minipool = NULL ; } ftmp = last_barrier ; } else { HOST_WIDE_INT max_address ; gcc_assert ( ftmp ) ; max_address = minipool_vector_head -> max_address ; if ( ftmp -> address < max_address ) max_address = ftmp -> address ; last_barrier = create_fix_barrier ( last_added_fix , max_address ) ; } assign_minipool_offsets ( last_barrier ) ; while ( ftmp ) { if ( GET_CODE ( ftmp -> insn ) != BARRIER && ( ( ftmp -> minipool = add_minipool_backward_ref ( ftmp ) ) == NULL ) ) break ; ftmp = ftmp -> next ; } for ( this_fix = fix ; this_fix && ftmp != this_fix ; this_fix = this_fix -> next ) if ( GET_CODE ( this_fix -> insn ) != BARRIER ) { rtx addr = plus_constant ( gen_rtx_LABEL_REF ( VOIDmode , minipool_vector_label ) , this_fix -> minipool -> offset ) ; * this_fix -> loc = gen_rtx_MEM ( this_fix -> mode , addr ) ; } dump_minipool ( last_barrier -> insn ) ; fix = ftmp ; } after_arm_reorg = 1 ; obstack_free ( & minipool_obstack , minipool_startobj ) ; } </s>

Gcc puts the pool in the wrong place for ARM , since we can only load addresses a limited distance around the pc . We do some special munging to move the constant pool values to the correct point in the code .


<s> void print ( raw_ostream & OS ) const override { switch ( Kind ) { case k_Register : OS << "Reg<" << Reg . Num << ">" ; break ; case k_Immediate : OS << "Imm<" << ( ( const MCConstantExpr * ) Imm . Val ) -> getValue ( ) << ">" ; break ; case k_Token : OS << Tok . Data ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> static void ix86_default_align ( struct gcc_options * opts ) { if ( opts -> x_flag_align_loops && ! opts -> x_str_align_loops ) opts -> x_str_align_loops = processor_cost_table [ ix86_tune ] -> align_loop ; if ( opts -> x_flag_align_jumps && ! opts -> x_str_align_jumps ) opts -> x_str_align_jumps = processor_cost_table [ ix86_tune ] -> align_jump ; if ( opts -> x_flag_align_labels && ! opts -> x_str_align_labels ) opts -> x_str_align_labels = processor_cost_table [ ix86_tune ] -> align_label ; if ( opts -> x_flag_align_functions && ! opts -> x_str_align_functions ) opts -> x_str_align_functions = processor_cost_table [ ix86_tune ] -> align_func ; } </s>

Default align_ * from the processor table .


<s> MandarinTargetLowering :: ConstraintType MandarinTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
bool
ARMTargetLowering
::
canCombineStoreAndExtract
(
Type
*
VectorTy
,
Value
*
Idx
,
unsigned
&
Cost
)
const
{
if
(
!
Subtarget
->
hasNEON
(
)
)
return
false
;
if
(
VectorTy
->
isFPOrFPVectorTy
(
)
)
return
false
;
if
(
!
isa
<
ConstantInt
>
(
Idx
)
)
return
false
;
assert
(
VectorTy
->
isVectorTy
(
)
&&
"VectorTy is not a vector type"
)
;
unsigned
BitWidth
=
VectorTy
->
getPrimitiveSizeInBits
(
)
.
getFixedSize
(
)
;
if
(
BitWidth
==
64
||
BitWidth
==
128
)
{
Cost
=
0
;
return
true
;
}
return
false
;
}
</s>

Return true if the target can combine store ( extractelement VectorTy , Idx ) .


<s> Value * X86TargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { return M . getGlobalVariable ( "__security_cookie" ) ; } return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( 2 , Size - 1 ) . getAsInteger ( 10 , RegNo ) ; if ( ! Failed && RegNo >= 0 && RegNo <= 31 ) { if ( VT != MVT :: Other && VT . getSizeInBits ( ) == 64 ) { Res . first = AArch64 :: FPR64RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR64RegClass ; } else { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> Register MipsOutgoingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( Mips :: SP ) ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> OperandMatchResultTy MINA32AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNo = matchRegisterName ( lowerCase ) ; if ( RegNo != 0 ) { return MatchOperand_Success ; } } return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : case ARM :: GPRPairRegClassID : return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM::GPRRegClassID ARM::SPRRegClassID ARM::DPRRegClassID ARM::QPRRegClassID ARM::QQPRRegClassID ARM::QQQQPRRegClassID ARM::GPRPairRegClassID


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> static bool mips_classify_address ( struct mips_address_info * info , rtx x , machine_mode mode , bool strict_p ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return mips_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; return ( mips_valid_base_register_p ( info -> reg , mode , strict_p ) && mips_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; info -> symbol_type = mips_classify_symbolic_expression ( info -> offset , SYMBOL_CONTEXT_MEM ) ; return ( mips_valid_base_register_p ( info -> reg , mode , strict_p ) && mips_valid_lo_sum_p ( info -> symbol_type , mode ) ) ; case CONST_INT : info -> type = ADDRESS_CONST_INT ; return ! TARGET_MIPS16 && SMALL_INT ( x ) ; case CONST : case LABEL_REF : case SYMBOL_REF : info -> type = ADDRESS_SYMBOLIC ; return ( mips_symbolic_constant_p ( x , SYMBOL_CONTEXT_MEM , & info -> symbol_type ) && mips_symbol_insns ( info -> symbol_type , mode ) > 0 && ! mips_split_p [ info -> symbol_type ] ) ; default : return false ; } } </s>

Return true if X is a valid address for machine mode MODE . If it is , fill in INFO appropriately . STRICT is true if we should only accept hard base registers .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; if ( Ty -> isVectorTy ( ) && Ty -> getVectorIsScalable ( ) ) return AM . HasBaseReg && ! AM . BaseOffs && ! AM . Scale ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static rtx arm_dwarf_register_span ( rtx rtl ) { machine_mode mode ; unsigned regno ; rtx parts [ 16 ] ; int nregs ; int i ; regno = REGNO ( rtl ) ; if ( ! IS_VFP_REGNUM ( regno ) ) return NULL_RTX ; mode = GET_MODE ( rtl ) ; if ( GET_MODE_SIZE ( mode ) < 8 ) return NULL_RTX ; if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) { nregs = GET_MODE_SIZE ( mode ) / 4 ; for ( i = 0 ; i < nregs ; i += 2 ) if ( TARGET_BIG_END ) { parts [ i ] = gen_rtx_REG ( SImode , regno + i + 1 ) ; parts [ i + 1 ] = gen_rtx_REG ( SImode , regno + i ) ; } else { parts [ i ] = gen_rtx_REG ( SImode , regno + i ) ; parts [ i + 1 ] = gen_rtx_REG ( SImode , regno + i + 1 ) ; } } else { nregs = GET_MODE_SIZE ( mode ) / 8 ; for ( i = 0 ; i < nregs ; i ++ ) parts [ i ] = gen_rtx_REG ( DImode , regno + i ) ; } return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nregs , parts ) ) ; } </s>

Dwarf models VFPv3 registers as 32 64-bit registers . GCC models tham as 64 32-bit registers , so we need to describe this to the DWARF generation code . Other registers can use the default .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) -> getOperand ( 0 ) . getReg ( ) ; } auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 1 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> unsigned SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static tree cygwin_d_handle_target_object_format ( void ) { const char * objfmt = "coff" ; return build_string_literal ( strlen ( objfmt ) + 1 , objfmt ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` objectFormat '' ) ' .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( 0 ) ; break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s>
bool
AArch64AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
AArch64InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static void arm_init_bf16_types ( void ) { arm_bf16_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( arm_bf16_type_node ) = 16 ; SET_TYPE_MODE ( arm_bf16_type_node , BFmode ) ; layout_type ( arm_bf16_type_node ) ; lang_hooks . types . register_builtin_type ( arm_bf16_type_node , "__bf16" ) ; arm_bf16_ptr_type_node = build_pointer_type ( arm_bf16_type_node ) ; } </s>

Initialize the backend REAL_TYPE type supporting bfloat types .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> void rs6000_emit_eh_reg_restore ( rtx source , rtx scratch ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx operands [ 2 ] ; operands [ 0 ] = source ; operands [ 1 ] = scratch ; if ( info -> lr_save_p ) { rtx frame_rtx = stack_pointer_rtx ; HOST_WIDE_INT sp_offset = 0 ; rtx tmp ; if ( frame_pointer_needed || cfun -> calls_alloca || info -> total_size > 32767 ) { tmp = gen_frame_mem ( Pmode , frame_rtx ) ; emit_move_insn ( operands [ 1 ] , tmp ) ; frame_rtx = operands [ 1 ] ; } else if ( info -> push_p ) sp_offset = info -> total_size ; tmp = plus_constant ( Pmode , frame_rtx , info -> lr_save_offset + sp_offset ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_move_insn ( tmp , operands [ 0 ] ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LR_REGNO ) , operands [ 0 ] ) ; cfun -> machine -> lr_save_state = info -> lr_save_p + 1 ; } </s>

Emit instructions to restore the link register after determining where its value has been stored .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { if ( IsLittleEndian && Size == 4 && isMicroMips ( STI ) ) { EmitInstruction ( Val >> 16 , 2 , STI , OS ) ; EmitInstruction ( Val , 2 , STI , OS ) ; } else { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static tree aarch64_preferred_else_value ( unsigned , tree , unsigned int nops , tree * ops ) { return nops == 3 ? ops [ 2 ] : ops [ 0 ] ; } </s>

Implement TARGET_PREFERRED_ELSE_VALUE . For binary operations , prefer to use the first arithmetic operand as the else value if the else value does n't matter , since that exactly matches the SVE destructive merging form . For ternary operations we could either pick the first operand and use FMAD-like instructions or the last operand and use FMLA-like instructions ; the latter seems more natural .


<s>
static
bool
rename_single_chain
(
du_head_p
head
,
HARD_REG_SET
*
unavailable
)
{
int
best_new_reg
;
int
n_uses
=
0
;
struct
du_chain
*
tmp
;
int
reg
=
head
->
regno
;
enum
reg_class
super_class
=
NO_REGS
;
if
(
head
->
cannot_rename
)
return
false
;
if
(
fixed_regs
[
reg
]
||
global_regs
[
reg
]
||
(
frame_pointer_needed
&&
reg
==
HARD_FRAME_POINTER_REGNUM
)
)
return
false
;
for
(
tmp
=
head
->
first
;
tmp
;
tmp
=
tmp
->
next_use
)
{
if
(
DEBUG_INSN_P
(
tmp
->
insn
)
)
continue
;
n_uses
++
;
IOR_COMPL_HARD_REG_SET
(
*
unavailable
,
reg_class_contents
[
tmp
->
cl
]
)
;
super_class
=
reg_class_superunion
[
(
int
)
super_class
]
[
(
int
)
tmp
->
cl
]
;
}
if
(
n_uses
<
1
)
return
false
;
best_new_reg
=
find_rename_reg
(
head
,
super_class
,
unavailable
,
reg
,
false
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Register %s in insn %d"
,
reg_names
[
reg
]
,
INSN_UID
(
head
->
first
->
insn
)
)
;
if
(
head
->
need_caller_save_reg
)
fprintf
(
dump_file
,
" crosses a call"
)
;
}
if
(
best_new_reg
==
reg
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"; no available better choice\n"
)
;
return
false
;
}
if
(
regrename_do_replace
(
head
,
best_new_reg
)
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
", renamed as %s\n"
,
reg_names
[
best_new_reg
]
)
;
df_set_regs_ever_live
(
best_new_reg
,
true
)
;
}
else
{
if
(
dump_file
)
fprintf
(
dump_file
,
", renaming as %s failed\n"
,
reg_names
[
best_new_reg
]
)
;
return
false
;
}
return
true
;
}
</s>

Rename the register HEAD- > regno in all the insns in the chain HEAD to any register not in the set UNAVAILABLE . Adapted from rename_chains in regrename.c .


<s> static int reg_plus_index_p ( rtx x , enum machine_mode mode , int strict ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return 0 ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( BASE_REGISTER_P ( xfoo0 , strict ) && index_term_p ( xfoo1 , mode , strict ) ) return 1 ; if ( BASE_REGISTER_P ( xfoo1 , strict ) && index_term_p ( xfoo0 , mode , strict ) ) return 1 ; return 0 ; } </s>

Return 1 if X is the sum of a register and a valid index term for mode MODE .


<s> static struct machine_function * nds32_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> use_eh_return_p = 0 ; machine -> naked_p = 0 ; machine -> fp_as_gp_p = 0 ; machine -> strict_aligned_p = 0 ; return machine ; } </s>

Function to save and restore machine-specific function data .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static bool aarch64_option_valid_attribute_p ( tree fndecl , tree , tree args , int ) { struct cl_target_option cur_target ; bool ret ; tree old_optimize ; tree new_target , new_optimize ; tree existing_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! existing_target && args == current_target_pragma ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_option_current_node ; return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , existing_options ) ; } else cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args , "attribute" ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options ) ; if ( fndecl && ret ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret ; } </s>

Implement TARGET_OPTION_VALID_ATTRIBUTE_P . This is used to process attribute ( ( target ( `` ... '' ) ) ) .


<s> static unsigned HOST_WIDE_INT arm_asan_shadow_offset ( void ) { return HOST_WIDE_INT_1U << 29 ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SRA : return PerformSRACombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { gcc_assert ( epilogue_completed ) ; rtx rval , mem , oldval , newval , scratch , x , model_rtx ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; enum memmodel model ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; model_rtx = operands [ 5 ] ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ( ! is_weak && ! aarch64_track_speculation && oldval == const0_rtx && mode != TImode ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; else { rtx cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; x = gen_rtx_NE ( VOIDmode , cc_reg , const0_rtx ) ; } x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; emit_label ( label2 ) ; if ( strong_zero_p ) aarch64_gen_compare_reg ( NE , rval , const0_rtx ) ; if ( is_mm_sync ( model ) ) aarch64_emit_post_barrier ( model ) ; } </s>


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> StringRef X86ATTInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> bool ARMFrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
static
bool
aarch64_rtx_costs_wrapper
(
rtx
x
,
int
code
,
int
outer
,
int
param
,
int
*
cost
,
bool
speed
)
{
bool
result
=
aarch64_rtx_costs
(
x
,
code
,
outer
,
param
,
cost
,
speed
)
;
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
cost
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

Wrapper around aarch64_rtx_costs , dumps the partial , or total cost calculated for X . This cost is stored in * COST . Returns true if the total cost of X was calculated .

aarch64
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> bool CSKYAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> const RegisterBankInfo :: InstructionMapping & X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) || Opc == TargetOpcode :: G_PHI ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; case TargetOpcode :: G_TRUNC : case TargetOpcode :: G_ANYEXT : { auto & Op0 = MI . getOperand ( 0 ) ; auto & Op1 = MI . getOperand ( 1 ) ; const LLT Ty0 = MRI . getType ( Op0 . getReg ( ) ) ; const LLT Ty1 = MRI . getType ( Op1 . getReg ( ) ) ; bool isFPTrunc = ( Ty0 . getSizeInBits ( ) == 32 || Ty0 . getSizeInBits ( ) == 64 ) && Ty1 . getSizeInBits ( ) == 128 && Opc == TargetOpcode :: G_TRUNC ; bool isFPAnyExt = Ty0 . getSizeInBits ( ) == 128 && ( Ty1 . getSizeInBits ( ) == 32 || Ty1 . getSizeInBits ( ) == 64 ) && Opc == TargetOpcode :: G_ANYEXT ; getInstrPartialMappingIdxs ( MI , MRI , isFPTrunc || isFPAnyExt , OpRegBankIdx ) ; } break ; default : getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; break ; } SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return getInvalidInstructionMapping ( ) ; return getInstructionMapping ( DefaultMappingID , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .


"      \"\", RS6000_BIF_NONE, NULL_TREE, NULL\n"

Write the decls and initializers for rs6000_overload_info [ ] and rs6000_instance_info [ ] .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableAArch64CopyPropagation ) addPass ( createMachineCopyPropagationPass ( true ) ) ; addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void load_lr_save ( int regno , rtx frame_reg_rtx , int offset ) { rtx mem = gen_frame_mem_offset ( Pmode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( Pmode , regno ) ; emit_move_insn ( reg , mem ) ; } </s>

Like cr , the move to lr instruction can be scheduled after the stack deallocation , but unlike cr , its stack frame save is still valid . So we only need to emit the cfa_restore on the correct instruction .


<s> unsigned AArch64TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case Intrinsic :: umin : case Intrinsic :: umax : { auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . second == MVT :: v2i64 ) return LT . first * 2 ; LLVM_FALLTHROUGH ; } case Intrinsic :: smin : case Intrinsic :: smax : { static const auto ValidMinMaxTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } default : break ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> SDValue PPCTargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRSQRTES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRSQRTE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasQPX ( ) ) || ( VT == MVT :: v4f64 && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = true ; return DAG . getNode ( PPCISD :: FRSQRTE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> MachineBasicBlock :: iterator CSKYFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { Register SPReg = CSKY :: R14 ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == CSKY :: ADJCALLSTACKDOWN ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static enum rtx_code ix86_prepare_sse_fp_compare_args ( rtx dest , enum rtx_code code , rtx * pop0 , rtx * pop1 ) { rtx tmp ; switch ( code ) { case LTGT : case UNEQ : return UNKNOWN ; case LT : case LE : case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED : case ORDERED : if ( ! dest || ! rtx_equal_p ( dest , * pop1 ) ) break ; case GE : case GT : case UNLE : case UNLT : tmp = * pop0 ; * pop0 = * pop1 ; * pop1 = tmp ; code = swap_condition ( code ) ; break ; default : gcc_unreachable ( ) ; } return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to an sse comparison with a mask result . Thus we differ a bit from ix86_prepare_fp_compare_args which expects to produce a flags result . The DEST operand exists to help determine whether to commute commutative operators . The POP0/POP1 operands are updated in place . The new comparison code is returned , or UNKNOWN if not implementable .


<s> void PPCInstrInfo :: setSpecialOperandAttr ( MachineInstr & MI , uint16_t Flags ) const { MI . setFlags ( Flags ) ; MI . clearFlag ( MachineInstr :: MIFlag :: NoSWrap ) ; MI . clearFlag ( MachineInstr :: MIFlag :: NoUWrap ) ; MI . clearFlag ( MachineInstr :: MIFlag :: IsExact ) ; } </s>

This is an architecture-specific helper function of reassociateOps .


<s> static int symbolic_expression_p ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF ) return 1 ; if ( GET_CODE ( x ) == CONST ) return symbolic_expression_p ( XEXP ( x , 0 ) ) ; if ( UNARY_P ( x ) ) return symbolic_expression_p ( XEXP ( x , 0 ) ) ; if ( ARITHMETIC_P ( x ) ) return ( symbolic_expression_p ( XEXP ( x , 0 ) ) || symbolic_expression_p ( XEXP ( x , 1 ) ) ) ; return 0 ; } </s>

Return 1 if X contains a symbolic expression . We know these expressions will have one of a few well defined forms , so we need only check those forms .


<s> void mips_output_aligned_decl_common ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { if ( TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ( DECL_INITIAL ( decl ) == 0 || DECL_INITIAL ( decl ) == error_mark_node ) ) { if ( TREE_PUBLIC ( decl ) && DECL_NAME ( decl ) ) targetm . asm_out . globalize_label ( stream , name ) ; readonly_data_section ( ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( align / BITS_PER_UNIT ) ) ; mips_declare_object ( stream , name , "" , ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n" , size ) ; } else mips_declare_common_object ( stream , name , "\n\t.comm\t" , size , align , true ) ; } </s>

Implement ASM_OUTPUT_ALIGNED_DECL_COMMON . This is usually the same as the elfos.h version , but we also need to handle -muninit-const-in-rodata .


<s> bool nds32_isr_function_critical_p ( tree func ) { tree t_intr ; tree t_excp ; tree t_critical ; tree attrs ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; attrs = DECL_ATTRIBUTES ( func ) ; t_intr = lookup_attribute ( "interrupt" , attrs ) ; t_excp = lookup_attribute ( "exception" , attrs ) ; t_critical = lookup_attribute ( "critical" , attrs ) ; if ( ( t_intr == NULL_TREE ) && ( t_excp == NULL_TREE ) ) return false ; if ( t_critical != NULL_TREE ) return true ; if ( t_intr != NULL_TREE || t_excp != NULL_TREE ) { char target_str [ 100 ] ; char * critical_str ; tree t_check ; tree string_arg ; t_check = t_intr ? t_intr : t_excp ; if ( TREE_CODE ( TREE_VALUE ( TREE_VALUE ( t_check ) ) ) == STRING_CST ) { string_arg = TREE_VALUE ( TREE_VALUE ( t_check ) ) ; strcpy ( target_str , TREE_STRING_POINTER ( string_arg ) ) ; critical_str = strstr ( target_str , "critical" ) ; if ( critical_str ) return true ; } } return false ; } </s>

Return true if FUNC is a isr function with critical attribute .

nds32 "interrupt" "exception" "critical" 100 "critical"


<s> static void predict_jump ( int prob ) { rtx_insn * insn = get_last_insn ( ) ; gcc_assert ( JUMP_P ( insn ) ) ; add_int_reg_note ( insn , REG_BR_PROB , prob ) ; } </s>

Predict just emitted jump instruction to be taken with probability PROB .


<s> int arm_early_load_addr_dep ( rtx producer , rtx consumer ) { rtx value , addr ; if ( ! arm_get_set_operands ( producer , consumer , & value , & addr ) ) return 0 ; return reg_overlap_mentioned_p ( value , addr ) ; } </s>

Return nonzero if the CONSUMER instruction ( a load ) does need PRODUCER 's value to calculate the address .


"block as it would convert a WLS from forward to a "

Checks if loop has a backwards branching WLS , and if possible , fixes it .


<s> const LC2200InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
static_cast
<
MipsTargetMachine
&
>
(
TM
)
.
getABI
(
)
.
GetEnumValue
(
)
)
{
case
MipsABIInfo
::
ABI
::
O32
:
return
"abi32"
;
case
MipsABIInfo
::
ABI
::
N32
:
return
"abiN32"
;
case
MipsABIInfo
::
ABI
::
N64
:
return
"abi64"
;
default
:
llvm_unreachable
(
"Unknown Mips ABI"
)
;
}
}
</s>

Mips
Mips
Mips
Mips
"abi32"
Mips
"abiN32"
Mips
"abi64"
"Unknown Mips ABI"


Return an array that contains the bitmask target flag values and their names .


<s> FastISel * ARM64TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { return ARM64 :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


"MMIX Internal: This is not a recognized address"


runOnMachineFunction - Emit the function body .


<s> static rtx gen_load_const_gp ( rtx reg ) { return PMODE_INSN ( gen_load_const_gp , ( reg ) ) ; } </s>

Return an instruction that copies $ gp into register REG . We want GCC to treat the register 's value as constant , so that its value can be rematerialized on demand .


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( Subtarget . isTargetAndroid ( ) ) { int Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x18 , getAddressSpace ( ) ) ; } return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_PORTABLE_RUNTIME ) return false ; if ( TARGET_64BIT ) return false ; return ( decl && ! TREE_PUBLIC ( decl ) ) ; } </s>

Only direct calls to static functions are allowed to be sibling ( tail ) call optimized . This restriction is necessary because some linker generated stubs will store return pointers into rp ' in some cases which might clobber a live value already in rp ' . In a sibcall the current function and the target function share stack space . Thus if the path to the current function and the path to the target function save a value in rp ' , they save the value into the same stack slot , which has undesirable consequences . Because of the deferred binding nature of shared libraries any function with external scope could be in a different load module and thus require rp ' to be saved when calling that function . So sibcall optimizations can only be safe for static function . Note that GCC never needs return value relocations , so we do n't have to worry about static calls with return value relocations ( which require saving rp ' ) . It is safe to perform a sibcall optimization when the target function will never return .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_VFP_BASE && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return IN_RANGE ( val , - 1020 , 1020 ) && ( val & 3 ) == 0 ; else return IN_RANGE ( val , - 255 , 4095 - 4 ) ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const ARMBaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , ARMCC :: CondCodes Pred = ARMCC :: AL , unsigned PredReg = 0 ) { emitRegPlusImmediate ( isARM , MBB , MBBI , dl , TII , ARM :: SP , ARM :: SP , NumBytes , MIFlags , Pred , PredReg ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARMCC::CondCodes ARMCC::AL 0 ARM ARM::SP ARM::SP


<s> static int power9_sched_reorder2 ( rtx_insn * * ready , int lastpos ) { int pos ; enum attr_type type , type2 ; type = get_attr_type ( last_scheduled_insn ) ; if ( type == TYPE_DIV && divide_cnt == 0 ) { divide_cnt = 1 ; pos = lastpos ; while ( pos >= 0 ) { if ( recog_memoized ( ready [ pos ] ) >= 0 && get_attr_type ( ready [ pos ] ) == TYPE_DIV ) { move_to_end_of_ready ( ready , pos , lastpos ) ; break ; } pos -- ; } } else { divide_cnt = 0 ; if ( type == TYPE_VECLOAD ) { if ( vec_pairing == 0 ) { int vecload_pos = - 1 ; pos = lastpos ; while ( pos >= 0 ) { if ( recog_memoized ( ready [ pos ] ) >= 0 ) { type2 = get_attr_type ( ready [ pos ] ) ; if ( is_power9_pairable_vec_type ( type2 ) ) { move_to_end_of_ready ( ready , pos , lastpos ) ; vec_pairing = 1 ; return cached_can_issue_more ; } else if ( type2 == TYPE_VECLOAD && vecload_pos == - 1 ) vecload_pos = pos ; } pos -- ; } if ( vecload_pos >= 0 ) { move_to_end_of_ready ( ready , vecload_pos , lastpos ) ; vec_pairing = 1 ; return cached_can_issue_more ; } } } else if ( is_power9_pairable_vec_type ( type ) ) { if ( vec_pairing == 0 ) { int vec_pos = - 1 ; pos = lastpos ; while ( pos >= 0 ) { if ( recog_memoized ( ready [ pos ] ) >= 0 ) { type2 = get_attr_type ( ready [ pos ] ) ; if ( type2 == TYPE_VECLOAD ) { move_to_end_of_ready ( ready , pos , lastpos ) ; vec_pairing = 1 ; return cached_can_issue_more ; } else if ( is_power9_pairable_vec_type ( type2 ) && vec_pos == - 1 ) vec_pos = pos ; } pos -- ; } if ( vec_pos >= 0 ) { move_to_end_of_ready ( ready , vec_pos , lastpos ) ; vec_pairing = 1 ; return cached_can_issue_more ; } } } vec_pairing = 0 ; } return cached_can_issue_more ; } </s>

Do Power9 specific sched_reorder2 reordering of ready list .


<s> static bool rs6000_parm_needs_stack ( cumulative_args_t args_so_far , tree type ) { machine_mode mode ; int unsignedp ; rtx entry_parm ; if ( type == NULL || type == error_mark_node ) return true ; if ( TYPE_MODE ( type ) == VOIDmode ) return false ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) return ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) || rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) ) ; if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; if ( pass_by_reference ( get_cumulative_args ( args_so_far ) , TYPE_MODE ( type ) , type , true ) ) type = build_pointer_type ( type ) ; unsignedp = TYPE_UNSIGNED ( type ) ; mode = promote_mode ( type , TYPE_MODE ( type ) , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( mode , type ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , mode , type , true ) ; if ( entry_parm == NULL ) return true ; if ( GET_CODE ( entry_parm ) == PARALLEL && XEXP ( XVECEXP ( entry_parm , 0 , 0 ) , 0 ) == NULL_RTX ) return true ; if ( rs6000_arg_partial_bytes ( args_so_far , mode , type , true ) != 0 ) return true ; rs6000_function_arg_advance ( args_so_far , mode , type , true ) ; return false ; } </s>

Process parameter of type TYPE after ARGS_SO_FAR parameters were already processes . Return true if the parameter must be passed ( fully or partially ) on the stack .


<s>
unsigned
VEInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool mips_store_data_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { if ( GET_CODE ( PATTERN ( in_insn ) ) == UNSPEC_VOLATILE ) return false ; return ! store_data_bypass_p ( out_insn , in_insn ) ; } </s>

True if the dependency between OUT_INSN and IN_INSN is on the store data rather than the address . We need this because the cprestore pattern is type `` store '' , but is defined using an UNSPEC_VOLATILE , which causes the default routine to abort . We just return false for that case .


<s> bool contains ( MachineInstr * MI ) { return Insts . count ( MI ) > 0 ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> static rtx function_arg_vector_value ( int size , int regno ) { const int nregs = MAX ( 1 , size / 8 ) ; rtx regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nregs ) ) ; if ( size < 8 ) XVECEXP ( regs , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , regno ) , const0_rtx ) ; else for ( int i = 0 ; i < nregs ; i ++ ) XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , regno + 2 * i ) , GEN_INT ( i * 8 ) ) ; return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions for passing and returning BLKmode vectors . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the vector . REGNO is the FP hard register the vector will be passed in .


<s> static bool mips_expand_vpc_loongson_pshufh ( struct expand_vec_perm_d * d ) { unsigned i , mask ; rtx rmask ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI ) ) return false ; if ( d -> vmode != V4HImode ) return false ; if ( d -> testing_p ) return true ; for ( i = mask = 0 ; i < 4 ; i ++ ) mask |= ( d -> perm [ i ] & 3 ) << ( i * 2 ) ; rmask = force_reg ( SImode , GEN_INT ( mask ) ) ; if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ 4 ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = 0 ; i < 4 ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & 4 ? constm1_rtx : const0_rtx ) ; merge = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmerge ) ) ; merge = force_reg ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , merge , t1 ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_NOT ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , x , t0 ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; } return true ; } </s>

Recognize patterns for the Loongson PSHUFH instruction .


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { emitA64MappingSymbol ( ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED ) { cum -> words = 0 ; cum -> prototype_p = fntype && TYPE_ARG_TYPES ( fntype ) ; cum -> libcall_p = fntype == 0 ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void emit_v9_brxx_insn ( enum rtx_code code , rtx op0 , rtx label ) { gcc_assert ( sparc_compare_emitted == NULL_RTX ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; } </s>

Emit a conditional jump insn for the v9 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the v9 brxx insns .


<s> bool and_operands_ok ( machine_mode mode , rtx op1 , rtx op2 ) { if ( memory_operand ( op1 , mode ) ) { if ( TARGET_MIPS16 ) { struct mips_address_info addr ; if ( ! mips_classify_address ( & addr , op1 , mode , false ) ) return false ; } return and_load_operand ( op2 , mode ) ; } else return and_reg_operand ( op2 , mode ) ; } </s>

Return true iff OP1 and OP2 are valid operands together for the * and < MODE > 3 and * and < MODE > 3_mips16 patterns . For the cases to consider , see the table in the comment before the pattern .


<s> const PPCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool AArch64TargetLowering :: shouldLocalize ( const MachineInstr & MI , const TargetTransformInfo * TTI ) const { switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_GLOBAL_VALUE : { const GlobalValue & GV = * MI . getOperand ( 1 ) . getGlobal ( ) ; if ( GV . isThreadLocal ( ) && Subtarget -> isTargetMachO ( ) ) return false ; break ; } case AArch64 :: ADRP : case AArch64 :: G_ADD_LOW : return true ; default : break ; } return TargetLoweringBase :: shouldLocalize ( MI , TTI ) ; } </s>

Check whether or not MI needs to be moved close to its uses .


<s> AArch64DCBasicBlock & getParent ( ) { return static_cast < AArch64DCBasicBlock & > ( DCInstruction :: getParent ( ) ) ; } </s>

getParent - Return the last analyzed interval .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> static unsigned rs6000_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; } return retval ; } </s>


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSectionData & TextSectionData = MCA . getOrCreateSectionData ( * OFI . getTextSection ( ) ) ; MCSectionData & DataSectionData = MCA . getOrCreateSectionData ( * OFI . getDataSection ( ) ) ; MCSectionData & BSSSectionData = MCA . getOrCreateSectionData ( * OFI . getBSSSection ( ) ) ; TextSectionData . setAlignment ( std :: max ( 16u , TextSectionData . getAlignment ( ) ) ) ; DataSectionData . setAlignment ( std :: max ( 16u , DataSectionData . getAlignment ( ) ) ) ; BSSSectionData . setAlignment ( std :: max ( 16u , BSSSectionData . getAlignment ( ) ) ) ; uint64_t Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features & Mips :: FeatureGP64Bit ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features & Mips :: FeatureMips64r2 || Features & Mips :: FeatureMips64 ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( EFlags & ELF :: EF_MIPS_CPIC && getABI ( ) . IsN64 ( ) ) EFlags |= ELF :: EF_MIPS_PIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> void CJGFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> void rs6000_emit_eh_reg_restore ( rtx source , rtx scratch ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx operands [ 2 ] ; operands [ 0 ] = source ; operands [ 1 ] = scratch ; if ( info -> lr_save_p ) { rtx frame_rtx = stack_pointer_rtx ; HOST_WIDE_INT sp_offset = 0 ; rtx tmp ; if ( frame_pointer_needed || current_function_calls_alloca || info -> total_size > 32767 ) { tmp = gen_rtx_MEM ( Pmode , frame_rtx ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , rs6000_sr_alias_set ) ; emit_move_insn ( operands [ 1 ] , tmp ) ; frame_rtx = operands [ 1 ] ; } else if ( info -> push_p ) sp_offset = info -> total_size ; tmp = plus_constant ( frame_rtx , info -> lr_save_offset + sp_offset ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , rs6000_sr_alias_set ) ; emit_move_insn ( tmp , operands [ 0 ] ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LINK_REGISTER_REGNUM ) , operands [ 0 ] ) ; } </s>

Emit instructions to restore the link register after determining where its value has been stored .


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , HOST_WIDE_INT val ) { rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; return gen_const_vec_duplicate ( mode , c ) ; } </s>


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips "interrupt"


<s> bool rs6000_emit_set_const ( rtx dest , rtx source ) { machine_mode mode = GET_MODE ( dest ) ; rtx temp , set ; rtx_insn * insn ; HOST_WIDE_INT c ; gcc_checking_assert ( CONST_INT_P ( source ) ) ; c = INTVAL ( source ) ; switch ( mode ) { case QImode : case HImode : emit_insn ( gen_rtx_SET ( VOIDmode , dest , source ) ) ; return true ; case SImode : temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) 0xffff ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & 0xffff ) ) ) ) ; break ; case DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == 0 , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != 0 , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> 32 ) ) ; c = ( ( c & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT ( c ) ) ; return true ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s> bool mips_expand_vec_perm_const ( rtx operands [ 4 ] ) { struct expand_vec_perm_d d ; int i , nelt , which ; unsigned char orig_perm [ MAX_VECT_LEN ] ; rtx sel ; bool ok ; d . target = operands [ 0 ] ; d . op0 = operands [ 1 ] ; d . op1 = operands [ 2 ] ; sel = operands [ 3 ] ; d . vmode = GET_MODE ( d . target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; for ( i = which = 0 ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , 0 , i ) ; int ei = INTVAL ( e ) & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( ! rtx_equal_p ( d . op0 , d . op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = d . op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = d . op0 ; d . one_vector_p = true ; break ; } ok = mips_expand_vec_perm_const_1 ( & d ) ; if ( ! ok && which == 3 ) { d . op0 = operands [ 1 ] ; d . op1 = operands [ 2 ] ; d . one_vector_p = false ; memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; } return ok ; } </s>


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return false ; case PPC :: CMPWI : case PPC :: CMPLWI : case PPC :: CMPDI : case PPC :: CMPLDI : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; Value = MI . getOperand ( 2 ) . getImm ( ) ; Mask = 0xFFFF ; return true ; case PPC :: CMPW : case PPC :: CMPLW : case PPC :: CMPD : case PPC :: CMPLD : case PPC :: FCMPUS : case PPC :: FCMPUD : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; Value = 0 ; Mask = 0 ; return true ; } } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static void mips_start_unique_function ( const char * name ) { tree decl ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = 1 ; TREE_STATIC ( decl ) = 1 ; cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , 0 ) ; switch_to_section ( get_named_section ( decl , NULL , 0 ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( "\t.hidden\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; } </s>

Declare a unique , locally-binding function called NAME , then start its definition .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64MachineFunctionInfo * MFI = MF . getInfo < AArch64MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> bool X86RegisterInfo :: hasReservedSpillSlot ( MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Reg == FramePtr && hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> uint64_t X86TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . is64Bit ( ) ) { Align TyAlign = DL . getABITypeAlign ( Ty ) ; if ( TyAlign > 8 ) return TyAlign . value ( ) ; return 8 ; } Align Alignment ( 4 ) ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty , Alignment ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> inline static int number_of_first_bit_set ( unsigned mask ) { int bit ; for ( bit = 0 ; ( mask & ( 1 << bit ) ) == 0 ; ++ bit ) continue ; return bit ; } </s>

Return the number ( counting from 0 ) of the least significant set bit in MASK .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


"Only support MVT::i32 register passing"

"Can only pass arguments as either registers or via the stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> int arm_no_early_mul_dep ( rtx producer , rtx consumer ) { rtx value , op ; if ( ! arm_get_set_operands ( producer , consumer , & value , & op ) ) return 0 ; if ( GET_CODE ( op ) == PLUS || GET_CODE ( op ) == MINUS ) { if ( GET_CODE ( XEXP ( op , 0 ) ) == MULT ) return ! reg_overlap_mentioned_p ( value , XEXP ( op , 0 ) ) ; else return ! reg_overlap_mentioned_p ( value , XEXP ( op , 1 ) ) ; } return 0 ; } </s>

Return nonzero if the CONSUMER ( a mul or mac op ) does not have an early register mult dependency on the result of PRODUCER .