<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return SYMBOL_GOT_DISP ; gcc_assert ( SYMBOL_REF_P ( x ) ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ; if ( SYMBOL_REF_P ( x ) ) return SYMBOL_GOT_DISP ; return SYMBOL_GOT_DISP ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createAArch64ELFObjectWriter ( OS , OSABI , IsLittleEndian ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool ix86_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( BND_REGNO_P ( regno ) ) return VALID_BND_REG_MODE ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SFmode ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SImode ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> static pad_direction ia64_function_arg_padding ( machine_mode mode , const_tree type ) { if ( TARGET_HPUX && type && AGGREGATE_TYPE_P ( type ) && int_size_in_bytes ( type ) < UNITS_PER_WORD ) return PAD_UPWARD ; return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . For the HP-UX IA64 aggregate parameters are passed stored in the most significant bits of the stack slot .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


"insertBranch must not be told to insert a fallthrough"

"SHUXI branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: BUILD_VECTOR : return PerformBuildVectorCombine ( N , DAG , DCI , Subtarget , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
bool
PPCTargetLowering
::
isFPExtFree
(
EVT
DestVT
,
EVT
SrcVT
)
const
{
assert
(
DestVT
.
isFloatingPoint
(
)
&&
SrcVT
.
isFloatingPoint
(
)
&&
"invalid fpext types"
)
;
return
true
;
}
</s>

Return true if an fpext operation is free ( for instance , because single-precision floating-point numbers are implicitly extended to double-precision ) .


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> GetInstSizeInBytes ( J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> bool MipsTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . hasMips3 ( ) && Subtarget . useSoftFloat ( ) ) { if ( Type == MVT :: i32 ) return true ; } return IsSigned ; } </s>

Returns true if arguments should be sign-extended in lib calls .


<s> static rtx ix86_load_bounds ( rtx slot , rtx ptr , rtx slot_no ) { rtx reg = gen_reg_rtx ( BNDmode ) ; rtx addr ; addr = ix86_get_arg_address_for_bt ( slot , slot_no , arg_pointer_rtx ) ; if ( ! ptr ) { gcc_assert ( MEM_P ( slot ) ) ; ptr = copy_addr_to_reg ( slot ) ; } if ( ! register_operand ( ptr , Pmode ) ) ptr = ix86_zero_extend_to_Pmode ( ptr ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_ldx ( reg , addr , ptr ) : gen_bnd32_ldx ( reg , addr , ptr ) ) ; return reg ; } </s>

Expand pass uses this hook to load bounds for function parameter PTR passed in SLOT in case its bounds are not passed in a register . If SLOT is a memory , then bounds are loaded as for regular pointer loaded from memory . PTR may be NULL in case SLOT is a memory . In such case value of PTR ( if required ) may be loaded from SLOT . If SLOT is NULL or a register then SLOT_NO is an integer constant holding number of the target dependent special slot which should be used to obtain bounds . Return loaded bounds .


<s> void function_builder :: add_overloaded_function ( const function_instance & instance , aarch64_feature_flags required_extensions ) { char * name = get_name ( instance , true ) ; if ( registered_function * * map_value = m_overload_names . get ( name ) ) { gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value ) -> required_extensions & ~ required_extensions ) == 0 ) ; obstack_free ( & m_string_obstack , name ) ; } else { registered_function & rfn = add_function ( instance , name , m_overload_type , NULL_TREE , required_extensions , true , m_direct_overloads ) ; m_overload_names . put ( name , & rfn ) ; } } </s>

Add one function decl for INSTANCE , to be used with manual overload resolution . REQUIRED_EXTENSIONS are the set of architecture extensions that the function requires . For simplicity , deal with duplicate attempts to add the same function , including cases in which the new function requires more features than the original one did . In that case we 'll check whether the required features are available as part of resolving the function to the relevant unique function .


<s>
void
dump
(
)
{
errs
(
)
<<
"SystemZAddressingMode "
<<
this
<<
'\n'
;
errs
(
)
<<
" Base "
;
if
(
Base
.
getNode
(
)
!=
0
)
Base
.
getNode
(
)
->
dump
(
)
;
else
errs
(
)
<<
"null\n"
;
if
(
hasIndexField
(
)
)
{
errs
(
)
<<
" Index "
;
if
(
Index
.
getNode
(
)
!=
0
)
Index
.
getNode
(
)
->
dump
(
)
;
else
errs
(
)
<<
"null\n"
;
}
errs
(
)
<<
" Disp "
<<
Disp
;
if
(
IncludesDynAlloc
)
errs
(
)
<<
" + ADJDYNALLOC"
;
errs
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

SystemZ
"SystemZAddressingMode "
" Base "
0
"null\n"
" Index "
0
"null\n"
" Disp "
" + ADJDYNALLOC"


<s> void arm_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { enum memmodel model = ( enum memmodel ) INTVAL ( model_rtx ) ; machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; rtx_code_label * label ; rtx x ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( model == MEMMODEL_RELAXED || model == MEMMODEL_CONSUME || model == MEMMODEL_RELEASE ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( model == MEMMODEL_RELAXED || model == MEMMODEL_CONSUME || model == MEMMODEL_ACQUIRE ) ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , 0 ) ; arm_emit_load_exclusive ( mode , old_out , mem , use_acquire ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } case PLUS : if ( mode == DImode ) { emit_move_insn ( new_out , old_out ) ; if ( code == PLUS ) x = gen_adddi3 ( new_out , new_out , value ) ; else x = gen_subdi3 ( new_out , new_out , value ) ; emit_insn ( x ) ; break ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ; break ; } arm_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , use_release ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , cond , const0_rtx , label ) ) ; if ( ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( model ) ; } </s>

Split an atomic operation pattern . Operation is given by CODE and is one of PLUS , MINUS , IOR , XOR , SET ( for an exchange operation ) or NOT ( for a nand operation ) . Operation is performed on the content at MEM and on VALUE following the memory model MODEL_RTX . The content at MEM before and after the operation is returned in OLD_OUT and NEW_OUT respectively while the success of the operation is returned in COND . Using a scratch register or an operand register for these determines what result is returned for that pattern .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; GISelCSEAnalysisWrapper & Wrapper = getAnalysis < GISelCSEAnalysisWrapperPass > ( ) . getCSEWrapper ( ) ; auto * CSEInfo = & Wrapper . get ( TPC . getCSEConfig ( ) ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; AArch64PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , & TPC ) ; return C . combineMachineInstrs ( MF , CSEInfo ) ; } </s>

runOnMachineFunction - Emit the function body .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s> static unsigned int bit_count ( unsigned int x ) { const unsigned int m1 = 0x55555555 ; const unsigned int m2 = 0x33333333 ; const unsigned int m4 = 0x0f0f0f0f ; x -= ( x >> 1 ) & m1 ; x = ( x & m2 ) + ( ( x >> 2 ) & m2 ) ; x = ( x + ( x >> 4 ) ) & m4 ; x += x >> 8 ; return ( x + ( x >> 16 ) ) & 0x3f ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - CHILD |ret | return address -- | | \ | | call saved | | registers | | / -- | | \ | | local | | variables frame pointer - > | | / -- | | \ | | outgoing | Decreasing | | arguments | addresses current stack pointer - > | | / | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V | |


<s> static bool contains_string_p ( const char * * arr , const char * str ) { bool res = false ; if ( arr [ 0 ] != NULL ) { res = strstr ( arr [ 0 ] , str ) != NULL ; if ( res ) return res ; if ( arr [ 1 ] != NULL ) return strstr ( arr [ 1 ] , str ) != NULL ; } return false ; } </s>

Return true iff ARR contains STR in one of its two elements .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; if ( ! usePackedStack ( MF ) ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; restrictIT = TM . getSubtarget < ARMSubtarget > ( ) . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>


<s> static void rs6000_set_sched_context ( void * _sc ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; cached_can_issue_more = sc -> cached_can_issue_more ; last_scheduled_insn = sc -> last_scheduled_insn ; load_store_pendulum = sc -> load_store_pendulum ; divide_cnt = sc -> divide_cnt ; vec_pairing = sc -> vec_pairing ; } </s>

Sets the global scheduling context to the one pointed to by _SC .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
PrintImmValue
=
[
&
]
(
const
MCExpr
*
Val
,
const
char
*
VName
)
{
if
(
Val
->
getKind
(
)
==
MCExpr
::
Constant
)
{
if
(
auto
Imm
=
cast
<
MCConstantExpr
>
(
Val
)
->
getValue
(
)
)
OS
<<
VName
<<
Imm
;
}
else
if
(
Val
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
{
if
(
auto
*
SRE
=
dyn_cast
<
MCSymbolRefExpr
>
(
Val
)
)
{
const
MCSymbol
&
Sym
=
SRE
->
getSymbol
(
)
;
if
(
const
char
*
SymNameStr
=
Sym
.
getName
(
)
.
data
(
)
)
OS
<<
VName
<<
SymNameStr
;
}
}
}
;
switch
(
Kind
)
{
case
Token
:
OS
<<
Tok
.
Data
;
break
;
case
Register
:
OS
<<
"Reg:"
<<
X86IntelInstPrinter
::
getRegisterName
(
Reg
.
RegNo
)
;
break
;
case
DXRegister
:
OS
<<
"DXReg"
;
break
;
case
Immediate
:
PrintImmValue
(
Imm
.
Val
,
"Imm:"
)
;
break
;
case
Prefix
:
OS
<<
"Prefix:"
<<
Pref
.
Prefixes
;
break
;
case
Memory
:
OS
<<
"Memory: ModeSize="
<<
Mem
.
ModeSize
;
if
(
Mem
.
Size
)
OS
<<
",Size="
<<
Mem
.
Size
;
if
(
Mem
.
BaseReg
)
OS
<<
",BaseReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
BaseReg
)
;
if
(
Mem
.
IndexReg
)
OS
<<
",IndexReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
IndexReg
)
;
if
(
Mem
.
Scale
)
OS
<<
",Scale="
<<
Mem
.
Scale
;
if
(
Mem
.
Disp
)
PrintImmValue
(
Mem
.
Disp
,
",Disp="
)
;
if
(
Mem
.
SegReg
)
OS
<<
",SegReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
SegReg
)
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

X86
"Reg:"
X86
"DXReg"
"Imm:"
"Prefix:"
"Memory: ModeSize="
",Size="
",BaseReg="
X86
",IndexReg="
X86
",Scale="
",Disp="
",SegReg="
X86


<s> class LLVM_LIBRARY_VISIBILITY KudeyarMCInstLower { typedef MachineOperand :: MachineOperandType MachineOperandType ; KudeyarAsmPrinter & Printer ; public : KudeyarMCInstLower ( KudeyarAsmPrinter & asmprinter ) ; void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; private : MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand & MO ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCOperand LowerOperand ( const MachineOperand & MO , unsigned offset = 0 ) const ; } </s>

Return the MCSymbol for the specified ExternalSymbol .

Kudeyar Kudeyar Kudeyar Kudeyar Kudeyar 0


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tSpill
0


<s>
const
char
*
getPassName
(
)
const
override
{
return
"optimise barriers pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( ) const { if ( STI . hasFeature ( X86 :: Mode16Bit ) ) return 4 ; if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Mode64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s> const Thumb1RegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( N . getOperand ( 0 ) , LHSKnown ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { DAG . computeKnownBits ( N . getOperand ( 1 ) , RHSKnown ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const { if ( ! NumCycles ) return false ; if ( MBB . getParent ( ) -> getFunction ( ) -> optForSize ( ) ) { MachineBasicBlock * Pred = * MBB . pred_begin ( ) ; if ( ! Pred -> empty ( ) ) { MachineInstr * LastMI = & * Pred -> rbegin ( ) ; if ( LastMI -> getOpcode ( ) == ARM :: t2Bcc ) { MachineBasicBlock :: iterator CmpMI = LastMI ; if ( CmpMI != Pred -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == ARM :: tCMPi8 || CmpMI -> getOpcode ( ) == ARM :: t2CMPri ) { unsigned Reg = CmpMI -> getOperand ( 0 ) . getReg ( ) ; unsigned PredReg = 0 ; ARMCC :: CondCodes P = getInstrPredicate ( CmpMI , PredReg ) ; if ( P == ARMCC :: AL && CmpMI -> getOperand ( 1 ) . getImm ( ) == 0 && isARMLowRegister ( Reg ) ) return false ; } } } } } const unsigned ScalingUpFactor = 1024 ; unsigned UnpredCost = Probability . scale ( NumCycles * ScalingUpFactor ) ; UnpredCost += ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; return ( NumCycles + ExtraPredCycles ) * ScalingUpFactor <= UnpredCost ; } </s>


<s>
unsigned
MipsABIInfo
::
GetCalleeAllocdArgSizeInBytes
(
CallingConv
::
ID
CC
)
const
{
if
(
IsO32
(
)
)
return
CC
!=
CallingConv
::
Fast
16
:
0
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
0
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

Obtain the size of the area allocated by the callee for arguments .


<s> bool ARMBaseInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . size ( ) == 2 ) { ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) ( int ) Cond [ 0 ] . getImm ( ) ; Cond [ 0 ] . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return false ; } return true ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


"\nrs6000_preferred_reload_class, return %s, rclass = %s, "

Debug version of rs6000_preferred_reload_class .


<s> SDValue OR1KTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_OR1K32 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool PPCTargetLowering :: IsEligibleForTailCallOptimization ( CallSDNode * TheCall , SDValue Ret , SelectionDAG & DAG ) const { if ( ! PerformTailCallOpt || TheCall -> isVarArg ( ) ) return false ; if ( CheckTailCallReturnConstraints ( TheCall , Ret ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; unsigned CalleeCC = TheCall -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = 0 ; i != TheCall -> getNumArgs ( ) ; i ++ ) { ISD :: ArgFlagsTy Flags = TheCall -> getArgFlags ( i ) ; if ( Flags . isByVal ( ) ) return false ; } SDValue Callee = TheCall -> getCallee ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> void rs6000_expand_vector_extract ( rtx target , rtx vec , int elt ) { enum machine_mode mode = GET_MODE ( vec ) ; enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx mem , x ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) , 0 ) ; mem = adjust_address_nv ( mem , mode , elt * GET_MODE_SIZE ( inner_mode ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_STVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , mem , vec ) , x ) ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , 0 ) ) ; } </s>

Extract field ELT from VEC into TARGET .


"Can't store this register to stack slot"


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; bool IsN64 = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ; if ( Subtarget . inMips16Mode ( ) ) return TFI -> hasFP ( MF ) ? Mips :: S0 : Mips :: SP ; else return TFI -> hasFP ( MF ) ? ( IsN64 ? Mips :: FP_64 : Mips :: FP ) : ( IsN64 ? Mips :: SP_64 : Mips :: SP ) ; } </s>

Mips Mips Mips Mips Mips::S0 Mips::SP Mips::FP_64 Mips::FP Mips::SP_64 Mips::SP


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> const X86InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"MINA32 DAG->DAG Instruction Selection"
;
}
</s>


<s> bool nds32_n9_2r1w_mm_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : if ( post_update_insn_p ( producer ) ) return false ; def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return n9_2r1w_consumed_by_ex_dep_p ( consumer , def_reg ) ; } </s>


<s> bool KudeyarFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; Register ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt , Subtarget -> hasSPE ( ) ? PPC :: EVLDD : PPC :: LFD ) ) return false ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> bool isReg ( ) const { return Kind == CV_Register ; } </s>


<s> bool ELFAArch64AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


A TUNE_MIPS4130 helper function . Given that INSN1 is at the head of the ready queue and that INSN2 is the instruction after it , return true if it is worth promoting INSN2 ahead of INSN1 . Look for cases in which INSN1 and INSN2 can probably issue in parallel , but for which ( INSN2 , INSN1 ) should be less sensitive to instruction alignment than ( INSN1 , INSN2 ) . See 4130.md for more details .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
Triple
(
TM
.
getTargetTriple
(
)
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
getOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


"  Copied r%d to a scalar register r%d for insn %d\n"

Convert all definitions of register REGNO and fix its uses . Scalar copies may be created in case register is used in not convertible insn .


<s> bool system_reg_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { switch ( REGNO ( op ) ) { case PR_REG : case MACL_REG : case MACH_REG : return true ; } return false ; } </s>

Returns 1 if OP is MACL , MACH or PR . The input must be a REG rtx . Used only in general_movsrc_operand .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: GPRPairRegClassID : return Super ; case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : if ( MF . getSubtarget < ARMSubtarget > ( ) . hasNEON ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM::GPRRegClassID ARM::SPRRegClassID ARM::DPRRegClassID ARM::GPRPairRegClassID ARM::QPRRegClassID ARM::QQPRRegClassID ARM::QQQQPRRegClassID ARM


<s> static int mips_adjust_cost ( rtx insn ATTRIBUTE_UNUSED , rtx link , rtx dep ATTRIBUTE_UNUSED , int cost ) { if ( REG_NOTE_KIND ( link ) != 0 ) return 0 ; return cost ; } </s>

Implement TARGET_SCHED_ADJUST_COST . We assume that anti and output dependencies have no cost .


<s> static bool aarch64_if_then_else_costs ( rtx op0 , rtx op1 , rtx op2 , int * cost , bool speed ) { rtx inner ; rtx comparator ; enum rtx_code cmpcode ; const struct cpu_cost_table * extra_cost = aarch64_tune_params . insn_extra_cost ; if ( COMPARISON_P ( op0 ) ) { inner = XEXP ( op0 , 0 ) ; comparator = XEXP ( op0 , 1 ) ; cmpcode = GET_CODE ( op0 ) ; } else { inner = op0 ; comparator = const0_rtx ; cmpcode = NE ; } if ( GET_CODE ( op1 ) == PC || GET_CODE ( op2 ) == PC ) { if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) return true ; else { if ( cmpcode == NE || cmpcode == EQ ) { if ( comparator == const0_rtx ) { if ( GET_CODE ( inner ) == ZERO_EXTRACT ) * cost += rtx_cost ( XEXP ( inner , 0 ) , VOIDmode , ZERO_EXTRACT , 0 , speed ) ; else * cost += rtx_cost ( inner , VOIDmode , cmpcode , 0 , speed ) ; return true ; } if ( register_operand ( inner , VOIDmode ) && aarch64_imm24 ( comparator , VOIDmode ) ) { * cost += COSTS_N_INSNS ( 2 ) ; if ( speed ) * cost += extra_cost -> alu . arith * 2 ; return true ; } } else if ( cmpcode == LT || cmpcode == GE ) { if ( comparator == const0_rtx ) return true ; } } } else if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) { if ( GET_CODE ( op1 ) == COMPARE ) { if ( XEXP ( op1 , 1 ) == const0_rtx ) * cost += 1 ; if ( speed ) { machine_mode mode = GET_MODE ( XEXP ( op1 , 0 ) ) ; const struct cpu_cost_table * extra_cost = aarch64_tune_params . insn_extra_cost ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) * cost += extra_cost -> alu . arith ; else * cost += extra_cost -> fp [ mode == DFmode ] . compare ; } return true ; } if ( GET_CODE ( op1 ) == NEG || GET_CODE ( op1 ) == NOT || ( GET_CODE ( op1 ) == PLUS && XEXP ( op1 , 1 ) == const1_rtx ) ) op1 = XEXP ( op1 , 0 ) ; else if ( GET_CODE ( op1 ) == ZERO_EXTEND && GET_CODE ( op2 ) == ZERO_EXTEND ) { op1 = XEXP ( op1 , 0 ) ; op2 = XEXP ( op2 , 0 ) ; } * cost += rtx_cost ( op1 , VOIDmode , IF_THEN_ELSE , 1 , speed ) ; * cost += rtx_cost ( op2 , VOIDmode , IF_THEN_ELSE , 2 , speed ) ; return true ; } return false ; } </s>

Calculate the cost of calculating ( if_then_else ( OP0 ) ( OP1 ) ( OP2 ) ) , storing it in * COST . Result is true if the total cost of the operation has now been calculated .


<s> bool X86TargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return VT1 == MVT :: i32 && VT2 == MVT :: i64 && Subtarget . is64Bit ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s>
StringRef
ARM64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> void SICMCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> static int ix86_agi_dependant ( rtx insn , rtx dep_insn , enum attr_type insn_type ) { rtx addr ; if ( insn_type == TYPE_LEA && TARGET_PENTIUM ) { addr = PATTERN ( insn ) ; if ( GET_CODE ( addr ) == PARALLEL ) addr = XVECEXP ( addr , 0 , 0 ) ; gcc_assert ( GET_CODE ( addr ) == SET ) ; addr = SET_SRC ( addr ) ; } else { int i ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( GET_CODE ( recog_data . operand [ i ] ) == MEM ) { addr = XEXP ( recog_data . operand [ i ] , 0 ) ; goto found ; } return 0 ; found : ; } return modified_in_p ( addr , dep_insn ) ; } </s>

A subroutine of ix86_adjust_cost -- return true iff INSN has a memory address with operands set by DEP_INSN .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SPISD :: NodeType ) Opcode ) { case SPISD :: FIRST_NUMBER : break ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: EH_SJLJ_SETJMP : return "SPISD::EH_SJLJ_SETJMP" ; case SPISD :: EH_SJLJ_LONGJMP : return "SPISD::EH_SJLJ_LONGJMP" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
bool
X86InstrInfo
::
hasReassociableOperands
(
const
MachineInstr
&
Inst
,
const
MachineBasicBlock
*
MBB
)
const
{
assert
(
Inst
.
getNumExplicitOperands
(
)
==
3
&&
Inst
.
getNumExplicitDefs
(
)
==
1
&&
Inst
.
getNumDefs
(
)
<=
2
&&
"Reassociation needs binary operators"
)
;
const
MachineOperand
*
FlagDef
=
Inst
.
findRegisterDefOperand
(
X86
::
EFLAGS
)
;
assert
(
(
Inst
.
getNumDefs
(
)
==
1
||
FlagDef
)
&&
"Implicit def isn't flags?"
)
;
if
(
FlagDef
&&
!
FlagDef
->
isDead
(
)
)
return
false
;
return
TargetInstrInfo
::
hasReassociableOperands
(
Inst
,
MBB
)
;
}
</s>

Return true when \P Inst has reassociable operands in the same \P MBB .


<s> const LegalizerInfo * getLegalizerInfo ( ) const override { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( "no_split_stack" , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = 1 ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , 12 ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } rtx ret = plus_constant ( Pmode , cfun -> machine -> split_stack_arg_pointer , FIRST_PARM_OFFSET ( current_function_decl ) ) ; return copy_to_reg ( ret ) ; } return virtual_incoming_args_rtx ; } </s>

Return the internal arg pointer used for function incoming arguments . When -fsplit-stack , the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls and suchlike . We 'd really like to use a pseudo here for the internal arg pointer but data-flow analysis is not prepared to accept pseudos as live at the beginning of a function .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static bool sh1_builtin_p ( void ) { return TARGET_SH1 ; } </s>

This function can be used if there are any built-ins that are not for SHmedia . It 's commented out to avoid the defined-but-unused warning .


<s>
unsigned
X86InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
X86
::
JMP_1
&&
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
==
X86
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMachObjectWriter ( new ARMMachObjectWriter ( false , object :: mach :: CTM_ARM , object :: mach :: CSARM_V7 ) , OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
void
mep_asm_output_opcode
(
FILE
*
file
,
const
char
*
ptr
)
{
int
this_opcode
=
op_none
;
const
char
*
hazard
=
0
;
switch
(
*
ptr
)
{
case
'f'
:
if
(
strncmp
(
ptr
,
"fsft"
,
4
)
==
0
&&
!
ISGRAPH
(
ptr
[
4
]
)
)
this_opcode
=
op_fsft
;
break
;
case
'r'
:
if
(
strncmp
(
ptr
,
"ret"
,
3
)
==
0
&&
!
ISGRAPH
(
ptr
[
3
]
)
)
this_opcode
=
op_ret
;
break
;
case
's'
:
if
(
strncmp
(
ptr
,
"stc"
,
3
)
==
0
&&
!
ISGRAPH
(
ptr
[
3
]
)
)
this_opcode
=
op_stc
;
break
;
}
if
(
prev_opcode
==
op_stc
&&
this_opcode
==
op_fsft
)
hazard
=
"nop"
;
if
(
prev_opcode
==
op_stc
&&
this_opcode
==
op_ret
)
hazard
=
"nop"
;
if
(
hazard
)
fprintf
(
file
,
"%s\t# %s-%s hazard\n\t"
,
hazard
,
opnames
[
prev_opcode
]
,
opnames
[
this_opcode
]
)
;
prev_opcode
=
this_opcode
;
}
</s>

This is n't as optimal as it could be , because we do n't know what control register the STC opcode is storing in . We only need to add the nop if it 's the relevant register , but we add it for irrelevant registers also .


<s> void insertSSPDeclarations ( Module & M ) const override { } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; InstructionCost NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , 0 , TTI :: TCK_RecipThroughput ) ; } } unsigned const NumStoresVal = * NumStores . getValue ( ) ; unsigned const Max = ( NumStoresVal ? ( 12 / NumStoresVal ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: ELFCallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; } if ( MF . front ( ) . isLiveIn ( SystemZ :: R6D ) && ZFI -> getRestoreGPRRegs ( ) . LowGPR != SystemZ :: R6D ) for ( auto & MO : MRI -> use_nodbg_operands ( SystemZ :: R6D ) ) MO . setIsKill ( false ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case E_V2DFmode : case E_V2DImode : case E_V2SFmode : case E_V2SImode : return false ; case E_V4DImode : if ( ! TARGET_64BIT ) return false ; case E_V4DFmode : case E_V8SFmode : case E_V8SImode : case E_V16HImode : case E_V32QImode : case E_V4SFmode : case E_V4SImode : case E_V8HImode : case E_V4HImode : break ; case E_V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case E_V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( UINTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


"Scale factor in address must be 1, 2, 4 or 8"

"Displacement in address must fit into 32-bit signed "

Perform target-specific instruction verification .


<s> bool X86InstructionSelector :: selectBinaryOp ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { const unsigned DefReg = I . getOperand ( 0 ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; unsigned NewOpc = I . getOpcode ( ) ; switch ( NewOpc ) { case TargetOpcode :: G_FADD : NewOpc = getFAddOp ( Ty , RB ) ; break ; case TargetOpcode :: G_FSUB : NewOpc = getFSubOp ( Ty , RB ) ; break ; case TargetOpcode :: G_ADD : NewOpc = getAddOp ( Ty , RB ) ; break ; case TargetOpcode :: G_SUB : NewOpc = getSubOp ( Ty , RB ) ; break ; default : break ; } if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s>
void
MipsInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
Opc
=
IsN64
Mips
::
SW_P8
:
Mips
::
SW
;
else
if
(
RC
==
Mips
::
CPU64RegsRegisterClass
)
Opc
=
IsN64
Mips
::
SD_P8
:
Mips
::
SD
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
Opc
=
IsN64
Mips
::
SWC1_P8
:
Mips
::
SWC1
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
Opc
=
Mips
::
SDC1
;
else
if
(
RC
==
Mips
::
FGR64RegisterClass
)
Opc
=
IsN64
Mips
::
SDC164_P8
:
Mips
::
SDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx mips16e_collect_propagate_value ( rtx x , rtx * reg_values ) { x = avoid_constant_pool_reference ( x ) ; if ( UNARY_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , 0 ) , reg_values ) ; return simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , x0 , GET_MODE ( XEXP ( x , 0 ) ) ) ; } if ( ARITHMETIC_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , 0 ) , reg_values ) ; rtx x1 = mips16e_collect_propagate_value ( XEXP ( x , 1 ) , reg_values ) ; return simplify_gen_binary ( GET_CODE ( x ) , GET_MODE ( x ) , x0 , x1 ) ; } if ( REG_P ( x ) && reg_values [ REGNO ( x ) ] && ! rtx_unstable_p ( reg_values [ REGNO ( x ) ] ) ) return reg_values [ REGNO ( x ) ] ; return x ; } </s>

Return a simplified form of X using the register values in REG_VALUES . REG_VALUES [ R ] is the last value assigned to hard register R , or null if R has not been modified . This function is rather limited , but is good enough for our purposes .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { Register GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( * MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool sh_lra_p ( void ) { return sh_lra_flag ; } </s>

Return true if we use LRA instead of reload pass .


"%qE attribute only applies to functions"

"%qE attribute only available for 32-bit"

"%qE attribute requires an integer constant argument"

"argument to %qE attribute is neither zero, nor one"

Handle a `` callee_pop_aggregate_return '' attribute ; arguments as in struct attribute_spec handler .


<s> static void ix86_vec_perm_index_canon ( struct expand_vec_perm_d * d ) { unsigned nelt = d -> nelt ; if ( d -> perm [ 0 ] < nelt ) return ; for ( unsigned i = 0 ; i != nelt ; i ++ ) d -> perm [ i ] = ( d -> perm [ i ] + nelt ) % ( 2 * nelt ) ; std :: swap ( d -> op0 , d -> op1 ) ; return ; } </s>

Canonicalize vec_perm index to make the first index always comes from the first vector .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) , bool matchingInlineAsm = false ) { if ( matchingInlineAsm ) return true ; return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return getParser ( ) . Error ( L , Msg ) ; } </s>


"no identifier found in stanza header.\n"

Parse one stanza of the input overload file . linebuf already contains the first line to parse .


<s> static rtx gen_rx_store_vector ( unsigned int low , unsigned int high ) { unsigned int i ; unsigned int count = ( high - low ) + 2 ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( ( count - 1 ) * UNITS_PER_WORD ) ) ) ; for ( i = 0 ; i < count - 1 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( ( i + 1 ) * UNITS_PER_WORD ) ) ) , gen_rtx_REG ( SImode , high - i ) ) ; return vector ; } </s>

Generate a PARALLEL that will pass the rx_store_multiple_vector predicate .


<s> static unsigned int arm_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( IS_VPR_REGNUM ( regno ) ) return CEIL ( GET_MODE_SIZE ( mode ) , 2 ) ; if ( TARGET_32BIT && regno > PC_REGNUM && regno != FRAME_POINTER_REGNUM && regno != ARG_POINTER_REGNUM && ! IS_VFP_REGNUM ( regno ) ) return 1 ; return ARM_NUM_REGS ( mode ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . On the ARM core regs are UNITS_PER_WORD bytes wide .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool ix86_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) { if ( ( mode == P2QImode || mode == P2HImode ) ) return MASK_PAIR_REGNO_P ( regno ) ; return ( ( TARGET_AVX512F && VALID_MASK_REG_MODE ( mode ) ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; } if ( GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( VALID_AVX512F_REG_OR_XI_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && ( mode == V64SFmode || mode == V64SImode ) && MOD4_SSE_REGNO_P ( regno ) ) return true ; if ( TARGET_AVX512VL && ( VALID_AVX256_REG_OR_OI_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; if ( TARGET_SSE2 && mode == HImode ) return true ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) || VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> void FixupLEAPass :: processInstruction ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr * MI = I ; int opcode = MI -> getOpcode ( ) ; const MCInstrDesc & Desc = MI -> getDesc ( ) ; int AddrOffset = X86II :: getMemoryOperandNo ( Desc . TSFlags , opcode ) ; if ( AddrOffset >= 0 ) { AddrOffset += X86II :: getOperandBias ( Desc ) ; MachineOperand & p = MI -> getOperand ( AddrOffset + X86 :: AddrBaseReg ) ; if ( p . isReg ( ) && p . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( p , I , MFI ) ; } MachineOperand & q = MI -> getOperand ( AddrOffset + X86 :: AddrIndexReg ) ; if ( q . isReg ( ) && q . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( q , I , MFI ) ; } } } </s>

Process a single instruction and collect debug info anchors .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned RA = ABI . IsN64 ( ) ? Mips :: RA_64 : Mips :: RA ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) { setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? 10 : 16 , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"reverse ARM hazard checking unsupported"

RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & FS , bool isT ) : ARMArchVersion ( V4 ) , ARMFPUType ( None ) , UseNEONForSinglePrecisionFP ( false ) , SlowVMLx ( false ) , IsThumb ( isT ) , ThumbMode ( Thumb1 ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( UseMOVT ) , HasFP16 ( false ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; if ( CPUString == "generic" && ( FS . empty ( ) || FS == "generic" ) ) ARMArchVersion = V4T ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 5 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { ARMArchVersion = V7A ; } else if ( SubVer == '6' ) { ARMArchVersion = V6 ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == '2' ) ARMArchVersion = V6T2 ; } else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + 2 && TT [ Idx + 1 ] == 't' ) ARMArchVersion = V4T ; else ARMArchVersion = V4 ; } } if ( ARMArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) ARMArchVersion = V6T2 ; if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( ARMArchVersion < V6 ) ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
const
char
*
aarch64_output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
HOST_WIDE_INT
stack_clash_probe_interval
=
1
<<
param_stack_clash_protection_guard_size
;
xops
[
0
]
=
reg1
;
HOST_WIDE_INT
interval
;
if
(
flag_stack_clash_protection
)
interval
=
stack_clash_probe_interval
;
else
interval
=
PROBE_INTERVAL
;
gcc_assert
(
aarch64_uimm12_shift
(
interval
)
)
;
xops
[
1
]
=
GEN_INT
(
interval
)
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
if
(
flag_stack_clash_protection
)
xops
[
1
]
=
GEN_INT
(
STACK_CLASH_CALLER_GUARD
)
;
else
xops
[
1
]
=
CONST0_RTX
(
GET_MODE
(
xops
[
1
]
)
)
;
output_asm_insn
(
"str\txzr, [%0, %1]"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tb.ne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> EVT MipsTargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> unsigned int call_properties ( const function_instance & ) const override { return 0 ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


<s> bool ARMPassConfig :: addInstSelector ( ) { addPass ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool pru_arg_in_reg_bysize ( size_t sz ) { return sz == 1 || sz == 2 || sz == 3 || sz == 4 || sz == 8 ; } </s>


This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
static
void
rs6000_define_or_undefine_macro
(
bool
define_p
,
const
char
*
name
)
{
if
(
TARGET_DEBUG_BUILTIN
||
TARGET_DEBUG_TARGET
)
fprintf
(
stderr
,
"#%s %s\n"
,
(
define_p
)
"define"
:
"undef"
,
name
)
;
if
(
define_p
)
cpp_define
(
parse_in
,
name
)
;
else
cpp_undef
(
parse_in
,
name
)
;
}
</s>


<s>
Register
SparcTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"i0"
,
SP
::
I0
)
.
Case
(
"i1"
,
SP
::
I1
)
.
Case
(
"i2"
,
SP
::
I2
)
.
Case
(
"i3"
,
SP
::
I3
)
.
Case
(
"i4"
,
SP
::
I4
)
.
Case
(
"i5"
,
SP
::
I5
)
.
Case
(
"i6"
,
SP
::
I6
)
.
Case
(
"i7"
,
SP
::
I7
)
.
Case
(
"o0"
,
SP
::
O0
)
.
Case
(
"o1"
,
SP
::
O1
)
.
Case
(
"o2"
,
SP
::
O2
)
.
Case
(
"o3"
,
SP
::
O3
)
.
Case
(
"o4"
,
SP
::
O4
)
.
Case
(
"o5"
,
SP
::
O5
)
.
Case
(
"o6"
,
SP
::
O6
)
.
Case
(
"o7"
,
SP
::
O7
)
.
Case
(
"l0"
,
SP
::
L0
)
.
Case
(
"l1"
,
SP
::
L1
)
.
Case
(
"l2"
,
SP
::
L2
)
.
Case
(
"l3"
,
SP
::
L3
)
.
Case
(
"l4"
,
SP
::
L4
)
.
Case
(
"l5"
,
SP
::
L5
)
.
Case
(
"l6"
,
SP
::
L6
)
.
Case
(
"l7"
,
SP
::
L7
)
.
Case
(
"g0"
,
SP
::
G0
)
.
Case
(
"g1"
,
SP
::
G1
)
.
Case
(
"g2"
,
SP
::
G2
)
.
Case
(
"g3"
,
SP
::
G3
)
.
Case
(
"g4"
,
SP
::
G4
)
.
Case
(
"g5"
,
SP
::
G5
)
.
Case
(
"g6"
,
SP
::
G6
)
.
Case
(
"g7"
,
SP
::
G7
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> static rtx rs6000_emit_stack_reset ( rtx frame_reg_rtx , HOST_WIDE_INT frame_off , unsigned updt_regno ) { if ( frame_off == 0 && REGNO ( frame_reg_rtx ) == updt_regno ) return NULL_RTX ; rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 ) return emit_insn ( gen_stack_restore_tie ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; if ( frame_off != 0 ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else return emit_move_insn ( updt_reg_rtx , frame_reg_rtx ) ; return NULL_RTX ; } </s>

Emit a sequence of insns , including a stack tie if needed , for resetting the stack pointer . If UPDT_REGNO is not 1 , then do n't reset the stack pointer , but move the base of the frame into reg UPDT_REGNO for use by out-of-line register restore routines .


<s> static machine_mode aarch64_reg_save_mode ( tree fndecl , unsigned regno ) { return GP_REGNUM_P ( regno ) ? E_DImode : ( aarch64_simd_decl_p ( fndecl ) ? E_TFmode : E_DFmode ) ; } </s>

Return the mode a register save/restore should use . DImode for integer registers , DFmode for FP registers in non-SIMD functions ( they only save the bottom half of a 128 bit register ) , or TFmode for FP registers in SIMD functions .


<s> static inline bool return_addr_reg_needed_p ( int leaf_function ) { if ( df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) ) return true ; if ( ! leaf_function || crtl -> uses_pic_offset_table || df_regs_ever_live_p ( INCOMING_RETURN_ADDR_REGNUM ) ) return true ; return false ; } </s>

Return whether the return address register ( % i7 ) is needed .


<s> bool ARMFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> bool MipsTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { PM -> add ( createMipsDelaySlotFillerPass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static recpe_type get_recpe_type ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return ( gen_aarch64_frecpesf ) ; case E_V2SFmode : return ( gen_aarch64_frecpev2sf ) ; case E_V4SFmode : return ( gen_aarch64_frecpev4sf ) ; case E_DFmode : return ( gen_aarch64_frecpedf ) ; case E_V2DFmode : return ( gen_aarch64_frecpev2df ) ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal initial estimate insn depending on machine mode .


<s> static inline tree def_builtin2 ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask ; if ( mask == 0 || ( mask & ix86_isa_flags2 ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values2 |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } return decl ; } </s>

Like def_builtin , but for additional isa2 flags .


Create mask of ones , covering the lowest to highest bits set in VAL_IN . Assumed precondition : VAL_IN Is not zero .


<s> static bool already_warned ( tree fndecl ) { struct decl_chain * warned ; for ( warned = warned_decls ; warned != NULL ; warned = warned -> next ) if ( warned -> fndecl == fndecl ) return true ; return false ; } </s>

Returns TRUE if FNDECL is on our list of warned about decls .


<s> int arm_coproc_mem_operand ( rtx op , bool wb ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( GET_CODE ( op ) != MEM ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) == CONST_INT ) ) ) return TRUE ; if ( GET_CODE ( ind ) == REG ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( wb && ( GET_CODE ( ind ) == PRE_INC || GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC || GET_CODE ( ind ) == POST_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( wb && ( GET_CODE ( ind ) == POST_MODIFY || GET_CODE ( ind ) == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( ind , 1 ) , 0 ) , XEXP ( ind , 0 ) ) ) ind = XEXP ( ind , 1 ) ; if ( GET_CODE ( ind ) == PLUS && GET_CODE ( XEXP ( ind , 0 ) ) == REG && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && GET_CODE ( XEXP ( ind , 1 ) ) == CONST_INT && INTVAL ( XEXP ( ind , 1 ) ) > - 1024 && INTVAL ( XEXP ( ind , 1 ) ) < 1024 && ( INTVAL ( XEXP ( ind , 1 ) ) & 3 ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a valid coprocessor memory address pattern . WB if true if writeback address modes are allowed .


<s> const LC3bRegisterInfo & LC3bInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool isShiftedMask ( uint64_t Mask , EVT VT ) { assert ( VT == MVT :: i32 || VT == MVT :: i64 ) ; if ( VT == MVT :: i32 ) return isShiftedMask_32 ( Mask ) ; return isShiftedMask_64 ( Mask ) ; } </s>

Return true if this APInt value contains a non-empty sequence of ones with the remainder zero .


<s> bool X86CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { if ( Val ) return false ; ( void ) RetCC_X86 ; MIRBuilder . buildInstr ( X86 :: RET ) . addImm ( 0 ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static bool sparc_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) == PLUS && sparc_pic_register_p ( XEXP ( addr , 0 ) ) && symbolic_operand ( XEXP ( addr , 1 ) , VOIDmode ) ) return true ; return false ; } </s>

Return true if ADDR ( a legitimate address expression ) has an effect that depends on the machine mode it is used for . In PIC mode , ( mem : HI [ % l7+a ] ) is not equivalent to ( mem : QI [ % l7+a ] ) ( mem : QI [ % l7+a+1 ] ) because [ % l7+a+1 ] is interpreted as the address of ( a+1 ) .


<s> int SparcRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return SparcGenRegisterInfo :: getDwarfRegNumFull ( RegNum , 0 ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s> static rtx mips_strip_unspec_call ( rtx src ) { if ( GET_CODE ( src ) == UNSPEC && XINT ( src , 1 ) == UNSPEC_LOAD_CALL ) return mips_strip_unspec_address ( XVECEXP ( src , 0 , 1 ) ) ; return NULL_RTX ; } </s>

If SRC is the RHS of a load_call < mode > insn , return the underlying symbol reference . Return NULL_RTX otherwise .


<s> static SDValue WidenVector ( SDValue V64Reg , SelectionDAG & DAG ) { EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = MVT :: getVectorVT ( EltTy , 2 * NarrowSize ) ; SDLoc DL ( V64Reg ) ; return DAG . getNode ( ISD :: INSERT_SUBVECTOR , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( 0 , MVT :: i32 ) ) ; } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s> void sh_emit_scc_to_t ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx t_reg = get_t_reg_rtx ( ) ; enum rtx_code oldcode = code ; machine_mode mode ; switch ( code ) { case NE : gcc_unreachable ( ) ; case LT : code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) std :: swap ( op0 , op1 ) ; mode = GET_MODE ( op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( op1 ) ; op0 = force_reg ( mode , op0 ) ; if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; sh_emit_set_t_insn ( gen_rtx_SET ( t_reg , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) , mode ) ; } </s>

Prepare the operands for an scc instruction ; make sure that the compare has been done and the result is in T_REG .


<s> static void ix86_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { unsigned * cost = ( unsigned * ) data ; * prologue_cost = cost [ vect_prologue ] ; * body_cost = cost [ vect_body ] ; * epilogue_cost = cost [ vect_epilogue ] ; } </s>


"selected fp16 options are incompatible"

"%<-mstack-protector-guard=tls%> needs a hardware TLS register"

Reconfigure global status flags from the active_target.isa .


<s> const MINA32InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


"/* This table has been generated by divtab-sh4.cc.  */"

"\ /* 1/-128 .. 1/127, normalized.  There is an implicit leading 1 in bit 32,\n\ or in bit 33 for powers of two.  */\n\ .balign 4"

Main program to convert flat files into built-in initialization code .


<s> bool AArch64CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , const CallInst & CI , unsigned CalleeReg , unsigned ResReg , ArrayRef < unsigned > ArgRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; SmallVector < MVT , 8 > ArgTys ; for ( auto & Arg : CI . arg_operands ( ) ) ArgTys . push_back ( MVT :: getVT ( Arg -> getType ( ) ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * CallAssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; SmallVector < unsigned , 8 > PhysRegs ; handleAssignments ( MIRBuilder , CallAssignFn , ArgTys , ArgRegs , [ & ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . buildCopy ( PhysReg , ValReg ) ; PhysRegs . push_back ( PhysReg ) ; } ) ; MachineInstrBuilder MIB ; if ( CalleeReg ) MIB = MIRBuilder . buildInstr ( AArch64 :: BLR ) . addUse ( CalleeReg ) ; else MIB = MIRBuilder . buildInstr ( AArch64 :: BL ) . addGlobalAddress ( CI . getCalledFunction ( ) ) ; auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; for ( auto Reg : PhysRegs ) MIB . addUse ( Reg , RegState :: Implicit ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( ! CI . getType ( ) -> isVoidTy ( ) ) handleAssignments ( MIRBuilder , RetAssignFn , MVT :: getVT ( CI . getType ( ) ) , ResReg , [ & ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . buildCopy ( ValReg , PhysReg ) ; MIB . addDef ( PhysReg , RegState :: Implicit ) ; } ) ; return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( Register :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const X86Subtarget & X86MCInstLower :: getSubtarget ( ) const { return AsmPrinter . getSubtarget ( ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { printInstruction ( MI , OS ) ; if ( CommentStream ) { printAnnotation ( OS , Annot ) ; EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned ARMTargetLowering :: getJumpTableEncoding ( ) const { return MachineJumpTableInfo :: EK_Inline ; } </s>

Return the entry encoding for a jump table in the current function .


"Switch should handle all register classes"


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr & MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp , LiveVariables * LV ) const { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; if ( LV ) LV -> replaceKillInstruction ( SrcReg , MI , * Copy ) ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s>
static
void
mmix_option_override
(
void
)
{
if
(
flag_pic
)
{
warning
(
0
,
"-f%s not supported: ignored"
,
(
flag_pic
>
1
)
"PIC"
:
"pic"
)
;
flag_pic
=
0
;
}
}
</s>


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Cond
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterInfo
&
TRI
=
*
MRI
.
getTargetRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
X86
::
getCMovOpcode
(
TRI
.
getRegSizeInBits
(
RC
)
/
8
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
Cond
[
0
]
.
getImm
(
)
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> static unsigned int ix86_minimum_incoming_stack_boundary ( bool sibcall ) { unsigned int incoming_stack_boundary ; if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == 128 ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ; if ( incoming_stack_boundary > MIN_STACK_BOUNDARY && lookup_attribute ( ix86_force_align_arg_pointer_string , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; if ( incoming_stack_boundary < crtl -> parm_stack_boundary ) incoming_stack_boundary = crtl -> parm_stack_boundary ; if ( incoming_stack_boundary > MAIN_STACK_BOUNDARY && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) incoming_stack_boundary = MAIN_STACK_BOUNDARY ; return incoming_stack_boundary ; } </s>

Return minimum incoming stack alignment .


"64-bit code requested on a subtarget that doesn't "

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"created and used with different architectures / ABIs"

"created and used with different endianness"


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool aarch64_evpc_trn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn2v16qi ; break ; case V8QImode : gen = gen_aarch64_trn2v8qi ; break ; case V8HImode : gen = gen_aarch64_trn2v8hi ; break ; case V4HImode : gen = gen_aarch64_trn2v4hi ; break ; case V4SImode : gen = gen_aarch64_trn2v4si ; break ; case V2SImode : gen = gen_aarch64_trn2v2si ; break ; case V2DImode : gen = gen_aarch64_trn2v2di ; break ; case V4HFmode : gen = gen_aarch64_trn2v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn2v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn2v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn2v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn1v16qi ; break ; case V8QImode : gen = gen_aarch64_trn1v8qi ; break ; case V8HImode : gen = gen_aarch64_trn1v8hi ; break ; case V4HImode : gen = gen_aarch64_trn1v4hi ; break ; case V4SImode : gen = gen_aarch64_trn1v4si ; break ; case V2SImode : gen = gen_aarch64_trn1v2si ; break ; case V2DImode : gen = gen_aarch64_trn1v2di ; break ; case V4HFmode : gen = gen_aarch64_trn1v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn1v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn1v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn1v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the TRN instructions .


<s> static rtx aarch64_gen_loadwb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case DImode : return gen_loadwb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; case DFmode : return gen_loadwb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; default : gcc_unreachable ( ) ; } } </s>

Load the pair of register REG , REG2 of mode MODE from stack location BASE , adjusting it by ADJUSTMENT afterwards .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const PPCTargetMachine & TM ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , IsPPC64 ( TargetTriple . getArch ( ) == Triple :: ppc64 || TargetTriple . getArch ( ) == Triple :: ppc64le ) , TM ( TM ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( * this ) , TLInfo ( TM , * this ) , TSInfo ( TM . getDataLayout ( ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool classof ( const CAHPMCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static bool aarch64_if_then_else_costs ( rtx op0 , rtx op1 , rtx op2 , int * cost , bool speed ) { rtx inner ; rtx comparator ; enum rtx_code cmpcode ; if ( COMPARISON_P ( op0 ) ) { inner = XEXP ( op0 , 0 ) ; comparator = XEXP ( op0 , 1 ) ; cmpcode = GET_CODE ( op0 ) ; } else { inner = op0 ; comparator = const0_rtx ; cmpcode = NE ; } if ( GET_CODE ( op1 ) == PC || GET_CODE ( op2 ) == PC ) { if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) return true ; else { if ( cmpcode == NE || cmpcode == EQ ) { if ( comparator == const0_rtx ) { if ( GET_CODE ( inner ) == ZERO_EXTRACT ) * cost += rtx_cost ( XEXP ( inner , 0 ) , ZERO_EXTRACT , 0 , speed ) ; else * cost += rtx_cost ( inner , cmpcode , 0 , speed ) ; return true ; } } else if ( cmpcode == LT || cmpcode == GE ) { if ( comparator == const0_rtx ) return true ; } } } else if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) { if ( GET_CODE ( op1 ) == NEG || GET_CODE ( op1 ) == NOT || ( GET_CODE ( op1 ) == PLUS && XEXP ( op1 , 1 ) == const1_rtx ) ) op1 = XEXP ( op1 , 0 ) ; * cost += rtx_cost ( op1 , IF_THEN_ELSE , 1 , speed ) ; * cost += rtx_cost ( op2 , IF_THEN_ELSE , 2 , speed ) ; return true ; } return false ; } </s>

Calculate the cost of calculating ( if_then_else ( OP0 ) ( OP1 ) ( OP2 ) ) , storing it in * COST . Result is true if the total cost of the operation has now been calculated .


<s> void vax_expand_prologue ( void ) { int regno , offset ; int mask = 0 ; HOST_WIDE_INT size ; rtx insn ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) mask |= 1 << regno ; insn = emit_insn ( gen_procedure_entry_mask ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; vax_add_reg_cfa_offset ( insn , 4 , arg_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , 8 , frame_pointer_rtx ) ; vax_add_reg_cfa_offset ( insn , 12 , pc_rtx ) ; offset = 16 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( mask & ( 1 << regno ) ) { vax_add_reg_cfa_offset ( insn , offset , gen_rtx_REG ( SImode , regno ) ) ; offset += 4 ; } add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , frame_pointer_rtx , offset ) ) ; size = get_frame_size ( ) ; size -= STARTING_FRAME_OFFSET ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ; emit_insn ( gen_blockage ( ) ) ; } </s>

Generate the assembly code for function entry . FILE is a stdio stream to output the code to . SIZE is an int : how many units of temporary storage to allocate . Refer to the array ` regs_ever_live ' to determine which registers to save ; ` regs_ever_live [ I ] ' is nonzero if register number I is ever used in the function . This function is responsible for knowing which registers should not be saved even if used .


<s>
Register
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Case
(
"sp"
,
Mips
::
SP_64
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
else
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Case
(
"sp"
,
Mips
::
SP
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createAArch64ELFObjectWriter ( OS , OSABI , IsLittle ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
bool
MipsSEDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Base
,
Offset
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_m
:
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_R
:
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_ZC
:
if
(
Subtarget
->
inMicroMipsMode
(
)
)
{
if
(
selectAddrRegImm12
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
Subtarget
->
hasMips32r6
(
)
)
{
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1"

Return the output template for emitting a dbra type insn . Note it may perform some output operations on its own before returning the final output string .


"MMIX Internal: This is not a recognized address"


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI , OS ) ; } </s>

Print the specified MCInst to the specified raw_ostream .