<s> void IncomingValueHandler :: assignValueToAddress ( Register ValVReg , const CCValAssign & VA ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt || VA . getLocInfo ( ) == CCValAssign :: AExt ) { auto Load = buildLoad ( LLT :: scalar ( 32 ) , VA ) ; MIRBuilder . buildTrunc ( ValVReg , Load ) ; } else buildLoad ( ValVReg , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool PPCTTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { if ( ! LsrNoInsnsCost ) return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; else return TargetTransformInfoImplBase :: isLSRCostLess ( C1 , C2 ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> void PPCRegisterInfo :: lowerQuadwordSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; bool IsKilled = MI . getOperand ( 0 ) . isKill ( ) ; Register Reg = PPC :: X0 + ( SrcReg - PPC :: G8p0 ) * 2 ; bool IsLittleEndian = Subtarget . isLittleEndian ( ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( PPC :: STD ) ) . addReg ( Reg , getKillRegState ( IsKilled ) ) , FrameIndex , IsLittleEndian ? 8 : 0 ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( PPC :: STD ) ) . addReg ( Reg + 1 , getKillRegState ( IsKilled ) ) , FrameIndex , IsLittleEndian ? 0 : 8 ) ; MBB . erase ( II ) ; } </s>

lowerQuadwordSpilling - Generate code to spill paired general register .


<s> static rtx gen_pop ( rtx arg ) { if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( VOIDmode , arg , gen_rtx_MEM ( word_mode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ) ; } </s>

Generate an `` pop '' pattern for input ARG .


<s> bool aarch64_sve_float_arith_immediate_p ( rtx x , bool negate_p ) { rtx elt ; REAL_VALUE_TYPE r ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_DOUBLE_P ( elt ) ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate_p ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst1 ) ) return true ; if ( real_equal ( & r , & dconsthalf ) ) return true ; return false ; } </s>

Return true if X is a valid immediate operand for an SVE FADD or FSUB instruction . Negate X first if NEGATE_P is true .


<s> bool e8_consumed_by_addr_in_p ( rtx_insn * consumer , rtx def_reg ) { return n8_consumed_by_addr_in_p ( consumer , def_reg ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at AG ( II ) .


<s> void AArch64PassConfig :: addPreLegalizeMachineIR ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createAArch64O0PreLegalizerCombiner ( ) ) ; else addPass ( createAArch64PreLegalizerCombiner ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s> void mips_move_integer ( rtx temp , rtx dest , unsigned HOST_WIDE_INT value ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; machine_mode mode ; unsigned int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = mips_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , temp , x ) ) ; x = temp ; } else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Post Select Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void rs6000_print_isa_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT flags ) { rs6000_print_options_internal ( file , indent , string , flags , "-m" , & rs6000_opt_masks [ 0 ] , ARRAY_SIZE ( rs6000_opt_masks ) ) ; } </s>

Helper function to print the current isa options on a line .


<s> inline void classify_registers ( const_tree , HOST_WIDE_INT bitpos , bool fp , classify_data_t * data ) { if ( fp ) { data -> fp_regs = true ; if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word = true ; } else data -> int_regs = true ; } </s>

A subroutine of function_arg_slotno . Classify the field .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMipsELFObjectWriter ( OS , OSType , IsLittle ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { ( void ) isDivergent ; if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } if ( Subtarget -> hasMVEIntegerOps ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: MQQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: MQQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> const AArch64RegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { if ( UpdateMF ) MFI . setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> static int ix86_fp_comparison_cost ( enum rtx_code code ) { int arith_cost ; switch ( code ) { case UNLE : case UNLT : case LTGT : case GT : case GE : case UNORDERED : case ORDERED : case UNEQ : arith_cost = 4 ; break ; case LT : case NE : case EQ : case UNGE : arith_cost = TARGET_IEEE_FP ? 5 : 4 ; break ; case LE : case UNGT : arith_cost = TARGET_IEEE_FP ? 6 : 4 ; break ; default : gcc_unreachable ( ) ; } switch ( ix86_fp_comparison_strategy ( code ) ) { case IX86_FPCMP_COMI : return arith_cost > 4 ? 3 : 2 ; case IX86_FPCMP_SAHF : return arith_cost > 4 ? 4 : 3 ; default : return arith_cost ; } } </s>

Compute cost of the comparison done using any method . See ix86_fp_comparison_arithmetics_cost for the metrics .


<s> int nds32_can_use_bclr_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival ) ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bclr ' instruction can be used with IVAL .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
ScheduleHazardRecognizer
::
HazardType
PPCHazardRecognizer970
::
getHazardType
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
NoHazard
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
NumIssued
!=
0
&&
(
isFirst
||
isSingle
)
)
return
Hazard
;
if
(
isCracked
&&
NumIssued
>
2
)
return
Hazard
;
switch
(
InstrType
)
{
default
:
assert
(
0
&&
"Unknown instruction type!"
)
;
case
PPCII
::
PPC970_FXU
:
case
PPCII
::
PPC970_LSU
:
case
PPCII
::
PPC970_FPU
:
case
PPCII
::
PPC970_VALU
:
case
PPCII
::
PPC970_VPERM
:
if
(
NumIssued
==
4
)
return
Hazard
;
break
;
case
PPCII
::
PPC970_CRU
:
if
(
NumIssued
>=
2
)
return
Hazard
;
break
;
case
PPCII
::
PPC970_BRU
:
break
;
}
if
(
HasCTRSet
&&
(
Opcode
==
PPC
::
BCTRL_Macho
||
Opcode
==
PPC
::
BCTRL_ELF
)
)
return
NoopHazard
;
if
(
isLoad
&&
NumStores
)
{
unsigned
LoadSize
;
switch
(
Opcode
)
{
default
:
assert
(
0
&&
"Unknown load!"
)
;
case
PPC
::
LBZ
:
case
PPC
::
LBZU
:
case
PPC
::
LBZX
:
case
PPC
::
LBZ8
:
case
PPC
::
LBZU8
:
case
PPC
::
LBZX8
:
case
PPC
::
LVEBX
:
LoadSize
=
1
;
break
;
case
PPC
::
LHA
:
case
PPC
::
LHAU
:
case
PPC
::
LHAX
:
case
PPC
::
LHZ
:
case
PPC
::
LHZU
:
case
PPC
::
LHZX
:
case
PPC
::
LVEHX
:
case
PPC
::
LHBRX
:
case
PPC
::
LHA8
:
case
PPC
::
LHAU8
:
case
PPC
::
LHAX8
:
case
PPC
::
LHZ8
:
case
PPC
::
LHZU8
:
case
PPC
::
LHZX8
:
LoadSize
=
2
;
break
;
case
PPC
::
LFS
:
case
PPC
::
LFSU
:
case
PPC
::
LFSX
:
case
PPC
::
LWZ
:
case
PPC
::
LWZU
:
case
PPC
::
LWZX
:
case
PPC
::
LWA
:
case
PPC
::
LWAX
:
case
PPC
::
LVEWX
:
case
PPC
::
LWBRX
:
case
PPC
::
LWZ8
:
case
PPC
::
LWZX8
:
LoadSize
=
4
;
break
;
case
PPC
::
LFD
:
case
PPC
::
LFDU
:
case
PPC
::
LFDX
:
case
PPC
::
LD
:
case
PPC
::
LDU
:
case
PPC
::
LDX
:
LoadSize
=
8
;
break
;
case
PPC
::
LVX
:
case
PPC
::
LVXL
:
LoadSize
=
16
;
break
;
}
if
(
isLoadOfStoredAddress
(
LoadSize
,
Node
->
getOperand
(
0
)
,
Node
->
getOperand
(
1
)
)
)
return
NoopHazard
;
}
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .


<s> bool n13_consumed_by_e1_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : return n13_alu_e1_insn_dep_reg_p ( consumer , def_reg ) ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_PBSAD : case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_BRANCH : use_rtx = extract_branch_target_rtx ( consumer ) ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; default : return false ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at E1 . Because the address generation unti is at E1 , the address input should be ready at E1 . Note that the branch target is also a kind of addresses , so we have to check it .


<s> bool MipsTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( isCheriPointer ( AS , & DL ) ) { switch ( AM . Scale ) { case 0 : case 1 : return true ; default : return false ; } } switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void MipsELFStreamer :: EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; MipsTargetELFStreamer * ELFTargetStreamer = static_cast < MipsTargetELFStreamer * > ( getTargetStreamer ( ) ) ; for ( unsigned OpIndex = 0 ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } if ( ELFTargetStreamer -> isMicroMipsEnabled ( ) ) { for ( auto Label : Labels ) { MCSymbolData & Data = getOrCreateSymbolData ( Label ) ; MCELF :: setOther ( Data , ELF :: STO_MIPS_MICROMIPS >> 2 ) ; } } Labels . clear ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static tree find_sole_member ( tree type ) { tree field , member = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_SIZE ( field ) ) return NULL_TREE ; if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( member ) return NULL_TREE ; member = field ; } return member ; } </s>

TYPE is a RECORD_TYPE . If there is only a single non-zero-sized member , return it .


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


<s> unsigned VEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: LDrii || MI . getOpcode ( ) == VE :: LDLSXrii || MI . getOpcode ( ) == VE :: LDUrii ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static bool rs6000_secondary_reload_direct_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { bool ret = false ; enum insn_code icode = CODE_FOR_nothing ; int cost = 0 ; int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_POWERPC64 && size == 16 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( TARGET_POWERPC64 && mode == SFmode ) { if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } else if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 2 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } } else if ( ! TARGET_POWERPC64 && size == 8 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && ! altivec_p ) { cost = 3 ; icode = reg_addr [ mode ] . reload_fpr_gpr ; } } if ( icode != CODE_FOR_nothing ) { ret = true ; if ( sri ) { sri -> icode = icode ; sri -> extra_cost = cost ; } } return ret ; } </s>

Power8 helper function for rs6000_secondary_reload , handle all of the special direct moves that involve allocating an extra register , return the insn code of the helper function if there is such a function or CODE_FOR_nothing if not .


<s> unsigned int rs6000_data_alignment ( tree type , unsigned int align , enum data_align how ) { if ( how != align_opt ) { if ( TREE_CODE ( type ) == VECTOR_TYPE ) { if ( ( TARGET_SPE && SPE_VECTOR_MODE ( TYPE_MODE ( type ) ) ) || ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( TYPE_MODE ( type ) ) ) ) { if ( align < 64 ) align = 64 ; } else if ( align < 128 ) align = 128 ; } else if ( TARGET_E500_DOUBLE && TREE_CODE ( type ) == REAL_TYPE && TYPE_MODE ( type ) == DFmode ) { if ( align < 64 ) align = 64 ; } } if ( how != align_abi ) { if ( TREE_CODE ( type ) == ARRAY_TYPE && TYPE_MODE ( TREE_TYPE ( type ) ) == QImode ) { if ( align < BITS_PER_WORD ) align = BITS_PER_WORD ; } } return align ; } </s>

Return alignment of TYPE . Existing alignment is ALIGN . HOW selects whether the alignment is abi mandated , optional , or both abi and optional alignment .


<s> static rtx sparc_function_value_1 ( const_tree type , machine_mode mode , bool outgoing ) { int regbase = ( outgoing ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 32 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_record_value ( type , mode , 0 , 1 , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . else_blk ( ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } else if ( TARGET_ARCH32 && ! ( type && AGGREGATE_TYPE_P ( type ) ) && mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle TARGET_FUNCTION_VALUE , and TARGET_LIBCALL_VALUE target hook . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s> static rtx sparc_delegitimize_address ( rtx x ) { x = delegitimize_mem_from_attrs ( x ) ; if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , 1 ) ) == UNSPEC ) switch ( XINT ( XEXP ( x , 1 ) , 1 ) ) { case UNSPEC_MOVE_PIC : case UNSPEC_TLSLE : x = XVECEXP ( XEXP ( x , 1 ) , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; break ; default : break ; } if ( GET_CODE ( x ) == MINUS && REG_P ( XEXP ( x , 0 ) ) && REGNO ( XEXP ( x , 0 ) ) == PIC_OFFSET_TABLE_REGNUM && GET_CODE ( XEXP ( x , 1 ) ) == LO_SUM && GET_CODE ( XEXP ( XEXP ( x , 1 ) , 1 ) ) == UNSPEC && XINT ( XEXP ( XEXP ( x , 1 ) , 1 ) , 1 ) == UNSPEC_MOVE_PIC_LABEL ) { x = XVECEXP ( XEXP ( XEXP ( x , 1 ) , 1 ) , 0 , 0 ) ; gcc_assert ( GET_CODE ( x ) == LABEL_REF ) ; } return x ; } </s>

Delegitimize an address that was legitimized by the above function .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 Address Type Promotion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ix86_bnd_prefixed_insn_p ( rtx insn ) { if ( insn && CALL_P ( insn ) ) { rtx call = get_call_rtx_from ( insn ) ; if ( call ) return CALL_EXPR_WITH_BOUNDS_P ( call ) ; } return chkp_function_instrumented_p ( current_function_decl ) ; } </s>

Return 1 if control tansfer instruction INSN should be encoded with bnd prefix . If insn is NULL then return 1 when control transfer instructions should be prefixed with bnd by default for current function .


<s>
static
void
loongarch_print_int_branch_condition
(
FILE
*
file
,
enum
rtx_code
code
,
int
letter
)
{
switch
(
code
)
{
case
EQ
:
case
NE
:
case
GT
:
case
GE
:
case
LT
:
case
LE
:
case
GTU
:
case
GEU
:
case
LTU
:
case
LEU
:
fputs
(
GET_RTX_NAME
(
code
)
,
file
)
;
break
;
default
:
output_operand_lossage
(
"'%%%c' is not a valid operand prefix"
,
letter
)
;
break
;
}
}
</s>

PRINT_OPERAND prefix LETTER refers to the integer branch instruction associated with condition CODE . Print the condition part of the opcode to FILE .

loongarch
"'%%%c' is not a valid operand prefix"


<s> int num_insns_constant ( rtx op , machine_mode mode ) { HOST_WIDE_INT low , high ; switch ( GET_CODE ( op ) ) { case CONST_INT : if ( ( INTVAL ( op ) >> 31 ) != 0 && ( INTVAL ( op ) >> 31 ) != - 1 && rs6000_is_valid_and_mask ( op , mode ) ) return 2 ; else return num_insns_constant_wide ( INTVAL ( op ) ) ; case CONST_WIDE_INT : { int i ; int ins = CONST_WIDE_INT_NUNITS ( op ) - 1 ; for ( i = 0 ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) ins += num_insns_constant_wide ( CONST_WIDE_INT_ELT ( op , i ) ) ; return ins ; } case CONST_DOUBLE : if ( mode == SFmode || mode == SDmode ) { long l ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL32 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } long l [ 2 ] ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL64 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; high = l [ WORDS_BIG_ENDIAN == 0 ] ; low = l [ WORDS_BIG_ENDIAN != 0 ] ; if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ; else { if ( ( high == 0 && low >= 0 ) || ( high == - 1 && low < 0 ) ) return num_insns_constant_wide ( low ) ; else if ( rs6000_is_valid_and_mask ( op , mode ) ) return 2 ; else if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } default : gcc_unreachable ( ) ; } } </s>

Return the number of instructions it takes to form a constant in as many gprs are needed for MODE .


<s> static rtx nds32_gen_dup_4_byte_to_word_value ( rtx value ) { rtx value4word = gen_reg_rtx ( SImode ) ; gcc_assert ( GET_MODE ( value ) == QImode || CONST_INT_P ( value ) ) ; if ( CONST_INT_P ( value ) ) { unsigned HOST_WIDE_INT val = UINTVAL ( value ) & GET_MODE_MASK ( QImode ) ; rtx new_val = gen_int_mode ( val | ( val << 8 ) | ( val << 16 ) | ( val << 24 ) , SImode ) ; emit_move_insn ( value4word , new_val ) ; } else { rtx tmp1 , tmp2 , tmp3 , tmp4 , final_value ; tmp1 = expand_binop ( SImode , and_optab , value , gen_int_mode ( 0xff , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp2 = expand_binop ( SImode , ashl_optab , tmp1 , gen_int_mode ( 8 , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp3 = expand_binop ( SImode , ior_optab , tmp1 , tmp2 , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp4 = expand_binop ( SImode , ashl_optab , tmp3 , gen_int_mode ( 16 , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; final_value = expand_binop ( SImode , ior_optab , tmp3 , tmp4 , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_move_insn ( value4word , final_value ) ; } return value4word ; } </s>

Auxiliary function for expand setmem pattern .


<s> bool ThumbRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const ARMSubtarget & STI = MBB . getParent ( ) -> getSubtarget < ARMSubtarget > ( ) ; if ( ! STI . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: saveScavengerRegister ( MBB , I , UseMI , RC , Reg ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( ARMCC :: AL ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugInstr ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) . add ( predOps ( ARMCC :: AL ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> bool ARM64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count & 3 ) != 0 ) { for ( uint64_t i = 0 , e = ( Count & 3 ) ; i != e ; ++ i ) OW -> Write8 ( 0 ) ; } Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> Write32 ( 0xd503201f ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return getTargetMachine ( ) . getOptLevel ( ) != 0 ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI , Subtarget ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ARMISD :: BFI : return PerformBFICombine ( N , DCI ) ; case ARMISD :: VMOVRRD : return PerformVMOVRRDCombine ( N , DCI ) ; case ARMISD :: VMOVDRR : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case ISD :: STORE : return PerformSTORECombine ( N , DCI ) ; case ISD :: BUILD_VECTOR : return PerformBUILD_VECTORCombine ( N , DCI ) ; case ISD :: INSERT_VECTOR_ELT : return PerformInsertEltCombine ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case ARMISD :: VDUPLANE : return PerformVDUPLANECombine ( N , DCI ) ; case ISD :: FP_TO_SINT : case ISD :: FP_TO_UINT : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case ISD :: FDIV : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SELECT_CC : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case ARMISD :: CMOV : return PerformCMOVCombine ( N , DCI . DAG ) ; case ARMISD :: VLD2DUP : case ARMISD :: VLD3DUP : case ARMISD :: VLD4DUP : return CombineBaseUpdate ( N , DCI ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : return CombineBaseUpdate ( N , DCI ) ; default : break ; } break ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; int ZeroOperandPosition = - 1 ; bool BranchWithZeroOperand = false ; if ( I -> isBranch ( ) && ! I -> isPseudo ( ) ) { auto TRI = I -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; ZeroOperandPosition = I -> findRegisterUseOperandIdx ( Mips :: ZERO , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - 1 ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> void X86FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog , Optional < MachineFunction :: DebugInstrOperandPair > InstrNum ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: STACKALLOC_W_PROBING ) ) . addImm ( 0 ) ; } else { emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog , InstrNum ) ; } } </s>


"calling %qD with attribute sseregparm without "

"calling %qT with attribute sseregparm without "

"calling %qD with SSE caling convention without "

Return 1 or 2 , if we can pass up to SSE_REGPARM_MAX SFmode ( 1 ) and DFmode ( 2 ) arguments in SSE registers for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall . Otherwise return 0 .


<s> static bool ia64_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( lookup_attribute ( "syscall_linkage" , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) return false ; return ( decl && ( * targetm . binds_local_p ) ( decl ) ) || TARGET_CONST_GP ; } </s>

True if it is OK to do sibling call optimization for the specified call expression EXP . DECL will be the called function , or NULL if this is an indirect call .


<s> void or1k_expand_compare ( rtx * operands ) { rtx sr_f = gen_rtx_REG ( BImode , SR_F_REGNUM ) ; rtx righthand_op = XEXP ( operands [ 0 ] , 1 ) ; rtx_code cmp_code = GET_CODE ( operands [ 0 ] ) ; bool flag_check_ne = true ; if ( ! TARGET_SFIMM && CONST_INT_P ( righthand_op ) ) XEXP ( operands [ 0 ] , 1 ) = force_reg ( SImode , righthand_op ) ; switch ( cmp_code ) { case LTGT : cmp_code = UNEQ ; flag_check_ne = false ; break ; case ORDERED : cmp_code = UNORDERED ; flag_check_ne = false ; break ; default : break ; } PUT_MODE ( operands [ 0 ] , BImode ) ; PUT_CODE ( operands [ 0 ] , cmp_code ) ; emit_insn ( gen_rtx_SET ( sr_f , operands [ 0 ] ) ) ; operands [ 0 ] = flag_check_ne ? gen_rtx_NE ( VOIDmode , sr_f , const0_rtx ) : gen_rtx_EQ ( VOIDmode , sr_f , const0_rtx ) ; operands [ 1 ] = sr_f ; operands [ 2 ] = const0_rtx ; } </s>

Used to expand patterns `` movsicc '' , `` movqicc '' , `` movhicc '' , `` cstoresi4 '' and `` cbranchsi4 '' . Expands a comparison where OPERANDS is an array of RTX describing the comparison . The first argument OPERANDS [ 0 ] is the operator and OPERANDS [ 1 ] and OPERANDS [ 2 ] are the operands . Split out the compare into SR [ F ] and return a new operation in OPERANDS [ 0 ] . The inputs OPERANDS [ 1 ] and OPERANDS [ 2 ] are not directly used , only overridden .


<s> int nonpic_symbol_mentioned_p ( rtx x ) { register const char * fmt ; register int i ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == PC ) return 1 ; if ( GET_CODE ( x ) == CONST_DOUBLE ) return 0 ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC || XINT ( x , 1 ) == UNSPEC_GOT || XINT ( x , 1 ) == UNSPEC_GOTOFF || XINT ( x , 1 ) == UNSPEC_GOTPLT || XINT ( x , 1 ) == UNSPEC_GOTTPOFF || XINT ( x , 1 ) == UNSPEC_DTPOFF || XINT ( x , 1 ) == UNSPEC_PLT ) ) return 0 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( nonpic_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && nonpic_symbol_mentioned_p ( XEXP ( x , i ) ) ) return 1 ; } return 0 ; } </s>

Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol is n't protected by a PIC unspec .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void ARMHazardRecognizer :: Reset ( ) { LastMI = nullptr ; FpMLxStalls = 0 ; ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> static rtx rs6000_mixed_function_arg ( machine_mode mode , const_tree type , int align_words ) { int n_units ; int i , k ; rtx rvec [ GP_ARG_NUM_REG + 1 ] ; if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; n_units = rs6000_arg_size ( mode , type ) ; if ( n_units == 0 || ( n_units == 1 && mode != BLKmode ) ) return gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; k = 0 ; if ( align_words + n_units > GP_ARG_NUM_REG ) rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; i = 0 ; do { rtx r = gen_rtx_REG ( SImode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * 4 ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_units != 0 ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( k , rvec ) ) ; } </s>

Determine where to place an argument in 64-bit mode with 32-bit ABI .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> ARMSubtarget :: ARMSubtarget ( const Module & M , const std :: string & FS , bool thumb ) : ARMArchVersion ( V4T ) , HasVFP2 ( false ) , IsThumb ( thumb ) , UseThumbBacktraces ( false ) , IsR9Reserved ( false ) , stackAlignment ( 4 ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { std :: string CPU = "generic" ; ParseSubtargetFeatures ( FS , CPU ) ; const std :: string & TT = M . getTargetTriple ( ) ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 6 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer > '4' && SubVer <= '9' ) { if ( SubVer >= '6' ) ARMArchVersion = V6 ; else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } } } if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } else if ( TT . empty ( ) ) { TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) { UseThumbBacktraces = true ; IsR9Reserved = true ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> int ix86_check_movabs ( rtx insn , int opnum ) { rtx set , mem ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; mem = XEXP ( set , opnum ) ; while ( GET_CODE ( mem ) == SUBREG ) mem = SUBREG_REG ( mem ) ; gcc_assert ( GET_CODE ( mem ) == MEM ) ; return ( volatile_ok || ! MEM_VOLATILE_P ( mem ) ) ; } </s>

Return nonzero if OPNUM 's MEM should be matched in movabs * patterns .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static rtx sh_trampoline_adjust_address ( rtx tramp ) { return tramp ; } </s>

On SH5 , trampolines are SHmedia code , so add 1 to the address .


<s> static rtx expand_mla_mls_lane ( function_expander & e , int unspec ) { e . rotate_inputs_left ( 0 , 4 ) ; insn_code icode = code_for_aarch64_lane ( unspec , e . vector_mode ( 0 ) ) ; return e . use_exact_insn ( icode ) ; } </s>

Expand a call to svmla_lane or svmls_lane using floating-point unspec UNSPEC .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: STXVD2X : case PPC :: SPILL_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < ARMSubtarget > ( ) ) ) ) return false ; if ( STI . isGPRegisterReserved ( BasePtr - ARM :: R0 ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


"argument %d must be a constant immediate"

Expand a FCMLA lane expression EXP with code FCODE and result going to TARGET if that is convenient .


<s> static int ix86_function_regparm ( const_tree type , const_tree decl ) { tree attr ; int regparm ; unsigned int ccvt ; if ( TARGET_64BIT ) return ( ix86_function_type_abi ( type ) == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; ccvt = ix86_get_callcvt ( type ) ; regparm = ix86_regparm ; if ( ( ccvt & IX86_CALLCVT_REGPARM ) != 0 ) { attr = lookup_attribute ( "regparm" , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { regparm = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; return regparm ; } } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) return 2 ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) return 1 ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { if ( target -> local && target -> can_change_signature ) { int local_regparm , globals = 0 , regno ; for ( local_regparm = 0 ; local_regparm < REGPARM_MAX ; local_regparm ++ ) if ( fixed_regs [ local_regparm ] ) break ; if ( local_regparm == 3 && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = 2 ; if ( flag_split_stack ) { if ( local_regparm == 3 ) local_regparm = 2 ; else if ( local_regparm == 2 && DECL_STATIC_CHAIN ( target -> decl ) ) local_regparm = 1 ; } for ( regno = AX_REG ; regno <= DI_REG ; regno ++ ) if ( fixed_regs [ regno ] ) globals ++ ; local_regparm = globals < local_regparm ? local_regparm - globals : 0 ; if ( local_regparm > regparm ) regparm = local_regparm ; } } } return regparm ; } </s>

Return the regparm value for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall .


<s> static bool consume ( InternalInstruction * insn , T & ptr ) { auto r = insn -> bytes ; uint64_t offset = insn -> readerCursor - insn -> startLocation ; if ( offset + sizeof ( T ) > r . size ( ) ) return true ; T ret = 0 ; for ( unsigned i = 0 ; i < sizeof ( T ) ; ++ i ) ret |= ( uint64_t ) r [ offset + i ] << ( i * 8 ) ; ptr = ret ; insn -> readerCursor += sizeof ( T ) ; return false ; } </s>


<s> unsigned X86TTIImpl :: getScalarizationOverhead ( Type * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { auto * VecTy = cast < VectorType > ( Ty ) ; unsigned Cost = 0 ; if ( Insert ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ( MScalarTy == MVT :: i16 && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) || ( MScalarTy == MVT :: f32 && ST -> hasSSE41 ( ) ) ) { if ( LT . second . getSizeInBits ( ) <= 128 ) { Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , false ) ; } else { unsigned NumSubVecs = LT . second . getSizeInBits ( ) / 128 ; Cost += ( PowerOf2Ceil ( NumSubVecs ) - 1 ) * LT . first ; Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == MVT :: f32 ) for ( unsigned i = 0 , e = VecTy -> getNumElements ( ) ; i < e ; i += 4 ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( VecTy -> getNumElements ( ) ) ; Cost += ( std :: min < unsigned > ( NumElts , Pow2Elts ) - 1 ) * LT . first ; } } if ( Extract ) Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , false , Extract ) ; return Cost ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> void MipsTargetStreamer :: emitGPRestore ( int Offset , SMLoc IDLoc , const MCSubtargetInfo * STI ) { emitLoadWithImmOffset ( Mips :: LW , Mips :: GP , Mips :: SP , Offset , Mips :: GP , IDLoc , STI ) ; } </s>

Emit the $ gp restore operation for .cprestore .

Mips Mips Mips::LW Mips::GP Mips::SP Mips::GP


<s> bool MipsInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: BuildPairF64 : ExpandBuildPairF64 ( MBB , MI ) ; break ; case Mips :: ExtractElementF64 : ExpandExtractElementF64 ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> const VESubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> const MMIXRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static unsigned HOST_WIDE_INT mips_shift_truncation_mask ( machine_mode mode ) { if ( TARGET_LOONGSON_MMI && VECTOR_MODE_P ( mode ) ) return 0 ; return GET_MODE_BITSIZE ( mode ) - 1 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK . We want to keep the default behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even when TARGET_LOONGSON_VECTORS is true .


<s> virtual unsigned getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { if ( ArgTy -> isVectorTy ( ) ) return std :: min ( DL . getABITypeAlignment ( ArgTy ) , 8U ) ; return DL . getABITypeAlignment ( ArgTy ) ; } </s>

Return the correct alignment for the current calling convention .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tSTRspi
0


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return RegisterVT ; } if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v16i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> int mips_trampoline_code_size ( void ) { if ( TARGET_USE_PIC_FN_ADDR_REG ) return 4 * 4 ; else if ( ptr_mode == DImode ) return 8 * 4 ; else if ( ISA_HAS_LOAD_DELAY ) return 6 * 4 ; else return 4 * 4 ; } </s>

Return the size in bytes of the trampoline code , padded to TRAMPOLINE_ALIGNMENT bits . The static chain pointer and target function address immediately follow .


<s> void sparc_flat_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == 0 ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( VOIDmode , i7 , o7 ) ) ; emit_use ( i7 ) ; } } if ( frame_pointer_needed ) { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; if ( crtl -> uses_pic_offset_table ) load_got_register ( ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the GOT register if needed .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
.
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
const
GlobalValue
*
Global
=
MI
.
getOperand
(
0
)
.
getGlobal
(
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addGlobalAddress
(
Global
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
0
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> static bool sh_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P ) { rtx base , offset ; split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base , INTVAL ( offset ) ) ) return false ; } if ( TARGET_FDPIC && ( SYMBOLIC_CONST_P ( x ) || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && SYMBOLIC_CONST_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) ) ) return false ; if ( TARGET_SHMEDIA && ( ( mode != DFmode && GET_MODE_CLASS ( mode ) != MODE_VECTOR_FLOAT ) || x == CONST0_RTX ( mode ) || ! TARGET_SHMEDIA_FPU || TARGET_SHMEDIA64 ) ) return false ; return GET_CODE ( x ) != CONST_DOUBLE || mode == DFmode || mode == SFmode || mode == DImode || GET_MODE ( x ) == VOIDmode ; } </s>


<s> void func_fma_steering :: analyze_fma_fmul_insn ( fma_forest * ref_forest , du_chain * chain , du_head_p head ) { fma_forest * forest ; fma_node * node = this -> get_fma_node ( chain -> insn ) ; if ( ! node ) { fma_root_node * root_node ; root_node = new fma_root_node ( this , chain , this -> m_next_forest_id ++ ) ; forest = root_node -> get_forest ( ) ; node = root_node ; this -> m_fma_forests . push_back ( forest ) ; } else forest = node -> get_forest ( ) ; node -> set_head ( head ) ; if ( ref_forest ) { ref_forest -> merge_forest ( forest ) ; return ; } for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * child_fma ; rtx fma_rtx , * accum_rtx_p ; if ( ! is_fmul_fmac_insn ( chain -> insn , false ) ) continue ; fma_rtx = SET_SRC ( PATTERN ( chain -> insn ) ) ; if ( GET_CODE ( fma_rtx ) == NEG ) fma_rtx = XEXP ( fma_rtx , 0 ) ; accum_rtx_p = & XEXP ( fma_rtx , 2 ) ; if ( ! REG_P ( * accum_rtx_p ) ) accum_rtx_p = & XEXP ( * accum_rtx_p , 0 ) ; if ( accum_rtx_p != chain -> loc ) continue ; if ( this -> get_fma_node ( chain -> insn ) ) continue ; child_fma = new fma_node ( node , chain ) ; node -> add_child ( child_fma ) ; } } </s>

Allocate and initialize fma_node objects for the FMUL or FMADD/FMSUB instruction in CHAIN- > insn and its dependent FMADD/FMSUB instructions , all part of FOREST . For the children , the associated head is left untouched ( and thus null ) as this function will be called again when considering the chain where they are def . For the parent , the chain is given in HEAD .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_R
:
case
InlineAsm
::
Constraint_S
:
case
InlineAsm
::
Constraint_T
:
SDValue
Base
,
Disp
,
Index
;
if
(
selectBDXAddr
(
SystemZAddressingMode
::
FormBD
,
SystemZAddressingMode
::
Disp12Only
,
Op
,
Base
,
Disp
,
Index
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
break
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

SystemZ
SystemZ
"Unexpected asm memory constraint"
SystemZAddressingMode::FormBD
SystemZAddressingMode::Disp12Only


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; PPCLowering = TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ; PPCSubTarget = TM . getSubtargetImpl ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! PPCSubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>


<s> virtual const MandarinRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool ARMInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > 2 || Pred2 . size ( ) > 2 ) return false ; ARMCC :: CondCodes CC1 = ( ARMCC :: CondCodes ) Pred1 [ 0 ] . getImm ( ) ; ARMCC :: CondCodes CC2 = ( ARMCC :: CondCodes ) Pred2 [ 0 ] . getImm ( ) ; if ( CC1 == CC2 ) return true ; switch ( CC1 ) { default : return false ; case ARMCC :: AL : return true ; case ARMCC :: HS : return CC2 == ARMCC :: HI ; case ARMCC :: LS : return CC2 == ARMCC :: LO || CC2 == ARMCC :: EQ ; case ARMCC :: GE : return CC2 == ARMCC :: GT ; case ARMCC :: LE : return CC2 == ARMCC :: LT ; } } </s>

Returns true if the first specified predicate subsumes the second , e.g .

ARM ARM 2 2 ARMCC::CondCodes ARMCC::CondCodes 0 ARMCC::CondCodes ARMCC::CondCodes 0 ARMCC::AL ARMCC::HS ARMCC::HI ARMCC::LS ARMCC::LO ARMCC::EQ ARMCC::GE ARMCC::GT ARMCC::LE ARMCC::LT


<s> void X86InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . canRealignStack ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < PPCSubtarget > ( ) . getInstrInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; bool Changed = false ; for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock ( B ) ) Changed = true ; return Changed ; } </s>


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( const Type * Ty ) const { if ( Subtarget -> is64Bit ( ) ) { unsigned TyAlign = TD -> getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget -> hasXMM ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> void AArch64TargetStreamer :: emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } getStreamer ( ) . EmitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { llvm_unreachable ( "UNIMP" ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> int attr_length_indirect_call ( rtx insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) return 12 ; if ( TARGET_FAST_INDIRECT_CALLS || ( ! TARGET_PORTABLE_RUNTIME && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < 7600000 ) || distance < 240000 ) ) ) return 8 ; if ( flag_pic ) return 24 ; if ( TARGET_PORTABLE_RUNTIME ) return 20 ; return 12 ; } </s>

Return the attribute length of the indirect call instruction INSN . The length must match the code generated by output_indirect call . The returned length includes the delay slot . Currently , the delay slot of an indirect call sequence is not exposed and it is used by the sequence itself .


<s> TargetLowering :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { auto PTy = cast < PointerType > ( LI -> getPointerOperand ( ) -> getType ( ) ) ; return needsCmpXchgNb ( PTy -> getElementType ( ) ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> void KudeyarFrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; KudeyarMachineFunctionInfo * KudeyarFI = MF . getInfo < KudeyarMachineFunctionInfo > ( ) ; const KudeyarInstrInfo & TII = * static_cast < const KudeyarInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = 0 ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - 4 ; NumBytes = FrameSize - KudeyarFI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Kudeyar :: PUSH_R ) ) . addReg ( Kudeyar :: FP , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Kudeyar :: MOV_RR ) , Kudeyar :: FP ) . addReg ( Kudeyar :: SP ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( Kudeyar :: FP ) ; } else NumBytes = StackSize - KudeyarFI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == Kudeyar :: PUSH_R ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Kudeyar :: SUB_RI32 ) , Kudeyar :: SP ) . addReg ( Kudeyar :: SP ) . addImm ( NumBytes ) ; } } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Kudeyar Kudeyar Kudeyar Kudeyar Kudeyar Kudeyar Kudeyar 0 4 Kudeyar Kudeyar::PUSH_R Kudeyar::FP Kudeyar::MOV_RR Kudeyar::FP Kudeyar::SP Kudeyar::FP Kudeyar Kudeyar::PUSH_R Kudeyar::SUB_RI32 Kudeyar::SP Kudeyar::SP


<s> static bool arm_fastmul_rtx_costs ( rtx x , int code , int outer_code , int * total ) { enum machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = 8 ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = 30 ; return true ; } if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 8 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost += 2 ; } * total = cost ; return true ; } * total = 8 + ( REG_OR_SUBREG_REG ( XEXP ( x , 0 ) ) ? 0 : 4 ) + ( REG_OR_SUBREG_REG ( XEXP ( x , 1 ) ) ? 0 : 4 ) ; return true ; default : * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; } } </s>

RTX cost for cores with a fast multiply unit ( M variants ) .


<s> static void ix86_add_cfa_restore_note ( rtx insn , rtx reg , HOST_WIDE_INT cfa_offset ) { if ( ! crtl -> shrink_wrapped && cfa_offset <= cfun -> machine -> fs . red_zone_offset ) return ; if ( insn ) { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else queued_cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , reg , queued_cfa_restores ) ; } </s>

Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack manipulation insn . The value is on the stack at CFA - CFA_OFFSET . Do n't add the note if the previously saved value will be left untouched within stack red-zone till return , as unwinders can find the same value in the register and on the stack .


<s> const CallLowering * getCallLowering ( ) const override { return CL . get ( ) ; } </s>


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; return PO ; } </s>

Compute the offset immediately following this block .


<s> static enum reg_class init_unavailable ( tag_insn_info * insn_info , tag_map_t & tag_map , du_head_p head , HARD_REG_SET * unavailable ) { unsigned dest = head -> regno ; enum reg_class super_class = NO_REGS ; machine_mode mode = GET_MODE ( insn_info -> dest ) ; CLEAR_HARD_REG_SET ( * unavailable ) ; for ( struct du_chain * tmp = head -> first ; tmp ; tmp = tmp -> next_use ) { if ( DEBUG_INSN_P ( tmp -> insn ) ) continue ; * unavailable |= ~ reg_class_contents [ tmp -> cl ] ; super_class = reg_class_superunion [ ( int ) super_class ] [ ( int ) tmp -> cl ] ; } for ( unsigned i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( fixed_regs [ i ] || global_regs [ i ] ) add_to_hard_reg_set ( unavailable , mode , i ) ; arg_pair_t arg = arg_pair_t ( insn_info , unavailable ) ; tag_map . traverse < arg_pair_t * , check_colliding_tags > ( & arg ) ; ignore_all_aliases ( unavailable , mode , dest & 0xf ) ; return super_class ; } </s>

Initialize and build a set of hard register numbers UNAVAILABLE to avoid for renaming . INSN_INFO is the original insn , TAG_MAP is the map of the list of insns indexed by their tags , HEAD is the def/use chain head of the destination register of the original insn . The routine returns the super class of register classes that may be used during the renaming .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: VSELECT : case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: ADD : return PerformAddCombine ( N , DAG , Subtarget ) ; case ISD :: SUB : return PerformSubCombine ( N , DAG , Subtarget ) ; case X86ISD :: ADC : return PerformADCCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: AND : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: XOR : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: LOAD : return PerformLOADCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case ISD :: SINT_TO_FP : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case ISD :: FADD : return PerformFADDCombine ( N , DAG , Subtarget ) ; case ISD :: FSUB : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG , Subtarget ) ; case X86ISD :: SETCC : return PerformSETCCCombine ( N , DAG ) ; case X86ISD :: SHUFP : case X86ISD :: PALIGN : case X86ISD :: UNPCKH : case X86ISD :: UNPCKL : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case X86ISD :: VPERMILP : case X86ISD :: VPERM2X128 : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static rtx mips16_local_alias ( rtx func ) { if ( mips16_local_aliases == NULL ) mips16_local_aliases = hash_map < rtx , rtx , local_alias_traits > :: create_ggc ( 37 ) ; bool existed ; rtx * slot = & mips16_local_aliases -> get_or_insert ( func , & existed ) ; gcc_assert ( slot != NULL ) ; if ( ! existed ) { const char * func_name , * local_name ; rtx local ; func_name = targetm . strip_name_encoding ( XSTR ( func , 0 ) ) ; local_name = ACONCAT ( ( "__fn_local_" , func_name , NULL ) ) ; local = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( local_name ) ) ; SYMBOL_REF_FLAGS ( local ) = SYMBOL_REF_FLAGS ( func ) | SYMBOL_FLAG_LOCAL ; * slot = local ; } return * slot ; } </s>

FUNC is the symbol for a locally-defined hard-float MIPS16 function . Return a local alias for it , creating a new one if necessary .


<s> void rs6000_expand_vector_extract ( rtx target , rtx vec , rtx elt ) { machine_mode mode = GET_MODE ( vec ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx mem ; if ( VECTOR_MEM_VSX_P ( mode ) && CONST_INT_P ( elt ) ) { switch ( mode ) { default : break ; case E_V1TImode : gcc_assert ( INTVAL ( elt ) == 0 && inner_mode == TImode ) ; emit_move_insn ( target , gen_lowpart ( TImode , vec ) ) ; break ; case E_V2DFmode : emit_insn ( gen_vsx_extract_v2df ( target , vec , elt ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_extract_v2di ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf ( target , vec , elt ) ) ; return ; case E_V16QImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v16qi ( target , vec , elt ) ) ; return ; } else break ; case E_V8HImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v8hi ( target , vec , elt ) ) ; return ; } else break ; case E_V4SImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v4si ( target , vec , elt ) ) ; return ; } break ; } } else if ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( elt ) && TARGET_DIRECT_MOVE_64BIT ) { if ( GET_MODE ( elt ) != DImode ) { rtx tmp = gen_reg_rtx ( DImode ) ; convert_move ( tmp , elt , 0 ) ; elt = tmp ; } else if ( ! REG_P ( elt ) ) elt = force_reg ( DImode , elt ) ; switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_extract_v2df_var ( target , vec , elt ) ) ; return ; case E_V2DImode : emit_insn ( gen_vsx_extract_v2di_var ( target , vec , elt ) ) ; return ; case E_V4SFmode : emit_insn ( gen_vsx_extract_v4sf_var ( target , vec , elt ) ) ; return ; case E_V4SImode : emit_insn ( gen_vsx_extract_v4si_var ( target , vec , elt ) ) ; return ; case E_V8HImode : emit_insn ( gen_vsx_extract_v8hi_var ( target , vec , elt ) ) ; return ; case E_V16QImode : emit_insn ( gen_vsx_extract_v16qi_var ( target , vec , elt ) ) ; return ; default : gcc_unreachable ( ) ; } } gcc_assert ( CONST_INT_P ( elt ) ) ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , vec ) ; mem = adjust_address_nv ( mem , inner_mode , INTVAL ( elt ) * GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , 0 ) ) ; } </s>

Extract field ELT from VEC into TARGET .


<s> void mips_expand_conditional_move ( rtx * operands ) { rtx cond ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; mips_emit_compare ( & code , & op0 , & op1 , true ) ; cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; if ( ISA_HAS_SEL && INTEGRAL_MODE_P ( GET_MODE ( operands [ 2 ] ) ) && register_operand ( operands [ 2 ] , VOIDmode ) && register_operand ( operands [ 3 ] , VOIDmode ) ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; rtx temp = gen_reg_rtx ( mode ) ; rtx temp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ 2 ] , const0_rtx ) ) ) ; cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , GET_MODE ( op0 ) , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp2 , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ 3 ] , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IOR ( mode , temp , temp2 ) ) ) ; } else { if ( FLOAT_MODE_P ( GET_MODE ( operands [ 2 ] ) ) && ! ISA_HAS_SEL ) { operands [ 2 ] = force_reg ( GET_MODE ( operands [ 0 ] ) , operands [ 2 ] ) ; operands [ 3 ] = force_reg ( GET_MODE ( operands [ 0 ] ) , operands [ 3 ] ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , cond , operands [ 2 ] , operands [ 3 ] ) ) ) ; } } </s>

Perform the comparison in OPERANDS [ 1 ] . Move OPERANDS [ 2 ] into OPERANDS [ 0 ] if the condition holds , otherwise move OPERANDS [ 3 ] into OPERANDS [ 0 ] .


<s> static void sh_setup_incoming_varargs ( cumulative_args_t ca , const function_arg_info & arg , int * pretend_arg_size , int second_time ATTRIBUTE_UNUSED ) { gcc_assert ( cfun -> stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs = 0 , anon_parm_regs ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , arg . mode ) + CEIL ( arg . promoted_size_in_bytes ( ) , UNITS_PER_WORD ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > 0 ) * pretend_arg_size = anon_parm_regs * 4 ; } } </s>

We actually emit the code in sh_expand_prologue . We used to use a static variable to flag that we need to emit this code , but that does n't when inlining , when functions are deferred and then emitted later . Fortunately , we already have two flags that are part of struct function that tell if a function uses varargs or stdarg .


<s> bool mips_can_use_return_insn ( void ) { if ( cfun -> machine -> interrupt_handler_p ) return false ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return false ; return cfun -> machine -> frame . total_size == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> unsigned getElementSize ( ) const { return CurType . ElementSize ; } </s>

Return the size of an element read or written by Inst .


<s> static bool expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( target , x ) ; rtx_insn * insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel perm ) ) ) and return true if that 's a valid instruction in the active ISA .


<s>
const
MCPhysReg
*
PPCRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
PPCSubtarget
&
Subtarget
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
{
if
(
!
TM
.
isPPC64
(
)
&&
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"AnyReg unimplemented on 32-bit AIX."
)
;
if
(
Subtarget
.
hasVSX
(
)
)
return
CSR_64_AllRegs_VSX_SaveList
;
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_64_AllRegs_Altivec_SaveList
;
return
CSR_64_AllRegs_SaveList
;
}
if
(
TM
.
isPPC64
(
)
&&
MF
->
getInfo
<
PPCFunctionInfo
>
(
)
->
isSplitCSR
(
)
)
{
if
(
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"SplitCSR unimplemented on AIX."
)
;
return
CSR_SRV464_TLS_PE_SaveList
;
}
bool
SaveR2
=
MF
->
getRegInfo
(
)
.
isAllocatable
(
PPC
::
X2
)
&&
!
Subtarget
.
isUsingPCRelativeCalls
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Cold
)
{
if
(
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"Cold calling unimplemented on AIX."
)
;
if
(
TM
.
isPPC64
(
)
)
{
if
(
Subtarget
.
hasAltivec
(
)
)
return
SaveR2
CSR_SVR64_ColdCC_R2_Altivec_SaveList
:
CSR_SVR64_ColdCC_Altivec_SaveList
;
return
SaveR2
CSR_SVR64_ColdCC_R2_SaveList
:
CSR_SVR64_ColdCC_SaveList
;
}
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_SVR32_ColdCC_Altivec_SaveList
;
else
if
(
Subtarget
.
hasSPE
(
)
)
return
CSR_SVR32_ColdCC_SPE_SaveList
;
return
CSR_SVR32_ColdCC_SaveList
;
}
if
(
TM
.
isPPC64
(
)
)
{
if
(
Subtarget
.
hasAltivec
(
)
)
return
SaveR2
CSR_PPC64_R2_Altivec_SaveList
:
CSR_PPC64_Altivec_SaveList
;
return
SaveR2
CSR_PPC64_R2_SaveList
:
CSR_PPC64_SaveList
;
}
if
(
Subtarget
.
isAIXABI
(
)
)
return
CSR_AIX32_SaveList
;
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_SVR432_Altivec_SaveList
;
else
if
(
Subtarget
.
hasSPE
(
)
)
return
CSR_SVR432_SPE_SaveList
;
return
CSR_SVR432_SaveList
;
}
</s>

PowerPC
PPC
PPC
PPC
PPC
"AnyReg unimplemented on 32-bit AIX."
PPC
PPC
"SplitCSR unimplemented on AIX."
PPC::X2
"Cold calling unimplemented on AIX."
PPC
PPC
PPC
PPC
PPC
PPC


<s> const uint32_t * CSKYRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


"Only Linux target is expected to contain LOAD_STACK_GUARD"

This function is called for all pseudo instructions that remain after register allocation .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
(
Kind
==
k_Register
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
Divisor
.
isNegatedPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasCMov
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
APInt
Lg2Mask
=
APInt
::
getLowBitsSet
(
VT
.
getSizeInBits
(
)
,
Lg2
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
Lg2Mask
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i8
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> static rtx gen_load_pcrel_sym ( rtx op0 , rtx op1 , rtx op2 , rtx op3 ) { int orig_flag_pic = flag_pic ; rtx insn ; flag_pic = 0 ; if ( TARGET_ARCH64 ) insn = gen_load_pcrel_symdi ( op0 , op1 , op2 , op3 ) ; else insn = gen_load_pcrel_symsi ( op0 , op1 , op2 , op3 ) ; flag_pic = orig_flag_pic ; return insn ; } </s>

Wrapper around the load_pcrel_sym { si , di } patterns .


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; if ( const auto * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; if ( const auto * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; if ( isa < UndefValue > ( C ) ) { unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : break ; case MVT :: f32 : if ( ! Subtarget -> hasSSE1 ( ) ) Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( ! Subtarget -> hasSSE2 ( ) ) Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : Opc = X86 :: LD_Fp080 ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> SDValue LanaiTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: OR : case ISD :: XOR : return combineSelectAndUseCommutative ( N , DCI , false ) ; case ISD :: AND : return combineSelectAndUseCommutative ( N , DCI , true ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

Lanai Lanai ISD::ADD ISD::OR ISD::XOR ISD::AND ISD::SUB


<s> bool ARM64TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode * Node : Copy -> uses ( ) ) { if ( Node -> getOpcode ( ) != ARM64ISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void sh_expand_sym_label2reg ( rtx reg , rtx sym , rtx lab , bool sibcall_p ) { const_tree decl = SYMBOL_REF_DECL ( sym ) ; bool is_weak = ( decl && DECL_P ( decl ) && DECL_WEAK ( decl ) ) ; if ( ! is_weak && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_sym_label2reg ( reg , sym , lab ) ) ; else if ( sibcall_p && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_symPCREL_label2reg ( reg , sym , lab ) ) ; else emit_insn ( gen_symPLT_label2reg ( reg , sym , lab ) ) ; } </s>

Expand to appropriate sym * _label2reg for SYM and SIBCALL_P .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) ) { return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static bool is_load_p ( rtx_insn * insn ) { enum attr_itanium_class insn_class = ia64_safe_itanium_class ( insn ) ; return ( ( insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD ) && get_attr_check_load ( insn ) == CHECK_LOAD_NO ) ; } </s>

Return TRUE if INSN is a load ( either normal or speculative , but not a speculation check ) , FALSE otherwise .


<s>
static
void
sparc_file_end
(
void
)
{
if
(
got_helper_needed
)
{
const
char
*
name
=
XSTR
(
got_helper_rtx
,
0
)
;
bool
do_cfi
;
if
(
USE_HIDDEN_LINKONCE
)
{
tree
decl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
name
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
DECL_RESULT
(
decl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
make_decl_one_only
(
decl
,
DECL_ASSEMBLER_NAME
(
decl
)
)
;
DECL_VISIBILITY
(
decl
)
=
VISIBILITY_HIDDEN
;
DECL_VISIBILITY_SPECIFIED
(
decl
)
=
1
;
resolve_unique_section
(
decl
,
0
,
flag_function_sections
)
;
allocate_struct_function
(
decl
,
true
)
;
cfun
->
is_thunk
=
1
;
current_function_decl
=
decl
;
init_varasm_status
(
)
;
assemble_start_function
(
decl
,
name
)
;
}
else
{
const
int
align
=
floor_log2
(
FUNCTION_BOUNDARY
/
BITS_PER_UNIT
)
;
switch_to_section
(
text_section
)
;
if
(
align
>
0
)
ASM_OUTPUT_ALIGN
(
asm_out_file
,
align
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
}
do_cfi
=
dwarf2out_do_cfi_asm
(
)
;
if
(
do_cfi
)
output_asm_insn
(
".cfi_startproc"
,
)
;
if
(
flag_delayed_branch
)
{
output_asm_insn
(
"jmp\t%%o7+8"
,
)
;
output_asm_insn
(
" add\t%%o7, %0, %0"
,
&
got_register_rtx
)
;
}
else
{
output_asm_insn
(
"add\t%%o7, %0, %0"
,
&
got_register_rtx
)
;
output_asm_insn
(
"jmp\t%%o7+8"
,
)
;
output_asm_insn
(
" nop"
,
)
;
}
if
(
do_cfi
)
output_asm_insn
(
".cfi_endproc"
,
)
;
}
if
(
NEED_INDICATE_EXEC_STACK
)
file_end_indicate_exec_stack
(
)
;
solaris_file_end
(
)
;
}
</s>

Do whatever processing is required at the end of a file .


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
PM
->
add
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
getARMSubtarget
(
)
.
hasNEON
(
)
)
PM
->
add
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
PM
->
add
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
addPass
(
IfConverterID
)
;
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
PM
->
add
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM::DPRRegClass
ARM
ARM
ARM


<s> void PPCRegisterInfo :: adjustStackMapLiveOutMask ( uint32_t * Mask ) const { unsigned PseudoRegs [ ] = { PPC :: ZERO , PPC :: ZERO8 , PPC :: RM } ; for ( unsigned i = 0 , ie = array_lengthof ( PseudoRegs ) ; i != ie ; ++ i ) { unsigned Reg = PseudoRegs [ i ] ; Mask [ Reg / 32 ] &= ~ ( 1u << ( Reg % 32 ) ) ; } } </s>

Prior to adding the live-out mask to a stackmap or patchpoint instruction , provide the target the opportunity to adjust it ( mainly to remove pseudo-registers that should be ignored ) .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86SpeculativeLoadHardeningPass ( ) ) ; addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86DynAllocaExpander ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PreTileConfigPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static void scan_record_type ( tree type , int * intregs_p , int * fpregs_p , int * packed_p ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) scan_record_type ( TREE_TYPE ( field ) , intregs_p , fpregs_p , 0 ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU ) * fpregs_p = 1 ; else * intregs_p = 1 ; if ( packed_p && DECL_PACKED ( field ) ) * packed_p = 1 ; } } } </s>

Scan the record type TYPE and return the following predicates : - INTREGS_P : the record contains at least one field or sub-field that is eligible for promotion in integer registers . - FP_REGS_P : the record contains at least one field or sub-field that is eligible for promotion in floating-point registers . - PACKED_P : the record contains at least one field that is packed . Sub-fields are not taken into account for the PACKED_P predicate .


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCFrameLowering
*
PPCFI
=
static_cast
<
const
PPCFrameLowering
*
>
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
)
;
unsigned
StackEst
=
PPCFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

PowerPC
PPC
0
"Local offset must be negative"
PPC::ADDI
PPC::ADDI8
2
0
PPC
PPC
PPC
PPC


<s>
bool
MipsOs16
::
runOnModule
(
Module
&
M
)
{
bool
usingMask
=
Mips32FunctionMask
.
length
(
)
>
0
;
bool
doneUsingMask
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Run on Module MipsOs16 \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
if
(
usingMask
)
LLVM_DEBUG
(
dbgs
(
)
<<
"using mask \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
unsigned
int
functionIndex
=
0
;
bool
modified
=
false
;
for
(
auto
&
F
:
M
)
{
if
(
F
.
isDeclaration
(
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Working on "
<<
F
.
getName
(
)
<<
"\n"
)
;
if
(
usingMask
)
{
if
(
!
doneUsingMask
)
{
if
(
functionIndex
==
Mips32FunctionMask
.
length
(
)
)
functionIndex
=
0
;
switch
(
Mips32FunctionMask
[
functionIndex
]
)
{
case
'1'
:
LLVM_DEBUG
(
dbgs
(
)
<<
"mask forced mips32: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"nomips16"
)
;
break
;
case
'.'
:
doneUsingMask
=
true
;
break
;
default
:
break
;
}
functionIndex
++
;
}
}
else
{
if
(
needsFP
(
F
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"os16 forced mips32: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"nomips16"
)
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"os16 forced mips16: "
<<
F
.
getName
(
)
<<
"\n"
)
;
F
.
addFnAttr
(
"mips16"
)
;
}
}
}
return
modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

Mips
Mips
Mips
0
"Run on Module MipsOs16 \n"
Mips
"\n"
"using mask \n"
Mips
"\n"
0
"Working on "
"\n"
Mips
0
Mips
"mask forced mips32: "
"\n"
"nomips16"
"os16 forced mips32: "
"\n"
"nomips16"
"os16 forced mips16: "
"\n"
"mips16"


<s> int SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } else { FrameReg = SP :: O6 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6