<s>
void
ARMTargetStreamer
::
emitInst
(
uint32_t
Inst
,
char
Suffix
)
{
unsigned
Size
;
char
Buffer
[
4
]
;
const
bool
LittleEndian
=
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
->
isLittleEndian
(
)
;
switch
(
Suffix
)
{
case
'\0'
:
Size
=
4
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
++
)
{
const
unsigned
I
=
LittleEndian
(
Size
II
1
)
:
II
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I
*
CHAR_BIT
)
;
}
break
;
case
'n'
:
case
'w'
:
Size
=
(
Suffix
==
'n'
2
:
4
)
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
=
II
+
2
)
{
const
unsigned
I0
=
LittleEndian
II
+
0
:
II
+
1
;
const
unsigned
I1
=
LittleEndian
II
+
1
:
II
+
0
;
Buffer
[
Size
II
2
]
=
uint8_t
(
Inst
>>
I0
*
CHAR_BIT
)
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I1
*
CHAR_BIT
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid Suffix"
)
;
}
getStreamer
(
)
.
emitBytes
(
StringRef
(
Buffer
,
Size
)
)
;
}
</s>

Callback used to implement the .inst directive .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s> static void ia64_sysv4_init_libfuncs ( void ) { ia64_init_libfuncs ( ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; } </s>

Rename the TFmode libfuncs available from soft-fp in glibc using the HPUX conventions .


<s> void SparcRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; NumBytes += 92 ; NumBytes = ( NumBytes + 7 ) & ~ 7 ; NumBytes = - NumBytes ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const AArch64Disassembler * Dis = static_cast < const AArch64Disassembler * > ( D ) ; return Dis -> getRegInfo ( ) -> getRegClass ( RC ) . getRegister ( RegNo ) ; } </s>

Returns the register associated with this edge .


<s> bool X86TTIImpl :: isLegalMaskedExpandLoad ( Type * DataTy ) { if ( ! isa < VectorType > ( DataTy ) ) return false ; if ( ! ST -> hasAVX512 ( ) ) return false ; if ( cast < FixedVectorType > ( DataTy ) -> getNumElements ( ) == 1 ) return false ; Type * ScalarTy = cast < VectorType > ( DataTy ) -> getElementType ( ) ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasVBMI2 ( ) ) ; } </s>

Return true if the target supports masked expand load .


<s> bool aarch64_simd_check_vect_par_cnst_half ( rtx op , machine_mode mode , bool high ) { int nelts ; if ( ! VECTOR_MODE_P ( mode ) || ! GET_MODE_NUNITS ( mode ) . is_constant ( & nelts ) ) return false ; rtx ideal = aarch64_simd_vect_par_cnst_half ( mode , nelts , high ) ; HOST_WIDE_INT count_op = XVECLEN ( op , 0 ) ; HOST_WIDE_INT count_ideal = XVECLEN ( ideal , 0 ) ; int i = 0 ; if ( count_op != count_ideal ) return false ; for ( i = 0 ; i < count_ideal ; i ++ ) { rtx elt_op = XVECEXP ( op , 0 , i ) ; rtx elt_ideal = XVECEXP ( ideal , 0 , i ) ; if ( ! CONST_INT_P ( elt_op ) || INTVAL ( elt_ideal ) != INTVAL ( elt_op ) ) return false ; } return true ; } </s>

Check OP for validity as a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low lanes , from the perspective of the architecture . See the diagram above aarch64_simd_vect_par_cnst_half for more details .


<s>
SDValue
MipsTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
,
TargetLowering
::
CallLoweringInfo
&
CLI
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MipsCCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Mips
,
CLI
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
RVLocs
[
i
]
.
getLocReg
(
)
,
RVLocs
[
i
]
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
if
(
VA
.
isUpperBitsInLoc
(
)
)
{
unsigned
ValSizeInBits
=
Ins
[
i
]
.
ArgVT
.
getSizeInBits
(
)
;
unsigned
LocSizeInBits
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
unsigned
Shift
=
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExtUpper
ISD
::
SRL
:
ISD
::
SRA
;
Val
=
DAG
.
getNode
(
Shift
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getConstant
(
LocSizeInBits
ValSizeInBits
,
VA
.
getLocVT
(
)
)
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
AExt
:
case
CCValAssign
::
AExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
case
CCValAssign
::
ZExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
case
CCValAssign
::
SExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

Mips
Mips
ISD::InputArg
16
Mips
Mips
0
"Can only return in registers!"
1
2
ISD::SRL
ISD::SRA
"Unknown loc info!"
ISD::BITCAST
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> static bool aarch64_evpc_reencode ( struct expand_vec_perm_d * d ) { expand_vec_perm_d newd ; unsigned HOST_WIDE_INT nelt ; if ( d -> vec_flags != VEC_ADVSIMD ) return false ; poly_uint64 vec_bits = GET_MODE_BITSIZE ( d -> vmode ) ; unsigned int new_elt_bits = GET_MODE_UNIT_BITSIZE ( d -> vmode ) * 2 ; auto new_elt_mode = int_mode_for_size ( new_elt_bits , false ) . require ( ) ; machine_mode new_mode = aarch64_simd_container_mode ( new_elt_mode , vec_bits ) ; if ( new_mode == word_mode ) return false ; nelt = d -> perm . length ( ) . to_constant ( ) ; vec_perm_builder newpermconst ; newpermconst . new_vector ( nelt / 2 , nelt / 2 , 1 ) ; for ( unsigned int i = 0 ; i < nelt ; i += 2 ) { poly_int64 elt0 = d -> perm [ i ] ; poly_int64 elt1 = d -> perm [ i + 1 ] ; poly_int64 newelt ; if ( ! multiple_p ( elt0 , 2 , & newelt ) || maybe_ne ( elt0 + 1 , elt1 ) ) return false ; newpermconst . quick_push ( newelt . to_constant ( ) ) ; } newpermconst . finalize ( ) ; newd . vmode = new_mode ; newd . vec_flags = VEC_ADVSIMD ; newd . target = d -> target ? gen_lowpart ( new_mode , d -> target ) : NULL ; newd . op0 = d -> op0 ? gen_lowpart ( new_mode , d -> op0 ) : NULL ; newd . op1 = d -> op1 ? gen_lowpart ( new_mode , d -> op1 ) : NULL ; newd . testing_p = d -> testing_p ; newd . one_vector_p = d -> one_vector_p ; newd . perm . new_vector ( newpermconst , newd . one_vector_p ? 1 : 2 , nelt / 2 ) ; return aarch64_expand_vec_perm_const_1 ( & newd ) ; } </s>

Try to re-encode the PERM constant so it combines odd and even elements . This rewrites constants such as { 0 , 1 , 4 , 5 } /V4SF to { 0 , 2 } /V2DI . We retry with this new constant with the full suite of patterns .


<s> int sh_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( sh_cfun_interrupt_handler_p ( ) && ! regs_ever_live [ new_reg ] ) return 0 ; return 1 ; } </s>

Return nonzero if register old_reg can be renamed to register new_reg .


<s> void rs6000_xcoff_declare_object_name ( FILE * file , const char * name , tree decl ) { struct declare_alias_data data = { file , false } ; RS6000_OUTPUT_BASENAME ( file , name ) ; fputs ( ":\n" , file ) ; symtab_node :: get_create ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; } </s>

This macro produces the initial definition of a object ( variable ) name . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static Mfix * create_fix_barrier ( Mfix * fix , HOST_WIDE_INT max_address ) { HOST_WIDE_INT count = 0 ; rtx barrier ; rtx from = fix -> insn ; rtx selected = from ; int selected_cost ; HOST_WIDE_INT selected_address ; Mfix * new_fix ; HOST_WIDE_INT max_count = max_address - fix -> address ; rtx label = gen_label_rtx ( ) ; selected_cost = arm_barrier_cost ( from ) ; selected_address = fix -> address ; while ( from && count < max_count ) { rtx tmp ; int new_cost ; gcc_assert ( GET_CODE ( from ) != BARRIER ) ; count += get_attr_length ( from ) ; tmp = is_jump_table ( from ) ; if ( tmp != NULL ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ; fix -> next = new_fix ; return new_fix ; } </s>

Find the best place in the insn stream in the range ( FIX- > address , MAX_ADDRESS ) to forcibly insert a minipool barrier . Create the barrier by inserting a jump and add a new fix entry for it .


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> unsigned getNumFixupKinds ( ) const { return 2 ; } </s>

Get the number of target specific fixup kinds .


"AArch64 FastISel doesn't support types larger than i64"

This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the given getelementptr index value .


<s>
static
bool
arm_rtx_costs
(
rtx
x
,
int
code
,
int
outer_code
,
int
opno
ATTRIBUTE_UNUSED
,
int
*
total
,
bool
speed
)
{
bool
result
;
if
(
TARGET_OLD_RTX_COSTS
||
(
!
current_tune
->
insn_extra_cost
&&
!
TARGET_NEW_GENERIC_COSTS
)
)
{
if
(
!
speed
)
result
=
arm_size_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
total
)
;
else
result
=
current_tune
->
rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
total
,
speed
)
;
}
else
{
if
(
current_tune
->
insn_extra_cost
)
result
=
arm_new_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
current_tune
->
insn_extra_cost
,
total
,
speed
)
;
else
result
=
arm_new_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
&
generic_extra_costs
,
total
,
speed
)
;
}
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
total
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

arm
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
0
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s>
const
char
*
output_v8plus_mult
(
rtx_insn
*
insn
,
rtx
*
operands
,
const
char
*
opcode
)
{
char
mulstr
[
32
]
;
gcc_assert
(
!
TARGET_ARCH64
)
;
if
(
sparc_check_64
(
operands
[
1
]
,
insn
)
<=
0
)
output_asm_insn
(
"srl\t%L1, 0, %L1"
,
operands
)
;
if
(
which_alternative
==
1
)
output_asm_insn
(
"sllx\t%H1, 32, %H1"
,
operands
)
;
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
)
{
if
(
which_alternative
==
1
)
{
output_asm_insn
(
"or\t%L1, %H1, %H1"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%H1, %%2, %%L0"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
return
"srlx\t%L0, 32, %H0"
;
}
else
{
output_asm_insn
(
"sllx\t%H1, 32, %3"
,
operands
)
;
output_asm_insn
(
"or\t%L1, %3, %3"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%3, %%2, %%3"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
output_asm_insn
(
"srlx\t%3, 32, %H0"
,
operands
)
;
return
"mov\t%3, %L0"
;
}
}
else
if
(
rtx_equal_p
(
operands
[
1
]
,
operands
[
2
]
)
)
{
if
(
which_alternative
==
1
)
{
output_asm_insn
(
"or\t%L1, %H1, %H1"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%H1, %%H1, %%L0"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
return
"srlx\t%L0, 32, %H0"
;
}
else
{
output_asm_insn
(
"sllx\t%H1, 32, %3"
,
operands
)
;
output_asm_insn
(
"or\t%L1, %3, %3"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%3, %%3, %%3"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
output_asm_insn
(
"srlx\t%3, 32, %H0"
,
operands
)
;
return
"mov\t%3, %L0"
;
}
}
if
(
sparc_check_64
(
operands
[
2
]
,
insn
)
<=
0
)
output_asm_insn
(
"srl\t%L2, 0, %L2"
,
operands
)
;
if
(
which_alternative
==
1
)
{
output_asm_insn
(
"or\t%L1, %H1, %H1"
,
operands
)
;
output_asm_insn
(
"sllx\t%H2, 32, %L1"
,
operands
)
;
output_asm_insn
(
"or\t%L2, %L1, %L1"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%H1, %%L1, %%L0"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
return
"srlx\t%L0, 32, %H0"
;
}
else
{
output_asm_insn
(
"sllx\t%H1, 32, %3"
,
operands
)
;
output_asm_insn
(
"sllx\t%H2, 32, %4"
,
operands
)
;
output_asm_insn
(
"or\t%L1, %3, %3"
,
operands
)
;
output_asm_insn
(
"or\t%L2, %4, %4"
,
operands
)
;
sprintf
(
mulstr
,
"%s\t%%3, %%4, %%3"
,
opcode
)
;
output_asm_insn
(
mulstr
,
operands
)
;
output_asm_insn
(
"srlx\t%3, 32, %H0"
,
operands
)
;
return
"mov\t%3, %L0"
;
}
}
</s>

Output a wide multiply instruction in V8+ mode . INSN is the instruction , OPERANDS are its operands and OPCODE is the mnemonic to be used .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: X86_FastCall ) ; F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> void LC2200AsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> SDValue DLXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"code model %qs not supported in ilp32 mode"

A checking mechanism for the implementation of the various code models .


<s> static int arm_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int cost , unsigned int ) { rtx i_pat , d_pat ; if ( TARGET_THUMB1 && dep_type == 0 && recog_memoized ( insn ) == CODE_FOR_cbranchsi4_insn && recog_memoized ( dep ) >= 0 && get_attr_conds ( dep ) == CONDS_SET ) return 0 ; if ( current_tune -> sched_adjust_cost != NULL ) { if ( ! current_tune -> sched_adjust_cost ( insn , dep_type , dep , & cost ) ) return cost ; } if ( dep_type == REG_DEP_ANTI || dep_type == REG_DEP_OUTPUT ) return 0 ; if ( dep_type == 0 && CALL_P ( insn ) ) return 1 ; if ( ( i_pat = single_set ( insn ) ) != NULL && MEM_P ( SET_SRC ( i_pat ) ) && ( d_pat = single_set ( dep ) ) != NULL && MEM_P ( SET_DEST ( d_pat ) ) ) { rtx src_mem = XEXP ( SET_SRC ( i_pat ) , 0 ) ; if ( ( SYMBOL_REF_P ( src_mem ) && CONSTANT_POOL_ADDRESS_P ( src_mem ) ) || reg_mentioned_p ( stack_pointer_rtx , src_mem ) || reg_mentioned_p ( frame_pointer_rtx , src_mem ) || reg_mentioned_p ( hard_frame_pointer_rtx , src_mem ) ) return 1 ; } return cost ; } </s>

This function implements the target macro TARGET_SCHED_ADJUST_COST . It corrects the value of COST based on the relationship between INSN and DEP through the dependence LINK . It returns the new value . There is a per-core adjust_cost hook to adjust scheduler costs and the per-core hook can choose to completely override the generic adjust_cost function . Only put bits of code into arm_adjust_cost that are common across all cores .


"-mno-power9-vector turns off -mpower9-dform"

If the user used -mno-vsx , we need turn off all of the implicit ISA 2.06 , 2.07 , and 3.0 options that relate to the vector unit ( -mdirect-move , -mupper-regs-df , etc. ) . If the user used -mno-power8-vector , we need to turn off all of the implicit ISA 2.07 and 3.0 options that relate to the vector unit . If the user used -mno-power9-vector , we need to turn off all of the implicit ISA 3.0 options that relate to the vector unit . This function does not handle explicit options such as the user specifying -mdirect-move . These are handled in rs6000_option_override_internal , and the appropriate error is given if needed . We return a mask of all of the implicit options that should not be enabled by default .


<s> rtx sfunc_uses_reg ( rtx insn ) { int i ; rtx pattern , part , reg_part , reg ; if ( GET_CODE ( insn ) != INSN ) return 0 ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return 0 ; for ( reg_part = 0 , i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return 0 ; reg = XEXP ( reg_part , 0 ) ; for ( i = XVECLEN ( pattern , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( part == reg_part || GET_CODE ( part ) == CLOBBER ) continue ; if ( reg_mentioned_p ( reg , ( ( GET_CODE ( part ) == SET && GET_CODE ( SET_DEST ( part ) ) == REG ) ? SET_SRC ( part ) : part ) ) ) return 0 ; } return reg ; } </s>

If the instruction INSN is implemented by a special function , and we can positively find the register that is used to call the sfunc , and this register is not used anywhere else in this instruction - except as the destination of a set , return this register ; else , return 0 .


<s>
void
AArch64TargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
if
(
Constraint
.
size
(
)
!=
1
)
return
;
switch
(
Constraint
[
0
]
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'Z'
:
{
ConstantSDNode
*
C
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
C
)
return
;
uint64_t
CVal
=
C
->
getZExtValue
(
)
;
uint32_t
Bits
;
switch
(
Constraint
[
0
]
)
{
default
:
llvm_unreachable
(
"Unimplemented C_Other constraint"
)
;
case
'I'
:
if
(
CVal
<=
0xfff
)
break
;
return
;
case
'K'
:
if
(
A64Imms
::
isLogicalImm
(
32
,
CVal
,
Bits
)
)
break
;
return
;
case
'L'
:
if
(
A64Imms
::
isLogicalImm
(
64
,
CVal
,
Bits
)
)
break
;
return
;
case
'Z'
:
if
(
CVal
==
0
)
break
;
return
;
}
Result
=
DAG
.
getTargetConstant
(
CVal
,
Op
.
getValueType
(
)
)
;
break
;
}
case
'S'
:
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
Op
.
getDebugLoc
(
)
,
GA
->
getValueType
(
0
)
)
;
}
else
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
BA
->
getValueType
(
0
)
)
;
}
else
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
)
;
}
else
return
;
break
;
}
case
'Y'
:
if
(
const
ConstantFPSDNode
*
CFP
=
dyn_cast
<
ConstantFPSDNode
>
(
Op
)
)
{
if
(
CFP
->
isExactlyValue
(
0.0
)
)
{
Result
=
DAG
.
getTargetConstantFP
(
0.0
,
CFP
->
getValueType
(
0
)
)
;
break
;
}
}
return
;
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> void load_got_register ( void ) { if ( ! got_register_rtx ) got_register_rtx = gen_rtx_REG ( Pmode , GLOBAL_OFFSET_TABLE_REGNUM ) ; if ( TARGET_VXWORKS_RTP ) emit_insn ( gen_vxworks_load_got ( ) ) ; else { if ( ! got_helper_rtx ) { char name [ 32 ] ; get_pc_thunk_name ( name , GLOBAL_OFFSET_TABLE_REGNUM ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; } emit_insn ( gen_load_pcrel_sym ( got_register_rtx , sparc_got ( ) , got_helper_rtx ) ) ; } } </s>


<s> static void fixup_mova ( rtx mova ) { if ( ! flag_pic ) { SET_SRC ( PATTERN ( mova ) ) = XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , 0 , 0 ) ; INSN_CODE ( mova ) = - 1 ; } else { rtx worker = mova ; rtx lab = gen_label_rtx ( ) ; rtx wpat , wpat0 , wpat1 , wsrc , diff ; do { worker = NEXT_INSN ( worker ) ; gcc_assert ( worker && GET_CODE ( worker ) != CODE_LABEL && GET_CODE ( worker ) != JUMP_INSN ) ; } while ( GET_CODE ( worker ) == NOTE || recog_memoized ( worker ) != CODE_FOR_casesi_worker_1 ) ; wpat = PATTERN ( worker ) ; wpat0 = XVECEXP ( wpat , 0 , 0 ) ; wpat1 = XVECEXP ( wpat , 0 , 1 ) ; wsrc = SET_SRC ( wpat0 ) ; PATTERN ( worker ) = ( gen_casesi_worker_2 ( SET_DEST ( wpat0 ) , XVECEXP ( wsrc , 0 , 1 ) , XEXP ( XVECEXP ( wsrc , 0 , 2 ) , 0 ) , lab , XEXP ( wpat1 , 0 ) ) ) ; INSN_CODE ( worker ) = - 1 ; diff = gen_rtx_MINUS ( Pmode , XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , 0 , 0 ) , gen_rtx_LABEL_REF ( Pmode , lab ) ) ; diff = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , diff ) , UNSPEC_PIC ) ; SET_SRC ( PATTERN ( mova ) ) = gen_rtx_CONST ( Pmode , diff ) ; INSN_CODE ( mova ) = - 1 ; } } </s>

Fix up a mova from a switch that went out of range .


"passing %qT to argument %d of %qE, which"

Like infer_vector_type , but also require the type to be integral .


<s> bool enablePostRAScheduler ( ) const override { return isGeneric ( ) || isCortexA53 ( ) || isCortexA57 ( ) || isKryo ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> int64_t getBytes ( ) const { return Bytes ; } </s>

Extract a fixed number of bytes from the location given by the cursor .


<s> MCContext & getContext ( ) { return getStreamer ( ) . getContext ( ) ; } </s>

Return the LLVMContext used by the analysis .


<s> const SparcSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
void
AArch64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
AArch64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
STI
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
AArch64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
const
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
STI
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
AArch64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
AArch64InstPrinter
::
printInst
(
MI
,
Address
,
Annot
,
STI
,
O
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
llvm_report_error
(
"SSE register return with SSE disabled"
)
;
}
if
(
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
}
SDValue
Val
;
if
(
Is64Bit
&&
CopyVT
.
isVector
(
)
&&
CopyVT
.
getSizeInBits
(
)
==
64
)
{
if
(
VA
.
getLocReg
(
)
==
X86
::
XMM0
||
VA
.
getLocReg
(
)
==
X86
::
XMM1
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
v2i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
Val
=
DAG
.
getNode
(
ISD
::
EXTRACT_VECTOR_ELT
,
dl
,
MVT
::
i64
,
Val
,
DAG
.
getConstant
(
0
,
MVT
::
i64
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
Val
=
DAG
.
getNode
(
ISD
::
BIT_CONVERT
,
dl
,
CopyVT
,
Val
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
{
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool arm_cirrus_insn_p ( rtx insn ) { enum attr_cirrus attr ; if ( ! insn || GET_CODE ( insn ) != INSN || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return 0 ; attr = get_attr_cirrus ( insn ) ; return attr != CIRRUS_NOT ; } </s>

Return TRUE if INSN is a Cirrus instruction .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , Address , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; } </s>


<s> bool function_expander :: overlaps_input_p ( rtx x ) { for ( unsigned int i = 0 ; i < args . length ( ) ; ++ i ) if ( reg_overlap_mentioned_p ( x , args [ i ] ) ) return true ; return false ; } </s>


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; if ( arm_current_function_pac_enabled_p ( ) ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_or_fixed_reg_p ( 3 ) ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( IS_CMSE_ENTRY ( func_type ) && ( saved_int_regs || TARGET_HAVE_FPCXT_CMSE ) ) return 0 ; if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_VFP_BASE ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( reg_needs_saving_p ( regno ) ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( reg_needs_saving_p ( regno ) ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> bool AArch64IndirectThunks :: doInitialization ( Module & M ) { initTIs ( M , TIs ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return ABI . IsCheriPureCap ( ) ? Mips :: C16 : ( ABI . IsN64 ( ) ? Mips :: A0_64 : Mips :: A0 ) ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> static void pa_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx end_addr = gen_reg_rtx ( Pmode ) ; rtx line_length = gen_reg_rtx ( Pmode ) ; rtx r_tramp , tmp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; r_tramp = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; if ( ! TARGET_64BIT ) { tmp = adjust_address ( m_tramp , Pmode , 48 ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , 52 ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , 56 ) ; emit_move_insn ( tmp , r_tramp ) ; tmp = adjust_address ( m_tramp , Pmode , 60 ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , 19 ) ) ; emit_insn ( gen_andsi3 ( start_addr , r_tramp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , TRAMPOLINE_CODE_SIZE - 1 ) ) ; emit_insn ( gen_andsi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushsi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushsi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } else { tmp = adjust_address ( m_tramp , Pmode , 56 ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , 64 ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , 16 ) ; emit_move_insn ( tmp , force_reg ( Pmode , plus_constant ( Pmode , r_tramp , 32 ) ) ) ; tmp = adjust_address ( m_tramp , Pmode , 24 ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , 27 ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , 32 ) ) ; emit_insn ( gen_anddi3 ( start_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , tmp , TRAMPOLINE_CODE_SIZE - 1 ) ) ; emit_insn ( gen_anddi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushdi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushdi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . Move the function address to the trampoline template at offset 36 . Move the static chain value to trampoline template at offset 40 . Move the trampoline address to trampoline template at offset 44 . Move r19 to trampoline template at offset 48 . The latter two words create a plabel for the indirect call to the trampoline . A similar sequence is used for the 64-bit port but the plabel is at the beginning of the trampoline . Finally , the cache entries for the trampoline code are flushed . This is necessary to ensure that the trampoline instruction sequence is written to memory prior to any attempts at prefetching the code sequence .


<s> static rtx get_vector_offset ( rtx mem , rtx element , rtx base_tmp , unsigned scalar_size ) { if ( CONST_INT_P ( element ) ) return GEN_INT ( INTVAL ( element ) * scalar_size ) ; gcc_assert ( satisfies_constraint_Q ( mem ) ) ; rtx num_ele_m1 = GEN_INT ( GET_MODE_NUNITS ( GET_MODE ( mem ) ) - 1 ) ; rtx and_op = gen_rtx_AND ( Pmode , element , num_ele_m1 ) ; emit_insn ( gen_rtx_SET ( base_tmp , and_op ) ) ; int shift = exact_log2 ( scalar_size ) ; gcc_assert ( shift >= 0 ) ; if ( shift > 0 ) { rtx shift_op = gen_rtx_ASHIFT ( Pmode , base_tmp , GEN_INT ( shift ) ) ; emit_insn ( gen_rtx_SET ( base_tmp , shift_op ) ) ; } return base_tmp ; } </s>

Return the offset within a memory object ( MEM ) of a vector type to a given element within the vector ( ELEMENT ) with an element size ( SCALAR_SIZE ) . If the element is constant , we return a constant integer . Otherwise , we use a base register temporary to calculate the offset after masking it to fit within the bounds of the vector and scaling it . The masking is required by the 64-bit ELF version 2 ABI for the vec_extract built-in function .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerFormalArguments_SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool isMem ( RegisterKind RegKind , MemoryKind MemKind ) const { return ( Kind == KindMem && Mem . RegKind == RegKind && ( MemKind == BDXMem || ! Mem . Index ) && ( MemKind == BDLMem ) == ( Mem . Length != 0 ) ) ; } </s>


<s> static unsigned long arm_isr_value ( tree argument ) { const isr_attribute_arg * ptr ; const char * arg ; if ( argument == NULL_TREE ) return ARM_FT_ISR ; if ( TREE_VALUE ( argument ) == NULL_TREE || TREE_CODE ( TREE_VALUE ( argument ) ) != STRING_CST ) return ARM_FT_UNKNOWN ; arg = TREE_STRING_POINTER ( TREE_VALUE ( argument ) ) ; for ( ptr = isr_attribute_args ; ptr -> arg != NULL ; ptr ++ ) if ( streq ( arg , ptr -> arg ) ) return ptr -> return_value ; return ARM_FT_UNKNOWN ; } </s>

Returns the ( interrupt ) function type of the current function , or ARM_FT_UNKNOWN if the type can not be determined .


<s> TargetTransformInfo AArch64TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( AArch64TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool aarch64_offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , poly_int64 offset ) { HOST_WIDE_INT const_offset ; return ( offset . is_constant ( & const_offset ) && IN_RANGE ( const_offset , - 256 , 255 ) ) ; } </s>

Return true if OFFSET is a signed 9-bit value .


<s> unsigned X86InstrInfo :: getFMA3OpcodeToCommuteOperands ( const MachineInstr & MI , unsigned SrcOpIdx1 , unsigned SrcOpIdx2 , const X86InstrFMA3Group & FMA3Group ) const { unsigned Opc = MI . getOpcode ( ) ; if ( SrcOpIdx1 > SrcOpIdx2 ) std :: swap ( SrcOpIdx1 , SrcOpIdx2 ) ; if ( FMA3Group . isIntrinsic ( ) && SrcOpIdx1 == 1 ) return 0 ; int Case = getThreeSrcCommuteCase ( MI . getDesc ( ) . TSFlags , SrcOpIdx1 , SrcOpIdx2 ) ; if ( Case < 0 ) return 0 ; const unsigned Form132Index = 0 ; const unsigned Form213Index = 1 ; const unsigned Form231Index = 2 ; static const unsigned FormMapping [ ] [ 3 ] = { { Form231Index , Form213Index , Form132Index } , { Form132Index , Form231Index , Form213Index } , { Form213Index , Form132Index , Form231Index } } ; unsigned FMAForms [ 3 ] ; if ( FMA3Group . isRegOpcodeFromGroup ( Opc ) ) { FMAForms [ 0 ] = FMA3Group . getReg132Opcode ( ) ; FMAForms [ 1 ] = FMA3Group . getReg213Opcode ( ) ; FMAForms [ 2 ] = FMA3Group . getReg231Opcode ( ) ; } else { FMAForms [ 0 ] = FMA3Group . getMem132Opcode ( ) ; FMAForms [ 1 ] = FMA3Group . getMem213Opcode ( ) ; FMAForms [ 2 ] = FMA3Group . getMem231Opcode ( ) ; } unsigned FormIndex ; for ( FormIndex = 0 ; FormIndex < 3 ; FormIndex ++ ) if ( Opc == FMAForms [ FormIndex ] ) break ; FormIndex = FormMapping [ Case ] [ FormIndex ] ; return FMAForms [ FormIndex ] ; } </s>

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted .


<s>
X86TargetMachine
::
X86TargetMachine
(
const
Target
&
T
,
const
std
::
string
&
TT
,
const
std
::
string
&
FS
,
bool
is64Bit
)
:
LLVMTargetMachine
(
T
,
TT
)
,
Subtarget
(
TT
,
FS
,
is64Bit
)
,
DataLayout
(
Subtarget
.
getDataLayout
(
)
)
,
FrameInfo
(
TargetFrameInfo
::
StackGrowsDown
,
Subtarget
.
getStackAlignment
(
)
,
(
Subtarget
.
isTargetWin64
(
)
40
:
(
Subtarget
.
is64Bit
(
)
8
:
4
)
)
)
,
InstrInfo
(
*
this
)
,
JITInfo
(
*
this
)
,
TLInfo
(
*
this
)
,
ELFWriterInfo
(
*
this
)
{
DefRelocModel
=
getRelocationModel
(
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
Default
)
{
if
(
!
Subtarget
.
isTargetDarwin
(
)
)
setRelocationModel
(
Reloc
::
Static
)
;
else
if
(
Subtarget
.
is64Bit
(
)
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
setRelocationModel
(
Reloc
::
DynamicNoPIC
)
;
}
assert
(
getRelocationModel
(
)
!=
Reloc
::
Default
&&
"Relocation mode not picked"
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
{
if
(
is64Bit
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
if
(
!
Subtarget
.
isTargetDarwin
(
)
)
setRelocationModel
(
Reloc
::
Static
)
;
}
if
(
getRelocationModel
(
)
==
Reloc
::
Static
&&
Subtarget
.
isTargetDarwin
(
)
&&
is64Bit
)
setRelocationModel
(
Reloc
::
PIC_
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
Static
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
)
;
}
else
if
(
Subtarget
.
isTargetCygMing
(
)
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
)
;
}
else
if
(
Subtarget
.
isTargetDarwin
(
)
)
{
if
(
Subtarget
.
is64Bit
(
)
)
Subtarget
.
setPICStyle
(
PICStyles
::
RIPRel
)
;
else
if
(
getRelocationModel
(
)
==
Reloc
::
PIC_
)
Subtarget
.
setPICStyle
(
PICStyles
::
StubPIC
)
;
else
{
assert
(
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
;
Subtarget
.
setPICStyle
(
PICStyles
::
StubDynamicNoPIC
)
;
}
}
else
if
(
Subtarget
.
isTargetELF
(
)
)
{
if
(
Subtarget
.
is64Bit
(
)
)
Subtarget
.
setPICStyle
(
PICStyles
::
RIPRel
)
;
else
Subtarget
.
setPICStyle
(
PICStyles
::
GOT
)
;
}
if
(
Subtarget
.
getPICStyle
(
)
==
PICStyles
::
)
setRelocationModel
(
Reloc
::
Static
)
;
}
</s>


<s> static rtx sparc_struct_value_rtx ( tree fndecl , int incoming ) { if ( TARGET_ARCH64 ) return 0 ; else { rtx mem ; if ( incoming ) mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; if ( incoming == 2 && sparc_std_struct_return && TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) && TREE_CODE ( TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ) == INTEGER_CST ) { rtx ret_reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx scratch = gen_reg_rtx ( SImode ) ; rtx_code_label * endlab = gen_label_rtx ( ) ; tree size = TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ; rtx size_rtx = GEN_INT ( TREE_INT_CST_LOW ( size ) & 0xfff ) ; rtx temp_val = assign_stack_local ( Pmode , TREE_INT_CST_LOW ( size ) , 0 ) ; emit_move_insn ( scratch , gen_rtx_MEM ( SImode , plus_constant ( Pmode , ret_reg , 8 ) ) ) ; emit_insn ( gen_add3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_cmp_and_jump_insns ( scratch , size_rtx , EQ , const0_rtx , SImode , 0 , endlab ) ; emit_insn ( gen_sub3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_move_insn ( mem , XEXP ( temp_val , 0 ) ) ; emit_label ( endlab ) ; } return mem ; } } </s>

Handle the TARGET_STRUCT_VALUE target hook . Return where to find the structure return value address .


<s> static void rs6000_function_specific_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_rs6000_isa_flags = opts -> x_rs6000_isa_flags ; ptr -> x_rs6000_isa_flags_explicit = opts -> x_rs6000_isa_flags_explicit ; } </s>


<s> static void mips_emit_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 , bool need_eq_ne_p ) { rtx cmp_op0 = * op0 ; rtx cmp_op1 = * op1 ; if ( GET_MODE_CLASS ( GET_MODE ( * op0 ) ) == MODE_INT ) { if ( ! need_eq_ne_p && * op1 == const0_rtx ) ; else if ( * code == EQ || * code == NE ) { if ( need_eq_ne_p ) { * op0 = mips_zero_if_equal ( cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; } else * op1 = force_reg ( GET_MODE ( cmp_op0 ) , cmp_op1 ) ; } else { bool invert = false ; * op0 = gen_reg_rtx ( GET_MODE ( cmp_op0 ) ) ; mips_emit_int_order_test ( * code , & invert , * op0 , cmp_op0 , cmp_op1 ) ; * code = ( invert ? EQ : NE ) ; * op1 = const0_rtx ; } } else if ( ALL_FIXED_POINT_MODE_P ( GET_MODE ( cmp_op0 ) ) ) { * op0 = gen_rtx_REG ( CCDSPmode , CCDSP_CC_REGNUM ) ; mips_emit_binary ( * code , * op0 , cmp_op0 , cmp_op1 ) ; * code = NE ; * op1 = const0_rtx ; } else { enum rtx_code cmp_code ; cmp_code = * code ; if ( ISA_HAS_CCF ) { * code = NE ; * op0 = gen_reg_rtx ( CCFmode ) ; } else { * code = mips_reversed_fp_cond ( & cmp_code ) ? EQ : NE ; if ( ISA_HAS_8CC ) * op0 = mips_allocate_fcc ( CCmode ) ; else * op0 = gen_rtx_REG ( CCmode , FPSW_REGNUM ) ; } * op1 = const0_rtx ; mips_emit_binary ( cmp_code , * op0 , cmp_op0 , cmp_op1 ) ; } } </s>

Convert a comparison into something that can be used in a branch or conditional move . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update * CODE , * OP0 and * OP1 so that they describe the final comparison . If NEED_EQ_NE_P , then only EQ or NE comparisons against zero are possible , otherwise any standard branch condition can be used . The standard branch conditions are : - EQ or NE between two registers . - any comparison between a register and zero .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < ReachingDefAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new ARMFrameLowering ( * this ) : ( ARMFrameLowering * ) new Thumb1FrameLowering ( * this ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM ARM ARM


<s> int crx_const_double_ok ( rtx op ) { if ( GET_MODE ( op ) == DFmode ) { REAL_VALUE_TYPE r ; long l [ 2 ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_DOUBLE ( r , l ) ; return ( UNSIGNED_INT_FITS_N_BITS ( l [ 0 ] , 4 ) && UNSIGNED_INT_FITS_N_BITS ( l [ 1 ] , 4 ) ) ? 1 : 0 ; } if ( GET_MODE ( op ) == SFmode ) { REAL_VALUE_TYPE r ; long l ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , l ) ; return UNSIGNED_INT_FITS_N_BITS ( l , 4 ) ? 1 : 0 ; } return ( UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_LOW ( op ) , 4 ) && UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_HIGH ( op ) , 4 ) ) ? 1 : 0 ; } </s>

Check if a const_double is ok for crx store-immediate instructions


"getBranchTargetOpValueMM expects only expressions or immediates"

getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand .


<s> static void ix86_emit_restore_regs_using_pop ( void ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , false , true ) ) ix86_emit_restore_reg_using_pop ( gen_rtx_REG ( word_mode , regno ) ) ; } </s>

Emit code to restore saved registers using POP insns .


<s> void AArch64TTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , UP ) ; if ( L -> getLoopDepth ( ) > 1 ) UP . PartialThreshold *= 2 ; UP . PartialOptSizeThreshold = 0 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> int mips_class_max_nregs ( enum reg_class class ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( class == ST_REGS ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; else return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Implement CLASS_MAX_NREGS . Usually all registers are word-sized . The only supported exception is -mgp64 -msingle-float , which has 64-bit words but 32-bit float registers . A word-based calculation is correct even in that case , since -msingle-float disallows multi-FPR values . The FP status registers are an exception to this rule . They are always 4 bytes wide as they only hold condition code modes , and CCmode is always considered to be 4 bytes wide .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
enum
calling_abi
ix86_function_type_abi
(
const_tree
fntype
)
{
enum
calling_abi
abi
=
ix86_abi
;
if
(
fntype
==
NULL_TREE
||
TYPE_ATTRIBUTES
(
fntype
)
==
NULL_TREE
)
return
abi
;
if
(
abi
==
SYSV_ABI
&&
lookup_attribute
(
"ms_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
{
static
int
warned
;
if
(
TARGET_X32
&&
!
warned
)
{
error
(
"X32 does not support ms_abi attribute"
)
;
warned
=
1
;
}
abi
=
MS_ABI
;
}
else
if
(
abi
==
MS_ABI
&&
lookup_attribute
(
"sysv_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
abi
=
SYSV_ABI
;
return
abi
;
}
</s>

Returns value SYSV_ABI , MS_ABI dependent on fntype , specifying the call abi used .


<s>
void
dump
(
SelectionDAG
*
DAG
=
nullptr
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
DAG
)
;
else
dbgs
(
)
<<
"nul\n"
;
if
(
BaseType
==
FrameIndexBase
)
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
;
dbgs
(
)
<<
" Scale "
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
DAG
)
;
else
dbgs
(
)
<<
"nul\n"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" MCSym "
;
if
(
MCSym
)
dbgs
(
)
<<
MCSym
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul\n"
" Base.FrameIndex "
" Scale "
"IndexReg "
"nul\n"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" MCSym "
"nul"
" JT"
" Align"


<s> bool MipsPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static bool aarch64_evpc_trn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn2v16qi ; break ; case V8QImode : gen = gen_aarch64_trn2v8qi ; break ; case V8HImode : gen = gen_aarch64_trn2v8hi ; break ; case V4HImode : gen = gen_aarch64_trn2v4hi ; break ; case V4SImode : gen = gen_aarch64_trn2v4si ; break ; case V2SImode : gen = gen_aarch64_trn2v2si ; break ; case V2DImode : gen = gen_aarch64_trn2v2di ; break ; case V4SFmode : gen = gen_aarch64_trn2v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn2v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn1v16qi ; break ; case V8QImode : gen = gen_aarch64_trn1v8qi ; break ; case V8HImode : gen = gen_aarch64_trn1v8hi ; break ; case V4HImode : gen = gen_aarch64_trn1v4hi ; break ; case V4SImode : gen = gen_aarch64_trn1v4si ; break ; case V2SImode : gen = gen_aarch64_trn1v2si ; break ; case V2DImode : gen = gen_aarch64_trn1v2di ; break ; case V4SFmode : gen = gen_aarch64_trn1v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn1v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the TRN instructions .


<s> bool PPCTargetLowering :: SelectAddressRegRegOnly ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { if ( SelectAddressRegReg ( N , Base , Index , DAG ) ) return true ; if ( N . getOpcode ( ) == ISD :: ADD ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } Base = DAG . getRegister ( PPC :: R0 , N . getValueType ( ) ) ; Index = N ; return true ; } </s>

SelectAddressRegRegOnly - Given the specified addressed , force it to be represented as an indexed [ r+r ] operation .


<s> void X86AsmPrinter :: emitEndOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { emitNonLazyStubs ( MMI , * OutStreamer ) ; emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } else if ( TT . isOSBinFormatCOFF ( ) ) { if ( MMI -> usesMSVCFloatingPoint ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86 ) ? "__fltused" : "_fltused" ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; return ; } emitStackMaps ( SM ) ; } else if ( TT . isOSBinFormatELF ( ) ) { emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } if ( TT . getArch ( ) == Triple :: x86_64 && TM . getCodeModel ( ) == CodeModel :: Large ) { if ( MCSymbol * AddrSymbol = OutContext . lookupSymbol ( "__morestack_addr" ) ) { Align Alignment ( 1 ) ; MCSection * ReadOnlySection = getObjFileLowering ( ) . getSectionForConstant ( getDataLayout ( ) , SectionKind :: getReadOnly ( ) , nullptr , Alignment ) ; OutStreamer -> SwitchSection ( ReadOnlySection ) ; OutStreamer -> emitLabel ( AddrSymbol ) ; unsigned PtrSize = MAI -> getCodePointerSize ( ) ; OutStreamer -> emitSymbolValue ( GetExternalSymbolSymbol ( "__morestack" ) , PtrSize ) ; } } } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> unsigned ARMTargetLowering :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( Subtarget -> isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void PPCScoreboardHazardRecognizer :: AdvanceCycle ( ) { ScoreboardHazardRecognizer :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> TargetLowering :: ConstraintWeight Cpu0TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'c' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
void
mmix_output_register_setting
(
FILE
*
stream
,
int
regno
,
int64_t
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\t"
)
;
if
(
insn_const_int_ok_for_constraint
(
value
,
CONSTRAINT_K
)
)
fprintf
(
stream
,
"NEGU %s,0,%"
PRId64
,
reg_names
[
regno
]
,
value
)
;
else
if
(
mmix_shiftable_wyde_value
(
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
uint64_t
)
value
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
"\n\tNEGU %s,0,%s"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
~
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
~
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
~
(
uint64_t
)
value
)
;
fprintf
(
stream
,
"\n\tNOR %s,%s,0"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
{
static
const
char
*
const
higher_parts
[
]
=
{
"L"
,
"ML"
,
"MH"
,
"H"
}
;
const
char
*
op
=
"SET"
;
const
char
*
line_begin
=
""
;
int
insns
=
0
;
int
i
;
int64_t
tmpvalue
=
value
;
for
(
i
=
0
;
i
<
4
&&
tmpvalue
!=
0
;
i
++
)
{
if
(
tmpvalue
&
65535
)
insns
++
;
tmpvalue
>>=
16
;
}
if
(
TARGET_BASE_ADDRESSES
&&
insns
==
3
)
{
fprintf
(
stream
,
"LDA %s,"
,
reg_names
[
regno
]
)
;
mmix_output_octa
(
stream
,
value
,
0
)
;
}
else
{
for
(
i
=
0
;
i
<
4
&&
value
!=
0
;
i
++
)
{
if
(
value
&
65535
)
{
fprintf
(
stream
,
"%s%s%s %s,#%x"
,
line_begin
,
op
,
higher_parts
[
i
]
,
reg_names
[
regno
]
,
(
int
)
(
value
&
65535
)
)
;
op
=
"INC"
;
line_begin
=
"\n\t"
;
}
value
>>=
16
;
}
}
}
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Output an optimal sequence for setting a register to a specific constant . Used in an alternative for const_ints in movdi , and when using large stack-frame offsets . Use do_begin_end to say if a line-starting TAB and newline before the first insn and after the last insn is wanted .


<s> int AArch64TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static bool aarch64_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_SALT_ADDR ) { output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; return true ; } return false ; } </s>


<s> static tree make_resolver_func ( const tree default_decl , const tree dispatch_decl , basic_block * empty_bb ) { tree decl_name = clone_function_name ( default_decl , "resolver" ) ; const char * resolver_name = IDENTIFIER_POINTER ( decl_name ) ; tree type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; tree decl = build_fn_decl ( resolver_name , type ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 0 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( dispatch_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; DECL_ATTRIBUTES ( dispatch_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( dispatch_decl ) ) ; cgraph_node :: create_same_body_alias ( dispatch_decl , decl ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


"PowerPC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static rtx nds32_expand_builtin_store ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ 1 ] . mode ) ; op0 = nds32_legitimize_argument ( icode , 0 , op0 ) ; op1 = nds32_legitimize_argument ( icode , 2 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , addr_helper , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( 0 ) ) ; emit_insn ( pat ) ; return target ; } </s>


<s>
bool
X86TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
assert
(
SVI
->
getType
(
)
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
SmallVector
<
unsigned
,
4
>
Indices
;
auto
Mask
=
SVI
->
getShuffleMask
(
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Indices
.
push_back
(
Mask
[
i
]
)
;
ArrayRef
<
ShuffleVectorInst
*
>
Shuffles
=
makeArrayRef
(
SVI
)
;
IRBuilder
<
>
Builder
(
SI
)
;
X86InterleavedAccessGroup
Grp
(
SI
,
Shuffles
,
Indices
,
Factor
,
Subtarget
,
Builder
)
;
return
Grp
.
isSupported
(
)
&&
Grp
.
lowerIntoOptimizedSequence
(
)
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s>
static
void
aarch64_sls_emit_function_stub
(
FILE
*
out_file
,
int
regnum
)
{
asm_fprintf
(
out_file
,
"\tmov\tx16, x%d\n"
,
regnum
)
;
asm_fprintf
(
out_file
,
"\tbr\tx16\n"
)
;
}
</s>

Helper function for aarch64_sls_emit_blr_function_thunks and aarch64_sls_emit_shared_blr_thunks below .


runOnMachineFunction - Emit the function body .


"shouldAssumeDSOLocal gave inconsistent answer"

Classify a global function reference for the current subtarget .


<s> bool FPGATTIImpl :: isTypeLegal ( Type * Ty ) { return true ; } </s>


<s> bool ARMAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a00000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write ( OS , nopEncoding , Endian ) ; if ( Count & 1 ) OS << '\0' ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write ( OS , nopEncoding , Endian ) ; switch ( Count % 4 ) { default : break ; case 1 : OS << '\0' ; break ; case 2 : OS . write ( "\0\0" , 2 ) ; break ; case 3 : OS . write ( "\0\0\xa0" , 3 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool classof ( const SDNode * N ) { return N -> getOpcode ( ) == X86ISD :: MSCATTER ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Mips
::
NumTargetFixupKinds
]
=
{
{
"fixup_Mips_16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_26"
,
0
,
26
,
0
}
,
{
"fixup_Mips_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_Global"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_Local"
,
0
,
16
,
0
}
,
{
"fixup_Mips_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Mips_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Mips_64"
,
0
,
64
,
0
}
,
{
"fixup_Mips_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Mips_DTPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_DTPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_GPOFF_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPOFF_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_PAGE"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_OFST"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool nds32_tls_referenced_p ( rtx x ) { if ( ! targetm . have_tls ) return false ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = XEXP ( XEXP ( x , 0 ) , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) ) return true ; return false ; } </s>

Return true if X contains a thread-local symbol .


<s> void SystemZInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << '%' << getRegisterName ( RegNo ) ; } </s>


<s> bool XNCMAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printSrcMemOperand ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static int rs6000_reassociation_width ( unsigned int opc ATTRIBUTE_UNUSED , machine_mode mode ) { switch ( rs6000_cpu ) { case PROCESSOR_POWER8 : case PROCESSOR_POWER9 : if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return 1 ; if ( VECTOR_MODE_P ( mode ) ) return 4 ; if ( INTEGRAL_MODE_P ( mode ) ) return opc == MULT_EXPR ? 4 : 6 ; if ( FLOAT_MODE_P ( mode ) ) return 4 ; break ; default : break ; } return 1 ; } </s>

Determine the reassociation width to be used in reassociate_bb . This takes into account how many parallel operations we can actually do of a given type , and also the latency . P8 : int add/sub 6/cycle mul 2/cycle vect add/sub/mul 2/cycle fp add/sub/mul 2/cycle dfp 1/cycle


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; this -> TM = & TM ; } </s>

This method must be called before any actual lowering is done .


<s> bool X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream ) const { InternalInstruction internalInstr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , logger , ( void * ) & vStream , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return false ; } else { size = internalInstr . length ; translateInstruction ( instr , internalInstr ) ; return true ; } } </s>

Returns the disassembly of a single instruction .


<s>
int
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
ValTy
,
bool
IsPairwiseForm
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s>
void
X86FrameLowering
::
inlineStackProbe
(
MachineFunction
&
MF
,
MachineBasicBlock
&
PrologMBB
)
const
{
const
StringRef
ChkStkStubSymbol
=
"__chkstk_stub"
;
MachineInstr
*
ChkStkStub
=
nullptr
;
for
(
MachineInstr
&
MI
:
PrologMBB
)
{
if
(
MI
.
isCall
(
)
&&
MI
.
getOperand
(
0
)
.
isSymbol
(
)
&&
ChkStkStubSymbol
==
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
)
{
ChkStkStub
=
&
MI
;
break
;
}
}
if
(
ChkStkStub
!=
nullptr
)
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
next
(
ChkStkStub
->
getIterator
(
)
)
;
assert
(
std
::
prev
(
MBBI
)
.
operator
==
(
ChkStkStub
)
&&
"MBBI expected after __chkstk_stub."
)
;
DebugLoc
DL
=
PrologMBB
.
findDebugLoc
(
MBBI
)
;
emitStackProbeInline
(
MF
,
PrologMBB
,
MBBI
,
DL
,
true
)
;
ChkStkStub
->
eraseFromParent
(
)
;
}
}
</s>

Replace a StackProbe inline-stub with the actual probe code inline .


<s> static void aarch64_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; int gr_saved , vr_saved ; local_cum = * cum ; aarch64_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; gr_saved = NUM_ARG_REGS - local_cum . aapcs_ncrn ; vr_saved = NUM_FP_ARG_REGS - local_cum . aapcs_nvrn ; if ( ! TARGET_FLOAT ) { gcc_assert ( local_cum . aapcs_nvrn == 0 ) ; vr_saved = 0 ; } if ( ! no_rtl ) { if ( gr_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > 0 ) { machine_mode mode = TImode ; int off , i ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) ; off -= vr_saved * UNITS_PER_VREG ; for ( i = local_cum . aapcs_nvrn ; i < NUM_FP_ARG_REGS ; ++ i ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; aarch64_emit_move ( mem , gen_rtx_REG ( mode , V0_REGNUM + i ) ) ; off += UNITS_PER_VREG ; } } } cfun -> machine -> frame . saved_varargs_size = ( ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) + vr_saved * UNITS_PER_VREG ) ; } </s>


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool IsN64 = Subtarget . isABI_N64 ( ) ; return TFI -> hasFP ( MF ) ? ( IsN64 ? Mips :: FP_64 : Mips :: FP ) : ( IsN64 ? Mips :: SP_64 : Mips :: SP ) ; } </s>

Mips Mips Mips::FP_64 Mips::FP Mips::SP_64 Mips::SP


<s> const TargetRegisterClass * MipsSETargetLowering :: getRepRegClassFor ( MVT VT ) const { if ( VT == MVT :: Untyped ) return Subtarget . hasDSP ( ) ? & Mips :: ACC64DSPRegClass : & Mips :: ACC64RegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .


<s> static enum aarch64_parse_opt_result aarch64_parse_arch ( const char * to_parse , const struct processor * * res , unsigned long * isa_flags , std :: string * invalid_extension ) { const char * ext ; const struct processor * arch ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( arch = all_architectures ; arch -> name != NULL ; arch ++ ) { if ( strlen ( arch -> name ) == len && strncmp ( arch -> name , to_parse , len ) == 0 ) { unsigned long isa_temp = arch -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = arch ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the architecture struct that it selects into RES and the architectural features into ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
{
++
I
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
*
MI
;
)
;
unsigned
OutReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
SmallVector
<
unsigned
,
4
>
OrigRegs
;
OrigRegs
.
push_back
(
OutReg
)
;
OrigRegs
.
push_back
(
InReg
)
;
OrigRegs
.
push_back
(
GPR3
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
->
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
->
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
->
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( ! nregs ) { if ( cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; } } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


"********** AArch64 Conditional Compares **********\n"


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasOptNone ( ) ) OptimizationGoal = 6 ; else if ( F . hasMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . hasOptSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( Align ( 2 ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>


<s> static void ix86_emit_cmove ( rtx dst , rtx src , enum rtx_code code , rtx op1 , rtx op2 ) { rtx t ; if ( TARGET_CMOVE ) { t = ix86_expand_compare ( code , op1 , op2 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dst , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dst ) , t , src , dst ) ) ) ; } else { rtx nomove = gen_label_rtx ( ) ; emit_cmp_and_jump_insns ( op1 , op2 , reverse_condition ( code ) , const0_rtx , GET_MODE ( op1 ) , 1 , nomove ) ; emit_move_insn ( dst , src ) ; emit_label ( nomove ) ; } } </s>

Emit conditional move of SRC to DST with condition OP1 CODE OP2 .


<s>
void
LC3MCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
2
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


"Relocation emission for MachO/PPC64 unimplemented."


<s> void Cpu0PassConfig :: addPreEmitPass ( ) { Cpu0TargetMachine & TM = getCpu0TargetMachine ( ) ; addPass ( createCpu0DelJmpPass ( TM ) ) ; addPass ( createCpu0DelaySlotFillerPass ( TM ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool X86InstrInfo :: analyzeBranchPredicate ( MachineBasicBlock & MBB , MachineBranchPredicate & MBP , bool AllowModify ) const { using namespace std :: placeholders ; SmallVector < MachineOperand , 4 > Cond ; SmallVector < MachineInstr * , 4 > CondBranches ; if ( AnalyzeBranchImpl ( MBB , MBP . TrueDest , MBP . FalseDest , Cond , CondBranches , AllowModify ) ) return true ; if ( Cond . size ( ) != 1 ) return true ; assert ( MBP . TrueDest && "expected!" ) ; if ( ! MBP . FalseDest ) MBP . FalseDest = MBB . getNextNode ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstr * ConditionDef = nullptr ; bool SingleUseCondition = true ; for ( auto I = std :: next ( MBB . rbegin ( ) ) , E = MBB . rend ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( X86 :: EFLAGS , TRI ) ) { ConditionDef = & * I ; break ; } if ( I -> readsRegister ( X86 :: EFLAGS , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn ( X86 :: EFLAGS ) ) SingleUseCondition = false ; } MBP . ConditionDef = ConditionDef ; MBP . SingleUseCondition = SingleUseCondition ; const unsigned TestOpcode = Subtarget . is64Bit ( ) ? X86 :: TEST64rr : X86 :: TEST32rr ; if ( ConditionDef -> getOpcode ( ) == TestOpcode && ConditionDef -> getNumOperands ( ) == 3 && ConditionDef -> getOperand ( 0 ) . isIdenticalTo ( ConditionDef -> getOperand ( 1 ) ) && ( Cond [ 0 ] . getImm ( ) == X86 :: COND_NE || Cond [ 0 ] . getImm ( ) == X86 :: COND_E ) ) { MBP . LHS = ConditionDef -> getOperand ( 0 ) ; MBP . RHS = MachineOperand :: CreateImm ( 0 ) ; MBP . Predicate = Cond [ 0 ] . getImm ( ) == X86 :: COND_NE ? MachineBranchPredicate :: PRED_NE : MachineBranchPredicate :: PRED_EQ ; return false ; } return true ; } </s>

Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> bool LanaiDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , AluOp ; switch ( ConstraintCode ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! selectAddrRr ( Op , Op0 , Op1 , AluOp ) && ! selectAddrRi ( Op , Op0 , Op1 , AluOp ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size ( ) != 0 ) add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( cfun -> machine -> split_stack_argp_used ) add_to_hard_reg_set ( & set -> set , Pmode , 12 ) ; } </s>

Add r30 to hard reg set if the prologue sets it up and it is not pic_offset_table_rtx .


<s> AArch64PLT1 * AArch64PLT :: create ( ) { AArch64PLT1 * plt1_entry = new ( std :: nothrow ) AArch64PLT1 ( * m_pSectionData ) ; if ( ! plt1_entry ) fatal ( diag :: fail_allocate_memory_plt ) ; return plt1_entry ; } </s>


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> int short_memory_operand ( rtx x , machine_mode mode ) { if ( ! memory_operand ( x , mode ) ) return 0 ; return ( GET_CODE ( XEXP ( x , 0 ) ) != PLUS ) ; } </s>

Return 1 if OP is a valid operand for a ` short ' memory reference insn .


<s> gimple * gimple_folder :: fold_to_vl_pred ( unsigned int vl ) { tree vectype = TREE_TYPE ( lhs ) ; tree element_type = TREE_TYPE ( vectype ) ; tree minus_one = build_all_ones_cst ( element_type ) ; tree zero = build_zero_cst ( element_type ) ; unsigned int element_bytes = type_suffix ( 0 ) . element_bytes ; unsigned int count = constant_lower_bound ( TYPE_VECTOR_SUBPARTS ( vectype ) ) ; gcc_assert ( vl * element_bytes <= count ) ; tree_vector_builder builder ( vectype , count , 2 ) ; for ( unsigned int i = 0 ; i < count * 2 ; ++ i ) { bool bit = ( i & ( element_bytes - 1 ) ) == 0 && i < vl * element_bytes ; builder . quick_push ( bit ? minus_one : zero ) ; } return gimple_build_assign ( lhs , builder . build ( ) ) ; } </s>

Fold an operation to a constant predicate in which the first VL elements are set and the rest are clear . Take the element size from type suffix 0 .


<s> int arm_regno_class ( int regno ) { if ( TARGET_THUMB ) { if ( regno == STACK_POINTER_REGNUM ) return STACK_REG ; if ( regno == CC_REGNUM ) return CC_REG ; if ( regno < 8 ) return LO_REGS ; return HI_REGS ; } if ( regno <= LAST_ARM_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GENERAL_REGS ; if ( regno == CC_REGNUM || regno == VFPCC_REGNUM ) return NO_REGS ; if ( IS_CIRRUS_REGNUM ( regno ) ) return CIRRUS_REGS ; if ( IS_VFP_REGNUM ( regno ) ) return VFP_REGS ; if ( IS_IWMMXT_REGNUM ( regno ) ) return IWMMXT_REGS ; if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return IWMMXT_GR_REGS ; return FPA_REGS ; } </s>

For efficiency and historical reasons LO_REGS , HI_REGS and CC_REGS are not used in arm mode .


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s>
unsigned
MipsABIInfo
::
GetCalleeAllocdArgSizeInBytes
(
CallingConv
::
ID
CC
)
const
{
if
(
IsO32
(
)
)
return
CC
!=
CallingConv
::
Fast
16
:
0
;
if
(
IsN32
(
)
||
IsN64
(
)
||
IsEABI
(
)
)
return
0
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

Obtain the size of the area allocated by the callee for arguments .


<s> const CallLowering * getCallLowering ( ) const override { return CallLoweringInfo . get ( ) ; } </s>


<s>
unsigned
Cpu0ABIInfo
::
GetCalleeAllocdArgSizeInBytes
(
CallingConv
::
ID
CC
)
const
{
if
(
IsO32
(
)
)
return
CC
!=
0
;
if
(
IsS32
(
)
)
return
0
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws"


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) { return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) >= TLS_MODEL_REAL ) ; } </s>

Return true if X is a symbol that refers to real ( rather than emulated ) TLS .