<s> static void push_regs ( HARD_REG_SET * mask , int interrupt_handler ) { int i ; int skip_fpscr = 0 ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_regs_intersect_p ( mask , & reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG ) ; COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = 1 ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> bool SystemZTDCPass :: runOnFunction ( Function & F ) { auto & TPC = getAnalysis < TargetPassConfig > ( ) ; if ( TPC . getTM < TargetMachine > ( ) . getSubtarget < SystemZSubtarget > ( F ) . hasSoftFloat ( ) ) return false ; ConvertedInsts . clear ( ) ; LogicOpsWorklist . clear ( ) ; PossibleJunk . clear ( ) ; for ( auto & I : instructions ( F ) ) { if ( I . getOpcode ( ) == Instruction :: FCmp ) convertFCmp ( cast < CmpInst > ( I ) ) ; else if ( I . getOpcode ( ) == Instruction :: ICmp ) convertICmp ( cast < CmpInst > ( I ) ) ; } if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 0 ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 1 ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , 0 ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Function * TDCFunc = Intrinsic :: getDeclaration ( & M , Intrinsic :: s390_tdc , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true ; } if ( ! MadeChange ) return false ; for ( auto * I : PossibleJunk ) if ( I -> user_empty ( ) ) I -> eraseFromParent ( ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


<s> const MipsTargetMachine & getTargetMachine ( ) { return static_cast < const MipsTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


"CFGuard check mechanism only used on 32-bit X86"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNo
;
}
</s>

Returns the register associated with this edge .


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget . isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; unsigned AddressSpace , Offset ; if ( Subtarget . is64Bit ( ) ) { Offset = 0x48 ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = 256 ; else AddressSpace = 257 ; } else { Offset = 0x24 ; AddressSpace = 256 ; } return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> unsigned PPCFastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill ) { const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_r ( MachineInstOpcode , UseRC , Op0 , Op0IsKill ) ; } </s>

Emit a MachineInstr with one register operand and a result register in the given register class .


<s> bool LC3TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_LC3 ) ) { return false ; } if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) { return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> unsigned PPCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == PPC :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { StackMapOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else { return get ( Opcode ) . getSize ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static void nds32_emit_stack_v3push ( unsigned Rb , unsigned Re , unsigned imm8u ) { unsigned regno ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx push_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; num_use_regs = Re - Rb + 1 + 3 ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = - ( num_use_regs * 4 ) ; for ( regno = Rb ; regno <= Re ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; offset = - ( num_use_regs * 4 ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset - imm8u ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; RTX_FRAME_RELATED_P ( adjust_sp_rtx ) = 1 ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; } </s>

Function to create a parallel rtx pattern which presents stack v3push behavior . The overall concept are : `` push registers to memory '' , `` adjust stack pointer '' .


<s> bool AArch64Subtarget :: supportsAddressTopByteIgnored ( ) const { if ( ! UseAddressTopByteIgnored ) return false ; if ( TargetTriple . isDriverKit ( ) ) return true ; if ( TargetTriple . isiOS ( ) ) { return TargetTriple . getiOSVersion ( ) >= VersionTuple ( 8 ) ; } return false ; } </s>

CPU has TBI ( top byte of addresses is ignored during HW address translation ) and OS enables it .


<s> Bucket ( const SCEV * B , Instruction * I ) : BaseSCEV ( B ) , Elements ( 1 , BucketElement ( I ) ) { } </s>

The bucket assigned by balanced partitioning .


<s> static void mips_for_each_saved_reg ( HOST_WIDE_INT sp_offset , mips_save_restore_fn fn ) { enum machine_mode fpr_mode ; HOST_WIDE_INT offset ; int regno ; offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( regno = GP_REG_LAST ; regno >= GP_REG_FIRST ; regno -- ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { mips_save_restore_reg ( gpr_mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( gpr_mode ) ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; fpr_mode = ( TARGET_SINGLE_FLOAT ? SFmode : DFmode ) ; for ( regno = ( FP_REG_LAST - FP_INC + 1 ) ; regno >= FP_REG_FIRST ; regno -= FP_INC ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { mips_save_restore_reg ( fpr_mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( fpr_mode ) ; } } </s>

Call FN for each register that is saved by the current function . SP_OFFSET is the offset of the current stack pointer from the start of the frame .


<s> static void iq2000_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int iq2000_off = ! cum -> last_arg_fp ; unsigned int iq2000_fp_off = cum -> last_arg_fp ; if ( ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) ) { int iq2000_save_gp_regs = MAX_ARGS_IN_REGISTERS - cum -> arg_words - iq2000_off ; int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum -> fp_arg_words - iq2000_fp_off ) ; if ( iq2000_save_gp_regs < 0 ) iq2000_save_gp_regs = 0 ; if ( iq2000_save_fp_regs < 0 ) iq2000_save_fp_regs = 0 ; * pretend_size = ( ( iq2000_save_gp_regs * UNITS_PER_WORD ) + ( iq2000_save_fp_regs * UNITS_PER_FPREG ) ) ; if ( ! ( no_rtl ) ) { if ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - ( iq2000_save_gp_regs * UNITS_PER_WORD ) ) ; mem = gen_rtx_MEM ( BLKmode , ptr ) ; move_block_from_reg ( cum -> arg_words + GP_ARG_FIRST + iq2000_off , mem , iq2000_save_gp_regs ) ; } } } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> EVT SICTargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i24 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> SDValue AArch64TargetLowering :: getTargetNode ( BlockAddressSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , 0 , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> static int min_insn_size ( rtx insn ) { int l = 0 ; if ( ! INSN_P ( insn ) || ! active_insn_p ( insn ) ) return 0 ; if ( GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPECV_ALIGN ) return 0 ; if ( GET_CODE ( insn ) == JUMP_INSN && ( GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) ) return 0 ; if ( GET_CODE ( insn ) == CALL_INSN && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) && ! SIBLING_CALL_P ( insn ) ) return 5 ; if ( get_attr_length ( insn ) <= 1 ) return 1 ; if ( GET_CODE ( insn ) != JUMP_INSN ) { l = get_attr_length_address ( insn ) ; if ( l < 4 && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) ) l = 4 ; } if ( l ) return 1 + l ; else return 2 ; } </s>

We do n't have exact information about the insn sizes , but we may assume quite safely that we are informed about all 1 byte insns and memory address sizes . This is enough to eliminate unnecessary padding in 99 % of cases .


<s> bool DCPU16DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"After expanding ARM pseudo instructions."

runOnMachineFunction - Emit the function body .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasOptNone ( ) ) OptimizationGoal = 6 ; else if ( F . hasMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . hasOptSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>


<s> void MipsAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> int getStackPointerBias ( ) override final { return 0 ; } </s>

The 64-bit ABI uses biased stack and frame pointers , so the stack frame of the current function is the area from [ sp+BIAS ] to [ fp+BIAS ] .


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> static void loongarch_split_plus ( rtx x , rtx * base_ptr , HOST_WIDE_INT * offset_ptr ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) ) { * base_ptr = XEXP ( x , 0 ) ; * offset_ptr = INTVAL ( XEXP ( x , 1 ) ) ; } else { * base_ptr = x ; * offset_ptr = 0 ; } } </s>

If X is a PLUS of a CONST_INT , return the two terms in * BASE_PTR and * OFFSET_PTR . Return X in * BASE_PTR and 0 in * OFFSET_PTR otherwise .


<s> const TargetRegisterClass * getRepRegClassFor ( MVT VT ) const override { if ( VT == MVT :: Untyped ) return Subtarget -> hasDSP ( ) ? & Mips :: ACC64DSPRegClass : & Mips :: ACC64RegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .


<s>
static
bool
Check
(
DecodeStatus
&
Out
,
DecodeStatus
In
)
{
switch
(
In
)
{
case
MCDisassembler
::
Success
:
return
true
;
case
MCDisassembler
::
SoftFail
:
Out
=
In
;
return
true
;
case
MCDisassembler
::
Fail
:
Out
=
In
;
return
false
;
}
llvm_unreachable
(
"Invalid DecodeStatus!"
)
;
}
</s>

Matches check string and its `` not strings '' and/or `` dag strings '' .


<s> StringRef getPassName ( ) const override { return X86_MACHINEINSTR_PRINTER_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool check_builtin_call ( location_t location , vec < location_t > , unsigned int code , tree fndecl , unsigned int nargs , tree * args ) { const registered_function & rfn = * ( * registered_functions ) [ code ] ; if ( ! check_required_extensions ( location , rfn . decl , rfn . required_extensions ) ) return false ; return function_checker ( location , rfn . instance , fndecl , TREE_TYPE ( rfn . decl ) , nargs , args ) . check ( ) ; } </s>

Perform any semantic checks needed for a call to the SVE function with subcode CODE , such as testing for integer constant expressions . The call occurs at location LOCATION and has NARGS arguments , given by ARGS . FNDECL is the original function decl , before overload resolution . Return true if the call is valid , otherwise report a suitable error .


<s> static int ix86_memory_move_cost ( machine_mode mode , reg_class_t regclass , bool in ) { return inline_memory_move_cost ( mode , ( enum reg_class ) regclass , in ? 1 : 0 ) ; } </s>

Return the cost of moving data of mode M between a register and memory . A value of 2 is the default ; this cost is relative to those in ` REGISTER_MOVE_COST ' . If moving between registers and memory is more expensive than between two registers , you should define this macro to express the relative cost . Model also increased moving costs of QImode registers in non Q_REGS classes .


<s>
void
AArch64InstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
if
(
MI
->
getOpcode
(
)
==
AArch64
::
TLSDESCCALL
)
{
O
<<
"\t.tlsdesccall "
<<
*
MI
->
getOperand
(
0
)
.
getExpr
(
)
;
}
else
if
(
!
printAliasInstr
(
MI
,
O
)
)
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool ARMTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForNode ( CallConv , true , isVarArg ) ) ; } </s>


"\t.word\t0x00000000\t\t# <static chain value>\n"

Worker for TARGET_ASM_TRAMPOLINE_TEMPLATE .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> static void vax_trampoline_init ( rtx m_tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , HImode , 0 ) ; emit_move_insn ( mem , gen_const_mem ( HImode , fnaddr ) ) ; mem = adjust_address ( m_tramp , SImode , 4 ) ; emit_move_insn ( mem , cxt ) ; mem = adjust_address ( m_tramp , SImode , 11 ) ; emit_move_insn ( mem , plus_constant ( Pmode , fnaddr , 2 ) ) ; emit_insn ( gen_sync_istream ( ) ) ; } </s>

We copy the register-mask from the function 's pure code to the start of the trampoline .


<s> void KudeyarInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( Kudeyar :: MOV_MR32 ) ) . addFrameIndex ( FrameIdx ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


Implement target hook libgcc_floating_mode_supported_p .


<s> int AArch64TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( AM , Ty , AS ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( ( type -> isVectorTy ( ) || type -> isFloatingPointTy ( ) ) && Subtarget . hasVector ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> bool X86PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> static int mips16_rewrite_pool_refs ( rtx * x , void * data ) { struct mips16_constant_pool * pool = data ; if ( GET_CODE ( * x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( * x ) ) * x = gen_rtx_LABEL_REF ( Pmode , add_constant ( pool , get_pool_constant ( * x ) , get_pool_mode ( * x ) ) ) ; return 0 ; } </s>

Rewrite * X so that constant pool references refer to the constant 's label instead . DATA points to the constant pool structure .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void aarch64_update_cpp_builtins ( cpp_reader * pfile ) { aarch64_def_or_undef ( flag_unsafe_math_optimizations , "__ARM_FP_FAST" , pfile ) ; builtin_define_with_int_value ( "__ARM_ARCH" , aarch64_architecture_version ) ; builtin_define_with_int_value ( "__ARM_SIZEOF_MINIMAL_ENUM" , flag_short_enums ? 1 : 4 ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__AARCH64EB__" , pfile ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__ARM_BIG_ENDIAN" , pfile ) ; aarch64_def_or_undef ( ! TARGET_BIG_END , "__AARCH64EL__" , pfile ) ; aarch64_def_or_undef ( TARGET_FLOAT , "__ARM_FEATURE_FMA" , pfile ) ; if ( TARGET_FLOAT || TARGET_SIMD ) { builtin_define_with_int_value ( "__ARM_FP" , 0x0E ) ; builtin_define ( "__ARM_FP16_FORMAT_IEEE" ) ; builtin_define ( "__ARM_FP16_ARGS" ) ; } else cpp_undef ( pfile , "__ARM_FP" ) ; aarch64_def_or_undef ( TARGET_FP_F16INST , "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_F16INST , "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_FEATURE_NUMERIC_MAXMIN" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_NEON" , pfile ) ; aarch64_def_or_undef ( TARGET_CRC32 , "__ARM_FEATURE_CRC32" , pfile ) ; aarch64_def_or_undef ( TARGET_DOTPROD , "__ARM_FEATURE_DOTPROD" , pfile ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_TINY__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_SMALL__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_LARGE__" ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : builtin_define ( "__AARCH64_CMODEL_TINY__" ) ; break ; case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : builtin_define ( "__AARCH64_CMODEL_SMALL__" ) ; break ; case AARCH64_CMODEL_LARGE : builtin_define ( "__AARCH64_CMODEL_LARGE__" ) ; break ; default : break ; } aarch64_def_or_undef ( TARGET_ILP32 , "_ILP32" , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , "__ILP32__" , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , "__ARM_FEATURE_CRYPTO" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , "__ARM_FEATURE_QRDMX" , pfile ) ; aarch64_def_or_undef ( TARGET_SVE , "__ARM_FEATURE_SVE" , pfile ) ; cpp_undef ( pfile , "__ARM_FEATURE_SVE_BITS" ) ; if ( TARGET_SVE ) { int bits ; if ( ! BITS_PER_SVE_VECTOR . is_constant ( & bits ) ) bits = 0 ; builtin_define_with_int_value ( "__ARM_FEATURE_SVE_BITS" , bits ) ; } aarch64_def_or_undef ( TARGET_AES , "__ARM_FEATURE_AES" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA2 , "__ARM_FEATURE_SHA2" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , "__ARM_FEATURE_SHA3" , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , "__ARM_FEATURE_SHA512" , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , "__ARM_FEATURE_SM3" , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , "__ARM_FEATURE_SM4" , pfile ) ; aarch64_def_or_undef ( TARGET_F16FML , "__ARM_FEATURE_FP16_FML" , pfile ) ; cpp_undef ( pfile , "__FLT_EVAL_METHOD__" ) ; builtin_define_with_int_value ( "__FLT_EVAL_METHOD__" , c_flt_eval_method ( true ) ) ; cpp_undef ( pfile , "__FLT_EVAL_METHOD_C99__" ) ; builtin_define_with_int_value ( "__FLT_EVAL_METHOD_C99__" , c_flt_eval_method ( false ) ) ; } </s>

Undefine/redefine macros that depend on the current backend state and may need to change when a target pragma modifies the backend state .


<s> static hashval_t mips_hash_base ( rtx base ) { int do_not_record_p ; return hash_rtx ( base , GET_MODE ( base ) , & do_not_record_p , NULL , false ) ; } </s>

Return a hash value for SYMBOL_REF or LABEL_REF BASE .


<s> bool i386_pe_valid_dllimport_attribute_p ( tree decl ) { if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; return true ; } </s>

Handle the -mno-fun-dllimport target switch .


<s> void function_expander :: add_output_operand ( insn_code icode ) { unsigned int opno = m_ops . length ( ) ; machine_mode mode = insn_data [ icode ] . operand [ opno ] . mode ; m_ops . safe_grow ( opno + 1 , true ) ; create_output_operand ( & m_ops . last ( ) , possible_target , mode ) ; } </s>

Create output and add it into M_OPS and increase OPNO .


<s>
static
unsigned
getOpcode_EXTEND_VECTOR_INREG
(
unsigned
Opcode
)
{
switch
(
Opcode
)
{
case
ISD
::
ANY_EXTEND
:
case
ISD
::
ANY_EXTEND_VECTOR_INREG
:
return
ISD
::
ANY_EXTEND_VECTOR_INREG
;
case
ISD
::
ZERO_EXTEND
:
case
ISD
::
ZERO_EXTEND_VECTOR_INREG
:
return
ISD
::
ZERO_EXTEND_VECTOR_INREG
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
SIGN_EXTEND_VECTOR_INREG
:
return
ISD
::
SIGN_EXTEND_VECTOR_INREG
;
}
llvm_unreachable
(
"Unknown opcode"
)
;
}
</s>

Convert * _EXTEND to * _EXTEND_VECTOR_INREG opcode .


<s>
unsigned
char
X86Subtarget
::
ClassifyGlobalReference
(
const
GlobalValue
*
GV
,
const
TargetMachine
&
TM
)
const
{
if
(
GV
->
hasDLLImportLinkage
(
)
)
return
X86II
::
MO_DLLIMPORT
;
bool
isDecl
=
GV
->
isDeclaration
(
)
&&
!
GV
->
hasNotBeenReadFromBitcode
(
)
;
if
(
isPICStyleRIPRel
(
)
)
{
if
(
TM
.
getCodeModel
(
)
==
CodeModel
::
Large
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
->
hasDefaultVisibility
(
)
&&
(
isDecl
||
GV
->
isWeakForLinker
(
)
)
)
return
X86II
::
MO_GOTPCREL
;
}
else
{
assert
(
isTargetELF
(
)
&&
"Unknown rip-relative target"
)
;
if
(
!
GV
->
hasLocalLinkage
(
)
&&
GV
->
hasDefaultVisibility
(
)
)
return
X86II
::
MO_GOTPCREL
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isPICStyleGOT
(
)
)
{
if
(
GV
->
hasLocalLinkage
(
)
||
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_GOTOFF
;
return
X86II
::
MO_GOT
;
}
if
(
isPICStyleStubPIC
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_PIC_BASE_OFFSET
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
;
}
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
if
(
isPICStyleStubNoDynamic
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY
;
}
return
X86II
::
MO_NO_FLAG
;
}
return
X86II
::
MO_NO_FLAG
;
}
</s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> static bool loongarch_rtx_constant_in_small_data_p ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) <= g_switch_value ) ; } </s>

Return true if rtx constants of mode MODE should be put into a small data section .


<s> void Cpu0MCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> static bool expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt ) { machine_mode v2mode ; rtx x ; if ( ! GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) . exists ( & v2mode ) ) return false ; x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return expand_vselect ( target , x , perm , nelt ) ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s> bool PPCFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , ISD :: ADD ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , ISD :: OR ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , ISD :: SUB ) ; case Instruction :: Call : return selectCall ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I ) ; default : break ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } } </s>


<s> static bool ix86_cannot_force_const_mem ( rtx x ) { return ! legitimate_constant_p ( x ) ; } </s>

Determine if it 's legal to put X into the constant pool . This is not possible for the address of thread-local symbols , which is checked above .


<s> static tree sparc_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= SPARC_BUILTIN_MAX ) return error_mark_node ; return sparc_builtins [ code ] ; } </s>


<s> static bool aarch64_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t ) { unsigned int from_flags = aarch64_classify_vector_mode ( from ) ; unsigned int to_flags = aarch64_classify_vector_mode ( to ) ; bool from_sve_p = ( from_flags & VEC_ANY_SVE ) ; bool to_sve_p = ( to_flags & VEC_ANY_SVE ) ; bool from_partial_sve_p = from_sve_p && ( from_flags & VEC_PARTIAL ) ; bool to_partial_sve_p = to_sve_p && ( to_flags & VEC_PARTIAL ) ; bool from_pred_p = ( from_flags & VEC_SVE_PRED ) ; bool to_pred_p = ( to_flags & VEC_SVE_PRED ) ; if ( from_pred_p != to_pred_p ) return false ; if ( from_partial_sve_p != to_partial_sve_p ) return false ; if ( from_partial_sve_p && ( aarch64_sve_container_bits ( from ) != aarch64_sve_container_bits ( to ) || GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) ) return false ; if ( maybe_ne ( BITS_PER_SVE_VECTOR , 128u ) ) { if ( from_sve_p && ! to_sve_p && maybe_gt ( GET_MODE_BITSIZE ( to ) , 128 ) ) return false ; if ( to_sve_p && ! from_sve_p && maybe_gt ( GET_MODE_BITSIZE ( from ) , 128 ) ) return false ; } if ( BYTES_BIG_ENDIAN ) { if ( from_sve_p != to_sve_p ) return false ; if ( from_sve_p && GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) return false ; } return true ; } </s>


<s> static void mips_block_move_loop ( rtx dest , rtx src , HOST_WIDE_INT length ) { rtx label , src_reg , dest_reg , final_src ; HOST_WIDE_INT leftover ; leftover = length % MAX_MOVE_BYTES ; length -= leftover ; mips_adjust_block_mem ( src , MAX_MOVE_BYTES , & src_reg , & src ) ; mips_adjust_block_mem ( dest , MAX_MOVE_BYTES , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; mips_block_move_straight ( dest , src , MAX_MOVE_BYTES ) ; emit_move_insn ( src_reg , plus_constant ( src_reg , MAX_MOVE_BYTES ) ) ; emit_move_insn ( dest_reg , plus_constant ( dest_reg , MAX_MOVE_BYTES ) ) ; if ( Pmode == DImode ) emit_insn ( gen_cmpdi ( src_reg , final_src ) ) ; else emit_insn ( gen_cmpsi ( src_reg , final_src ) ) ; emit_jump_insn ( gen_bne ( label ) ) ; if ( leftover ) mips_block_move_straight ( dest , src , leftover ) ; } </s>

Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES per iteration . LENGTH must be at least MAX_MOVE_BYTES . Assume that the memory regions do not overlap .


<s> int getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 21 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getSExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s>
static
void
process_epilogue
(
)
{
if
(
block_num
!=
n_basic_blocks
1
)
{
fprintf
(
asm_out_file
,
"\t.label_state 1\n"
)
;
need_copy_state
=
1
;
}
fprintf
(
asm_out_file
,
"\t.restore sp\n"
)
;
}
</s>

The function emits unwind directives for the start of an epilogue .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( 0 ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> static void vax_init_libfuncs ( void ) { if ( TARGET_BSD_DIVMOD ) { set_optab_libfunc ( udiv_optab , SImode , TARGET_ELF ? "*__udiv" : "*udiv" ) ; set_optab_libfunc ( umod_optab , SImode , TARGET_ELF ? "*__urem" : "*urem" ) ; } } </s>

We can use the BSD C library routines for the libgcc calls that are still generated , since that 's what they boil down to anyways . When ELF , avoid the user 's namespace .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH ) ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool ix86_tieable_integer_mode_p ( enum machine_mode mode ) { switch ( mode ) { case HImode : case SImode : return true ; case QImode : return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case DImode : return TARGET_64BIT ; default : return false ; } } </s>

A subroutine of ix86_modes_tieable_p . Return true if MODE is a tieable integer mode .


"Pseudo flag setting opcodes only exist in Selection DAG"

Perform target-specific instruction verification .


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool AArch64InstrInfo :: getMemOperandsWithOffsetWidth ( const MachineInstr & LdSt , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; const MachineOperand * BaseOp ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , OffsetIsScalable , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true ; } </s>

Get zero or more base operands and the byte offset of an instruction that reads/writes memory .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; if ( getPPCTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) addPass ( createPPCTLSDynamicCallPass ( ) ) ; if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool ARM64AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"TOY DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = 0 ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = 0 ; } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum -> force_bnd_pass = nregs ; if ( ! nregs ) { if ( cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; if ( flag_check_pointer_bounds ) cum -> bnds_in_bt = chkp_type_bounds_count ( type ) ; } } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getVectorElementType ( ) . getSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static bool aarch64_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t ) { if ( BYTES_BIG_ENDIAN ) { bool from_sve_p = aarch64_sve_data_mode_p ( from ) ; bool to_sve_p = aarch64_sve_data_mode_p ( to ) ; if ( from_sve_p != to_sve_p ) return false ; if ( from_sve_p && GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) return false ; } return true ; } </s>


<s> void X86DynAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { const DebugLoc & DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getDynAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; bool Is64BitAlloca = MI -> getOpcode ( ) == X86 :: DYN_ALLOCA_64 ; assert ( SlotSize == 4 || SlotSize == 8 ) ; Optional < MachineFunction :: DebugInstrOperandPair > InstrNum = None ; if ( unsigned Num = MI -> peekDebugInstrNum ( ) ) { InstrNum = { Num , 2 } ; } switch ( L ) { case TouchAndSub : { assert ( Amount >= SlotSize ) ; unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; } case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64BitAlloca , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false , InstrNum ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64BitAlloca ? X86 :: SUB64rr : X86 :: SUB32rr ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; } break ; } Register AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; if ( MRI -> use_empty ( AmountReg ) ) if ( MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ) AmountDef -> eraseFromParent ( ) ; } </s>


"max branch displacement must be enough to jump"

Determine if the branch target is in range .


<s> void rs6000_expand_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , cond ; machine_mode mode ; enum memmodel model ; rtx label , x , mask , shift ; retval = operands [ 0 ] ; mem = operands [ 1 ] ; val = operands [ 2 ] ; model = memmodel_base ( INTVAL ( operands [ 3 ] ) ) ; mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( ! TARGET_SYNC_HI_QI && ( mode == QImode || mode == HImode ) ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; val = convert_modes ( SImode , mode , val , 1 ) ; val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; x = val ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , val , mask ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; rs6000_post_atomic_barrier ( model ) ; if ( shift ) rs6000_finish_atomic_subword ( operands [ 0 ] , retval , shift ) ; } </s>


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> DecodeStatus ARM64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { CommentStream = & cs ; uint8_t bytes [ 4 ] ; Size = 0 ; if ( Region . readBytes ( Address , 4 , ( uint8_t * ) bytes ) == - 1 ) return Fail ; Size = 4 ; uint32_t insn = ( bytes [ 3 ] << 24 ) | ( bytes [ 2 ] << 16 ) | ( bytes [ 1 ] << 8 ) | ( bytes [ 0 ] << 0 ) ; DecodeStatus result = decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; if ( ! result ) return Fail ; return Success ; } </s>

Returns the disassembly of a single instruction .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , LI -> getAlign ( ) , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; Register IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> static void pa_select_section ( tree exp , int reloc , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TREE_CODE ( exp ) == VAR_DECL && TREE_READONLY ( exp ) && ! TREE_THIS_VOLATILE ( exp ) && DECL_INITIAL ( exp ) && ( DECL_INITIAL ( exp ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( exp ) ) ) && ! reloc ) { if ( TARGET_SOM && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) som_one_only_readonly_data_section ( ) ; else readonly_data_section ( ) ; } else if ( CONSTANT_CLASS_P ( exp ) && ! reloc ) readonly_data_section ( ) ; else if ( TARGET_SOM && TREE_CODE ( exp ) == VAR_DECL && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) som_one_only_data_section ( ) ; else data_section ( ) ; } </s>

On hpux10 , the linker will give an error if we have a reference in the read-only data section to a symbol defined in a shared library . Therefore , expressions that might require a reloc can not be placed in the read-only data section .


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> bool hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr * DefMI , unsigned DefIdx ) const override { return false ; } </s>

Compute operand latency of a def of 'Reg ' .


"%qs requires PowerPC64 architecture, enabling"

The Darwin version of SUBTARGET_OVERRIDE_OPTIONS .


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
<<
"alignment  : "
<<
DebugStr
(
MF
.
getFrameInfo
(
)
.
getObjectAlign
(
FrameIndex
)
)
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"
"alignment  : "
"\n"


<s> inline tree function_instance :: memory_scalar_type ( ) const { return base -> memory_scalar_type ( * this ) ; } </s>

If the function addresses memory , return the type of a single scalar memory element .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
(
Divisor
)
.
isPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasCMov
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
APInt
Lg2Mask
=
APInt
::
getLowBitsSet
(
VT
.
getSizeInBits
(
)
,
Lg2
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
Lg2Mask
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i8
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> static machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_NEXT_MODE ( o ) . require ( ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * 2 ) ; gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return n ; } </s>

Get a vector mode of the same size as the original but with elements twice as wide . This is only guaranteed to apply to integral vectors .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool AArch64Subtarget :: supportsAddressTopByteIgnored ( ) const { if ( ! UseAddressTopByteIgnored ) return false ; if ( TargetTriple . isiOS ( ) ) { return TargetTriple . getiOSVersion ( ) >= VersionTuple ( 8 ) ; } return false ; } </s>

CPU has TBI ( top byte of addresses is ignored during HW address translation ) and OS enables it .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSPDSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR" MipsISD::EXTP "MipsISD::EXTP" MipsISD::EXTPDP "MipsISD::EXTPDP" MipsISD::EXTR_S_H "MipsISD::EXTR_S_H" MipsISD::EXTR_W "MipsISD::EXTR_W" MipsISD::EXTR_R_W "MipsISD::EXTR_R_W" MipsISD::EXTR_RS_W "MipsISD::EXTR_RS_W" MipsISD::SHILO "MipsISD::SHILO" MipsISD::MTHLIP "MipsISD::MTHLIP" MipsISD::MULT "MipsISD::MULT" MipsISD::MULTU "MipsISD::MULTU" MipsISD::MADD_DSP "MipsISD::MADD_DSPDSP" MipsISD::MADDU_DSP "MipsISD::MADDU_DSP" MipsISD::MSUB_DSP "MipsISD::MSUB_DSP" MipsISD::MSUBU_DSP "MipsISD::MSUBU_DSP"


<s> unsigned LEGInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { unsigned NumInserted = 0 ; if ( Cond . size ( ) > 0 ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( LEG :: Bcc ) ) . addOperand ( Cond [ 0 ] ) . addMBB ( TBB ) ; NumInserted ++ ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( LEG :: B ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ; } return NumInserted ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s>
SDValue
OpenRISCTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

OpenRISC
OpenRISC
ISD::InputArg
"Unsupported calling convention"


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MFI -> hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool runOnFunction ( Function & F ) override { bool C = false ; TargetMachine * TM = & getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ; TargetLibraryInfo * TLI = & getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( F ) ; X86LowerAMXCast LAC ( F ) ; C |= LAC . combineAMXcast ( TLI ) ; C |= LAC . transformAllAMXCast ( ) ; X86LowerAMXType LAT ( F ) ; C |= LAT . visit ( ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) { if ( ! F . hasFnAttribute ( Attribute :: OptimizeNone ) ) { X86VolatileTileData VTD ( F ) ; C = VTD . volatileTileData ( ) || C ; } } return C ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void xstormy16_expand_andqi3 ( rtx * operands ) { rtx in , out , outsub , val ; out = operands [ 0 ] ; in = operands [ 1 ] ; val = operands [ 2 ] ; if ( xstormy16_onebit_clr_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_andqi3_internal ( out , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; return ; } if ( GET_CODE ( in ) != REG ) in = copy_to_mode_reg ( QImode , in ) ; if ( GET_CODE ( val ) != REG && GET_CODE ( val ) != CONST_INT ) val = copy_to_mode_reg ( QImode , val ) ; if ( GET_CODE ( out ) != REG ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , 0 ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , 0 ) ; if ( GET_CODE ( val ) != CONST_INT ) val = simplify_gen_subreg ( HImode , val , QImode , 0 ) ; emit_insn ( gen_andhi3 ( outsub , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; } </s>


<s>
MachineOperand
&
AArch64InstrInfo
::
getMemOpBaseRegImmOfsOffsetOperand
(
MachineInstr
&
LdSt
)
const
{
assert
(
LdSt
.
mayLoadOrStore
(
)
&&
"Expected a memory operation."
)
;
MachineOperand
&
OfsOp
=
LdSt
.
getOperand
(
LdSt
.
getNumExplicitOperands
(
)
1
)
;
assert
(
OfsOp
.
isImm
(
)
&&
"Offset operand wasn't immediate."
)
;
return
OfsOp
;
}
</s>

Return the immediate offset of the base register in a load/store LdSt .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : case 'v' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Immediate ; default : break ; } } else if ( Constraint . size ( ) == 2 && Constraint [ 0 ] == 'Z' ) { switch ( Constraint [ 1 ] ) { case 'Q' : case 'R' : case 'S' : case 'T' : return C_Address ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static long ppc_linux_aux_vector ( long which ) { extern long * __libc_stack_end ; long argc ; char * * argv ; char * * envp ; struct auxv { long a_type ; long a_val ; } * auxp ; argc = __libc_stack_end [ 0 ] ; argv = ( char * * ) __libc_stack_end + 1 ; envp = argv + argc + 1 ; while ( * envp ++ ) continue ; for ( auxp = ( struct auxv * ) envp ; auxp -> a_type != 0 ; ++ auxp ) if ( auxp -> a_type == which ) return auxp -> a_val ; return 0 ; } </s>

Find an entry in the process auxiliary vector . The canonical way to test for VMX is to look at AT_HWCAP .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( AdjustSPLabel , - StackSize ) ) ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; unsigned S1 = MRI -> getDwarfRegNum ( Mips :: S1 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , S1 , - 8 ) ) ; unsigned S0 = MRI -> getDwarfRegNum ( Mips :: S0 , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , S0 , - 12 ) ) ; unsigned RA = MRI -> getDwarfRegNum ( Mips :: RA , true ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , RA , - 4 ) ) ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> tree loongarch_build_builtin_va_list ( void ) { return ptr_type_node ; } </s>


<s> static void mips_macc_chains_record ( rtx insn ) { if ( get_attr_may_clobber_hilo ( insn ) ) mips_macc_chains_last_hilo = insn ; } </s>

A TUNE_MACC_CHAINS helper function . Record that instruction INSN has been scheduled , updating mips_macc_chains_last_hilo appropriately .


"Blocked load and store instructions: \n"

runOnMachineFunction - Emit the function body .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( Register :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( ( FlagSfiLoad && N -> getOpcode ( ) == ISD :: LOAD ) || ( FlagSfiStore && N -> getOpcode ( ) == ISD :: STORE ) ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::LOAD ISD::STORE ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> void neon_disambiguate_copy ( rtx * operands , rtx * dest , rtx * src , unsigned int count ) { unsigned int i ; if ( ! reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) || REGNO ( operands [ 0 ] ) < REGNO ( operands [ 1 ] ) ) { for ( i = 0 ; i < count ; i ++ ) { operands [ 2 * i ] = dest [ i ] ; operands [ 2 * i + 1 ] = src [ i ] ; } } else { for ( i = 0 ; i < count ; i ++ ) { operands [ 2 * i ] = dest [ count - i - 1 ] ; operands [ 2 * i + 1 ] = src [ count - i - 1 ] ; } } } </s>

Set up OPERANDS for a register copy from SRC to DEST , taking care not to early-clobber SRC registers in the process . We assume that the operands described by SRC and DEST represent a decomposed copy of OPERANDS [ 1 ] into OPERANDS [ 0 ] . COUNT is the number of components into which the copy has been decomposed .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETI : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: NACL_CG_TCRETURNdi64 : case X86 :: NACL_CG_TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> virtual unsigned int execute ( function * fun ) { return rs6000_analyze_swaps ( fun ) ; } </s>


<s> SDValue DCPU16TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_DCPU16 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static int getMemScale ( const MachineInstr & MI ) { return getMemScale ( MI . getOpcode ( ) ) ; } </s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> bool isLegalMaskedLoad ( Type * DataType ) { return ST -> hasSVE ( ) ; } </s>

Return true if the target supports masked load .


<s> virtual const PPCRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void func_fma_steering :: dfs ( void ( * process_forest ) ( fma_forest * ) , void ( * process_root ) ( fma_forest * , fma_root_node * ) , void ( * process_node ) ( fma_forest * , fma_node * ) , bool free ) { vec < fma_node * > to_process ; std :: list < fma_forest * > :: iterator forest_iter ; to_process . create ( 0 ) ; for ( forest_iter = this -> m_fma_forests . begin ( ) ; forest_iter != this -> m_fma_forests . end ( ) ; forest_iter ++ ) { std :: list < fma_root_node * > :: iterator root_iter ; if ( process_forest ) process_forest ( * forest_iter ) ; for ( root_iter = ( * forest_iter ) -> get_roots ( ) -> begin ( ) ; root_iter != ( * forest_iter ) -> get_roots ( ) -> end ( ) ; root_iter ++ ) { if ( process_root ) process_root ( * forest_iter , * root_iter ) ; to_process . safe_push ( * root_iter ) ; } while ( ! to_process . is_empty ( ) ) { fma_node * node ; std :: list < fma_node * > :: iterator child_iter ; node = to_process . pop ( ) ; if ( process_node ) process_node ( * forest_iter , node ) ; if ( node -> get_children ( ) -> empty ( ) ) continue ; for ( child_iter = node -> get_children ( ) -> begin ( ) ; child_iter != node -> get_children ( ) -> end ( ) ; child_iter ++ ) to_process . safe_push ( * child_iter ) ; if ( free ) { if ( node -> root_p ( ) ) delete static_cast < fma_root_node * > ( node ) ; else delete node ; } } if ( free ) delete * forest_iter ; } to_process . release ( ) ; } </s>

Perform a depth-first search of the forests of fma_node in THIS- > m_fma_forests , calling PROCESS_FOREST ( ) on each fma_forest object in THIS- > m_fma_forests list , PROCESS_ROOT ( ) on each tree root and PROCESS_NODE ( ) on each node . If FREE is true , free all std : :list in the same dfs .


<s> unsigned X86TTIImpl :: getScalarizationOverhead ( VectorType * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { unsigned Cost = 0 ; if ( Insert ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ( MScalarTy == MVT :: i16 && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) || ( MScalarTy == MVT :: f32 && ST -> hasSSE41 ( ) ) ) { if ( LT . second . getSizeInBits ( ) <= 128 ) { Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , false ) ; } else { unsigned Num128Lanes = LT . second . getSizeInBits ( ) / 128 * LT . first ; unsigned NumElts = LT . second . getVectorNumElements ( ) * LT . first ; APInt WidenedDemandedElts = DemandedElts . zextOrSelf ( NumElts ) ; unsigned Scale = NumElts / Num128Lanes ; for ( unsigned I = 0 ; I < NumElts ; I += Scale ) { APInt Mask = WidenedDemandedElts . getBitsSet ( NumElts , I , I + Scale ) ; APInt MaskedDE = Mask & WidenedDemandedElts ; unsigned Population = MaskedDE . countPopulation ( ) ; Cost += ( Population > 0 && Population != Scale && I % LT . second . getVectorNumElements ( ) != 0 ) ; Cost += Population > 0 ; } Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == MVT :: f32 ) for ( unsigned i = 0 , e = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; i < e ; i += 4 ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ) ; Cost += ( std :: min < unsigned > ( NumElts , Pow2Elts ) - 1 ) * LT . first ; } } if ( Extract ) Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , false , Extract ) ; return Cost ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> MVT :: SimpleValueType MipsTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> int emit_cbcond_nop ( rtx_insn * insn ) { rtx next = next_active_insn ( insn ) ; if ( ! next ) return 1 ; if ( NONJUMP_INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) == SEQUENCE ) next = XVECEXP ( PATTERN ( next ) , 0 , 0 ) ; else if ( CALL_P ( next ) && GET_CODE ( PATTERN ( next ) ) == PARALLEL ) { rtx delay = XVECEXP ( PATTERN ( next ) , 0 , 1 ) ; if ( GET_CODE ( delay ) == RETURN ) { if ( sparc_leaf_function_p || TARGET_FLAT ) return 0 ; } } if ( NONJUMP_INSN_P ( next ) ) return 0 ; return 1 ; } </s>

Return nonzero if we should emit a nop after a cbcond instruction . The cbcond instruction does not have a delay slot , however there is a severe performance penalty if a control transfer appears right after a cbcond . Therefore we emit a nop when we detect this situation .


<s> void LC3InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> static void mark_frame_related ( rtx insn ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = PATTERN ( insn ) ; if ( GET_CODE ( insn ) == PARALLEL ) { unsigned int i ; for ( i = 0 ; i < ( unsigned ) XVECLEN ( insn , 0 ) ; i ++ ) RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , i ) ) = 1 ; } } </s>

Mark INSN as being frame related . If it is a PARALLEL then mark each element as being frame related as well .


<s>
void
X86InstPrinterCommon
::
printPCRelImm
(
const
MCInst
*
MI
,
uint64_t
Address
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
if
(
SymbolizeOperands
)
return
;
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
{
if
(
PrintBranchImmAsAddress
)
{
uint64_t
Target
=
Address
+
Op
.
getImm
(
)
;
if
(
MAI
.
getCodePointerSize
(
)
==
4
)
Target
&=
0xffffffff
;
O
<<
formatHex
(
Target
)
;
}
else
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
}
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
Op
.
getExpr
(
)
->
print
(
O
,
&
MAI
)
;
}
}
}
</s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createARMMachObjectWriter ( OS , false , object :: mach :: CTM_ARM , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : { if ( tryInlineAsm ( N ) ) return ; break ; } case SPISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; if ( ( ( SparcTargetMachine & ) TM ) . getSubtargetImpl ( ) -> performSDIVReplace ( ) && Opcode == SP :: SDIVrr ) { Opcode = SP :: SDIVCCrr ; } CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; return ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> enum non_prefixed_form reg_to_non_prefixed ( rtx reg , machine_mode mode ) { if ( ! REG_P ( reg ) && ! SUBREG_P ( reg ) ) return NON_PREFIXED_DEFAULT ; unsigned int r = reg_or_subregno ( reg ) ; if ( ! HARD_REGISTER_NUM_P ( r ) ) return NON_PREFIXED_DEFAULT ; unsigned size = GET_MODE_SIZE ( mode ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode || size == 8 || FLOAT128_2REG_P ( mode ) ) return NON_PREFIXED_D ; else if ( size < 8 ) return NON_PREFIXED_X ; else if ( TARGET_VSX && size >= 16 && ( VECTOR_MODE_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || mode == TImode || mode == CTImode ) ) return ( TARGET_P9_VECTOR ) ? NON_PREFIXED_DQ : NON_PREFIXED_X ; else return NON_PREFIXED_DEFAULT ; } else if ( ALTIVEC_REGNO_P ( r ) ) { if ( ! TARGET_P9_VECTOR ) return NON_PREFIXED_X ; if ( mode == SFmode || size == 8 || FLOAT128_2REG_P ( mode ) ) return NON_PREFIXED_DS ; else if ( size < 8 ) return NON_PREFIXED_X ; else if ( TARGET_VSX && size >= 16 && ( VECTOR_MODE_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || mode == TImode || mode == CTImode ) ) return NON_PREFIXED_DQ ; else return NON_PREFIXED_DEFAULT ; } else if ( TARGET_POWERPC64 && size >= 8 ) return NON_PREFIXED_DS ; return NON_PREFIXED_D ; } </s>

Helper function to take a REG and a MODE and turn it into the non-prefixed instruction format ( D/DS/DQ ) used for offset memory .


<s> static int mips_address_cost ( rtx addr , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return mips_address_insns ( addr , mode , false ) ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { unsigned PredReg = 0 ; return llvm :: getITInstrPredicate ( MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s>
void
Cpu0InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOStore
)
;
unsigned
Opc
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Cpu0
::
ST
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned int getNumFixupKinds ( ) const { return AArch64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static void pa_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int arg_size = pa_function_arg_size ( arg . mode , arg . type ) ; cum -> nargs_prototype -- ; cum -> words += ( arg_size + ( ( cum -> words & 01 ) && arg . type != NULL_TREE && arg_size > 1 ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> rtx thumb_legitimize_address ( rtx x , rtx orig_x , enum machine_mode mode ) { if ( arm_tls_symbol_p ( x ) ) return legitimize_tls_address ( x , NULL_RTX ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( x , 1 ) ) >= 32 * GET_MODE_SIZE ( mode ) || INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset >= 0 && offset < 256 + 31 * GET_MODE_SIZE ( mode ) ) { HOST_WIDE_INT delta ; if ( offset >= 256 ) delta = offset - ( 256 - GET_MODE_SIZE ( mode ) ) ; else if ( offset < 32 * GET_MODE_SIZE ( mode ) + 8 ) delta = 31 * GET_MODE_SIZE ( mode ) ; else delta = offset & ( ~ 31 * GET_MODE_SIZE ( mode ) ) ; xop0 = force_operand ( plus_constant ( xop0 , offset - delta ) , NULL_RTX ) ; x = plus_constant ( xop0 , delta ) ; } else if ( offset < 0 && offset > - 256 ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , 1 ) , SImode ) && ! s_register_operand ( XEXP ( x , 0 ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , 1 ) ) ; } if ( flag_pic ) { rtx new_x = legitimize_pic_address ( orig_x , mode , NULL_RTX ) ; if ( new_x != orig_x ) x = new_x ; } return x ; } </s>

Try machine-dependent ways of modifying an illegitimate Thumb address to be legitimate . If we find one , return the new , valid address .


<s> TargetPassConfig * MipsTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MipsPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static tree ix86_vectorize_builtin_gather ( const_tree mem_vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX2 || ! TARGET_USE_GATHER ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( mem_vectype ) ) { case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DF : IX86_BUILTIN_GATHER3DIV2DF ; else code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DF : IX86_BUILTIN_GATHER3DIV4DF ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DI : IX86_BUILTIN_GATHER3DIV2DI ; else code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DI : IX86_BUILTIN_GATHER3DIV4DI ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SF : IX86_BUILTIN_GATHER3DIV4SF ; else code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SF : IX86_BUILTIN_GATHER3ALTDIV8SF ; else code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SI : IX86_BUILTIN_GATHER3DIV4SI ; else code = si ? IX86_BUILTIN_GATHERSIV4SI : IX86_BUILTIN_GATHERDIV4SI ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SI : IX86_BUILTIN_GATHER3ALTDIV8SI ; else code = si ? IX86_BUILTIN_GATHERSIV8SI : IX86_BUILTIN_GATHERALTDIV8SI ; break ; case E_V8DFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DF : IX86_BUILTIN_GATHER3DIV8DF ; else return NULL_TREE ; break ; case E_V8DImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DI : IX86_BUILTIN_GATHER3DIV8DI ; else return NULL_TREE ; break ; case E_V16SFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SF : IX86_BUILTIN_GATHER3ALTDIV16SF ; else return NULL_TREE ; break ; case E_V16SImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SI : IX86_BUILTIN_GATHER3ALTDIV16SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return ix86_get_builtin ( code ) ; } </s>

Returns a decl of a function that implements gather load with memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE . Return NULL_TREE if it is not available .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwin ( ) ) Reserved . set ( PPC :: R2 ) ; if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! EnableRegisterScavenging ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; } if ( needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


Do one-time initialization of COSTS given that we 're costing the loop vectorization described by LOOP_VINFO .


<s> static void nds32_setup_incoming_varargs ( cumulative_args_t ca , const function_arg_info & arg , int * pretend_args_size , int second_time ATTRIBUTE_UNUSED ) { unsigned int total_args_regs ; unsigned int num_of_used_regs ; unsigned int remaining_reg_count ; CUMULATIVE_ARGS * cum ; if ( TARGET_HARD_FLOAT ) return ; cum = get_cumulative_args ( ca ) ; total_args_regs = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) num_of_used_regs = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , arg . mode , arg . type ) + NDS32_NEED_N_REGS_FOR_ARG ( arg . mode , arg . type ) ; else num_of_used_regs = cum -> gpr_offset + NDS32_GPR_ARG_FIRST_REGNUM ; remaining_reg_count = total_args_regs - num_of_used_regs ; * pretend_args_size = remaining_reg_count * UNITS_PER_WORD ; return ; } </s>


<s>
InstructionCost
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
TargetCostKind
CostKind
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
if
(
CostKind
!=
TTI
::
TCK_RecipThroughput
)
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
,
Args
,
CxtI
)
;
InstructionCost
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static rtx loongarch_legitimize_tls_address ( rtx loc ) { rtx dest , tp , tmp ; enum tls_model model = SYMBOL_REF_TLS_MODEL ( loc ) ; rtx_insn * insn ; switch ( model ) { case TLS_MODEL_LOCAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; insn = loongarch_call_tls_get_addr ( loc , SYMBOL_TLSLDM , tmp ) ; emit_libcall_block ( insn , dest , tmp , loc ) ; break ; case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; insn = loongarch_call_tls_get_addr ( loc , SYMBOL_TLSGD , tmp ) ; emit_libcall_block ( insn , dest , tmp , loc ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( loongarch_got_load_tls_ie ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( loongarch_got_load_tls_le ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread-local SYMBOL_REF , and return its address . The return value will be both a valid address and a valid SET_SRC ( either a REG or a LO_SUM ) .