<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MIB -> copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
const
char
*
nds32_output_return
(
void
)
{
char
pattern
[
100
]
;
rtx
operands
[
2
]
;
int
re_callee_saved
=
cfun
->
machine
->
callee_saved_last_gpr_regno
;
int
sp_adjust
;
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
re_callee_saved
)
;
sp_adjust
=
cfun
->
machine
->
local_size
+
cfun
->
machine
->
out_args_size
+
cfun
->
machine
->
callee_saved_area_gpr_padding_bytes
+
cfun
->
machine
->
callee_saved_fpr_regs_size
;
if
(
satisfies_constraint_Iu08
(
GEN_INT
(
sp_adjust
)
)
&&
NDS32_DOUBLE_WORD_ALIGN_P
(
sp_adjust
)
&&
!
cfun
->
calls_alloca
)
operands
[
1
]
=
GEN_INT
(
sp_adjust
)
;
else
operands
[
1
]
=
GEN_INT
(
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"pop25\t%%0, %%1"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
TOY
::
NumTargetFixupKinds
]
=
{
{
"fixup_TOY_CALL"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_TOY_BR"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static void ix86_test_loading_dump_fragment_1 ( ) { rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "x86_64/copy-hard-reg-into-frame.rtl" ) ) ; rtx_insn * insn = get_insn_by_uid ( 1 ) ; tree mem_expr ; { rtx pat = PATTERN ( insn ) ; ASSERT_EQ ( SET , GET_CODE ( pat ) ) ; { rtx dest = SET_DEST ( pat ) ; ASSERT_EQ ( MEM , GET_CODE ( dest ) ) ; ASSERT_TRUE ( RTX_FLAG ( dest , call ) ) ; ASSERT_EQ ( SImode , GET_MODE ( dest ) ) ; { rtx addr = XEXP ( dest , 0 ) ; ASSERT_EQ ( PLUS , GET_CODE ( addr ) ) ; ASSERT_EQ ( DImode , GET_MODE ( addr ) ) ; { rtx lhs = XEXP ( addr , 0 ) ; ASSERT_RTX_PTR_EQ ( frame_pointer_rtx , lhs ) ; } { rtx rhs = XEXP ( addr , 1 ) ; ASSERT_EQ ( CONST_INT , GET_CODE ( rhs ) ) ; ASSERT_EQ ( - 4 , INTVAL ( rhs ) ) ; } } ASSERT_EQ ( 1 , MEM_ALIAS_SET ( dest ) ) ; mem_expr = MEM_EXPR ( dest ) ; ASSERT_NE ( mem_expr , NULL ) ; ASSERT_EQ ( VAR_DECL , TREE_CODE ( mem_expr ) ) ; ASSERT_EQ ( integer_type_node , TREE_TYPE ( mem_expr ) ) ; ASSERT_EQ ( IDENTIFIER_NODE , TREE_CODE ( DECL_NAME ( mem_expr ) ) ) ; ASSERT_STREQ ( "i" , IDENTIFIER_POINTER ( DECL_NAME ( mem_expr ) ) ) ; ASSERT_TRUE ( MEM_OFFSET_KNOWN_P ( dest ) ) ; ASSERT_EQ ( 0 , MEM_OFFSET ( dest ) ) ; ASSERT_EQ ( 4 , MEM_SIZE ( dest ) ) ; ASSERT_EQ ( 32 , MEM_ALIGN ( dest ) ) ; } { rtx src = SET_SRC ( pat ) ; ASSERT_EQ ( REG , GET_CODE ( src ) ) ; ASSERT_EQ ( SImode , GET_MODE ( src ) ) ; ASSERT_EQ ( 5 , REGNO ( src ) ) ; tree reg_expr = REG_EXPR ( src ) ; ASSERT_EQ ( reg_expr , mem_expr ) ; } } } </s>

Verify loading an RTL dump ; specifically a dump of copying a param on x86_64 from a hard reg into the frame . This test is target-specific since the dump contains target-specific hard reg names .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr & MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp , LiveVariables * LV ) const { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI . getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ; switch ( LQR ) { case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI . killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; if ( LV ) LV -> replaceKillInstruction ( SrcReg , MI , * Copy ) ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> const X86Subtarget * getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> bool X86LowerTileCopy :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; const X86InstrInfo * TII = ST . getInstrInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { if ( ! MI . isCopy ( ) ) continue ; MachineOperand & DstMO = MI . getOperand ( 0 ) ; MachineOperand & SrcMO = MI . getOperand ( 1 ) ; Register SrcReg = SrcMO . getReg ( ) ; Register DstReg = DstMO . getReg ( ) ; if ( ! X86 :: TILERegClass . contains ( DstReg , SrcReg ) ) continue ; const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; unsigned Size = TRI -> getSpillSize ( X86 :: TILERegClass ) ; Align Alignment = TRI -> getSpillAlign ( X86 :: TILERegClass ) ; int TileSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Size = TRI -> getSpillSize ( X86 :: GR64RegClass ) ; Alignment = TRI -> getSpillAlign ( X86 :: GR64RegClass ) ; int StrideSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Register GR64Cand = X86 :: RAX ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , TII -> get ( X86 :: IMPLICIT_DEF ) , GR64Cand ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64mr ) ) , StrideSS ) . addReg ( GR64Cand ) ; BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64ri ) , GR64Cand ) . addImm ( 64 ) ; unsigned Opc = X86 :: TILESTORED ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) ) , TileSS ) . addReg ( SrcReg , getKillRegState ( SrcMO . isKill ( ) ) ) ; MachineOperand & MO = NewMI -> getOperand ( 2 ) ; MO . setReg ( GR64Cand ) ; MO . setIsKill ( true ) ; Opc = X86 :: TILELOADD ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) , DstReg ) , TileSS ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64rm ) , GR64Cand ) , StrideSS ) ; MI . eraseFromParent ( ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> inline set_of_reg sh_find_set_of_reg ( rtx reg , rtx_insn * insn , F stepfunc , bool ignore_reg_reg_copies = false ) { set_of_reg result ; result . insn = insn ; result . set_rtx = NULL_RTX ; result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; rtx_insn * previnsn = insn ; for ( result . insn = stepfunc ( insn ) ; result . insn != NULL_RTX ; previnsn = result . insn , result . insn = stepfunc ( result . insn ) ) { if ( BARRIER_P ( result . insn ) ) break ; if ( ! NONJUMP_INSN_P ( result . insn ) ) continue ; if ( reg_set_p ( reg , result . insn ) ) { result . set_rtx = set_of ( reg , result . insn ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , 1 ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) { reg = SUBREG_REG ( result . set_src ) ; continue ; } break ; } } if ( result . insn == NULL ) result . insn = previnsn ; if ( result . set_src != NULL ) gcc_assert ( result . insn != NULL && result . set_rtx != NULL ) ; return result ; } </s>

Given a reg rtx and a start insn , try to find the insn that sets the specified reg by using the specified insn stepping function , such as 'prev_nonnote_insn_bb ' . When the insn is found , try to extract the rtx of the reg set .


<s> void SICFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SICFunctionInfo * SICFI = MF . getInfo < SICFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) setAliasRegs ( MF , SavedRegs , SIC :: L ) ; return ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


Function to tell the preprocessor about the defines for the current target .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) || MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> MCFragment * MINA32MCExpr :: findAssociatedFragment ( ) const { return Expr -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static inline void aarch64_add_sp ( int scratchreg , HOST_WIDE_INT delta , bool emit_move_imm ) { aarch64_add_constant_internal ( Pmode , SP_REGNUM , scratchreg , delta , true , emit_move_imm ) ; } </s>

Add DELTA to the stack pointer , marking the instructions frame-related . TEMP1 is available as a temporary if nonnull . EMIT_MOVE_IMM is false if TEMP1 already contains abs ( DELTA ) .


<s> unsigned getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

DLX ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


<s> bool CAHPAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetELF ( ) || Subtarget -> isTargetCygMing ( ) ) { AU . addRequired < MachineModuleInfo > ( ) ; } AU . addRequired < DwarfWriter > ( ) ; AsmPrinter :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool ix86_vector_mode_supported_p ( enum machine_mode mode ) { if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) return true ; if ( TARGET_MMX && VALID_MMX_REG_MODE ( mode ) ) return true ; if ( TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW ( mode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { if ( ST -> getCPUDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , SE , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> TargetLoweringBase :: LegalizeTypeAction AArch64TargetLowering :: getPreferredVectorAction ( EVT VT ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( SVT == MVT :: v1i8 || SVT == MVT :: v1i16 || SVT == MVT :: v1i32 || SVT == MVT :: v1f32 ) return TypeWidenVector ; if ( VT . isScalableVector ( ) && ( VT . getVectorNumElements ( ) == 1 ) ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static void paired_emit_vector_compare ( enum rtx_code rcode , rtx dest , rtx op0 , rtx op1 , rtx cc_op0 , rtx cc_op1 ) { rtx tmp = gen_reg_rtx ( V2SFmode ) ; rtx tmp1 , max , min ; gcc_assert ( TARGET_PAIRED_FLOAT ) ; gcc_assert ( GET_MODE ( op0 ) == GET_MODE ( op1 ) ) ; switch ( rcode ) { case LT : case LTU : paired_emit_vector_compare ( GE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case GE : case GEU : emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case LE : case LEU : paired_emit_vector_compare ( GE , dest , op0 , op1 , cc_op1 , cc_op0 ) ; return ; case GT : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case EQ : tmp1 = gen_reg_rtx ( V2SFmode ) ; max = gen_reg_rtx ( V2SFmode ) ; min = gen_reg_rtx ( V2SFmode ) ; gen_reg_rtx ( V2SFmode ) ; emit_insn ( gen_subv2sf3 ( tmp , cc_op0 , cc_op1 ) ) ; emit_insn ( gen_selv2sf4 ( max , tmp , cc_op0 , cc_op1 , CONST0_RTX ( SFmode ) ) ) ; emit_insn ( gen_subv2sf3 ( tmp , cc_op1 , cc_op0 ) ) ; emit_insn ( gen_selv2sf4 ( min , tmp , cc_op0 , cc_op1 , CONST0_RTX ( SFmode ) ) ) ; emit_insn ( gen_subv2sf3 ( tmp1 , min , max ) ) ; emit_insn ( gen_selv2sf4 ( dest , tmp1 , op0 , op1 , CONST0_RTX ( SFmode ) ) ) ; return ; case NE : paired_emit_vector_compare ( EQ , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNLE : paired_emit_vector_compare ( LE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNLT : paired_emit_vector_compare ( LT , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNGE : paired_emit_vector_compare ( GE , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; case UNGT : paired_emit_vector_compare ( GT , dest , op1 , op0 , cc_op0 , cc_op1 ) ; return ; default : gcc_unreachable ( ) ; } return ; } </s>

Emit vector compare for code RCODE . DEST is destination , OP1 and OP2 are two VEC_COND_EXPR operands , CC_OP0 and CC_OP1 are the two operands for the relation operation COND . This is a recursive function .


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_74KC : case PROCESSOR_74KF2_1 : case PROCESSOR_74KF1_1 : case PROCESSOR_74KF3_2 : case PROCESSOR_R10000 : return 4 ; case PROCESSOR_20KC : case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R5900 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : case PROCESSOR_OCTEON : case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : case PROCESSOR_I6400 : case PROCESSOR_GS264E : return 2 ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return 3 ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_GS464 : case PROCESSOR_GS464E : case PROCESSOR_P5600 : case PROCESSOR_P6600 : return 4 ; case PROCESSOR_XLP : return ( reload_completed ? 4 : 3 ) ; default : return 1 ; } } </s>

Return the number of instructions that can be issued per cycle .


<s> static int arm_get_strip_length ( char c ) { switch ( c ) { ARM_NAME_ENCODING_LENGTHS default : return 0 ; } } </s>

Return the length of a function name prefix that starts with the character ' c ' .


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool isMultiStoresCheaperThanBitsMerge ( EVT LTy , EVT HTy ) const override { if ( ( LTy . isFloatingPoint ( ) && HTy . isInteger ( ) ) || ( LTy . isInteger ( ) && HTy . isFloatingPoint ( ) ) ) return true ; return false ; } </s>

Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores .


"SVE requires vector length in multiples of 128!"

"Minimum SVE vector size should not be larger than its maximum!"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> Cpu0TargetLowering :: ConstraintType Cpu0TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'c' : return C_RegisterClass ; case 'R' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool aarch64_is_extend_from_extract ( scalar_int_mode mode , rtx mult_imm , rtx extract_imm ) { HOST_WIDE_INT mult_val , extract_val ; if ( ! CONST_INT_P ( mult_imm ) || ! CONST_INT_P ( extract_imm ) ) return false ; mult_val = INTVAL ( mult_imm ) ; extract_val = INTVAL ( extract_imm ) ; if ( extract_val > 8 && extract_val < GET_MODE_BITSIZE ( mode ) && exact_log2 ( extract_val & ~ 7 ) > 0 && ( extract_val & 7 ) <= 4 && mult_val == ( 1 << ( extract_val & 7 ) ) ) return true ; return false ; } </s>

Return true if the offsets to a zero/sign-extract operation represent an expression that matches an extend operation . The operands represent the paramters from ( extract : MODE ( mult ( reg ) ( MULT_IMM ) ) ( EXTRACT_IMM ) ( const_int 0 ) ) .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( Subtarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( ! Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; Register TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { MF -> getInfo < PPCFunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC MVT::i32 PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> bool X86TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool X86TargetLowering :: shouldUseStrictFP_TO_INT ( EVT FpVT , EVT IntVT , bool IsSigned ) const { return ! IsSigned && FpVT == MVT :: f80 && Subtarget . hasCMov ( ) ; } </s>

Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value .


<s> void AArch64TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; if ( Res . getNode ( ) ) for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , ARMArch ( ARMv4t ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> static rtx altivec_expand_vec_ext_builtin ( tree exp , rtx target ) { machine_mode tmode , mode0 ; tree arg0 , arg1 ; int elt ; rtx op0 ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_extract ( target , op0 , elt ) ; return target ; } </s>


<s> static enum insn_path get_insn_path ( rtx_insn * insn ) { enum attr_amdfam10_decode path = get_attr_amdfam10_decode ( insn ) ; if ( ( int ) path == 0 ) return path_single ; if ( ( int ) path == 1 ) return path_double ; return path_multi ; } </s>

Return single or double path for instructions .


<s>
static
void
rs6000_output_savres_externs
(
FILE
*
file
)
{
rs6000_stack_t
*
info
=
rs6000_stack_info
(
)
;
if
(
TARGET_DEBUG_STACK
)
debug_stack_info
(
info
)
;
if
(
info
->
first_fp_reg_save
<
64
&&
!
TARGET_MACHO
&&
!
TARGET_ELF
)
{
char
*
name
;
int
regno
=
info
->
first_fp_reg_save
32
;
if
(
(
info
->
savres_strategy
&
SAVE_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
SAVE_NOINLINE_FPRS_SAVES_LR
)
!=
0
;
int
sel
=
SAVRES_SAVE
|
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
if
(
(
info
->
savres_strategy
&
REST_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
)
==
0
;
int
sel
=
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
}
}
</s>

Output .extern statements for the save/restore routines we use .


<s> bool X86InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; bool isWin64 = TM . getSubtarget < X86Subtarget > ( ) . isTargetWin64 ( ) ; unsigned SlotSize = is64Bit ? 8 : 4 ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned FPReg = RI . getFrameRegister ( MF ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned Opc = is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i - 1 ] . getRegClass ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( RegClass != & X86 :: VR128RegClass && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RegClass ) ; } } X86FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


"ARM Loops: Failed to find all loop components.\n"

Dump the plan to stderr ( for debugging ) .


<s> static int sh_symbian_get_strip_length ( int c ) { return ( c == SH_SYMBIAN_FLAG_CHAR [ 0 ] ) ? strlen ( DLL_EXPORT_PREFIX ) : 0 ; } </s>

Return the length of a function name prefix that starts with the character ' c ' .


<s> bool X86TargetLowering :: isFsqrtCheap ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . getScalarType ( ) == MVT :: f16 ) return true ; if ( DAG . doesNodeExist ( X86ISD :: FRSQRT , DAG . getVTList ( VT ) , Op ) ) return false ; if ( VT . isVector ( ) ) return Subtarget . hasFastVectorFSQRT ( ) ; return Subtarget . hasFastScalarFSQRT ( ) ; } </s>

Return true if SQRT ( X ) should n't be replaced with X * RSQRT ( X ) .


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_OR : return AArch64 :: ORRWrr ; case TargetOpcode :: G_XOR : return AArch64 :: EORWrr ; case TargetOpcode :: G_AND : return AArch64 :: ANDWrr ; case TargetOpcode :: G_ADD : return AArch64 :: ADDWrr ; case TargetOpcode :: G_SUB : return AArch64 :: SUBWrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_OR : return AArch64 :: ORRXrr ; case TargetOpcode :: G_XOR : return AArch64 :: EORXrr ; case TargetOpcode :: G_AND : return AArch64 :: ANDXrr ; case TargetOpcode :: G_ADD : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SUB : return AArch64 :: SUBXrr ; default : return GenericOpc ; } } } ; return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> std :: pair < unsigned , unsigned > ARMInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { const unsigned Mask = ARMII :: MO_OPTION_MASK ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> static int mips_small_data_pattern_1 ( rtx x , enum mips_symbol_context context ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , ALL ) { rtx x = * iter ; if ( GET_CODE ( x ) == LO_SUM || GET_CODE ( x ) == ASM_OPERANDS ) iter . skip_subrtxes ( ) ; else if ( MEM_P ( x ) ) { if ( mips_small_data_pattern_1 ( XEXP ( x , 0 ) , SYMBOL_CONTEXT_MEM ) ) return true ; iter . skip_subrtxes ( ) ; } else if ( mips_rewrite_small_data_p ( x , context ) ) return true ; } return false ; } </s>

A for_each_rtx callback for mips_small_data_pattern_p .


<s>
const
uint32_t
*
LoongArchRegisterInfo
::
getCallPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
CC
)
const
{
auto
&
Subtarget
=
MF
.
getSubtarget
<
LoongArchSubtarget
>
(
)
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
LoongArchABI
::
ABI_ILP32S
:
case
LoongArchABI
::
ABI_LP64S
:
return
CSR_ILP32S_LP64S_RegMask
;
case
LoongArchABI
::
ABI_ILP32F
:
case
LoongArchABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_RegMask
;
case
LoongArchABI
::
ABI_ILP32D
:
case
LoongArchABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."

"PRINT_OPERAND_ADDRESS, invalid insn #2"

"PRINT_OPERAND_ADDRESS, invalid insn #1"

A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR . ADDR is an RTL expression .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
CallLowering
*
AArch64Subtarget
::
getCallLowering
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getCallLowering
(
)
;
}
</s>


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV16_rm : case X86 :: MOV32rm : case X86 :: MOV32_rm : case X86 :: MOV64rm : case X86 :: LD_Fp64m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MOVAPSrm : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 4 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 1 && MI -> getOperand ( 3 ) . getReg ( ) == 0 && MI -> getOperand ( 4 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static std :: unique_ptr < SparcOperand > CreateReg ( unsigned RegNum , unsigned Kind , SMLoc S , SMLoc E ) { auto Op = make_unique < SparcOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = ( SparcOperand :: RegisterKind ) Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .

Sparc Sparc Sparc SparcOperand::RegisterKind


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> int SystemZTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( BitSize > 64 ) return TTI :: TCC_Free ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( ( Imm . getZExtValue ( ) & 0xffffffff ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { if ( ST -> getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; } BaseT :: getUnrollingPreferences ( L , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static void mips_init_builtins ( void ) { const struct mips_builtin_description * d ; unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_builtins ) ; i ++ ) { d = & mips_builtins [ i ] ; if ( d -> avail ( ) ) mips_builtin_decls [ i ] = add_builtin_function ( d -> name , mips_build_function_type ( d -> function_type ) , i , BUILT_IN_MD , NULL , NULL ) ; } } </s>

Init builtin functions . This is called from TARGET_INIT_BUILTIN .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: R2 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! EnableRegisterScavenging ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"PPC hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> static void arm_option_params_internal ( void ) { if ( TARGET_THUMB1 ) { targetm . min_anchor_offset = 0 ; targetm . max_anchor_offset = 127 ; } else if ( TARGET_THUMB2 ) { targetm . min_anchor_offset = - 248 ; targetm . max_anchor_offset = 4095 ; } else { targetm . min_anchor_offset = TARGET_MIN_ANCHOR_OFFSET ; targetm . max_anchor_offset = TARGET_MAX_ANCHOR_OFFSET ; } max_insns_skipped = optimize_size ? 4 : current_tune -> max_insns_skipped ; if ( TARGET_THUMB2 ) max_insns_skipped = MIN ( max_insns_skipped , MAX_INSN_PER_IT_BLOCK ) ; } </s>

Recompute the global settings depending on target attribute options .


<s> SDValue SparcTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { if ( Subtarget -> is64Bit ( ) ) return LowerReturn_64 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; return LowerReturn_32 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void MipsRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; if ( MFI -> hasCalls ( ) && isPIC ) { MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MFI -> setObjectOffset ( MipsFI -> getGPFI ( ) , MipsFI -> getGPStackOffset ( ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


Output at end of assembler file . On the RS/6000 , referencing data should automatically pull in text .


<s>
StringRef
getPassName
(
)
const
override
{
return
"CAHP Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
add
(
HOST_WIDE_INT
val
)
{
asm_fprintf
(
t_file
,
"\tadds\t%s, #"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
dst_regname
,
val
)
;
}
</s>

Make function pointers for the various linear operators we can apply to compute a multiplicative value .


<s> static bool rs6000_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { bool testing_p = ! target ; if ( TARGET_ALTIVEC && testing_p ) return true ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; if ( ( vmode == V2DFmode || vmode == V2DImode ) && VECTOR_MEM_VSX_P ( vmode ) ) { if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 1 ) ; op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 2 ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ 0 ] , sel [ 1 ] ) ) return true ; } if ( TARGET_ALTIVEC ) { if ( vmode != V16QImode ) return false ; if ( altivec_expand_vec_perm_const ( target , op0 , op1 , sel ) ) return true ; } return false ; } </s>


<s> static section * aarch64_select_rtx_section ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { return function_section ( current_function_decl ) ; } </s>

Select appropriate section for constants depending on where we place literal pools .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
LC3
::
NumTargetFixupKinds
]
=
{
{
"fixup_lc3_mov_hi16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_lc3_mov_lo16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
{
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
Register
DstReg
,
ArrayRef
<
MachineOperand
>
Cond
,
Register
TrueReg
,
Register
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterInfo
&
TRI
=
*
MRI
.
getTargetRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
X86
::
getCMovOpcode
(
TRI
.
getRegSizeInBits
(
RC
)
/
8
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
Cond
[
0
]
.
getImm
(
)
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , const TargetInstrInfo & TII ) { unsigned Opc ; uint64_t Chunk ; bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; if ( Offset >= ( 1LL << 15 ) - 1 ) { Opc = SystemZ :: ADD64ri32 ; Chunk = ( 1LL << 31 ) - 1 ; } else { Opc = SystemZ :: ADD64ri16 ; Chunk = ( 1LL << 15 ) - 1 ; } DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , SystemZ :: R15D ) . addReg ( SystemZ :: R15D ) . addImm ( isSub ? - ThisVal : ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> bool ix86_standard_x87sse_constant_load_p ( const rtx_insn * insn , rtx dst ) { rtx src = find_constant_src ( insn ) ; gcc_assert ( REG_P ( dst ) ) ; if ( src == NULL || ( SSE_REGNO_P ( REGNO ( dst ) ) && standard_sse_constant_p ( src , GET_MODE ( dst ) ) != 1 ) || ( STACK_REGNO_P ( REGNO ( dst ) ) && standard_80387_constant_p ( src ) < 1 ) ) return false ; return true ; } </s>

Returns true if INSN can be transformed from a memory load to a supported FP constant load .


<s>
SUnit
*
SystemZPostRASchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
IsTopNode
=
true
;
if
(
Available
.
empty
(
)
)
return
nullptr
;
if
(
Available
.
size
(
)
==
1
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Only one: "
;
HazardRec
.
dumpSU
(
*
Available
.
begin
(
)
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
return
*
Available
.
begin
(
)
;
}
DEBUG
(
dbgs
(
)
<<
"+++ Available: "
;
Available
.
dump
(
HazardRec
)
;
)
;
Candidate
Best
;
for
(
auto
*
SU
:
Available
)
{
Candidate
c
(
SU
,
HazardRec
)
;
if
(
Best
.
SU
==
nullptr
||
c
<
Best
)
{
Best
=
c
;
DEBUG
(
dbgs
(
)
<<
"+++ Best sofar: "
;
HazardRec
.
dumpSU
(
Best
.
SU
,
dbgs
(
)
)
;
if
(
Best
.
GroupingCost
!=
0
)
dbgs
(
)
<<
"\tGrouping cost:"
<<
Best
.
GroupingCost
;
if
(
Best
.
ResourcesCost
!=
0
)
dbgs
(
)
<<
" Resource cost:"
<<
Best
.
ResourcesCost
;
dbgs
(
)
<<
" Height:"
<<
Best
.
SU
->
getHeight
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
}
if
(
!
SU
->
isScheduleHigh
&&
Best
.
noCost
(
)
)
break
;
}
assert
(
Best
.
SU
!=
nullptr
)
;
return
Best
.
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

SystemZ
SystemZ
1
"+++ Only one: "
"\n"
"+++ Available: "
"+++ Best sofar: "
0
"\tGrouping cost:"
0
" Resource cost:"
" Height:"
"\n"


<s> bool XNCMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? STI . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s>
static
const
char
*
shift_op
(
rtx
op
,
HOST_WIDE_INT
*
amountp
)
{
const
char
*
mnem
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
switch
(
code
)
{
case
ROTATE
:
if
(
!
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
code
=
ROTATERT
;
*
amountp
=
32
INTVAL
(
XEXP
(
op
,
1
)
)
;
mnem
=
"ror"
;
break
;
case
ASHIFT
:
case
ASHIFTRT
:
case
LSHIFTRT
:
case
ROTATERT
:
mnem
=
arm_shift_nmem
(
code
)
;
if
(
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
*
amountp
=
INTVAL
(
XEXP
(
op
,
1
)
)
;
}
else
if
(
REG_P
(
XEXP
(
op
,
1
)
)
)
{
*
amountp
=
1
;
return
mnem
;
}
else
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
break
;
case
MULT
:
if
(
!
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
*
amountp
=
INTVAL
(
XEXP
(
op
,
1
)
)
&
0xFFFFFFFF
;
if
(
*
amountp
&
(
*
amountp
1
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
*
amountp
=
int_log2
(
*
amountp
)
;
return
ARM_LSL_NAME
;
default
:
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
if
(
code
==
ROTATERT
)
*
amountp
&=
31
;
else
if
(
*
amountp
!=
(
*
amountp
&
31
)
)
{
if
(
code
==
ASHIFT
)
mnem
=
"lsr"
;
*
amountp
=
32
;
}
if
(
*
amountp
==
0
)
return
;
return
mnem
;
}
</s>

Ensure valid constant shifts and return the appropriate shift mnemonic for the operation code . The returned result should not be overwritten . OP is the rtx code of the shift . On exit , * AMOUNTP will be -1 if the shift is by a register , or a constant shift .


"All AArch64 cmps should have 2 operands"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static opt_machine_mode aarch64_vectorize_related_mode ( machine_mode vector_mode , scalar_mode element_mode , poly_uint64 nunits ) { unsigned int vec_flags = aarch64_classify_vector_mode ( vector_mode ) ; poly_uint64 sve_nunits ; if ( ( vec_flags & VEC_SVE_DATA ) && multiple_p ( BYTES_PER_SVE_VECTOR , GET_MODE_SIZE ( element_mode ) , & sve_nunits ) ) { machine_mode sve_mode ; if ( maybe_ne ( nunits , 0U ) ) { if ( multiple_p ( sve_nunits , nunits ) && aarch64_sve_data_mode ( element_mode , nunits ) . exists ( & sve_mode ) ) return sve_mode ; } else { sve_nunits = ordered_min ( sve_nunits , GET_MODE_SIZE ( vector_mode ) ) ; if ( aarch64_sve_data_mode ( element_mode , sve_nunits ) . exists ( & sve_mode ) ) return sve_mode ; } } if ( ( vec_flags & VEC_ADVSIMD ) && known_eq ( nunits , 0U ) && known_eq ( GET_MODE_BITSIZE ( vector_mode ) , 64U ) && maybe_ge ( GET_MODE_BITSIZE ( element_mode ) * GET_MODE_NUNITS ( vector_mode ) , 128U ) ) { machine_mode res = aarch64_simd_container_mode ( element_mode , 128 ) ; if ( VECTOR_MODE_P ( res ) ) return res ; } return default_vectorize_related_mode ( vector_mode , element_mode , nunits ) ; } </s>


<s> bool ARMPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> static rtx aarch64_gen_load_pair ( machine_mode mode , rtx reg1 , rtx mem1 , rtx reg2 , rtx mem2 ) { switch ( mode ) { case E_DImode : return gen_load_pair_dw_didi ( reg1 , mem1 , reg2 , mem2 ) ; case E_DFmode : return gen_load_pair_dw_dfdf ( reg1 , mem1 , reg2 , mem2 ) ; case E_TFmode : return gen_load_pair_dw_tftf ( reg1 , mem1 , reg2 , mem2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and regurn a load pair isntruction of mode MODE to load register REG1 from MEM1 and register REG2 from MEM2 .


"%qs attribute only applies to functions"

"%qs attribute argument not a string constant"

Handle an `` sp_switch '' attribute ; arguments as in struct attribute_spec.handler .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
FeatureBitset
MissingFeatures
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
MissingFeatures
.
any
(
)
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
for
(
unsigned
I
=
0
,
E
=
MissingFeatures
.
size
(
)
;
I
!=
E
;
++
I
)
{
if
(
MissingFeatures
[
I
]
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
I
)
;
}
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
SystemZMnemonicSpellCheck
(
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

SystemZ
SystemZ
"Unknown missing feature!"
"instruction requires:"
0
" "
0ULL
"too few operands for instruction"
SystemZ
"invalid operand for instruction"
SystemZ
SystemZ
0
"invalid instruction"
SystemZ
0
"Unexpected match type"


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> void function_expander :: rotate_inputs_left ( unsigned int start , unsigned int end ) { rtx new_last = args [ start ] ; for ( unsigned int i = start ; i < end - 1 ; ++ i ) args [ i ] = args [ i + 1 ] ; args [ end - 1 ] = new_last ; } </s>

Rotate inputs args [ START : END ] one position to the left , so that args [ START ] becomes args [ END - 1 ] .


"Should be loading %r15 and something else"


<s> static rtx_insn * mips_call_tls_get_addr ( rtx sym , enum mips_symbol_type type , rtx v0 ) { rtx loc , a0 ; rtx_insn * insn ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Return an instruction sequence that calls __tls_get_addr . SYM is the TLS symbol we are referencing and TYPE is the symbol type to use ( either global dynamic or local dynamic ) . V0 is an RTX for the return value location .


<s>
SDValue
CJGTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_CJG
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
CJGISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void aarch64_override_options_after_change ( void ) { aarch64_override_options_after_change_1 ( & global_options ) ; } </s>


"sret virtual register not created in the entry block"


<s>
static
tree
rs6000_mangle_decl_assembler_name
(
tree
decl
,
tree
id
)
{
if
(
TARGET_FLOAT128_TYPE
&&
TARGET_IEEEQUAD
&&
TARGET_LONG_DOUBLE_128
&&
TREE_CODE
(
decl
)
==
FUNCTION_DECL
&&
DECL_IS_UNDECLARED_BUILTIN
(
decl
)
&&
DECL_BUILT_IN_CLASS
(
decl
)
==
BUILT_IN_NORMAL
)
{
size_t
len
=
IDENTIFIER_LENGTH
(
id
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
id
)
;
char
*
newname
=
;
switch
(
DECL_FUNCTION_CODE
(
decl
)
)
{
case
BUILT_IN_DREML
:
newname
=
xstrdup
(
"__remainderieee128"
)
;
break
;
case
BUILT_IN_GAMMAL
:
newname
=
xstrdup
(
"__lgammaieee128"
)
;
break
;
case
BUILT_IN_GAMMAL_R
:
case
BUILT_IN_LGAMMAL_R
:
newname
=
xstrdup
(
"__lgammaieee128_r"
)
;
break
;
case
BUILT_IN_NEXTTOWARD
:
newname
=
xstrdup
(
"__nexttoward_to_ieee128"
)
;
break
;
case
BUILT_IN_NEXTTOWARDF
:
newname
=
xstrdup
(
"__nexttowardf_to_ieee128"
)
;
break
;
case
BUILT_IN_NEXTTOWARDL
:
newname
=
xstrdup
(
"__nexttowardieee128"
)
;
break
;
case
BUILT_IN_POW10L
:
newname
=
xstrdup
(
"__exp10ieee128"
)
;
break
;
case
BUILT_IN_SCALBL
:
newname
=
xstrdup
(
"__scalbieee128"
)
;
break
;
case
BUILT_IN_SIGNIFICANDL
:
newname
=
xstrdup
(
"__significandieee128"
)
;
break
;
case
BUILT_IN_SINCOSL
:
newname
=
xstrdup
(
"__sincosieee128"
)
;
break
;
default
:
break
;
}
if
(
!
newname
)
{
size_t
printf_len
=
strlen
(
"printf"
)
;
size_t
scanf_len
=
strlen
(
"scanf"
)
;
size_t
printf_chk_len
=
strlen
(
"printf_chk"
)
;
if
(
len
>=
printf_len
&&
strcmp
(
name
+
len
printf_len
,
"printf"
)
==
0
)
newname
=
xasprintf
(
"__%sieee128"
,
name
)
;
else
if
(
len
>=
scanf_len
&&
strcmp
(
name
+
len
scanf_len
,
"scanf"
)
==
0
)
newname
=
xasprintf
(
"__isoc99_%sieee128"
,
name
)
;
else
if
(
len
>=
printf_chk_len
&&
strcmp
(
name
+
len
printf_chk_len
,
"printf_chk"
)
==
0
)
newname
=
xasprintf
(
"%sieee128"
,
name
)
;
else
if
(
name
[
len
1
]
==
'l'
)
{
bool
uses_ieee128_p
=
false
;
tree
type
=
TREE_TYPE
(
decl
)
;
machine_mode
ret_mode
=
TYPE_MODE
(
type
)
;
if
(
ret_mode
==
TFmode
||
ret_mode
==
TCmode
)
uses_ieee128_p
=
true
;
else
{
function_args_iterator
args_iter
;
tree
arg
;
FOREACH_FUNCTION_ARGS
(
type
,
arg
,
args_iter
)
{
machine_mode
arg_mode
=
TYPE_MODE
(
arg
)
;
if
(
arg_mode
==
TFmode
||
arg_mode
==
TCmode
)
{
uses_ieee128_p
=
true
;
break
;
}
}
}
if
(
uses_ieee128_p
)
newname
=
xasprintf
(
"__%.*sieee128"
,
(
int
)
(
len
1
)
,
name
)
;
}
}
if
(
newname
)
{
if
(
TARGET_DEBUG_BUILTIN
)
fprintf
(
stderr
,
"Map %s => %s\n"
,
name
,
newname
)
;
id
=
get_identifier
(
newname
)
;
free
(
newname
)
;
}
}
return
id
;
}
</s>

On 64-bit Linux and Freebsd systems , possibly switch the long double library function names from < foo > l to < foo > f128 if the default long double type is IEEE 128-bit . Typically , with the C and C++ languages , the standard math.h include file switches the names on systems that support long double as IEEE 128-bit , but that does n't work if the user uses __builtin_ < foo > l directly . In the future , glibc will export names like __ieee128_sinf128 and we can switch to using those instead of using sinf128 , which pollutes the user 's namespace . This will switch the names for Fortran math functions as well ( which does n't use math.h ) . However , Fortran needs other changes to the compiler and library before you can switch the real * 16 type at compile time . We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name . We only do this transformation if the __float128 type is enabled . This prevents us from doing the transformation on older 32-bit ports that might have enabled using IEEE 128-bit floating point as the default long double type . We also use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change the function names used for complex multiply and divide to the appropriate names .


<s> void xstormy16_expand_prologue ( ) { struct xstormy16_stack_layout layout ; int regno ; rtx insn ; rtx mem_push_rtx ; rtx mem_fake_push_rtx ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_push_rtx = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; mem_push_rtx = gen_rtx_MEM ( HImode , mem_push_rtx ) ; mem_fake_push_rtx = gen_rtx_PRE_INC ( Pmode , stack_pointer_rtx ) ; mem_fake_push_rtx = gen_rtx_MEM ( HImode , mem_fake_push_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . stdarg_save_size ) for ( regno = FIRST_ARGUMENT_REGISTER ; regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS ; regno ++ ) { rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem_fake_push_rtx , reg ) , REG_NOTES ( insn ) ) ; } for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem_fake_push_rtx , reg ) , REG_NOTES ( insn ) ) ; } if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) { insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( layout . locals_size ) { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( layout . locals_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( frame_pointer_needed && layout . sp_minus_fp != layout . locals_size ) { insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( layout . sp_minus_fp ) { insn = emit_addhi3_postreload ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - layout . sp_minus_fp ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } </s>

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling . Also any insns generated here should have RTX_FRAME_RELATED_P ( insn ) = 1 so that the debug info generation code can handle them properly .


<s> static void function_arg_record_value_3 ( HOST_WIDE_INT bitpos , struct function_arg_record_value_parms * parms ) { enum machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_slotno , intslots , intoffset ; rtx reg ; if ( parms -> intoffset == - 1 ) return ; intoffset = parms -> intoffset ; parms -> intoffset = - 1 ; startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intslots = ( endbit - startbit ) / BITS_PER_WORD ; this_slotno = parms -> slotno + intoffset / BITS_PER_WORD ; intslots = MIN ( intslots , SPARC_INT_ARG_MAX - this_slotno ) ; if ( intslots <= 0 ) return ; if ( intoffset % BITS_PER_WORD != 0 ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; intoffset /= BITS_PER_UNIT ; do { regno = parms -> regbase + this_slotno ; reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_slotno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; parms -> nregs += 1 ; intslots -= 1 ; } while ( intslots > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign the bits of the structure between parms- > intoffset and bitpos to integer registers .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } if ( EnableSpeculativeLoadHardening ) addPass ( createX86SpeculativeLoadHardeningPass ( ) ) ; addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool PPCInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { const TargetRegisterClass * RCs [ ] = { & PPC :: CRRCRegClass , & PPC :: CRBITRCRegClass , & PPC :: CTRRCRegClass , & PPC :: CTRRC8RegClass } ; bool Found = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { for ( unsigned c = 0 ; c < array_lengthof ( RCs ) && ! Found ; ++ c ) { const TargetRegisterClass * RC = RCs [ c ] ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && RC -> contains ( MO . getReg ( ) ) ) { Pred . push_back ( MO ) ; Found = true ; } } else if ( MO . isRegMask ( ) ) { for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , IE = RC -> end ( ) ; I != IE ; ++ I ) if ( MO . clobbersPhysReg ( * I ) ) { Pred . push_back ( MO ) ; Found = true ; } } } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

PowerPC PPC PPC::CRRCRegClass PPC::CRBITRCRegClass PPC::CTRRCRegClass PPC::CTRRC8RegClass 0


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; if ( isa < ScalableVectorType > ( Ty ) ) return AM . HasBaseReg && ! AM . BaseOffs && ! AM . Scale ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static bool arm_function_in_section_p ( tree decl , section * section ) { if ( ! decl_binds_to_current_def_p ( decl ) ) return false ; if ( ! DECL_SECTION_NAME ( decl ) ) { if ( flag_function_sections || DECL_COMDAT_GROUP ( decl ) ) return false ; } return function_section ( decl ) == section ; } </s>

Return true if DECL is known to be linked into section SECTION .


<s>
const
uint32_t
*
AArch64RegisterInfo
::
getThisReturnPreservedMask
(
const
MachineFunction
&
MF
,
CallingConv
::
ID
CC
)
const
{
assert
(
CC
!=
CallingConv
::
GHC
&&
"should not be GHC calling convention."
)
;
return
CSR_AArch64_AAPCS_ThisReturn_RegMask
;
}
</s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == Mips :: JALR_HB && ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> bool PPCRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return EnableRegisterScavenging ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> void ix86_print_patchable_function_entry ( FILE * file , unsigned HOST_WIDE_INT patch_area_size , bool record_p ) { if ( cfun -> machine -> function_label_emitted ) { return ; } default_print_patchable_function_entry ( file , patch_area_size , record_p ) ; } </s>


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
SDValue
LC2200TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
DAG
.
getMachineFunction
(
)
,
CCInfo
,
Outs
,
true
,
nullptr
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocVT
(
)
==
MVT
::
i32
&&
VA
.
getValVT
(
)
==
MVT
::
f64
)
{
llvm_unreachable
(
"not supported"
)
;
}
else
{
Val
=
convertValVTToLocVT
(
DAG
,
Val
,
VA
,
DL
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
{
RetOps
.
push_back
(
Glue
)
;
}
const
Function
&
Func
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
;
if
(
Func
.
hasFnAttribute
(
"interrupt"
)
)
{
llvm_unreachable
(
"interrupts not supported"
)
;
}
return
DAG
.
getNode
(
LC2200ISD
::
RET
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>


<s> static void ix86_dwarf_handle_frame_unspec ( const char * label , rtx pattern , int index ) { rtx unspec = SET_SRC ( pattern ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; switch ( index ) { case UNSPEC_REG_SAVE : dwarf2out_reg_save_reg ( label , XVECEXP ( unspec , 0 , 0 ) , SET_DEST ( pattern ) ) ; break ; case UNSPEC_DEF_CFA : dwarf2out_def_cfa ( label , REGNO ( SET_DEST ( pattern ) ) , INTVAL ( XVECEXP ( unspec , 0 , 0 ) ) ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook . This is called from dwarf2out.c to emit call frame instructions for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Sparc Sparc 0 SPISD::CMPICC "SPISD::CMPICC" SPISD::CMPFCC "SPISD::CMPFCC" SPISD::BRICC "SPISD::BRICC" SPISD::BRXCC "SPISD::BRXCC" SPISD::BRFCC "SPISD::BRFCC" SPISD::SELECT_ICC "SPISD::SELECT_ICC" SPISD::SELECT_XCC "SPISD::SELECT_XCC" SPISD::SELECT_FCC "SPISD::SELECT_FCC" SPISD::Hi "SPISD::Hi" SPISD::Lo "SPISD::Lo" SPISD::FTOI "SPISD::FTOI" SPISD::ITOF "SPISD::ITOF" SPISD::CALL "SPISD::CALL" SPISD::RET_FLAG "SPISD::RET_FLAG" SPISD::GLOBAL_BASE_REG "SPISD::GLOBAL_BASE_REG" SPISD::FLUSHW "SPISD::FLUSHW"


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LD ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LDC1 ) || ( Opc == Mips :: LDC164 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static inline bool rs6000_builtin_type_compatible ( tree t , int id ) { tree builtin_type ; builtin_type = rs6000_builtin_type ( id ) ; if ( t == error_mark_node ) return false ; if ( INTEGRAL_TYPE_P ( t ) && INTEGRAL_TYPE_P ( builtin_type ) ) return true ; else return lang_hooks . types_compatible_p ( t , builtin_type ) ; } </s>

Return true iff ARGTYPE can be compatibly passed as PARMTYPE .


<s> SDValue PPCTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { EVT VT = N -> getValueType ( 0 ) ; if ( VT == MVT :: i64 && ! Subtarget . isPPC64 ( ) ) return SDValue ( ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; bool IsNegPow2 = ( - Divisor ) . isPowerOf2 ( ) ; unsigned Lg2 = ( IsNegPow2 ? - Divisor : Divisor ) . countTrailingZeros ( ) ; SDValue ShiftAmt = DAG . getConstant ( Lg2 , DL , VT ) ; SDValue Op = DAG . getNode ( PPCISD :: SRA_ADDZE , DL , VT , N0 , ShiftAmt ) ; if ( Created ) Created -> push_back ( Op . getNode ( ) ) ; if ( IsNegPow2 ) { Op = DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , Op ) ; if ( Created ) Created -> push_back ( Op . getNode ( ) ) ; } return Op ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


"getBranchTarget26OpValue expects only expressions or immediates"

getBranchTarget26OpValue - Return binary encoding of the branch target operand .


<s> static void aarch64_emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; insn = emit_jump_insn ( insn ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s>
unsigned
MipsCodeEmitter
::
getJumpOffset16OpValue
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
llvm_unreachable
(
"Unimplemented function."
)
;
return
0
;
}
</s>

getJumpOffset16OpValue - Return binary encoding of the jump target operand .


<s> static unsigned arm_add_stmt_cost ( vec_info * vinfo , void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , tree vectype , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { int stmt_cost = arm_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( vinfo , stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vzipv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vzipv4hf_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static int noncall_uses_reg ( rtx reg , rtx insn , rtx * set ) { rtx pattern , reg2 ; * set = NULL_RTX ; reg2 = sfunc_uses_reg ( insn ) ; if ( reg2 && REGNO ( reg2 ) == REGNO ( reg ) ) { pattern = single_set ( insn ) ; if ( pattern && GET_CODE ( SET_DEST ( pattern ) ) == REG && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) * set = pattern ; return 0 ; } if ( GET_CODE ( insn ) != CALL_INSN ) { pattern = single_set ( insn ) ; if ( pattern && GET_CODE ( SET_DEST ( pattern ) ) == REG && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) { rtx par , part ; int i ; * set = pattern ; par = PATTERN ( insn ) ; if ( GET_CODE ( par ) == PARALLEL ) for ( i = XVECLEN ( par , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( par , 0 , i ) ; if ( GET_CODE ( part ) != SET && reg_mentioned_p ( reg , part ) ) return 1 ; } return reg_mentioned_p ( reg , SET_SRC ( pattern ) ) ; } return 1 ; } pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) { int i ; for ( i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) if ( reg_mentioned_p ( reg , XVECEXP ( pattern , 0 , i ) ) ) return 1 ; pattern = XVECEXP ( pattern , 0 , 0 ) ; } if ( GET_CODE ( pattern ) == SET ) { if ( reg_mentioned_p ( reg , SET_DEST ( pattern ) ) ) { if ( GET_CODE ( SET_DEST ( pattern ) ) != REG || REGNO ( reg ) != REGNO ( SET_DEST ( pattern ) ) ) return 1 ; * set = pattern ; } pattern = SET_SRC ( pattern ) ; } if ( GET_CODE ( pattern ) != CALL || GET_CODE ( XEXP ( pattern , 0 ) ) != MEM || ! rtx_equal_p ( reg , XEXP ( XEXP ( pattern , 0 ) , 0 ) ) ) return 1 ; return 0 ; } </s>

See if the only way in which INSN uses REG is by calling it , or by setting it while calling it . Set * SET to a SET rtx if the register is set by INSN .


<s> static reg_class_t sh_preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , reg_class_t rclass ) { return rclass ; } </s>


<s> bool AArch64RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg ) const { return ! isReservedReg ( MF , PhysReg ) ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s> bool emitSymbolAttribute ( MCSymbol * Symbol , MCSymbolAttr Attribute ) override { bool Val = MCELFStreamer :: emitSymbolAttribute ( Symbol , Attribute ) ; if ( ! IsThumb ) return Val ; unsigned Type = cast < MCSymbolELF > ( Symbol ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) && Symbol -> isDefined ( ) ) getAssembler ( ) . setIsThumbFunc ( Symbol ) ; return Val ; } </s>


<s> void LanaiAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned , uint64_t Value , bool , MCContext & ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool PPCFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT Evt = TLI . getValueType ( DL , Ty , true ) ; if ( Evt == MVT :: Other || ! Evt . isSimple ( ) ) return false ; VT = Evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> void func_fma_steering :: analyze ( ) { int i , n_blocks , * bb_dfs_preorder ; basic_block bb ; rtx_insn * insn ; bb_dfs_preorder = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n_blocks = pre_and_rev_post_order_compute ( bb_dfs_preorder , NULL , false ) ; for ( i = 0 ; i < n_blocks ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , bb_dfs_preorder [ i ] ) ; FOR_BB_INSNS ( bb , insn ) { operand_rr_info * dest_op_info ; struct du_chain * chain = NULL ; unsigned dest_regno ; fma_forest * forest = NULL ; du_head_p head = NULL ; int i ; if ( ! is_fmul_fmac_insn ( insn , true ) ) continue ; dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; dest_regno = REGNO ( SET_DEST ( PATTERN ( insn ) ) ) ; for ( i = 0 ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; forest = NULL ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * * fma_slot ; if ( ! is_fmul_fmac_insn ( chain -> insn , true ) ) continue ; if ( chain -> loc != & SET_DEST ( PATTERN ( chain -> insn ) ) ) continue ; if ( chain -> insn == insn ) break ; fma_slot = this -> m_insn_fma_head_map -> get ( chain -> insn ) ; if ( fma_slot && ( * fma_slot ) -> get_children ( ) ) forest = ( * fma_slot ) -> get_forest ( ) ; } if ( chain ) break ; } if ( i < dest_op_info -> n_chains ) this -> analyze_fma_fmul_insn ( forest , chain , head ) ; } } free ( bb_dfs_preorder ) ; if ( dump_file ) this -> dfs ( dump_forest_info , dump_tree_root_info , dump_tree_node_info , false ) ; } </s>

Count how many times each regno is referenced as base address for a memory access .


<s> bool ARMBaseInstrInfo :: isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const { return Subtarget . isProfitableToUnpredicate ( ) ; } </s>

Return true if it 's profitable to unpredicate one side of a 'diamond ' , i.e .


"without AVX512F enabled changes the ABI"

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


"Don't know how to handle that operation"


<s> static rtx promote_duplicated_reg_to_size ( rtx val , int size_needed , int desired_align , int align ) { rtx promoted_val ; if ( TARGET_64BIT && ( size_needed > 4 || ( desired_align > align && desired_align > 4 ) ) ) promoted_val = promote_duplicated_reg ( DImode , val ) ; else if ( size_needed > 2 || ( desired_align > align && desired_align > 2 ) ) promoted_val = promote_duplicated_reg ( SImode , val ) ; else if ( size_needed > 1 || ( desired_align > align && desired_align > 1 ) ) promoted_val = promote_duplicated_reg ( HImode , val ) ; else promoted_val = val ; return promoted_val ; } </s>

Duplicate value VAL using promote_duplicated_reg into maximal size that will be needed by main loop copying SIZE_NEEDED chunks and prologue getting alignment from ALIGN to DESIRED_ALIGN .


<s> void AArch64FrameLowering :: resetCFIToInitialState ( MachineBasicBlock & MBB ) const { MachineFunction & MF = * MBB . getParent ( ) ; const auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const auto & TRI = static_cast < const AArch64RegisterInfo & > ( * Subtarget . getRegisterInfo ( ) ) ; const auto & MFI = * MF . getInfo < AArch64FunctionInfo > ( ) ; const MCInstrDesc & CFIDesc = TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ; DebugLoc DL ; MachineBasicBlock :: iterator InsertPt = MBB . begin ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfa ( nullptr , TRI . getDwarfRegNum ( AArch64 :: SP , true ) , 0 ) ) ; BuildMI ( MBB , InsertPt , DL , CFIDesc ) . addCFIIndex ( CFIIndex ) ; if ( MFI . shouldSignReturnAddress ( ) ) { CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createNegateRAState ( nullptr ) ) ; BuildMI ( MBB , InsertPt , DL , CFIDesc ) . addCFIIndex ( CFIIndex ) ; } if ( needsShadowCallStackPrologueEpilogue ( MF ) ) insertCFISameValue ( CFIDesc , MF , MBB , InsertPt , TRI . getDwarfRegNum ( AArch64 :: X18 , true ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; for ( const auto & Info : CSI ) { unsigned Reg = Info . getReg ( ) ; if ( ! TRI . regNeedsCFI ( Reg , Reg ) ) continue ; insertCFISameValue ( CFIDesc , MF , MBB , InsertPt , TRI . getDwarfRegNum ( Reg , true ) ) ; } } </s>

Emit CFI instructions that recreate the state of the unwind information upon fucntion entry .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { switch ( ( VE :: Fixups ) Fixup . getKind ( ) ) { default : return false ; case VE :: fixup_ve_tls_gd_hi32 : case VE :: fixup_ve_tls_gd_lo32 : case VE :: fixup_ve_tpoff_hi32 : case VE :: fixup_ve_tpoff_lo32 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
case
k_RegPair
:
OS
<<
"RegPair<"
<<
RegIdx
.
Index
<<
","
<<
RegIdx
.
Index
+
1
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static void load_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx dest = gen_rtx_REG ( word_mode , reg ) ; rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx src ; if ( VAL_14_BITS_P ( disp ) ) src = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , basereg , disp ) ) ; else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; if ( TARGET_DISABLE_INDEXING ) { emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; src = gen_rtx_MEM ( word_mode , tmpreg ) ; } else src = gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; } else { rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , high ) ; src = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; } emit_move_insn ( dest , src ) ; } </s>

Emit RTL to load REG from the memory location specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns .


Return an array that contains the bitmask target flag values and their names .

ARM ARM ARM "arm-coffstub" "arm-got" "arm-sbrel" "arm-dllimport" "arm-secrel" "arm-nonlazy"


<s> static int arm_address_register_rtx_p ( rtx x , int strict_p ) { int regno ; if ( ! REG_P ( x ) ) return 0 ; regno = REGNO ( x ) ; if ( strict_p ) return ARM_REGNO_OK_FOR_BASE_P ( regno ) ; return ( regno <= LAST_ARM_REGNUM || regno >= FIRST_PSEUDO_REGISTER || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return nonzero if X is valid as an ARM state addressing register .


"expected larger existing stack allocation"

Target-specific cleanup for formal ByVal parameters .


<s> bool PPCTargetLowering :: SelectAddressPCRel ( SDValue N , SDValue & Base ) const { ConstantPoolSDNode * ConstPoolNode = dyn_cast < ConstantPoolSDNode > ( N . getNode ( ) ) ; bool HasFlag = ConstPoolNode && ConstPoolNode -> getTargetFlags ( ) == PPCII :: MO_PCREL_FLAG ; bool HasNode = N . getOpcode ( ) == PPCISD :: MAT_PCREL_ADDR ; if ( HasFlag || HasNode ) { Base = N ; return true ; } return false ; } </s>

SelectAddressPCRel - Represent the specified address as pc relative to be represented as [ pc+imm ] .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const TargetFrameLowering * TFI = STI . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; Reserved . set ( ARM :: APSR_NZCV ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void OR1KFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const OR1KRegisterInfo * TRI = static_cast < const OR1KRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool IsPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; int Offset = - 4 ; if ( MFI -> adjustsStack ( ) || IsPIC ) { MFI -> CreateFixedObject ( 4 , Offset , true ) ; SavedRegs . set ( OR1K :: R9 ) ; Offset -= 4 ; } if ( hasFP ( MF ) ) { MFI -> CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; } if ( TRI -> hasBasePointer ( MF ) ) { MFI -> CreateFixedObject ( 4 , Offset , true ) ; SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void UPTInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( UPT :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>