<s> void AArch64AsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( ! TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return ; unsigned Flags = 0 ; if ( const auto * BTE = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "branch-target-enforcement" ) ) ) if ( BTE -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ; if ( const auto * Sign = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "sign-return-address" ) ) ) if ( Sign -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_PAC ; if ( Flags == 0 ) return ; if ( auto * TS = static_cast < AArch64TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) TS -> emitNoteSection ( Flags ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . padShortFunctions ( ) ) { addPass ( createX86PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( createX86NaClRewritePass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"the layout of aggregates containing vectors with"

" %d-byte alignment has changed in GCC 5"

Previous GCC releases forced all vector types to have 16-byte alignment .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttr ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= 16 && ( Op . isAligned ( Align ( 16 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Op . size ( ) >= 8 && ( Op . isAligned ( Align ( 8 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; } addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static int hard_regs_intersect_p ( HARD_REG_SET * a , HARD_REG_SET * b ) { HARD_REG_SET c ; COPY_HARD_REG_SET ( c , * a ) ; AND_HARD_REG_SET ( c , * b ) ; GO_IF_HARD_REG_SUBSET ( c , reg_class_contents [ ( int ) NO_REGS ] , lose ) ; return 1 ; lose : return 0 ; } </s>

Determine if two hard register sets intersect . Return 1 if they do .


<s> static void store_reg_modify ( int base , int reg , HOST_WIDE_INT mod ) { rtx insn , basereg , srcreg , delta ; gcc_assert ( VAL_14_BITS_P ( mod ) ) ; basereg = gen_rtx_REG ( Pmode , base ) ; srcreg = gen_rtx_REG ( word_mode , reg ) ; delta = GEN_INT ( mod ) ; insn = emit_insn ( gen_post_store ( basereg , srcreg , delta ) ) ; if ( DO_FRAME_NOTES ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; } } </s>

Emit RTL to store REG at the memory location specified by BASE and then add MOD to BASE . MOD must be < = 8k .


<s> rtx aarch64_simd_vect_par_cnst_half ( machine_mode mode , int nunits , bool high ) { rtvec v = rtvec_alloc ( nunits / 2 ) ; int high_base = nunits / 2 ; int low_base = 0 ; int base ; rtx t1 ; int i ; if ( BYTES_BIG_ENDIAN ) base = high ? low_base : high_base ; else base = high ? high_base : low_base ; for ( i = 0 ; i < nunits / 2 ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( base + i ) ; t1 = gen_rtx_PARALLEL ( mode , v ) ; return t1 ; } </s>

Construct and return a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low ( HIGH == FALSE ) half of the vector - from the perspective of the architecture . This does not line up with GCC 's perspective on lane numbers , so we end up with different masks depending on our target endian-ness . The diagram below may help . We must draw the distinction when building masks which select one half of the vector . An instruction selecting architectural low-lanes for a big-endian target , must be described using a mask selecting GCC high-lanes . Big-Endian Little-EndianGCC 0 1 2 3 3 2 1 0 | x | x | x | x | | x | x | x | x |Architecture 3 2 1 0 3 2 1 0Low Mask : { 2 , 3 } { 0 , 1 } High Mask : { 0 , 1 } { 2 , 3 }


<s> int sparc_flat_epilogue_delay_slots ( ) { if ( ! current_frame_info . initialized ) ( void ) sparc_flat_compute_frame_size ( get_frame_size ( ) ) ; if ( current_frame_info . total_size == 0 ) return 1 ; return 0 ; } </s>

Define the number of delay slots needed for the function epilogue . On the sparc , we need a slot if either no stack has been allocated , or the only register saved is the return register .


<s> void buildLoad ( unsigned Val , const CCValAssign & VA ) { MachineMemOperand * MMO ; unsigned Addr = getStackAddress ( VA , MMO ) ; MIRBuilder . buildLoad ( Val , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


"Removing insn %d from candidates list\n"

For a given bitmap of insn UIDs scans all instructions and remove insn from CANDIDATES in case it has both convertible and not convertible definitions . All insns in a bitmap are conversion candidates according to scalar_to_vector_candidate_p . Currently it implies all insns are single_set .


<s> bool X86PassConfig :: addRegBankSelect ( ) { return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512RegClassID : if ( getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> static bool rs6000_slow_unaligned_access ( machine_mode mode , unsigned int align ) { return ( STRICT_ALIGNMENT || ( ! TARGET_EFFICIENT_UNALIGNED_VSX && ( ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && align < 32 ) || ( ( VECTOR_MODE_P ( mode ) || FLOAT128_VECTOR_P ( mode ) ) && ( int ) align < VECTOR_ALIGN ( mode ) ) ) ) ) ; } </s>

Implement TARGET_SLOW_UNALIGNED_ACCESS . Altivec vector memory instructions simply ignore the low bits ; VSX memory instructions are aligned to 4 or 8 bytes .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; MipsSubtarget const & STI = static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; const TargetRegisterClass * RC = STI . inMips16Mode ( ) ? & Mips :: CPU16RegsRegClass : STI . inMicroMipsMode ( ) ? & Mips :: GPRMM16RegClass : static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
static
void
pa_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
ASM_OUTPUT_LABEL
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
)
;
fputs
(
"\t.PROC\n"
,
file
)
;
fprintf
(
file
,
"\t.CALLINFO FRAME="
HOST_WIDE_INT_PRINT_DEC
,
actual_fsize
)
;
if
(
crtl
->
is_leaf
)
fputs
(
",NO_CALLS"
,
file
)
;
else
fputs
(
",CALLS"
,
file
)
;
if
(
rp_saved
)
fputs
(
",SAVE_RP"
,
file
)
;
if
(
frame_pointer_needed
)
fputs
(
",SAVE_SP"
,
file
)
;
if
(
gr_saved
)
fprintf
(
file
,
",ENTRY_GR=%d"
,
gr_saved
+
2
)
;
if
(
fr_saved
)
fprintf
(
file
,
",ENTRY_FR=%d"
,
fr_saved
+
11
)
;
fputs
(
"\n\t.ENTRY\n"
,
file
)
;
remove_useless_addtr_insns
(
0
)
;
}
</s>

On HP-PA , move-double insns between fpu and cpu need an 8-byte block of memory . If any fpu reg is used in the function , we allocate such a block here , at the bottom of the frame , just in case it 's needed . If this function is a leaf procedure , then we may choose not to do a `` save '' insn . The decision about whether or not to do this is made in regclass.c .


<s> rtx loongarch_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST . Assume that the move expanders can handle all moves if ! can_create_pseudo_p ( ) . The distinction is important because , unlike emit_move_insn , the move expanders know how to force Pmode objects into the constant pool even when the constant pool address is not itself legitimate .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isDFPImm ( ) ) { return static_cast < unsigned > ( bit_cast < double > ( MO . getDFPImm ( ) ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool sparc_can_use_return_insn_p ( void ) { return sparc_prologue_data_valid_p && ( actual_fsize == 0 || ! sparc_leaf_function_p ) ; } </s>

Return true if it is appropriate to emit ` return ' instructions in the body of a function .


<s> static tree rx_decl_for_addr ( rtx op ) { if ( GET_CODE ( op ) == MEM ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; while ( GET_CODE ( op ) == PLUS ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_DECL ( op ) ; return NULL_TREE ; } </s>

Find a SYMBOL_REF in a `` standard '' MEM address and return its decl .


<s> virtual void EmitInstruction ( const MCInst & Inst ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || flag_signed_zeros ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; if ( MEM_P ( if_true ) && MEM_P ( if_false ) ) if_true = force_reg ( mode , if_true ) ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"MOV to LEA transformation pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"%qE attribute only applies to variables"

"address region attributes not allowed with auto storage class"

"address region attributes on pointed-to types ignored"


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> void PPCPostRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand ) { PostGenericScheduler :: tryCandidate ( Cand , TryCand ) ; if ( ! Cand . isValid ( ) ) return ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return ; if ( biasAddiCandidate ( Cand , TryCand ) ) return ; } </s>

Apply a set of heuristics to a new candidate .


<s> bool x86_maybe_negate_const_int ( rtx * loc , machine_mode mode ) { HOST_WIDE_INT val ; if ( ! CONST_INT_P ( * loc ) ) return false ; switch ( mode ) { case DImode : gcc_assert ( x86_64_immediate_operand ( * loc , mode ) ) ; mode = SImode ; break ; case SImode : case HImode : case QImode : break ; default : gcc_unreachable ( ) ; } if ( mode_signbit_p ( mode , * loc ) ) return false ; val = INTVAL ( * loc ) ; if ( ( val < 0 && val != - 128 ) || val == 128 ) { * loc = GEN_INT ( - val ) ; return true ; } return false ; } </s>

If profitable , negate ( without causing overflow ) integer constant of mode MODE at location LOC . Return true in this case .


<s> int ix86_return_pops_args ( tree fundecl , tree funtype , int size ) { int rtd = TARGET_RTD && ( ! fundecl || TREE_CODE ( fundecl ) != IDENTIFIER_NODE ) ; if ( ! lookup_attribute ( "cdecl" , TYPE_ATTRIBUTES ( funtype ) ) ) { if ( lookup_attribute ( "stdcall" , TYPE_ATTRIBUTES ( funtype ) ) || lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( funtype ) ) ) rtd = 1 ; if ( rtd && ( TYPE_ARG_TYPES ( funtype ) == NULL_TREE || ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( funtype ) ) ) == void_type_node ) ) ) return size ; } if ( aggregate_value_p ( TREE_TYPE ( funtype ) , fundecl ) && ! TARGET_64BIT && ! KEEP_AGGREGATE_RETURN_POINTER ) { int nregs = ix86_function_regparm ( funtype , fundecl ) ; if ( ! nregs ) return GET_MODE_SIZE ( Pmode ) ; } return 0 ; } </s>

Value is the number of bytes of arguments automatically popped when returning from a subroutine call . FUNDECL is the declaration node of the function ( as a tree ) , FUNTYPE is the data type of the function ( as a tree ) , or for a library call it is an identifier node for the subroutine name . SIZE is the number of bytes of arguments passed on the stack . On the 80386 , the RTD insn may be used to pop them if the number of args is fixed , but if the number is variable then the caller must pop them all . RTD ca n't be used for library calls now because the library is compiled with the Unix compiler . Use of RTD is a selectable option , since it is incompatible with standard Unix calling sequences . If the option is not selected , the caller must always pop the args . The attribute stdcall is equivalent to RTD on a per module basis .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 FP Stackifier"
;
}
</s>


<s> void AArch64CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , const SplitArgTy & PerformArgSplit ) const { const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( SplitVTs . size ( ) == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ 0 ] . getTypeForEVT ( Ctx ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } SmallVector < uint64_t , 4 > BitOffsets ; for ( auto Offset : Offsets ) BitOffsets . push_back ( Offset * 8 ) ; SmallVector < unsigned , 8 > SplitRegs ; for ( auto I = & SplitArgs [ FirstRegIdx ] ; I != SplitArgs . end ( ) ; ++ I ) SplitRegs . push_back ( I -> Reg ) ; PerformArgSplit ( SplitRegs , BitOffsets ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static enum reg_class mep_secondary_copro_reload_class ( enum reg_class rclass , rtx x ) { if ( mep_general_reg ( x ) ) return NO_REGS ; if ( mep_general_copro_reg ( x ) ) { if ( mep_have_copro_copro_moves_p ) return NO_REGS ; if ( mep_have_core_copro_moves_p ) return GENERAL_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , LOADABLE_CR_REGS ) && constraint_satisfied_p ( x , CONSTRAINT_U ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the secondary reload class needed for moving value X to or from a register in coprocessor register class CLASS .


<s> int uses_TOC ( ) { rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( PATTERN ( insn ) , 0 , i ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , 0 , i ) , 1 ) == 7 ) return 1 ; } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


<s> bool isMem ( ) const { return Kind == Memory ; } </s>


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static unsigned HOST_WIDE_INT aarch64_asan_shadow_offset ( void ) { return ( HOST_WIDE_INT_1 << 36 ) ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; unsigned Align = 1 << LogAlign ; return ( PO + Align - 1 ) / Align * Align ; } </s>

Compute the offset immediately following this block .


<s> const TOYInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo ; } </s>

getRegInfo - Return information about the registers currently in use .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool X86TargetLowering :: isNarrowingProfitable ( MVT VT1 , MVT VT2 ) const { return ! ( VT1 == MVT :: i32 && VT2 == MVT :: i16 ) ; } </s>

Return true if it 's profitable to narrow operations of type SrcVT to DestVT .


<s> bool SystemZFrameLowering :: hasFP ( const MachineFunction & MF ) const { return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getInfo < SystemZMachineFunctionInfo > ( ) -> getManipulatesSP ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void arm32_output_mi_thunk ( FILE * file , tree , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const bool long_call_p = arm_is_long_call_p ( function ) ; int this_regno = ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ? R1_REGNUM : R0_REGNUM ) ; rtx temp = gen_rtx_REG ( Pmode , IP_REGNUM ) ; rtx this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( delta != 0 ) arm_split_constant ( PLUS , Pmode , NULL_RTX , delta , this_rtx , this_rtx , false ) ; if ( vcall_offset != 0 ) { emit_move_insn ( temp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; arm_split_constant ( PLUS , Pmode , NULL_RTX , vcall_offset , temp , temp , false ) ; emit_move_insn ( temp , gen_rtx_MEM ( Pmode , temp ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } rtx funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; if ( long_call_p ) { emit_move_insn ( temp , funexp ) ; funexp = temp ; } funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx_insn * insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; emit_barrier ( ) ; if ( long_call_p ) { split_all_insns_noflow ( ) ; arm_reorg ( ) ; } insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


Expand cpymem , as if from a __builtin_memcpy . Return true if we succeed , otherwise return false .


<s> bool ix86_using_red_zone ( void ) { return ( TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI && ( ! cfun -> machine -> has_local_indirect_jump || cfun -> machine -> indirect_branch_type == indirect_branch_keep ) ) ; } </s>


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> static bool mips_interrupt_extra_call_saved_reg_p ( unsigned int regno ) { if ( ( ISA_HAS_HILO || TARGET_DSP ) && MD_REG_P ( regno ) ) return true ; if ( TARGET_DSP && DSP_ACC_REG_P ( regno ) ) return true ; if ( GP_REG_P ( regno ) && cfun -> machine -> use_shadow_register_set == SHADOW_SET_NO ) { if ( regno == GP_REG_FIRST ) return false ; if ( KERNEL_REG_P ( regno ) ) return false ; if ( regno == STACK_POINTER_REGNUM ) return false ; return call_used_regs [ regno ] ; } return false ; } </s>

Return true if REGNO is a register that is ordinarily call-clobbered but must nevertheless be preserved by an interrupt handler .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( const CalleeSavedInfo & I : CSI ) { Register Reg = I . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , I . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( const CalleeSavedInfo & I : CSI ) { Register Reg = I . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
bool
Valid
;
StringRef
Name
=
AArch64DB
::
DBarrierMapper
(
)
.
toString
(
getBarrier
(
)
,
Valid
)
;
if
(
Valid
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
getShiftedImmVal
(
)
->
print
(
OS
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
bool
Valid
;
StringRef
Name
=
AArch64PRFM
::
PRFMMapper
(
)
.
toString
(
getPrefetch
(
)
,
Valid
)
;
if
(
Valid
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_ShiftExtend
:
{
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
AArch64DB::DBarrierMapper
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
AArch64PRFM::PRFMMapper
"<prfop "
">"
"<prfop invalid #"
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> TargetPassConfig * CSKYTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new CSKYPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: Writer < support :: little > ( OS ) . write < uint32_t > ( Binary ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


"iwmmxt requires an AAPCS compatible ABI for proper operation"

"iwmmxt abi requires an iwmmxt capable cpu"

"target CPU does not support interworking"

"AAPCS does not support %<-mcaller-super-interworking%>"

"AAPCS does not support %<-mcallee-super-interworking%>"

"target CPU does not support ARMv8-M Security Extensions"

"ARMv8-M Security Extensions incompatible with selected FPU"

"%<-mfloat-abi=hard%>: selected processor lacks an FPU"

Perform some validation between the desired architecture and the rest of the options .


<s>
bool
SparcAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
if
(
parseBranchModifiers
(
Operands
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
||
getLexer
(
)
.
is
(
AsmToken
::
Plus
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Plus
)
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
"+"
,
Parser
.
getTok
(
)
.
getLoc
(
)
)
)
;
}
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Sparc
Sparc
SparcOperand::CreateToken
0
"unexpected token"
"unexpected token"
SparcOperand::CreateToken
"+"
"unexpected token"
"unexpected token"


<s> unsigned PPCRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( ! Subtarget . isPPC64 ( ) ) return hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0x01000000 , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> unsigned LEGRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return LEG :: SP ; } </s>


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void arm_override_options_after_change ( void ) { arm_override_options_after_change_1 ( & global_options ) ; } </s>


<s>
SDNode
*
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
std
::
pair
<
bool
,
SDNode
*
>
Ret
=
selectNode
(
Node
)
;
if
(
Ret
.
first
)
return
Ret
.
second
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."
"=> "
"\n"


"secondary output reload copy from %s %s to "


<s> bool shouldTransformSignedTruncationCheck ( EVT XVT , unsigned KeptBits ) const override { if ( XVT . isVector ( ) ) return false ; auto VTIsOk = [ ] ( EVT VT ) -> bool { return VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 || VT == MVT :: i64 ; } ; MVT KeptBitsVT = MVT :: getIntegerVT ( KeptBits ) ; return VTIsOk ( XVT ) && VTIsOk ( KeptBitsVT ) ; } </s>

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not : ( add x , ( 1 < < ( KeptBits-1 ) ) ) srccond ( 1 < < KeptBits ) Into it 's more traditional form : ( ( x < < C ) a > > C ) dstcond x Return true if we should transform .


"passing %qT to argument %d of %qE, but"

Require argument ARGNO to match argument FIRST_ARGNO , which was inferred to be a pointer to a scalar element of type TYPE .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( EVT VT ) const { if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return ARM :: QQPRRegisterClass ; else if ( VT == MVT :: v8i64 ) return ARM :: QQQQPRRegisterClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegisterClass MVT::v8i64 ARM::QQQQPRRegisterClass


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> EVT PPCTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . useCRBits ( ) ? MVT :: i1 : MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void rs6000_output_function_entry ( FILE * file , const char * fname ) { if ( fname [ 0 ] != '.' ) { switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , "L." ) ; break ; case ABI_ELFv2 : case ABI_V4 : case ABI_DARWIN : break ; } } RS6000_OUTPUT_BASENAME ( file , fname ) ; } </s>


<s> static rtx ix86_expand_sse_fabs ( rtx op0 , rtx * smask ) { machine_mode vmode , mode = GET_MODE ( op0 ) ; rtx xa , mask ; xa = gen_reg_rtx ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; mask = ix86_build_signbit_mask ( vmode , VECTOR_MODE_P ( mode ) , true ) ; if ( ! VECTOR_MODE_P ( mode ) ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) ) ; tmp = gen_rtx_VEC_SELECT ( mode , mask , tmp ) ; mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( mask , tmp ) ) ; } emit_insn ( gen_rtx_SET ( xa , gen_rtx_AND ( mode , op0 , mask ) ) ) ; if ( smask ) * smask = mask ; return xa ; } </s>

Expand fabs ( OP0 ) and return a new rtx that holds the result . The mask for masking out the sign-bit is stored in * SMASK , if that is non-null .


<s> bool SystemZInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned LowReg = 0 , HighReg = 0 , StartOffset = - 1U , EndOffset = 0 ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass != & SystemZ :: FP64RegClass ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += 8 ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64mr : SystemZ :: MOV64mrm ) ) ) ; MIB . addReg ( SystemZ :: R15D ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & SystemZ :: FP64RegClass ) { MBB . addLiveIn ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getArchName ( ) != "arm64e" && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> static void ia64_output_function_end_prologue ( FILE * file ) { if ( ia64_except_unwind_info ( & global_options ) != UI_TARGET ) return ; fputs ( "\t.body\n" , file ) ; } </s>

Emit the .body directive at the scheduled end of the prologue .


<s> bool mips_use_ins_ext_p ( rtx op , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { if ( ! ISA_HAS_EXT_INS || ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; if ( ! IN_RANGE ( width , 1 , GET_MODE_BITSIZE ( GET_MODE ( op ) ) - 1 ) ) return false ; if ( bitpos < 0 || bitpos + width > GET_MODE_BITSIZE ( GET_MODE ( op ) ) ) return false ; return true ; } </s>

Return true if ( zero_extract OP SIZE POSITION ) can be used as the source of an `` ext '' instruction or the destination of an `` ins '' instruction . OP must be a register operand and the following conditions must hold : 0 < = POSITION < GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < SIZE < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < POSITION + SIZE < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) Also reject lengths equal to a word as they are better handled by the move patterns .


<s> StringRef X86TargetLowering :: getStackProbeSymbolName ( MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) -> getFnAttribute ( "probe-stack" ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) ) return "" ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? "___chkstk_ms" : "__chkstk" ; return Subtarget . isTargetCygMing ( ) ? "_alloca" : "_chkstk" ; } </s>

Returns the name of the symbol used to emit stack probes or the empty string if not applicable .


<s> static bool arm_const_not_ok_for_debug_p ( rtx p ) { tree decl_op0 = NULL ; tree decl_op1 = NULL ; if ( GET_CODE ( p ) == UNSPEC ) return true ; if ( GET_CODE ( p ) == MINUS ) { if ( GET_CODE ( XEXP ( p , 1 ) ) == SYMBOL_REF ) { decl_op1 = SYMBOL_REF_DECL ( XEXP ( p , 1 ) ) ; if ( decl_op1 && GET_CODE ( XEXP ( p , 0 ) ) == SYMBOL_REF && ( decl_op0 = SYMBOL_REF_DECL ( XEXP ( p , 0 ) ) ) ) { if ( ( VAR_P ( decl_op1 ) || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( VAR_P ( decl_op0 ) || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ; if ( TREE_CODE ( decl_op1 ) == LABEL_DECL && TREE_CODE ( decl_op0 ) == LABEL_DECL ) return ( DECL_CONTEXT ( decl_op1 ) != DECL_CONTEXT ( decl_op0 ) ) ; } return true ; } } return false ; } </s>

This is a temporary fix for PR60655 . Ideally we need to handle most of these cases in the generic part but currently we reject minus ( .. ) ( sym_ref ) . We try to ameliorate the case with minus ( sym_ref1 ) ( sym_ref2 ) where they are in the same section .


<s> static int arm_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int cost ) { rtx i_pat , d_pat ; if ( TARGET_THUMB1 && REG_NOTE_KIND ( link ) == 0 && recog_memoized ( insn ) == CODE_FOR_cbranchsi4_insn && recog_memoized ( dep ) >= 0 && get_attr_conds ( dep ) == CONDS_SET ) return 0 ; if ( current_tune -> sched_adjust_cost != NULL ) { if ( ! current_tune -> sched_adjust_cost ( insn , link , dep , & cost ) ) return cost ; } if ( REG_NOTE_KIND ( link ) == REG_DEP_ANTI || REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) return 0 ; if ( REG_NOTE_KIND ( link ) == 0 && CALL_P ( insn ) ) return 1 ; if ( ( i_pat = single_set ( insn ) ) != NULL && MEM_P ( SET_SRC ( i_pat ) ) && ( d_pat = single_set ( dep ) ) != NULL && MEM_P ( SET_DEST ( d_pat ) ) ) { rtx src_mem = XEXP ( SET_SRC ( i_pat ) , 0 ) ; if ( ( GET_CODE ( src_mem ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( src_mem ) ) || reg_mentioned_p ( stack_pointer_rtx , src_mem ) || reg_mentioned_p ( frame_pointer_rtx , src_mem ) || reg_mentioned_p ( hard_frame_pointer_rtx , src_mem ) ) return 1 ; } return cost ; } </s>

This function implements the target macro TARGET_SCHED_ADJUST_COST . It corrects the value of COST based on the relationship between INSN and DEP through the dependence LINK . It returns the new value . There is a per-core adjust_cost hook to adjust scheduler costs and the per-core hook can choose to completely override the generic adjust_cost function . Only put bits of code into arm_adjust_cost that are common across all cores .


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != CONST_INT ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || ( unsigned HOST_WIDE_INT ) summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> bool nds32_n13_last_two_load_to_e1_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_two_def_reg = extract_nth_access_reg ( producer , - 2 ) ; if ( last_two_def_reg == NULL_RTX ) return false ; return n13_consumed_by_e1_dep_p ( consumer , last_two_def_reg ) ; } </s>

Check dependencies from LMW ( N , N-1 ) to E2 .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; const auto & DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> Value * AArch64TargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getGlobalVariable ( "__security_cookie" ) ; return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


<s> void dimode_scalar_chain :: replace_with_subreg_in_insn ( rtx_insn * insn , rtx reg , rtx new_reg ) { replace_with_subreg ( single_set ( insn ) , reg , new_reg ) ; } </s>

Replace REG in INSN with a V2DI subreg of NEW_REG .


<s> bool Thumb1FrameInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned ARMTargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget -> useInlineJumpTables ( ) ) { return MachineJumpTableInfo :: EK_Inline ; } else { return TargetLowering :: getJumpTableEncoding ( ) ; } } </s>

Return the entry encoding for a jump table in the current function .


<s> int ix86_expand_strlen ( rtx out , rtx src , rtx eoschar , rtx align ) { rtx addr , scratch1 , scratch2 , scratch3 , scratch4 ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! TARGET_INLINE_ALL_STRINGOPS && ! optimize_size && ( GET_CODE ( align ) != CONST_INT || INTVAL ( align ) < 4 ) ) return 0 ; addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; scratch1 = gen_reg_rtx ( Pmode ) ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! optimize_size ) { emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; if ( TARGET_64BIT ) emit_insn ( gen_subdi3 ( out , out , addr ) ) ; else emit_insn ( gen_subsi3 ( out , out , addr ) ) ; } else { rtx unspec ; scratch2 = gen_reg_rtx ( Pmode ) ; scratch3 = gen_reg_rtx ( Pmode ) ; scratch4 = force_reg ( Pmode , constm1_rtx ) ; emit_move_insn ( scratch3 , addr ) ; eoschar = force_reg ( QImode , eoschar ) ; emit_insn ( gen_cld ( ) ) ; src = replace_equiv_address_nv ( src , scratch3 ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , src , eoschar , align , scratch4 ) , UNSPEC_SCAS ) ; emit_insn ( gen_strlenqi_1 ( scratch1 , scratch3 , unspec ) ) ; if ( TARGET_64BIT ) { emit_insn ( gen_one_cmpldi2 ( scratch2 , scratch1 ) ) ; emit_insn ( gen_adddi3 ( out , scratch2 , constm1_rtx ) ) ; } else { emit_insn ( gen_one_cmplsi2 ( scratch2 , scratch1 ) ) ; emit_insn ( gen_addsi3 ( out , scratch2 , constm1_rtx ) ) ; } } return 1 ; } </s>


<s> virtual const MandarinInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> DecodeStatus MipsDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian , IsMicroMips ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( IsMicroMips ) { Result = decodeInstruction ( DecoderTableMicroMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } Result = decodeInstruction ( DecoderTableMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> static inline bool has_func_attr ( const_tree decl , const char * func_attr ) { if ( decl == NULL_TREE ) decl = current_function_decl ; return lookup_attribute ( func_attr , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ; } </s>

Returns true if the provided function has the specified attribute .


<s> void AArch64LongBranchStub :: applyFixup ( Relocation & pSrcReloc , IRBuilder & pBuilder , BranchIsland & pIsland ) { LDSymbol * symbol = pSrcReloc . symInfo ( ) -> outSymbol ( ) ; uint64_t dest = symbol -> fragRef ( ) -> frag ( ) -> getParent ( ) -> getSection ( ) . addr ( ) + symbol -> fragRef ( ) -> getOutputOffset ( ) ; uint64_t src = pIsland . getParent ( ) -> getSection ( ) . addr ( ) + pIsland . offset ( ) + pIsland . size ( ) ; if ( isValidForADRP ( src , dest ) ) { m_pData = ADRP_TEMPLATE ; m_Name = "adrp_veneer" ; m_Size = sizeof ( ADRP_TEMPLATE ) ; getFixupList ( ) . clear ( ) ; addFixup ( 0x0 , 0 , llvm :: ELF :: R_AARCH64_ADR_PREL_PG_HI21 ) ; addFixup ( 0x4 , 0 , llvm :: ELF :: R_AARCH64_ADD_ABS_LO12_NC ) ; } Stub :: applyFixup ( pSrcReloc , pBuilder , pIsland ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool arm_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; return for_each_rtx ( & x , arm_tls_operand_p_1 , NULL ) ; } </s>

Return TRUE if X contains any TLS symbol references .


<s> bool PPCTTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { if ( ! LsrNoInsnsCost ) return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; else return TargetTransformInfoImplBase :: isLSRCostLess ( C1 , C2 ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> static bool arm_scalar_mode_supported_p ( machine_mode mode ) { if ( mode == HFmode ) return ( arm_fp16_format != ARM_FP16_FORMAT_NONE ) ; else if ( ALL_FIXED_POINT_MODE_P ( mode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Implement TARGET_SCALAR_MODE_SUPPORTED_P . This simply adds HFmode as a supported mode ; even though we do n't implement arithmetic on this type directly , it 's supported by optabs conversions , much the way the double-word arithmetic is special-cased in the default hook .


<s> static int const_ok_for_op ( HOST_WIDE_INT i , enum rtx_code code ) { if ( const_ok_for_arm ( i ) ) return 1 ; switch ( code ) { case PLUS : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : case IOR : return 0 ; case AND : return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if I is a valid constant for the operation CODE .


<s> static bool aarch64_extending_load_p ( class vec_info * vinfo , stmt_vec_info stmt_info ) { gassign * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ; if ( ! assign || ! CONVERT_EXPR_CODE_P ( gimple_assign_rhs_code ( assign ) ) ) return false ; tree rhs = gimple_assign_rhs1 ( stmt_info -> stmt ) ; tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( rhs ) ; if ( ! INTEGRAL_TYPE_P ( lhs_type ) || ! INTEGRAL_TYPE_P ( rhs_type ) || TYPE_PRECISION ( lhs_type ) <= TYPE_PRECISION ( rhs_type ) ) return false ; stmt_vec_info def_stmt_info = vinfo -> lookup_def ( rhs ) ; return ( def_stmt_info && STMT_VINFO_DATA_REF ( def_stmt_info ) && DR_IS_READ ( STMT_VINFO_DATA_REF ( def_stmt_info ) ) ) ; } </s>

Return true if STMT_INFO extends the result of a load .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> void UnwindOpcodeAssembler :: EmitRegSave ( uint32_t RegSave ) { if ( RegSave == 0u ) return ; if ( RegSave & ( 1u << 4 ) ) { uint32_t Range = 0 ; uint32_t Mask = ( 1u << 4 ) ; for ( uint32_t Bit = ( 1u << 5 ) ; Bit < ( 1u << 12 ) ; Bit <<= 1 ) { if ( ( RegSave & Bit ) == 0u ) break ; ++ Range ; Mask |= Bit ; } uint32_t UnmaskedReg = RegSave & 0xfff0u & ( ~ Mask ) ; if ( UnmaskedReg == 0u ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4 | Range ) ; RegSave &= 0x000fu ; } else if ( UnmaskedReg == ( 1u << 14 ) ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range ) ; RegSave &= 0x000fu ; } } if ( ( RegSave & 0xfff0u ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK_R4 | ( RegSave >> 4 ) ) ; if ( ( RegSave & 0x000fu ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK | ( RegSave & 0x000fu ) ) ; } </s>

Emit unwind opcodes for .save directives .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
if
(
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
}
SDValue
Val
;
if
(
Is64Bit
&&
CopyVT
.
isVector
(
)
&&
CopyVT
.
getSizeInBits
(
)
==
64
)
{
if
(
VA
.
getLocReg
(
)
==
X86
::
XMM0
||
VA
.
getLocReg
(
)
==
X86
::
XMM1
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
v2i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
Val
=
DAG
.
getNode
(
ISD
::
EXTRACT_VECTOR_ELT
,
dl
,
MVT
::
i64
,
Val
,
DAG
.
getConstant
(
0
,
MVT
::
i64
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
Val
=
DAG
.
getNode
(
ISD
::
BIT_CONVERT
,
dl
,
CopyVT
,
Val
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
{
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> Type * ARMTargetLowering :: shouldConvertSplatType ( ShuffleVectorInst * SVI ) const { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return nullptr ; Type * SVIType = SVI -> getType ( ) ; Type * ScalarType = SVIType -> getScalarType ( ) ; if ( ScalarType -> isFloatTy ( ) ) return Type :: getInt32Ty ( SVIType -> getContext ( ) ) ; if ( ScalarType -> isHalfTy ( ) ) return Type :: getInt16Ty ( SVIType -> getContext ( ) ) ; return nullptr ; } </s>

Given a shuffle vector SVI representing a vector splat , return a new scalar type of size equal to SVI 's scalar type if the new type is more profitable .


<s> static bool arm_cxx_guard_mask_bit ( void ) { return TARGET_AAPCS_BASED ; } </s>

The EABI says test the least significant bit of a guard variable .


<s> static void pa_hpux_init_libfuncs ( void ) { set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( sqrt_optab , TFmode , "_U_Qfsqrt" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; set_optab_libfunc ( unord_optab , TFmode , "_U_Qfunord" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" : "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_usgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_udbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; } </s>

Initialize optabs to point to HPUX long double emulation routines .


<s> void MMIXFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MMIXRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; uint64_t MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


"ADJSTACKDOWN and ADJSTACKUP should be no-ops"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void LC2200AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { exit ( - 1 ) ; } </s>


<s> static int num_insns_constant_multi ( HOST_WIDE_INT value , machine_mode mode ) { int nregs = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int total = 0 ; while ( nregs -- > 0 ) { HOST_WIDE_INT low = sext_hwi ( value , BITS_PER_WORD ) ; int insns = num_insns_constant_gpr ( low ) ; if ( insns > 2 && rs6000_is_valid_and_mask ( GEN_INT ( low ) , DImode ) ) insns = 2 ; total += insns ; value >>= BITS_PER_WORD ; } return total ; } </s>

Helper for num_insns_constant . Allow constants formed by the num_insns_constant_gpr sequences , plus li -1 , rldicl/rldicr/rlwinm , and handle modes that require multiple gprs .


<s> static int ix86_adjust_cost ( rtx insn , rtx link , rtx dep_insn , int cost ) { enum attr_type insn_type , dep_insn_type ; enum attr_memory memory ; rtx set , set2 ; int dep_insn_code_number ; if ( REG_NOTE_KIND ( link ) != 0 ) return 0 ; dep_insn_code_number = recog_memoized ( dep_insn ) ; if ( dep_insn_code_number < 0 || recog_memoized ( insn ) < 0 ) return cost ; insn_type = get_attr_type ( insn ) ; dep_insn_type = get_attr_type ( dep_insn ) ; switch ( ix86_tune ) { case PROCESSOR_PENTIUM : if ( ix86_agi_dependant ( insn , dep_insn , insn_type ) ) cost += 1 ; if ( ix86_flags_dependant ( insn , dep_insn , insn_type ) ) cost = 0 ; if ( insn_type == TYPE_FMOV && get_attr_memory ( insn ) == MEMORY_STORE && ! ix86_agi_dependant ( insn , dep_insn , insn_type ) ) cost += 1 ; break ; case PROCESSOR_PENTIUMPRO : memory = get_attr_memory ( insn ) ; if ( get_attr_fp_int_src ( dep_insn ) ) cost += 5 ; if ( insn_type == TYPE_FMOV && ( set = single_set ( dep_insn ) ) != NULL_RTX && ( set2 = single_set ( insn ) ) != NULL_RTX && rtx_equal_p ( SET_DEST ( set ) , SET_SRC ( set2 ) ) && GET_CODE ( SET_DEST ( set2 ) ) == MEM ) cost += 1 ; if ( ( memory == MEMORY_LOAD || memory == MEMORY_BOTH ) && ! ix86_agi_dependant ( insn , dep_insn , insn_type ) ) { if ( dep_insn_type == TYPE_IMOV || dep_insn_type == TYPE_FMOV ) cost = 1 ; else if ( cost > 1 ) cost -- ; } break ; case PROCESSOR_K6 : memory = get_attr_memory ( insn ) ; if ( ( insn_type == TYPE_PUSH || insn_type == TYPE_POP ) && ( dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP ) ) return 1 ; if ( get_attr_fp_int_src ( dep_insn ) ) cost += 5 ; if ( ( memory == MEMORY_LOAD || memory == MEMORY_BOTH ) && ! ix86_agi_dependant ( insn , dep_insn , insn_type ) ) { if ( dep_insn_type == TYPE_IMOV || dep_insn_type == TYPE_FMOV ) cost = 1 ; else if ( cost > 2 ) cost -= 2 ; else cost = 1 ; } break ; case PROCESSOR_ATHLON : case PROCESSOR_K8 : memory = get_attr_memory ( insn ) ; if ( ( memory == MEMORY_LOAD || memory == MEMORY_BOTH ) && ! ix86_agi_dependant ( insn , dep_insn , insn_type ) ) { enum attr_unit unit = get_attr_unit ( insn ) ; int loadcost = 3 ; if ( unit == UNIT_INTEGER || unit == UNIT_UNKNOWN ) loadcost = 3 ; else loadcost = TARGET_ATHLON ? 2 : 0 ; if ( cost >= loadcost ) cost -= loadcost ; else cost = 0 ; } default : break ; } return cost ; } </s>

This function corrects the value of COST ( latency ) based on the relationship between INSN and DEP_INSN through a dependence of type DEP_TYPE , and strength DW . It should return the new value . On x86 CPUs this is most commonly used to model the fact that valus of registers used to compute address of memory operand needs to be ready earlier than values of registers used in the actual operation .


<s> static unsigned int ATTRIBUTE_UNUSED x86_64_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ix86_in_large_data_p ( decl ) ) flags |= SECTION_LARGE ; if ( decl == NULL_TREE && ( strcmp ( name , ".ldata.rel.ro" ) == 0 || strcmp ( name , ".ldata.rel.ro.local" ) == 0 ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , ".lbss" ) == 0 || strncmp ( name , ".lbss." , 5 ) == 0 || strncmp ( name , ".gnu.linkonce.lb." , 16 ) == 0 ) flags |= SECTION_BSS ; return flags ; } </s>

Select a set of attributes for section NAME based on the properties of DECL and whether or not RELOC indicates that DECL 's initializer might contain runtime relocations .


<s> void i386_pe_record_external_function ( tree decl , const char * name ) { struct extern_list * p ; p = ggc_alloc < extern_list > ( ) ; p -> next = extern_head ; p -> decl = decl ; p -> name = name ; extern_head = p ; } </s>

Assemble an external function reference . We need to keep a list of these , so that we can output the function types at the end of the assembly . We ca n't output the types now , because we might see a definition of the function later on and emit debugging information for it then .


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || F . needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt && ! blockEndIsUnreachable ( MBB , I ) ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>


<s> bool targetHandlesStackFrameRounding ( ) const override { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> static rtx x86_this_parameter ( tree function ) { tree type = TREE_TYPE ( function ) ; if ( TARGET_64BIT ) { int n = aggregate_value_p ( TREE_TYPE ( type ) , type ) != 0 ; return gen_rtx_REG ( DImode , x86_64_int_parameter_registers [ n ] ) ; } if ( ix86_function_regparm ( type , function ) > 0 ) { tree parm ; parm = TYPE_ARG_TYPES ( type ) ; for ( ; parm ; parm = TREE_CHAIN ( parm ) ) if ( TREE_VALUE ( parm ) == void_type_node ) break ; if ( parm ) { int regno = 0 ; if ( lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( type ) ) ) regno = 2 ; return gen_rtx_REG ( SImode , regno ) ; } } if ( aggregate_value_p ( TREE_TYPE ( type ) , type ) ) return gen_rtx_MEM ( SImode , plus_constant ( stack_pointer_rtx , 8 ) ) ; else return gen_rtx_MEM ( SImode , plus_constant ( stack_pointer_rtx , 4 ) ) ; } </s>

Returns an expression indicating where the this parameter is located on entry to the FUNCTION .


"rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n"

A C expressions returning the cost of moving data of MODE from a register to or from memory .


<s> unsigned pass_tiabi_check :: execute ( function * fun ) { struct walk_stmt_info wi ; const_tree fntype = TREE_TYPE ( fun -> decl ) ; gimple_seq body = gimple_body ( current_function_decl ) ; memset ( & wi , 0 , sizeof ( wi ) ) ; wi . info = NULL ; wi . want_locations = true ; walk_gimple_seq ( body , NULL , check_op_callback , & wi ) ; chk_function_decl ( fntype , fun -> function_start_locus ) ; return 0 ; } </s>


<s> static bool arm_block_set_vect_profit_p ( unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT align , machine_mode mode ) { int num ; bool unaligned_p = ( ( align & 3 ) != 0 ) ; unsigned int nelt = GET_MODE_NUNITS ( mode ) ; num = 1 ; num += ( length + nelt - 1 ) / nelt ; if ( ! unaligned_p && ( length & 3 ) != 0 ) num ++ ; if ( ! unaligned_p && mode == V16QImode ) num -- ; return ( num <= arm_block_set_max_insns ( ) ) ; } </s>

Return TRUE if it 's profitable to set block of memory for vectorized case . LENGTH is the number of bytes to set . ALIGN is the alignment of destination memory in bytes . MODE is the vector mode used to set the memory .


<s> static const struct processor * aarch64_get_arch ( enum aarch64_arch arch ) { if ( arch != aarch64_no_arch ) return & all_architectures [ arch ] ; const struct processor * cpu = & all_cores [ TARGET_CPU_DEFAULT & 0x3f ] ; return & all_architectures [ cpu -> arch ] ; } </s>

Return the architecture corresponding to the enum ARCH . If it does n't specify a valid architecture , return the default .


<s> bool sh_small_register_classes_for_mode_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return ( ! TARGET_SHMEDIA ) ; } </s>

Return true if registers in machine mode MODE will likely be allocated to registers in small register classes .


<s> static rtx csky_function_value ( const_tree type , const_tree func , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsignedp ATTRIBUTE_UNUSED ; int size ; mode = TYPE_MODE ( type ) ; size = int_size_in_bytes ( type ) ; if ( FUNCTION_VARG_MODE_P ( mode ) ) { mode = promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; return gen_rtx_REG ( mode , CSKY_FIRST_VFP_REGNUM ) ; } if ( INTEGRAL_TYPE_P ( type ) ) { mode = promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; return gen_rtx_REG ( mode , CSKY_FIRST_RET_REGNUM ) ; } if ( mode == BLKmode && size > UNITS_PER_WORD && size <= UNITS_PER_WORD * 2 ) { rtx ret_regs [ 2 ] ; ret_regs [ 0 ] = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , CSKY_FIRST_RET_REGNUM ) , GEN_INT ( 0 * UNITS_PER_WORD ) ) ; ret_regs [ 1 ] = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , CSKY_FIRST_RET_REGNUM + 1 ) , GEN_INT ( 1 * UNITS_PER_WORD ) ) ; rtvec vec = gen_rtvec ( 2 , ret_regs [ 0 ] , ret_regs [ 1 ] ) ; return gen_rtx_PARALLEL ( mode , vec ) ; } return gen_rtx_REG ( mode , CSKY_FIRST_RET_REGNUM ) ; } </s>


<s> static bool ix86_eax_live_at_start_p ( void ) { return REGNO_REG_SET_P ( ENTRY_BLOCK_PTR -> il . rtl -> global_live_at_end , 0 ) ; } </s>

Return true if EAX is live at the start of the function . Used by ix86_expand_prologue to determine if we need special help before calling allocate_stack_worker .


<s> static void mips_set_current_function ( tree fndecl ) { mips_set_compression_mode ( mips_get_compress_mode ( fndecl ) ) ; } </s>

Implement TARGET_SET_CURRENT_FUNCTION . Decide whether the current function should use the MIPS16 or microMIPS ISA and switch modes accordingly .


<s> FastISel * Mips :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new MipsFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static machine_mode vax_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { switch ( m1 ) { default : gcc_unreachable ( ) ; case E_CCmode : switch ( m2 ) { default : gcc_unreachable ( ) ; case E_CCmode : case E_CCNZmode : case E_CCNmode : case E_CCZmode : return m1 ; } case E_CCNZmode : switch ( m2 ) { default : gcc_unreachable ( ) ; case E_CCmode : return m2 ; case E_CCNmode : case E_CCNZmode : case E_CCZmode : return m1 ; } case E_CCNmode : case E_CCZmode : switch ( m2 ) { default : gcc_unreachable ( ) ; case E_CCmode : case E_CCNZmode : return m2 ; case E_CCNmode : case E_CCZmode : return m1 == m2 ? m1 : E_CCNZmode ; } } } </s>

Return the narrowest CC mode that spans both modes offered . If they intersect , this will be the wider of the two , and if they do not then find find one that is a superset of both ( i.e . CCNZmode for a pair consisting of CCNmode and CCZmode ) . A wider CC writer will satisfy a narrower CC reader , e.g . a comparison operator that uses CCZmode can use a CCNZmode output of a previous instruction .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfo > ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : nullptr ; LibInfo = getAnalysisIfAvailable < TargetLibraryInfo > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>


<s> void VEDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { case VEISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ 0 ] << 24 ) | ( Bytes [ 1 ] << 16 ) | ( Bytes [ 2 ] << 8 ) | ( Bytes [ 3 ] << 0 ) ; return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> bool ix86_avoid_lea_for_add ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 , regno1 , regno2 ; if ( ! TARGET_OPT_AGU || optimize_function_for_size_p ( cfun ) ) return false ; regno0 = true_regnum ( operands [ 0 ] ) ; regno1 = true_regnum ( operands [ 1 ] ) ; regno2 = true_regnum ( operands [ 2 ] ) ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; else return ! ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , 1 , false ) ; } </s>

Return true if we need to split op0 = op1 + op2 into a sequence of move and add to avoid AGU stalls .


<s> static rtx rs6000_legitimize_tls_address_aix ( rtx addr , enum tls_model model ) { rtx sym , mem , tocref , tlsreg , tmpreg , dest , tlsaddr ; const char * name ; char * tlsname ; name = XSTR ( addr , 0 ) ; if ( name [ strlen ( name ) - 1 ] != ']' && ( TREE_PUBLIC ( SYMBOL_REF_DECL ( addr ) ) || bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ) ) { tlsname = XALLOCAVEC ( char , strlen ( name ) + 4 ) ; strcpy ( tlsname , name ) ; strcat ( tlsname , bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ? "[UL]" : "[TL]" ) ; tlsaddr = copy_rtx ( addr ) ; XSTR ( tlsaddr , 0 ) = ggc_strdup ( tlsname ) ; } else tlsaddr = addr ; sym = force_const_mem ( GET_MODE ( tlsaddr ) , tlsaddr ) ; if ( constant_pool_expr_p ( XEXP ( sym , 0 ) ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( XEXP ( sym , 0 ) ) , Pmode ) ) { tocref = create_TOC_reference ( XEXP ( sym , 0 ) , NULL_RTX ) ; mem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( mem , get_TOC_alias_set ( ) ) ; } else return sym ; if ( model == TLS_MODEL_GLOBAL_DYNAMIC || model == TLS_MODEL_LOCAL_DYNAMIC ) { name = XSTR ( XVECEXP ( XEXP ( mem , 0 ) , 0 , 0 ) , 0 ) ; tlsname = XALLOCAVEC ( char , strlen ( name ) + 1 ) ; strcpy ( tlsname , "*LCM" ) ; strcat ( tlsname , name + 3 ) ; rtx modaddr = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( tlsname ) ) ; SYMBOL_REF_FLAGS ( modaddr ) |= SYMBOL_FLAG_LOCAL ; tocref = create_TOC_reference ( modaddr , NULL_RTX ) ; rtx modmem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( modmem , get_TOC_alias_set ( ) ) ; rtx modreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( modreg , modmem ) ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_32BIT ) emit_insn ( gen_tls_get_addrsi ( dest , modreg , tmpreg ) ) ; else emit_insn ( gen_tls_get_addrdi ( dest , modreg , tmpreg ) ) ; return dest ; } else if ( TARGET_32BIT ) { tlsreg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tls_get_tpointer ( tlsreg ) ) ; } else tlsreg = gen_rtx_REG ( DImode , 13 ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_MINUS ( Pmode , addr , tlsreg ) ) ; dest = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , tmpreg , tlsreg ) ) ; return dest ; } </s>


<s> int iq2000_initial_elimination_offset ( int from , int to ATTRIBUTE_UNUSED ) { int offset ; compute_frame_size ( get_frame_size ( ) ) ; if ( ( from ) == FRAME_POINTER_REGNUM ) ( offset ) = 0 ; else if ( ( from ) == ARG_POINTER_REGNUM ) ( offset ) = ( cfun -> machine -> total_size ) ; else if ( ( from ) == RETURN_ADDRESS_POINTER_REGNUM ) { if ( leaf_function_p ( ) ) ( offset ) = 0 ; else ( offset ) = cfun -> machine -> gp_sp_offset + ( ( UNITS_PER_WORD - ( POINTER_SIZE / BITS_PER_UNIT ) ) * ( BYTES_BIG_ENDIAN != 0 ) ) ; } return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET . FROM is either the frame pointer , argument pointer , or return address pointer . TO is either the stack pointer or hard frame pointer .


<s> static rtx mips_gen_const_int_vector_shuffle ( machine_mode mode , int val ) { int nunits = GET_MODE_NUNITS ( mode ) ; int nsets = nunits / 4 ; rtx elts [ MAX_VECT_LEN ] ; int set = 0 ; int i , j ; for ( j = 0 ; j < nsets ; j ++ , set = 4 * j ) for ( i = 0 ; i < 4 ; i ++ ) elts [ set + i ] = GEN_INT ( set + ( ( val >> ( 2 * i ) ) & 0x3 ) ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nunits , elts ) ) ; } </s>

Return a vector of repeated 4-element sets generated from immediate VAL in mode MODE .


<s> bool easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return false ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ; else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , 0 ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , 1 ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) == - 1 && INTVAL ( CONST_VECTOR_ELT ( op , 1 ) ) == - 1 ) return true ; return false ; } else if ( mode == V1TImode ) return false ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( vspltis_shifted ( op ) != 0 ) return true ; return false ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


<s> static int ix86_value_regno ( enum machine_mode mode , tree func , tree fntype ) { gcc_assert ( ! TARGET_64BIT ) ; if ( ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 8 ) ) return FIRST_MMX_REG ; if ( mode == TImode || ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 16 ) ) return FIRST_SSE_REG ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT || ! TARGET_FLOAT_RETURNS_IN_80387 ) return 0 ; if ( ( func || fntype ) && ( mode == SFmode || mode == DFmode ) ) { int sse_level = ix86_function_sseregparm ( fntype , func ) ; if ( ( sse_level >= 1 && mode == SFmode ) || ( sse_level == 2 && mode == DFmode ) ) return FIRST_SSE_REG ; } return FIRST_FLOAT_REG ; } </s>

Given a mode , return the register to use for a return value .


"Can only put epilog before 'retl' instruction!"


<s>
bool
PPCInstrInfo
::
FoldImmediate
(
MachineInstr
*
UseMI
,
MachineInstr
*
DefMI
,
unsigned
Reg
,
MachineRegisterInfo
*
MRI
)
const
{
unsigned
DefOpc
=
DefMI
->
getOpcode
(
)
;
if
(
DefOpc
!=
PPC
::
LI
&&
DefOpc
!=
PPC
::
LI8
)
return
false
;
if
(
!
DefMI
->
getOperand
(
1
)
.
isImm
(
)
)
return
false
;
if
(
DefMI
->
getOperand
(
1
)
.
getImm
(
)
!=
0
)
return
false
;
const
MCInstrDesc
&
UseMCID
=
UseMI
->
getDesc
(
)
;
if
(
UseMCID
.
isPseudo
(
)
)
return
false
;
unsigned
UseIdx
;
for
(
UseIdx
=
0
;
UseIdx
<
UseMI
->
getNumOperands
(
)
;
++
UseIdx
)
if
(
UseMI
->
getOperand
(
UseIdx
)
.
isReg
(
)
&&
UseMI
->
getOperand
(
UseIdx
)
.
getReg
(
)
==
Reg
)
break
;
assert
(
UseIdx
<
UseMI
->
getNumOperands
(
)
&&
"Cannot find Reg in UseMI"
)
;
assert
(
UseIdx
<
UseMCID
.
getNumOperands
(
)
&&
"No operand description for Reg"
)
;
const
MCOperandInfo
*
UseInfo
=
&
UseMCID
.
OpInfo
[
UseIdx
]
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
if
(
UseInfo
->
RegClass
!=
1
)
return
false
;
}
else
{
if
(
UseInfo
->
RegClass
!=
PPC
::
GPRC_NOR0RegClassID
&&
UseInfo
->
RegClass
!=
PPC
::
G8RC_NOX0RegClassID
)
return
false
;
}
if
(
UseInfo
->
Constraints
!=
0
)
return
false
;
unsigned
ZeroReg
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
ZeroReg
=
isPPC64
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
else
{
ZeroReg
=
UseInfo
->
RegClass
==
PPC
::
G8RC_NOX0RegClassID
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
bool
DeleteDef
=
MRI
->
hasOneNonDBGUse
(
Reg
)
;
UseMI
->
getOperand
(
UseIdx
)
.
setReg
(
ZeroReg
)
;
if
(
DeleteDef
)
DefMI
->
eraseFromParent
(
)
;
return
true
;
}
</s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> TargetPassConfig * FISCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new FISCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
static
bool
rs6000_declare_alias
(
struct
symtab_node
*
n
,
void
*
d
)
{
struct
declare_alias_data
*
data
=
(
struct
declare_alias_data
*
)
d
;
if
(
!
n
->
alias
||
n
->
weakref
)
return
false
;
if
(
lookup_attribute
(
"ifunc"
,
DECL_ATTRIBUTES
(
n
->
decl
)
)
)
return
false
;
TREE_ASM_WRITTEN
(
n
->
decl
)
=
true
;
const
char
*
name
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
n
->
decl
)
)
;
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
2
)
;
char
*
p
;
int
dollar_inside
=
0
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
n
->
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
n
->
decl
)
)
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
{
fputs
(
"\t.globl ."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
fputs
(
"\t.globl "
,
data
->
file
)
;
assemble_name
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
else
if
(
DECL_WEAK
(
n
->
decl
)
&&
!
data
->
function_descriptor
)
ASM_WEAKEN_DECL
(
data
->
file
,
n
->
decl
,
name
,
)
;
}
else
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
{
fputs
(
"\t.lglobl ."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
fputs
(
"\t.lglobl "
,
data
->
file
)
;
assemble_name
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
if
(
data
->
function_descriptor
)
putc
(
'.'
,
data
->
file
)
;
ASM_OUTPUT_LABEL
(
data
->
file
,
buffer
)
;
return
false
;
}
</s>

Declare alias N. A helper function for for_node_and_aliases .


<s> bool ARMFrameLowering :: enableCalleeSaveSkip ( const MachineFunction & MF ) const { assert ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoReturn ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) && ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: UWTable ) ) ; return true ; } </s>

Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functions .


<s> static rtx lxvrze_expand_builtin ( rtx target , insn_code icode , rtx * op , machine_mode tmode , machine_mode smode ) { rtx pat , addr ; op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; if ( op [ 0 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 1 ] ) ; else { op [ 0 ] = copy_to_mode_reg ( Pmode , op [ 0 ] ) ; addr = gen_rtx_MEM ( smode , gen_rtx_PLUS ( Pmode , op [ 1 ] , op [ 0 ] ) ) ; } pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Expand a builtin function that loads a scalar into a vector register with zero extension , and return the expanded rtx .


<s> bool legitimate_constant_address_p ( rtx x ) { if ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || CONST_INT_P ( x ) || GET_CODE ( x ) == HIGH ) return true ; if ( GET_CODE ( x ) != CONST ) return false ; if ( flag_pic && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) return false ; return true ; } </s>

1 if X is an rtx for a constant that is a valid address .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool expand_vec_perm_broadcast ( struct expand_vec_perm_d * d ) { unsigned i , elt , nelt = d -> nelt ; unsigned char perm2 [ 2 ] ; rtx temp ; bool ok ; if ( ! d -> one_operand_p ) return false ; elt = d -> perm [ 0 ] ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; switch ( d -> vmode ) { case V2SImode : case V2SFmode : perm2 [ 0 ] = elt ; perm2 [ 1 ] = elt + 2 ; ok = expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , perm2 , 2 ) ; gcc_assert ( ok ) ; break ; case V8QImode : if ( BYTES_BIG_ENDIAN ) elt = 7 - elt ; elt *= BITS_PER_UNIT ; temp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_extzv ( temp , gen_lowpart ( DImode , d -> op0 ) , GEN_INT ( 8 ) , GEN_INT ( elt ) ) ) ; emit_insn ( gen_mux1_brcst_qi ( d -> target , gen_lowpart ( QImode , temp ) ) ) ; break ; case V4HImode : default : gcc_unreachable ( ) ; } return true ; } </s>


<s> static rtx emit_memmov ( rtx destmem , rtx * srcmem , rtx destptr , rtx srcptr , HOST_WIDE_INT size_to_move ) { rtx dst = destmem , src = * srcmem , tempreg ; enum insn_code code ; machine_mode move_mode ; int piece_size , i ; piece_size = 1 << floor_log2 ( size_to_move ) ; while ( ! int_mode_for_size ( piece_size * BITS_PER_UNIT , 0 ) . exists ( & move_mode ) || ( code = optab_handler ( mov_optab , move_mode ) ) == CODE_FOR_nothing ) { gcc_assert ( piece_size > 1 ) ; piece_size >>= 1 ; } if ( GET_MODE_SIZE ( move_mode ) > GET_MODE_SIZE ( word_mode ) ) { int nunits = GET_MODE_SIZE ( move_mode ) / GET_MODE_SIZE ( word_mode ) ; if ( ! mode_for_vector ( word_mode , nunits ) . exists ( & move_mode ) || ( code = optab_handler ( mov_optab , move_mode ) ) == CODE_FOR_nothing ) { move_mode = word_mode ; piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; } } gcc_assert ( code != CODE_FOR_nothing ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , 0 ) ; src = adjust_automodify_address_nv ( src , move_mode , srcptr , 0 ) ; gcc_assert ( size_to_move % piece_size == 0 ) ; for ( i = 0 ; i < size_to_move ; i += piece_size ) { tempreg = gen_reg_rtx ( move_mode ) ; emit_insn ( GEN_FCN ( code ) ( tempreg , src ) ) ; emit_insn ( GEN_FCN ( code ) ( dst , tempreg ) ) ; emit_move_insn ( destptr , plus_constant ( Pmode , copy_rtx ( destptr ) , piece_size ) ) ; emit_move_insn ( srcptr , plus_constant ( Pmode , copy_rtx ( srcptr ) , piece_size ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; src = adjust_automodify_address_nv ( src , move_mode , srcptr , piece_size ) ; } * srcmem = src ; return dst ; } </s>

This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to DESTMEM . SRC is passed by pointer to be updated on return . Return value is updated DST .