<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_cpu_index
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_tune_index
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
if
(
rs6000_default_cpu
==
0
||
rs6000_default_cpu
[
0
]
==
'\0'
||
!
global_options_set
.
x_rs6000_cpu_index
)
{
fputs
(
"\t.machine "
,
asm_out_file
)
;
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MODULO
)
!=
0
)
fputs
(
"power9\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
fputs
(
"power8\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
fputs
(
"power7\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_CMPB
)
!=
0
)
fputs
(
"power6\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
fputs
(
"power5\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MFCRF
)
!=
0
)
fputs
(
"power4\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
fputs
(
"ppc64\n"
,
asm_out_file
)
;
else
fputs
(
"ppc\n"
,
asm_out_file
)
;
}
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
}
</s>

Do anything needed at the start of the asm file .


<s> unsigned getSize ( ) const { return CurType . Size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> void SystemZPassConfig :: addPreSched2 ( ) { addPass ( createSystemZExpandPseudoPass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool MipsAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( MBB -> isEHPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> MCELFStreamer & MipsTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( * Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> static bool pru_valid_addr_expr_p ( machine_mode mode , rtx base , rtx offset , bool strict_p ) { if ( ! strict_p && GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; if ( ! strict_p && GET_CODE ( offset ) == SUBREG ) offset = SUBREG_REG ( offset ) ; if ( REG_P ( base ) && pru_regno_ok_for_base_p ( REGNO ( base ) , strict_p ) && ( ( CONST_INT_P ( offset ) && pru_valid_const_ubyte_offset ( mode , INTVAL ( offset ) ) ) || ( REG_P ( offset ) && pru_regno_ok_for_index_p ( REGNO ( offset ) , strict_p ) ) ) ) return true ; else if ( REG_P ( base ) && pru_regno_ok_for_index_p ( REGNO ( base ) , strict_p ) && ctable_base_operand ( offset , VOIDmode ) ) return true ; else return false ; } </s>

Return true if the address expression formed by BASE + OFFSET is valid . Note that the following address is not handled here : base CTABLE constant base + UBYTE constant offset The constants will be folded . The ctable_addr_operand predicate will take care of the validation . The CTABLE base+offset split will happen during operand printing .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool MipsTargetObjectFile :: IsConstantInSmallSection ( const Constant * CN , const TargetMachine & TM ) const { return ( TM . getSubtarget < MipsSubtarget > ( ) . useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( CN -> getType ( ) ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


"r%d has non convertible definition in insn %d\n"

"Removing insn %d from candidates list\n"

The DImode version of remove_non_convertible_regs .


<s>
Sparc
::
Fixups
SparcMCExpr
::
getFixupKind
(
SparcMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Unhandled SparcMCExpr::VariantKind"
)
;
case
VK_Sparc_LO
:
return
Sparc
::
fixup_sparc_lo10
;
case
VK_Sparc_HI
:
return
Sparc
::
fixup_sparc_hi22
;
case
VK_Sparc_H44
:
return
Sparc
::
fixup_sparc_h44
;
case
VK_Sparc_M44
:
return
Sparc
::
fixup_sparc_m44
;
case
VK_Sparc_L44
:
return
Sparc
::
fixup_sparc_l44
;
case
VK_Sparc_HH
:
return
Sparc
::
fixup_sparc_hh
;
case
VK_Sparc_HM
:
return
Sparc
::
fixup_sparc_hm
;
case
VK_Sparc_LM
:
return
Sparc
::
fixup_sparc_lm
;
case
VK_Sparc_PC22
:
return
Sparc
::
fixup_sparc_pc22
;
case
VK_Sparc_PC10
:
return
Sparc
::
fixup_sparc_pc10
;
case
VK_Sparc_GOT22
:
return
Sparc
::
fixup_sparc_got22
;
case
VK_Sparc_GOT10
:
return
Sparc
::
fixup_sparc_got10
;
case
VK_Sparc_GOT13
:
return
Sparc
::
fixup_sparc_got13
;
case
VK_Sparc_13
:
return
Sparc
::
fixup_sparc_13
;
case
VK_Sparc_WPLT30
:
return
Sparc
::
fixup_sparc_wplt30
;
case
VK_Sparc_WDISP30
:
return
Sparc
::
fixup_sparc_call30
;
case
VK_Sparc_TLS_GD_HI22
:
return
Sparc
::
fixup_sparc_tls_gd_hi22
;
case
VK_Sparc_TLS_GD_LO10
:
return
Sparc
::
fixup_sparc_tls_gd_lo10
;
case
VK_Sparc_TLS_GD_ADD
:
return
Sparc
::
fixup_sparc_tls_gd_add
;
case
VK_Sparc_TLS_GD_CALL
:
return
Sparc
::
fixup_sparc_tls_gd_call
;
case
VK_Sparc_TLS_LDM_HI22
:
return
Sparc
::
fixup_sparc_tls_ldm_hi22
;
case
VK_Sparc_TLS_LDM_LO10
:
return
Sparc
::
fixup_sparc_tls_ldm_lo10
;
case
VK_Sparc_TLS_LDM_ADD
:
return
Sparc
::
fixup_sparc_tls_ldm_add
;
case
VK_Sparc_TLS_LDM_CALL
:
return
Sparc
::
fixup_sparc_tls_ldm_call
;
case
VK_Sparc_TLS_LDO_HIX22
:
return
Sparc
::
fixup_sparc_tls_ldo_hix22
;
case
VK_Sparc_TLS_LDO_LOX10
:
return
Sparc
::
fixup_sparc_tls_ldo_lox10
;
case
VK_Sparc_TLS_LDO_ADD
:
return
Sparc
::
fixup_sparc_tls_ldo_add
;
case
VK_Sparc_TLS_IE_HI22
:
return
Sparc
::
fixup_sparc_tls_ie_hi22
;
case
VK_Sparc_TLS_IE_LO10
:
return
Sparc
::
fixup_sparc_tls_ie_lo10
;
case
VK_Sparc_TLS_IE_LD
:
return
Sparc
::
fixup_sparc_tls_ie_ld
;
case
VK_Sparc_TLS_IE_LDX
:
return
Sparc
::
fixup_sparc_tls_ie_ldx
;
case
VK_Sparc_TLS_IE_ADD
:
return
Sparc
::
fixup_sparc_tls_ie_add
;
case
VK_Sparc_TLS_LE_HIX22
:
return
Sparc
::
fixup_sparc_tls_le_hix22
;
case
VK_Sparc_TLS_LE_LOX10
:
return
Sparc
::
fixup_sparc_tls_le_lox10
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s>
void
ATTRIBUTE_UNUSED
ix86_debug_options
(
void
)
{
char
*
opts
=
ix86_target_string
(
ix86_isa_flags
,
ix86_isa_flags2
,
target_flags
,
ix86_target_flags
,
ix86_arch_string
,
ix86_tune_string
,
ix86_fpmath
,
true
)
;
if
(
opts
)
{
fprintf
(
stderr
,
"%s\n\n"
,
opts
)
;
free
(
opts
)
;
}
else
fputs
(
"<no options>\n\n"
,
stderr
)
;
return
;
}
</s>

Function that is callable from the debugger to print the current options .


<s> unsigned char X86Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return X86II :: MO_NO_FLAG ; assert ( ! isTargetCOFF ( ) ) ; if ( isTargetELF ( ) ) return X86II :: MO_PLT ; if ( is64Bit ( ) ) { auto * F = dyn_cast_or_null < Function > ( GV ) ; if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_NO_FLAG ; } return X86II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static machine_mode rs6000_secondary_memory_needed_mode ( machine_mode mode ) { if ( lra_in_progress && mode == SDmode ) return DDmode ; return mode ; } </s>

Return the mode to be used for memory when a secondary memory location is needed . For SDmode values we need to use DDmode , in all other cases we can use the same mode .


<s> void MipsTargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; if ( Res ) for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> static tree rs6000_builtin_vectorized_libmass ( combined_fn fn , tree type_out , tree type_in ) { char name [ 32 ] ; const char * suffix = NULL ; tree fntype , new_fndecl , bdecl = NULL_TREE ; int n_args = 1 ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations || ! TARGET_VSX ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_ATAN2 : CASE_CFN_HYPOT : CASE_CFN_POW : n_args = 2 ; gcc_fallthrough ( ) ; CASE_CFN_ACOS : CASE_CFN_ACOSH : CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == 2 ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = "d2" ; } else if ( el_mode == SFmode && n == 4 ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = "4" ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( "__builtin_" ) - 1 ) ; strcat ( name , suffix ) ; if ( n_args == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == 2 ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for the Mathematical Acceleration Subsystem ( mass ) interface to a library with vectorized intrinsics .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Condition Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; return simplifyCode ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == 0 ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
(
PseudoSourceValue
::
getFixedStack
(
FI
)
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tSpill
0


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createX86AtomicExpandPass ( & getX86TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool ARMSubtarget :: enableMachineScheduler ( ) const { return useMachineScheduler ( ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> static rtx function_arg_32 ( const CUMULATIVE_ARGS * cum , machine_mode mode , machine_mode orig_mode , const_tree type , HOST_WIDE_INT bytes , HOST_WIDE_INT words ) { if ( mode == VOIDmode ) return constm1_rtx ; switch ( mode ) { default : break ; case BLKmode : if ( bytes < 0 ) break ; case DImode : case SImode : case HImode : case QImode : if ( words <= cum -> nregs ) { int regno = cum -> regno ; if ( cum -> fastcall ) { if ( mode == BLKmode || mode == DImode || ( type && AGGREGATE_TYPE_P ( type ) ) ) break ; if ( regno == AX_REG ) regno = CX_REG ; } return gen_rtx_REG ( mode , regno ) ; } break ; case DFmode : if ( cum -> float_in_sse < 2 ) break ; case SFmode : if ( cum -> float_in_sse < 1 ) break ; case TImode : case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V4SFmode : case V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case OImode : case XImode : gcc_unreachable ( ) ; case V64QImode : case V32HImode : case V16SImode : case V8DImode : case V16SFmode : case V8DFmode : case V8SFmode : case V8SImode : case V32QImode : case V16HImode : case V4DFmode : case V4DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case V8QImode : case V4HImode : case V2SImode : case V2SFmode : case V1TImode : case V1DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> mmx_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> mmx_regno + FIRST_MMX_REG ) ; } break ; } return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> int pa_adjust_insn_length ( rtx insn , int length ) { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( pat ) == PARALLEL && get_attr_type ( insn ) == TYPE_BTABLE_BRANCH ) return 4 ; else if ( GET_CODE ( insn ) == INSN && GET_CODE ( pat ) != SEQUENCE && GET_CODE ( pat ) != USE && GET_CODE ( pat ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) return 4 ; else if ( GET_CODE ( insn ) == INSN && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == BLKmode ) return compute_movmem_length ( insn ) - 4 ; else if ( GET_CODE ( insn ) == INSN && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) == const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode ) return compute_clrmem_length ( insn ) - 4 ; else if ( GET_CODE ( insn ) == JUMP_INSN && ! simplejump_p ( insn ) ) { if ( GET_CODE ( pat ) == SET && length == 4 && ! forward_branch_p ( insn ) ) return 4 ; else if ( GET_CODE ( pat ) == PARALLEL && get_attr_type ( insn ) == TYPE_PARALLEL_BRANCH && length == 4 ) return 4 ; else if ( GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 1 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) == REG && ! FP_REG_P ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) && length == 4 && ! forward_branch_p ( insn ) ) return 4 ; else return 0 ; } return 0 ; } </s>

Return any length adjustment needed by INSN which already has its length computed as LENGTH . Return zero if no adjustment is necessary . For the PA : function calls , millicode calls , and backwards short conditional branches with unfilled delay slots need an adjustment by +1 ( to account for the NOP which will be inserted into the instruction stream ) . Also compute the length of an inline block move here as it is too complicated to express as a length attribute in pa.md .


<s> static reg_class_t loongarch_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( reg_class_subset_p ( FP_REGS , rclass ) && loongarch_mode_ok_for_mov_fmt_p ( GET_MODE ( x ) ) ) return FP_REGS ; if ( reg_class_subset_p ( GR_REGS , rclass ) ) rclass = GR_REGS ; return rclass ; } </s>


<s> static rtx gen_reg_or_parallel ( machine_mode mode , machine_mode orig_mode , unsigned int regno ) { rtx tmp ; if ( orig_mode != BLKmode ) tmp = gen_rtx_REG ( orig_mode , regno ) ; else { tmp = gen_rtx_REG ( mode , regno ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_PARALLEL ( orig_mode , gen_rtvec ( 1 , tmp ) ) ; } return tmp ; } </s>

We want to pass a value in REGNO whose `` natural '' mode is MODE . However , this may not agree with the mode that the type system has chosen for the register , which is ORIG_MODE . If ORIG_MODE is not BLKmode , then we can go ahead and use it . Otherwise we have to build a PARALLEL instead .


"%qE has no form that takes %qT arguments"

Report that the function has no form that takes type suffix TYPE . Return error_mark_node .


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named , bool incoming ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; const int regbase = incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; slotno = function_arg_slotno ( cum , mode , type , named , incoming , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && VECTOR_INTEGER_TYPE_P ( type ) ) mclass = MODE_FLOAT ; if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( type && VECTOR_TYPE_P ( type ) && mode == BLKmode ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_vector_value ( size , slotno , named , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . else_blk ( ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool MipsTargetObjectFile :: IsConstantInSmallSection ( const DataLayout & DL , const Constant * CN , const TargetMachine & TM ) const { return ( static_cast < const MipsTargetMachine & > ( TM ) . getSubtargetImpl ( ) -> useSmallSection ( ) && LocalSData && IsInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> void emitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> inMips16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: emitConstantPool ( ) ; } </s>

Print to the current output stream assembly representations of the constants in the constant pool MCP .


<s> int is_function_label_plus_const ( rtx op ) { if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , 0 ) , Pmode ) && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ; } </s>

Returns 1 if OP is a function label involved in a simple addition with a constant . Used to keep certain patterns from matching during instruction combination .


<s> static rtx extract_sfunc_addr ( rtx insn ) { rtx pattern = PATTERN ( insn ) ; const int len = XVECLEN ( pattern , 0 ) ; for ( int i = 0 ; i < len ; i ++ ) { rtx part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == Pmode && GENERAL_REGISTER_P ( true_regnum ( XEXP ( part , 0 ) ) ) ) return XEXP ( part , 0 ) ; } gcc_assert ( GET_CODE ( XVECEXP ( pattern , 0 , 0 ) ) == UNSPEC_VOLATILE ) ; return XVECEXP ( XVECEXP ( pattern , 0 , 0 ) , 0 , 1 ) ; } </s>

INSN is an sfunc ; return the rtx that describes the address used .


<s>
static
const
char
*
output_probe_stack_range_1
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addi %0,%0,%1"
,
xops
)
;
xops
[
1
]
=
gen_rtx_REG
(
Pmode
,
0
)
;
output_asm_insn
(
"stw %1,0(%0)"
,
xops
)
;
xops
[
1
]
=
reg2
;
if
(
TARGET_64BIT
)
output_asm_insn
(
"cmpd 0,%0,%1"
,
xops
)
;
else
output_asm_insn
(
"cmpw 0,%0,%1"
,
xops
)
;
fputs
(
"\tbne 0,"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are addresses , not offsets .


<s> void aarch64_save_restore_target_globals ( tree new_tree ) { if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } </s>

Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE . Used by aarch64_set_current_function and aarch64_pragma_target_parse to make sure optab availability predicates are recomputed when necessary .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86InstrInfo & TII = * TM . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * TM . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! llvm :: prior ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"insertBranch must not be told to insert a fallthrough"

"SystemZ branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> static const char * aarch64_mangle_type ( const_tree type ) { if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type ) , va_list_type ) ) return "St9__va_list" ; if ( TYPE_NAME ( type ) != NULL ) return aarch64_mangle_builtin_type ( type ) ; return NULL ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
bool
VEAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
StringRef
Mnemonic
=
splitMnemonic
(
Name
,
NameLoc
,
&
Operands
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Mnemonic
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Mnemonic
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

VE
VE
0
"unexpected token"
"unexpected token"
"unexpected token"


<s> bool MandarinFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getTargetData
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


"Expected a reg or frame index operand."

Return true if this is a load/store that can be potentially paired/merged .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static void mips_sim_record_set ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { struct mips_sim * state ; state = ( struct mips_sim * ) data ; if ( REG_P ( x ) ) { unsigned int regno , end_regno ; end_regno = END_REGNO ( x ) ; for ( regno = REGNO ( x ) ; regno < end_regno ; regno ++ ) { state -> last_set [ regno ] . insn = mips_sim_insn ; state -> last_set [ regno ] . time = state -> time ; } } } </s>

mips_sim_insn has just set X. Update the LAST_SET array in simulation state DATA .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
unsigned
Encoding
,
const
TargetMachine
&
TM
,
MachineModuleInfo
*
MMI
,
MCStreamer
&
Streamer
)
const
{
if
(
TM
.
getMCAsmInfo
(
)
->
getExceptionHandlingType
(
)
!=
ExceptionHandling
::
ARM
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Encoding
,
TM
,
MMI
,
Streamer
)
;
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
return
MCSymbolRefExpr
::
create
(
TM
.
getSymbol
(
GV
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
ARM
"Can handle absptr encoding only"
ARM


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; hasV8Ops = TM . getSubtarget < ARMSubtarget > ( ) . hasV8Ops ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : break ; } unsigned Idx = 1 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > 4 ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; Idx = 0 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & * I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> void AArch64Operand :: dump ( ) const { print ( errs ( ) ) ; } </s>

Dump the plan to stderr ( for debugging ) .


<s> const char * host_detect_local_cpu ( int argc , const char * * argv ) { const char * cpu = NULL ; char * buf = NULL ; kstat_ctl_t * kc ; kstat_t * ksp ; kstat_named_t * brand = NULL ; char buf [ 128 ] ; FILE * f ; int i ; if ( argc < 1 ) return NULL ; if ( strcmp ( argv [ 0 ] , "cpu" ) && strcmp ( argv [ 0 ] , "tune" ) ) return NULL ; kc = kstat_open ( ) ; if ( kc != NULL ) { ksp = kstat_lookup ( kc , CONST_CAST2 ( char * , const char * , "cpu_info" ) , - 1 , NULL ) ; if ( ksp != NULL && kstat_read ( kc , ksp , NULL ) != - 1 && ksp -> ks_type == KSTAT_TYPE_NAMED ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , "brand" ) ) ; if ( brand == NULL ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , "implementation" ) ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_STRING ) buf = KSTAT_NAMED_STR_PTR ( brand ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_CHAR ) buf = brand -> value . c ; } kstat_close ( kc ) ; for ( i = 0 ; cpu_names [ i ] . name != NULL ; i ++ ) if ( strcmp ( buf , cpu_names [ i ] . name ) == 0 ) cpu = cpu_names [ i ] . cpu ; f = fopen ( "/proc/cpuinfo" , "r" ) ; if ( f == NULL ) return NULL ; while ( fgets ( buf , sizeof ( buf ) , f ) != NULL ) if ( strncmp ( buf , "cpu\t\t:" , sizeof ( "cpu\t\t:" ) - 1 ) == 0 ) { for ( i = 0 ; cpu_names [ i ] . name ; i ++ ) if ( strstr ( buf , cpu_names [ i ] . name ) != NULL ) { cpu = cpu_names [ i ] . cpu ; break ; } break ; } fclose ( f ) ; if ( cpu == NULL ) return NULL ; return concat ( "-m" , argv [ 0 ] , "=" , cpu , NULL ) ; } </s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . isPPC64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . isPPC64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ; return SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR432_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR432_SPE_SaveList ; return CSR_SVR432_SaveList ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC::X2 PPC PPC


<s> static void pa_add_gc_roots ( ) { ggc_add_rtx_root ( & hppa_compare_op0 , 1 ) ; ggc_add_rtx_root ( & hppa_compare_op1 , 1 ) ; ggc_add_root ( & deferred_plabels , 1 , sizeof ( & deferred_plabels ) , & mark_deferred_plabels ) ; } </s>

Called to register all of our global variables with the garbage collector .


<s>
Register
SparcTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"i0"
,
SP
::
I0
)
.
Case
(
"i1"
,
SP
::
I1
)
.
Case
(
"i2"
,
SP
::
I2
)
.
Case
(
"i3"
,
SP
::
I3
)
.
Case
(
"i4"
,
SP
::
I4
)
.
Case
(
"i5"
,
SP
::
I5
)
.
Case
(
"i6"
,
SP
::
I6
)
.
Case
(
"i7"
,
SP
::
I7
)
.
Case
(
"o0"
,
SP
::
O0
)
.
Case
(
"o1"
,
SP
::
O1
)
.
Case
(
"o2"
,
SP
::
O2
)
.
Case
(
"o3"
,
SP
::
O3
)
.
Case
(
"o4"
,
SP
::
O4
)
.
Case
(
"o5"
,
SP
::
O5
)
.
Case
(
"o6"
,
SP
::
O6
)
.
Case
(
"o7"
,
SP
::
O7
)
.
Case
(
"l0"
,
SP
::
L0
)
.
Case
(
"l1"
,
SP
::
L1
)
.
Case
(
"l2"
,
SP
::
L2
)
.
Case
(
"l3"
,
SP
::
L3
)
.
Case
(
"l4"
,
SP
::
L4
)
.
Case
(
"l5"
,
SP
::
L5
)
.
Case
(
"l6"
,
SP
::
L6
)
.
Case
(
"l7"
,
SP
::
L7
)
.
Case
(
"g0"
,
SP
::
G0
)
.
Case
(
"g1"
,
SP
::
G1
)
.
Case
(
"g2"
,
SP
::
G2
)
.
Case
(
"g3"
,
SP
::
G3
)
.
Case
(
"g4"
,
SP
::
G4
)
.
Case
(
"g5"
,
SP
::
G5
)
.
Case
(
"g6"
,
SP
::
G6
)
.
Case
(
"g7"
,
SP
::
G7
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> BitVector XNCMRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( XNCM :: IP ) ; Reserved . set ( XNCM :: SP ) ; Reserved . set ( XNCM :: LR ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LD ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LDC1 ) || ( Opc == Mips :: LDC164 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) addPass ( createInsertDivideCheckPass ( ) ) ; if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; const ARMSubtarget * Subtarget = & getARMSubtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"\tARM::shouldCoalesce - Coalesced Weight: "


"SHUXI DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static bool reg_plus_index_p ( rtx x , machine_mode mode , bool strict ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( BASE_REGISTER_P ( xfoo0 , strict ) && index_term_p ( xfoo1 , mode , strict ) ) return true ; if ( BASE_REGISTER_P ( xfoo1 , strict ) && index_term_p ( xfoo0 , mode , strict ) ) return true ; return false ; } </s>

Return 1 if X is the sum of a register and a valid index term for mode MODE .


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCSubtarget
&
Subtarget
=
MF
.
getSubtarget
<
PPCSubtarget
>
(
)
;
const
PPCFrameLowering
*
PPCFI
=
static_cast
<
const
PPCFrameLowering
*
>
(
Subtarget
.
getFrameLowering
(
)
)
;
unsigned
StackEst
=
PPCFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
getBaseRegister
(
MF
)
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

PowerPC
PPC
0
"Local offset must be negative"
PPC::ADDI
PPC::ADDI8
2
0
PPC
PPC
PPC
PPC
PPC
PPC


<s> static char * detect_caches_darwin ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; size_t len = 4 ; static int l1_size_name [ 2 ] = { CTL_HW , HW_L1DCACHESIZE } ; static int l1_line_name [ 2 ] = { CTL_HW , HW_CACHELINE } ; static int l2_size_name [ 2 ] = { CTL_HW , HW_L2CACHESIZE } ; sysctl ( l1_size_name , 2 , & l1_sizekb , & len , NULL , 0 ) ; sysctl ( l1_line_name , 2 , & l1_line , & len , NULL , 0 ) ; sysctl ( l2_size_name , 2 , & l2_sizekb , & len , NULL , 0 ) ; l1_assoc = 0 ; return describe_cache ( l1_sizekb / 1024 , l1_line , l1_assoc , l2_sizekb / 1024 ) ; } </s>

Returns the description of caches on Darwin .


<s> bool CAHPAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << CAHPInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; default : break ; } } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static bool mayAlias ( MachineInstr & MIa , SmallVectorImpl < MachineInstr * > & MemInsns , const AArch64InstrInfo * TII ) { for ( MachineInstr * MIb : MemInsns ) if ( mayAlias ( MIa , * MIb , TII ) ) return true ; return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s>
unsigned
SystemZInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
break
;
if
(
!
getBranchInfo
(
*
I
)
.
hasMBBTarget
(
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

SystemZ
SystemZ
"code size not handled"
0


<s>
bool
SHUXIInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Xbranch condition!"
)
;
SHUXICC
::
CondCodes
CC
=
static_cast
<
SHUXICC
::
CondCodes
>
(
Cond
[
0
]
.
getImm
(
)
)
;
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Invalid branch condition!"
)
;
case
SHUXICC
::
COND_C
:
CC
=
SHUXICC
::
COND_NC
;
break
;
case
SHUXICC
::
COND_N
:
CC
=
SHUXICC
::
COND_NN
;
break
;
case
SHUXICC
::
COND_V
:
CC
=
SHUXICC
::
COND_NV
;
break
;
case
SHUXICC
::
COND_Z
:
CC
=
SHUXICC
::
COND_NZ
;
break
;
case
SHUXICC
::
COND_GE
:
CC
=
SHUXICC
::
COND_L
;
break
;
case
SHUXICC
::
COND_NC
:
CC
=
SHUXICC
::
COND_C
;
break
;
case
SHUXICC
::
COND_NN
:
CC
=
SHUXICC
::
COND_N
;
break
;
case
SHUXICC
::
COND_NV
:
CC
=
SHUXICC
::
COND_V
;
break
;
case
SHUXICC
::
COND_NZ
:
CC
=
SHUXICC
::
COND_Z
;
break
;
case
SHUXICC
::
COND_L
:
CC
=
SHUXICC
::
COND_GE
;
break
;
}
Cond
[
0
]
.
setImm
(
CC
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
const
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
0
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
->
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> SDValue TOYTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && "Unsupported" ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_TOY ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( createELFObjectTargetWriter ( ) , OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , MachineBasicBlock & FMBB , unsigned NumF ) const { return NumT && NumF && NumT <= 2 && NumF <= 2 ; } </s>


<s> bool PadShortFunc :: runOnMachineFunction ( MachineFunction & MF ) { bool OptForSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; if ( OptForSize ) return false ; TM = & MF . getTarget ( ) ; TII = TM -> getInstrInfo ( ) ; ReturnBBs . clear ( ) ; findReturns ( MF . begin ( ) ) ; bool MadeChange = false ; MachineBasicBlock :: iterator ReturnLoc ; MachineBasicBlock * MBB ; unsigned int Cycles = 0 ; unsigned int BBCycles ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { if ( ! cyclesUntilReturn ( MBB , BBCycles , & ReturnLoc ) ) continue ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++ ; MadeChange = true ; } } return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx or1k_adjust_atomic_subword ( rtx orig_mem , rtx * pshift , rtx * pmask ) { rtx addr , align , shift , mask , mem ; machine_mode mode = GET_MODE ( orig_mem ) ; addr = XEXP ( orig_mem , 0 ) ; addr = force_reg ( Pmode , addr ) ; align = expand_binop ( Pmode , and_optab , addr , GEN_INT ( - 4 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; mem = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; rtx mode_mask = GEN_INT ( mode == QImode ? 3 : 2 ) ; shift = expand_binop ( SImode , and_optab , gen_lowpart ( SImode , addr ) , mode_mask , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_binop ( SImode , xor_optab , shift , mode_mask , shift , 1 , OPTAB_LIB_WIDEN ) ; shift = expand_binop ( SImode , ashl_optab , shift , GEN_INT ( 3 ) , shift , 1 , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_binop ( SImode , ashl_optab , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; * pmask = mask ; return mem ; } </s>

A subroutine of the various atomic expanders . For sub-word operations , we must adjust things to operate on SImode . Given the original MEM , return a new aligned memory . Also build and return the quantities by which to shift and mask .


<s> void ix86_emit_swsqrtsf ( rtx res , rtx a , machine_mode mode , bool recip ) { rtx x0 , e0 , e1 , e2 , e3 , mthree , mhalf ; REAL_VALUE_TYPE r ; int unspec ; x0 = gen_reg_rtx ( mode ) ; e0 = gen_reg_rtx ( mode ) ; e1 = gen_reg_rtx ( mode ) ; e2 = gen_reg_rtx ( mode ) ; e3 = gen_reg_rtx ( mode ) ; real_from_integer ( & r , VOIDmode , - 3 , SIGNED ) ; mthree = const_double_from_real_value ( r , SFmode ) ; real_arithmetic ( & r , NEGATE_EXPR , & dconsthalf , NULL ) ; mhalf = const_double_from_real_value ( r , SFmode ) ; unspec = UNSPEC_RSQRT ; if ( VECTOR_MODE_P ( mode ) ) { mthree = ix86_build_const_vector ( mode , true , mthree ) ; mhalf = ix86_build_const_vector ( mode , true , mhalf ) ; if ( GET_MODE_SIZE ( mode ) == 64 ) unspec = UNSPEC_RSQRT14 ; } a = force_reg ( mode , a ) ; emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , a ) , unspec ) ) ) ; if ( ! recip ) { rtx zero = force_reg ( mode , CONST0_RTX ( mode ) ) ; rtx mask ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 64 ) { mask = gen_reg_rtx ( HImode ) ; emit_insn ( gen_avx512f_cmpv16sf3 ( mask , zero , a , GEN_INT ( 0x4 ) ) ) ; emit_insn ( gen_avx512f_blendmv16sf ( x0 , zero , x0 , mask ) ) ; } else { mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( mask , gen_rtx_NE ( mode , zero , a ) ) ) ; emit_insn ( gen_rtx_SET ( x0 , gen_rtx_AND ( mode , x0 , mask ) ) ) ; } } emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , a ) ) ) ; emit_insn ( gen_rtx_SET ( e1 , gen_rtx_MULT ( mode , e0 , x0 ) ) ) ; mthree = force_reg ( mode , mthree ) ; emit_insn ( gen_rtx_SET ( e2 , gen_rtx_PLUS ( mode , e1 , mthree ) ) ) ; mhalf = force_reg ( mode , mhalf ) ; if ( recip ) emit_insn ( gen_rtx_SET ( e3 , gen_rtx_MULT ( mode , x0 , mhalf ) ) ) ; else emit_insn ( gen_rtx_SET ( e3 , gen_rtx_MULT ( mode , e0 , mhalf ) ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_MULT ( mode , e2 , e3 ) ) ) ; } </s>

Output code to perform a Newton-Rhapson approximation of a single precision floating point [ reciprocal ] square root .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"MIPS16 Hard Float Pass"
;
}
</s>


"\nrs6000_secondary_reload_gpr, type = %s\n"

Convert reloads involving 64-bit gprs and misaligned offset addressing , or multiple 32-bit gprs and offsets that are too large , to use indirect addressing .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
Cpu0TargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
return
std
::
make_pair
(
0U
,
&
Cpu0
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
)
return
std
::
make_pair
(
0U
,
&
Cpu0
::
CPURegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Cpu0
::
T9
,
&
Cpu0
::
CPURegsRegClass
)
;
assert
(
"Unexpected type."
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
parseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
TRI
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
void
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
override
{
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
Opcode
)
;
if
(
Opcode
==
TargetOpcode
::
COPY_TO_REGCLASS
)
return
;
uint64_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
case
4
:
if
(
IsLittleEndian
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
break
;
case
8
:
if
(
IsLittleEndian
)
{
uint64_t
Swapped
=
(
Bits
<<
32
)
|
(
Bits
>>
32
)
;
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
Swapped
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint64_t
>
(
Bits
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid instruction size"
)
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

PowerPC
4
support::endian
support::little
support::endian
support::big
8
32
32
support::endian
support::little
support::endian
support::big
"Invalid instruction size"


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return TargetLowering :: shouldFormOverflowOp ( Opcode , VT , true ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s> static rtx gen_stack_pointer_dec ( rtx decrement ) { return gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , decrement ) ) ; } </s>

Generate a decrement for the stack pointer .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void xstormy16_expand_arith ( machine_mode mode , enum rtx_code code , rtx dest , rtx src0 , rtx src1 ) { int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; int firstloop = 1 ; if ( code == NEG ) emit_move_insn ( src0 , const0_rtx ) ; for ( i = 0 ; i < num_words ; i ++ ) { rtx w_src0 , w_src1 , w_dest ; rtx insn ; w_src0 = simplify_gen_subreg ( word_mode , src0 , mode , i * UNITS_PER_WORD ) ; w_src1 = simplify_gen_subreg ( word_mode , src1 , mode , i * UNITS_PER_WORD ) ; w_dest = simplify_gen_subreg ( word_mode , dest , mode , i * UNITS_PER_WORD ) ; switch ( code ) { case PLUS : if ( firstloop && CONST_INT_P ( w_src1 ) && INTVAL ( w_src1 ) == 0 ) continue ; if ( firstloop ) insn = gen_addchi4 ( w_dest , w_src0 , w_src1 ) ; else insn = gen_addchi5 ( w_dest , w_src0 , w_src1 ) ; break ; case NEG : case MINUS : case COMPARE : if ( code == COMPARE && i == num_words - 1 ) { rtx branch , sub , clobber , sub_1 ; sub_1 = gen_rtx_MINUS ( HImode , w_src0 , gen_rtx_ZERO_EXTEND ( HImode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ) ; sub = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_MINUS ( HImode , sub_1 , w_src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( HImode , sub_1 , w_src1 ) , pc_rtx , pc_rtx ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 3 , branch , sub , clobber ) ) ; } else if ( firstloop && code != COMPARE && CONST_INT_P ( w_src1 ) && INTVAL ( w_src1 ) == 0 ) continue ; else if ( firstloop ) insn = gen_subchi4 ( w_dest , w_src0 , w_src1 ) ; else insn = gen_subchi5 ( w_dest , w_src0 , w_src1 ) ; break ; case IOR : case XOR : case AND : if ( CONST_INT_P ( w_src1 ) && INTVAL ( w_src1 ) == - ( code == AND ) ) continue ; insn = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_fmt_ee ( code , mode , w_src0 , w_src1 ) ) ; break ; case NOT : insn = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_NOT ( mode , w_src0 ) ) ; break ; default : gcc_unreachable ( ) ; } firstloop = 0 ; emit ( insn ) ; } if ( firstloop ) emit ( gen_nop ( ) ) ; } </s>

Expander for arithmetic operations ; emit insns to compute ( set DEST ( CODE : MODE SRC0 SRC1 ) ) using CARRY as a temporary . When CODE is COMPARE , a branch template is generated ( this saves duplicating code in xstormy16_split_cbranch ) .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_BSWAP
:
return
legalizeBSwap
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_SBFX
:
case
TargetOpcode
::
G_UBFX
:
return
legalizeBitfieldExtract
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ROTR
:
return
legalizeRotate
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTPOP
:
return
legalizeCTPOP
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpxchg128
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTTZ
:
return
legalizeCTTZ
(
MI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s>
void
CJGMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

CJG
CJG
4
"Unexpected instruction size!"


<s> const uint16_t * TeeRISCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { TeeRISC :: R6 , TeeRISC :: R7 , TeeRISC :: R8 , TeeRISC :: R9 , TeeRISC :: R10 } ; return CalleeSavedRegs ; } </s>


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_64BIT ) return false ; if ( TARGET_PORTABLE_RUNTIME ) return false ; return decl && targetm . binds_local_p ( decl ) ; } </s>

Only direct calls to static functions are allowed to be sibling ( tail ) call optimized . This restriction is necessary because some linker generated stubs will store return pointers into rp ' in some cases which might clobber a live value already in rp ' . In a sibcall the current function and the target function share stack space . Thus if the path to the current function and the path to the target function save a value in rp ' , they save the value into the same stack slot , which has undesirable consequences . Because of the deferred binding nature of shared libraries any function with external scope could be in a different load module and thus require rp ' to be saved when calling that function . So sibcall optimizations can only be safe for static function . Note that GCC never needs return value relocations , so we do n't have to worry about static calls with return value relocations ( which require saving rp ' ) . It is safe to perform a sibcall optimization when the target function will never return .


<s> bool isOSWindows ( ) const { return TargetTriple . isOSWindows ( ) ; } </s>


<s> static unsigned HOST_WIDE_INT sparc_asan_shadow_offset ( void ) { return TARGET_ARCH64 ? ( HOST_WIDE_INT_1 << 43 ) : ( HOST_WIDE_INT_1 << 29 ) ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
bool
CJGInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
I
->
getOpcode
(
)
==
CJG
::
JMP
)
{
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
I
->
getOpcode
(
)
==
CJG
::
JCC
&&
"Invalid conditional branch"
)
;
CJGCC
::
CondCodes
BranchCode
=
static_cast
<
CJGCC
::
CondCodes
>
(
I
->
getOperand
(
1
)
.
getImm
(
)
)
;
if
(
BranchCode
==
CJGCC
::
COND_INVALID
)
return
true
;
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
1
)
;
assert
(
TBB
)
;
if
(
TBB
!=
I
->
getOperand
(
0
)
.
getMBB
(
)
)
return
true
;
CJGCC
::
CondCodes
OldBranchCode
=
(
CJGCC
::
CondCodes
)
Cond
[
0
]
.
getImm
(
)
;
if
(
OldBranchCode
==
BranchCode
)
continue
;
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGlobalMergePass ( TM , 4095 ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


<s> bool AZPRPassConfig :: addPreEmitPass ( ) { addPass ( createAZPRDelaySlotFillerPass ( getAZPRTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool ExpandPseudo :: expand ( ) { bool Expanded = false ; for ( auto & MBB : MF ) { for ( Iter I = MBB . begin ( ) , End = MBB . end ( ) ; I != End ; ) Expanded |= expandInstr ( MBB , I ++ ) ; } return Expanded ; } </s>

expand - Expand a record into a set of elements if possible .


<s> void PPCMachOTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileMachO :: Initialize ( Ctx , TM ) ; LSDASection = getMachOSection ( "__TEXT" , "__gcc_except_tab" , 0 , SectionKind :: getReadOnlyWithRel ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return elements + 1 ; else return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return PPCMaterializeInt ( C , VT , VT != MVT :: i1 ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasXMMInt ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x60000000 ) ; switch ( Count % 4 ) { default : break ; case 1 : OW -> Write8 ( 0 ) ; break ; case 2 : OW -> Write16 ( 0 ) ; break ; case 3 : OW -> Write16 ( 0 ) ; OW -> Write8 ( 0 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static rtx ix86_expand_sse_compare ( const struct builtin_description * d , tree exp , rtx target , bool swap ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 ; machine_mode tmode = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ 2 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( swap ) std :: swap ( op0 , op1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 1 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ 2 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of comparison insns .


<s>
bool
arm_check_builtin_call
(
location_t
,
vec
<
location_t
>
,
tree
fndecl
,
tree
,
unsigned
int
,
tree
*
)
{
int
fcode
=
DECL_MD_FUNCTION_CODE
(
fndecl
)
;
if
(
fcode
==
ARM_BUILTIN_saturation_occurred
||
fcode
==
ARM_BUILTIN_set_saturation
)
{
if
(
cfun
&&
cfun
->
decl
)
DECL_ATTRIBUTES
(
cfun
->
decl
)
=
tree_cons
(
get_identifier
(
"acle qbit"
)
,
NULL_TREE
,
DECL_ATTRIBUTES
(
cfun
->
decl
)
)
;
}
if
(
fcode
==
ARM_BUILTIN_sel
)
{
if
(
cfun
&&
cfun
->
decl
)
DECL_ATTRIBUTES
(
cfun
->
decl
)
=
tree_cons
(
get_identifier
(
"acle gebits"
)
,
NULL_TREE
,
DECL_ATTRIBUTES
(
cfun
->
decl
)
)
;
}
return
true
;
}
</s>

Implement TARGET_CHECK_BUILTIN_CALL . Record a read of the Q bit through intrinsics in the machine function .


<s> bool csky_symbol_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == SYMBOL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( csky_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && csky_symbol_mentioned_p ( XEXP ( x , i ) ) ) return true ; } return false ; } </s>

Return TRUE if X references a SYMBOL_REF .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
7
,
21
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
1
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
1
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
TargetAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void i386_pe_seh_unwind_emit ( FILE * asm_out_file , rtx_insn * insn ) { rtx note , pat ; bool handled_one = false ; struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( prev && ! insn_nothrow_p ( prev ) ) fputs ( "\tnop\n" , asm_out_file ) ; fputs ( "\t.seh_endproc\n" , asm_out_file ) ; seh -> in_cold_section = true ; return ; } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( seh -> after_prologue ) return ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , 1 ) ) { switch ( REG_NOTE_KIND ( note ) ) { case REG_FRAME_RELATED_EXPR : pat = XEXP ( note , 0 ) ; goto found ; case REG_CFA_DEF_CFA : case REG_CFA_EXPRESSION : gcc_unreachable ( ) ; break ; case REG_CFA_REGISTER : gcc_unreachable ( ) ; case REG_CFA_ADJUST_CFA : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; } seh_cfa_adjust_cfa ( asm_out_file , seh , pat ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) pat = single_set ( insn ) ; seh_cfa_offset ( asm_out_file , seh , pat ) ; handled_one = true ; break ; default : break ; } } if ( handled_one ) return ; pat = PATTERN ( insn ) ; found : seh_frame_related_expr ( asm_out_file , seh , pat ) ; } </s>

This function looks at a single insn and emits any SEH directives required for unwind of this insn .


"mnop-mcount only supported with fentry-call"

runOnMachineFunction - Emit the function body .


<s> static SDValue getSplatValue ( SDNode * N ) { if ( auto * BuildVec = dyn_cast < BuildVectorSDNode > ( N ) ) { return BuildVec -> getSplatValue ( ) ; } return SDValue ( ) ; } </s>

If V is a splat vector , return its scalar source operand by extracting that element from the source vector .


<s> EVT AArch64TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static void sparc_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.word\t%r_tls_dtpoff32(" , file ) ; break ; case 8 : fputs ( "\t.xword\t%r_tls_dtpoff64(" , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; fputs ( ")" , file ) ; } </s>

This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> static void ix86_store_returned_bounds ( rtx slot , rtx bounds ) { gcc_assert ( REG_P ( slot ) ) ; emit_move_insn ( slot , bounds ) ; } </s>

Store BOUNDS returned by function into SLOT .


<s> bool AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < AArch64Subtarget > ( ) . isTargetMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; return true ; } </s>


<s> static rtx_code_label * ix86_expand_sse_compare_and_jump ( enum rtx_code code , rtx op0 , rtx op1 , bool swap_operands ) { bool unordered_compare = ix86_unordered_fp_compare ( code ) ; rtx_code_label * label ; rtx tmp , reg ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; label = gen_label_rtx ( ) ; tmp = gen_rtx_COMPARE ( CCFPmode , op0 , op1 ) ; if ( unordered_compare ) tmp = gen_rtx_UNSPEC ( CCFPmode , gen_rtvec ( 1 , tmp ) , UNSPEC_NOTRAP ) ; reg = gen_rtx_REG ( CCFPmode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , reg , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) = label ; return label ; } </s>

Expands a comparison of OP0 with OP1 using comparison code CODE , swapping the operands if SWAP_OPERANDS is true . The expanded code is a forward jump to a newly created label in case the comparison is true . The generated label rtx is returned .


<s> bool ix86_can_use_return_insn_p ( void ) { struct ix86_frame frame ; if ( ! reload_completed || frame_pointer_needed ) return 0 ; if ( crtl -> args . pops_args && crtl -> args . size >= 32768 ) return 0 ; ix86_compute_frame_layout ( & frame ) ; return ( frame . stack_pointer_offset == UNITS_PER_WORD && ( frame . nregs + frame . nsseregs ) == 0 ) ; } </s>

Return 1 if it is appropriate to emit ` ret ' instructions in the body of a function . Do this only if the epilogue is simple , needing a couple of insns . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then . Return 0 if there is no frame marker to de-allocate .


"ARM PIC Global Base Reg Initialization"

getPassName - Return a nice clean name for a pass .


<s>
unsigned
PPCVSXSwapRemoval
::
lookThruCopyLike
(
unsigned
SrcReg
,
unsigned
VecIdx
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
;
if
(
MI
->
isCopy
(
)
)
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
CopySrcReg
)
)
{
if
(
!
isScalarVecReg
(
CopySrcReg
)
)
SwapVector
[
VecIdx
]
.
MentionsPhysVR
=
1
;
return
CopySrcReg
;
}
return
lookThruCopyLike
(
CopySrcReg
,
VecIdx
)
;
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


<s> int emit_cbcond_nop ( rtx insn ) { rtx next = next_active_insn ( insn ) ; if ( ! next ) return 1 ; if ( NONJUMP_INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) == SEQUENCE ) next = XVECEXP ( PATTERN ( next ) , 0 , 0 ) ; else if ( CALL_P ( next ) && GET_CODE ( PATTERN ( next ) ) == PARALLEL ) { rtx delay = XVECEXP ( PATTERN ( next ) , 0 , 1 ) ; if ( GET_CODE ( delay ) == RETURN ) { if ( sparc_leaf_function_p || TARGET_FLAT ) return 0 ; } } if ( NONJUMP_INSN_P ( next ) ) return 0 ; return 1 ; } </s>

Return nonzero if we should emit a nop after a cbcond instruction . The cbcond instruction does not have a delay slot , however there is a severe performance penalty if a control transfer appears right after a cbcond . Therefore we emit a nop when we detect this situation .


<s> void MipsTargetELFStreamer :: emitAssignment ( MCSymbol * Symbol , const MCExpr * Value ) { if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; if ( ! ( MCELF :: getOther ( Data ) & ( ELF :: STO_MIPS_MICROMIPS >> 2 ) ) ) return ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; MCELF :: setOther ( SymbolData , ELF :: STO_MIPS_MICROMIPS >> 2 ) ; } </s>


<s> const MCPhysReg * AArch64RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_PCS_SaveList ; } </s>


<s> static bool aarch64_evpc_rev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev64v16qi ; break ; case V8QImode : gen = gen_aarch64_rev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev32v16qi ; break ; case V8QImode : gen = gen_aarch64_rev32v8qi ; break ; case V8HImode : gen = gen_aarch64_rev64v8hi ; break ; case V4HImode : gen = gen_aarch64_rev64v4hi ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev16v16qi ; break ; case V8QImode : gen = gen_aarch64_rev16v8qi ; break ; case V8HImode : gen = gen_aarch64_rev32v8hi ; break ; case V4HImode : gen = gen_aarch64_rev32v4hi ; break ; case V4SImode : gen = gen_aarch64_rev64v4si ; break ; case V2SImode : gen = gen_aarch64_rev64v2si ; break ; case V4SFmode : gen = gen_aarch64_rev64v4sf ; break ; case V2SFmode : gen = gen_aarch64_rev64v2sf ; break ; case V8HFmode : gen = gen_aarch64_rev64v8hf ; break ; case V4HFmode : gen = gen_aarch64_rev64v4hf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . hasMips64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < MipsFunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < 16 > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void ARMELFStreamer :: Reset ( ) { ExTab = NULL ; FnStart = NULL ; Personality = NULL ; PersonalityIndex = ARM :: EHABI :: NUM_PERSONALITY_INDEX ; FPReg = ARM :: SP ; FPOffset = 0 ; SPOffset = 0 ; PendingOffset = 0 ; UsedFP = false ; CantUnwind = false ; Opcodes . clear ( ) ; UnwindOpAsm . Reset ( ) ; } </s>


<s> unsigned ARMBaseInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; switch ( MI . getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case ARM :: MOVi16_ga_pcrel : case ARM :: MOVTi16_ga_pcrel : case ARM :: t2MOVi16_ga_pcrel : case ARM :: t2MOVTi16_ga_pcrel : return 4 ; case ARM :: MOVi32imm : case ARM :: t2MOVi32imm : return 8 ; case ARM :: CONSTPOOL_ENTRY : case ARM :: JUMPTABLE_INSTS : case ARM :: JUMPTABLE_ADDRS : case ARM :: JUMPTABLE_TBB : case ARM :: JUMPTABLE_TBH : return MI . getOperand ( 2 ) . getImm ( ) ; case ARM :: Int_eh_sjlj_longjmp : return 16 ; case ARM :: tInt_eh_sjlj_longjmp : return 10 ; case ARM :: tInt_WIN_eh_sjlj_longjmp : return 12 ; case ARM :: Int_eh_sjlj_setjmp : case ARM :: Int_eh_sjlj_setjmp_nofp : return 20 ; case ARM :: tInt_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp_nofp : return 12 ; case ARM :: SPACE : return MI . getOperand ( 1 ) . getImm ( ) ; case ARM :: INLINEASM : case ARM :: INLINEASM_BR : { unsigned Size = getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < ARMFunctionInfo > ( ) -> isThumbFunction ( ) ) Size = alignTo ( Size , 4 ) ; return Size ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .