<s> void xstormy16_split_cbranch ( enum machine_mode mode , rtx label , rtx comparison , rtx dest , rtx carry ) { rtx op0 = XEXP ( comparison , 0 ) ; rtx op1 = XEXP ( comparison , 1 ) ; rtx seq , last_insn ; rtx compare ; start_sequence ( ) ; xstormy16_expand_arith ( mode , COMPARE , dest , op0 , op1 , carry ) ; seq = get_insns ( ) ; end_sequence ( ) ; gcc_assert ( INSN_P ( seq ) ) ; last_insn = seq ; while ( NEXT_INSN ( last_insn ) != NULL_RTX ) last_insn = NEXT_INSN ( last_insn ) ; compare = SET_SRC ( XVECEXP ( PATTERN ( last_insn ) , 0 , 0 ) ) ; PUT_CODE ( XEXP ( compare , 0 ) , GET_CODE ( comparison ) ) ; XEXP ( compare , 1 ) = gen_rtx_LABEL_REF ( VOIDmode , label ) ; emit_insn ( seq ) ; } </s>

Take a SImode conditional branch , one of GT/LE/GTU/LEU , and split the arithmetic operation . Most of the work is done by xstormy16_expand_arith .


<s> void X86TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( ! Subtarget -> is64Bit ( ) ) return ; X86MachineFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < X86MachineFunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> static int hi_const ( rtx src ) { return ( GET_CODE ( src ) == CONST_INT && INTVAL ( src ) >= - 32768 && INTVAL ( src ) <= 32767 ) ; } </s>

Return nonzero if constant would be an ok source for a mov.w instead of a mov.l .


"built-in function %qE not supported for MIPS16"

Expand builtin functions . This is called from TARGET_EXPAND_BUILTIN .


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> static bool rs6000_secondary_reload_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { if ( to_type == NO_REG_TYPE || from_type == NO_REG_TYPE ) return false ; if ( ( to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE ) || ( to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( from_type ) ) || ( from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( to_type ) ) ) return true ; if ( to_type == from_type && IS_STD_REG_TYPE ( to_type ) ) return true ; if ( rs6000_secondary_reload_simple_move ( to_type , from_type , mode ) ) { if ( sri ) { sri -> icode = CODE_FOR_nothing ; sri -> extra_cost = 0 ; } return true ; } return rs6000_secondary_reload_direct_move ( to_type , from_type , mode , sri , altivec_p ) ; } </s>

Return whether a move between two register classes can be done either directly ( simple move ) or via a pattern that uses a single extra temporary ( using power8 's direct move in this case .


<s>
bool
SystemZXPLINKFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
return
true
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
SystemZMachineFunctionInfo
*
ZFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
const
SystemZSubtarget
&
Subtarget
=
MF
.
getSubtarget
<
SystemZSubtarget
>
(
)
;
const
TargetInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
auto
&
Regs
=
Subtarget
.
getSpecialRegisters
<
SystemZXPLINK64Registers
>
(
)
;
SystemZ
::
GPRRegs
SpillGPRs
=
ZFI
->
getSpillGPRRegs
(
)
;
DebugLoc
DL
;
if
(
SpillGPRs
.
LowGPR
)
{
assert
(
SpillGPRs
.
LowGPR
!=
SpillGPRs
.
HighGPR
&&
"Should be saving multiple registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
->
get
(
SystemZ
::
STMG
)
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
LowGPR
,
false
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
HighGPR
,
false
)
;
MIB
.
addReg
(
Regs
.
getStackPointerRegister
(
)
)
;
MIB
.
addImm
(
SpillGPRs
.
GPROffset
)
;
auto
&
GRRegClass
=
SystemZ
::
GR64BitRegClass
;
for
(
const
CalleeSavedInfo
&
I
:
CSI
)
{
Register
Reg
=
I
.
getReg
(
)
;
if
(
GRRegClass
.
contains
(
Reg
)
)
addSavedGPR
(
MBB
,
MIB
,
Reg
,
true
)
;
}
}
for
(
const
CalleeSavedInfo
&
I
:
CSI
)
{
Register
Reg
=
I
.
getReg
(
)
;
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
I
.
getFrameIdx
(
)
,
&
SystemZ
::
FP64BitRegClass
,
TRI
)
;
}
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
I
.
getFrameIdx
(
)
,
&
SystemZ
::
VR128BitRegClass
,
TRI
)
;
}
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ::GPRRegs
"Should be saving multiple registers"
SystemZ::STMG
SystemZ::GR64BitRegClass
SystemZ::FP64BitRegClass
SystemZ::FP64BitRegClass
SystemZ::VR128BitRegClass
SystemZ::VR128BitRegClass


<s> static bool isPairableLdStInst ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: STRXui : case AArch64 :: STRWui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : case AArch64 :: LDRXui : case AArch64 :: LDRWui : case AArch64 :: LDRSWui : case AArch64 :: STURSi : case AArch64 :: STURDi : case AArch64 :: STURQi : case AArch64 :: STURWi : case AArch64 :: STURXi : case AArch64 :: LDURSi : case AArch64 :: LDURDi : case AArch64 :: LDURQi : case AArch64 :: LDURWi : case AArch64 :: LDURXi : case AArch64 :: LDURSWi : return true ; } } </s>

Return true if pairing the given load or store may be paired with another .


<s> MCInst Thumb2InstrInfo :: getNop ( ) const { return MCInstBuilder ( ARM :: tHINT ) . addImm ( 0 ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ; } </s>

Return the noop instruction to use for a noop .


<s> SDValue getAddr ( NodeTy * N , SelectionDAG & DAG , bool IsLocal = true ) const { SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned Flag = CSKYII :: MO_None ; bool IsPIC = isPositionIndependent ( ) ; if ( IsPIC ) Flag = IsLocal ? CSKYII :: MO_GOTOFF : IsCall ? CSKYII :: MO_PLT32 : CSKYII :: MO_GOT32 ; SDValue TCPV = getTargetConstantPoolValue ( N , Ty , DAG , Flag ) ; SDValue TV = getTargetNode ( N , DL , Ty , DAG , Flag ) ; SDValue Addr = DAG . getNode ( CSKYISD :: LOAD_ADDR , DL , Ty , { TV , TCPV } ) ; if ( ! IsPIC ) return Addr ; SDValue Result = DAG . getNode ( ISD :: ADD , DL , Ty , { DAG . getGLOBAL_OFFSET_TABLE ( Ty ) , Addr } ) ; if ( IsLocal ) return Result ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; } </s>

Return the address accessed by this recipe .


<s> bool PPCInstructionSelector :: select ( MachineInstr & I ) { if ( selectImpl ( I , * CoverageInfo ) ) return true ; return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> bool SparcAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".byte" ) return parseDirectiveWord ( 1 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".half" ) return parseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".nword" ) return parseDirectiveWord ( is64Bit ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( is64Bit ( ) && IDVal == ".xword" ) return parseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".register" ) { Parser . eatToEndOfStatement ( ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { if ( Subtarget . isThumb2 ( ) ) { if ( ! Subtarget . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; PM . add ( createUnpackMachineBundlesPass ( ) ) ; } PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
DEBUG_FUNCTION
void
rs6000_debug_print_mode
(
ssize_t
m
)
{
ssize_t
rc
;
int
spaces
=
0
;
fprintf
(
stderr
,
"Mode: %-5s"
,
GET_MODE_NAME
(
m
)
)
;
for
(
rc
=
0
;
rc
<
N_RELOAD_REG
;
rc
++
)
fprintf
(
stderr
,
" %s: %s"
,
reload_reg_map
[
rc
]
.
name
,
rs6000_debug_addr_mask
(
reg_addr
[
m
]
.
addr_mask
[
rc
]
,
true
)
)
;
if
(
(
reg_addr
[
m
]
.
reload_store
!=
CODE_FOR_nothing
)
||
(
reg_addr
[
m
]
.
reload_load
!=
CODE_FOR_nothing
)
)
{
fprintf
(
stderr
,
"%*s  Reload=%c%c"
,
spaces
,
""
,
(
reg_addr
[
m
]
.
reload_store
!=
CODE_FOR_nothing
)
's'
:
'*'
,
(
reg_addr
[
m
]
.
reload_load
!=
CODE_FOR_nothing
)
'l'
:
'*'
)
;
spaces
=
0
;
}
else
spaces
+=
strlen
(
"  Reload=sl"
)
;
if
(
reg_addr
[
m
]
.
scalar_in_vmx_p
)
{
fprintf
(
stderr
,
"%*s  Upper=y"
,
spaces
,
""
)
;
spaces
=
0
;
}
else
spaces
+=
strlen
(
"  Upper=y"
)
;
if
(
rs6000_vector_unit
[
m
]
!=
VECTOR_NONE
||
rs6000_vector_mem
[
m
]
!=
VECTOR_NONE
)
{
fprintf
(
stderr
,
"%*s  vector: arith=%-10s mem=%s"
,
spaces
,
""
,
rs6000_debug_vector_unit
(
rs6000_vector_unit
[
m
]
)
,
rs6000_debug_vector_unit
(
rs6000_vector_mem
[
m
]
)
)
;
}
fputs
(
"\n"
,
stderr
)
;
}
</s>

Print the address masks in a human readble fashion .


<s> static bool is_imported_p ( rtx x ) { if ( ! TARGET_DLLIMPORT_DECL_ATTRIBUTES || GET_CODE ( x ) != SYMBOL_REF ) return false ; return SYMBOL_REF_DLLIMPORT_P ( x ) || SYMBOL_REF_STUBVAR_P ( x ) ; } </s>

Nonzero if the symbol is marked as dllimport , or as stub-variable , otherwise zero .


"cannot return value in vector register because"

" altivec instructions are disabled, use -maltivec"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> void PPCOperand :: print ( raw_ostream & OS ) const { switch ( Kind ) { case Token : OS << "'" << getToken ( ) << "'" ; break ; case Immediate : case ContextImmediate : OS << getImm ( ) ; break ; case Expression : OS << * getExpr ( ) ; break ; case TLSRegister : OS << * getTLSReg ( ) ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> unsigned getAlign ( ) const { return Align ; } </s>

Return the minimum known alignment in bytes of the actual memory reference .


<s> bool PPCInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { const TargetRegisterClass * RCs [ ] = { & PPC :: CRRCRegClass , & PPC :: CRBITRCRegClass , & PPC :: CTRRCRegClass , & PPC :: CTRRC8RegClass } ; bool Found = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { for ( unsigned c = 0 ; c < array_lengthof ( RCs ) && ! Found ; ++ c ) { const TargetRegisterClass * RC = RCs [ c ] ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && RC -> contains ( MO . getReg ( ) ) ) { Pred . push_back ( MO ) ; Found = true ; } } else if ( MO . isRegMask ( ) ) { for ( MCPhysReg R : * RC ) if ( MO . clobbersPhysReg ( R ) ) { Pred . push_back ( MO ) ; Found = true ; } } } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

PowerPC PPC PPC::CRRCRegClass PPC::CRBITRCRegClass PPC::CTRRCRegClass PPC::CTRRC8RegClass 0


<s> static bool mips_near_type_p ( const_tree type ) { return lookup_attribute ( "near" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Predicates to test for presence of `` near '' and `` far '' / '' long_call '' attributes on the given TYPE .


<s> bool LanaiRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s>
PPCTTI
::
PopcntSupportKind
PPCTTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
ST
->
hasPOPCNTD
(
)
&&
TyWidth
<=
64
)
return
PSK_FastHardware
;
return
PSK_Software
;
}
</s>

Return hardware support for population count .

PowerPC
PPC
PPC
"Ty width must be power of 2"
64


<s> static fixed_size_mode aarch64_get_reg_raw_mode ( int regno ) { if ( TARGET_SVE && FP_REGNUM_P ( regno ) ) return as_a < fixed_size_mode > ( V16QImode ) ; return default_get_reg_raw_mode ( regno ) ; } </s>


<s> const MCExpr * X86ELFTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_DTPOFF , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s>
int
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
needsStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
IgnoreSPUpdates
&&
!
TFI
->
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
return
getFrameIndexReferenceSP
(
MF
,
FI
,
FrameReg
,
StackSize
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool aarch_bti_j_insn_p ( rtx_insn * insn ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; rtx pat = PATTERN ( insn ) ; return GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == VUNSPEC_BTI_NOP ; } </s>


<s>
const
char
*
mips_output_equal_conditional_branch
(
rtx_insn
*
insn
,
rtx
*
operands
,
bool
inverted_p
)
{
const
char
*
branch
[
2
]
;
if
(
TARGET_MICROMIPS
&&
mips_isa_rev
<=
5
&&
operands
[
3
]
==
const0_rtx
&&
get_attr_length
(
insn
)
<=
8
)
{
if
(
mips_cb
==
MIPS_CB_OPTIMAL
)
{
branch
[
!
inverted_p
]
=
"%*b%C1z%:\t%2,%0"
;
branch
[
inverted_p
]
=
"%*b%N1z%:\t%2,%0"
;
}
else
{
branch
[
!
inverted_p
]
=
"%*b%C1z\t%2,%0%/"
;
branch
[
inverted_p
]
=
"%*b%N1z\t%2,%0%/"
;
}
}
else
if
(
TARGET_CB_MAYBE
)
{
if
(
operands
[
3
]
==
const0_rtx
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b%C1z"
,
"%2,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"b%N1z"
,
"%2,%0"
)
;
}
else
if
(
REGNO
(
operands
[
2
]
)
!=
REGNO
(
operands
[
3
]
)
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b%C1"
,
"%2,%3,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"b%N1"
,
"%2,%3,%0"
)
;
}
else
{
if
(
GET_CODE
(
operands
[
1
]
)
==
NE
)
inverted_p
=
!
inverted_p
;
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b"
,
"%0"
)
;
branch
[
inverted_p
]
=
"%*\t\t# branch never"
;
}
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH
(
"b%C1"
,
"%2,%z3,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH
(
"b%N1"
,
"%2,%z3,%0"
)
;
}
return
mips_output_conditional_branch
(
insn
,
operands
,
branch
[
1
]
,
branch
[
0
]
)
;
}
</s>

Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some equality condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; OPERANDS [ 3 ] is the second operand and may be zero or a register .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32r1"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32r1"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> static bool sparc_lra_p ( void ) { return TARGET_LRA ; } </s>

Return true if we use LRA instead of reload pass .


<s>
int
LC2200FrameLowering
::
getFrameIndexReference
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
)
const
{
int
offset
=
TargetFrameLowering
::
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
offset
%
4
==
0
&&
"4-byte addressibility"
)
;
return
offset
/
4
;
}
</s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> int ARMTargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) { if ( Subtarget -> hasFPAO ( ) ) return AM . Scale < 0 ? 1 : 0 ; return 0 ; } return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static inline HOST_WIDE_INT htm_spr_num ( enum rs6000_gen_builtins code ) { if ( code == RS6000_BIF_GET_TFHAR || code == RS6000_BIF_SET_TFHAR ) return TFHAR_SPR ; else if ( code == RS6000_BIF_GET_TFIAR || code == RS6000_BIF_SET_TFIAR ) return TFIAR_SPR ; else if ( code == RS6000_BIF_GET_TEXASR || code == RS6000_BIF_SET_TEXASR ) return TEXASR_SPR ; gcc_assert ( code == RS6000_BIF_GET_TEXASRU || code == RS6000_BIF_SET_TEXASRU ) ; return TEXASRU_SPR ; } </s>

Return the appropriate SPR number associated with the given builtin .


<s> bool X86Subtarget :: enableEarlyIfConversion ( ) const { return canUseCMOV ( ) && X86EarlyIfConv ; } </s>

Enable the use of the early if conversion pass .


Function that may creates more instructions for large value on adjusting stack pointer . In nds32 target , 'addi ' can be used for stack pointer adjustment in prologue/epilogue stage . However , sometimes there are too many local variables so that the adjustment value is not able to be fit in the 'addi ' instruction . One solution is to move value into a register and then use 'add ' instruction . In practice , we use TA_REGNUM ( $ r15 ) to accomplish this purpose .


<s> static void mips_avoid_hazard ( rtx_insn * after , rtx_insn * insn , int * hilo_delay , rtx * delayed_reg , rtx lo_reg ) { rtx pattern , set ; int nops , ninsns ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= 0 ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / 4 ; if ( ninsns == 0 ) return ; if ( * hilo_delay < 2 && reg_set_p ( lo_reg , pattern ) ) nops = 2 - * hilo_delay ; else if ( * delayed_reg != 0 && reg_referenced_p ( * delayed_reg , pattern ) ) nops = 1 ; else nops = 0 ; * hilo_delay += nops ; while ( nops -- > 0 ) emit_insn_after ( gen_hazard_nop ( ) , after ) ; * hilo_delay += ninsns ; * delayed_reg = 0 ; if ( INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_HILO : * hilo_delay = 0 ; break ; case HAZARD_DELAY : set = single_set ( insn ) ; gcc_assert ( set ) ; * delayed_reg = SET_DEST ( set ) ; break ; } } </s>

Subroutine of mips_reorg . If there is a hazard between INSN and a previous instruction , avoid it by inserting nops after instruction AFTER . * DELAYED_REG and * HILO_DELAY describe the hazards that apply at this point . If * DELAYED_REG is non-null , INSN must wait a cycle before using the value of that register . * HILO_DELAY counts the number of instructions since the last hilo hazard ( that is , the number of instructions since the last mflo or mfhi ) . After inserting nops for INSN , update * DELAYED_REG and * HILO_DELAY for the next instruction . LO_REG is an rtx for the LO register , used in dependence checking .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? Mips :: FP : Mips :: SP ; } </s>


<s> void thumb2_expand_return ( bool simple_return ) { int i , num_regs ; unsigned long saved_regs_mask ; arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = 0 , num_regs = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { if ( num_regs == 1 ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; XVECEXP ( par , 0 , 1 ) = gen_rtx_SET ( SImode , reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , 0 , 1 ) ) = 1 ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( 1 << LR_REGNUM ) ; saved_regs_mask |= ( 1 << PC_REGNUM ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; } } else { emit_jump_insn ( simple_return_rtx ) ; } } </s>


<s> bool LC3RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned OpId ; switch ( Inst . getOpcode ( ) ) { default : OpId = 0 ; if ( Inst . getNumOperands ( ) == 0 ) return false ; break ; case ARM :: MVE_WLSTP_8 : case ARM :: MVE_WLSTP_16 : case ARM :: MVE_WLSTP_32 : case ARM :: MVE_WLSTP_64 : case ARM :: t2WLS : case ARM :: MVE_LETP : case ARM :: t2LEUpdate : OpId = 2 ; break ; case ARM :: t2LE : OpId = 1 ; break ; } if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( OpId ) . getImm ( ) + 4 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> static void push_regs ( HARD_REG_SET * mask , int interrupt_handler ) { int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0 ; int skip_fpscr = 0 ; for ( ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_reg_set_intersect_p ( * mask , reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG ) ; COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = 1 ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = 0 ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + 1 ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = frame_insn ( x ) ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * 4 ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - 32 ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; } else for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) && ! sh_cfun_resbank_handler_p ( ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle , bool MinSize ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , ReservedGPRegisters ( ARM :: GPRRegClass . getNumRegs ( ) ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new ARMCallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new ARMLegalizerInfo ( * this ) ) ; auto * RBI = new ARMRegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createARMInstructionSelector ( * static_cast < const ARMBaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

ARM ARM ARM ARM ARM ARM::GPRRegClass ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s> static void xstormy16_print_operand_address ( FILE * file , machine_mode , rtx address ) { HOST_WIDE_INT offset ; int pre_dec , post_inc ; if ( CONST_INT_P ( address ) ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( address ) & 0xFFFF ) ; return ; } if ( CONSTANT_P ( address ) || LABEL_P ( address ) ) { output_addr_const ( file , address ) ; return ; } if ( GET_CODE ( address ) == PLUS ) { gcc_assert ( CONST_INT_P ( XEXP ( address , 1 ) ) ) ; offset = INTVAL ( XEXP ( address , 1 ) ) ; address = XEXP ( address , 0 ) ; } else offset = 0 ; pre_dec = ( GET_CODE ( address ) == PRE_DEC ) ; post_inc = ( GET_CODE ( address ) == POST_INC ) ; if ( pre_dec || post_inc ) address = XEXP ( address , 0 ) ; gcc_assert ( REG_P ( address ) ) ; fputc ( '(' , file ) ; if ( pre_dec ) fputs ( "--" , file ) ; fputs ( reg_names [ REGNO ( address ) ] , file ) ; if ( post_inc ) fputs ( "++" , file ) ; if ( offset != 0 ) fprintf ( file , "," HOST_WIDE_INT_PRINT_DEC , offset ) ; fputc ( ')' , file ) ; } </s>

Print a memory address as an operand to reference that memory location .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: R2 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! requiresRegisterScavenging ( MF ) ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
ATOMIC_LOAD_ADD
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMADD64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_AND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_NAND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMNAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_OR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_SUB
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSUB64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_XOR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMXOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSWAP64_DAG
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMCMPXCHG64_DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVector < MBBInfo , 16 > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / 4 ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { MF -> getInfo < MipsFunctionInfo > ( ) -> setEmitNOAT ( ) ; uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MipsCCState :: originalTypeIsF128 ( const Type * Ty , const char * Func ) { if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == 1 && Ty -> getStructElementType ( 0 ) -> isFP128Ty ( ) ) return true ; return ( Func && Ty -> isIntegerTy ( 128 ) && isF128SoftLibCall ( Func ) ) ; } </s>

This function returns true if Ty is fp128 , { f128 } or i128 which was originally a fp128 .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s>
unsigned
getMemSize
(
)
const
{
assert
(
Kind
==
Memory
&&
"Invalid access!"
)
;
return
Mem
.
Size
;
}
</s>

Returns the size in bytes of the memory access .


<s> bool fixupNeedsRelaxation ( const MCFixup & , uint64_t , const MCRelaxableFragment * , const MCAsmLayout & ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
VT
=
VA
.
getValVT
(
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VT
,
InFlag
)
.
getValue
(
1
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> unsigned int nds32_local_alignment ( tree local ATTRIBUTE_UNUSED , unsigned int basic_align ) { bool at_least_align_to_word = false ; switch ( TREE_CODE ( local ) ) { case ARRAY_TYPE : case RECORD_TYPE : case UNION_TYPE : at_least_align_to_word = true ; break ; default : at_least_align_to_word = false ; break ; } if ( at_least_align_to_word && ( basic_align < BITS_PER_WORD ) ) return BITS_PER_WORD ; else return basic_align ; } </s>


<s> void MipsSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { } </s>

Override generic scheduling policy within a region .


<s> static int function_arg_slotno ( const struct sparc_args * cum , enum machine_mode mode , tree type , int named , int incoming_p , int * pregno , int * ppadding ) { int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = 0 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != 0 ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) slotno ++ , * ppadding = 1 ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) == UNION_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } else { int intregs_p = 0 , fpregs_p = 0 , packed_p = 0 ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) fpregs_p = 1 ; else scan_record_type ( type , & intregs_p , & fpregs_p , & packed_p ) ; if ( packed_p || ! named ) fpregs_p = 0 , intregs_p = 1 ; if ( fpregs_p && slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( ! fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX ) return - 1 ; return slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s> void rs6000_split_lock_test_and_set ( rtx retval , rtx mem , rtx val , rtx scratch ) { enum machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond = gen_rtx_REG ( CCmode , CR0_REGNO ) ; emit_insn ( gen_memory_barrier ( ) ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; emit_move_insn ( scratch , val ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; emit_insn ( gen_isync ( ) ) ; } </s>

Expand an atomic test and set operation . MEM is the memory on which to operate . VAL is the value set . SCRATCH is a scratch GPR .


<s>
void
X86InstrInfo
::
genAlternativeCodeSequence
(
MachineInstr
&
Root
,
MachineCombinerPattern
::
MC_PATTERN
Pattern
,
SmallVectorImpl
<
MachineInstr
*
>
&
InsInstrs
,
SmallVectorImpl
<
MachineInstr
*
>
&
DelInstrs
,
DenseMap
<
unsigned
,
unsigned
>
&
InstIdxForVirtReg
)
const
{
MachineRegisterInfo
&
MRI
=
Root
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
Prev
=
nullptr
;
switch
(
Pattern
)
{
case
MachineCombinerPattern
::
MC_REASSOC_AX_BY
:
case
MachineCombinerPattern
::
MC_REASSOC_XA_BY
:
Prev
=
MRI
.
getUniqueVRegDef
(
Root
.
getOperand
(
1
)
.
getReg
(
)
)
;
break
;
case
MachineCombinerPattern
::
MC_REASSOC_AX_YB
:
case
MachineCombinerPattern
::
MC_REASSOC_XA_YB
:
Prev
=
MRI
.
getUniqueVRegDef
(
Root
.
getOperand
(
2
)
.
getReg
(
)
)
;
}
assert
(
Prev
&&
"Unknown pattern for machine combiner"
)
;
reassociateOps
(
Root
,
*
Prev
,
Pattern
,
InsInstrs
,
DelInstrs
,
InstIdxForVirtReg
)
;
return
;
}
</s>

When getMachineCombinerPatterns ( ) finds potential patterns , this function generates the instructions that could replace the original code sequence .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) || TT . isOSWindows ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool ix86_find_max_used_stack_alignment ( unsigned int & stack_alignment , bool check_stack_slot ) { HARD_REG_SET set_up_by_prologue , prologue_used ; basic_block bb ; CLEAR_HARD_REG_SET ( prologue_used ) ; CLEAR_HARD_REG_SET ( set_up_by_prologue ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , STACK_POINTER_REGNUM ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , ARG_POINTER_REGNUM ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( stack_alignment > crtl -> preferred_stack_boundary ) stack_alignment = crtl -> preferred_stack_boundary ; bool require_stack_frame = false ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) && requires_stack_frame_p ( insn , prologue_used , set_up_by_prologue ) ) { require_stack_frame = true ; if ( check_stack_slot ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) if ( MEM_P ( * iter ) && ( reg_mentioned_p ( stack_pointer_rtx , * iter ) || reg_mentioned_p ( frame_pointer_rtx , * iter ) ) ) { unsigned int alignment = MEM_ALIGN ( * iter ) ; if ( alignment > stack_alignment ) stack_alignment = alignment ; } } } } return require_stack_frame ; } </s>

Return true if stack frame is required . Update STACK_ALIGNMENT to the largest alignment , in bits , of stack slot used if stack frame is required and CHECK_STACK_SLOT is true .


<s> void mips_final_prescan_insn ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPEC_CONSTTABLE ) mips_set_text_contents_type ( asm_out_file , "__pool_" , XINT ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 0 ) , FALSE ) ; if ( mips_need_noat_wrapper_p ( insn , opvec , noperands ) ) mips_push_asm_switch ( & mips_noat ) ; } </s>


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr ) { if ( ! isSupportedType ( Val -> getType ( ) ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; ArgInfo ArgRetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , 0 , RetInfos , OrigArgIndices ) ; SmallVector < ISD :: OutputArg , 8 > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , RetInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool SystemZRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool BaseImplRetVal = TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM , Matrix ) ; if ( MRI -> getRegClass ( VirtReg ) == & SystemZ :: GRX32BitRegClass ) { SmallVector < unsigned , 8 > Worklist ; SmallSet < unsigned , 4 > DoneRegs ; Worklist . push_back ( VirtReg ) ; while ( Worklist . size ( ) ) { unsigned Reg = Worklist . pop_back_val ( ) ; if ( ! DoneRegs . insert ( Reg ) . second ) continue ; for ( auto & Use : MRI -> use_instructions ( Reg ) ) if ( Use . getOpcode ( ) == SystemZ :: LOCRMux ) { MachineOperand & TrueMO = Use . getOperand ( 1 ) ; MachineOperand & FalseMO = Use . getOperand ( 2 ) ; const TargetRegisterClass * RC = TRI -> getCommonSubClass ( getRC32 ( FalseMO , VRM , MRI ) , getRC32 ( TrueMO , VRM , MRI ) ) ; if ( RC && RC != & SystemZ :: GRX32BitRegClass ) { SmallSet < unsigned , 4 > CopyHints ; CopyHints . insert ( Hints . begin ( ) , Hints . end ( ) ) ; Hints . clear ( ) ; for ( MCPhysReg Reg : Order ) if ( CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; for ( MCPhysReg Reg : Order ) if ( ! CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; return true ; } unsigned OtherReg = ( TrueMO . getReg ( ) == Reg ? FalseMO . getReg ( ) : TrueMO . getReg ( ) ) ; if ( MRI -> getRegClass ( OtherReg ) == & SystemZ :: GRX32BitRegClass ) Worklist . push_back ( OtherReg ) ; } } } return BaseImplRetVal ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> static bool isReverseMask ( ArrayRef < int > M , EVT VT ) { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) ) return false ; for ( unsigned i = 0 ; i != NumElts ; ++ i ) if ( M [ i ] >= 0 && M [ i ] != ( int ) ( NumElts - 1 - i ) ) return false ; return true ; } </s>

Return true if this shuffle mask swaps the order of elements from exactly one source vector .


<s> static rtx construct_plt_address ( rtx symbol ) { rtx tmp , unspec ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; gcc_assert ( ix86_cmodel == CM_LARGE_PIC && ! TARGET_PECOFF ) ; gcc_assert ( Pmode == DImode ) ; tmp = gen_reg_rtx ( Pmode ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , symbol ) , UNSPEC_PLTOFF ) ; emit_move_insn ( tmp , gen_rtx_CONST ( Pmode , unspec ) ) ; emit_insn ( ix86_gen_add3 ( tmp , tmp , pic_offset_table_rtx ) ) ; return tmp ; } </s>

For given symbol ( function ) construct code to compute address of it 's PLT entry in large x86-64 PIC model .


<s> static rtx aapcs_vfp_allocate_return_reg ( enum arm_pcs pcs_variant ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { if ( ! use_vfp_abi ( pcs_variant , false ) ) return NULL ; if ( mode == BLKmode || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) >= GET_MODE_SIZE ( TImode ) && ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) ) { int count ; machine_mode ag_mode ; int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= 2 ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } return gen_rtx_REG ( mode , FIRST_VFP_REGNUM ) ; } </s>

Implement the allocate_return_reg field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt16 ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) ) . addReg ( StackReg ) . addReg ( StackReg ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const char * output_387_reg_move ( rtx_insn * insn , rtx * operands ) { if ( REG_P ( operands [ 0 ] ) ) { if ( REG_P ( operands [ 1 ] ) && find_regno_note ( insn , REG_DEAD , REGNO ( operands [ 1 ] ) ) ) { if ( REGNO ( operands [ 0 ] ) == FIRST_STACK_REG ) return output_387_ffreep ( operands , 0 ) ; return "fstp\t%y0" ; } if ( STACK_TOP_P ( operands [ 0 ] ) ) return "fld%Z1\t%y1" ; return "fst\t%y0" ; } else if ( MEM_P ( operands [ 0 ] ) ) { gcc_assert ( REG_P ( operands [ 1 ] ) ) ; if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ 1 ] ) ) ) return "fstp%Z0\t%y0" ; else { if ( GET_MODE ( operands [ 0 ] ) == XFmode ) return "fstp%Z0\t%y0\n\tfld%Z0\t%y0" ; else return "fst%Z0\t%y0" ; } } else gcc_unreachable ( ) ; } </s>

Output code to perform an x87 FP register move , from OPERANDS [ 1 ] to OPERANDS [ 0 ] .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { if ( Ord == SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; if ( isAtLeastRelease ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; return nullptr ; } </s>


<s> void altivec_expand_stvex_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx tmp = gen_reg_rtx ( mode ) ; rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( 1 , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( gen_rtx_SET ( op0 , stvx ) ) ; } </s>

Generate code for a `` stve * x '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


"SystemZ DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0


<s> static machine_mode hfa_element_mode ( const_tree type , bool nested ) { machine_mode element_mode = VOIDmode ; machine_mode mode ; enum tree_code code = TREE_CODE ( type ) ; int know_element_mode = 0 ; tree t ; if ( ! nested && ( ! TYPE_SIZE ( type ) || integer_zerop ( TYPE_SIZE ( type ) ) ) ) return VOIDmode ; switch ( code ) { case VOID_TYPE : case INTEGER_TYPE : case ENUMERAL_TYPE : case BOOLEAN_TYPE : case POINTER_TYPE : case OFFSET_TYPE : case REFERENCE_TYPE : case METHOD_TYPE : case LANG_TYPE : case FUNCTION_TYPE : return VOIDmode ; case COMPLEX_TYPE : if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_COMPLEX_FLOAT && TYPE_MODE ( type ) != TCmode ) return GET_MODE_INNER ( TYPE_MODE ( type ) ) ; else return VOIDmode ; case REAL_TYPE : if ( nested && TYPE_MODE ( type ) != TFmode ) return TYPE_MODE ( type ) ; else return VOIDmode ; case ARRAY_TYPE : return hfa_element_mode ( TREE_TYPE ( type ) , 1 ) ; case RECORD_TYPE : case UNION_TYPE : case QUAL_UNION_TYPE : for ( t = TYPE_FIELDS ( type ) ; t ; t = DECL_CHAIN ( t ) ) { if ( TREE_CODE ( t ) != FIELD_DECL ) continue ; mode = hfa_element_mode ( TREE_TYPE ( t ) , 1 ) ; if ( know_element_mode ) { if ( mode != element_mode ) return VOIDmode ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT ) return VOIDmode ; else { know_element_mode = 1 ; element_mode = mode ; } } return element_mode ; default : return VOIDmode ; } return VOIDmode ; } </s>

Check whether TYPE is a homogeneous floating point aggregate . If it is , return the mode of the floating point type that appears in all leafs . If it is not , return VOIDmode . An aggregate is a homogeneous floating point aggregate is if all fields/elements in it have the same floating point type ( e.g , SFmode ) . 128-bit quad-precision floats are excluded .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> SDValue X86TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , NegatibleCost & Cost , unsigned Depth ) const { if ( SDValue Arg = isFNEG ( DAG , Op . getNode ( ) , Depth ) ) { Cost = NegatibleCost :: Cheaper ; return DAG . getBitcast ( Op . getValueType ( ) , Arg ) ; } EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; SDNodeFlags Flags = Op . getNode ( ) -> getFlags ( ) ; switch ( Opc ) { case ISD :: FMA : case X86ISD :: FMSUB : case X86ISD :: FNMADD : case X86ISD :: FNMSUB : case X86ISD :: FMADD_RND : case X86ISD :: FMSUB_RND : case X86ISD :: FNMADD_RND : case X86ISD :: FNMSUB_RND : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == MVT :: f32 || SVT == MVT :: f64 ) || ! isOperationLegal ( ISD :: FMA , VT ) ) break ; if ( ! Flags . hasNoSignedZeros ( ) ) break ; SmallVector < SDValue , 4 > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = 0 ; i != 3 ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; bool NegA = ! ! NewOps [ 0 ] ; bool NegB = ! ! NewOps [ 1 ] ; bool NegC = ! ! NewOps [ 2 ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; Cost = ( NegA || NegB || NegC ) ? NegatibleCost :: Cheaper : NegatibleCost :: Neutral ; for ( int i = 0 , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } case X86ISD :: FRCP : if ( SDValue NegOp0 = getNegatedExpression ( Op . getOperand ( 0 ) , DAG , LegalOperations , ForCodeSize , Cost , Depth + 1 ) ) return DAG . getNode ( Opc , SDLoc ( Op ) , VT , NegOp0 ) ; break ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Cost , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> void addLiveInAttr ( unsigned VReg , ISD :: ArgFlagsTy Flags ) { LiveInAttrs . push_back ( std :: make_pair ( VReg , Flags ) ) ; } </s>

This function associates attributes for each live-in virtual register .


<s> static rtx aapcs_vfp_allocate_return_reg ( enum arm_pcs pcs_variant ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { if ( ! use_vfp_abi ( pcs_variant , false ) ) return NULL ; if ( mode == BLKmode || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) >= GET_MODE_SIZE ( TImode ) && ! TARGET_NEON ) ) { int count ; machine_mode ag_mode ; int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! TARGET_NEON ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= 2 ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } return gen_rtx_REG ( mode , FIRST_VFP_REGNUM ) ; } </s>


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static rtx sh_legitimize_address ( rtx x , rtx oldx , machine_mode mode ) { if ( flag_pic ) x = legitimize_pic_address ( oldx , mode , NULL_RTX ) ; if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return x ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && BASE_REGISTER_RTX_P ( XEXP ( x , 0 ) ) ) { struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( XEXP ( x , 1 ) ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = expand_binop ( Pmode , add_optab , XEXP ( x , 0 ) , adj . offset_adjust , NULL_RTX , 0 , OPTAB_LIB_WIDEN ) ; return gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; } } return x ; } </s>

Try to modify an illegitimate address and make it legitimate . If we find one , return the new , valid address . Otherwise , return the original address .


<s>
void
SystemZPostRASchedStrategy
::
enterMBB
(
MachineBasicBlock
*
NextMBB
)
{
assert
(
(
SchedStates
.
find
(
NextMBB
)
==
SchedStates
.
end
(
)
)
&&
"Entering MBB twice?"
)
;
DEBUG
(
dbgs
(
)
<<
"** Entering "
<<
printMBBReference
(
*
NextMBB
)
)
;
MBB
=
NextMBB
;
HazardRec
=
SchedStates
[
MBB
]
=
new
SystemZHazardRecognizer
(
TII
,
&
SchedModel
)
;
DEBUG
(
const
MachineLoop
*
Loop
=
MLI
->
getLoopFor
(
MBB
)
;
if
(
Loop
&&
Loop
->
getHeader
(
)
==
MBB
)
dbgs
(
)
<<
" (Loop header)"
;
dbgs
(
)
<<
":\n"
;
)
;
MachineBasicBlock
*
SinglePredMBB
=
getSingleSchedPred
(
MBB
,
MLI
->
getLoopFor
(
MBB
)
)
;
if
(
SinglePredMBB
==
nullptr
||
SchedStates
.
find
(
SinglePredMBB
)
==
SchedStates
.
end
(
)
)
return
;
DEBUG
(
dbgs
(
)
<<
"** Continued scheduling from "
<<
printMBBReference
(
*
SinglePredMBB
)
<<
"\n"
;
)
;
HazardRec
->
copyState
(
SchedStates
[
SinglePredMBB
]
)
;
DEBUG
(
HazardRec
->
dumpState
(
)
;
)
;
for
(
MachineBasicBlock
::
iterator
I
=
SinglePredMBB
->
getFirstTerminator
(
)
;
I
!=
SinglePredMBB
->
end
(
)
;
I
++
)
{
DEBUG
(
dbgs
(
)
<<
"** Emitting incoming branch: "
;
I
->
dump
(
)
;
)
;
bool
TakenBranch
=
(
I
->
isBranch
(
)
&&
(
TII
->
getBranchInfo
(
*
I
)
.
Target
->
isReg
(
)
||
TII
->
getBranchInfo
(
*
I
)
.
Target
->
getMBB
(
)
==
MBB
)
)
;
HazardRec
->
emitInstruction
(
&
*
I
,
TakenBranch
)
;
if
(
TakenBranch
)
break
;
}
}
</s>

Tell the strategy that MBB is about to be processed .

SystemZ
SystemZ
"Entering MBB twice?"
"** Entering "
SystemZ
" (Loop header)"
":\n"
"** Continued scheduling from "
"\n"
"** Emitting incoming branch: "


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> static int sh_address_cost ( rtx x , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return 2 ; if ( REG_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return 1 ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == GBR_REG && gbr_displacement ( XEXP ( x , 1 ) , mode ) ) return 2 ; const HOST_WIDE_INT offset = INTVAL ( XEXP ( x , 1 ) ) ; if ( offset == 0 ) return 1 ; if ( offset > 0 && offset <= sh_max_mov_insn_displacement ( mode , false ) ) return ( mode == HImode || mode == QImode ) ? 2 : 1 ; if ( TARGET_SH2A && offset > 0 && offset <= sh_max_mov_insn_displacement ( mode , true ) ) return 2 ; return 3 ; } if ( GET_CODE ( x ) == PLUS && ! CONSTANT_P ( XEXP ( x , 1 ) ) && ! TARGET_SHMEDIA ) return 3 ; return 10 ; } </s>

Compute the cost of an address . For the SH , all valid addresses are the same cost . Use a slightly higher cost for reg + reg addressing , since it increases pressure on r0 .


Output the assembly for a call instruction .


<s> void or1k_expand_call ( rtx retval , rtx fnaddr , rtx callarg1 , bool sibcall ) { rtx call , use = NULL ; if ( flag_pic && GET_CODE ( XEXP ( fnaddr , 0 ) ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( XEXP ( fnaddr , 0 ) ) ) { crtl -> uses_pic_offset_table = 1 ; rtx hard_pic = gen_rtx_REG ( Pmode , REAL_PIC_OFFSET_TABLE_REGNUM ) ; emit_move_insn ( hard_pic , pic_offset_table_rtx ) ; use_reg ( & use , hard_pic ) ; } if ( ! call_insn_operand ( XEXP ( fnaddr , 0 ) , Pmode ) ) { fnaddr = copy_to_mode_reg ( Pmode , XEXP ( fnaddr , 0 ) ) ; fnaddr = gen_rtx_MEM ( SImode , fnaddr ) ; } call = gen_rtx_CALL ( VOIDmode , fnaddr , callarg1 ) ; if ( retval ) call = gen_rtx_SET ( retval , call ) ; if ( ! sibcall ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , call , clob ) ) ; } call = emit_call_insn ( call ) ; CALL_INSN_FUNCTION_USAGE ( call ) = use ; } </s>

Expand the patterns `` call '' , `` sibcall '' , `` call_value '' and `` sibcall_value '' . Expands a function call where argument RETVAL is an optional RTX providing return value storage , the argument FNADDR is and RTX describing the function to call , the argument CALLARG1 is the number or registers used as operands and the argument SIBCALL should be true if this is a nested function call . If FNADDR is a non local symbol and FLAG_PIC is enabled this will generate a PLT call .


<s> void X86TTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { if ( ! UsePartialUnrolling ) return ; unsigned MaxBranches , MaxOps ; if ( PartialUnrollingThreshold . getNumOccurrences ( ) > 0 ) { MaxBranches = PartialUnrollingMaxBranches ; MaxOps = PartialUnrollingThreshold ; } else if ( ST -> isAtom ( ) ) { MaxBranches = 2 ; MaxOps = 10 ; } else if ( ST -> hasFSGSBase ( ) && ST -> hasXOP ( ) ) { MaxBranches = 16 ; MaxOps = 40 ; } else if ( ST -> hasFMA4 ( ) ) { return ; } else if ( ST -> hasAVX ( ) || ST -> hasSSE42 ( ) ) { MaxBranches = 8 ; MaxOps = 28 ; } else if ( ST -> hasSSSE3 ( ) ) { MaxBranches = 4 ; MaxOps = 18 ; } else { return ; } unsigned MaxDepth = 0 ; for ( df_iterator < BasicBlock * > DI = df_begin ( L -> getHeader ( ) ) , DE = df_end ( L -> getHeader ( ) ) ; DI != DE ; ) { if ( ! L -> contains ( * DI ) ) { DI . skipChildren ( ) ; continue ; } MaxDepth = std :: max ( MaxDepth , DI . getPathLength ( ) ) ; if ( MaxDepth > MaxBranches ) return ; for ( BasicBlock :: iterator I = DI -> begin ( ) , IE = DI -> end ( ) ; I != IE ; ++ I ) if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } ++ DI ; } UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP . PartialOptSizeThreshold = MaxOps ; if ( MaxDepth > 1 ) UP . MaxCount = ( MaxBranches - 1 ) / ( MaxDepth - 1 ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , RegKind Kind , SMLoc S , SMLoc E , MCContext & Ctx , AArch64_AM :: ShiftExtendType ExtTy = AArch64_AM :: LSL , unsigned ShiftAmount = 0 , unsigned HasExplicitAmount = false ) { auto Op = make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = Kind ; Op -> Reg . ElementWidth = 0 ; Op -> Reg . ShiftExtend . Type = ExtTy ; Op -> Reg . ShiftExtend . Amount = ShiftAmount ; Op -> Reg . ShiftExtend . HasExplicitAmount = HasExplicitAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool MipsAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t i = 0 , e = Count % 4 ; i != e ; ++ i ) OW -> Write8 ( 0 ) ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"%qs requires the %qs option and either the %qs or %qs option"

"%qs requires quad-precision floating-point arithmetic"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> reg_class_t csky_secondary_reload ( bool in_p ATTRIBUTE_UNUSED , rtx x , reg_class_t rclass , machine_mode mode , secondary_reload_info * sri ATTRIBUTE_UNUSED ) { int regno = - 1 ; if ( GET_CODE ( x ) == SIGN_EXTEND ) { int off = 0 ; x = XEXP ( x , 0 ) ; if ( reg_renumber ) regno = true_regnum ( x ) ; else { while ( GET_CODE ( x ) == SUBREG ) { off += subreg_regno_offset ( REGNO ( SUBREG_REG ( x ) ) , GET_MODE ( SUBREG_REG ( x ) ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) ; x = SUBREG_REG ( x ) ; } if ( GET_CODE ( x ) == REG ) regno = REGNO ( x ) + off ; } } else if ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( rclass == HILO_REGS && ! CSKY_GENERAL_REGNO_P ( regno ) ) return GENERAL_REGS ; if ( rclass == V_REGS && ! CSKY_GENERAL_REGNO_P ( regno ) ) { if ( MEM_P ( x ) && ( mode == SFmode || mode == DFmode ) ) return NO_REGS ; else return GENERAL_REGS ; } return NO_REGS ; } </s>

Implement TARGET_SECONDARY_RELOAD . If copying a register of RCLASS from/to X requires an intermediate register , the hook should return the REGISTER_CLASS required for this intermediate register . If no intermediate register is required , it should return NO_REGS . If more than one intermediate register is required , describe the one that is closest in the copy chain to the reload register .


<s> const ARMTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> static void detect_l2_cache ( struct cache_desc * level2 ) { unsigned eax , ebx , ecx , edx ; unsigned assoc ; __cpuid ( 0x80000006 , eax , ebx , ecx , edx ) ; level2 -> sizekb = ( ecx >> 16 ) & 0xffff ; level2 -> line = ecx & 0xff ; assoc = ( ecx >> 12 ) & 0xf ; if ( assoc == 6 ) assoc = 8 ; else if ( assoc == 8 ) assoc = 16 ; else if ( assoc >= 0xa && assoc <= 0xc ) assoc = 32 + ( assoc - 0xa ) * 16 ; else if ( assoc >= 0xd && assoc <= 0xe ) assoc = 96 + ( assoc - 0xd ) * 32 ; level2 -> assoc = assoc ; } </s>

Detect L2 cache parameters using CPUID extended function 0x80000006 .


<s> int arm_no_early_store_addr_dep ( rtx producer , rtx consumer ) { rtx value = arm_find_sub_rtx_with_code ( PATTERN ( producer ) , SET , false ) ; rtx addr = arm_find_sub_rtx_with_code ( PATTERN ( consumer ) , SET , false ) ; if ( value ) value = SET_DEST ( value ) ; if ( addr ) addr = SET_DEST ( addr ) ; if ( ! value || ! addr ) return 0 ; return ! reg_overlap_mentioned_p ( value , addr ) ; } </s>

Return nonzero if the CONSUMER instruction ( a store ) does not need PRODUCER 's value to calculate the address .


<s>
StringRef
CAHPMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_CAHP_LO
:
return
"lo"
;
case
VK_CAHP_HI
:
return
"hi"
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .

CAHP
CAHP
"Invalid ELF symbol kind"
CAHP
"lo"
CAHP
"hi"


<s> const char * aarch64_gen_far_branch ( rtx * operands , int pos_label , const char * dest , const char * branch_format ) { rtx_code_label * tmp_label = gen_label_rtx ( ) ; char label_buf [ 256 ] ; char buffer [ 128 ] ; ASM_GENERATE_INTERNAL_LABEL ( label_buf , dest , CODE_LABEL_NUMBER ( tmp_label ) ) ; const char * label_ptr = targetm . strip_name_encoding ( label_buf ) ; rtx dest_label = operands [ pos_label ] ; operands [ pos_label ] = tmp_label ; snprintf ( buffer , sizeof ( buffer ) , "%s%s" , branch_format , label_ptr ) ; output_asm_insn ( buffer , operands ) ; snprintf ( buffer , sizeof ( buffer ) , "b\t%%l%d\n%s:" , pos_label , label_ptr ) ; operands [ pos_label ] = dest_label ; output_asm_insn ( buffer , operands ) ; return "" ; } </s>

Generate code to enable conditional branches in functions over 1 MiB .


<s>
void
thumb1_final_prescan_insn
(
rtx_insn
*
insn
)
{
if
(
flag_print_asm_name
)
asm_fprintf
(
asm_out_file
,
"%@ 0x%04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
INSN_CODE
(
insn
)
!=
CODE_FOR_cbranchsi4_insn
)
{
enum
attr_conds
conds
;
if
(
cfun
->
machine
->
thumb1_cc_insn
)
{
if
(
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op0
,
insn
)
||
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op1
,
insn
)
)
CC_STATUS_INIT
;
}
conds
=
get_attr_conds
(
insn
)
;
if
(
conds
==
CONDS_SET
)
{
rtx
set
=
single_set
(
insn
)
;
cfun
->
machine
->
thumb1_cc_insn
=
insn
;
cfun
->
machine
->
thumb1_cc_op0
=
SET_DEST
(
set
)
;
cfun
->
machine
->
thumb1_cc_op1
=
const0_rtx
;
cfun
->
machine
->
thumb1_cc_mode
=
CC_NZmode
;
if
(
INSN_CODE
(
insn
)
==
CODE_FOR_thumb1_subsi3_insn
)
{
rtx
src1
=
XEXP
(
SET_SRC
(
set
)
,
1
)
;
if
(
src1
==
const0_rtx
)
cfun
->
machine
->
thumb1_cc_mode
=
CCmode
;
}
else
if
(
REG_P
(
SET_DEST
(
set
)
)
&&
REG_P
(
SET_SRC
(
set
)
)
)
{
cfun
->
machine
->
thumb1_cc_op0
=
SET_SRC
(
set
)
;
}
}
else
if
(
conds
!=
CONDS_NOCOND
)
cfun
->
machine
->
thumb1_cc_insn
=
NULL_RTX
;
}
if
(
cfun
->
machine
->
lr_save_eliminated
&&
get_attr_far_jump
(
insn
)
==
FAR_JUMP_YES
)
internal_error
(
"Unexpected thumb1 far jump"
)
;
}
</s>

Scan INSN just before assembler is output for it . For Thumb-1 , we track the status of the condition codes ; this information is used in the cbranchsi4_insn pattern .

arm
"%@ 0x%04x\n"
1
"Unexpected thumb1 far jump"


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI -> getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 1 , 2 ) ; } return false ; } default : if ( isFMA3 ( MI -> getOpcode ( ) ) ) return findFMA3CommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return false ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> static bool rs6000_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] ; unsigned from_nregs = hard_regno_nregs [ FIRST_FPR_REGNO ] [ from ] ; if ( TARGET_IEEEQUAD && ( to == TFmode || from == TFmode ) ) return true ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return true ; if ( from_size < 8 || to_size < 8 ) return true ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return true ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return true ; return false ; } else return false ; } if ( TARGET_E500_DOUBLE && ( ( ( ( to ) == DFmode ) + ( ( from ) == DFmode ) ) == 1 || ( ( ( to ) == TFmode ) + ( ( from ) == TFmode ) ) == 1 || ( ( ( to ) == DDmode ) + ( ( from ) == DDmode ) ) == 1 || ( ( ( to ) == TDmode ) + ( ( from ) == TDmode ) ) == 1 || ( ( ( to ) == DImode ) + ( ( from ) == DImode ) ) == 1 ) ) return true ; if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs [ FIRST_FPR_REGNO ] [ to ] > num_regs || hard_regno_nregs [ FIRST_FPR_REGNO ] [ from ] > num_regs ) return true ; return ( from_size != 8 && from_size != 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return true ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( from ) + SPE_VECTOR_MODE ( to ) ) == 1 && reg_classes_intersect_p ( GENERAL_REGS , rclass ) ) return true ; return false ; } </s>

Return nonzero if for CLASS a mode change from FROM to TO is invalid .


<s> void sh_remove_reg_dead_or_unused_notes ( rtx_insn * i , int regno ) { if ( rtx n = find_regno_note ( i , REG_DEAD , regno ) ) remove_note ( i , n ) ; if ( rtx n = find_regno_note ( i , REG_UNUSED , regno ) ) remove_note ( i , n ) ; } </s>

Given an insn and a reg number , remove reg dead or reg unused notes to mark it as being used after the insn .


<s> rtx extract_movd44_odd_reg ( rtx_insn * insn ) { gcc_assert ( movd44_insn_p ( insn ) ) ; rtx def_reg = SET_DEST ( PATTERN ( insn ) ) ; machine_mode mode ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; switch ( GET_MODE ( def_reg ) ) { case E_DImode : mode = SImode ; break ; case E_DFmode : mode = SFmode ; break ; default : gcc_unreachable ( ) ; } return gen_highpart ( mode , def_reg ) ; } </s>

Extract the second result ( odd reg ) of a movd44 insn .


<s> static machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_WIDER_MODE ( o ) . require ( ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * 2 ) ; gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return n ; } </s>

Get a vector mode of the same size as the original but with elements twice as wide . This is only guaranteed to apply to integral vectors .


<s> bool X86TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return Imm == ( int32_t ) Imm ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> bool mips_can_use_return_insn ( void ) { if ( cfun -> machine -> interrupt_handler_p ) return false ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return false ; return ( cfun -> machine -> frame . total_size == 0 && ! cfun -> machine -> use_frame_header_for_callee_saved_regs ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , int FrameIndex ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static void i386_pe_seh_fini ( FILE * f , bool cold ) { struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; seh = cfun -> machine -> seh ; if ( cold != seh -> in_cold_section ) return ; XDELETE ( seh ) ; cfun -> machine -> seh = NULL ; fputs ( "\t.seh_endproc\n" , f ) ; } </s>

Emit an assembler directive for the end of the function .


<s> void print_operand_address ( FILE * file , rtx x ) { if ( REG_P ( x ) ) fprintf ( file , "0(%s)" , reg_names [ REGNO ( x ) ] ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) { output_addr_const ( file , x ) ; if ( small_data_operand ( x , GET_MODE ( x ) ) ) fprintf ( file , "@%s(%s)" , SMALL_DATA_RELOC , reg_names [ SMALL_DATA_REG ] ) ; else gcc_assert ( ! TARGET_TOC ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REG_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == 0 ) fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC "(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { fprintf ( file , "lo16(" ) ; output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , ")(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false , & tocrel_base_oac , & tocrel_offset_oac ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base_oac ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "(%s)" , reg_names [ REGNO ( XVECEXP ( tocrel_base_oac , 0 , 1 ) ) ] ) ; } else gcc_unreachable ( ) ; } </s>

Print the operand address represented by the rtx addr


<s> void SparcTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( nullptr , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> bool LanaiInstrInfo :: getMemOperandWithOffset ( MachineInstr & LdSt , MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { switch ( LdSt . getOpcode ( ) ) { default : return false ; case Lanai :: LDW_RI : case Lanai :: LDW_RR : case Lanai :: SW_RR : case Lanai :: SW_RI : case Lanai :: LDHs_RI : case Lanai :: LDHz_RI : case Lanai :: STH_RI : case Lanai :: LDBs_RI : case Lanai :: LDBz_RI : unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> static bool originalTypeIsF128 ( const Type * Ty , const char * Func ) { if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == 1 && Ty -> getStructElementType ( 0 ) -> isFP128Ty ( ) ) return true ; return ( Func && Ty -> isIntegerTy ( 128 ) && isF128SoftLibCall ( Func ) ) ; } </s>

This function returns true if Ty is fp128 , { f128 } or i128 which was originally a fp128 .


<s> static bool arm_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if a type must be passed in memory . For AAPCS , small aggregates ( padded to the size of a word ) should be passed in a register .


<s> const uint16_t * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_SaveList : CSR_SVR464_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static inline int atomic_alloc ( unsigned int * mask ) { unsigned int old = * mask , ret , new ; while ( 1 ) { if ( old == 0 ) return - 1 ; ret = old & - old ; new = old & ~ ret ; new = __sync_val_compare_and_swap ( mask , old , new ) ; if ( old == new ) break ; old = new ; } return __builtin_ffs ( ret ) - 1 ; } </s>

MASK is a bitmap describing the allocation state of emergency buffers , with bit set indicating free . Return > = 0 if allocation is successful ; < 0 if failure .


<s> bool ix86_vec_interleave_v2df_operator_ok ( rtx operands [ 3 ] , bool high ) { if ( MEM_P ( operands [ 0 ] ) ) return rtx_equal_p ( operands [ 0 ] , operands [ 1 + high ] ) ; if ( MEM_P ( operands [ 1 ] ) && MEM_P ( operands [ 2 ] ) ) return TARGET_SSE3 && rtx_equal_p ( operands [ 1 ] , operands [ 2 ] ) ; return true ; } </s>

Return TRUE if the operands to a vec_interleave_ { high , low } v2df are ok , keeping in mind the possible movddup alternative .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax_rex"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
64
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static void ix86_conditional_register_usage ( void ) { int i , c_mask ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } c_mask = ( TARGET_64BIT_MS_ABI ? ( 1 << 3 ) : TARGET_64BIT ? ( 1 << 2 ) : ( 1 << 1 ) ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_SSE ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) SSE_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) FLOAT_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } if ( ! TARGET_MPX ) for ( i = FIRST_BND_REG ; i <= LAST_BND_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } </s>

Update register usage after having seen the compiler flags .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"%<-g%> with %<-mno-apcs-frame%> may not give sensible "

"cannot use %<-mtp=cp15%> with 16-bit Thumb"

"%s only supports non-pic code on M-profile targets with the "

"%s only supports non-pic code on M-profile targets"

"%s incompatible with %<-mword-relocations%>"

Check any incompatible options that the user has specified .


<s>
void
FISCMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

FISC
FISC
4
"Unexpected instruction size!"


"missing name in %<target(\"arch=\")%> pragma or attribute"

"invalid name (\"%s\") in %<target(\"arch=\")%> pragma or attribute"

"invalid feature modifier %s of value (\"%s\") in "

Handle the ARCH_STR argument to the arch= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> bool umips_movep_target_p ( rtx reg1 , rtx reg2 ) { int regno1 , regno2 , pair ; unsigned int i ; static const int match [ 8 ] = { 0x00000060 , 0x000000a0 , 0x000000c0 , 0x00200010 , 0x00400010 , 0x00000030 , 0x00000050 , 0x00000090 } ; if ( ! REG_P ( reg1 ) || ! REG_P ( reg2 ) ) return false ; regno1 = REGNO ( reg1 ) ; regno2 = REGNO ( reg2 ) ; if ( ! GP_REG_P ( regno1 ) || ! GP_REG_P ( regno2 ) ) return false ; pair = ( 1 << regno1 ) | ( 1 << regno2 ) ; for ( i = 0 ; i < ARRAY_SIZE ( match ) ; i ++ ) if ( pair == match [ i ] ) return true ; return false ; } </s>

Return true if REG1 and REG2 match the criteria for a movep insn .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetSPMoveOp ( ) ; if ( MFI . getStackSize ( ) == 0 && ! MFI . adjustsStack ( ) ) return ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


Enable AARCH64_FL_ * flags EXTRA_FLAGS on top of the base Advanced SIMD set .


<s> CAHPSubtarget & CAHPSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static bool arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_VFP_BASE && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( IS_VPR_REGNUM ( regno ) ) return mode == HImode || mode == V16BImode || mode == V8BImode || mode == V4BImode ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_VFP_BASE && IS_VFP_REGNUM ( regno ) ) { if ( mode == DFmode || mode == DImode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode || mode == BFmode || mode == HImode || mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; if ( TARGET_HAVE_MVE ) return ( ( VALID_MVE_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ) ; return false ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return false ; if ( TARGET_THUMB2 && ! ( TARGET_HAVE_MVE || TARGET_CDE ) ) return true ; return ! ( ( TARGET_LDRD || TARGET_CDE ) && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return false ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> bool PPCFunctionInfo :: isLiveInSExt ( Register VReg ) const { for ( const std :: pair < Register , ISD :: ArgFlagsTy > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isSExt ( ) ; return false ; } </s>

This function returns true if the specified vreg is a live-in register and sign-extended .


<s>
void
Comet2DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"### Select\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static bool csky_allocate_stack_slots_for_args ( void ) { return ! CSKY_FUNCTION_IS_NAKED ( get_csky_current_func_type ( ) ) ; } </s>


<s> static bool ia64_needs_block_p ( ds_t ts ) { if ( ts & BEGIN_DATA ) return ! mflag_sched_spec_ldc ; gcc_assert ( ( ts & BEGIN_CONTROL ) != 0 ) ; return ! ( mflag_sched_spec_control_ldc && mflag_sched_spec_ldc ) ; } </s>

Return nonzero , if INSN needs branchy recovery check .


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
0
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>