<s> MachineBasicBlock :: iterator PPCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; const DebugLoc & dl = I -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool hasVectorBlend ( ) const override { return true ; } </s>

Return true if the target has a vector blend instruction .


<s> static const char * mips_get_compress_on_name ( unsigned int flags ) { if ( flags == MASK_MIPS16 ) return "mips16" ; return "micromips" ; } </s>

Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS flags FLAGS .


Return an array that contains the bitmask target flag values and their names .

ARM ARM ARM "arm-got" "arm-sbrel" "arm-dllimport" "arm-secrel" "arm-nonlazy"


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static void emit_final_compare_vec ( rtx str1 , rtx str2 , rtx result , rtx s1addr , rtx s2addr , rtx orig_src1 , rtx orig_src2 , rtx off_reg , rtx vec_result ) { if ( TARGET_P9_VECTOR ) { rtx diffix = gen_reg_rtx ( SImode ) ; rtx chr1 = gen_reg_rtx ( SImode ) ; rtx chr2 = gen_reg_rtx ( SImode ) ; rtx chr1_di = simplify_gen_subreg ( DImode , chr1 , SImode , 0 ) ; rtx chr2_di = simplify_gen_subreg ( DImode , chr2 , SImode , 0 ) ; emit_insn ( gen_vclzlsbb_v16qi ( diffix , vec_result ) ) ; emit_insn ( gen_vextublx ( chr1 , diffix , str1 ) ) ; emit_insn ( gen_vextublx ( chr2 , diffix , str2 ) ) ; do_sub3 ( result , chr1_di , chr2_di ) ; } else { gcc_assert ( TARGET_P8_VECTOR ) ; rtx diffix = gen_reg_rtx ( DImode ) ; rtx result_gbbd = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_p8v_vgbbd ( result_gbbd , vec_result ) ) ; rtx result_shifted = gen_reg_rtx ( V16QImode ) ; int shift_amt = ( BYTES_BIG_ENDIAN ) ? 7 : 9 ; emit_insn ( gen_altivec_vsldoi_v16qi ( result_shifted , result_gbbd , result_gbbd , GEN_INT ( shift_amt ) ) ) ; rtx diffix_df = simplify_gen_subreg ( DFmode , diffix , DImode , 0 ) ; emit_insn ( gen_p8_mfvsrd_3_v16qi ( diffix_df , result_shifted ) ) ; rtx count = gen_reg_rtx ( DImode ) ; if ( BYTES_BIG_ENDIAN ) emit_insn ( gen_clzdi2 ( count , diffix ) ) ; else emit_insn ( gen_ctzdi2 ( count , diffix ) ) ; do_add3 ( off_reg , off_reg , count ) ; rtx chr1 = gen_reg_rtx ( QImode ) ; rtx chr2 = gen_reg_rtx ( QImode ) ; rtx addr1 = gen_rtx_PLUS ( Pmode , s1addr , off_reg ) ; do_load_for_compare_from_addr ( QImode , chr1 , addr1 , orig_src1 ) ; rtx addr2 = gen_rtx_PLUS ( Pmode , s2addr , off_reg ) ; do_load_for_compare_from_addr ( QImode , chr2 , addr2 , orig_src2 ) ; machine_mode rmode = GET_MODE ( result ) ; rtx chr1_rm = simplify_gen_subreg ( rmode , chr1 , QImode , 0 ) ; rtx chr2_rm = simplify_gen_subreg ( rmode , chr2 , QImode , 0 ) ; do_sub3 ( result , chr1_rm , chr2_rm ) ; } return ; } </s>

Generate the final sequence that identifies the differing byte and generates the final result , taking into account zero bytes : P8 : vgbbd 0,0 vsldoi 0,0,0,9 mfvsrd 9,32 addi 10,9 , -1 # count trailing zero bits andc 9,10,9 popcntd 9,9 lbzx 10,28,9 # use that offset to load differing byte lbzx 3,29,9 subf 3,3,10 # subtract for final result P9 : vclzlsbb # counts trailing bytes with lsb=0 vextublx # extract differing byte STR1 is the reg rtx for data from string 1 . STR2 is the reg rtx for data from string 2 . RESULT is the reg rtx for the comparison result . S1ADDR is the register to use for the base address of the first string . S2ADDR is the register to use for the base address of the second string . ORIG_SRC1 is the unmodified rtx for the first string . ORIG_SRC2 is the unmodified rtx for the second string . OFF_REG is the register to use for the string offset for loads . VEC_RESULT is the rtx for the vector result indicating the byte difference .


Return true if C is an acceptable character inside a symbol name .


<s>
void
PPCHazardRecognizer970
::
EmitInstruction
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
Opcode
==
PPC
::
MTCTR
)
HasCTRSet
=
true
;
if
(
isStore
)
{
unsigned
ThisStoreSize
;
switch
(
Opcode
)
{
default
:
assert
(
0
&&
"Unknown store instruction!"
)
;
case
PPC
::
STB
:
case
PPC
::
STB8
:
case
PPC
::
STBU
:
case
PPC
::
STBU8
:
case
PPC
::
STBX
:
case
PPC
::
STBX8
:
case
PPC
::
STVEBX
:
ThisStoreSize
=
1
;
break
;
case
PPC
::
STH
:
case
PPC
::
STH8
:
case
PPC
::
STHU
:
case
PPC
::
STHU8
:
case
PPC
::
STHX
:
case
PPC
::
STHX8
:
case
PPC
::
STVEHX
:
case
PPC
::
STHBRX
:
ThisStoreSize
=
2
;
break
;
case
PPC
::
STFS
:
case
PPC
::
STFSU
:
case
PPC
::
STFSX
:
case
PPC
::
STWX
:
case
PPC
::
STWX8
:
case
PPC
::
STWUX
:
case
PPC
::
STW
:
case
PPC
::
STW8
:
case
PPC
::
STWU
:
case
PPC
::
STWU8
:
case
PPC
::
STVEWX
:
case
PPC
::
STFIWX
:
case
PPC
::
STWBRX
:
ThisStoreSize
=
4
;
break
;
case
PPC
::
STD_32
:
case
PPC
::
STDX_32
:
case
PPC
::
STD
:
case
PPC
::
STDU
:
case
PPC
::
STFD
:
case
PPC
::
STFDX
:
case
PPC
::
STDX
:
case
PPC
::
STDUX
:
ThisStoreSize
=
8
;
break
;
case
PPC
::
STVX
:
case
PPC
::
STVXL
:
ThisStoreSize
=
16
;
break
;
}
StoreSize
[
NumStores
]
=
ThisStoreSize
;
StorePtr1
[
NumStores
]
=
Node
->
getOperand
(
1
)
;
StorePtr2
[
NumStores
]
=
Node
->
getOperand
(
2
)
;
++
NumStores
;
}
if
(
InstrType
==
PPCII
::
PPC970_BRU
||
isSingle
)
NumIssued
=
4
;
++
NumIssued
;
if
(
isCracked
)
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int neon_immediate_valid_for_shift ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth , bool isleftshift ) { unsigned int innersize = GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; unsigned int n_elts = CONST_VECTOR_NUNITS ( op ) , i ; unsigned HOST_WIDE_INT last_elt = 0 ; unsigned HOST_WIDE_INT maxshift ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( op , i ) ; unsigned HOST_WIDE_INT elpart ; if ( CONST_INT_P ( el ) ) elpart = INTVAL ( el ) ; else if ( CONST_DOUBLE_P ( el ) ) return 0 ; else gcc_unreachable ( ) ; if ( i != 0 && elpart != last_elt ) return 0 ; last_elt = elpart ; } maxshift = innersize * 8 ; if ( isleftshift ) { if ( last_elt >= maxshift ) return 0 ; } else { if ( last_elt == 0 || last_elt > maxshift ) return 0 ; } if ( elementwidth ) * elementwidth = innersize * 8 ; if ( modconst ) * modconst = CONST_VECTOR_ELT ( op , 0 ) ; return 1 ; } </s>

Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction . If the immediate is valid , write a constant suitable for using as an operand to VSHR/VSHL to * MODCONST and the corresponding element width to * ELEMENTWIDTH . ISLEFTSHIFT is for determine left or right shift , because they have different limitations .


<s> bool UPTFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static int indirectable_constant_address_p ( rtx x ) { return CONSTANT_ADDRESS_P ( x ) ; } </s>

Re-definition of CONSTANT_ADDRESS_P , which is true only when there are no SYMBOL_REFs for external symbols present .


<s> void PPCInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , 4 > NewMIs ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs ) ) { PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( ) ; } for ( unsigned i = 0 , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
void
PPCMIPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
MRI
=
&
MF
->
getRegInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
MPDT
=
&
getAnalysis
<
MachinePostDominatorTree
>
(
)
;
MBFI
=
&
getAnalysis
<
MachineBlockFrequencyInfo
>
(
)
;
EntryFreq
=
MBFI
->
getEntryFreq
(
)
;
TII
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** PowerPC MI peephole pass ***\n\n"
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

PowerPC
PPC
PPC
"*** PowerPC MI peephole pass ***\n\n"


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return RegisterVT ; } if ( VT == MVT :: v3f16 && Subtarget . hasFP16 ( ) ) return MVT :: v8f16 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> int get_dest_uid ( rtx label , int max_uid ) { rtx dest = next_real_insn ( label ) ; int dest_uid ; if ( ! dest ) return 0 ; dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( GET_CODE ( dest ) == JUMP_INSN && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return 0 ; return dest_uid ; } </s>

Return the UID of the insn that follows the specified label .


<s> static void mips_end_ll_sc_sync_block ( void ) { if ( ! ISA_HAS_LL_SC ) output_asm_insn ( ".set\tpop" , 0 ) ; } </s>

End a block started by mips_start_ll_sc_sync_block .


<s> static int find_r0_life_regions ( basic_block b ) { rtx_insn * end , * insn ; rtx pset ; rtx r0_reg ; int live ; int set ; int death = 0 ; if ( REGNO_REG_SET_P ( df_get_live_in ( b ) , R0_REG ) ) { set = 1 ; live = 1 ; } else { set = 0 ; live = 0 ; } insn = BB_HEAD ( b ) ; end = BB_END ( b ) ; r0_reg = gen_rtx_REG ( SImode , R0_REG ) ; while ( 1 ) { if ( INSN_P ( insn ) ) { if ( find_regno_note ( insn , REG_DEAD , R0_REG ) ) { death ++ ; live = 0 ; } if ( ! live && ( pset = single_set ( insn ) ) && reg_overlap_mentioned_p ( r0_reg , SET_DEST ( pset ) ) && ! find_regno_note ( insn , REG_UNUSED , R0_REG ) ) { set ++ ; live = 1 ; } } if ( insn == end ) break ; insn = NEXT_INSN ( insn ) ; } return set - death ; } </s>


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , const BranchProbability & Probability ) const override { return true ; } </s>


<s> void PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool ARMBaseRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : case AArch64 :: FPR64_loRegClassID : case AArch64 :: FPR16_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> Sched :: Preference PPCTargetLowering :: getSchedulingPreference ( SDNode * N ) const { if ( DisableILPPref || PPCSubTarget . enableMachineScheduler ( ) ) return TargetLowering :: getSchedulingPreference ( N ) ; return Sched :: ILP ; } </s>


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool VectorRegs = ( ClassID == 1 ) ; if ( VectorRegs ) { return 0 ; } return 64 ; } </s>


<s> bool rs6000_is_valid_mask ( rtx mask , int * b , int * e , machine_mode mode ) { unsigned HOST_WIDE_INT val = INTVAL ( mask ) ; unsigned HOST_WIDE_INT bit ; int nb , ne ; int n = GET_MODE_PRECISION ( mode ) ; if ( mode != DImode && mode != SImode ) return false ; if ( INTVAL ( mask ) >= 0 ) { bit = val & - val ; ne = exact_log2 ( bit ) ; nb = exact_log2 ( val + bit ) ; } else if ( val + 1 == 0 ) { nb = n ; ne = 0 ; } else if ( val & 1 ) { val = ~ val ; bit = val & - val ; nb = exact_log2 ( bit ) ; ne = exact_log2 ( val + bit ) ; } else { bit = val & - val ; ne = exact_log2 ( bit ) ; if ( val + bit == 0 ) nb = n ; else nb = 0 ; } nb -- ; if ( nb < 0 || ne < 0 || nb >= n || ne >= n ) return false ; if ( b ) * b = nb ; if ( e ) * e = ne ; return true ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwinm , rldicl , rldicr , or rldic instruction in mode MODE . If so , if E is not zero , store there the bit offset ( counted from the right ) where the single stretch of 1 bits begins ; and similarly for B , the bit offset where it ends .


<s> void ix86_expand_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx mask , set , dst , src ; bool use_sse = false ; bool vector_mode = VECTOR_MODE_P ( mode ) ; machine_mode vmode = mode ; if ( vector_mode ) use_sse = true ; else if ( mode == TFmode ) use_sse = true ; else if ( TARGET_SSE_MATH ) { use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; } if ( use_sse ) mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; else mask = NULL_RTX ; dst = operands [ 0 ] ; src = operands [ 1 ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( dst , set ) ; if ( mask ) { rtx use , clob ; rtvec par ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode ) par = gen_rtvec ( 2 , set , use ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 3 , set , use , clob ) ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } else emit_insn ( set ) ; } </s>

Generate code for floating point ABS or NEG .


<s> bool x86_extended_QIreg_mentioned_p ( rtx_insn * insn ) { int i ; extract_insn_cached ( insn ) ; for ( i = 0 ; i < recog_data . n_operands ; i ++ ) if ( GENERAL_REG_P ( recog_data . operand [ i ] ) && ! QI_REGNO_P ( REGNO ( recog_data . operand [ i ] ) ) ) return true ; return false ; } </s>

Return nonzero when QImode register that must be represented via REX prefix is used .


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; mode = mode_for_size ( bits , MODE_INT , 0 ) ; delta = bits / BITS_PER_UNIT ; regs = alloca ( sizeof ( rtx ) * length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; if ( ! mips_expand_unaligned_load ( regs [ i ] , part , bits , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; if ( ! mips_expand_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> bool ix86_operands_ok_for_move_multiple ( rtx * operands , bool load , machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) != REGNO ( reg_2 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 + msize != offval_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into move multiple . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return 0 ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
static
void
arm_unwind_emit
(
FILE
*
out_file
,
rtx_insn
*
insn
)
{
rtx
note
,
pat
;
bool
handled_one
=
false
;
if
(
arm_except_unwind_info
(
&
global_options
)
!=
UI_TARGET
)
return
;
if
(
!
(
flag_unwind_tables
||
crtl
->
uses_eh_lsda
)
&&
(
TREE_NOTHROW
(
current_function_decl
)
||
crtl
->
all_throwers_are_sibcalls
)
)
return
;
if
(
NOTE_P
(
insn
)
||
!
RTX_FRAME_RELATED_P
(
insn
)
)
return
;
for
(
note
=
REG_NOTES
(
insn
)
;
note
;
note
=
XEXP
(
note
,
1
)
)
{
switch
(
REG_NOTE_KIND
(
note
)
)
{
case
REG_FRAME_RELATED_EXPR
:
pat
=
XEXP
(
note
,
0
)
;
goto
found
;
case
REG_CFA_REGISTER
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
{
pat
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pat
)
==
PARALLEL
)
pat
=
XVECEXP
(
pat
,
0
,
0
)
;
}
{
rtx
dest
,
src
;
unsigned
reg
;
src
=
SET_SRC
(
pat
)
;
dest
=
SET_DEST
(
pat
)
;
gcc_assert
(
src
==
stack_pointer_rtx
||
IS_PAC_REGNUM
(
REGNO
(
src
)
)
)
;
reg
=
REGNO
(
dest
)
;
if
(
IS_PAC_REGNUM
(
REGNO
(
src
)
)
)
arm_unwind_emit_set
(
out_file
,
PATTERN
(
insn
)
)
;
else
asm_fprintf
(
out_file
,
"\t.unwind_raw 0, 0x%x @ vsp = r%d\n"
,
reg
+
0x90
,
reg
)
;
}
handled_one
=
true
;
break
;
case
REG_CFA_DEF_CFA
:
case
REG_CFA_ADJUST_CFA
:
case
REG_CFA_RESTORE
:
return
;
case
REG_CFA_EXPRESSION
:
case
REG_CFA_OFFSET
:
gcc_unreachable
(
)
;
default
:
break
;
}
}
if
(
handled_one
)
return
;
pat
=
PATTERN
(
insn
)
;
found
:
switch
(
GET_CODE
(
pat
)
)
{
case
SET
:
arm_unwind_emit_set
(
out_file
,
pat
)
;
break
;
case
SEQUENCE
:
arm_unwind_emit_sequence
(
out_file
,
pat
)
;
break
;
default
:
abort
(
)
;
}
}
</s>

Emit unwind directives for the given insn .


<s> bool ARMTargetLowering :: splitValueIntoRegisterParts ( SelectionDAG & DAG , const SDLoc & DL , SDValue Val , SDValue * Parts , unsigned NumParts , MVT PartVT , Optional < CallingConv :: ID > CC ) const { bool IsABIRegCopy = CC . hasValue ( ) ; EVT ValueVT = Val . getValueType ( ) ; if ( IsABIRegCopy && ( ValueVT == MVT :: f16 || ValueVT == MVT :: bf16 ) && PartVT == MVT :: f32 ) { unsigned ValueBits = ValueVT . getSizeInBits ( ) ; unsigned PartBits = PartVT . getSizeInBits ( ) ; Val = DAG . getNode ( ISD :: BITCAST , DL , MVT :: getIntegerVT ( ValueBits ) , Val ) ; Val = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: getIntegerVT ( PartBits ) , Val ) ; Val = DAG . getNode ( ISD :: BITCAST , DL , PartVT , Val ) ; Parts [ 0 ] = Val ; return true ; } return false ; } </s>

Target-specific splitting of values into parts that fit a register storing a legal type .


<s> static const TargetRegisterClass * getRegClass ( const MachineInstr & MI , Register Reg ) { if ( MI . getParent ( ) == nullptr ) return nullptr ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; return MF ? MF -> getRegInfo ( ) . getRegClassOrNull ( Reg ) : nullptr ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> bool mips_9bit_offset_address_p ( rtx x , machine_mode mode ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && MIPS_9BIT_OFFSET_P ( INTVAL ( addr . offset ) ) ) ; } </s>

Return true if X is a legitimate address with a 9-bit offset . MODE is the mode of the value being accessed .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicCmpXchgIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicCmpXchgInst
*
CI
,
Value
*
AlignedAddr
,
Value
*
CmpVal
,
Value
*
NewVal
,
Value
*
Mask
,
AtomicOrdering
Ord
)
const
{
assert
(
shouldInlineQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
CmpVal
->
getType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
IntCmpXchg
=
Intrinsic
::
getDeclaration
(
M
,
Intrinsic
::
ppc_cmpxchg_i128
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
CmpLo
=
Builder
.
CreateTrunc
(
CmpVal
,
Int64Ty
,
"cmp_lo"
)
;
Value
*
CmpHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
CmpVal
,
64
)
,
Int64Ty
,
"cmp_hi"
)
;
Value
*
NewLo
=
Builder
.
CreateTrunc
(
NewVal
,
Int64Ty
,
"new_lo"
)
;
Value
*
NewHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
NewVal
,
64
)
,
Int64Ty
,
"new_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
emitLeadingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
IntCmpXchg
,
{
Addr
,
CmpLo
,
CmpHi
,
NewLo
,
NewHi
}
)
;
emitTrailingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> static enum flt_eval_method ix86_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; case EXCESS_PRECISION_TYPE_STANDARD : case EXCESS_PRECISION_TYPE_IMPLICIT : if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! TARGET_SSE_MATH ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD in float.h . When using only the FPU , assume that the fpcw is set to extended precision ; when using only SSE , rounding is correct ; when using both SSE and the FPU , the rounding precision is indeterminate , since either may be chosen apparently at random .


<s> int first_fp_reg_to_save ( void ) { int first_reg ; for ( first_reg = 14 + 32 ; first_reg <= 63 ; first_reg ++ ) if ( regs_ever_live [ first_reg ] ) break ; return first_reg ; } </s>


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
X86
::
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
LivePhysRegs
LiveRegs
(
getRegisterInfo
(
)
)
;
LiveRegs
.
addLiveOuts
(
MBB
)
;
SmallVector
<
std
::
pair
<
unsigned
,
const
MachineOperand
*
>
,
8
>
Clobbers
;
LiveRegs
.
stepForward
(
*
MIB
,
Clobbers
)
;
for
(
const
auto
&
C
:
Clobbers
)
{
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
)
;
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
|
RegState
::
Define
)
;
}
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


<s> static bool pa_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == 8 ? "\t.dword\t" : "\t.word\t" , asm_out_file ) ; if ( ! TARGET_FAST_INDIRECT_CALLS ) fputs ( "P%" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . This code handles aligned SI and DI integers specially , since function references must be preceded by P % .


<s> uint64_t Mips64GOT :: emit ( MemoryRegion & pRegion ) { uint64_t * buffer = reinterpret_cast < uint64_t * > ( pRegion . begin ( ) ) ; uint64_t result = 0 ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { Mips64GOTEntry * got = & ( llvm :: cast < Mips64GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint64_t > ( got -> getValue ( ) ) ; result += got -> size ( ) ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".llong" ) return ParseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".tc" ) return ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".machine" ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> Optional < ExtAddrMode > X86InstrInfo :: getAddrModeFromMemoryOp ( const MachineInstr & MemI , const TargetRegisterInfo * TRI ) const { const MCInstrDesc & Desc = MemI . getDesc ( ) ; int MemRefBegin = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( MemRefBegin < 0 ) return None ; MemRefBegin += X86II :: getOperandBias ( Desc ) ; auto & BaseOp = MemI . getOperand ( MemRefBegin + X86 :: AddrBaseReg ) ; if ( ! BaseOp . isReg ( ) ) return None ; const MachineOperand & DispMO = MemI . getOperand ( MemRefBegin + X86 :: AddrDisp ) ; if ( ! DispMO . isImm ( ) ) return None ; ExtAddrMode AM ; AM . BaseReg = BaseOp . getReg ( ) ; AM . ScaledReg = MemI . getOperand ( MemRefBegin + X86 :: AddrIndexReg ) . getReg ( ) ; AM . Scale = MemI . getOperand ( MemRefBegin + X86 :: AddrScaleAmt ) . getImm ( ) ; AM . Displacement = DispMO . getImm ( ) ; return AM ; } </s>

Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory .


<s> static tree ix86_build_builtin_va_list ( void ) { tree ret = ix86_build_builtin_va_list_abi ( ix86_abi ) ; if ( TARGET_64BIT ) { tree t ; if ( ix86_abi == MS_ABI ) { t = ix86_build_builtin_va_list_abi ( SYSV_ABI ) ; if ( TREE_CODE ( t ) != RECORD_TYPE ) t = build_variant_type_copy ( t ) ; sysv_va_list_type_node = t ; } else { t = ret ; if ( TREE_CODE ( t ) != RECORD_TYPE ) t = build_variant_type_copy ( t ) ; sysv_va_list_type_node = t ; } if ( ix86_abi != MS_ABI ) { t = ix86_build_builtin_va_list_abi ( MS_ABI ) ; if ( TREE_CODE ( t ) != RECORD_TYPE ) t = build_variant_type_copy ( t ) ; ms_va_list_type_node = t ; } else { t = ret ; if ( TREE_CODE ( t ) != RECORD_TYPE ) t = build_variant_type_copy ( t ) ; ms_va_list_type_node = t ; } } return ret ; } </s>


<s> bool arm_pad_arg_upward ( enum machine_mode mode , tree type ) { if ( ! TARGET_AAPCS_BASED ) return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) == upward ; if ( type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P ( type ) ) return false ; return true ; } </s>

For use by FUNCTION_ARG_PADDING ( MODE , TYPE ) . Return true if an argument passed on the stack should be padded upwards , i.e . if the least-significant byte has useful data . For legacy APCS ABIs we use the default . For AAPCS based ABIs small aggregate types are placed in the lowest memory address .


<s> bool ARMTargetLowering :: shouldAlignPointerArgs ( CallInst * CI , unsigned & MinSize , unsigned & PrefAlign ) const { if ( ! isa < MemIntrinsic > ( CI ) ) return false ; MinSize = 8 ; PrefAlign = ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isMClass ( ) ? 8 : 4 ) ; return true ; } </s>

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: BLENDPDrri : case X86 :: BLENDPSrri : case X86 :: PBLENDWrri : case X86 :: VBLENDPDrri : case X86 :: VBLENDPSrri : case X86 :: VBLENDPDYrri : case X86 :: VBLENDPSYrri : case X86 :: VPBLENDDrri : case X86 :: VPBLENDDYrri : case X86 :: VPBLENDWrri : case X86 :: VPBLENDWYrri : SrcOpIdx1 = 1 ; SrcOpIdx2 = 2 ; return true ; case X86 :: VFMADDPDr231r : case X86 :: VFMADDPSr231r : case X86 :: VFMADDSDr231r : case X86 :: VFMADDSSr231r : case X86 :: VFMSUBPDr231r : case X86 :: VFMSUBPSr231r : case X86 :: VFMSUBSDr231r : case X86 :: VFMSUBSSr231r : case X86 :: VFNMADDPDr231r : case X86 :: VFNMADDPSr231r : case X86 :: VFNMADDSDr231r : case X86 :: VFNMADDSSr231r : case X86 :: VFNMSUBPDr231r : case X86 :: VFNMSUBPSr231r : case X86 :: VFNMSUBSDr231r : case X86 :: VFNMSUBSSr231r : case X86 :: VFMADDPDr231rY : case X86 :: VFMADDPSr231rY : case X86 :: VFMSUBPDr231rY : case X86 :: VFMSUBPSr231rY : case X86 :: VFNMADDPDr231rY : case X86 :: VFNMADDPSr231rY : case X86 :: VFNMSUBPDr231rY : case X86 :: VFNMSUBPSr231rY : SrcOpIdx1 = 2 ; SrcOpIdx2 = 3 ; return true ; default : return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> opt_machine_mode arm_get_mask_mode ( machine_mode mode ) { if ( TARGET_HAVE_MVE ) return arm_mode_to_pred_mode ( mode ) ; return default_get_mask_mode ( mode ) ; } </s>


<s> bool AArch64TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != 128 ) return false ; return ! isOpSuitableForLDPSTP ( SI ) ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ; } </s>

True if the stack can be realigned for the target .


<s> bool MipsTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s>
unsigned
ARMBaseInstrInfo
::
getPartialRegUpdateClearance
(
const
MachineInstr
&
MI
,
unsigned
OpNum
,
const
TargetRegisterInfo
*
TRI
)
const
{
auto
PartialUpdateClearance
=
Subtarget
.
getPartialUpdateClearance
(
)
;
if
(
!
PartialUpdateClearance
)
return
0
;
assert
(
TRI
&&
"Need TRI instance"
)
;
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OpNum
)
;
if
(
MO
.
readsReg
(
)
)
return
0
;
unsigned
Reg
=
MO
.
getReg
(
)
;
int
UseOp
=
1
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VLDRS
:
case
ARM
::
FCONSTS
:
case
ARM
::
VMOVSR
:
case
ARM
::
VMOVv8i8
:
case
ARM
::
VMOVv4i16
:
case
ARM
::
VMOVv2i32
:
case
ARM
::
VMOVv2f32
:
case
ARM
::
VMOVv1i64
:
UseOp
=
MI
.
findRegisterUseOperandIdx
(
Reg
,
false
,
TRI
)
;
break
;
case
ARM
::
VLD1LNd32
:
UseOp
=
3
;
break
;
default
:
return
0
;
}
if
(
UseOp
!=
1
&&
MI
.
getOperand
(
UseOp
)
.
readsReg
(
)
)
return
0
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
Reg
)
)
{
if
(
!
MO
.
getSubReg
(
)
||
MI
.
readsVirtualRegister
(
Reg
)
)
return
0
;
}
else
if
(
ARM
::
SPRRegClass
.
contains
(
Reg
)
)
{
unsigned
DReg
=
TRI
->
getMatchingSuperReg
(
Reg
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DReg
||
!
MI
.
definesRegister
(
DReg
,
TRI
)
)
return
0
;
}
return
PartialUpdateClearance
;
}
</s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> StackOffset SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { StackOffset Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI , FrameReg ) ; return Offset + StackOffset :: getFixed ( SystemZMC :: CallFrameSize ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static void sh_symbian_mark_dllexport ( tree decl ) { const char * oldname ; char * newname ; rtx rtlname ; tree idp ; rtlname = XEXP ( DECL_RTL ( decl ) , 0 ) ; if ( GET_CODE ( rtlname ) == MEM ) rtlname = XEXP ( rtlname , 0 ) ; gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , 0 ) ; if ( sh_symbian_dllimport_name_p ( oldname ) ) { oldname += strlen ( DLL_IMPORT_PREFIX ) ; DECL_NON_ADDR_CONST_P ( decl ) = 0 ; } else if ( sh_symbian_dllexport_name_p ( oldname ) ) return ; newname = alloca ( strlen ( DLL_EXPORT_PREFIX ) + strlen ( oldname ) + 1 ) ; sprintf ( newname , "%s%s" , DLL_EXPORT_PREFIX , oldname ) ; idp = get_identifier ( newname ) ; XEXP ( DECL_RTL ( decl ) , 0 ) = gen_rtx_SYMBOL_REF ( Pmode , IDENTIFIER_POINTER ( idp ) ) ; } </s>

Mark a DECL as being dllexport 'd . Note that we override the previous setting ( e.g . : dllimport ) .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void release_scratch_register_on_entry ( struct scratch_reg * sr ) { if ( sr -> saved ) { struct machine_function * m = cfun -> machine ; rtx x , insn = emit_insn ( gen_pop ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( UNITS_PER_WORD ) ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; } } </s>

Release a scratch register obtained from the preceding function . If RELEASE_VIA_POP is true , we just pop the register off the stack to release it . This is what non-Linux systems use with -fstack-check . Otherwise we use OFFSET to locate the saved register and the allocated stack space becomes part of the local frame and is deallocated by the epilogue .


<s> static const char * mips16_call_stub_mode_suffix ( machine_mode mode ) { if ( mode == SFmode ) return "sf" ; else if ( mode == DFmode ) return "df" ; else if ( mode == SCmode ) return "sc" ; else if ( mode == DCmode ) return "dc" ; else if ( mode == V2SFmode ) { gcc_assert ( TARGET_PAIRED_SINGLE_FLOAT ) ; return "df" ; } else gcc_unreachable ( ) ; } </s>

Return the two-character string that identifies floating-point return mode MODE in the name of a MIPS16 function stub .


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( OptLevel != CodeGenOpt :: None && Subtarget . isCortexA9 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool insn_uses_reg_mem ( unsigned int regno , rtx insn ) { df_ref use ; FOR_EACH_INSN_USE ( use , insn ) if ( DF_REF_REG_MEM_P ( use ) && regno == DF_REF_REGNO ( use ) ) return true ; return false ; } </s>

Function checks if instruction INSN uses register number REGNO as a part of address expression .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
>
I
=
df_ext_begin
(
Entry
,
Processed
)
,
E
=
df_ext_end
(
Entry
,
Processed
)
;
I
!=
E
;
++
I
)
Changed
|=
processBasicBlock
(
MF
,
*
*
I
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> const char * i386_pe_strip_name_encoding_full ( const char * str ) { const char * p ; const char * name = default_strip_name_encoding ( str ) ; if ( * name == '@' ) name ++ ; p = strchr ( name , '@' ) ; if ( p ) return ggc_alloc_string ( name , p - name ) ; return name ; } </s>

Also strip the fastcall prefix and stdcall suffix .


<s> static tree rs6000_init_stack_protect_guard ( void ) { if ( rs6000_stack_protector_guard == SSP_GLOBAL ) return default_stack_protect_guard ( ) ; return NULL_TREE ; } </s>

Only create the global variable for the stack protect guard if we are using the global flavor of that guard .


"DLX DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'f' : case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
static
unsigned
getOpcode_EXTEND
(
unsigned
Opcode
)
{
switch
(
Opcode
)
{
case
ISD
::
ANY_EXTEND
:
case
ISD
::
ANY_EXTEND_VECTOR_INREG
:
return
ISD
::
ANY_EXTEND
;
case
ISD
::
ZERO_EXTEND
:
case
ISD
::
ZERO_EXTEND_VECTOR_INREG
:
return
ISD
::
ZERO_EXTEND
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
SIGN_EXTEND_VECTOR_INREG
:
return
ISD
::
SIGN_EXTEND
;
}
llvm_unreachable
(
"Unknown opcode"
)
;
}
</s>

Convert * _EXTEND_VECTOR_INREG to * _EXTEND opcode .


<s> static bool expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt ) { machine_mode v2mode ; rtx x ; v2mode = GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) ; x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return expand_vselect ( target , x , perm , nelt ) ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s> static unsigned int ix86_select_alt_pic_regnum ( void ) { if ( current_function_is_leaf && ! current_function_profile ) { int i ; for ( i = 2 ; i >= 0 ; -- i ) if ( ! regs_ever_live [ i ] ) return i ; } return INVALID_REGNUM ; } </s>

Return > = 0 if there is an unused call-clobbered register available for the entire function .


"passing %qT to argument %d of %qE, which"

" expects a vector of 32-bit or 64-bit elements"

Like infer_vector_type , but also require the element size to be 32 or 64 bits .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned RA = ABI . GetReturnAddress ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . GetBasePtr ( ) ; if ( hasFP ( MF ) ) { setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( MF ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( MF ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( STI . isCheri ( ) ) { if ( STI . isABI_CheriPureCap ( ) ) { if ( isInt < 10 > ( MaxSPOffset ) ) return ; } else if ( isInt < 15 > ( MaxSPOffset ) ) return ; } else if ( isIntN ( STI . hasMSA ( ) ? 10 : 16 , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 ) { if ( Subtarget -> hasInt256 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasFp256 ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool isLegalMaskedScatter ( Type * Ty , Align Alignment ) { return isLegalMaskedGather ( Ty , Alignment ) ; } </s>

Return true if the target supports masked scatter .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , unsigned CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerFormalArguments_SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
void
PPCDispatchGroupSBHazardRecognizer
::
RecedeCycle
(
)
{
llvm_unreachable
(
"Bottom-up scheduling not supported"
)
;
}
</s>

RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .

PowerPC
PPC
"Bottom-up scheduling not supported"


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { emitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; auto Stubs = MMIMacho . getAuthGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( "__DATA" , "__auth_ptr" , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; emitAlignment ( Align ( 8 ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> const uint16_t * Cpu0RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


"static const void *__offload_target_data[] = {\n"

"  &__offload_image_intelmic_start, &__offload_image_intelmic_end\n"

"void GOMP_offload_register (void *, int, void *);\n"

"void GOMP_offload_unregister (void *, int, void *);\n\n"

"  GOMP_offload_register (&__OFFLOAD_TABLE__, %d, __offload_target_data);\n"

"  GOMP_offload_unregister (&__OFFLOAD_TABLE__, %d, __offload_target_data);\n"

Generates object file with the host side descriptor .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = X86FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const X86InstrInfo * TII = TM -> getInstrInfo ( ) ; unsigned PC ; if ( TM -> getSubtarget < X86Subtarget > ( ) . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( & X86 :: GR32RegClass ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: MOVPC32r ) , PC ) . addImm ( 0 ) ; if ( TM -> getSubtarget < X86Subtarget > ( ) . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: ADD32ri ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , X86II :: MO_GOT_ABSOLUTE_ADDRESS ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void vax_file_start ( void ) { default_file_start ( ) ; if ( write_symbols == DBX_DEBUG ) fprintf ( asm_out_file , "___vax_%c_doubles:\n" , ASM_DOUBLE_CHAR ) ; } </s>

When debugging with stabs , we want to output an extra dummy label so that gas can distinguish between D_float and G_float prior to processing the .stabs directive identifying type double .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f128 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: f128 ; return Size >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>


"ShadowCallStack attribute not supported on Darwin."

"ShadowCallStack attribute not supported with swifttail"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> rtx function_expander :: get_reg_target ( ) { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) ) ; if ( ! possible_target || GET_MODE ( possible_target ) != target_mode ) possible_target = gen_reg_rtx ( target_mode ) ; return possible_target ; } </s>

Return a REG rtx that can be used for the result of the function , using the preferred target if suitable .


"Don't know how to handle that operation"


<s>
const
char
*
output_mov_double_arm_from_fpa
(
rtx
*
operands
)
{
int
arm_reg0
=
REGNO
(
operands
[
0
]
)
;
rtx
ops
[
2
]
;
gcc_assert
(
arm_reg0
!=
IP_REGNUM
)
;
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
arm_reg0
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
1
+
arm_reg0
)
;
output_asm_insn
(
"stf%?d\t%1, [%|sp, #-8]!"
,
operands
)
;
output_asm_insn
(
"ldm%?fd\t%|sp!, {%0, %1}"
,
ops
)
;
return
""
;
}
</s>

Output a move from an fpa register to arm registers . OPERANDS [ 0 ] is the first registers of an arm register pair . OPERANDS [ 1 ] is an fpa register .


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeCopy ( & MBB ) ; return Changed ; } </s>


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> static rtx ix86_expand_int_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { enum machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , flags , tmp ) ) ; return gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; } </s>

Generate insn patterns to do an integer compare of OPERANDS .


"Due to potential STLF stall, split instruction:\n"

Split vector load from parm_decl to elemental loads to avoid STLF stalls .


<s> int ARMBaseInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const { if ( ! DefNode -> isMachineOpcode ( ) ) return 1 ; const TargetInstrDesc & DefTID = get ( DefNode -> getMachineOpcode ( ) ) ; if ( isZeroCost ( DefTID . Opcode ) ) return 0 ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return DefTID . mayLoad ( ) ? 3 : 1 ; if ( ! UseNode -> isMachineOpcode ( ) ) { int Latency = ItinData -> getOperandCycle ( DefTID . getSchedClass ( ) , DefIdx ) ; if ( Subtarget . isCortexA9 ( ) ) return Latency <= 2 ? 1 : Latency - 1 ; else return Latency <= 3 ? 1 : Latency - 2 ; } const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > 1 && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: LDRBrs : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( 2 ) ) -> getZExtValue ( ) ; unsigned ShImm = ARM_AM :: getAM2Offset ( ShOpVal ) ; if ( ShImm == 0 || ( ShImm == 2 && ARM_AM :: getAM2ShiftOpc ( ShOpVal ) == ARM_AM :: lsl ) ) -- Latency ; break ; } case ARM :: t2LDRs : case ARM :: t2LDRBs : case ARM :: t2LDRHs : case ARM :: t2LDRSHs : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( 2 ) ) -> getZExtValue ( ) ; if ( ShAmt == 0 || ShAmt == 2 ) -- Latency ; break ; } } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> static bool loongarch_int_order_operand_ok_p ( enum rtx_code code , rtx cmp1 ) { switch ( code ) { case GT : case GTU : return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return cmp1 == const1_rtx ; case LT : case LTU : return arith_operand ( cmp1 , VOIDmode ) ; case LE : return sle_operand ( cmp1 , VOIDmode ) ; case LEU : return sleu_operand ( cmp1 , VOIDmode ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if CMP1 is a suitable second operand for integer ordering test CODE .


<s> static int ix86_simd_clone_usable ( struct cgraph_node * node ) { switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) return - 1 ; if ( ! TARGET_AVX ) return 0 ; return TARGET_AVX512F ? 3 : TARGET_AVX2 ? 2 : 1 ; case 'c' : if ( ! TARGET_AVX ) return - 1 ; return TARGET_AVX512F ? 2 : TARGET_AVX2 ? 1 : 0 ; case 'd' : if ( ! TARGET_AVX2 ) return - 1 ; return TARGET_AVX512F ? 1 : 0 ; case 'e' : if ( ! TARGET_AVX512F ) return - 1 ; return 0 ; default : gcc_unreachable ( ) ; } } </s>

If SIMD clone NODE ca n't be used in a vectorized loop in current function , return -1 , otherwise return a badness of using it ( 0 if it is most desirable from vecsize_mangle point of view , 1 slightly less desirable , etc . ) .


<s> const MipsRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> StringRef getPassName ( ) const override { return FIXUPLEA_DESC ; } </s>

getPassName - Return a nice clean name for a pass .


<s> unsigned getMaxInlineSizeThreshold ( ) const { return 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> bool mep_expand_binary_intrinsic ( int ATTRIBUTE_UNUSED immediate , int ATTRIBUTE_UNUSED immediate3 , int ATTRIBUTE_UNUSED reg , int ATTRIBUTE_UNUSED reg3 , rtx * operands ATTRIBUTE_UNUSED ) { return false ; } </s>

Likewise , but apply a binary operation to OPERANDS [ 1 ] and OPERANDS [ 2 ] . OPERANDS [ 1 ] is a register_operand , OPERANDS [ 2 ] can be a general_operand . IMMEDIATE and IMMEDIATE3 are intrinsics that take an immediate third operand . REG and REG3 take register operands only .


"Return from a call instruction in the loop."

NULL if INSN insn is valid within a low-overhead loop . Otherwise return why doloop can not be applied .


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
addPass
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
getARMSubtarget
(
)
.
hasNEON
(
)
)
addPass
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
addPass
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
addPass
(
&
IfConverterID
)
;
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
addPass
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM::DPRRegClass
ARM
ARM
ARM


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
val
=
;
char
buf
[
128
]
;
FILE
*
f
=
;
bool
arch
;
const
struct
vendor_cpu
*
cpu_table
=
;
if
(
argc
<
1
)
goto
not_found
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"cpu"
)
!=
0
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
goto
not_found
;
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
not_found
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
{
if
(
strncmp
(
buf
,
"CPU implementer"
,
sizeof
(
"CPU implementer"
)
1
)
==
0
)
{
int
i
;
for
(
i
=
0
;
vendors
[
i
]
.
vendor_no
!=
;
i
++
)
if
(
strstr
(
buf
,
vendors
[
i
]
.
vendor_no
)
!=
)
{
cpu_table
=
vendors
[
i
]
.
vendor_parts
;
break
;
}
}
if
(
strncmp
(
buf
,
"CPU part"
,
sizeof
(
"CPU part"
)
1
)
==
0
)
{
int
i
;
if
(
cpu_table
==
)
goto
not_found
;
for
(
i
=
0
;
cpu_table
[
i
]
.
part_no
!=
;
i
++
)
if
(
strstr
(
buf
,
cpu_table
[
i
]
.
part_no
)
!=
)
{
val
=
arch
cpu_table
[
i
]
.
arch_name
:
cpu_table
[
i
]
.
cpu_name
;
break
;
}
break
;
}
}
fclose
(
f
)
;
if
(
val
==
)
goto
not_found
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
val
,
)
;
not_found
:
{
unsigned
int
i
;
unsigned
int
opt
;
const
char
*
search
[
]
=
{
,
"arch"
}
;
if
(
f
)
fclose
(
f
)
;
search
[
0
]
=
argv
[
0
]
;
for
(
opt
=
0
;
opt
<
ARRAY_SIZE
(
search
)
;
opt
++
)
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
configure_default_options
)
;
i
++
)
if
(
strcmp
(
configure_default_options
[
i
]
.
name
,
search
[
opt
]
)
==
0
)
return
concat
(
"-m"
,
search
[
opt
]
,
"="
,
configure_default_options
[
i
]
.
value
,
)
;
return
;
}
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> virtual const MipsInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static rtx aarch64_gen_compare_reg_maybe_ze ( RTX_CODE code , rtx x , rtx y , machine_mode y_mode ) { if ( y_mode == E_QImode || y_mode == E_HImode ) { if ( CONST_INT_P ( y ) ) y = GEN_INT ( INTVAL ( y ) & GET_MODE_MASK ( y_mode ) ) ; else { rtx t , cc_reg ; machine_mode cc_mode ; t = gen_rtx_ZERO_EXTEND ( SImode , y ) ; t = gen_rtx_COMPARE ( CC_SWPmode , t , x ) ; cc_mode = CC_SWPmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , t ) ; return cc_reg ; } } return aarch64_gen_compare_reg ( code , x , y ) ; } </s>

Similarly , but maybe zero-extend Y if Y_MODE < SImode .


<s> static bool is_load_insn ( rtx insn , rtx * load_mem ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; if ( CALL_P ( insn ) ) return false ; return is_load_insn1 ( PATTERN ( insn ) , load_mem ) ; } </s>


<s> void MipsAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void aarch64_init_fcmla_laneq_builtins ( void ) { unsigned int i = 0 ; for ( i = 0 ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_lookup_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_lookup_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_std_type ( SImode , qualifier_lane_pair_index ) ; tree ftype = build_function_type_list ( argtype , argtype , argtype , quadtype , lanetype , NULL_TREE ) ; tree fndecl = add_builtin_function ( d -> name , ftype , d -> fcode , BUILT_IN_MD , NULL , NULL_TREE ) ; aarch64_builtin_decls [ d -> fcode ] = fndecl ; } } </s>

Due to the architecture not providing lane variant of the lane instructions for fcmla we ca n't use the standard simd builtin expansion code , but we still want the majority of the validation that would normally be done .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new ARMFastISel ( funcInfo , libInfo ) ; } return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> void OR1KRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


Define the ` __builtin_va_list ' type for the ABI .


<s> const TargetRegisterClass * SystemZRegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & SystemZ :: CCRRegClass ) return & SystemZ :: GR32BitRegClass ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .

SystemZ SystemZ SystemZ::CCRRegClass SystemZ::GR32BitRegClass


<s> bool nds32_use_load_post_increment ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( E_DImode ) ) ; } </s>

Function that determine whether a load postincrement is a good thing to use for a given mode .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : X86GenSubtargetInfo ( TT , CPU , FS ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128XRegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void crx_function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { int l = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; if ( ! last_parm_in_reg ) return ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || ( cum -> ints < 0 ) ) return ; if ( mode == SImode || mode == HImode || mode == QImode || mode == DImode ) { if ( l <= 1 ) cum -> ints += 1 ; else cum -> ints += l ; } else if ( mode == SFmode || mode == DFmode ) cum -> ints += l ; else if ( ( mode ) == BLKmode ) { if ( ( l = enough_regs_for_param ( cum , type , mode ) ) != 0 ) cum -> ints += l ; } } </s>

Implements the macro FUNCTION_ARG_ADVANCE defined in crx.h .


<s> static bool chkp_type_has_function_pointer ( const_tree type ) { bool res = false ; if ( POINTER_TYPE_P ( type ) && FUNC_OR_METHOD_TYPE_P ( TREE_TYPE ( type ) ) ) res = true ; else if ( RECORD_OR_UNION_TYPE_P ( type ) ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) res = res || chkp_type_has_function_pointer ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( type ) == ARRAY_TYPE ) res = chkp_type_has_function_pointer ( TREE_TYPE ( type ) ) ; return res ; } </s>

Return 1 if type TYPE is a pointer to function type or a structure having a pointer to function type as one of its fields . Otherwise return 0 .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
CSR_Darwin_AArch64_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> void AArch64CA53ErratumStub :: applyFixup ( FragmentRef & pSrcFragRef , IRBuilder & pBuilder , BranchIsland & pIsland ) { assert ( isMyDuty ( pSrcFragRef ) ) ; std :: string sym_name ( "__" ) ; sym_name . append ( name ( ) ) . append ( llvm :: utohexstr ( pIsland . numOfStubs ( ) ) ) . append ( "@" ) . append ( pIsland . name ( ) ) ; LDSymbol * stub_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( sym_name , ResolveInfo :: NoType , ResolveInfo :: Define , ResolveInfo :: Local , size ( ) , initSymValue ( ) , FragmentRef :: Create ( * this , initSymValue ( ) ) , ResolveInfo :: Default ) ; setSymInfo ( stub_sym -> resolveInfo ( ) ) ; FragmentRef * target = FragmentRef :: Create ( * pSrcFragRef . frag ( ) , pSrcFragRef . offset ( ) + getErratumInsnOffset ( ) + AArch64InsnHelpers :: InsnSize ) ; ResolveInfo * target_info = pBuilder . CreateLocalSymbol ( * target ) ; fixup_iterator it = fixup_begin ( ) ; Relocation * reloc = Relocation :: Create ( ( * it ) -> type ( ) , * ( FragmentRef :: Create ( * this , ( * it ) -> offset ( ) ) ) , ( * it ) -> addend ( ) ) ; reloc -> setSymInfo ( target_info ) ; std :: unique_ptr < unsigned [ ] > code ( new unsigned [ getErratumSequenceSize ( ) / 4 ] ) ; pSrcFragRef . memcpy ( code . get ( ) , getErratumSequenceSize ( ) , 0 ) ; reloc -> target ( ) = code [ getErratumInsnOffset ( ) / AArch64InsnHelpers :: InsnSize ] ; pIsland . addRelocation ( * reloc ) ; ++ it ; reloc = Relocation :: Create ( ( * it ) -> type ( ) , * ( FragmentRef :: Create ( * this , ( * it ) -> offset ( ) ) ) , ( * it ) -> addend ( ) ) ; reloc -> setSymInfo ( target_info ) ; reloc -> target ( ) = AArch64InsnHelpers :: buildBranchInsn ( ) ; pIsland . addRelocation ( * reloc ) ; assert ( ( ++ it ) == fixup_end ( ) ) ; } </s>


<s> static bool ix86_save_reg ( unsigned int regno , bool maybe_eh_return , bool ignore_outlined ) { if ( cfun -> machine -> no_caller_saved_registers ) { rtx reg = crtl -> return_rtx ; if ( reg ) { unsigned int i = REGNO ( reg ) ; unsigned int nregs = REG_NREGS ( reg ) ; while ( nregs -- > 0 ) if ( ( i + nregs ) == regno ) return false ; reg = crtl -> return_bnd ; if ( reg ) { i = REGNO ( reg ) ; nregs = REG_NREGS ( reg ) ; while ( nregs -- > 0 ) if ( ( i + nregs ) == regno ) return false ; } } return ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = 0 ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( ignore_outlined && cfun -> machine -> call_ms2sysv ) { unsigned count = cfun -> machine -> call_ms2sysv_extra_regs + xlogue_layout :: MIN_REGS ; if ( xlogue_layout :: is_stub_managed_reg ( regno , count ) ) return false ; } if ( crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) && ! cfun -> machine -> no_drap_save_restore ) return true ; return ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 FP_REG_KILL inserter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void setFrameAdjustment ( MachineInstr & I , int64_t V ) const { assert ( isFrameInstr ( I ) ) ; if ( isFrameSetup ( I ) ) I . getOperand ( 2 ) . setImm ( V ) ; else I . getOperand ( 1 ) . setImm ( V ) ; } </s>

Sets the stack pointer adjustment made inside the frame made up by this instruction .


<s>
const
char
*
output_ubranch
(
rtx
dest
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
bool
v9_form
=
false
;
int
delta
;
char
*
p
;
delta
=
5000000
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
TARGET_V9
&&
delta
>=
260000
&&
delta
<
260000
)
v9_form
=
true
;
if
(
TARGET_CBCOND
)
{
bool
emit_nop
=
emit_cbcond_nop
(
insn
)
;
bool
far
=
false
;
const
char
*
rval
;
if
(
delta
<
500
||
delta
>
500
)
far
=
true
;
if
(
far
)
{
if
(
v9_form
)
rval
=
"ba,a,pt\t%%xcc, %l0"
;
else
rval
=
"b,a\t%l0"
;
}
else
{
if
(
emit_nop
)
rval
=
"cwbe\t%%g0, %%g0, %l0\n\tnop"
;
else
rval
=
"cwbe\t%%g0, %%g0, %l0"
;
}
return
rval
;
}
if
(
v9_form
)
strcpy
(
string
,
"ba%*,pt\t%%xcc, "
)
;
else
strcpy
(
string
,
"b%*\t"
)
;
p
=
strchr
(
string
,
'\0'
)
;
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
;
*
p
++
=
'%'
;
*
p
++
=
'('
;
*
p
=
'\0'
;
return
string
;
}
</s>

Output an unconditional branch to LABEL . INSN is the instruction .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MipsABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL ; unsigned ADDu = ABI . GetPtrAdduOp ( ) ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> static bool fits_dispatch_window ( rtx_insn * insn ) { dispatch_windows * window_list = dispatch_window_list ; dispatch_windows * window_list_next = dispatch_window_list -> next ; unsigned int num_restrict ; enum dispatch_group group = get_insn_group ( insn ) ; enum insn_path path = get_insn_path ( insn ) ; int sum ; if ( group == disp_jcc || group == disp_cmp ) return false ; if ( group == disp_no_group || group == disp_branch ) return true ; if ( window_list_next ) window_list = window_list_next ; if ( window_list -> window_num == 1 ) { sum = window_list -> prev -> window_size + window_list -> window_size ; if ( sum == 32 || ( min_insn_size ( insn ) + sum ) >= 48 ) return true ; } num_restrict = count_num_restricted ( insn , window_list ) ; if ( num_restrict > num_allowable_groups [ group ] ) return false ; if ( window_list -> window_num == 0 ) { if ( path == path_double && ( window_list -> num_uops + 2 ) > MAX_INSN ) return false ; else if ( path != path_single ) return false ; } return true ; } </s>

This function returns true if insn satisfies dispatch rules on the last window scheduled .


<s> static void or1k_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int nreg = CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= 2 ) ; if ( named ) * cum += nreg ; } </s>

Worker for TARGET_FUNCTION_ARG_ADVANCE . Update the cumulative args descriptor CUM_V to advance past the next function argument . Note , this is not called for arguments passed on the stack .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
)
return
CSR_AArch64_AAPCS_X18_SaveList
;
if
(
hasSVEArgsOrReturn
(
MF
)
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> bool mask_low_and_shift_p ( machine_mode mode , rtx mask , rtx shift , int maxlen ) { return IN_RANGE ( mask_low_and_shift_len ( mode , mask , shift ) , 1 , maxlen ) ; } </s>

Check if MASK and SHIFT are valid in mask-low-and-shift-left operation if MAXLEN is the maxium length of consecutive bits that can make up MASK . MODE is the mode of the operation . See mask_low_and_shift_len for the actual definition .


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; aarch64_emit_load_exclusive ( mode , rval , mem , operands [ 5 ] ) ; cond = aarch64_gen_compare_reg ( NE , rval , oldval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; aarch64_emit_store_exclusive ( mode , scratch , mem , newval , operands [ 5 ] ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; } emit_label ( label2 ) ; } </s>


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void loongarch_split_move ( rtx dest , rtx src , rtx insn_ ) { rtx low_dest ; gcc_checking_assert ( loongarch_split_move_p ( dest , src ) ) ; if ( FP_REG_RTX_P ( dest ) || FP_REG_RTX_P ( src ) ) { if ( ! TARGET_64BIT && GET_MODE ( dest ) == DImode ) emit_insn ( gen_move_doubleword_fprdi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == DFmode ) emit_insn ( gen_move_doubleword_fprdf ( dest , src ) ) ; else if ( TARGET_64BIT && GET_MODE ( dest ) == TFmode ) emit_insn ( gen_move_doubleword_fprtf ( dest , src ) ) ; else gcc_unreachable ( ) ; } else { low_dest = loongarch_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { loongarch_emit_move ( loongarch_subword ( dest , true ) , loongarch_subword ( src , true ) ) ; loongarch_emit_move ( low_dest , loongarch_subword ( src , false ) ) ; } else { loongarch_emit_move ( low_dest , loongarch_subword ( src , false ) ) ; loongarch_emit_move ( loongarch_subword ( dest , true ) , loongarch_subword ( src , true ) ) ; } } rtx_insn * insn = ( rtx_insn * ) insn_ ; struct loongarch_address_info addr = { } ; if ( insn ) { rtx_insn * next = next_nonnote_nondebug_insn_bb ( insn ) ; if ( next ) { rtx set = single_set ( next ) ; if ( set && SET_SRC ( set ) == dest ) { if ( MEM_P ( src ) ) { rtx tmp = XEXP ( src , 0 ) ; loongarch_classify_address ( & addr , tmp , GET_MODE ( tmp ) , true ) ; if ( addr . reg && ! reg_overlap_mentioned_p ( dest , addr . reg ) ) validate_change ( next , & SET_SRC ( set ) , src , false ) ; } else validate_change ( next , & SET_SRC ( set ) , src , false ) ; } } } } </s>

Split a move from SRC to DEST , given that loongarch_split_move_p holds . SPLIT_TYPE describes the split condition .


<s> void X86FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: STACKALLOC_W_PROBING ) ) . addImm ( 0 ) ; } else { emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog ) ; } } </s>


<s> void UnwindOpcodeAssembler :: EmitSPOffset ( int64_t Offset ) { if ( Offset > 0x200 ) { uint8_t Buff [ 16 ] ; Buff [ 0 ] = ARM :: EHABI :: UNWIND_OPCODE_INC_VSP_ULEB128 ; size_t ULEBSize = encodeULEB128 ( ( Offset - 0x204 ) >> 2 , Buff + 1 ) ; emitBytes ( Buff , ULEBSize + 1 ) ; } else if ( Offset > 0 ) { if ( Offset > 0x100 ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_INC_VSP | 0x3fu ) ; Offset -= 0x100 ; } EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_INC_VSP | static_cast < uint8_t > ( ( Offset - 4 ) >> 2 ) ) ; } else if ( Offset < 0 ) { while ( Offset < - 0x100 ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_DEC_VSP | 0x3fu ) ; Offset += 0x100 ; } EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_DEC_VSP | static_cast < uint8_t > ( ( ( - Offset ) - 4 ) >> 2 ) ) ; } } </s>

Emit unwind opcodes to add $ sp with an offset .


<s> rtx ix86_find_base_term ( rtx x ) { rtx term ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , 0 ) ; if ( GET_CODE ( term ) == PLUS && ( CONST_INT_P ( XEXP ( term , 1 ) ) || GET_CODE ( XEXP ( term , 1 ) ) == CONST_DOUBLE ) ) term = XEXP ( term , 0 ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , 1 ) != UNSPEC_GOTPCREL && XINT ( term , 1 ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , 0 , 0 ) ; } return ix86_delegitimize_address ( x ) ; } </s>

If X is a machine specific address ( i.e . a symbol or label being referenced as a displacement from the GOT implemented using an UNSPEC ) , then return the base term . Otherwise return X .