<s>
void
ARM64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
,
Mnemonic
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
ARM64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
ARM64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
printVectorList
(
MI
,
0
,
O
,
""
)
;
if
(
LdStDesc
->
LaneOperand
!=
0
)
O
<<
'['
<<
MI
->
getOperand
(
LdStDesc
->
LaneOperand
)
.
getImm
(
)
<<
']'
;
unsigned
AddrOpNum
=
LdStDesc
->
LaneOperand
+
1
;
unsigned
AddrReg
=
MI
->
getOperand
(
AddrOpNum
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
AddrOpNum
+
1
)
.
getReg
(
)
;
if
(
Reg
!=
ARM64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
ARM64InstPrinter
::
printInst
(
MI
,
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const MipsSubtarget & ST = MF . getTarget ( ) . getSubtarget < MipsSubtarget > ( ) ; if ( FixGlobalBaseReg ) return GlobalBaseReg = ST . isABI_N64 ( ) ? Mips :: GP_64 : Mips :: GP ; const TargetRegisterClass * RC ; RC = ST . isABI_N64 ( ) ? Mips :: CPU64RegsRegisterClass : Mips :: CPURegsRegisterClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips Mips Mips Mips Mips::GP_64 Mips::GP Mips::CPU64RegsRegisterClass Mips::CPURegsRegisterClass


"No DAG nodes should be reachable from ExitSU"

Apply the profile inference algorithm for a given function .


<s> tree function_resolver :: resolve ( ) { return shape -> resolve ( * this ) ; } </s>

If the call is erroneous , report an appropriate error and return error_mark_node . Otherwise , if the function is overloaded , return the decl of the non-overloaded function . Return NULL_TREE otherwise , indicating that the call should be processed in the normal way .


<s> bool SparcRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( getFrameLowering ( MF ) -> hasReservedCallFrame ( MF ) ) return true ; return false ; } </s>

True if the stack can be realigned for the target .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
if
(
requestsDoubleOperand
(
Name
)
)
{
setFpFormat
(
FP_FORMAT_D
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
}
else
{
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
EatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
MipsOperand::CreateToken
0
MipsOperand::CreateToken
1
MipsOperand::CreateToken
"c."
MipsOperand::CreateToken
"."
1
"Invalid conditional code"
MipsOperand::CreateImm
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> bool X86TTIImpl :: isLegalNTLoad ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( Alignment >= DataSize && ( DataSize == 16 || DataSize == 32 ) ) return DataSize == 16 ? ST -> hasSSE1 ( ) : ST -> hasAVX2 ( ) ; return false ; } </s>

Return true if the target supports nontemporal load .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> bool Thumb2ITBlock :: runOnMachineFunction ( MachineFunction & Fn ) { const ARMSubtarget & STI = Fn . getSubtarget < ARMSubtarget > ( ) ; if ( ! STI . isThumb2 ( ) ) return false ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= InsertITInstructions ( MBB ) ; if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> int SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI -> isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } else { FrameReg = SP :: O6 ; return FrameOffset + MF . getFrameInfo ( ) -> getStackSize ( ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


<s> virtual const MipsInstrInfo * getInstrInfo ( ) const { return InstrInfo ; } </s>


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; const TargetRegisterClass * RC = X86 :: VR256RegisterClass ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( MRI . isPhysRegUsed ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , 0 ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , 0 ) ; while ( 1 ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange ; } </s>


<s> bool TOYInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
.
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
IsSlowLEA
||
IsSlow3OpsLEA
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TSM
.
init
(
&
Func
.
getSubtarget
(
)
)
;
TII
=
ST
.
getInstrInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
,
IsSlowLEA
,
IsSlow3OpsLEA
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits ; unsigned bitsize ; unsigned mask ; HOST_WIDE_INT val ; HOST_WIDE_INT splat_val ; HOST_WIDE_INT msb_val ; if ( mode == V2DImode || mode == V2DFmode || mode == V1TImode ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; bitsize = GET_MODE_BITSIZE ( inner ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; splat_val = val ; msb_val = val >= 0 ? 0 : - 1 ; for ( i = 2 ; i <= copies ; i *= 2 ) { HOST_WIDE_INT small_val ; bitsize /= 2 ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( HOST_WIDE_INT ) ( ( unsigned HOST_WIDE_INT ) small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= 0 || ( step == 1 && copies == 1 ) ) ) ; else if ( EASY_VECTOR_MSB ( splat_val , inner ) ) ; else return false ; for ( i = 1 ; i < nunits ; ++ i ) { HOST_WIDE_INT desired_val ; unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i ; if ( ( i & ( step - 1 ) ) == 0 ) desired_val = val ; else desired_val = msb_val ; if ( desired_val != const_vector_elt_as_int ( op , elt ) ) return false ; } return true ; } </s>

Return true if OP can be synthesized with a particular vspltisb , vspltish or vspltisw instruction . OP is a CONST_VECTOR . Which instruction is used depends on STEP and COPIES , one of which will be 1 . If COPIES > 1 , all items are set to the same value and contain COPIES replicas of the vsplt 's operand ; if STEP > 1 , one in STEP elements is set to the vsplt 's operand and the others are set to the value of the operand 's msb .


<s> static bool aarch64_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( CONST_INT_P ( x ) || ( CONST_DOUBLE_P ( x ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) return true ; if ( ! GET_MODE_SIZE ( mode ) . is_constant ( ) ) return aarch64_simd_valid_immediate ( x , NULL ) ; if ( GET_CODE ( x ) == CONST_VECTOR ) return ! targetm . cannot_force_const_mem ( mode , x ) ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags == ( VEC_ADVSIMD | VEC_STRUCT ) ) return false ; if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; poly_int64 offset ; if ( poly_int_rtx_p ( x , & offset ) ) return aarch64_offset_temporaries ( false , offset ) <= 1 ; x = strip_offset_and_salt ( x , & offset ) ; if ( ! offset . is_constant ( ) && aarch64_offset_temporaries ( true , offset ) > 0 ) return false ; if ( maybe_ne ( offset , 0 ) && SYMBOL_REF_P ( x ) && SYMBOL_REF_ANCHOR_P ( x ) ) return false ; if ( SYMBOL_REF_P ( x ) && ! SYMBOL_REF_TLS_MODEL ( x ) ) return true ; if ( LABEL_REF_P ( x ) ) return true ; return false ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P hook . Return true for constants that should be rematerialized rather than spilled .


<s> void Thumb2RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: t2LDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) ARMCC :: AL ) . addReg ( 0 ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s>
enum
calling_abi
ix86_function_type_abi
(
const_tree
fntype
)
{
if
(
fntype
!=
NULL_TREE
&&
TYPE_ATTRIBUTES
(
fntype
)
!=
NULL_TREE
)
{
enum
calling_abi
abi
=
ix86_abi
;
if
(
abi
==
SYSV_ABI
)
{
if
(
lookup_attribute
(
"ms_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
{
if
(
TARGET_X32
)
{
static
bool
warned
=
false
;
if
(
!
warned
)
{
error
(
"X32 does not support ms_abi attribute"
)
;
warned
=
true
;
}
}
abi
=
MS_ABI
;
}
}
else
if
(
lookup_attribute
(
"sysv_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
abi
=
SYSV_ABI
;
return
abi
;
}
return
ix86_abi
;
}
</s>

Returns value SYSV_ABI , MS_ABI dependent on fntype , specifying the call abi used .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
!
MRI
.
isReserved
(
Reg1
)
)
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
if
(
!
MRI
.
isReserved
(
Reg2
)
)
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) Known . Zero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : Known . Zero = ~ 1U ; break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> size_t ARMELFAttributeData :: emit ( char * pBuf ) const { char * buffer = pBuf ; const ELFAttributeValue & attr_conformance = m_Attrs [ Tag_conformance ] ; if ( attr_conformance . shouldEmit ( ) ) { if ( ! ELFAttributeData :: WriteAttribute ( Tag_conformance , attr_conformance , buffer ) ) { return 0 ; } } const ELFAttributeValue & attr_nodefaults = m_Attrs [ Tag_nodefaults ] ; if ( attr_nodefaults . shouldEmit ( ) ) { if ( ! ELFAttributeData :: WriteAttribute ( Tag_nodefaults , attr_nodefaults , buffer ) ) { return 0 ; } } for ( unsigned i = 0 ; i < Tag_nodefaults ; ++ i ) { TagType tag = static_cast < TagType > ( i ) ; const ELFAttributeValue & value = m_Attrs [ tag ] ; if ( value . shouldEmit ( ) && ! ELFAttributeData :: WriteAttribute ( tag , value , buffer ) ) { return 0 ; } } for ( unsigned i = ( Tag_nodefaults + 1 ) ; i <= Tag_Max ; ++ i ) { TagType tag = static_cast < TagType > ( i ) ; const ELFAttributeValue & value = m_Attrs [ tag ] ; if ( value . shouldEmit ( ) && ( i != Tag_conformance ) && ! ELFAttributeData :: WriteAttribute ( tag , value , buffer ) ) { return 0 ; } } for ( UnknownAttrsMap :: const_iterator unknown_attr_it = m_UnknownAttrs . begin ( ) , unknown_attr_end = m_UnknownAttrs . end ( ) ; unknown_attr_it != unknown_attr_end ; ++ unknown_attr_it ) { TagType tag = unknown_attr_it -> first ; const ELFAttributeValue & value = unknown_attr_it -> second ; if ( value . shouldEmit ( ) && ! ELFAttributeData :: WriteAttribute ( tag , value , buffer ) ) { return 0 ; } } return ( buffer - pBuf ) ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> rtx sh_find_equiv_gbr_addr ( rtx_insn * insn , rtx mem ) { if ( ! MEM_P ( mem ) || gbr_address_mem ( mem , GET_MODE ( mem ) ) ) return NULL_RTX ; if ( side_effects_p ( XEXP ( mem , 0 ) ) ) return NULL_RTX ; if ( df == NULL ) return NULL_RTX ; base_reg_disp gbr_disp = sh_find_base_reg_disp ( insn , XEXP ( mem , 0 ) ) ; if ( gbr_disp . is_reg ( ) && REGNO ( gbr_disp . reg ( ) ) == GBR_REG ) { for ( df_ref d = DF_REG_DEF_CHAIN ( GBR_REG ) ; d != NULL ; d = DF_REF_NEXT_REG ( d ) ) { if ( CALL_P ( DF_REF_INSN ( d ) ) ) { if ( TEST_HARD_REG_BIT ( regs_invalidated_by_call , GBR_REG ) ) return NULL_RTX ; else continue ; } else return NULL_RTX ; } rtx disp = GEN_INT ( gbr_disp . disp ( ) ) ; if ( gbr_displacement ( disp , GET_MODE ( mem ) ) ) return gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , GBR_REG ) , disp ) ; } return NULL_RTX ; } </s>

Given an insn and a memory operand , try to find an equivalent GBR based memory address and return the corresponding new memory address . Return NULL_RTX if not found .


<s> StringRef getPassName ( ) const override { return TLSCLEANUP_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s>
const
char
*
output_movedouble
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
,
enum
machine_mode
mode
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
GET_CODE
(
dst
)
==
MEM
&&
GET_CODE
(
XEXP
(
dst
,
0
)
)
==
PRE_DEC
)
return
"mov.l	%T1,%0\n\tmov.l	%1,%0"
;
if
(
register_operand
(
dst
,
mode
)
&&
register_operand
(
src
,
mode
)
)
{
if
(
REGNO
(
src
)
==
MACH_REG
)
return
"sts	mach,%S0\n\tsts	macl,%R0"
;
if
(
REGNO
(
src
)
+
1
==
REGNO
(
dst
)
)
return
"mov	%T1,%T0\n\tmov	%1,%0"
;
else
return
"mov	%1,%0\n\tmov	%T1,%T0"
;
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
)
{
if
(
INTVAL
(
src
)
<
0
)
output_asm_insn
(
"mov	#-1,%S0"
,
operands
)
;
else
output_asm_insn
(
"mov	#0,%S0"
,
operands
)
;
return
"mov	%1,%R0"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
int
ptrreg
=
1
;
int
dreg
=
REGNO
(
dst
)
;
rtx
inside
=
XEXP
(
src
,
0
)
;
switch
(
GET_CODE
(
inside
)
)
{
case
REG
:
ptrreg
=
REGNO
(
inside
)
;
break
;
case
SUBREG
:
ptrreg
=
subreg_regno
(
inside
)
;
break
;
case
PLUS
:
ptrreg
=
REGNO
(
XEXP
(
inside
,
0
)
)
;
gcc_assert
(
GET_CODE
(
XEXP
(
inside
,
1
)
)
!=
REG
)
;
break
;
case
LABEL_REF
:
return
"mov.l	%1,%0\n\tmov.l	%1+4,%T0"
;
case
POST_INC
:
return
"mov.l	%1,%0\n\tmov.l	%1,%T0"
;
default
:
gcc_unreachable
(
)
;
}
if
(
dreg
==
ptrreg
)
return
"mov.l	%T1,%T0\n\tmov.l	%1,%0"
;
}
return
"mov.l	%1,%0\n\tmov.l	%T1,%T0"
;
}
</s>

Return a sequence of instructions to perform DI or DF move . Since the SH can not move a DI or DF in one instruction , we have to take care when we see overlapping source and dest registers .


<s> static bool ix86_function_value_regno_p ( const unsigned int regno ) { switch ( regno ) { case AX_REG : return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_cfun_abi ( ) != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ; case BND0_REG : case BND1_REG : return chkp_function_instrumented_p ( current_function_decl ) ; case ST0_REG : case ST1_REG : if ( TARGET_64BIT && ix86_cfun_abi ( ) == MS_ABI ) return false ; return TARGET_FLOAT_RETURNS_IN_80387 ; case XMM0_REG : case XMM1_REG : return TARGET_SSE ; case MM0_REG : if ( TARGET_MACHO || TARGET_64BIT ) return false ; return TARGET_MMX ; } return false ; } </s>

Return true if N is a possible register number of function value .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> bool ARMFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) return false ; if ( MF . getInfo < ARMFunctionInfo > ( ) -> shouldSignReturnAddress ( true ) ) return false ; return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> rtx aarch64_ptrue_all ( unsigned int elt_size ) { rtx_vector_builder builder ( VNx16BImode , elt_size , 1 ) ; builder . quick_push ( const1_rtx ) ; for ( unsigned int i = 1 ; i < elt_size ; ++ i ) builder . quick_push ( const0_rtx ) ; return builder . build ( ) ; } </s>

Return a VNx16BImode constant in which every sequence of ELT_SIZE bits has the lowest bit set and the upper bits clear . This is the VNx16BImode equivalent of a PTRUE for controlling elements of ELT_SIZE bytes . However , because the constant is VNx16BImode , all bits are significant , even the upper zeros .


<s> std :: pair < const TargetRegisterClass * , uint8_t > AArch64TargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: v4i64 : RRC = & AArch64 :: QPairRegClass ; Cost = 2 ; break ; case MVT :: v8i64 : RRC = & AArch64 :: QQuadRegClass ; Cost = 4 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> bool SystemZRegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator SaveMBBI , MachineBasicBlock :: iterator & UseMBBI , const TargetRegisterClass * RC , unsigned Reg ) const { MachineFunction & MF = * MBB . getParent ( ) ; const SystemZInstrInfo & TII = * static_cast < const SystemZInstrInfo * > ( TM . getInstrInfo ( ) ) ; const SystemZFrameLowering * TFI = static_cast < const SystemZFrameLowering * > ( TM . getFrameLowering ( ) ) ; unsigned Base = getFrameRegister ( MF ) ; uint64_t Offset = TFI -> getEmergencySpillSlotOffset ( MF ) ; DebugLoc DL ; unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( 0 ) ; BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base ) . addImm ( Offset ) . addReg ( 0 ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ 0 0


"%qE attribute only applies to variables"

Handle a `` shared '' attribute ; arguments as in struct attribute_spec.handler .


<s> static bool aarch64_evpc_rev_local ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT diff ; unsigned int i , size , unspec ; machine_mode pred_mode ; if ( d -> vec_flags == VEC_SVE_PRED || ! d -> one_vector_p || ! d -> perm [ 0 ] . is_constant ( & diff ) ) return false ; size = ( diff + 1 ) * GET_MODE_UNIT_SIZE ( d -> vmode ) ; if ( size == 8 ) { unspec = UNSPEC_REV64 ; pred_mode = VNx2BImode ; } else if ( size == 4 ) { unspec = UNSPEC_REV32 ; pred_mode = VNx4BImode ; } else if ( size == 2 ) { unspec = UNSPEC_REV16 ; pred_mode = VNx8BImode ; } else return false ; unsigned int step = diff + 1 ; for ( i = 0 ; i < step ; ++ i ) if ( ! d -> perm . series_p ( i , step , diff - i , step ) ) return false ; if ( d -> testing_p ) return true ; rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , unspec ) ; if ( d -> vec_flags == VEC_SVE_DATA ) { rtx pred = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 2 , pred , src ) , UNSPEC_MERGE_PTRUE ) ; } emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV { 64,32,16 } insns , which reverse elements within each 64-bit , 32-bit or 16-bit granule .


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN ( branch ) ) ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , 1 ) ; return INSN_ADDRESSES ( INSN_UID ( XEXP ( dest , 0 ) ) ) ; } </s>

Return the destination address of BRANCH . We need to use this instead of get_attr_length , because the cbranch_with_nops pattern conservatively sets its length to 6 , and we still prefer to use shorter sequences .


<s> void thumb2_expand_return ( bool simple_return ) { int i , num_regs ; unsigned long saved_regs_mask ; arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = 0 , num_regs = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { if ( num_regs == 1 ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; XVECEXP ( par , 0 , 1 ) = gen_rtx_SET ( reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , 0 , 1 ) ) = 1 ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( 1 << LR_REGNUM ) ; saved_regs_mask |= ( 1 << PC_REGNUM ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; } } else { emit_jump_insn ( simple_return_rtx ) ; } } </s>


<s> static void rs6000_set_sched_context ( void * _sc ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; cached_can_issue_more = sc -> cached_can_issue_more ; last_scheduled_insn = sc -> last_scheduled_insn ; load_store_pendulum = sc -> load_store_pendulum ; divide_cnt = sc -> divide_cnt ; vec_pairing = sc -> vec_pairing ; } </s>

Sets the global scheduling context to the one pointed to by _SC .


<s> bool X86TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { Type * MemType = SI -> getValueOperand ( ) -> getType ( ) ; bool NoImplicitFloatOps = SI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE1 ( ) || Subtarget . hasX87 ( ) ) ) return false ; return needsCmpXchgNb ( MemType ) ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( ExperimentalVectorWideningLegalization && VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static enum insn_code aarch64_constant_pool_reload_icode ( machine_mode mode ) { switch ( mode ) { case SFmode : return CODE_FOR_aarch64_reload_movcpsfdi ; case DFmode : return CODE_FOR_aarch64_reload_movcpdfdi ; case TFmode : return CODE_FOR_aarch64_reload_movcptfdi ; case V8QImode : return CODE_FOR_aarch64_reload_movcpv8qidi ; case V16QImode : return CODE_FOR_aarch64_reload_movcpv16qidi ; case V4HImode : return CODE_FOR_aarch64_reload_movcpv4hidi ; case V8HImode : return CODE_FOR_aarch64_reload_movcpv8hidi ; case V2SImode : return CODE_FOR_aarch64_reload_movcpv2sidi ; case V4SImode : return CODE_FOR_aarch64_reload_movcpv4sidi ; case V2DImode : return CODE_FOR_aarch64_reload_movcpv2didi ; case V2DFmode : return CODE_FOR_aarch64_reload_movcpv2dfdi ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; } </s>

Return the reload icode required for a constant pool in mode .


<s> std :: unique_ptr < CSEConfigBase > AArch64PassConfig :: getCSEConfig ( ) const { return getStandardCSEConfigForOpt ( TM -> getOptLevel ( ) ) ; } </s>

Returns the CSEConfig object to use for the current optimization level .


<s> unsigned int execute ( function * ) final override { return remove_partial_avx_dependency ( ) ; } </s>


<s> unsigned AArch64RegisterBankInfo :: copyCost ( const RegisterBank & A , const RegisterBank & B ) const { return 0 ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

PowerPC PPC PPC PPC::G8RCRegClass PPC::GPRCRegClass


<s> unsigned getFramePointerSaveOffset ( ) const { return FramePointerSaveOffset ; } </s>

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { return ( IsGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isDataRel ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) -> hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips "interrupt"


"Switch should handle all register classes"


<s>
void
MipsCallEntry
::
printCustom
(
raw_ostream
&
O
)
const
{
O
<<
"MipsCallEntry: "
;
if
(
Val
)
O
<<
Val
->
getName
(
)
;
else
O
<<
Name
;
}
</s>

Implement printing for PseudoSourceValue .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void ix86_avx256_split_vector_move_misalign ( rtx op0 , rtx op1 ) { rtx m ; rtx ( * extract ) ( rtx , rtx , rtx ) ; rtx ( * load_unaligned ) ( rtx , rtx ) ; rtx ( * store_unaligned ) ( rtx , rtx ) ; machine_mode mode ; switch ( GET_MODE ( op0 ) ) { default : gcc_unreachable ( ) ; case V32QImode : extract = gen_avx_vextractf128v32qi ; load_unaligned = gen_avx_loaddquv32qi ; store_unaligned = gen_avx_storedquv32qi ; mode = V16QImode ; break ; case V8SFmode : extract = gen_avx_vextractf128v8sf ; load_unaligned = gen_avx_loadups256 ; store_unaligned = gen_avx_storeups256 ; mode = V4SFmode ; break ; case V4DFmode : extract = gen_avx_vextractf128v4df ; load_unaligned = gen_avx_loadupd256 ; store_unaligned = gen_avx_storeupd256 ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_LOAD && optimize_insn_for_speed_p ( ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , 0 ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , 16 ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( misaligned_operand ( op1 , GET_MODE ( op1 ) ) ) emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; else emit_insn ( load_unaligned ( op0 , op1 ) ) ; } else if ( MEM_P ( op0 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_STORE && optimize_insn_for_speed_p ( ) ) { m = adjust_address ( op0 , mode , 0 ) ; emit_insn ( extract ( m , op1 , const0_rtx ) ) ; m = adjust_address ( op0 , mode , 16 ) ; emit_insn ( extract ( m , op1 , const1_rtx ) ) ; } else emit_insn ( store_unaligned ( op0 , op1 ) ) ; } else gcc_unreachable ( ) ; } </s>

Split 32-byte AVX unaligned load and store if needed .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


"LowerFormalArgments: Other types are not Implemented\n"

"Other types in stack are not supported yet!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
void
OR1KDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
SDLoc
dl
(
Node
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
SDValue
imm
=
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
OR1K
::
ADDI
;
if
(
Node
->
hasOneUse
(
)
)
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
,
imm
)
;
else
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Opc
,
dl
,
VT
,
TFI
,
imm
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s>
void
VEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
IsAliasOfSX
(
SrcReg
)
&&
IsAliasOfSX
(
DestReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
ORri
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
dbgs
(
)
<<
"Impossible reg-to-reg copy from "
<<
printReg
(
SrcReg
,
TRI
)
<<
" to "
<<
printReg
(
DestReg
,
TRI
)
<<
"\n"
;
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>

VE
VE
VE::ORri
0
"Impossible reg-to-reg copy from "
" to "
"\n"
"Impossible reg-to-reg copy"


<s> static bool nds32_reg_base_load_store_p ( rtx_insn * insn ) { rtx mem_src = NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : mem_src = SET_SRC ( PATTERN ( insn ) ) ; break ; case TYPE_STORE : mem_src = SET_DEST ( PATTERN ( insn ) ) ; break ; default : break ; } if ( mem_src != NULL_RTX ) { if ( ( GET_CODE ( mem_src ) == ZERO_EXTEND ) || ( GET_CODE ( mem_src ) == SIGN_EXTEND ) ) mem_src = XEXP ( mem_src , 0 ) ; if ( GET_CODE ( XEXP ( mem_src , 0 ) ) == REG ) return true ; } return false ; } </s>

Return true if is load/store with REG addressing mode and memory mode is SImode .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> bool SystemZTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 20 > ( AM . BaseOffs ) ) return false ; return AM . Scale == 0 || AM . Scale == 1 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; const X86RegisterInfo * X86RI = TM -> getRegisterInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; X86MachineFunctionInfo * FuncInfo = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned StackAlignment = X86RI -> getStackAlignment ( ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) if ( RI . getRegClass ( RegNum ) -> getAlignment ( ) > StackAlignment ) { FuncInfo -> setReserveFP ( true ) ; return true ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCSymbol * OR1KMCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; } </s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> void AArch64Subtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; Policy . DisableLatencyHeuristic = DisableLatencySchedHeuristic ; } </s>

Override generic scheduling policy within a region .


"internal error: builtin function %s already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ForCodeSize = MF . getFunction ( ) . optForSize ( ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> void rs6000_emit_swsqrt ( rtx dst , rtx src , bool recip ) { machine_mode mode = GET_MODE ( src ) ; rtx e = gen_reg_rtx ( mode ) ; rtx g = gen_reg_rtx ( mode ) ; rtx h = gen_reg_rtx ( mode ) ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; int i ; rtx mhalf ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; mhalf = rs6000_load_constant_and_splat ( mode , dconsthalf ) ; emit_insn ( gen_rtx_SET ( e , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , src ) , UNSPEC_RSQRT ) ) ) ; if ( ! recip ) { rtx zero = force_reg ( mode , CONST0_RTX ( mode ) ) ; if ( mode == SFmode ) { rtx target = emit_conditional_move ( e , GT , src , zero , mode , e , zero , mode , 0 ) ; if ( target != e ) emit_move_insn ( e , target ) ; } else { rtx cond = gen_rtx_GT ( VOIDmode , e , zero ) ; rs6000_emit_vector_cond_expr ( e , e , zero , cond , src , zero ) ; } } emit_insn ( gen_mul ( g , e , src ) ) ; emit_insn ( gen_mul ( h , e , mhalf ) ) ; if ( recip ) { if ( passes == 1 ) { rtx t = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t , g , h , mhalf ) ; rs6000_emit_madd ( dst , e , t , e ) ; } else { for ( i = 0 ; i < passes ; i ++ ) { rtx t1 = gen_reg_rtx ( mode ) ; rtx g1 = gen_reg_rtx ( mode ) ; rtx h1 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t1 , g , h , mhalf ) ; rs6000_emit_madd ( g1 , g , t1 , g ) ; rs6000_emit_madd ( h1 , h , t1 , h ) ; g = g1 ; h = h1 ; } emit_insn ( gen_add3_insn ( dst , h , h ) ) ; } } else { rtx t = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t , g , h , mhalf ) ; rs6000_emit_madd ( dst , g , t , g ) ; } return ; } </s>

Goldschmidt 's Algorithm for single/double-precision floating point sqrt and rsqrt . Assumes no trapping math and finite arguments .


<s> static bool aarch64_takes_arguments_in_sve_regs_p ( const_tree fntype ) { CUMULATIVE_ARGS args_so_far_v ; aarch64_init_cumulative_args ( & args_so_far_v , NULL_TREE , NULL_RTX , NULL_TREE , 0 , true ) ; cumulative_args_t args_so_far = pack_cumulative_args ( & args_so_far_v ) ; for ( tree chain = TYPE_ARG_TYPES ( fntype ) ; chain && chain != void_list_node ; chain = TREE_CHAIN ( chain ) ) { tree arg_type = TREE_VALUE ( chain ) ; if ( arg_type == error_mark_node ) return false ; function_arg_info arg ( arg_type , true ) ; apply_pass_by_reference_rules ( & args_so_far_v , arg ) ; pure_scalable_type_info pst_info ; if ( pst_info . analyze_registers ( arg . type ) ) { unsigned int end_zr = args_so_far_v . aapcs_nvrn + pst_info . num_zr ( ) ; unsigned int end_pr = args_so_far_v . aapcs_nprn + pst_info . num_pr ( ) ; gcc_assert ( end_zr <= NUM_FP_ARG_REGS && end_pr <= NUM_PR_ARG_REGS ) ; return true ; } targetm . calls . function_arg_advance ( args_so_far , arg ) ; } return false ; } </s>

Return true if a function with type FNTYPE takes arguments in SVE vector or predicate registers .


<s>
bool
SystemZAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
Operands
.
push_back
(
SystemZOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

SystemZ
SystemZ
0
SystemZ
"unexpected token in argument list"


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
ARMInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
Opcode
==
ARM
::
MOVs
)
{
const
MCOperand
&
Dst
=
MI
->
getOperand
(
0
)
;
const
MCOperand
&
MO1
=
MI
->
getOperand
(
1
)
;
const
MCOperand
&
MO2
=
MI
->
getOperand
(
2
)
;
const
MCOperand
&
MO3
=
MI
->
getOperand
(
3
)
;
O
<<
'\t'
<<
ARM_AM
::
getShiftOpcStr
(
ARM_AM
::
getSORegShOp
(
MO3
.
getImm
(
)
)
)
;
printSBitModifierOperand
(
MI
,
6
,
O
)
;
printPredicateOperand
(
MI
,
4
,
O
)
;
O
<<
'\t'
<<
getRegisterName
(
Dst
.
getReg
(
)
)
<<
", "
<<
getRegisterName
(
MO1
.
getReg
(
)
)
;
if
(
ARM_AM
::
getSORegShOp
(
MO3
.
getImm
(
)
)
==
ARM_AM
::
rrx
)
return
;
O
<<
", "
;
if
(
MO2
.
getReg
(
)
)
{
O
<<
getRegisterName
(
MO2
.
getReg
(
)
)
;
assert
(
ARM_AM
::
getSORegOffset
(
MO3
.
getImm
(
)
)
==
0
)
;
}
else
{
O
<<
"#"
<<
ARM_AM
::
getSORegOffset
(
MO3
.
getImm
(
)
)
;
}
return
;
}
if
(
(
Opcode
==
ARM
::
STMDB_UPD
||
Opcode
==
ARM
::
t2STMDB_UPD
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
ARM
::
SP
)
{
O
<<
'\t'
<<
"push"
;
printPredicateOperand
(
MI
,
2
,
O
)
;
if
(
Opcode
==
ARM
::
t2STMDB_UPD
)
O
<<
".w"
;
O
<<
'\t'
;
printRegisterList
(
MI
,
4
,
O
)
;
return
;
}
if
(
(
Opcode
==
ARM
::
LDMIA_UPD
||
Opcode
==
ARM
::
t2LDMIA_UPD
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
ARM
::
SP
)
{
O
<<
'\t'
<<
"pop"
;
printPredicateOperand
(
MI
,
2
,
O
)
;
if
(
Opcode
==
ARM
::
t2LDMIA_UPD
)
O
<<
".w"
;
O
<<
'\t'
;
printRegisterList
(
MI
,
4
,
O
)
;
return
;
}
if
(
(
Opcode
==
ARM
::
VSTMSDB_UPD
||
Opcode
==
ARM
::
VSTMDDB_UPD
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
ARM
::
SP
)
{
O
<<
'\t'
<<
"vpush"
;
printPredicateOperand
(
MI
,
2
,
O
)
;
O
<<
'\t'
;
printRegisterList
(
MI
,
4
,
O
)
;
return
;
}
if
(
(
Opcode
==
ARM
::
VLDMSIA_UPD
||
Opcode
==
ARM
::
VLDMDIA_UPD
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
ARM
::
SP
)
{
O
<<
'\t'
<<
"vpop"
;
printPredicateOperand
(
MI
,
2
,
O
)
;
O
<<
'\t'
;
printRegisterList
(
MI
,
4
,
O
)
;
return
;
}
printInstruction
(
MI
,
O
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s>
static
void
aarch64_emit_probe_stack_range
(
HOST_WIDE_INT
first
,
poly_int64
poly_size
)
{
HOST_WIDE_INT
size
;
if
(
!
poly_size
.
is_constant
(
&
size
)
)
{
sorry
(
"stack probes for SVE frames"
)
;
return
;
}
rtx
reg1
=
gen_rtx_REG
(
Pmode
,
PROBE_STACK_FIRST_REG
)
;
gcc_assert
(
(
first
%
ARITH_FACTOR
)
==
0
)
;
if
(
size
<=
PROBE_INTERVAL
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
size
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
(
first
+
base
)
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
base
size
)
)
;
}
else
if
(
size
<=
4
*
PROBE_INTERVAL
)
{
HOST_WIDE_INT
i
,
rem
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
(
first
+
PROBE_INTERVAL
)
)
)
;
emit_stack_probe
(
reg1
)
;
for
(
i
=
2
*
PROBE_INTERVAL
;
i
<
size
;
i
+=
PROBE_INTERVAL
)
{
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
reg1
,
PROBE_INTERVAL
)
)
;
emit_stack_probe
(
reg1
)
;
}
rem
=
size
(
i
PROBE_INTERVAL
)
;
if
(
rem
>
256
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
rem
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
reg1
,
base
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
base
rem
)
)
;
}
else
emit_stack_probe
(
plus_constant
(
Pmode
,
reg1
,
rem
)
)
;
}
else
{
rtx
reg2
=
gen_rtx_REG
(
Pmode
,
PROBE_STACK_SECOND_REG
)
;
HOST_WIDE_INT
rounded_size
=
size
&
PROBE_INTERVAL
;
emit_set_insn
(
reg1
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
first
)
)
;
HOST_WIDE_INT
adjustment
=
(
first
+
rounded_size
)
;
if
(
!
aarch64_uimm12_shift
(
adjustment
)
)
{
aarch64_internal_mov_immediate
(
reg2
,
GEN_INT
(
adjustment
)
,
true
,
Pmode
)
;
emit_set_insn
(
reg2
,
gen_rtx_PLUS
(
Pmode
,
stack_pointer_rtx
,
reg2
)
)
;
}
else
emit_set_insn
(
reg2
,
plus_constant
(
Pmode
,
stack_pointer_rtx
,
adjustment
)
)
;
emit_insn
(
gen_probe_stack_range
(
reg1
,
reg1
,
reg2
)
)
;
if
(
size
!=
rounded_size
)
{
HOST_WIDE_INT
rem
=
size
rounded_size
;
if
(
rem
>
256
)
{
const
HOST_WIDE_INT
base
=
ROUND_UP
(
rem
,
ARITH_FACTOR
)
;
emit_set_insn
(
reg2
,
plus_constant
(
Pmode
,
reg2
,
base
)
)
;
emit_stack_probe
(
plus_constant
(
Pmode
,
reg2
,
base
rem
)
)
;
}
else
emit_stack_probe
(
plus_constant
(
Pmode
,
reg2
,
rem
)
)
;
}
}
emit_insn
(
gen_blockage
(
)
)
;
}
</s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static rtx swap_selector_for_mode ( machine_mode mode ) { unsigned int swap2 [ 16 ] = { 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 } ; unsigned int swap4 [ 16 ] = { 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 , 11 , 10 , 9 , 8 , 15 , 14 , 13 , 12 } ; unsigned int swap8 [ 16 ] = { 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 , 9 , 8 , 11 , 10 , 13 , 12 , 15 , 14 } ; unsigned int swap16 [ 16 ] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 } ; unsigned int * swaparray , i ; rtx perm [ 16 ] ; switch ( mode ) { case E_V2DFmode : case E_V2DImode : swaparray = swap2 ; break ; case E_V4SFmode : case E_V4SImode : swaparray = swap4 ; break ; case E_V8HImode : swaparray = swap8 ; break ; case E_V16QImode : swaparray = swap16 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < 16 ; ++ i ) perm [ i ] = GEN_INT ( swaparray [ i ] ) ; return force_reg ( V16QImode , gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , perm ) ) ) ; } </s>

Return a constant vector for use as a little-endian permute control vector to reverse the order of elements of the given vector mode .


<s> bool ARMConstantPoolValue :: hasSameValue ( ARMConstantPoolValue * ACPV ) { if ( ACPV -> Kind == Kind && ACPV -> CVal == CVal && ACPV -> PCAdjust == PCAdjust && ( ACPV -> S == S || strcmp ( ACPV -> S , S ) == 0 ) && ( ACPV -> Modifier == Modifier || strcmp ( ACPV -> Modifier , Modifier ) == 0 ) ) { if ( ACPV -> LabelId == LabelId ) return true ; if ( Kind == ARMCP :: CPValue || Kind == ARMCP :: CPExtSymbol ) return true ; } return false ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .

ARM ARM ARM 0 0 ARMCP::CPValue ARMCP::CPExtSymbol


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr ) { int regno ; sr -> saved = false ; if ( TARGET_64BIT ) { regno = R11_REG ; } else { tree decl = current_function_decl , fntype = TREE_TYPE ( decl ) ; bool fastcall_p = lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool thiscall_p = lookup_attribute ( "thiscall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool static_chain_p = DECL_STATIC_CHAIN ( decl ) ; int regparm = ix86_function_regparm ( fntype , decl ) ; int drap_regno = crtl -> drap_reg ? REGNO ( crtl -> drap_reg ) : INVALID_REGNUM ; if ( ( regparm < 1 || ( fastcall_p && ! static_chain_p ) ) && drap_regno != AX_REG ) regno = AX_REG ; else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < 2 && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < 3 && ! fastcall_p && ! thiscall_p && ! static_chain_p && drap_regno != CX_REG ) regno = CX_REG ; else if ( ix86_save_reg ( BX_REG , true ) ) regno = BX_REG ; else if ( ! ( regparm == 3 && static_chain_p ) && ix86_save_reg ( SI_REG , true ) ) regno = SI_REG ; else if ( ix86_save_reg ( DI_REG , true ) ) regno = DI_REG ; else { regno = ( drap_regno == AX_REG ? DX_REG : AX_REG ) ; sr -> saved = true ; } } sr -> reg = gen_rtx_REG ( Pmode , regno ) ; if ( sr -> saved ) { rtx insn = emit_insn ( gen_push ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Return a short-lived scratch register for use on function entry . In 32-bit mode , it is valid only after the registers are saved in the prologue . This register must be released by means of release_scratch_register_on_entry once it is dead .


<s> static void mips_expand_msa_cmp ( rtx dest , enum rtx_code cond , rtx op0 , rtx op1 ) { machine_mode cmp_mode = GET_MODE ( op0 ) ; int unspec = - 1 ; bool negate = false ; switch ( cmp_mode ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : switch ( cond ) { case NE : cond = reverse_condition ( cond ) ; negate = true ; break ; case EQ : case LT : case LE : case LTU : case LEU : break ; case GE : case GT : case GEU : case GTU : std :: swap ( op0 , op1 ) ; cond = swap_condition ( cond ) ; break ; default : gcc_unreachable ( ) ; } mips_emit_binary ( cond , dest , op0 , op1 ) ; if ( negate ) emit_move_insn ( dest , gen_rtx_NOT ( GET_MODE ( dest ) , dest ) ) ; break ; case E_V4SFmode : case E_V2DFmode : switch ( cond ) { case UNORDERED : case ORDERED : case EQ : case NE : case UNEQ : case UNLE : case UNLT : break ; case LTGT : cond = NE ; break ; case UNGE : cond = UNLE ; std :: swap ( op0 , op1 ) ; break ; case UNGT : cond = UNLT ; std :: swap ( op0 , op1 ) ; break ; case LE : unspec = UNSPEC_MSA_FSLE ; break ; case LT : unspec = UNSPEC_MSA_FSLT ; break ; case GE : unspec = UNSPEC_MSA_FSLE ; std :: swap ( op0 , op1 ) ; break ; case GT : unspec = UNSPEC_MSA_FSLT ; std :: swap ( op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } if ( unspec < 0 ) mips_emit_binary ( cond , dest , op0 , op1 ) ; else { rtx x = gen_rtx_UNSPEC ( GET_MODE ( dest ) , gen_rtvec ( 2 , op0 , op1 ) , unspec ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and store the result -1 or 0 in DEST .


<s> bool X86TargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget . hasLZCNT ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; Register stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) . getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ; } </s>


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( ( Encoding & DW_EH_PE_indirect ) && ( Encoding & DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool ARMBaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) PM . add ( createARMGlobalMergePass ( getTargetLowering ( ) ) ) ; return false ; } </s>


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,15]"

"immediate operand must be in the range [0,239]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void AArch64TargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasStackProtectorIndex ( ) ) { for ( unsigned int i = 0 , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI . getStackID ( i ) == TargetStackID :: ScalableVector && MFI . getObjectSSPLayout ( i ) != MachineFrameInfo :: SSPLK_None ) { MFI . setStackID ( MFI . getStackProtectorIndex ( ) , TargetStackID :: ScalableVector ) ; MFI . setObjectAlignment ( MFI . getStackProtectorIndex ( ) , Align ( 16 ) ) ; break ; } } } MFI . computeMaxCallFrameSize ( MF ) ; TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; int ZeroOperandPosition = - 1 ; bool BranchWithZeroOperand = false ; if ( I -> isBranch ( ) && ! I -> isPseudo ( ) ) { auto TRI = I -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; ZeroOperandPosition = I -> findRegisterUseOperandIdx ( Mips :: ZERO , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - 1 ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . cloneMemRefs ( * I ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> bool SystemZInstrInfo :: isStackSlotCopy ( const MachineInstr & MI , int & DestFrameIndex , int & SrcFrameIndex ) const { const MachineFrameInfo * MFI = MI . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; if ( MI . getOpcode ( ) != SystemZ :: MVC || ! MI . getOperand ( 0 ) . isFI ( ) || MI . getOperand ( 1 ) . getImm ( ) != 0 || ! MI . getOperand ( 3 ) . isFI ( ) || MI . getOperand ( 4 ) . getImm ( ) != 0 ) return false ; int64_t Length = MI . getOperand ( 2 ) . getImm ( ) ; unsigned FI1 = MI . getOperand ( 0 ) . getIndex ( ) ; unsigned FI2 = MI . getOperand ( 3 ) . getIndex ( ) ; if ( MFI -> getObjectSize ( FI1 ) != Length || MFI -> getObjectSize ( FI2 ) != Length ) return false ; DestFrameIndex = FI1 ; SrcFrameIndex = FI2 ; return true ; } </s>

Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect .


"instruction requires a CPU feature not currently enabled"

"source and destination must be different"


<s> static bool sh_legitimate_constant_p ( machine_mode mode , rtx x ) { return ( TARGET_SHMEDIA ? ( ( mode != DFmode && GET_MODE_CLASS ( mode ) != MODE_VECTOR_FLOAT ) || x == CONST0_RTX ( mode ) || ! TARGET_SHMEDIA_FPU || TARGET_SHMEDIA64 ) : ( GET_CODE ( x ) != CONST_DOUBLE || mode == DFmode || mode == SFmode || mode == DImode || GET_MODE ( x ) == VOIDmode ) ) ; } </s>


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
const
char
*
emit_fusion_p9_store
(
rtx
mem
,
rtx
reg
,
rtx
tmp_reg
)
{
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
store_string
;
int
r
;
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_store, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
store_string
=
"stfs"
;
else
if
(
mode
==
DFmode
)
store_string
=
"stfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_VECTOR
)
{
if
(
mode
==
SFmode
)
store_string
=
"stxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
store_string
=
"stxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
E_QImode
:
store_string
=
"stb"
;
break
;
case
E_HImode
:
store_string
=
"sth"
;
break
;
case
E_SImode
:
case
E_SFmode
:
store_string
=
"stw"
;
break
;
case
E_DImode
:
case
E_DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
store_string
=
"std"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_store, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_store not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
store_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a store using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
"emit_fusion_p9_store, bad reg #1"
"stfs"
"stfd"
"stxssp"
"stxsd"
"stb"
"sth"
"stw"
"std"
"emit_fusion_p9_store, bad reg #2"
"emit_fusion_p9_store not MEM"
0
""


<s> static bool is_cmp ( rtx_insn * insn ) { enum attr_type type ; type = get_attr_type ( insn ) ; return ( type == TYPE_TEST || type == TYPE_ICMP || type == TYPE_FCMP || GET_CODE ( PATTERN ( insn ) ) == COMPARE ) ; } </s>

Return true if insn is a compare instruction .


<s> bool SHUXIPassConfig :: addInstSelector ( ) { addPass ( createSHUXIISelDag ( getSHUXITargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void thumb_expand_cpymemqi ( rtx * operands ) { rtx out = copy_to_mode_reg ( SImode , XEXP ( operands [ 0 ] , 0 ) ) ; rtx in = copy_to_mode_reg ( SImode , XEXP ( operands [ 1 ] , 0 ) ) ; HOST_WIDE_INT len = INTVAL ( operands [ 2 ] ) ; HOST_WIDE_INT offset = 0 ; while ( len >= 12 ) { emit_insn ( gen_cpymem12b ( out , in , out , in ) ) ; len -= 12 ; } if ( len >= 8 ) { emit_insn ( gen_cpymem8b ( out , in , out , in ) ) ; len -= 8 ; } if ( len >= 4 ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= 4 ; offset += 4 ; } if ( len >= 2 ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movhi ( gen_rtx_MEM ( HImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; len -= 2 ; offset += 2 ; } if ( len ) { rtx reg = gen_reg_rtx ( QImode ) ; emit_insn ( gen_movqi ( reg , gen_rtx_MEM ( QImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; } } </s>


<s> static void CreateMem ( OwningPtr < ARMOperand > & Op , unsigned BaseRegNum , bool OffsetIsReg , const MCExpr * Offset , unsigned OffsetRegNum , bool OffsetRegShifted , enum ShiftType ShiftType , const MCExpr * ShiftAmount , bool Preindexed , bool Postindexed , bool Negative , bool Writeback , SMLoc S , SMLoc E ) { Op . reset ( new ARMOperand ) ; Op -> Kind = Memory ; Op -> Mem . BaseRegNum = BaseRegNum ; Op -> Mem . OffsetIsReg = OffsetIsReg ; Op -> Mem . Offset = Offset ; Op -> Mem . OffsetRegNum = OffsetRegNum ; Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc = S ; Op -> EndLoc = E ; } </s>


<s> const MCPhysReg * SystemZXPLINK64Registers :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SystemZ_XPLINK64_SaveList ; } </s>


<s> int ix86_attr_length_address_default ( rtx insn ) { int i ; if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; return memory_address_length ( SET_SRC ( set ) ) ; } extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( GET_CODE ( recog_data . operand [ i ] ) == MEM ) { return memory_address_length ( XEXP ( recog_data . operand [ i ] , 0 ) ) ; break ; } return 0 ; } </s>

Compute default value for `` length_address '' attribute .


<s> const char * X86TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget -> hasXMMInt ( ) ) return "Y" ; if ( Subtarget -> hasXMM ( ) ) return "x" ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> bool mips_use_ins_ext_p ( rtx op , rtx size , rtx position ) { HOST_WIDE_INT len , pos ; if ( ! ISA_HAS_EXT_INS || ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; len = INTVAL ( size ) ; pos = INTVAL ( position ) ; if ( len <= 0 || len >= GET_MODE_BITSIZE ( GET_MODE ( op ) ) || pos < 0 || pos + len > GET_MODE_BITSIZE ( GET_MODE ( op ) ) ) return false ; return true ; } </s>

Return true if ( zero_extract OP SIZE POSITION ) can be used as the source of an `` ext '' instruction or the destination of an `` ins '' instruction . OP must be a register operand and the following conditions must hold : 0 < = POSITION < GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < SIZE < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < POSITION + SIZE < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) Also reject lengths equal to a word as they are better handled by the move patterns .


<s> static unsigned getHashValue ( const TOCKey & PairVal ) { return detail :: combineHashValue ( DenseMapInfo < const MCSymbol * > :: getHashValue ( PairVal . first ) , DenseMapInfo < int > :: getHashValue ( PairVal . second ) ) ; } </s>

Using name and line to get hash value . It should already be mostly unique .


<s> static unsigned int aarch64_unspec_cond_code ( rtx_code code ) { switch ( code ) { case NE : return UNSPEC_COND_NE ; case EQ : return UNSPEC_COND_EQ ; case LT : return UNSPEC_COND_LT ; case GT : return UNSPEC_COND_GT ; case LE : return UNSPEC_COND_LE ; case GE : return UNSPEC_COND_GE ; case LTU : return UNSPEC_COND_LO ; case GTU : return UNSPEC_COND_HI ; case LEU : return UNSPEC_COND_LS ; case GEU : return UNSPEC_COND_HS ; case UNORDERED : return UNSPEC_COND_UO ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_COND_ * code for comparison CODE .


<s>
unsigned
Mips16InstrInfo
::
getInlineAsmLength
(
const
char
*
Str
,
const
MCAsmInfo
&
MAI
)
const
{
bool
atInsnStart
=
true
;
unsigned
Length
=
0
;
for
(
;
*
Str
;
++
Str
)
{
if
(
*
Str
==
'\n'
||
strncmp
(
Str
,
MAI
.
getSeparatorString
(
)
,
strlen
(
MAI
.
getSeparatorString
(
)
)
)
==
0
)
atInsnStart
=
true
;
if
(
atInsnStart
&&
!
std
::
isspace
(
static_cast
<
unsigned
char
>
(
*
Str
)
)
)
{
if
(
strncmp
(
Str
,
".space"
,
6
)
==
0
)
{
char
*
EStr
;
int
Sz
;
Sz
=
strtol
(
Str
+
6
,
&
EStr
,
10
)
;
while
(
isspace
(
*
EStr
)
)
++
EStr
;
if
(
*
EStr
==
'\0'
)
{
DEBUG
(
dbgs
(
)
<<
"parsed .space "
<<
Sz
<<
'\n'
)
;
return
Sz
;
}
}
Length
+=
MAI
.
getMaxInstLength
(
)
;
atInsnStart
=
false
;
}
if
(
atInsnStart
&&
strncmp
(
Str
,
MAI
.
getCommentString
(
)
,
strlen
(
MAI
.
getCommentString
(
)
)
)
==
0
)
atInsnStart
=
false
;
}
return
Length
;
}
</s>

Measure the specified inline asm to determine an approximation of its length .


<s> void print_operand_address ( FILE * file , rtx x ) { if ( REG_P ( x ) ) fprintf ( file , "0(%s)" , reg_names [ REGNO ( x ) ] ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) { output_addr_const ( file , x ) ; if ( small_data_operand ( x , GET_MODE ( x ) ) ) fprintf ( file , "@%s(%s)" , SMALL_DATA_RELOC , reg_names [ SMALL_DATA_REG ] ) ; else gcc_assert ( ! TARGET_TOC ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REG_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == 0 ) fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC "(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { fprintf ( file , "lo16(" ) ; output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , ")(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "(%s)" , reg_names [ REGNO ( XVECEXP ( tocrel_base , 0 , 1 ) ) ] ) ; } else gcc_unreachable ( ) ; } </s>

Print the operand address represented by the rtx addr


<s> int direct_return ( void ) { return ( reload_completed && xstormy16_compute_stack_layout ( ) . frame_size == 0 && ! xstormy16_interrupt_function_p ( ) ) ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> void split_double_mode ( machine_mode mode , rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { machine_mode half_mode ; unsigned int byte ; rtx mem_op = NULL_RTX ; int mem_num = 0 ; switch ( mode ) { case E_TImode : half_mode = DImode ; break ; case E_DImode : half_mode = SImode ; break ; case E_P2HImode : half_mode = HImode ; break ; case E_P2QImode : half_mode = QImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { if ( mem_op && rtx_equal_p ( op , mem_op ) ) { lo_half [ num ] = lo_half [ mem_num ] ; hi_half [ num ] = hi_half [ mem_num ] ; } else { mem_op = op ; mem_num = num ; lo_half [ num ] = adjust_address ( op , half_mode , 0 ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; } } else { lo_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , 0 ) ; rtx tmp = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , byte ) ; hi_half [ num ] = tmp ? tmp : gen_reg_rtx ( half_mode ) ; } } } </s>

Split one or more double-mode RTL references into pairs of half-mode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of double-mode RTLs to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( arm_disable_literal_pool && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


"attribute %<target%> argument not a string"

"invalid fpu for target attribute or pragma %qs"

"auto fpu selection not currently permitted here"

"invalid architecture for target attribute or pragma %qs"

"unknown target attribute or pragma %qs"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> static rtx loongarch_got_load_tls_ld ( rtx dest , rtx sym ) { return gen_got_load_tls_ld ( Pmode , dest , sym ) ; } </s>

Load an entry from the GOT for a TLS LD access .


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { if ( GET_CODE ( XEXP ( link , 0 ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , 0 ) , 0 ) ; if ( ix86_check_avx_upper_register ( arg ) ) return AVX_U128_DIRTY ; } } return AVX_U128_CLEAN ; } subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( ix86_check_avx_upper_register ( * iter ) ) return AVX_U128_DIRTY ; return AVX_U128_ANY ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool TOYFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> virtual void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool quad_address_p ( rtx addr , machine_mode mode , bool strict ) { rtx op0 , op1 ; if ( GET_MODE_SIZE ( mode ) != 16 ) return false ; if ( legitimate_indirect_address_p ( addr , strict ) ) return true ; if ( VECTOR_MODE_P ( mode ) && ! mode_supports_vsx_dform_quad ( mode ) ) return false ; if ( GET_CODE ( addr ) != PLUS ) return false ; op0 = XEXP ( addr , 0 ) ; if ( ! REG_P ( op0 ) || ! INT_REG_OK_FOR_BASE_P ( op0 , strict ) ) return false ; op1 = XEXP ( addr , 1 ) ; if ( ! CONST_INT_P ( op1 ) ) return false ; return quad_address_offset_p ( INTVAL ( op1 ) ) ; } </s>

Return true if the ADDR is an acceptable address for a quad memory operation of mode MODE ( either LQ/STQ for general purpose registers , or LXV/STXV for vector registers under ISA 3.0 . GPR_P is true if this address is intended for LQ/STQ . If it is false , the address is intended for the ISA 3.0 LXV/STXV instruction .


<s> bool LanaiTargetObjectFile :: isGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { return ( isGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static enum flt_eval_method ix86_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; case EXCESS_PRECISION_TYPE_STANDARD : case EXCESS_PRECISION_TYPE_IMPLICIT : if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH ) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD in float.h . When using only the FPU , assume that the fpcw is set to extended precision ; when using only SSE , rounding is correct ; when using both SSE and the FPU , the rounding precision is indeterminate , since either may be chosen apparently at random .


<s> static const char * pru_asm_regname ( rtx op ) { static char canon_reg_names [ 3 ] [ LAST_GP_REGNUM ] [ 8 ] ; int speci , regi ; gcc_assert ( REG_P ( op ) ) ; if ( ! canon_reg_names [ 0 ] [ 0 ] [ 0 ] ) { for ( regi = 0 ; regi < LAST_GP_REGNUM ; regi ++ ) for ( speci = 0 ; speci < 3 ; speci ++ ) { const int sz = ( speci == 0 ) ? 1 : ( ( speci == 1 ) ? 2 : 4 ) ; if ( ( regi + sz ) > ( 32 * 4 ) ) continue ; const char * suffix = "" ; switch ( ( sz << 8 ) | ( regi % 4 ) ) { case ( 1 << 8 ) | 0 : suffix = ".b0" ; break ; case ( 1 << 8 ) | 1 : suffix = ".b1" ; break ; case ( 1 << 8 ) | 2 : suffix = ".b2" ; break ; case ( 1 << 8 ) | 3 : suffix = ".b3" ; break ; case ( 2 << 8 ) | 0 : suffix = ".w0" ; break ; case ( 2 << 8 ) | 1 : suffix = ".w1" ; break ; case ( 2 << 8 ) | 2 : suffix = ".w2" ; break ; case ( 4 << 8 ) | 0 : suffix = "" ; break ; default : continue ; } sprintf ( & canon_reg_names [ speci ] [ regi ] [ 0 ] , "r%d%s" , regi / 4 , suffix ) ; } } switch ( GET_MODE_SIZE ( GET_MODE ( op ) ) ) { case 1 : speci = 0 ; break ; case 2 : speci = 1 ; break ; case 4 : speci = 2 ; break ; case 8 : speci = 2 ; break ; default : gcc_unreachable ( ) ; } regi = REGNO ( op ) ; gcc_assert ( regi < LAST_GP_REGNUM ) ; gcc_assert ( canon_reg_names [ speci ] [ regi ] [ 0 ] ) ; return & canon_reg_names [ speci ] [ regi ] [ 0 ] ; } </s>

Translate between the MachineDescription notion of 8-bit consecutive registers , to the PRU assembler syntax of REGWORD [ .SUBREG ] .


<s> int nds32_can_use_bset_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bset ' instruction can be used with IVAL .


<s> static bool ix86_can_inline_p ( tree caller , tree callee ) { bool ret = false ; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) ret = true ; else if ( ! caller_tree ) ret = false ; else { struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; if ( ( ( caller_opts -> x_ix86_isa_flags & callee_opts -> x_ix86_isa_flags ) != callee_opts -> x_ix86_isa_flags ) || ( ( caller_opts -> x_ix86_isa_flags2 & callee_opts -> x_ix86_isa_flags2 ) != callee_opts -> x_ix86_isa_flags2 ) ) ret = false ; else if ( caller_opts -> x_target_flags != callee_opts -> x_target_flags ) ret = false ; else if ( caller_opts -> arch != callee_opts -> arch ) ret = false ; else if ( caller_opts -> tune != callee_opts -> tune ) ret = false ; else if ( caller_opts -> x_ix86_fpmath != callee_opts -> x_ix86_fpmath ) ret = false ; else if ( caller_opts -> branch_cost != callee_opts -> branch_cost ) ret = false ; else ret = true ; } return ret ; } </s>

Hook to determine if one function can safely inline another .


<s> bool AArch64TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { if ( ExtTy != ISD :: NON_EXTLOAD ) return true ; MemSDNode * Mem = dyn_cast < MemSDNode > ( Load ) ; assert ( Mem ) ; const SDValue & Base = Mem -> getBasePtr ( ) ; if ( Base . getOpcode ( ) == ISD :: ADD && Base . getOperand ( 1 ) . getOpcode ( ) == ISD :: SHL && Base . getOperand ( 1 ) . hasOneUse ( ) && Base . getOperand ( 1 ) . getOperand ( 1 ) . getOpcode ( ) == ISD :: Constant ) { uint64_t ShiftAmount = Base . getOperand ( 1 ) . getConstantOperandVal ( 1 ) ; uint64_t LoadBytes = Mem -> getMemoryVT ( ) . getSizeInBits ( ) / 8 ; if ( ShiftAmount == Log2_32 ( LoadBytes ) ) return false ; } return true ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> void Warning ( SMLoc L , const Twine & Msg ) { getParser ( ) . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s>
bool
LoongArchAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
LoongArchOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
parseOptionalToken
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
while
(
parseOptionalToken
(
AsmToken
::
Comma
)
)
if
(
parseOperand
(
Operands
,
Name
)
)
return
true
;
if
(
parseOptionalToken
(
AsmToken
::
EndOfStatement
)
)
return
false
;
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
</s>

ParseInstruction - Parse one assembly instruction .

LoongArch
LoongArch
LoongArchOperand::createToken
"unexpected token"


<s> bool gw_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_PBSAD : case TYPE_MUL : case TYPE_DALU : case TYPE_DALU64 : case TYPE_DMUL : case TYPE_DPACK : case TYPE_DINSB : case TYPE_DCMP : case TYPE_DCLIP : case TYPE_DALUROUND : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : case TYPE_DMAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_DWEXT : return wext_odd_dep_p ( consumer , def_reg ) ; case TYPE_DBPICK : return bpick_ra_rb_dep_p ( consumer , def_reg ) ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> MCSymbol * ARM64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ 0 ] ) return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> static void emit_store_conditional ( enum machine_mode mode , rtx res , rtx mem , rtx val ) { rtx ( * fn ) ( rtx , rtx , rtx ) = NULL ; if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ; if ( PPC405_ERRATUM77 ) emit_insn ( gen_memory_barrier ( ) ) ; emit_insn ( fn ( res , mem , val ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a store-conditional instruction in MODE .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16Pass ( ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloatPass ( ) ) ; if ( getMipsSubtarget ( ) . isCheri ( ) ) { addPass ( createCheriLoopPointerDecanonicalize ( ) ) ; addPass ( createAggressiveDCEPass ( ) ) ; addPass ( createCheriRangeChecker ( ) ) ; addPass ( createCheriBoundAllocasPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool aarch64_rtx_arith_op_extract_p ( rtx x , machine_mode mode ) { if ( GET_CODE ( x ) == SIGN_EXTRACT || GET_CODE ( x ) == ZERO_EXTRACT ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; rtx op2 = XEXP ( x , 2 ) ; if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( op1 ) && op2 == const0_rtx && CONST_INT_P ( XEXP ( op0 , 1 ) ) && aarch64_is_extend_from_extract ( mode , XEXP ( op0 , 1 ) , op1 ) ) { return true ; } } return false ; } </s>

Return true if X is a zero or sign extract usable in an ADD or SUB ( extended register ) instruction .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: VLDR_P0_off : case ARM :: MVE_VLDRWU32 : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d8TPseudo : case ARM :: VLD1d16TPseudo : case ARM :: VLD1d32TPseudo : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d8QPseudo : case ARM :: VLD1d16QPseudo : case ARM :: VLD1d32QPseudo : case ARM :: VLD1d64QPseudo : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int NumBytes , ARMCC :: CondCodes Pred , unsigned PredReg , bool isThumb , const TargetInstrInfo & TII , const ARMRegisterInfo & MRI , DebugLoc dl ) { if ( isThumb ) emitThumbRegPlusImmediate ( MBB , MBBI , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , dl ) ; else emitARMRegPlusImmediate ( MBB , MBBI , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII , dl ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARMCC::CondCodes ARM ARM::SP ARM::SP ARM ARM::SP ARM::SP


<s> static void arm_emit_vfp_multi_reg_pop ( int first_reg , int num_regs , rtx base_reg ) { int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; gcc_assert ( num_regs && num_regs <= 32 ) ; if ( num_regs == 2 && ! arm_arch6 ) { if ( first_reg == 15 ) first_reg -- ; num_regs ++ ; } if ( num_regs > 16 ) { arm_emit_vfp_multi_reg_pop ( first_reg , 16 , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + 16 , num_regs - 16 , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; tmp = gen_rtx_SET ( VOIDmode , base_reg , plus_constant ( Pmode , base_reg , 8 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 0 ) = tmp ; for ( j = 0 , i = first_reg ; j < num_regs ; i += 2 ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( VOIDmode , reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , 8 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + 1 ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( TARGET_VFP && REGNO ( base_reg ) == IP_REGNUM ) { RTX_FRAME_RELATED_P ( par ) = 1 ; add_reg_note ( par , REG_CFA_DEF_CFA , hard_frame_pointer_rtx ) ; } else arm_add_cfa_adjust_cfa_note ( par , 2 * UNITS_PER_WORD * num_regs , base_reg , base_reg ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi of NUM_REGS consecutive VFP regs , starting at FIRST_REG . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> static sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; if ( bitmap_bit_p ( in , LR_REGNO ) || bitmap_bit_p ( gen , LR_REGNO ) || bitmap_bit_p ( kill , LR_REGNO ) ) bitmap_set_bit ( components , 0 ) ; return components ; } </s>