<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
{
Amount
,
MVT
::
i8
}
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
{
(
int64_t
)
CalleePopAmount
,
MVT
::
i8
}
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> bool ix86_rip_relative_addr_p ( struct ix86_address * parts ) { rtx base , index , disp ; base = parts -> base ; index = parts -> index ; disp = parts -> disp ; if ( disp && ! base && ! index ) { if ( TARGET_64BIT ) { rtx symbol = disp ; if ( GET_CODE ( disp ) == CONST ) symbol = XEXP ( disp , 0 ) ; if ( GET_CODE ( symbol ) == PLUS && CONST_INT_P ( XEXP ( symbol , 1 ) ) ) symbol = XEXP ( symbol , 0 ) ; if ( GET_CODE ( symbol ) == LABEL_REF || ( GET_CODE ( symbol ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( symbol ) == 0 ) || ( GET_CODE ( symbol ) == UNSPEC && ( XINT ( symbol , 1 ) == UNSPEC_GOTPCREL || XINT ( symbol , 1 ) == UNSPEC_PCREL || XINT ( symbol , 1 ) == UNSPEC_GOTNTPOFF ) ) ) return true ; } } return false ; } </s>

Check whether x86 address PARTS is a pc-relative address .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; if ( isPPC64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , 4 ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool ix86_d_has_stdcall_convention ( unsigned int * link_system , unsigned int * link_windows ) { if ( ix86_abi == MS_ABI ) { * link_system = 1 ; * link_windows = ( ! TARGET_64BIT ) ? 1 : 0 ; } else { * link_system = 0 ; * link_windows = 0 ; } return true ; } </s>

Implement TARGET_D_HAS_STDCALL_CONVENTION for x86 targets .


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineBasicBlock :: iterator MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; unsigned Opc = HasAVX ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; } else return ; MI -> addRegisterKilled ( Reg , TRI , true ) ; } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


"switch statement of size %lu entries too large"

Expander for the ` casesi ' pattern . INDEX is the index of the switch statement . LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding to the first table entry . RANGE is the number of table entries . TABLE is an ADDR_VEC that is the jump table . DEFAULT_LABEL is the address to branch to if INDEX is outside the range LOWER_BOUND to LOWER_BOUND+RANGE-1 .


<s> bool X86InstrInfo :: getMemOperandWithOffset ( const MachineInstr & MemOp , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { const MCInstrDesc & Desc = MemOp . getDesc ( ) ; int MemRefBegin = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( MemRefBegin < 0 ) return false ; MemRefBegin += X86II :: getOperandBias ( Desc ) ; BaseOp = & MemOp . getOperand ( MemRefBegin + X86 :: AddrBaseReg ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + X86 :: AddrScaleAmt ) . getImm ( ) != 1 ) return false ; if ( MemOp . getOperand ( MemRefBegin + X86 :: AddrIndexReg ) . getReg ( ) != X86 :: NoRegister ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + X86 :: AddrDisp ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; return true ; } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


"Builtin function %s is only valid for the cell processor"

"Builtin function %s requires the -mvsx option"

"Builtin function %s requires the -mhtm option"

"Builtin function %s requires the -maltivec option"

"Builtin function %s requires the -mpaired option"

"Builtin function %s requires the -mspe option"

"Builtin function %s requires the -mhard-dfp and"

"Builtin function %s requires the -mhard-dfp option"

"Builtin function %s requires the -mpower8-vector option"

"Builtin function %s requires the -mcpu=power9 and"

"Builtin function %s requires the -mcpu=power9 option"

"Builtin function %s requires the -mhard-float and"

"Builtin function %s requires the -mhard-float option"

"Builtin function %s requires the -mfloat128 option"

"Builtin function %s is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s>
StringRef
getPassName
(
)
const
override
{
return
"PowerPC Branch Selector"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool expand_vec_perm_1 ( struct expand_vec_perm_d * d ) { unsigned i , nelt = d -> nelt ; unsigned char perm2 [ MAX_VECT_LEN ] ; if ( d -> one_operand_p ) { if ( expand_vec_perm_identity ( d ) ) return true ; if ( expand_vselect ( d -> target , d -> op0 , d -> perm , nelt ) ) return true ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt ) ) return true ; if ( ! d -> one_operand_p ) { for ( i = 0 ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e >= nelt ) e -= nelt ; else e += nelt ; perm2 [ i ] = e ; } if ( expand_vselect_vconcat ( d -> target , d -> op1 , d -> op0 , perm2 , nelt ) ) return true ; } if ( expand_vec_perm_shrp ( d ) ) return true ; return false ; } </s>

Try to instantiate D in a single instruction .


<s> bool function_checker :: require_immediate_lane_index ( unsigned int rel_argno , unsigned int group_size ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; machine_mode mode = TYPE_MODE ( type_argument_type ( m_fntype , argno ) ) ; gcc_assert ( VECTOR_MODE_P ( mode ) ) ; unsigned int nlanes = 128 / ( group_size * GET_MODE_UNIT_BITSIZE ( mode ) ) ; return require_immediate_range ( rel_argno , 0 , nlanes - 1 ) ; } </s>

Check that argument REL_ARGNO is suitable for indexing argument REL_ARGNO - 1 , in groups of GROUP_SIZE elements . REL_ARGNO counts from the end of the predication arguments .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> HOST_WIDE_INT pa_function_arg_size ( machine_mode mode , const_tree type ) { HOST_WIDE_INT size ; size = mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ; return CEIL ( size , UNITS_PER_WORD ) ; } </s>

Figure out the size in words of the function argument .


<s> static bool ix86_pass_by_reference ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) return false ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) { HOST_WIDE_INT msize = GET_MODE_SIZE ( mode ) ; if ( type ) { if ( TREE_CODE ( type ) == ARRAY_TYPE ) return true ; if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != 1 && msize != 2 && msize != 4 && msize != 8 ; } else if ( type && int_size_in_bytes ( type ) == - 1 ) return true ; } return false ; } </s>

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { EVT VT = getValueType ( DL , Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"%qs attribute only applies to functions"

"fastcall and regparm attributes are not compatible"

"%qs attribute requires an integer constant argument"

"argument to %qs attribute larger than %d"

"fastcall and cdecl attributes are not compatible"

"fastcall and stdcall attributes are not compatible"

"stdcall and cdecl attributes are not compatible"

"stdcall and fastcall attributes are not compatible"

Handle `` cdecl '' , `` stdcall '' , `` fastcall '' , `` regparm '' and `` sseregparm '' calling convention attributes ; arguments as in struct attribute_spec.handler .


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( arm_disable_literal_pool && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
PLI
:
case
PPC
::
PLI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
XXSPLTI32DX
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
case
PPC
::
XXSETACCZ
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
unsigned
Size
=
getFixupKindSize
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
if
(
(
Target
.
isAbsolute
(
)
||
IsResolved
)
&&
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
Flags
&
MCFixupKindInfo
::
FKF_IsPCRel
)
{
if
(
Size
>
0
&&
!
isIntN
(
Size
*
8
,
SignedValue
)
)
Asm
.
getContext
(
)
.
reportError
(
Fixup
.
getLoc
(
)
,
"value of "
+
Twine
(
SignedValue
)
+
" is too large for field of "
+
Twine
(
Size
)
+
(
(
Size
==
1
)
" byte."
:
" bytes."
)
)
;
}
else
{
assert
(
(
Size
==
0
||
isIntN
(
Size
*
8
+
1
,
SignedValue
)
)
&&
"Value does not fit in the Fixup field"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget -> hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; if ( VT . isSimple ( ) ) { MVT VVT = VT . getSimpleVT ( ) ; const unsigned NumElts = VVT . getVectorNumElements ( ) ; const MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget -> hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget -> hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( VVT . is256BitVector ( ) || VVT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } if ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; case 32 : return MVT :: v32i1 ; } } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void AArch64AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; if ( AArch64FI -> getLOHRelated ( ) . count ( MI ) ) { MCSymbol * LOHLabel = GetTempSymbol ( "loh" , LOHLabelCounter ++ ) ; LOHInstToLabel [ MI ] = LOHLabel ; OutStreamer . EmitLabel ( LOHLabel ) ; } switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: DBG_VALUE : { if ( isVerbose ( ) && OutStreamer . hasRawTextSupport ( ) ) { SmallString < 128 > TmpStr ; raw_svector_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; } case AArch64 :: TCRETURNri : { MCInst TmpInst ; TmpInst . setOpcode ( AArch64 :: BR ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case AArch64 :: TCRETURNdi : { MCOperand Dest ; MCInstLowering . lowerOperand ( MI -> getOperand ( 0 ) , Dest ) ; MCInst TmpInst ; TmpInst . setOpcode ( AArch64 :: B ) ; TmpInst . addOperand ( Dest ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case AArch64 :: TLSDESC_BLR : { MCOperand Callee , Sym ; MCInstLowering . lowerOperand ( MI -> getOperand ( 0 ) , Callee ) ; MCInstLowering . lowerOperand ( MI -> getOperand ( 1 ) , Sym ) ; MCInst TLSDescCall ; TLSDescCall . setOpcode ( AArch64 :: TLSDESCCALL ) ; TLSDescCall . addOperand ( Sym ) ; EmitToStreamer ( OutStreamer , TLSDescCall ) ; MCInst BLR ; BLR . setOpcode ( AArch64 :: BLR ) ; BLR . addOperand ( Callee ) ; EmitToStreamer ( OutStreamer , BLR ) ; return ; } case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( OutStreamer , SM , * MI ) ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void ix86_d_target_versions ( void ) { if ( TARGET_64BIT ) { d_add_builtin_version ( "X86_64" ) ; if ( TARGET_X32 ) d_add_builtin_version ( "D_X32" ) ; } else d_add_builtin_version ( "X86" ) ; if ( TARGET_80387 ) d_add_builtin_version ( "D_HardFloat" ) ; else d_add_builtin_version ( "D_SoftFloat" ) ; } </s>

Implement TARGET_D_CPU_VERSIONS for x86 targets .


<s> static inline int and_xor_ior_costs ( rtx x , int code ) { const int cost_scale = GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return 1 * cost_scale ; int i = INTVAL ( XEXP ( x , 1 ) ) ; if ( ( i == 0xff || i == 0xffff ) && code == AND ) return 1 * cost_scale ; if ( CONST_OK_FOR_K08 ( i ) ) return 2 * cost_scale ; if ( CONST_OK_FOR_I08 ( i ) ) return 2 * cost_scale ; return 3 * cost_scale ; } </s>

Return the cost of an AND/XOR/IOR operation .


"MMIX Internal: %s is not a shiftable int"

Print operator suitable for doing something with a shiftable wyde . The type of operator is passed as an asm output modifier .


<s> static tree ATTRIBUTE_UNUSED ix86_stack_protect_fail ( void ) { return TARGET_64BIT ? default_external_stack_protect_fail ( ) : default_hidden_stack_protect_fail ( ) ; } </s>

For 32-bit code we can save PIC register setup by using __stack_chk_fail_local hidden function instead of calling __stack_chk_fail directly . 64-bit code does n't need to setup any PIC register , so it is better to call __stack_chk_fail directly .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = getSymbol ( * Mang , GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Mang , MMI , Encoding , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> static bool pa_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) != GET_MODE_CLASS ( mode2 ) ) return false ; return true ; } </s>

Returns TRUE if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2 . If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2 , for any hard reg , then this must be FALSE for correct output . We should return FALSE for QImode and HImode because these modes are not ok in the floating-point registers . However , this prevents tieing these modes to SImode and DImode in the general registers . So , this is n't a good idea . We rely on HARD_REGNO_MODE_OK and CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used in the floating-point registers .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool ix86_expand_mask_vec_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 ) { machine_mode mask_mode = GET_MODE ( dest ) ; machine_mode cmp_mode = GET_MODE ( cmp_op0 ) ; rtx imm = GEN_INT ( ix86_cmp_code_to_pcmp_immediate ( code , cmp_mode ) ) ; int unspec_code ; rtx unspec ; switch ( code ) { case LEU : case GTU : case GEU : case LTU : unspec_code = UNSPEC_UNSIGNED_PCMP ; break ; default : unspec_code = UNSPEC_PCMP ; } unspec = gen_rtx_UNSPEC ( mask_mode , gen_rtvec ( 3 , cmp_op0 , cmp_op1 , imm ) , unspec_code ) ; emit_insn ( gen_rtx_SET ( dest , unspec ) ) ; return true ; } </s>


<s> unsigned VEInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: STrii || MI . getOpcode ( ) == VE :: STLrii || MI . getOpcode ( ) == VE :: STUrii ) { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 3 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void TOYRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; unsigned FI = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case TOY :: LDR : case TOY :: STR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) + ImmOp . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TOY :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( EVT VT ) const { if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return ARM :: QQPRRegisterClass ; else if ( VT == MVT :: v8i64 ) return ARM :: QQQQPRRegisterClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegisterClass MVT::v8i64 ARM::QQQQPRRegisterClass


<s>
StringRef
getPassName
(
)
const
override
{
return
"CHERI invalidate pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int unqualifiedInlineAsmVariant ( ) const override { return 1 ; } </s>

The default variant to use in unqualified asm instructions .


<s> static rtx fixup_modeless_constant ( rtx x , machine_mode mode ) { if ( GET_MODE ( x ) == VOIDmode ) x = convert_to_mode ( mode , x , 1 ) ; return x ; } </s>

Fixup modeless constants to fit required mode .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
2
:
1
)
;
Register
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
add
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
add
(
MI
.
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
NewMI
.
add
(
condCodeOp
(
)
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
add
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> static int ix86_set_reg_reg_cost ( machine_mode mode ) { unsigned int units = UNITS_PER_WORD ; switch ( GET_MODE_CLASS ( mode ) ) { default : break ; case MODE_CC : units = GET_MODE_SIZE ( CCmode ) ; break ; case MODE_FLOAT : if ( ( TARGET_SSE && mode == TFmode ) || ( TARGET_80387 && mode == XFmode ) || ( ( TARGET_80387 || TARGET_SSE2 ) && mode == DFmode ) || ( ( TARGET_80387 || TARGET_SSE ) && mode == SFmode ) ) units = GET_MODE_SIZE ( mode ) ; break ; case MODE_COMPLEX_FLOAT : if ( ( TARGET_SSE && mode == TCmode ) || ( TARGET_80387 && mode == XCmode ) || ( ( TARGET_80387 || TARGET_SSE2 ) && mode == DCmode ) || ( ( TARGET_80387 || TARGET_SSE ) && mode == SCmode ) ) units = GET_MODE_SIZE ( mode ) ; break ; case MODE_VECTOR_INT : case MODE_VECTOR_FLOAT : if ( ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) || ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) || ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) || ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) || ( TARGET_MMX && VALID_MMX_REG_MODE ( mode ) ) ) units = GET_MODE_SIZE ( mode ) ; } return COSTS_N_INSNS ( CEIL ( GET_MODE_SIZE ( mode ) , units ) ) ; } </s>

Return the cost of moving between two registers of mode MODE .


<s> static bool ck803_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case SET : if ( MEM_P ( XEXP ( x , 1 ) ) ) { struct csky_address op1 ; bool address_valid = decompose_csky_address ( XEXP ( XEXP ( x , 1 ) , 0 ) , & op1 ) ; if ( op1 . index ) { * total = COSTS_N_INSNS ( 3 ) ; return true ; } else if ( address_valid ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } if ( REG_P ( XEXP ( x , 0 ) ) && ( GET_CODE ( XEXP ( x , 1 ) ) == PLUS ) ) { rtx sub_exp = XEXP ( x , 1 ) ; if ( REG_P ( XEXP ( sub_exp , 0 ) ) && REG_P ( XEXP ( sub_exp , 1 ) ) ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } return false ; case MULT : if ( REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , 1 ) ) ; if ( val % 2 == 0 && val < 0xffffffff && val > 0 ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } return false ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 3 ) ; return true ; default : return false ; } } </s>


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilderBase & Builder , Type * ValueTy , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValueTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntEltTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( ValueTy ) ) ; CallInst * CI = Builder . CreateCall ( Ldxr , Addr ) ; CI -> addParamAttr ( 0 , Attribute :: get ( Builder . getContext ( ) , Attribute :: ElementType , ValueTy ) ) ; Value * Trunc = Builder . CreateTrunc ( CI , IntEltTy ) ; return Builder . CreateBitCast ( Trunc , ValueTy ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> void MipsSEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips::SP_64 Mips::SP


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! EnableRegisterScavenging ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> PPC :: AddrMode PPCTargetLowering :: SelectForceXFormMode ( SDValue N , SDValue & Disp , SDValue & Base , SelectionDAG & DAG ) const { PPC :: AddrMode Mode = PPC :: AM_XForm ; int16_t ForceXFormImm = 0 ; if ( provablyDisjointOr ( DAG , N ) && ! isIntS16Immediate ( N . getOperand ( 1 ) , ForceXFormImm ) ) { Disp = N . getOperand ( 0 ) ; Base = N . getOperand ( 1 ) ; return Mode ; } if ( N . getOpcode ( ) == ISD :: ADD && ( ! isIntS16Immediate ( N . getOperand ( 1 ) , ForceXFormImm ) || ! N . getOperand ( 1 ) . hasOneUse ( ) || ! N . getOperand ( 0 ) . hasOneUse ( ) ) ) { Disp = N . getOperand ( 0 ) ; Base = N . getOperand ( 1 ) ; return Mode ; } Disp = DAG . getRegister ( Subtarget . isPPC64 ( ) ? PPC :: ZERO8 : PPC :: ZERO , N . getValueType ( ) ) ; Base = N ; return Mode ; } </s>

SelectForceXFormMode - Given the specified address , force it to be represented as an indexed [ r+r ] operation ( an XForm instruction ) .


<s> int adjacent_mem_locations ( rtx a , rtx b ) { if ( volatile_refs_p ( a ) || volatile_refs_p ( b ) ) return 0 ; if ( ( GET_CODE ( XEXP ( a , 0 ) ) == REG || ( GET_CODE ( XEXP ( a , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( a , 0 ) , 1 ) ) == CONST_INT ) ) && ( GET_CODE ( XEXP ( b , 0 ) ) == REG || ( GET_CODE ( XEXP ( b , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( b , 0 ) , 1 ) ) == CONST_INT ) ) ) { HOST_WIDE_INT val0 = 0 , val1 = 0 ; rtx reg0 , reg1 ; int val_diff ; if ( GET_CODE ( XEXP ( a , 0 ) ) == PLUS ) { reg0 = XEXP ( XEXP ( a , 0 ) , 0 ) ; val0 = INTVAL ( XEXP ( XEXP ( a , 0 ) , 1 ) ) ; } else reg0 = XEXP ( a , 0 ) ; if ( GET_CODE ( XEXP ( b , 0 ) ) == PLUS ) { reg1 = XEXP ( XEXP ( b , 0 ) , 0 ) ; val1 = INTVAL ( XEXP ( XEXP ( b , 0 ) , 1 ) ) ; } else reg1 = XEXP ( b , 0 ) ; if ( ! const_ok_for_op ( PLUS , val0 ) || ! const_ok_for_op ( PLUS , val1 ) ) return 0 ; if ( arm_eliminable_register ( reg0 ) ) return 0 ; val_diff = val1 - val0 ; if ( arm_ld_sched ) { return ( optimize_size && ( REGNO ( reg0 ) == REGNO ( reg1 ) ) && ( val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4 ) && ( val_diff == 4 || val_diff == - 4 ) ) ; } return ( ( REGNO ( reg0 ) == REGNO ( reg1 ) ) && ( val_diff == 4 || val_diff == - 4 ) ) ; } return 0 ; } </s>

If the target storage locations of arguments MEM1 and MEM2 are adjacent , then return the argument that has the lower address . Otherwise , return NULL_RTX .


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { switch ( Inst . getOpcode ( ) ) { case Mips :: JALR_HB : case Mips :: JALRC_HB_MMR6 : case Mips :: JALRC_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: LWP_MM : case Mips :: LWP_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 2 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: BLEZC : case Mips :: BGEZC : case Mips :: BGTZC : case Mips :: BLTZC : case Mips :: BEQZC : case Mips :: BNEZC : case Mips :: BLEZC64 : case Mips :: BGEZC64 : case Mips :: BGTZC64 : case Mips :: BLTZC64 : case Mips :: BEQZC64 : case Mips :: BNEZC64 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; return Match_Success ; case Mips :: BGEC : case Mips :: BLTC : case Mips :: BGEUC : case Mips :: BLTUC : case Mips :: BEQC : case Mips :: BNEC : case Mips :: BGEC64 : case Mips :: BLTC64 : case Mips :: BGEUC64 : case Mips :: BLTUC64 : case Mips :: BEQC64 : case Mips :: BNEC64 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 1 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 1 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; default : return Match_Success ; } } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> static bool important_for_bundling_p ( rtx_insn * insn ) { return ( INSN_P ( insn ) && ia64_safe_itanium_class ( insn ) != ITANIUM_CLASS_IGNORE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) ; } </s>

True when INSN is important for bundling .


<s> rtx ix86_fixup_binary_operands ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { int matching_memory ; rtx src1 , src2 , dst ; dst = operands [ 0 ] ; src1 = operands [ 1 ] ; src2 = operands [ 2 ] ; if ( GET_RTX_CLASS ( code ) == RTX_COMM_ARITH && ( rtx_equal_p ( dst , src2 ) || immediate_operand ( src1 , mode ) ) ) { rtx temp = src1 ; src1 = src2 ; src2 = temp ; } matching_memory = 0 ; if ( GET_CODE ( dst ) == MEM ) { if ( rtx_equal_p ( dst , src1 ) ) matching_memory = 1 ; else if ( GET_RTX_CLASS ( code ) == RTX_COMM_ARITH && rtx_equal_p ( dst , src2 ) ) matching_memory = 2 ; else dst = gen_reg_rtx ( mode ) ; } if ( GET_CODE ( src1 ) == MEM && GET_CODE ( src2 ) == MEM ) { if ( matching_memory != 2 ) src2 = force_reg ( mode , src2 ) ; else src1 = force_reg ( mode , src1 ) ; } if ( ( CONSTANT_P ( src1 ) || ( ! matching_memory && GET_CODE ( src1 ) == MEM ) ) && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH ) src1 = force_reg ( mode , src1 ) ; src1 = operands [ 1 ] = src1 ; src2 = operands [ 2 ] = src2 ; return dst ; } </s>

Fix up OPERANDS to satisfy ix86_binary_operator_ok . Return the destination to use for the operation . If different from the true destination in operands [ 0 ] , a copy operation will be required .


<s> void LC3FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = LC3 :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( LC3 :: ADDrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( LC3 :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>


<s> static void aarch64_restore_callee_saves ( machine_mode mode , HOST_WIDE_INT start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { rtx base_rtx = stack_pointer_rtx ; rtx ( * gen_mem_ref ) ( machine_mode , rtx ) = ( frame_pointer_needed ? gen_frame_mem : gen_rtx_MEM ) ; unsigned regno ; unsigned regno2 ; HOST_WIDE_INT offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { rtx reg , mem ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_mem_ref ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_mem_ref ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else emit_move_insn ( reg , mem ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfi_ops ) ; } } </s>

Emit code to restore the callee registers of mode MODE from register number START up to and including LIMIT . Restore from the stack offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true . Write the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { EVT VT = Op . getValueType ( ) ; const char * RecipOp ; if ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) RecipOp = "divf" ; else if ( ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) ) RecipOp = "vec-divf" ; else return SDValue ( ) ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; return DCI . DAG . getNode ( X86ISD :: FRCP , SDLoc ( Op ) , VT , Op ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> bool X86TargetLowering :: hasAndNotCompare ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( ! Subtarget . hasBMI ( ) ) return false ; if ( VT != MVT :: i32 && VT != MVT :: i64 ) return false ; return true ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool arm_const_double_by_parts ( rtx val ) { machine_mode mode = GET_MODE ( val ) ; rtx part ; if ( optimize_size || arm_ld_sched ) return true ; if ( mode == VOIDmode ) mode = DImode ; part = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; return false ; } </s>

Return true if it is worthwhile to split a 64-bit constant into two 32-bit operations . This is the case if optimizing for size , or if we have load delay slots , or if one 32-bit part can be done with a single data operation .


<s> Value * AArch64TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getFunction ( "__security_check_cookie" ) ; return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s> static rtx sparc_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , enum machine_mode tmode , int ignore ATTRIBUTE_UNUSED ) { tree arglist ; tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; unsigned int icode = DECL_FUNCTION_CODE ( fndecl ) ; rtx pat , op [ 4 ] ; enum machine_mode mode [ 4 ] ; int arg_count = 0 ; mode [ arg_count ] = tmode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) op [ arg_count ] = gen_reg_rtx ( tmode ) ; else op [ arg_count ] = target ; for ( arglist = TREE_OPERAND ( exp , 1 ) ; arglist ; arglist = TREE_CHAIN ( arglist ) ) { tree arg = TREE_VALUE ( arglist ) ; arg_count ++ ; mode [ arg_count ] = insn_data [ icode ] . operand [ arg_count ] . mode ; op [ arg_count ] = expand_expr ( arg , NULL_RTX , VOIDmode , 0 ) ; if ( ! ( * insn_data [ icode ] . operand [ arg_count ] . predicate ) ( op [ arg_count ] , mode [ arg_count ] ) ) op [ arg_count ] = copy_to_mode_reg ( mode [ arg_count ] , op [ arg_count ] ) ; } switch ( arg_count ) { case 1 : pat = GEN_FCN ( icode ) ( op [ 0 ] , op [ 1 ] ) ; break ; case 2 : pat = GEN_FCN ( icode ) ( op [ 0 ] , op [ 1 ] , op [ 2 ] ) ; break ; case 3 : pat = GEN_FCN ( icode ) ( op [ 0 ] , op [ 1 ] , op [ 2 ] , op [ 3 ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return op [ 0 ] ; } </s>

Handle TARGET_EXPAND_BUILTIN target hook . Expand builtin functions for sparc intrinsics .


Write PATCH_AREA_SIZE NOPs into the asm outfile FILE around a function entry . If RECORD_P is true and the target supports named sections , the location of the NOPs will be recorded in a special object section called `` __patchable_function_entries '' . This routine may be called twice per function to put NOPs before and after the function entry .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case MVT :: f64 : case MVT :: v2f64 : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static rtx nds32_expand_noarg_builtin ( enum insn_code icode , rtx target ) { rtx pat ; target = nds32_legitimize_target ( icode , target ) ; pat = GEN_FCN ( icode ) ( target ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86ISelDag ( * this , OptLevel ) ) ; if ( EnableFastISel ) PM . add ( createDeadMachineInstructionElimPass ( ) ) ; PM . add ( createX87FPRegKillInserterPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool ARMTargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == ISD :: ADD || U -> getOpcode ( ) == ISD :: SUB || U -> getOpcode ( ) == ISD :: SHL || U -> getOpcode ( ) == ARMISD :: VSHL ) ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .

ARM ARM ISD::ADD ISD::SUB ISD::SHL ARMISD::VSHL


<s> bool PPCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MFI . getStackSize ( ) ) && needsFP ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static unsigned getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) { return ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / 128 ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


<s> static void seh_emit_stackalloc ( FILE * f , struct seh_frame_state * seh , HOST_WIDE_INT offset ) { gcc_assert ( offset < 0 ) ; offset = - offset ; if ( seh -> cfa_reg == stack_pointer_rtx ) seh -> cfa_offset += offset ; seh -> sp_offset += offset ; if ( offset < SEH_MAX_FRAME_SIZE ) fprintf ( f , "\t.seh_stackalloc\t" HOST_WIDE_INT_PRINT_DEC "\n" , offset ) ; } </s>

Emit an assembler directive to adjust RSP by OFFSET .


<s> bool hasRawTextSupport ( ) const override { return true ; } </s>

Return true if this asm streamer supports emitting unformatted text to the .s file with EmitRawText .


<s> Value * AArch64TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , 0x48 ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - 0x8 ) ; return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> void ix86_simd_clone_adjust ( struct cgraph_node * node ) { const char * str = NULL ; if ( ! node -> definition ) return ; gcc_assert ( node -> decl == cfun -> decl ) ; switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) str = "sse2" ; break ; case 'c' : if ( TARGET_PREFER_AVX128 ) { if ( ! TARGET_AVX ) str = "avx,prefer-vector-width=256" ; else str = "prefer-vector-width=256" ; } else if ( ! TARGET_AVX ) str = "avx" ; break ; case 'd' : if ( TARGET_PREFER_AVX128 ) { if ( ! TARGET_AVX2 ) str = "avx2,prefer-vector-width=256" ; else str = "prefer-vector-width=256" ; } else if ( ! TARGET_AVX2 ) str = "avx2" ; break ; case 'e' : if ( TARGET_PREFER_AVX256 ) { if ( ! TARGET_AVX512F ) str = "avx512f,prefer-vector-width=512" ; else str = "prefer-vector-width=512" ; } else if ( ! TARGET_AVX512F ) str = "avx512f" ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , 0 ) ; gcc_assert ( ok ) ; pop_cfun ( ) ; ix86_reset_previous_fndecl ( ) ; ix86_set_current_function ( node -> decl ) ; } </s>

Add target attribute to SIMD clone NODE if needed .


<s> void nds32_expand_prologue_v3push ( void ) { int fp_adjust ; int sp_adjust ; int fpr_space = 0 ; unsigned Rb , Re ; nds32_compute_stack_frame ( ) ; if ( cfun -> machine -> callee_saved_gpr_regs_size > 0 ) df_set_regs_ever_live ( FP_REGNUM , 1 ) ; if ( cfun -> machine -> naked_p ) return ; Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) ) { nds32_emit_stack_v3push ( Rb , Re , sp_adjust ) ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_position = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_push_fpr_callee_saved ( fpr_position ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + sp_adjust ; nds32_emit_adjust_frame ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_adjust ) ; } } else { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_stack_v3push ( Rb , Re , fpr_space ) ; nds32_emit_push_fpr_callee_saved ( 0 ) ; } else { nds32_emit_stack_v3push ( Rb , Re , 0 ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { fp_adjust = fp_adjust + fpr_space ; } nds32_emit_adjust_frame ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_adjust ) ; } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - fpr_space ; } nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - 1 * sp_adjust ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>


<s> AArch64DCFunction & getParent ( ) { return static_cast < AArch64DCFunction & > ( DCBasicBlock :: getParent ( ) ) ; } </s>

getParent - Return the last analyzed interval .


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned PairedPhys = 0 ; if ( VRM && VRM -> hasPhys ( Hint . second ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Hint . second ) , Odd , this ) ; if ( PairedPhys && MRI . isReserved ( PairedPhys ) ) PairedPhys = 0 ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = 0 , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i8 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> class VISIBILITY_HIDDEN X86MCInstLower { MCContext & Ctx ; Mangler * Mang ; X86AsmPrinter & AsmPrinter ; const X86Subtarget & getSubtarget ( ) const ; public : X86MCInstLower ( MCContext & ctx , Mangler * mang , X86AsmPrinter & asmprinter ) : Ctx ( ctx ) , Mang ( mang ) , AsmPrinter ( asmprinter ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCSymbol * GetPICBaseSymbol ( ) const ; MCSymbol * GetSymbolFromOperand ( const MachineOperand & MO ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; private : MachineModuleInfoMachO & getMachOMMI ( ) const ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> static bool sh_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( 1 && ! sh_cfun_interrupt_handler_p ( ) && ( ! flag_pic || TARGET_FDPIC || ( decl && ! ( TREE_PUBLIC ( decl ) || DECL_WEAK ( decl ) ) ) || ( decl && DECL_VISIBILITY ( decl ) != VISIBILITY_DEFAULT ) ) ) ; } </s>

If PIC , we can not make sibling calls to global functions because the PLT requires r12 to be live .


<s> rtx nds32_legitimize_pic_address ( rtx x ) { rtx addr = x ; rtx reg = gen_reg_rtx ( Pmode ) ; rtx pat ; int relax_group_id = nds32_alloc_relax_group_id ( ) ; if ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( x ) || SYMBOL_REF_LOCAL_P ( x ) ) ) ) { addr = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_GOTOFF ) ; addr = gen_rtx_CONST ( SImode , addr ) ; emit_insn ( gen_sym_got ( reg , addr , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , reg , pic_offset_table_rtx ) ; } else if ( GET_CODE ( x ) == SYMBOL_REF ) { addr = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_GOT ) ; addr = gen_rtx_CONST ( SImode , addr ) ; emit_insn ( gen_sym_got ( reg , addr , GEN_INT ( relax_group_id ) ) ) ; x = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , reg ) ) ; } else if ( GET_CODE ( x ) == CONST ) { addr = XEXP ( x , 0 ) ; gcc_assert ( GET_CODE ( addr ) == PLUS ) ; rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; if ( ( GET_CODE ( op0 ) == LABEL_REF || ( GET_CODE ( op0 ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( op0 ) || SYMBOL_REF_LOCAL_P ( op0 ) ) ) ) && GET_CODE ( op1 ) == CONST_INT ) { pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , op0 ) , UNSPEC_GOTOFF ) ; pat = gen_rtx_PLUS ( Pmode , pat , op1 ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; emit_insn ( gen_sym_got ( reg , pat , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , reg , pic_offset_table_rtx ) ; } else if ( GET_CODE ( op0 ) == SYMBOL_REF && GET_CODE ( op1 ) == CONST_INT ) { addr = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , op0 ) , UNSPEC_GOT ) ; addr = gen_rtx_CONST ( SImode , addr ) ; emit_insn ( gen_sym_got ( reg , addr , GEN_INT ( relax_group_id ) ) ) ; addr = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , reg ) ) ; emit_move_insn ( reg , addr ) ; if ( satisfies_constraint_Is15 ( op1 ) ) x = gen_rtx_PLUS ( Pmode , reg , op1 ) ; else { rtx tmp_reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( tmp_reg , op1 ) ) ; x = gen_rtx_PLUS ( Pmode , reg , tmp_reg ) ; } } else { debug_rtx ( x ) ; gcc_unreachable ( ) ; } } return x ; } </s>

Expand PIC code for @ GOTOFF and @ GOT . Example for @ GOTOFF : la $ r0 , symbol @ GOTOFF - > sethi $ ta , hi20 ( symbol @ GOTOFF ) ori $ ta , $ ta , lo12 ( symbol @ GOTOFF ) add $ r0 , $ ta , $ gp Example for @ GOT : la $ r0 , symbol @ GOT - > sethi $ ta , hi20 ( symbol @ GOT ) ori $ ta , $ ta , lo12 ( symbol @ GOT ) lw $ r0 , [ $ ta + $ gp ]


<s>
X86TTI
::
PopcntSupportKind
X86TTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
ST
->
hasPOPCNT
(
)
PSK_FastHardware
:
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { unsigned elements ; switch ( type_of_cost ) { case scalar_stmt : return ix86_cost -> scalar_stmt_cost ; case scalar_load : return ix86_cost -> scalar_load_cost ; case scalar_store : return ix86_cost -> scalar_store_cost ; case vector_stmt : return ix86_cost -> vec_stmt_cost ; case vector_load : return ix86_cost -> vec_align_load_cost ; case vector_store : return ix86_cost -> vec_store_cost ; case vec_to_scalar : return ix86_cost -> vec_to_scalar_cost ; case scalar_to_vec : return ix86_cost -> scalar_to_vec_cost ; case unaligned_load : case unaligned_store : return ix86_cost -> vec_unalign_load_cost ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_cost -> vec_stmt_cost ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; return ix86_cost -> vec_stmt_cost * ( elements / 2 + 1 ) ; default : gcc_unreachable ( ) ; } } </s>


<s> static void mep_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { int nsave = 4 - ( get_cumulative_args ( cum ) -> nregs + 1 ) ; if ( nsave > 0 ) cfun -> machine -> arg_regs_to_save = nsave ; * pretend_size = nsave * 4 ; } </s>


<s> static inline bool mode_supports_pre_incdec_p ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_PRE_INCDEC ) != 0 ) ; } </s>

Helper function to say whether a mode supports PRE_INC or PRE_DEC .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool SVEIntrinsicOpts :: runOnModule ( Module & M ) { bool Changed = false ; SmallSetVector < Function * , 4 > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: aarch64_sve_ptrue : for ( User * U : F . users ( ) ) Functions . insert ( cast < Instruction > ( U ) -> getFunction ( ) ) ; break ; default : break ; } } if ( ! Functions . empty ( ) ) Changed |= optimizeFunctions ( Functions ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool X86TargetLowering :: isTypeDesirableForOp ( unsigned Opc , EVT VT ) const { if ( ! isTypeLegal ( VT ) ) return false ; if ( Opc == ISD :: SHL && VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i8 ) return false ; if ( Opc == ISD :: MUL && VT == MVT :: i8 ) return false ; if ( VT == MVT :: i16 ) { switch ( Opc ) { default : break ; case ISD :: LOAD : case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : case ISD :: SHL : case ISD :: SRL : case ISD :: SUB : case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : return false ; } } return true ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type for the given node type .


<s> void MipsRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( MipsFI -> needGPSaveRestore ( ) ) MFI -> setObjectOffset ( MipsFI -> getGPFI ( ) , MipsFI -> getGPStackOffset ( ) ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> const uint32_t * SICRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , 16 ) ; bool isAligned = ( MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
void
mmix_output_register_setting
(
FILE
*
stream
,
int
regno
,
HOST_WIDEST_INT
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\t"
)
;
if
(
mmix_shiftable_wyde_value
(
(
unsigned
HOST_WIDEST_INT
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
unsigned
HOST_WIDEST_INT
)
value
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
(
unsigned
HOST_WIDEST_INT
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
"\n\tNEGU %s,0,%s"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
~
(
unsigned
HOST_WIDEST_INT
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
~
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
~
(
unsigned
HOST_WIDEST_INT
)
value
)
;
fprintf
(
stream
,
"\n\tNOR %s,%s,0"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
{
static
const
char
*
const
higher_parts
[
]
=
{
"L"
,
"ML"
,
"MH"
,
"H"
}
;
const
char
*
op
=
"SET"
;
const
char
*
line_begin
=
""
;
int
insns
=
0
;
int
i
;
HOST_WIDEST_INT
tmpvalue
=
value
;
for
(
i
=
0
;
i
<
4
&&
tmpvalue
!=
0
;
i
++
)
{
if
(
tmpvalue
&
65535
)
insns
++
;
tmpvalue
>>=
16
;
}
if
(
TARGET_BASE_ADDRESSES
&&
insns
==
3
)
{
fprintf
(
stream
,
"LDA %s,"
,
reg_names
[
regno
]
)
;
mmix_output_octa
(
stream
,
value
,
0
)
;
}
else
{
for
(
i
=
0
;
i
<
4
&&
value
!=
0
;
i
++
)
{
if
(
value
&
65535
)
{
fprintf
(
stream
,
"%s%s%s %s,#%x"
,
line_begin
,
op
,
higher_parts
[
i
]
,
reg_names
[
regno
]
,
(
int
)
(
value
&
65535
)
)
;
op
=
"INC"
;
line_begin
=
"\n\t"
;
}
value
>>=
16
;
}
}
}
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Output an optimal sequence for setting a register to a specific constant . Used in an alternative for const_ints in movdi , and when using large stack-frame offsets . Use do_begin_end to say if a line-starting TAB and newline before the first insn and after the last insn is wanted .


"Unexpected operand in reassociable instruction"

Return true when \P Inst has reassociable operands in the same \P MBB .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; bool Promote = false ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : break ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : Promote = true ; break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && MayFoldIntoStore ( Op ) ) return false ; Promote = true ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote = true ; } } PVT = MVT :: i32 ; return Promote ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s> bool hasReservedCallFrame ( const MachineFunction & MF ) const override { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( Kind . isMergeableConst ( ) && C ) { const unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; std :: string COMDATSymName ; if ( Kind . isMergeableConst4 ( ) ) { if ( Align <= 4 ) { COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; Align = 4 ; } } else if ( Kind . isMergeableConst8 ( ) ) { if ( Align <= 8 ) { COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; Align = 8 ; } } else if ( Kind . isMergeableConst16 ( ) ) { if ( Align <= 16 ) { COMDATSymName = "__xmm@" + scalarConstantToHexString ( C ) ; Align = 16 ; } } else if ( Kind . isMergeableConst32 ( ) ) { if ( Align <= 32 ) { COMDATSymName = "__ymm@" + scalarConstantToHexString ( C ) ; Align = 32 ; } } if ( ! COMDATSymName . empty ( ) ) return getContext ( ) . getCOFFSection ( ".rdata" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } return TargetLoweringObjectFile :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void mips_expand_vec_unpack ( rtx operands [ 2 ] , bool unsigned_p , bool high_p ) { machine_mode imode = GET_MODE ( operands [ 1 ] ) ; rtx ( * unpack ) ( rtx , rtx , rtx ) ; rtx ( * cmpgt ) ( rtx , rtx , rtx ) ; rtx tmp , dest , zero ; switch ( imode ) { case V8QImode : if ( high_p ) unpack = gen_loongson_punpckhbh ; else unpack = gen_loongson_punpcklbh ; cmpgt = gen_loongson_pcmpgtb ; break ; case V4HImode : if ( high_p ) unpack = gen_loongson_punpckhhw ; else unpack = gen_loongson_punpcklhw ; cmpgt = gen_loongson_pcmpgth ; break ; default : gcc_unreachable ( ) ; } zero = force_reg ( imode , CONST0_RTX ( imode ) ) ; if ( unsigned_p ) tmp = zero ; else { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpgt ( tmp , zero , operands [ 1 ] ) ) ; } dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; } </s>

Expand an integral vector unpack operation .


"Lowering returned the wrong number of results!"

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> TargetPassConfig * VETargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new VEPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> enum machine_mode arm_select_dominance_cc_mode ( rtx x , rtx y , HOST_WIDE_INT cond_or ) { enum rtx_code cond1 , cond2 ; int swapped = 0 ; if ( ( arm_select_cc_mode ( cond1 = GET_CODE ( x ) , XEXP ( x , 0 ) , XEXP ( x , 1 ) ) != CCmode ) || ( arm_select_cc_mode ( cond2 = GET_CODE ( y ) , XEXP ( y , 0 ) , XEXP ( y , 1 ) ) != CCmode ) ) return CCmode ; if ( cond_or == DOM_CC_NX_OR_Y ) cond1 = reverse_condition ( cond1 ) ; if ( cond1 != cond2 && ! comparison_dominates_p ( cond1 , cond2 ) && ( swapped = 1 , ! comparison_dominates_p ( cond2 , cond1 ) ) ) return CCmode ; if ( swapped ) { enum rtx_code temp = cond1 ; cond1 = cond2 ; cond2 = temp ; } switch ( cond1 ) { case EQ : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DEQmode ; switch ( cond2 ) { case EQ : return CC_DEQmode ; case LE : return CC_DLEmode ; case LEU : return CC_DLEUmode ; case GE : return CC_DGEmode ; case GEU : return CC_DGEUmode ; default : gcc_unreachable ( ) ; } case LT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTmode ; switch ( cond2 ) { case LT : return CC_DLTmode ; case LE : return CC_DLEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTmode ; switch ( cond2 ) { case GT : return CC_DGTmode ; case GE : return CC_DGEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case LTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTUmode ; switch ( cond2 ) { case LTU : return CC_DLTUmode ; case LEU : return CC_DLEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTUmode ; switch ( cond2 ) { case GTU : return CC_DGTUmode ; case GEU : return CC_DGEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case NE : gcc_assert ( cond1 == cond2 ) ; return CC_DNEmode ; case LE : gcc_assert ( cond1 == cond2 ) ; return CC_DLEmode ; case GE : gcc_assert ( cond1 == cond2 ) ; return CC_DGEmode ; case LEU : gcc_assert ( cond1 == cond2 ) ; return CC_DLEUmode ; case GEU : gcc_assert ( cond1 == cond2 ) ; return CC_DGEUmode ; default : gcc_unreachable ( ) ; } } </s>

Select a dominance comparison mode if possible for a test of the general form ( OP ( COND_OR ( X ) ( Y ) ) ( const_int 0 ) ) . We support three forms . COND_OR == DOM_CC_X_AND_Y = > ( X & & Y ) COND_OR == DOM_CC_NX_OR_Y = > ( ( ! X ) || Y ) COND_OR == DOM_CC_X_OR_Y = > ( X || Y ) In all cases OP will be either EQ or NE , but we do n't need to know which here . If we are unable to support a dominance comparison we return CC mode . This will then fail to match for the RTL expressions that generate this call .


<s> static int ix86_mode_needed ( int entity , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_needed ( insn ) ; case AVX_U128 : return ix86_avx_u128_mode_needed ( insn ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return ix86_i387_mode_needed ( entity , insn ) ; default : gcc_unreachable ( ) ; } return 0 ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
ARM64
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_arm64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_arm64_movw"
,
5
,
16
,
0
}
,
{
"fixup_arm64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_arm64_tlsdesc_call"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned LblOperand = Inst . getOpcode ( ) == AArch64 :: Bcc ? 1 : 0 ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ; Target = Addr + Imm ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> int eligible_for_call_delay ( rtx_insn * trial ) { rtx pat ; if ( get_attr_in_branch_delay ( trial ) == IN_BRANCH_DELAY_FALSE ) return 0 ; if ( TARGET_GNU_TLS || ! TARGET_TLS ) return 1 ; pat = PATTERN ( trial ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == PLUS ) { rtx unspec = XEXP ( SET_SRC ( pat ) , 1 ) ; if ( GET_CODE ( unspec ) == UNSPEC && ( XINT ( unspec , 1 ) == UNSPEC_TLSGD || XINT ( unspec , 1 ) == UNSPEC_TLSLDM ) ) return 0 ; } return 1 ; } </s>

Return nonzero if TRIAL can go into the call delay slot .


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { APInt KnownZero2 , KnownOne2 ; KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZero , KnownOne , Depth + 1 ) ; DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero2 , KnownOne2 , Depth + 1 ) ; KnownOne &= KnownOne2 ; KnownZero &= KnownZero2 ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static int current_file_function_operand ( rtx sym_ref ) { if ( ENCODED_SHORT_CALL_ATTR_P ( XSTR ( sym_ref , 0 ) ) ) return 1 ; if ( sym_ref == XEXP ( DECL_RTL ( current_function_decl ) , 0 ) && ! DECL_WEAK ( current_function_decl ) ) return 1 ; return 0 ; } </s>

Return 1 if the operand is a SYMBOL_REF for a function known to be in this file and the function is not weakly defined .


<s> LLT getStackValueStoreType ( const DataLayout & DL , const CCValAssign & VA , ISD :: ArgFlagsTy Flags ) const override { if ( Flags . isPointer ( ) ) return CallLowering :: ValueHandler :: getStackValueStoreType ( DL , VA , Flags ) ; return getStackValueStoreTypeHack ( VA ) ; } </s>

Return the in-memory size to write for the argument at VA .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; unsigned Offset = getTargetMachine ( ) . Options . StackProtectorGuardOffset ; if ( Offset == ( unsigned ) - 1 ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; const auto & GuardReg = getTargetMachine ( ) . Options . StackProtectorGuardReg ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> tree i960_build_va_list ( ) { return build_array_type ( unsigned_type_node , build_index_type ( size_one_node ) ) ; } </s>

Define the ` __builtin_va_list ' type for the ABI .


<s>
bool
ARM64InstrInfo
::
isGPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
ARM64
::
GPR32RegClass
.
contains
(
DstReg
)
||
ARM64
::
GPR64RegClass
.
contains
(
DstReg
)
)
;
}
case
ARM64
::
ORRXrs
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
ARM64
::
XZR
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
->
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ORRrs operands"
)
;
return
true
;
}
case
ARM64
::
ADDXri
:
if
(
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
->
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ADDXri operands"
)
;
return
true
;
}
}
return
false
;
}
</s>

Does this instruction rename a GPR without modifying bits ?


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> bool SystemZLDCleanup :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( * F . getFunction ( ) ) ) return false ; TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; MF = & F ; SystemZMachineFunctionInfo * MFI = F . getInfo < SystemZMachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .

SystemZ SystemZ SystemZ SystemZ SystemZ 2 0


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> bool X86TTIImpl :: isLegalMaskedScatter ( Type * DataType , Align Alignment ) { if ( ! ST -> hasAVX512 ( ) ) return false ; return isLegalMaskedGather ( DataType , Alignment ) ; } </s>

Return true if the target supports masked scatter .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
bool
NeedShadowCallStackProlog
=
false
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
,
NeedShadowCallStackProlog
)
;
auto
EmitMI
=
[
&
]
(
const
RegPairInfo
&
RPI
)
{
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
;
if
(
ReverseCSRRestoreSeq
)
for
(
const
RegPairInfo
&
RPI
:
reverse
(
RegPairs
)
)
EmitMI
(
RPI
)
;
else
for
(
const
RegPairInfo
&
RPI
:
RegPairs
)
EmitMI
(
RPI
)
;
if
(
NeedShadowCallStackProlog
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AArch64
::
LDRXpre
)
)
.
addReg
(
AArch64
::
X18
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
X18
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void or1k_output_mi_thunk ( FILE * file , tree , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = 1 ; epilogue_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 4 ) ; else this_rtx = gen_rtx_REG ( Pmode , 3 ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! satisfies_constraint_I ( delta_rtx ) ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; HOST_WIDE_INT lo = sext_hwi ( vcall_offset , 16 ) ; HOST_WIDE_INT hi = vcall_offset - lo ; rtx tmp ; tmp = gen_rtx_MEM ( Pmode , this_rtx ) ; emit_move_insn ( scratch , tmp ) ; if ( hi != 0 ) { rtx scratch2 = gen_rtx_REG ( Pmode , RV_REGNUM ) ; emit_move_insn ( scratch2 , GEN_INT ( hi ) ) ; emit_insn ( gen_add2_insn ( scratch , scratch2 ) ) ; } tmp = plus_constant ( Pmode , scratch , lo ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( scratch , tmp ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; gcc_assert ( SYMBOL_REF_LOCAL_P ( funexp ) ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; epilogue_completed = 0 ; } </s>

Worker for TARGET_ASM_OUTPUT_MI_THUNK . Output the assembler code for a thunk function . THUNK_DECL is the declaration for the thunk function itself , FUNCTION is the decl for the target function . DELTA is an immediate constant offset to be added to THIS . If VCALL_OFFSET is nonzero , the word at address ( * THIS + VCALL_OFFSET ) should be additionally added to THIS .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout & DL = getDataLayout ( ) ; bool isPPC64 = DL . getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer -> getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; else Section = OutStreamer -> getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Section ) ; for ( const auto & TOCMapPair : TOC ) { const MCSymbol * const TOCEntryTarget = TOCMapPair . first ; MCSymbol * const TOCEntryLabel = TOCMapPair . second ; OutStreamer -> emitLabel ( TOCEntryLabel ) ; if ( isPPC64 ) { TS . emitTCEntry ( * TOCEntryTarget ) ; } else { OutStreamer -> emitValueToAlignment ( 4 ) ; OutStreamer -> emitSymbolValue ( TOCEntryTarget , 4 ) ; } } } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( ! TM . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s> static rtx aarch64_add_offset ( machine_mode mode , rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! aarch64_plus_immediate ( GEN_INT ( offset ) , mode ) ) { rtx high ; high = GEN_INT ( offset ) ; offset = 0 ; high = aarch64_force_temporary ( mode , temp , high ) ; reg = aarch64_force_temporary ( mode , temp , gen_rtx_PLUS ( mode , high , reg ) ) ; } return plus_constant ( mode , reg , offset ) ; } </s>

Set DEST to SRC + OFFSET . MODE is the mode of the addition . FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should be set and CFA adjustments added to the generated instructions . TEMP1 , if nonnull , is a register of mode MODE that can be used as a temporary if register allocation is already complete . This temporary register may overlap DEST if ! FRAME_RELATED_P but must not overlap SRC . If TEMP1 is known to hold abs ( OFFSET ) , EMIT_MOVE_IMM can be set to false to avoid emitting the immediate again . TEMP2 , if nonnull , is a second temporary register that does n't overlap either DEST or REG . Since this function may be used to adjust the stack pointer , we must ensure that it can not cause transient stack deallocation ( for example by first incrementing SP and then decrementing when adjusting by a large immediate ) .


<s> bool splitFramePushPop ( const MachineFunction & MF ) const { if ( MF . getInfo < ARMFunctionInfo > ( ) -> shouldSignReturnAddress ( ) ) return true ; return ( getFramePointerReg ( ) == ARM :: R7 && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ; } </s>

Returns true if the frame setup is split into two separate pushes ( first r0-r7 , lr then r8-r11 ) , principally so that the frame pointer is adjacent to lr .


<s>
const
char
*
output_ubranch
(
rtx
dest
,
int
label
,
rtx
insn
)
{
static
char
string
[
64
]
;
bool
v9_form
=
false
;
char
*
p
;
if
(
TARGET_V9
&&
INSN_ADDRESSES_SET_P
(
)
)
{
int
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
260000
&&
delta
<
260000
)
v9_form
=
true
;
}
if
(
v9_form
)
strcpy
(
string
,
"ba%*,pt\t%%xcc, "
)
;
else
strcpy
(
string
,
"b%*\t"
)
;
p
=
strchr
(
string
,
'\0'
)
;
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
+
label
;
*
p
++
=
'%'
;
*
p
++
=
'('
;
*
p
=
'\0'
;
return
string
;
}
</s>

Output an unconditional branch to LABEL . INSN is the instruction .


<s> int expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; bool constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return 0 ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return 1 ; if ( TARGET_ALTIVEC && align >= 128 ) clear_step = 16 ; else if ( TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) clear_step = 8 ; else if ( TARGET_SPE && align >= 64 ) clear_step = 8 ; else clear_step = 4 ; if ( optimize_size && bytes > 3 * clear_step ) return 0 ; if ( ! optimize_size && bytes > 8 * clear_step ) return 0 ; for ( offset = 0 ; bytes > 0 ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= 16 && TARGET_ALTIVEC && align >= 128 ) { clear_bytes = 16 ; mode = V4SImode ; } else if ( bytes >= 8 && TARGET_SPE && align >= 64 ) { clear_bytes = 8 ; mode = V2SImode ; } else if ( bytes >= 8 && TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 8 ; mode = DImode ; if ( offset == 0 && align < 64 ) { rtx addr ; addr = XEXP ( orig_dest , 0 ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , 1 ) ) & 3 ) != 0 ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= 4 && ( align >= 32 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 4 ; mode = SImode ; } else if ( bytes >= 2 && ( align >= 16 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 2 ; mode = HImode ; } else { clear_bytes = 1 ; mode = QImode ; } dest = adjust_address ( orig_dest , mode , offset ) ; emit_move_insn ( dest , CONST0_RTX ( mode ) ) ; } return 1 ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> static bool csky_legitimate_constant_p ( machine_mode mode , rtx x ) { return ( ! csky_cannot_force_const_mem ( mode , x ) && CONSTANT_P ( x ) ) ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . Returns nonzero if the constant value X is a legitimate general operand . It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> void loongarch_expand_conditional_move ( rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; if ( FLOAT_MODE_P ( GET_MODE ( op1 ) ) ) loongarch_emit_float_compare ( & code , & op0 , & op1 ) ; else { loongarch_extend_comparands ( code , & op0 , & op1 ) ; op0 = force_reg ( word_mode , op0 ) ; if ( code == EQ || code == NE ) { op0 = loongarch_zero_if_equal ( op0 , op1 ) ; op1 = const0_rtx ; } else { bool invert = false ; rtx target = gen_reg_rtx ( GET_MODE ( op0 ) ) ; loongarch_emit_int_order_test ( code , & invert , target , op0 , op1 ) ; code = invert ? EQ : NE ; op0 = target ; op1 = const0_rtx ; } } rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; if ( INTEGRAL_MODE_P ( GET_MODE ( operands [ 2 ] ) ) && register_operand ( operands [ 2 ] , VOIDmode ) && register_operand ( operands [ 3 ] , VOIDmode ) ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; rtx temp = gen_reg_rtx ( mode ) ; rtx temp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ 2 ] , const0_rtx ) ) ) ; cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , GET_MODE ( op0 ) , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( temp2 , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ 3 ] , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( mode , temp , temp2 ) ) ) ; } else emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , cond , operands [ 2 ] , operands [ 3 ] ) ) ) ; } </s>

Perform the comparison in OPERANDS [ 1 ] . Move OPERANDS [ 2 ] into OPERANDS [ 0 ] if the condition holds , otherwise move OPERANDS [ 3 ] into OPERANDS [ 0 ] .


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONPreAllocPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None && ! DisableLdStOpti && ! Subtarget . isThumb ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .