<s>
SDValue
AArch64TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
CCAssignFn
*
RetCC
=
CallConv
==
CallingConv
::
WebKit_JS
RetCC_AArch64_WebKit_JS
:
RetCC_AArch64_AAPCS
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
realRVLocIdx
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
,
++
realRVLocIdx
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
realRVLocIdx
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
if
(
Outs
[
i
]
.
ArgVT
==
MVT
::
i1
)
{
Arg
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
MVT
::
i1
,
Arg
)
;
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
Arg
)
;
}
break
;
case
CCValAssign
::
BCvt
:
Arg
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
AArch64ISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN


<s> static bool arm_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool named ATTRIBUTE_UNUSED ) { return type && TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ; } </s>

Variable sized types are passed by reference . This is a GCC extension to the ARM ABI .


<s> TargetPassConfig * SparcTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SparcPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility guarantee"

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static unsigned int rx_hard_regno_nregs ( unsigned int , machine_mode mode ) { return CLASS_MAX_NREGS ( 0 , mode ) ; } </s>


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"argument must be a 16-bit constant immediate"

Function to expand an expression EXP which calls one of the Transactional Memory Extension ( TME ) builtins FCODE with the result going to TARGET .


<s>
unsigned
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
bool
isPPC64
=
PPCSubTarget
.
isPPC64
(
)
;
bool
isDarwinABI
=
PPCSubTarget
.
isDarwinABI
(
)
;
if
(
(
isPPC64
&&
VT
!=
MVT
::
i64
&&
VT
!=
MVT
::
i32
)
||
(
!
isPPC64
&&
VT
!=
MVT
::
i32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
MVT
::
i64
;
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
isDarwinABI
0
:
(
is64Bit
PPC
::
X2
:
PPC
::
R2
)
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
isDarwinABI
)
0
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


"argument %d of %qE must be in the range %d...%d"

"argument %d of %qE must be a multiple of %d"

"incompatible type for argument %d of %qE"

Report that ARG can not be passed to argument ARGNUM of intrinsic function FNNAME . OPERAND describes the operand to which ARGNUM is mapped .


<s> static bool ia64_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( FR_REGNO_P ( regno ) ) return ( GET_MODE_CLASS ( mode ) != MODE_CC && mode != BImode && mode != TFmode ) ; if ( PR_REGNO_P ( regno ) ) return mode == BImode || GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GR_REGNO_P ( regno ) ) return mode != XFmode && mode != XCmode && mode != RFmode ; if ( AR_REGNO_P ( regno ) ) return mode == DImode ; if ( BR_REGNO_P ( regno ) ) return mode == DImode ; return false ; } </s>


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_AArch64_CXX_TLS_Darwin_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_AArch64_RT_MostRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool X86TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , unsigned CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; return CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> static bool aarch64_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_SIMD && ( AARCH64_VALID_SIMD_QREG_MODE ( mode ) || AARCH64_VALID_SIMD_DREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P .


<s> static rtx ix86_static_chain ( const_tree fndecl_or_type , bool incoming_p ) { unsigned regno ; if ( DECL_P ( fndecl_or_type ) && ! DECL_STATIC_CHAIN ( fndecl_or_type ) ) return NULL ; if ( TARGET_64BIT ) { regno = R10_REG ; } else { const_tree fntype , fndecl ; unsigned int ccvt ; regno = CX_REG ; if ( TREE_CODE ( fndecl_or_type ) == FUNCTION_DECL ) { fntype = TREE_TYPE ( fndecl_or_type ) ; fndecl = fndecl_or_type ; } else { fntype = fndecl_or_type ; fndecl = NULL ; } ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) { regno = AX_REG ; } else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { regno = AX_REG ; } else if ( ix86_function_regparm ( fntype , fndecl ) == 3 ) { if ( incoming_p ) { if ( fndecl == current_function_decl ) ix86_static_chain_on_stack = true ; return gen_frame_mem ( SImode , plus_constant ( Pmode , arg_pointer_rtx , - 8 ) ) ; } regno = SI_REG ; } } return gen_rtx_REG ( Pmode , regno ) ; } </s>

Find a location for the static chain incoming to a nested function . This is a register , unless all free registers are used by arguments .


<s> bool MOVToLEAPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; if ( Seed != 0 ) RNG . reset ( Fn . getFunction ( ) -> getParent ( ) -> createRNG ( Seed , this , Fn . getFunction ( ) -> getName ( ) ) ) ; else if ( ! RNG ) RNG . reset ( Fn . getFunction ( ) -> getParent ( ) -> createRNG ( this ) ) ; bool Changed = false ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ) { ++ PreMOVtoLEAInstructionCount ; if ( I -> getNumOperands ( ) != 2 || ! I -> getOperand ( 0 ) . isReg ( ) || ! I -> getOperand ( 1 ) . isReg ( ) ) { ++ I ; continue ; } unsigned leaOpc ; if ( I -> getOpcode ( ) == X86 :: MOV32rr ) { leaOpc = X86 :: LEA32r ; } else if ( I -> getOpcode ( ) == X86 :: MOV64rr ) { leaOpc = X86 :: LEA64r ; } else { ++ I ; continue ; } unsigned int Roll = RNG -> Random ( 100 ) ; ++ MOVCandidates ; if ( Roll >= multicompiler :: MOVToLEAPercentage ) { ++ I ; continue ; } ++ ReplacedMOV ; MachineBasicBlock :: iterator J = I ; ++ I ; addRegOffset ( BuildMI ( * BB , J , J -> getDebugLoc ( ) , TII -> get ( leaOpc ) , J -> getOperand ( 0 ) . getReg ( ) ) , J -> getOperand ( 1 ) . getReg ( ) , false , 0 ) ; J -> eraseFromParent ( ) ; Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MipsAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) & 0xffff ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - 1 ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val ; else O << "$0" ; return false ; } } } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
void
PPCInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLWINM
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
MB
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
bool
useSubstituteMnemonic
=
false
;
if
(
SH
<=
31
&&
MB
==
0
&&
ME
==
(
31
SH
)
)
{
O
<<
"\tslwi "
;
useSubstituteMnemonic
=
true
;
}
if
(
SH
<=
31
&&
MB
==
(
32
SH
)
&&
ME
==
31
)
{
O
<<
"\tsrwi "
;
useSubstituteMnemonic
=
true
;
SH
=
32
SH
;
}
if
(
useSubstituteMnemonic
)
{
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
}
if
(
(
MI
->
getOpcode
(
)
==
PPC
::
OR
||
MI
->
getOpcode
(
)
==
PPC
::
OR8
)
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
O
<<
"\tmr "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLDICR
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
63
SH
==
ME
)
{
O
<<
"\tsldi "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
}
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


"256-bit vector operations only available in AVX2"

"Can only select PackedSingle or PackedDouble"

"256-bit insert/extract only available in AVX2"

Change the opcode of MI to execute in Domain .


"We have a different number of location and args?!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> static tree parse_signature ( const function_instance & instance , const char * format , vec < tree > & argument_types ) { tree return_type = parse_type ( instance , format ) ; while ( format [ 0 ] == ',' ) { format += 1 ; tree argument_type = parse_type ( instance , format ) ; unsigned int count = parse_count ( instance , format ) ; for ( unsigned int i = 0 ; i < count ; ++ i ) argument_types . quick_push ( argument_type ) ; } gcc_assert ( format [ 0 ] == 0 ) ; return return_type ; } </s>

Read a type signature for INSTANCE from FORMAT . Add the argument types to ARGUMENT_TYPES and return the return type . The format is a comma-separated list of types ( as for parse_type ) , with the first type being the return type and the rest being the argument types . Each argument type can be followed by an optional count ( as for parse_count ) .


<s> ScheduleHazardRecognizer * Thumb2InstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData & II ) const { return ( ScheduleHazardRecognizer * ) new Thumb2HazardRecognizer ( II ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> rtx rs6000_longcall_ref ( rtx call_ref ) { const char * call_name ; tree node ; if ( GET_CODE ( call_ref ) != SYMBOL_REF ) return call_ref ; call_name = XSTR ( call_ref , 0 ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } return force_reg ( Pmode , call_ref ) ; } </s>

Return a reference suitable for calling a function with the longcall attribute .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Mips ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool MipsTargetObjectFile :: IsConstantInSmallSection ( const Constant * CN , const TargetMachine & TM ) const { return ( static_cast < const MipsTargetMachine & > ( TM ) . getSubtargetImpl ( ) -> useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( CN -> getType ( ) ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> static bool aarch64_evpc_ext ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT location ; rtx offset ; if ( d -> vec_flags == VEC_SVE_PRED || ! d -> perm [ 0 ] . is_constant ( & location ) || ! d -> perm . series_p ( 0 , 1 , location , 1 ) ) return false ; if ( d -> testing_p ) return true ; if ( BYTES_BIG_ENDIAN && location != 0 && d -> vec_flags == VEC_ADVSIMD ) { std :: swap ( d -> op0 , d -> op1 ) ; location = d -> perm . length ( ) . to_constant ( ) - location ; } offset = GEN_INT ( location ) ; emit_set_insn ( d -> target , gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 3 , d -> op0 , d -> op1 , offset ) , UNSPEC_EXT ) ) ; return true ; } </s>


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DF : IX86_BUILTIN_SCATTERDIV4DF ; else return NULL_TREE ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DI : IX86_BUILTIN_SCATTERDIV4DI ; else return NULL_TREE ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SF : IX86_BUILTIN_SCATTERALTDIV8SF ; else return NULL_TREE ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SI : IX86_BUILTIN_SCATTERALTDIV8SI ; else return NULL_TREE ; break ; case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DF : IX86_BUILTIN_SCATTERDIV2DF ; else return NULL_TREE ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DI : IX86_BUILTIN_SCATTERDIV2DI ; else return NULL_TREE ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SF : IX86_BUILTIN_SCATTERALTDIV4SF ; else return NULL_TREE ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SI : IX86_BUILTIN_SCATTERALTDIV4SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return ix86_builtins [ code ] ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s>
static
void
rs6000_xcoff_output_toc_section_asm_op
(
const
char
*
data
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_MINIMAL_TOC
)
{
if
(
!
toc_initialized
)
{
fputs
(
"\t.toc\nLCTOC..1:\n"
,
asm_out_file
)
;
fputs
(
"\t.tc toc_table[TC],toc_table[RW]\n"
,
asm_out_file
)
;
toc_initialized
=
1
;
}
fprintf
(
asm_out_file
,
"\t.csect toc_table[RW]%s\n"
,
(
TARGET_32BIT
""
:
",3"
)
)
;
}
else
fputs
(
"\t.toc\n"
,
asm_out_file
)
;
}
</s>

A get_unnamed_section callback , used for switching to toc_section .


<s> rtl_opt_pass * make_pass_tag_collision_avoidance ( gcc :: context * ctxt ) { return new pass_tag_collision_avoidance ( ctxt ) ; } </s>


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>


<s> static bool rs6000_use_blocks_for_decl_p ( const_tree decl ) { return ! DECL_THREAD_LOCAL_P ( decl ) ; } </s>

Do not place thread-local symbols refs in the object blocks .


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , rtx offset ) { if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || INTVAL ( offset ) < - 1048575 || INTVAL ( offset ) > 1048575 ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - 4294967263 ) , HOST_WIDE_INT_C ( 4294967264 ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_LARGE : if ( CONSTANT_POOL_ADDRESS_P ( x ) ) return SYMBOL_SMALL_ABSOLUTE ; else return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> static bool ia64_return_in_memory ( tree valtype , tree fntype ATTRIBUTE_UNUSED ) { enum machine_mode mode ; enum machine_mode hfa_mode ; HOST_WIDE_INT byte_size ; mode = TYPE_MODE ( valtype ) ; byte_size = GET_MODE_SIZE ( mode ) ; if ( mode == BLKmode ) { byte_size = int_size_in_bytes ( valtype ) ; if ( byte_size < 0 ) return true ; } hfa_mode = hfa_element_mode ( valtype , 0 ) ; if ( hfa_mode != VOIDmode ) { int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; if ( byte_size / hfa_size > MAX_ARGUMENT_SLOTS ) return true ; else return false ; } else if ( byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS ) return true ; else return false ; } </s>

Return 1 if function return value returned in memory . Return 0 if it is in a register .


<s> unsigned OR1KTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return OR1K :: R3 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0 , op1 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 OP1 ) ) .


<s> static rtx ix86_expand_sse_comi ( const struct builtin_description * d , tree arglist , rtx target ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; rtx op2 ; enum machine_mode mode0 = insn_data [ d -> icode ] . operand [ 0 ] . mode ; enum machine_mode mode1 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) { rtx tmp = op1 ; op1 = op0 ; op0 = tmp ; } target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , 0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ d -> icode ] . operand [ 0 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! ( * insn_data [ d -> icode ] . operand [ 1 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , SET_DEST ( pat ) , const0_rtx ) ) ) ; return SUBREG_REG ( target ) ; } </s>

Subroutine of ix86_expand_builtin to take care of comi insns .


<s> int regs_used ( rtx x , int is_dest ) { enum rtx_code code ; const char * fmt ; int used = 0 ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( x ) + is_dest ) ) ; return 0 ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return 0 ; } case SET : return regs_used ( SET_SRC ( x ) , 0 ) | regs_used ( SET_DEST ( x ) , 16 ) ; case RETURN : return 0x00ffff00 ; case CLOBBER : is_dest = 1 ; break ; case MEM : is_dest = 0 ; break ; case CALL : used |= 0x00ff00f0 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( int i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { for ( int j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return used ; } </s>

Given a X , a pattern of an insn or a part of it , return a mask of used general registers . Bits 0 .. 15 mean that the respective registers are used as inputs in the instruction . Bits 16 .. 31 mean that the registers 0 .. 15 , respectively , are used as outputs , or are clobbered . IS_DEST should be set to 16 if X is the destination of a SET , else to 0 .


"priority was %#x (%d) before adjustment\n"

A C statement ( sans semicolon ) to update the integer scheduling priority INSN_PRIORITY ( INSN ) . Reduce the priority to execute the INSN earlier , increase the priority to execute INSN later . Do not define this macro if you do not need to adjust the scheduling priorities of insns .


<s> SDValue XNCMTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_XNCM ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>


<s>
bool
AArch64InstrInfo
::
isGPRZero
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
MOVZWi
:
case
AArch64
::
MOVZXi
:
if
(
MI
->
getOperand
(
1
)
.
isImm
(
)
&&
MI
->
getOperand
(
1
)
.
getImm
(
)
==
0
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
&&
"invalid MOVZi operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ANDWri
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
case
AArch64
::
ANDXri
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
;
case
TargetOpcode
::
COPY
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
}
return
false
;
}
</s>

Does this instruction set its full destination register to zero ?


<s> static int forward_branch_p ( rtx insn ) { rtx label = JUMP_LABEL ( insn ) ; while ( insn ) { if ( insn == label ) break ; else insn = NEXT_INSN ( insn ) ; } return ( insn == label ) ; } </s>

Return 1 if INSN branches forward . Should be using insn_addresses to avoid walking through all the insns ...


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: TailCall : return "MipsISD::TailCall" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSPDSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::TailCall "MipsISD::TailCall" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR" MipsISD::EXTP "MipsISD::EXTP" MipsISD::EXTPDP "MipsISD::EXTPDP" MipsISD::EXTR_S_H "MipsISD::EXTR_S_H" MipsISD::EXTR_W "MipsISD::EXTR_W" MipsISD::EXTR_R_W "MipsISD::EXTR_R_W" MipsISD::EXTR_RS_W "MipsISD::EXTR_RS_W" MipsISD::SHILO "MipsISD::SHILO" MipsISD::MTHLIP "MipsISD::MTHLIP" MipsISD::MULT "MipsISD::MULT" MipsISD::MULTU "MipsISD::MULTU" MipsISD::MADD_DSP "MipsISD::MADD_DSPDSP" MipsISD::MADDU_DSP "MipsISD::MADDU_DSP" MipsISD::MSUB_DSP "MipsISD::MSUB_DSP" MipsISD::MSUBU_DSP "MipsISD::MSUBU_DSP"


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMTargetMachine & ARM_TM = static_cast < const ARMTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; genExecuteOnly = ARM_TM . getSubtargetImpl ( ) -> genExecuteOnly ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_ARM_PURECODE ; TextSection = Ctx . getELFSection ( ".text" , Type , Flags , 0 , "" , 0U ) ; } } </s>

This method must be called before any actual lowering is done .


<s> tree rs6000_builtin_reciprocal ( tree fndecl ) { switch ( DECL_MD_FUNCTION_CODE ( fndecl ) ) { case RS6000_BIF_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BIF_RSQRT_2DF ] ; case RS6000_BIF_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BIF_RSQRT_4SF ] ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
const
ARMFunctionInfo
&
AFI
=
*
C
.
getMF
(
)
->
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveToReg
(
MBB
,
It
,
Reg
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromReg
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
if
(
!
MBB
.
isLiveIn
(
ARM
::
LR
)
)
MBB
.
addLiveIn
(
ARM
::
LR
)
;
saveLROnStack
(
MBB
,
It
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveOnStack
(
MBB
,
It
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
restoreLRFromStack
(
MBB
,
It
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromStack
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
ARM
ARM
0
"No callee-saved register available?"
ARM::LR
ARM::LR
ARM::LR
ARM::LR


<s> bool AArch64FrameLowering :: enableStackSlotScavenging ( const MachineFunction & MF ) const { const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; return AFI -> hasCalleeSaveStackFreeSpace ( ) ; } </s>

Returns true if the stack slot holes in the fixed and callee-save stack area should be used when allocating other stack locations to reduce stack size .


<s> const uint32_t * LanaiRegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
Register
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> unsigned PPCFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , uint64_t Imm ) { if ( MachineInstOpcode == PPC :: ADDI ) MRI . setRegClass ( Op0 , & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; else if ( MachineInstOpcode == PPC :: ADDI8 ) MRI . setRegClass ( Op0 , & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_ri ( MachineInstOpcode , UseRC , Op0 , Imm ) ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s> StringRef getPassName ( ) const override { return "MipsPreLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> unsigned postOffset ( Align Alignment = Align ( 1 ) ) const { unsigned PO = Offset + Size ; const Align PA = std :: max ( PostAlign , Alignment ) ; if ( PA == Align ( 1 ) ) return PO ; return PO + UnknownPadding ( PA , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 256 ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v4f32 ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


A helper function to handle isr stuff at the end of asm file .


<s> bool isKZeroMasked ( ) const { return ( Attributes & KZeroMasked ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds k-zero-masked opcodes .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsUnalignedMemoryAccesses ( MVT :: v2f64 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsUnalignedMemoryAccesses ( MVT :: f64 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } if ( Size >= 4 ) return MVT :: i32 ; else if ( Size >= 2 ) return MVT :: i16 ; return MVT :: Other ; } </s>


<s> bool X86ATTAsmParser :: ParseInstruction ( const StringRef & Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { StringRef PatchedName = StringSwitch < StringRef > ( Name ) . Case ( "sal" , "shl" ) . Case ( "salb" , "shlb" ) . Case ( "sall" , "shll" ) . Case ( "salq" , "shlq" ) . Case ( "salw" , "shlw" ) . Case ( "repe" , "rep" ) . Case ( "repz" , "rep" ) . Case ( "repnz" , "repne" ) . Default ( Name ) ; Operands . push_back ( X86Operand :: CreateToken ( PatchedName , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( getLexer ( ) . is ( AsmToken :: Star ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( X86Operand :: CreateToken ( "*" , Loc ) ) ; Parser . Lex ( ) ; } if ( X86Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( X86Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; } } if ( ( Name . startswith ( "shr" ) || Name . startswith ( "sar" ) || Name . startswith ( "shl" ) ) && Operands . size ( ) == 3 && static_cast < X86Operand * > ( Operands [ 1 ] ) -> isImm ( ) && isa < MCConstantExpr > ( static_cast < X86Operand * > ( Operands [ 1 ] ) -> getImm ( ) ) && cast < MCConstantExpr > ( static_cast < X86Operand * > ( Operands [ 1 ] ) -> getImm ( ) ) -> getValue ( ) == 1 ) { delete Operands [ 1 ] ; Operands . erase ( Operands . begin ( ) + 1 ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> static void swap_reorder ( rtx * a , int n ) { rtx insn = a [ n - 1 ] ; int i = n - 2 ; while ( i >= 0 && rank_for_reorder ( a + i , & insn ) >= 0 ) { a [ i + 1 ] = a [ i ] ; i -= 1 ; } a [ i + 1 ] = insn ; } </s>

Resort the array A in which only element at index N may be out of order .


<s> void arm_asm_declare_function_name ( FILE * file , const char * name , tree decl ) { size_t cmse_name_len ; char * cmse_name = 0 ; char cmse_prefix [ ] = "__acle_se_" ; if ( use_cmse && lookup_attribute ( "cmse_nonsecure_entry" , DECL_ATTRIBUTES ( decl ) ) ) { cmse_name_len = sizeof ( cmse_prefix ) + strlen ( name ) ; cmse_name = XALLOCAVEC ( char , cmse_name_len ) ; snprintf ( cmse_name , cmse_name_len , "%s%s" , cmse_prefix , name ) ; targetm . asm_out . globalize_label ( file , cmse_name ) ; ARM_DECLARE_FUNCTION_NAME ( file , cmse_name , decl ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( file , cmse_name , "function" ) ; } ARM_DECLARE_FUNCTION_NAME ( file , name , decl ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , "function" ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; ASM_OUTPUT_LABEL ( file , name ) ; if ( cmse_name ) ASM_OUTPUT_LABEL ( file , cmse_name ) ; ARM_OUTPUT_FN_UNWIND ( file , TRUE ) ; } </s>

Output in FILE asm statements needed to declare the NAME of the function defined by its DECL node .


<s> int hppa_can_use_return_insn_p ( ) { return ( reload_completed && ( compute_frame_size ( get_frame_size ( ) , 0 ) ? 0 : 1 ) && ! regs_ever_live [ 2 ] && ! frame_pointer_needed ) ; } </s>

This is only valid once reload has completed because it depends on knowing exactly how much ( if any ) frame there is and ... It 's only valid if there is no frame marker to de-allocate and ... It 's only valid if % r2 has n't been saved into the caller 's frame ( we 're not profiling and % r2 is n't live anywhere ) .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static bool ix86_const_not_ok_for_debug_p ( rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) != UNSPEC_GOTOFF ) return true ; if ( SYMBOL_REF_P ( x ) && strcmp ( XSTR ( x , 0 ) , GOT_SYMBOL_NAME ) == 0 ) return true ; return false ; } </s>

Return true if X should n't be emitted into the debug info . Disallow UNSPECs other than @ gotoff - we ca n't emit _GLOBAL_OFFSET_TABLE_ symbol easily into the .debug_info section , so we need not to delegitimize , but instead assemble as @ gotoff . Disallow _GLOBAL_OFFSET_TABLE_ SYMBOL_REF - the assembler magically assembles that as _GLOBAL_OFFSET_TABLE_- . expression .


<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: const_iterator I = MemOp2RegOpTable . find ( Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return 0 ; bool FoldedLoad = I -> second . second & ( 1 << 4 ) ; bool FoldedStore = I -> second . second & ( 1 << 5 ) ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; if ( LoadRegIndex ) * LoadRegIndex = I -> second . second & 0xf ; return I -> second . first ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s> static bool arm_9e_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB1 ) { switch ( code ) { case MULT : if ( arm_arch6m && arm_m_profile_small_mul ) * total = COSTS_N_INSNS ( 32 ) ; else * total = COSTS_N_INSNS ( 3 ) ; return true ; default : * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = COSTS_N_INSNS ( 2 ) ; return false ; } if ( mode == DImode ) { * total = COSTS_N_INSNS ( 5 ) ; return false ; } if ( mode == SImode ) { * total = COSTS_N_INSNS ( 2 ) ; return false ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( TARGET_HARD_FLOAT && ( mode == SFmode || ( mode == DFmode && ! TARGET_VFP_SINGLE ) ) ) { * total = COSTS_N_INSNS ( 1 ) ; return false ; } } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; } } </s>


<s> static int loongarch_flatten_aggregate_argument ( const_tree type , loongarch_aggregate_field fields [ 2 ] ) { if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - 1 ; return loongarch_flatten_aggregate_field ( type , fields , 0 , 0 ) ; } </s>

Identify candidate aggregates for passing in floating-point registers . Candidates have at most two fields after flattening .


<s> const Thumb2RegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
GPR32RegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MoveR3216
;
else
if
(
Mips
::
GPR32RegClass
.
contains
(
DestReg
)
&&
Mips
::
CPU16RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
else
if
(
(
SrcReg
==
Mips
::
HI0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mfhi16
,
SrcReg
=
0
;
else
if
(
(
SrcReg
==
Mips
::
LO0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mflo16
,
SrcReg
=
0
;
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> const uint32_t * MINA32RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return nullptr ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static bool aarch64_option_valid_attribute_p ( tree fndecl , tree , tree args , int ) { struct cl_target_option cur_target ; bool ret ; tree old_optimize ; tree new_target , new_optimize ; tree existing_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! existing_target && args == current_target_pragma ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_option_current_node ; return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options , & global_options_set ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , & global_options_set , existing_options ) ; } else cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options , & global_options_set ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options , & global_options_set ) ; if ( fndecl && ret ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & global_options_set , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret ; } </s>

Implement TARGET_OPTION_VALID_ATTRIBUTE_P . This is used to process attribute ( ( target ( `` ... '' ) ) ) .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static enum mips_shadow_set mips_use_shadow_register_set ( tree type ) { tree attr = lookup_attribute ( "use_shadow_register_set" , TYPE_ATTRIBUTES ( type ) ) ; tree args ; if ( attr == NULL ) return SHADOW_SET_NO ; args = TREE_VALUE ( attr ) ; if ( args == NULL ) return SHADOW_SET_YES ; return SHADOW_SET_INTSTACK ; } </s>

Return the mips_shadow_set if the `` use_shadow_register_set '' attribute is set for a function .


<s> MVT X86TargetLowering :: getSetCCResultType ( MVT VT ) const { return MVT :: i8 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; TII . restoreFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips::Move32R16 Mips::SP Mips::S0 Mips::SP


<s> bool LEGInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case LEG :: MOVi32 : { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( 0 ) . isDead ( ) ; const MachineOperand & MO = MI . getOperand ( 1 ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( LEG :: MOVLOi16 ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( LEG :: MOVHIi16 ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm & 0xffff ; const unsigned Hi16 = ( Imm >> 16 ) & 0xffff ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | LEGII :: MO_LO16 ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | LEGII :: MO_HI16 ) ; } MBB . erase ( MI ) ; return true ; } } } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> void MipsELFStreamer :: EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = 0 ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool X86FrameInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::CallJG SystemZ::CallBR


"%qE attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> static enum sched_fusion_type fusion_load_store ( rtx_insn * insn , rtx * base , rtx * offset ) { rtx x , dest , src ; enum sched_fusion_type fusion = SCHED_FUSION_LD ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return SCHED_FUSION_NONE ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! aarch64_mode_valid_for_sched_fusion_p ( dest_mode ) ) return SCHED_FUSION_NONE ; if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , 0 ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , 0 ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ; return fusion ; } </s>

If INSN is a load or store of address in the form of [ base+offset ] , extract the two parts and set to BASE and OFFSET . IS_LOAD is set to TRUE if it 's a load . Return TRUE if INSN is such an instruction , otherwise return FALSE .


<s> void Cpu0FrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { } </s>

Determine the frame layout but do not update the machine function .


<s>
const
char
*
emit_fusion_p9_load
(
rtx
reg
,
rtx
mem
,
rtx
tmp_reg
)
{
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
load_string
;
int
r
;
if
(
GET_CODE
(
mem
)
==
FLOAT_EXTEND
||
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
{
mem
=
XEXP
(
mem
,
0
)
;
mode
=
GET_MODE
(
mem
)
;
}
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_load, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
load_string
=
"lfs"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_DFORM_SCALAR
)
{
if
(
mode
==
SFmode
)
load_string
=
"lxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
E_QImode
:
load_string
=
"lbz"
;
break
;
case
E_HImode
:
load_string
=
"lhz"
;
break
;
case
E_SImode
:
case
E_SFmode
:
load_string
=
"lwz"
;
break
;
case
E_DImode
:
case
E_DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
load_string
=
"ld"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_load, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_load not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 load fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
load_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a load using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

powerpcspe
0
0
"emit_fusion_p9_load, bad reg #1"
"lfs"
"lfd"
"lxssp"
"lxsd"
"lbz"
"lhz"
"lwz"
"ld"
"emit_fusion_p9_load, bad reg #2"
"emit_fusion_p9_load not MEM"
0
"power9 load fusion"
""


<s> static bool rs6000_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , to ) ; unsigned from_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , from ) ; bool to_float128_vector_p = FLOAT128_VECTOR_P ( to ) ; bool from_float128_vector_p = FLOAT128_VECTOR_P ( from ) ; if ( to_float128_vector_p && from_float128_vector_p ) return true ; else if ( to_float128_vector_p || from_float128_vector_p ) return false ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return false ; if ( from_size < 8 || to_size < 8 ) return false ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return false ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return false ; return true ; } else return true ; } if ( TARGET_E500_DOUBLE && ( ( ( ( to ) == DFmode ) + ( ( from ) == DFmode ) ) == 1 || ( ( ( to ) == TFmode ) + ( ( from ) == TFmode ) ) == 1 || ( ( ( to ) == IFmode ) + ( ( from ) == IFmode ) ) == 1 || ( ( ( to ) == KFmode ) + ( ( from ) == KFmode ) ) == 1 || ( ( ( to ) == DDmode ) + ( ( from ) == DDmode ) ) == 1 || ( ( ( to ) == TDmode ) + ( ( from ) == TDmode ) ) == 1 || ( ( ( to ) == DImode ) + ( ( from ) == DImode ) ) == 1 ) ) return false ; if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs ( FIRST_FPR_REGNO , to ) > num_regs || hard_regno_nregs ( FIRST_FPR_REGNO , from ) > num_regs ) return false ; return ( from_size == 8 || from_size == 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return false ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( from ) + SPE_VECTOR_MODE ( to ) ) == 1 && reg_classes_intersect_p ( GENERAL_REGS , rclass ) ) return false ; return true ; } </s>


<s> void Mips16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; const char * Mips16HelperFunction = 0 ; bool NeedMips16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Subtarget -> inMips16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) Mips16HelperFunction = getMips16HelperFunction ( CLI . RetTy , CLI . Args , NeedMips16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = Mips :: V0 ; if ( NeedMips16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( Mips16HelperFunction , getPointerTy ( ) ) ; JumpTarget = getAddrGlobal ( JumpTarget , DAG , MipsII :: MO_GOT ) ; } else RegsToPass . push_front ( std :: make_pair ( ( unsigned ) Mips :: T9 , Callee ) ) ; } Ops . push_back ( JumpTarget ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .

Mips Mips Mips 0 Mips Mips Mips Mips Mips Mips Mips Mips::V0 Mips Mips MipsII::MO_GOT Mips::T9 Mips


<s> unsigned getSize ( ) { return CurType . Size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


"Unexpected instruction type for reassociation"

"Must have dead EFLAGS operand in reassociable instruction"

"Unexpected operand in reassociable instruction"

This is an architecture-specific helper function of reassociateOps .


<s> StringRef X86TargetLowering :: getStackProbeSymbolName ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) ) return "" ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? "___chkstk_ms" : "__chkstk" ; return Subtarget . isTargetCygMing ( ) ? "_alloca" : "_chkstk" ; } </s>

Returns the name of the symbol used to emit stack probes or the empty string if not applicable .


<s> void loongarch_output_ascii ( FILE * stream , const char * string , size_t len ) { size_t i ; int cur_pos ; cur_pos = 17 ; fprintf ( stream , "\t.ascii\t\"" ) ; for ( i = 0 ; i < len ; i ++ ) { int c ; c = ( unsigned char ) string [ i ] ; if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; cur_pos ++ ; } putc ( c , stream ) ; cur_pos ++ ; } else { fprintf ( stream , "\\%03o" , c ) ; cur_pos += 4 ; } if ( cur_pos > 72 && i + 1 < len ) { cur_pos = 17 ; fprintf ( stream , "\"\n\t.ascii\t\"" ) ; } } fprintf ( stream , "\"\n" ) ; } </s>


<s> int arm_const_double_inline_cost ( rtx val ) { rtx lowpart , highpart ; enum machine_mode mode ; mode = GET_MODE ( val ) ; if ( mode == VOIDmode ) mode = DImode ; gcc_assert ( GET_MODE_SIZE ( mode ) == 8 ) ; lowpart = gen_lowpart ( SImode , val ) ; highpart = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( GET_CODE ( lowpart ) == CONST_INT ) ; gcc_assert ( GET_CODE ( highpart ) == CONST_INT ) ; return ( arm_gen_constant ( SET , SImode , NULL_RTX , INTVAL ( lowpart ) , NULL_RTX , NULL_RTX , 0 , 0 ) + arm_gen_constant ( SET , SImode , NULL_RTX , INTVAL ( highpart ) , NULL_RTX , NULL_RTX , 0 , 0 ) ) ; } </s>

Return the cost of synthesizing a 64-bit constant VAL inline . Returns the number of insns needed , or 99 if we do n't know how to do it .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSizeInBits ( ) == 64 ) return false ; return isTypeLegal ( VT . getSimpleVT ( ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static bool ix86_macro_fusion_pair_p ( rtx_insn * condgen , rtx_insn * condjmp ) { rtx src , dest ; enum rtx_code ccode ; rtx compare_set = NULL_RTX , test_if , cond ; rtx alu_set = NULL_RTX , addr = NULL_RTX ; if ( ! any_condjump_p ( condjmp ) ) return false ; if ( get_attr_type ( condgen ) != TYPE_TEST && get_attr_type ( condgen ) != TYPE_ICMP && get_attr_type ( condgen ) != TYPE_INCDEC && get_attr_type ( condgen ) != TYPE_ALU ) return false ; compare_set = single_set ( condgen ) ; if ( compare_set == NULL_RTX && ! TARGET_FUSE_ALU_AND_BRANCH ) return false ; if ( compare_set == NULL_RTX ) { int i ; rtx pat = PATTERN ( condgen ) ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set_src = SET_SRC ( XVECEXP ( pat , 0 , i ) ) ; if ( GET_CODE ( set_src ) == COMPARE ) compare_set = XVECEXP ( pat , 0 , i ) ; else alu_set = XVECEXP ( pat , 0 , i ) ; } } if ( compare_set == NULL_RTX ) return false ; src = SET_SRC ( compare_set ) ; if ( GET_CODE ( src ) != COMPARE ) return false ; if ( ( MEM_P ( XEXP ( src , 0 ) ) && CONST_INT_P ( XEXP ( src , 1 ) ) ) || ( MEM_P ( XEXP ( src , 1 ) ) && CONST_INT_P ( XEXP ( src , 0 ) ) ) ) return false ; if ( MEM_P ( XEXP ( src , 0 ) ) ) addr = XEXP ( XEXP ( src , 0 ) , 0 ) ; else if ( MEM_P ( XEXP ( src , 1 ) ) ) addr = XEXP ( XEXP ( src , 1 ) , 0 ) ; if ( addr ) { ix86_address parts ; int ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; if ( rip_relative_addr_p ( & parts ) ) return false ; } test_if = SET_SRC ( pc_set ( condjmp ) ) ; cond = XEXP ( test_if , 0 ) ; ccode = GET_CODE ( cond ) ; if ( ! TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS && ( ccode == GE || ccode == GT || ccode == LE || ccode == LT ) ) return false ; if ( get_attr_type ( condgen ) == TYPE_TEST || get_attr_type ( condgen ) == TYPE_ICMP ) return true ; if ( ! TARGET_FUSE_ALU_AND_BRANCH || ! alu_set ) return false ; dest = SET_DEST ( alu_set ) ; if ( MEM_P ( dest ) ) return false ; if ( get_attr_type ( condgen ) == TYPE_INCDEC && ( ccode == GEU || ccode == GTU || ccode == LEU || ccode == LTU ) ) return false ; return true ; } </s>

Check whether current microarchitecture support macro fusion for insn pair `` CONDGEN + CONDJMP '' . Refer to `` Intel Architectures Optimization Reference Manual '' .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool ix86_can_use_return_insn_p ( void ) { struct ix86_frame frame ; if ( ! reload_completed || frame_pointer_needed || cfun -> machine -> func_type != TYPE_NORMAL ) return 0 ; if ( crtl -> args . pops_args && crtl -> args . size >= 32768 ) return 0 ; ix86_compute_frame_layout ( & frame ) ; return ( frame . stack_pointer_offset == UNITS_PER_WORD && ( frame . nregs + frame . nsseregs ) == 0 ) ; } </s>

Return 1 if it is appropriate to emit ` ret ' instructions in the body of a function . Do this only if the epilogue is simple , needing a couple of insns . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then . Return 0 if there is no frame marker to de-allocate .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlign
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> const MCExpr * SparcELFTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MachineModuleInfoELF & ELFMMI = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , ".DW.stub" , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( StubSym . getPointer ( ) == 0 ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return SparcMCExpr :: Create ( SparcMCExpr :: VK_Sparc_R_DISP32 , MCSymbolRefExpr :: Create ( SSym , Ctx ) , Ctx ) ; } return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> bool sh_lra_p ( void ) { return sh_lra_flag ; } </s>

Return true if we use LRA instead of reload pass .


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LW_P8 ) || ( Opc == Mips :: LD ) || ( Opc == Mips :: LD_P8 ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LWC1_P8 ) || ( Opc == Mips :: LDC1 ) || ( Opc == Mips :: LDC164 ) || ( Opc == Mips :: LDC164_P8 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( x ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> static bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ) { tree fntype ; if ( CALL_EXPR_STATIC_CHAIN ( exp ) ) return false ; if ( decl ) fntype = TREE_TYPE ( decl ) ; else fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE && ! ( decl && decl == current_function_decl ) ) { function_args_iterator args_iter ; tree type ; int nvreg = 0 ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > 0 ) return false ; } if ( DEFAULT_ABI == ABI_DARWIN || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && decl && ! DECL_EXTERNAL ( decl ) && ! DECL_WEAK ( decl ) && ( * targetm . binds_local_p ) ( decl ) ) || ( DEFAULT_ABI == ABI_V4 && ( ! TARGET_SECURE_PLT || ! flag_pic || ( decl && ( * targetm . binds_local_p ) ( decl ) ) ) ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> int arm_legitimate_address_p ( enum machine_mode mode , rtx x , RTX_CODE outer , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; if ( use_ldrd && GET_CODE ( x ) == POST_MODIFY && GET_CODE ( addend ) == REG ) return 0 ; return ( ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) && arm_legitimate_index_p ( mode , addend , outer , strict_p ) ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT ) ) ) return 1 ; else if ( mode == TImode ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && arm_legitimate_index_p ( mode , xop0 , outer , strict_p ) ) ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( arm_address_register_rtx_p ( xop0 , strict_p ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid ARM state address operand .


<s> static void choose_basereg ( HOST_WIDE_INT cfa_offset , rtx & base_reg , HOST_WIDE_INT & base_offset , unsigned int align_reqested , unsigned int * align ) { const struct machine_function * m = cfun -> machine ; unsigned int hfp_align ; unsigned int drap_align ; unsigned int sp_align ; bool hfp_ok = fp_valid_at ( cfa_offset ) ; bool drap_ok = m -> fs . drap_valid ; bool sp_ok = sp_valid_at ( cfa_offset ) ; hfp_align = drap_align = sp_align = INCOMING_STACK_BOUNDARY ; if ( align_reqested ) { if ( m -> fs . realigned ) hfp_align = drap_align = sp_align = crtl -> stack_alignment_needed ; else if ( m -> fs . sp_realigned ) sp_align = crtl -> stack_alignment_needed ; hfp_ok = hfp_ok && hfp_align >= align_reqested ; drap_ok = drap_ok && drap_align >= align_reqested ; sp_ok = sp_ok && sp_align >= align_reqested ; } if ( m -> use_fast_prologue_epilogue ) { if ( hfp_ok ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( drap_ok ) { base_reg = crtl -> drap_reg ; base_offset = 0 - cfa_offset ; } else if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = 16 , tlen ; if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( drap_ok ) { toffset = 0 - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( hfp_ok ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; } } } if ( align ) { if ( base_reg == stack_pointer_rtx ) * align = sp_align ; else if ( base_reg == crtl -> drap_reg ) * align = drap_align ; else if ( base_reg == hard_frame_pointer_rtx ) * align = hfp_align ; } } </s>

Choose a base register based upon alignment requested , speed and/or size .


<s> static inline HOST_WIDE_INT htm_spr_num ( enum rs6000_builtins code ) { if ( code == HTM_BUILTIN_GET_TFHAR || code == HTM_BUILTIN_SET_TFHAR ) return TFHAR_SPR ; else if ( code == HTM_BUILTIN_GET_TFIAR || code == HTM_BUILTIN_SET_TFIAR ) return TFIAR_SPR ; else if ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR ) return TEXASR_SPR ; gcc_assert ( code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return TEXASRU_SPR ; } </s>

Return the appropriate SPR number associated with the given builtin .


<s> const MCSection * SystemZMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , MCSectionELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) , false ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> void SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : { if ( tryInlineAsm ( N ) ) return ; break ; } case SPISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; return ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: i32 , MulLHS , MulRHS ) ; SDValue ResultHigh = SDValue ( Mul , 1 ) ; ReplaceUses ( SDValue ( N , 0 ) , ResultHigh ) ; CurDAG -> RemoveDeadNode ( N ) ; return ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool loongarch_split_move_insn_p ( rtx dest , rtx src ) { return loongarch_split_move_p ( dest , src ) ; } </s>

Return true if a move from SRC to DEST in INSN should be split .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . elt ( 0 ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


<s> void AArch64MacroFusion :: apply ( ScheduleDAGInstrs * DAGInstrs ) { ScheduleDAGMI * DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; for ( SUnit & ISU : DAG -> SUnits ) scheduleAdjacentImpl ( DAG , ISU ) ; scheduleAdjacentImpl ( DAG , DAG -> ExitSU ) ; } </s>

Apply the profile inference algorithm for a given function .


<s> void function_expander :: add_address_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 ) ; create_address_operand ( & m_ops . last ( ) , x ) ; } </s>

Add an address operand with value X . The static operand data says what mode and form the address must have .


<s> bool ARMTTIImpl :: isLegalMaskedGather ( Type * Ty , Align Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == 32 && Alignment >= 4 ) || ( EltWidth == 16 && Alignment >= 2 ) || EltWidth == 8 ) ; } </s>

Return true if the target supports masked gather .


<s> StackOffset AArch64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED ) { rtx l1 , labelno , pic_tmp , pic_rtx , pic_reg ; if ( crtl -> uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( Pmode , pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; pic_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; pic_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pic_rtx ) , UNSPEC_GOTSYM_OFF ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; if ( TARGET_32BIT ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } else { if ( arm_pic_register != INVALID_REGNUM && REGNO ( pic_reg ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb1 ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_reg , pic_reg , labelno ) ) ; } else if ( arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && REGNO ( pic_reg ) <= LAST_LO_REGNUM ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; emit_move_insn ( gen_rtx_REG ( Pmode , arm_pic_register ) , pic_reg ) ; emit_use ( gen_rtx_REG ( Pmode , arm_pic_register ) ) ; } else emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } } emit_use ( pic_reg ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool X86RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( Reg == FramePtr && TFI -> hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> static unsigned long thumb1_compute_save_core_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( frame_pointer_needed ) mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function .


<s> bool X86TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT SrcVT = ExtVal . getOperand ( 0 ) . getValueType ( ) ; if ( SrcVT . getScalarType ( ) == MVT :: i1 ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> rtx rs6000_got_register ( rtx value ATTRIBUTE_UNUSED ) { if ( ! can_create_pseudo_p ( ) && ! df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) df_set_regs_ever_live ( RS6000_PIC_OFFSET_TABLE_REGNUM , true ) ; crtl -> uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } </s>


<s> BaseKind getKind ( ) const { return Kind ; } </s>


Try to find a mode with the given mode_suffix_info fields . Return the mode on success or MODE_none on failure .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


"CPU0 DAG to DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> const MipsRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .