<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> const char * LEGTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case LEGISD :: RET_FLAG : return "RetFlag" ; case LEGISD :: LOAD_SYM : return "LOAD_SYM" ; case LEGISD :: MOVEi32 : return "MOVEi32" ; case LEGISD :: CALL : return "CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void rs6000_emit_sCOND ( enum rtx_code code , rtx result ) { rtx condition_rtx ; enum machine_mode op_mode ; enum rtx_code cond_code ; condition_rtx = rs6000_generate_compare ( code ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( TARGET_E500 && rs6000_compare_fp_p && ! TARGET_FPRS && TARGET_HARD_FLOAT ) { rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , 0 ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; enum machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( rs6000_compare_op0 ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( rs6000_compare_op1 ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || rs6000_compare_fp_p ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , result , condition_rtx ) ) ; } } </s>


<s> bool AZPRAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( AZPRInstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; return false ; } return true ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static void rs6000_emit_prologue_move_from_cr ( rtx reg ) { if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ 8 ] , count = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == 1 ) { rtvec p = rtvec_alloc ( 1 ) ; rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ 0 ] ) ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - cr_reg [ 0 ] ) ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ; } } emit_insn ( gen_prologue_movesi_from_cr ( reg ) ) ; } </s>

Emit prologue code to store CR fields that need to be saved into REG . This function should only be called when moving the non-volatile CRs to REG , it is not a general purpose routine to move the entire set of CRs to REG . Specifically , gen_prologue_movesi_from_cr ( ) does not contain uses of the volatile CRs .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> DecodeStatus SystemZDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { Size = 0 ; if ( Bytes . size ( ) < 2 ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ 0 ] < 0x40 ) { Size = 2 ; Table = DecoderTable16 ; } else if ( Bytes [ 0 ] < 0xc0 ) { Size = 4 ; Table = DecoderTable32 ; } else { Size = 6 ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) return MCDisassembler :: Fail ; uint64_t Inst = 0 ; for ( uint64_t I = 0 ; I < Size ; ++ I ) Inst = ( Inst << 8 ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


"preferPredicateOverEpilogue: not a single block "

"preferPredicateOverEpilogue: hardware-loop is not "

Query the target whether it would be prefered to create a predicated vector loop , which can avoid the need to emit a scalar epilogue loop .


<s> static void register_vector_type ( vector_type_index type ) { tree vectype = abi_vector_types [ type ] ; tree id = get_identifier ( vector_types [ type ] . acle_name ) ; tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ; if ( decl && TREE_CODE ( decl ) == TYPE_DECL && TYPE_MAIN_VARIANT ( TREE_TYPE ( decl ) ) == vectype ) vectype = TREE_TYPE ( decl ) ; acle_vector_types [ 0 ] [ type ] = vectype ; } </s>

Register vector type TYPE under its risv_vector.h name .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI ) ; break ; case Mips :: PseudoLDC1 : expandDPLoadStore ( MBB , MI , Mips :: LDC1 , Mips :: LWC1 ) ; break ; case Mips :: PseudoSDC1 : expandDPLoadStore ( MBB , MI , Mips :: SDC1 , Mips :: SWC1 ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static char sizetochar ( int size ) { switch ( size ) { case 64 : return 'd' ; case 32 : return 's' ; case 16 : return 'h' ; case 8 : return 'b' ; default : gcc_unreachable ( ) ; } } </s>


<s> static bool rs6000_return_in_msb ( const_tree valtype ) { return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && rs6000_function_arg_padding ( TYPE_MODE ( valtype ) , valtype ) == PAD_UPWARD ) ; } </s>

Specify whether values returned in registers should be at the most significant end of a register . We want aggregates returned by value to match the way aggregates are passed to functions .


<s> AArch64Subtarget :: AArch64Subtarget ( StringRef TT , StringRef CPU , StringRef FS ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , HasNEON ( false ) , HasCrypto ( false ) , TargetTriple ( TT ) { ParseSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static rtx nds32_legitimize_target ( enum insn_code icode , rtx target ) { enum machine_mode mode = insn_data [ icode ] . operand [ 0 ] . mode ; if ( ! target || GET_MODE ( target ) != mode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , mode ) ) return gen_reg_rtx ( mode ) ; else return target ; } </s>

Return a legitimate rtx for instruction ICODE 's return value . Use TARGET if it 's not null , has the right mode , and satisfies operand 0 's predicate .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static rtx ix86_expand_v1ti_to_ti ( rtx x ) { rtx result = gen_reg_rtx ( TImode ) ; if ( TARGET_SSE2 ) { rtx temp = force_reg ( V2DImode , gen_lowpart ( V2DImode , x ) ) ; rtx lo = gen_lowpart ( DImode , result ) ; emit_insn ( gen_vec_extractv2didi ( lo , temp , const0_rtx ) ) ; rtx hi = gen_highpart ( DImode , result ) ; emit_insn ( gen_vec_extractv2didi ( hi , temp , const1_rtx ) ) ; } else emit_move_insn ( result , gen_lowpart ( TImode , x ) ) ; return result ; } </s>

Expand move of V1TI mode register X to a new TI mode register .


<s> bool X86TargetLowering :: isBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: ANDNP : case X86ISD :: PCMPGT : case X86ISD :: FMAX : case X86ISD :: FMIN : case X86ISD :: FANDN : case X86ISD :: VPSHA : case X86ISD :: VPSHL : case X86ISD :: VSHLV : case X86ISD :: VSRLV : case X86ISD :: VSRAV : return true ; } return TargetLoweringBase :: isBinOp ( Opcode ) ; } </s>

Add x86-specific opcodes to the default list .


<s> static int arm_tls_operand_p_1 ( rtx * x , void * data ATTRIBUTE_UNUSED ) { if ( GET_CODE ( * x ) == SYMBOL_REF ) return SYMBOL_REF_TLS_MODEL ( * x ) != 0 ; if ( GET_CODE ( * x ) == UNSPEC && XINT ( * x , 1 ) == UNSPEC_TLS ) return - 1 ; return 0 ; } </s>


<s> void VEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; emitEpilogueInsns ( MF , MBB , MBBI , NumBytes , true ) ; } </s>


"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static int ia64_function_arg_words ( const_tree type , machine_mode mode ) { int words ; if ( mode == BLKmode ) words = int_size_in_bytes ( type ) ; else words = GET_MODE_SIZE ( mode ) ; return ( words + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Return the number of words required to hold a quantity of TYPE and MODE when passed as an argument .


<s> static std :: unique_ptr < MipsOperand > CreateMem ( std :: unique_ptr < MipsOperand > Base , const MCExpr * Off , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = std :: make_unique < MipsOperand > ( k_Memory , Parser ) ; Op -> Mem . Base = Base . release ( ) ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
,
STI
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
0
)
)
;
return
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> int ix86_attr_length_vex_default ( rtx_insn * insn , bool has_0f_opcode , bool has_vex_w ) { int i , reg_only = 2 + 1 ; bool has_mem = false ; if ( ! has_0f_opcode || has_vex_w ) return 3 + 1 ; if ( ! TARGET_64BIT ) return 2 + 1 ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( REG_P ( recog_data . operand [ i ] ) ) { if ( GET_MODE ( recog_data . operand [ i ] ) == DImode && GENERAL_REG_P ( recog_data . operand [ i ] ) ) return 3 + 1 ; if ( REX_INT_REGNO_P ( recog_data . operand [ i ] ) || REX_SSE_REGNO_P ( recog_data . operand [ i ] ) ) reg_only = 3 + 1 ; } else if ( MEM_P ( recog_data . operand [ i ] ) ) { if ( x86_extended_reg_mentioned_p ( recog_data . operand [ i ] ) ) return 3 + 1 ; has_mem = true ; } return has_mem ? 2 + 1 : reg_only ; } </s>

Compute default value for `` length_vex '' attribute . It includes 2 or 3 byte VEX prefix and 1 opcode byte .


<s> static tree gen_regparm_prefix ( tree decl , unsigned nregs ) { unsigned total = 0 ; const char * asmname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; char * newsym ; tree formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return NULL_TREE ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { unsigned parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - 1 ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total += parm_size ; formal_type = TREE_CHAIN ( formal_type ) ; } } if ( nregs > total / BITS_PER_WORD ) nregs = total / BITS_PER_WORD ; gcc_assert ( nregs <= 9 ) ; newsym = alloca ( 3 + strlen ( asmname ) + 1 ) ; return get_identifier_with_length ( newsym , sprintf ( newsym , "_%u@%s" , nregs , asmname ) ) ; } </s>

Return string which is the former assembler name modified with an _n @ prefix where n represents the number of arguments passed in registers


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "sinl" , "sqrtl" , "truncl" } ; const char * const * End = LibCalls + array_lengthof ( LibCalls ) ; MipsTargetLowering :: LTStr Comp ; for ( const char * const * I = LibCalls ; I < End - 1 ; ++ I ) assert ( Comp ( * I , * ( I + 1 ) ) ) ; return std :: binary_search ( LibCalls , End , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>


<s> bool useAA ( ) const override { return UseAA ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> unsigned size ( ) const { return Insts . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> virtual bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const LLVM_OVERRIDE { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"AArch64 FastISel doesn't support types larger than i64"

This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the given getelementptr index value .


"Could not generate addis value for fusion"

Emit the addis instruction that will be part of a fused instruction sequence .


<s> int arm_count_output_move_double_insns ( rtx * operands ) { int count ; rtx ops [ 2 ] ; ops [ 0 ] = operands [ 0 ] ; ops [ 1 ] = operands [ 1 ] ; output_move_double ( ops , false , & count ) ; return count ; } </s>

Compute the number of instructions emitted by output_move_double .


<s> static void mips_expand_to_rtl_hook ( void ) { mips_set_tuning_info ( ) ; } </s>


<s> pure_scalable_type_info :: analysis_result pure_scalable_type_info :: analyze ( const_tree type ) { gcc_assert ( pieces . is_empty ( ) ) ; if ( type == error_mark_node ) return NO_ABI_IDENTITY ; if ( TYPE_SIZE ( type ) && integer_zerop ( TYPE_SIZE ( type ) ) ) return NO_ABI_IDENTITY ; piece p = { } ; if ( aarch64_sve :: builtin_type_p ( type , & p . num_zr , & p . num_pr ) ) { machine_mode mode = TYPE_MODE_RAW ( type ) ; gcc_assert ( VECTOR_MODE_P ( mode ) && ( ! TARGET_SVE || aarch64_sve_mode_p ( mode ) ) ) ; p . mode = p . orig_mode = mode ; add_piece ( p ) ; return IS_PST ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) return analyze_array ( type ) ; if ( TREE_CODE ( type ) == RECORD_TYPE ) return analyze_record ( type ) ; return ISNT_PST ; } </s>

Count how many times each regno is referenced as base address for a memory access .


<s> static rtx loongarch_force_binary ( machine_mode mode , enum rtx_code code , rtx op0 , rtx op1 ) { rtx reg ; reg = gen_reg_rtx ( mode ) ; loongarch_emit_binary ( code , reg , op0 , op1 ) ; return reg ; } </s>

Compute ( CODE OP0 OP1 ) and store the result in a new register of mode MODE . Return that new register .


<s> void ix86_rewrite_tls_address_1 ( rtx * loc ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { rtx addr = XEXP ( * loc , 0 ) ; rtx * x = & addr ; while ( GET_CODE ( * x ) == PLUS ) { int i ; for ( i = 0 ; i < 2 ; i ++ ) { rtx u = XEXP ( * x , i ) ; if ( GET_CODE ( u ) == ZERO_EXTEND ) u = XEXP ( u , 0 ) ; if ( GET_CODE ( u ) == UNSPEC && XINT ( u , 1 ) == UNSPEC_TP ) { addr_space_t as = DEFAULT_TLS_SEG_REG ; * x = XEXP ( * x , 1 - i ) ; * loc = replace_equiv_address_nv ( * loc , addr , true ) ; set_mem_addr_space ( * loc , as ) ; return ; } } x = & XEXP ( * x , 0 ) ; } iter . skip_subrtxes ( ) ; } } } </s>

Rewrite * LOC so that it refers to a default TLS address space .


<s> int aarch64_movk_shift ( const wide_int_ref & and_val , const wide_int_ref & ior_val ) { unsigned int precision = and_val . get_precision ( ) ; unsigned HOST_WIDE_INT mask = 0xffff ; for ( unsigned int shift = 0 ; shift < precision ; shift += 16 ) { if ( and_val == ~ mask && ( ior_val & mask ) == ior_val ) return shift ; mask <<= 16 ; } return - 1 ; } </s>

Test whether : X = ( X & AND_VAL ) | IOR_VAL ; can be implemented using : MOVK X , # ( IOR_VAL > > shift ) , LSL # shift Return the shift if so , otherwise return -1 .


<s>
void
X86AsmPrinter
::
printPCRelImm
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"Unknown pcrel immediate operand"
)
;
case
MachineOperand
::
MO_Register
:
printOperand
(
MI
,
OpNo
,
O
)
;
return
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
;
case
MachineOperand
::
MO_MachineBasicBlock
:
O
<<
*
MO
.
getMBB
(
)
->
getSymbol
(
)
;
return
;
case
MachineOperand
::
MO_GlobalAddress
:
case
MachineOperand
::
MO_ExternalSymbol
:
printSymbolOperand
(
MO
,
O
)
;
return
;
}
}
</s>


<s>
MCSymbol
*
XNCMMCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .

XNCM
XNCM
"Unknown target flag on GV operand"
0


<s>
void
aarch64_print_patchable_function_entry
(
FILE
*
file
,
unsigned
HOST_WIDE_INT
patch_area_size
,
bool
record_p
)
{
if
(
cfun
->
machine
->
label_is_assembled
&&
aarch64_bti_enabled
(
)
&&
!
cgraph_node
::
get
(
cfun
->
decl
)
->
only_called_directly_p
(
)
)
{
rtx_insn
*
insn
=
next_real_nondebug_insn
(
get_insns
(
)
)
;
if
(
insn
&&
INSN_P
(
insn
)
&&
GET_CODE
(
PATTERN
(
insn
)
)
==
UNSPEC_VOLATILE
&&
XINT
(
PATTERN
(
insn
)
,
1
)
==
UNSPECV_BTI_C
)
delete_insn
(
insn
)
;
asm_fprintf
(
file
,
"\thint\t34 // bti c\n"
)
;
}
default_print_patchable_function_entry
(
file
,
patch_area_size
,
record_p
)
;
}
</s>

Implement PRINT_PATCHABLE_FUNCTION_ENTRY . Check if the patch area is after the function label and emit a BTI if necessary .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void aarch64_pop_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment , rtx * cfi_ops ) { machine_mode mode = ( regno1 <= R30_REGNUM ) ? E_DImode : E_DFmode ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg1 , * cfi_ops ) ; if ( regno2 == INVALID_REGNUM ) { rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; } } </s>

Pop the two registers numbered REGNO1 , REGNO2 from the stack , adjusting it afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes into CFI_OPS .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool F2003fFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return false ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::BITCAST
ISD::SRL
ISD::SRA


<s>
bool
ARMAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

ARM
ARM
0
"unexpected inline asm memory operand"
"["
"]"


<s> unsigned getMinPrefetchStride ( ) const override { return MinPrefetchStride ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> static void ix86_simd_clone_adjust ( struct cgraph_node * node ) { const char * str = NULL ; gcc_assert ( node -> decl == cfun -> decl ) ; switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) str = "sse2" ; break ; case 'c' : if ( ! TARGET_AVX ) str = "avx" ; break ; case 'd' : if ( ! TARGET_AVX2 ) str = "avx2" ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , 0 ) ; gcc_assert ( ok ) ; pop_cfun ( ) ; ix86_reset_previous_fndecl ( ) ; ix86_set_current_function ( node -> decl ) ; } </s>

Add target attribute to SIMD clone NODE if needed .


"ARM pre- register allocation load / store optimization pass"

getPassName - Return a nice clean name for a pass .


<s> void Mips16FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RI = TII . getRegisterInfo ( ) ; const BitVector Reserved = RI . getReservedRegs ( MF ) ; bool SaveS2 = Reserved [ Mips :: S2 ] ; if ( SaveS2 ) SavedRegs . set ( Mips :: S2 ) ; if ( hasFP ( MF ) ) SavedRegs . set ( Mips :: S0 ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static tree parse_type ( const function_instance & instance , const char * & format ) { int ch = * format ++ ; if ( ch == '_' ) return void_type_node ; if ( ch == 'a' ) { ch = * format ++ ; if ( ch == 'l' ) return build_const_pointer ( instance . memory_scalar_type ( ) ) ; if ( ch == 'p' ) return const_ptr_type_node ; if ( ch == 's' ) return build_pointer_type ( instance . memory_scalar_type ( ) ) ; gcc_unreachable ( ) ; } if ( ch == 'b' ) return instance . base_vector_type ( ) ; if ( ch == 'd' ) return instance . displacement_vector_type ( ) ; if ( ch == 'e' ) { if ( startswith ( format , "pattern" ) ) { format += 7 ; return acle_svpattern ; } if ( startswith ( format , "prfop" ) ) { format += 5 ; return acle_svprfop ; } gcc_unreachable ( ) ; } if ( ch == 's' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return scalar_types [ type_suffixes [ suffix ] . vector_type ] ; } if ( ch == 't' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; vector_type_index vector_type = type_suffixes [ suffix ] . vector_type ; unsigned int num_vectors = instance . vectors_per_tuple ( ) ; return acle_vector_types [ num_vectors - 1 ] [ vector_type ] ; } if ( ch == 'v' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return acle_vector_types [ 0 ] [ type_suffixes [ suffix ] . vector_type ] ; } gcc_unreachable ( ) ; } </s>

Read and return a type from FORMAT for function INSTANCE . Advance FORMAT beyond the type string . The format is : _ - void al - array pointer for loads ap - array pointer for prefetches as - array pointer for stores b - base vector type ( from a _ < m0 > base suffix ) d - displacement vector type ( from a _ < m1 > index or _ < m1 > offset suffix ) e < name > - an enum with the given name s < elt > - a scalar type with the given element suffix t < elt > - a vector or tuple type with given element suffix [ * 1 ] v < elt > - a vector with the given element suffix where < elt > has the format described above parse_element_type [ * 1 ] the vectors_per_tuple function indicates whether the type should be a tuple , and if so , how many vectors it should contain .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> unsigned PPCTargetLowering :: combineRepeatedFPDivisors ( ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : return 3 ; case PPC :: DIR_440 : case PPC :: DIR_A2 : case PPC :: DIR_E500 : case PPC :: DIR_E500mc : case PPC :: DIR_E5500 : return 2 ; } } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool PPCTTIImpl :: isHardwareLoopProfitable ( Loop * L , ScalarEvolution & SE , AssumptionCache & AC , TargetLibraryInfo * LibInfo , TTI :: HardwareLoopInfo & HWLoopInfo ) { const PPCTargetMachine & TM = ST -> getTargetMachine ( ) ; TargetSchedModel SchedModel ; SchedModel . init ( ST ) ; unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , 32 > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( 6 * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo ) ) return false ; SmallVector < BasicBlock * , 4 > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = 0 , FalseWeight = 0 ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( 0 ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . isPPC64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , 1 ) ; return true ; } </s>

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> void AArch64InstPrinter :: printImplicitlyTypedVectorList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printVectorList ( MI , OpNum , O , "" ) ; } </s>

Print a list of vector registers where the type suffix is implicit ( i.e .


<s> bool X86InstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case X86 :: AND8rr : case X86 :: AND16rr : case X86 :: AND32rr : case X86 :: AND64rr : case X86 :: OR8rr : case X86 :: OR16rr : case X86 :: OR32rr : case X86 :: OR64rr : case X86 :: XOR8rr : case X86 :: XOR16rr : case X86 :: XOR32rr : case X86 :: XOR64rr : case X86 :: IMUL16rr : case X86 :: IMUL32rr : case X86 :: IMUL64rr : case X86 :: PANDrr : case X86 :: PORrr : case X86 :: PXORrr : case X86 :: VPANDrr : case X86 :: VPANDYrr : case X86 :: VPORrr : case X86 :: VPORYrr : case X86 :: VPXORrr : case X86 :: VPXORYrr : case X86 :: MAXCPDrr : case X86 :: MAXCPSrr : case X86 :: MAXCSDrr : case X86 :: MAXCSSrr : case X86 :: MINCPDrr : case X86 :: MINCPSrr : case X86 :: MINCSDrr : case X86 :: MINCSSrr : case X86 :: VMAXCPDrr : case X86 :: VMAXCPSrr : case X86 :: VMAXCPDYrr : case X86 :: VMAXCPSYrr : case X86 :: VMAXCSDrr : case X86 :: VMAXCSSrr : case X86 :: VMINCPDrr : case X86 :: VMINCPSrr : case X86 :: VMINCPDYrr : case X86 :: VMINCPSYrr : case X86 :: VMINCSDrr : case X86 :: VMINCSSrr : return true ; case X86 :: ADDPDrr : case X86 :: ADDPSrr : case X86 :: ADDSDrr : case X86 :: ADDSSrr : case X86 :: MULPDrr : case X86 :: MULPSrr : case X86 :: MULSDrr : case X86 :: MULSSrr : case X86 :: VADDPDrr : case X86 :: VADDPSrr : case X86 :: VADDPDYrr : case X86 :: VADDPSYrr : case X86 :: VADDSDrr : case X86 :: VADDSSrr : case X86 :: VMULPDrr : case X86 :: VMULPSrr : case X86 :: VMULPDYrr : case X86 :: VMULPSYrr : case X86 :: VMULSDrr : case X86 :: VMULSSrr : return Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s> static void mips_maybe_swap_ready ( rtx_insn * * ready , int pos1 , int pos2 , int limit ) { if ( pos1 < pos2 && INSN_PRIORITY ( ready [ pos1 ] ) + limit >= INSN_PRIORITY ( ready [ pos2 ] ) ) { rtx_insn * temp ; temp = ready [ pos1 ] ; ready [ pos1 ] = ready [ pos2 ] ; ready [ pos2 ] = temp ; } } </s>

If the priority of the instruction at POS2 in the ready queue READY is within LIMIT units of that of the instruction at POS1 , swap the instructions if POS2 is not already less than POS1 .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? d -> nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vuzpv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vuzpv4hf_internal ; break ; case V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> bool loongarch_do_optimize_block_move_p ( void ) { if ( target_flags_explicit & MASK_MEMCPY ) return ! TARGET_MEMCPY ; return ! optimize_size ; } </s>

Return true if loongarch_expand_block_move is the preferred implementation of the 'cpymemsi ' template .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( parseOptionalToken ( AsmToken :: Plus ) ) { NewOpcode = std :: string ( Name ) ; NewOpcode += '+' ; Name = NewOpcode ; } if ( parseOptionalToken ( AsmToken :: Minus ) ) { NewOpcode = std :: string ( Name ) ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( parseOptionalToken ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( ! parseOptionalToken ( AsmToken :: EndOfStatement ) ) { if ( parseToken ( AsmToken :: Comma ) || ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s> void VEInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '%' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> void ix86_split_convert_uns_si_sse ( rtx operands [ ] ) { machine_mode vecmode ; rtx value , large , zero_or_two31 , input , two31 , x ; large = operands [ 1 ] ; zero_or_two31 = operands [ 2 ] ; input = operands [ 3 ] ; two31 = operands [ 4 ] ; vecmode = GET_MODE ( large ) ; value = gen_rtx_REG ( vecmode , REGNO ( operands [ 0 ] ) ) ; if ( MEM_P ( input ) ) { if ( vecmode == V4SFmode ) emit_insn ( gen_vec_setv4sf_0 ( value , CONST0_RTX ( V4SFmode ) , input ) ) ; else emit_insn ( gen_sse2_loadlpd ( value , CONST0_RTX ( V2DFmode ) , input ) ) ; } else { input = gen_rtx_REG ( vecmode , REGNO ( input ) ) ; emit_move_insn ( value , CONST0_RTX ( vecmode ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_sse_movss ( value , value , input ) ) ; else emit_insn ( gen_sse2_movsd ( value , value , input ) ) ; } emit_move_insn ( large , two31 ) ; emit_move_insn ( zero_or_two31 , MEM_P ( two31 ) ? large : two31 ) ; x = gen_rtx_fmt_ee ( LE , vecmode , large , value ) ; emit_insn ( gen_rtx_SET ( VOIDmode , large , x ) ) ; x = gen_rtx_AND ( vecmode , zero_or_two31 , large ) ; emit_insn ( gen_rtx_SET ( VOIDmode , zero_or_two31 , x ) ) ; x = gen_rtx_MINUS ( vecmode , value , zero_or_two31 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , value , x ) ) ; large = gen_rtx_REG ( V4SImode , REGNO ( large ) ) ; emit_insn ( gen_ashlv4si3 ( large , large , GEN_INT ( 31 ) ) ) ; x = gen_rtx_REG ( V4SImode , REGNO ( value ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_fix_truncv4sfv4si2 ( x , value ) ) ; else emit_insn ( gen_sse2_cvttpd2dq ( x , value ) ) ; value = x ; emit_insn ( gen_xorv4si3 ( value , value , large ) ) ; } </s>

Post-reload splitter for converting an SF or DFmode value in an SSE register into an unsigned SImode .


<s> long long rs6000_const_f32_to_i32 ( rtx operand ) { long long value ; const struct real_value * rv = CONST_DOUBLE_REAL_VALUE ( operand ) ; gcc_assert ( GET_MODE ( operand ) == SFmode ) ; REAL_VALUE_TO_TARGET_SINGLE ( * rv , value ) ; return value ; } </s>

Convert a SFmode constant to the integer bit pattern .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( NumOps == 0 || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - 1 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) * Size ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineInstr
&
MI
)
const
{
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOAD_STACK_GUARD
)
{
expandLoadStackGuard
(
MI
)
;
MI
.
getParent
(
)
->
erase
(
MI
)
;
return
true
;
}
if
(
MI
.
getOpcode
(
)
==
ARM
::
MEMCPY
)
{
expandMEMCPY
(
MI
)
;
return
true
;
}
if
(
!
MI
.
isCopy
(
)
||
Subtarget
.
dontWidenVMOVS
(
)
||
!
Subtarget
.
hasFP64
(
)
)
return
false
;
Register
DstRegS
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
Register
SrcRegS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
.
definesRegister
(
DstRegD
,
TRI
)
||
MI
.
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
.
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
MI
)
;
MachineInstrBuilder
MIB
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
;
int
ImpDefIdx
=
MI
.
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
.
removeOperand
(
ImpDefIdx
)
;
MI
.
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
.
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
.
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
MI
.
getOperand
(
1
)
.
setIsUndef
(
)
;
MIB
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
.
getOperand
(
1
)
.
isKill
(
)
)
{
MI
.
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
.
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void SystemZInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void function_builder :: add_overloaded_function ( const function_instance & instance , uint64_t required_extensions ) { char * name = get_name ( instance , true ) ; if ( registered_function * * map_value = m_overload_names . get ( name ) ) { gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value ) -> required_extensions & ~ required_extensions ) == 0 ) ; obstack_free ( & m_string_obstack , name ) ; } else { registered_function & rfn = add_function ( instance , name , m_overload_type , NULL_TREE , required_extensions , true , m_direct_overloads ) ; m_overload_names . put ( name , & rfn ) ; } } </s>

Add one function decl for INSTANCE , to be used with manual overload resolution . REQUIRED_EXTENSIONS are the set of architecture extensions that the function requires . For simplicity , deal with duplicate attempts to add the same function , including cases in which the new function requires more features than the original one did . In that case we 'll check whether the required features are available as part of resolving the function to the relevant unique function .


<s> bool SystemZTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isUInt < 32 > ( Imm ) || isUInt < 32 > ( - Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> unsigned ARM64InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM64 :: STRWui : case ARM64 :: STRXui : case ARM64 :: STRBui : case ARM64 :: STRHui : case ARM64 :: STRSui : case ARM64 :: STRDui : case ARM64 :: STRQui : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: ELFNumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ELFArgGPRs [ I ] ) ; if ( ! MF . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool SICRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static int supersparc_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { enum attr_type insn_type ; if ( recog_memoized ( insn ) < 0 ) return cost ; insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == 0 ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + 3 ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + 3 ; } if ( insn_type == TYPE_SHIFT ) return cost + 3 ; } else { if ( insn_type == TYPE_IALU || insn_type == TYPE_SHIFT ) return 0 ; } return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s>
MachineBasicBlock
*
OR1KTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
Opc
==
OR1K
::
Select
||
Opc
==
OR1K
::
Selectf32
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
OR1K
::
BF
)
)
.
addMBB
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
OR1K
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static machine_mode arm_floatn_mode ( int n , bool extended ) { if ( ! extended && n == 16 ) return arm_fp16_format == ARM_FP16_FORMAT_IEEE ? HFmode : VOIDmode ; return default_floatn_mode ( n , extended ) ; } </s>

Implement TARGET_FLOATN_MODE . Make very sure that we do n't provide _Float16 if we are using anything other than ieee format for 16-bit floating point . Otherwise , punt to the default implementation .


<s> bool KudeyarPassConfig :: addPreEmitPass ( ) { return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool loongarch_valid_lo_sum_p ( enum loongarch_symbol_type symbol_type , machine_mode mode , rtx x ) { int align , size ; if ( loongarch_symbol_insns ( symbol_type , mode ) == 0 ) return false ; if ( ! loongarch_split_symbol_type ( symbol_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : 1 ) ; size = ( SYMBOL_REF_DECL ( x ) && DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ? tree_to_uhwi ( DECL_SIZE ( SYMBOL_REF_DECL ( x ) ) ) : 2 * BITS_PER_WORD ) ; } else { align = GET_MODE_ALIGNMENT ( mode ) ; size = GET_MODE_BITSIZE ( mode ) ; } if ( size > BITS_PER_WORD && ( ! TARGET_STRICT_ALIGN || size > align ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYMBOL_TYPE .


<s> unsigned AArch64InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: STRWui : case AArch64 :: STRXui : case AArch64 :: STRBui : case AArch64 :: STRHui : case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>


<s> virtual unsigned int execute ( function * ) { return sparc_do_work_around_errata ( ) ; } </s>


<s> static rtx ia64_dfa_pre_cycle_insn ( void ) { return dfa_pre_cycle_insn ; } </s>

The following function returns the pseudo insn DFA_PRE_CYCLE_INSN used by the DFA insn scheduler .


<s> static bool ix86_ok_to_clobber_flags ( rtx_insn * insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; df_ref use ; bitmap live ; while ( insn ) { if ( NONDEBUG_INSN_P ( insn ) ) { FOR_EACH_INSN_USE ( use , insn ) if ( DF_REF_REG_USE_P ( use ) && DF_REF_REGNO ( use ) == FLAGS_REG ) return false ; if ( insn_defines_reg ( FLAGS_REG , INVALID_REGNUM , insn ) ) return true ; } if ( insn == BB_END ( bb ) ) break ; insn = NEXT_INSN ( insn ) ; } live = df_get_live_out ( bb ) ; return ! REGNO_REG_SET_P ( live , FLAGS_REG ) ; } </s>

Return true if it is legal to clobber flags by INSN and false otherwise .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentInstruction ( Inst , Operands , getContext ( ) , Out ) ; Out . EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } if ( Triple ( TM -> getTargetTriple ( ) ) . isOSNaCl ( ) ) { addPass ( createX86NaClRewritePass ( ) ) ; } } </s>


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallPtrSet < Constant * , 8 > AlreadyChecked ; for ( Instruction & I : instructions ( & F ) ) { for ( Value * Op : I . operand_values ( ) ) { Constant * Cst = dyn_cast < Constant > ( Op ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } return LocalChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
.
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
||
ST
.
slow3OpsLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void x86_order_regs_for_local_alloc ( void ) { int pos = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] = 0 ; } </s>

Order the registers for register allocator .


<s> bool ARMBaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; unsigned SrcReg , SrcReg2 ; int CmpMask , CmpValue ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> static bool xstormy16_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case CONST_INT : if ( INTVAL ( x ) < 16 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) / 2 ; else if ( INTVAL ( x ) < 256 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( 2 ) ; return true ; case MULT : * total = COSTS_N_INSNS ( 35 + 6 ) ; return true ; case DIV : * total = COSTS_N_INSNS ( 51 - 6 ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


<s>
void
Cpu0InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Cpu0
::
LD
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


"ADJSTACKDOWN and ADJSTACKUP should be no-ops"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
void
rx_emit_stack_popm
(
rtx
*
operands
,
bool
is_popm
)
{
HOST_WIDE_INT
stack_adjust
;
HOST_WIDE_INT
last_reg
;
rtx
first_push
;
gcc_assert
(
CONST_INT_P
(
operands
[
0
]
)
)
;
stack_adjust
=
INTVAL
(
operands
[
0
]
)
;
gcc_assert
(
GET_CODE
(
operands
[
1
]
)
==
PARALLEL
)
;
last_reg
=
XVECLEN
(
operands
[
1
]
,
0
)
(
is_popm
2
:
3
)
;
first_push
=
XVECEXP
(
operands
[
1
]
,
0
,
1
)
;
gcc_assert
(
SET_P
(
first_push
)
)
;
first_push
=
SET_DEST
(
first_push
)
;
gcc_assert
(
REG_P
(
first_push
)
)
;
if
(
is_popm
)
asm_fprintf
(
asm_out_file
,
"\tpopm\t%s-%s\n"
,
reg_names
[
REGNO
(
first_push
)
]
,
reg_names
[
REGNO
(
first_push
)
+
last_reg
]
)
;
else
asm_fprintf
(
asm_out_file
,
"\trtsd\t#%d, %s-%s\n"
,
(
int
)
stack_adjust
,
reg_names
[
REGNO
(
first_push
)
]
,
reg_names
[
REGNO
(
first_push
)
+
last_reg
]
)
;
}
</s>

Generate a POPM or RTSD instruction that matches the given operands .


This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
void
ARM64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
ARM64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
bool
Valid
;
StringRef
Name
=
ARM64DB
::
DBarrierMapper
(
)
.
toString
(
getBarrier
(
)
,
Valid
)
;
if
(
Valid
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
k_Memory
:
OS
<<
"<memory>"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
bool
Valid
;
StringRef
Name
=
ARM64PRFM
::
PRFMMapper
(
)
.
toString
(
getPrefetch
(
)
,
Valid
)
;
if
(
Valid
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_Shifter
:
{
unsigned
Val
=
getShifter
(
)
;
OS
<<
"<"
<<
ARM64_AM
::
getShiftName
(
ARM64_AM
::
getShiftType
(
Val
)
)
<<
" #"
<<
ARM64_AM
::
getShiftValue
(
Val
)
<<
">"
;
break
;
}
case
k_Extend
:
{
unsigned
Val
=
getExtend
(
)
;
OS
<<
"<"
<<
ARM64_AM
::
getExtendName
(
ARM64_AM
::
getArithExtendType
(
Val
)
)
<<
" #"
<<
ARM64_AM
::
getArithShiftValue
(
Val
)
<<
">"
;
break
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .

ARM64
ARM64
"<fpimm "
"("
ARM64_AM::getFPImmFloat
") >"
ARM64DB::DBarrierMapper
"<barrier "
">"
"<barrier invalid #"
">"
"<memory>"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
ARM64PRFM::PRFMMapper
"<prfop "
">"
"<prfop invalid #"
">"
"<"
ARM64_AM::getShiftName
ARM64_AM::getShiftType
" #"
ARM64_AM::getShiftValue
">"
"<"
ARM64_AM::getExtendName
ARM64_AM::getArithExtendType
" #"
ARM64_AM::getArithShiftValue
">"


<s> void emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) override { EmitMappingSymbol ( "$d" ) ; MCELFStreamer :: emitValueImpl ( Value , Size , Loc ) ; } </s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .


<s> static int mips_immediate_operand_p ( int code , HOST_WIDE_INT x ) { switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : return true ; case ROTATE : case ROTATERT : return ISA_HAS_ROR ; case AND : case IOR : case XOR : return SMALL_OPERAND_UNSIGNED ( x ) ; case PLUS : case LT : case LTU : return SMALL_OPERAND ( x ) ; case EQ : case NE : case GT : case GTU : return x == 0 ; case GE : case GEU : return x == 1 ; case LE : return SMALL_OPERAND ( x + 1 ) ; case LEU : return SMALL_OPERAND ( x + 1 ) && x + 1 != 0 ; case SIGN_EXTRACT : case ZERO_EXTRACT : return ISA_HAS_EXT_INS ; default : return x == 0 ; } } </s>

Return true if there is a non-MIPS16 instruction that implements CODE and if that instruction accepts X as an immediate operand .


<s>
bool
MipsSEDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Base
,
Offset
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_m
:
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_R
:
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_ZC
:
if
(
Subtarget
->
inMicroMipsMode
(
)
)
{
if
(
selectAddrRegImm12
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
Subtarget
->
hasMips32r6
(
)
)
{
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( ) const { if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Mode64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: FeatureFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s> Optional < MCFixupKind > X86AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { if ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ) { if ( Name == "R_X86_64_NONE" ) return FK_NONE ; } else { if ( Name == "R_386_NONE" ) return FK_NONE ; } } return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static void fold_mergeeo_helper ( gimple_stmt_iterator * gsi , gimple * stmt , int use_odd ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree lhs_type = TREE_TYPE ( lhs ) ; int n_elts = TYPE_VECTOR_SUBPARTS ( lhs_type ) ; tree permute_type ; permute_type = map_to_integral_tree_type ( lhs_type ) ; tree_vector_builder elts ( permute_type , VECTOR_CST_NELTS ( arg0 ) , 1 ) ; for ( int i = 0 ; i < n_elts / 2 ; i ++ ) { elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , 2 * i + use_odd ) ) ; elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , 2 * i + use_odd + n_elts ) ) ; } tree permute = elts . build ( ) ; gimple * g = gimple_build_assign ( lhs , VEC_PERM_EXPR , arg0 , arg1 , permute ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the vector merge [ eo ] built-ins .


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( * F . getFunction ( ) ) ) return false ; const SystemZSubtarget & ST = F . getSubtarget < SystemZSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( * TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOCAL_ESCAPE
)
{
MachineOperand
&
FI
=
MI
.
getOperand
(
FIOperandNum
)
;
FI
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"Branch-taken block should post-dominate first candidate"

"Error in code produced by branch coalescing"

runOnMachineFunction - Emit the function body .


<s>
bool
SystemZAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
emitFunctionHeader
(
MF
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
VerboseAsm
&&
(
I
->
pred_empty
(
)
||
I
->
isOnlyReachableByFallthrough
(
)
)
)
{
}
else
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
printMachineInstruction
(
II
)
;
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size\t"
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
'\n'
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
return
false
;
}
</s>

SystemZ
SystemZ
"\n\n"
"\t.size\t"
", .-"


<s> void SICFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; SICFunctionInfo * SICFI = MF . getInfo < SICFunctionInfo > ( ) ; const SICInstrInfo & TII = * static_cast < const SICInstrInfo * > ( STI . getInstrInfo ( ) ) ; const SICRegisterInfo & RegInfo = * static_cast < const SICRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; SICABIInfo ABI = STI . getABI ( ) ; unsigned SP = SIC :: X ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

SIC SIC SIC SIC SIC SIC SIC SIC SIC SIC SIC::X


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
Reserved
.
set
(
ARM
::
SP
)
;
Reserved
.
set
(
ARM
::
PC
)
;
Reserved
.
set
(
ARM
::
FPSCR
)
;
Reserved
.
set
(
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
Reserved
.
set
(
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
Reserved
.
set
(
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
Reserved
.
set
(
ARM
::
R9
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
Reserved
.
set
(
ARM
::
D16
,
ARM
::
D31
+
1
)
;
}
const
TargetRegisterClass
*
RC
=
&
ARM
::
GPRPairRegClass
;
for
(
TargetRegisterClass
::
iterator
I
=
RC
->
begin
(
)
,
E
=
RC
->
end
(
)
;
I
!=
E
;
++
I
)
for
(
MCSubRegIterator
SI
(
*
I
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
Reserved
.
set
(
*
I
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static rtx rs6000_pre_atomic_barrier ( rtx mem , enum memmodel model ) { rtx addr = XEXP ( mem , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) && ! legitimate_indexed_address_p ( addr , strict_p ) ) { addr = force_reg ( Pmode , addr ) ; mem = replace_equiv_address_nv ( mem , addr ) ; } switch ( model ) { case MEMMODEL_RELAXED : case MEMMODEL_CONSUME : case MEMMODEL_ACQUIRE : break ; case MEMMODEL_RELEASE : case MEMMODEL_ACQ_REL : emit_insn ( gen_lwsync ( ) ) ; break ; case MEMMODEL_SEQ_CST : emit_insn ( gen_hwsync ( ) ) ; break ; default : gcc_unreachable ( ) ; } return mem ; } </s>

Expand barriers before and after a load_locked/store_cond sequence .


<s> unsigned AArch64Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) && ! GV -> hasInternalLinkage ( ) ) return AArch64II :: MO_GOT ; auto * F = dyn_cast < Function > ( GV ) ; if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI , OS ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"Requesting 64-bit offset in 32-bit immediate!"


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; } </s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createX86MachObjectWriter ( OS , true , MachO :: CPU_TYPE_X86_64 , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool mips_tls_symbol_p ( rtx x ) { return GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return true if X is a thread-local symbol .


<s> static int mips_multipass_dfa_lookahead ( void ) { if ( TUNE_SB1 ) return 4 ; if ( TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A ) return 4 ; if ( TUNE_OCTEON ) return 2 ; if ( TUNE_P5600 ) return 4 ; return 0 ; } </s>


<s> InstructionCost ARMTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { switch ( ICA . getID ( ) ) { case Intrinsic :: get_active_lane_mask : if ( ST -> hasMVEIntegerOps ( ) ) return 0 ; break ; case Intrinsic :: sadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: uadd_sat : case Intrinsic :: usub_sat : { if ( ! ST -> hasMVEIntegerOps ( ) ) break ; Type * VT = ICA . getReturnType ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VT ) ; if ( LT . second == MVT :: v4i32 || LT . second == MVT :: v8i16 || LT . second == MVT :: v16i8 ) { unsigned Instrs = LT . second . getScalarSizeInBits ( ) == VT -> getScalarSizeInBits ( ) ? 1 : 4 ; return LT . first * ST -> getMVEVectorCostFactor ( CostKind ) * Instrs ; } break ; } case Intrinsic :: abs : case Intrinsic :: smin : case Intrinsic :: smax : case Intrinsic :: umin : case Intrinsic :: umax : { if ( ! ST -> hasMVEIntegerOps ( ) ) break ; Type * VT = ICA . getReturnType ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VT ) ; if ( LT . second == MVT :: v4i32 || LT . second == MVT :: v8i16 || LT . second == MVT :: v16i8 ) return LT . first * ST -> getMVEVectorCostFactor ( CostKind ) ; break ; } case Intrinsic :: minnum : case Intrinsic :: maxnum : { if ( ! ST -> hasMVEFloatOps ( ) ) break ; Type * VT = ICA . getReturnType ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VT ) ; if ( LT . second == MVT :: v4f32 || LT . second == MVT :: v8f16 ) return LT . first * ST -> getMVEVectorCostFactor ( CostKind ) ; break ; } } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


"Instr doesn't have FrameIndex operand!"


<s> bool Thumb1InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"empty class %qT parameter passing ABI "

"changes in %<-fabi-version=12%> (GCC 8)"


<s> inline unsigned int function_instance :: vectors_per_tuple ( ) const { return base -> vectors_per_tuple ( ) ; } </s>

If the function operates on tuples of vectors , return the number of vectors in the tuples , otherwise return 1 .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> bool X86RegisterInfo :: isArgumentRegister ( const MachineFunction & MF , MCRegister Reg ) const { const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterInfo & TRI = * ST . getRegisterInfo ( ) ; auto IsSubReg = [ & ] ( MCRegister RegA , MCRegister RegB ) { return TRI . isSuperOrSubRegisterEq ( RegA , RegB ) ; } ; if ( ! ST . is64Bit ( ) ) return llvm :: any_of ( SmallVector < MCRegister > { X86 :: EAX , X86 :: ECX , X86 :: EDX } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) || ( ST . hasMMX ( ) && X86 :: VR64RegClass . contains ( Reg ) ) ; CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; if ( CC == CallingConv :: X86_64_SysV && IsSubReg ( X86 :: RAX , Reg ) ) return true ; if ( llvm :: any_of ( SmallVector < MCRegister > { X86 :: RDX , X86 :: RCX , X86 :: R8 , X86 :: R9 } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; if ( CC != CallingConv :: Win64 && llvm :: any_of ( SmallVector < MCRegister > { X86 :: RDI , X86 :: RSI } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; if ( ST . hasSSE1 ( ) && llvm :: any_of ( SmallVector < MCRegister > { X86 :: XMM0 , X86 :: XMM1 , X86 :: XMM2 , X86 :: XMM3 , X86 :: XMM4 , X86 :: XMM5 , X86 :: XMM6 , X86 :: XMM7 } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; return X86GenRegisterInfo :: isArgumentRegister ( MF , Reg ) ; } </s>

isArgumentReg - Returns true if Reg can be used as an argument to a function .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> getFnAttributes ( ) . hasNoImplicitFloatAttr ( ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> getStackAlignment ( ) >= 32 ) { if ( Subtarget -> hasAVX2 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasAVX ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } if ( TT . getArch ( ) == Triple :: x86_64 ) addPass ( createFineIBTHashesSectionPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static void rs6000_init_dwarf_reg_sizes_extra ( tree address ) { if ( TARGET_MACHO && ! TARGET_ALTIVEC ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 16 , mode ) ; for ( i = FIRST_ALTIVEC_REGNO ; i < LAST_ALTIVEC_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } } </s>

Fill in sizes of registers used by unwinder .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI . getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getSpillSize ( * TRI . getMinimalPhysRegClass ( * R ) ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; assert ( ! MFI . getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI . getObjectSize ( I ) , MaxAlign ) ; if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI . getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return alignTo ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s> void output_profile_hook ( int labelno ATTRIBUTE_UNUSED ) { if ( TARGET_PROFILE_KERNEL ) return ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( NO_PROFILE_COUNTERS ) emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode ) ; else { char buf [ 30 ] ; const char * label_name ; rtx fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LR_REGNO ; crtl -> uses_pic_offset_table = 1 ; if ( MACHOPIC_INDIRECT && crtl -> uses_pic_offset_table ) caller_addr_regno = 0 ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , LCT_NORMAL , VOIDmode , gen_rtx_REG ( Pmode , caller_addr_regno ) , Pmode ) ; } } </s>


<s>
scalar_chain
::
scalar_chain
(
enum
machine_mode
smode_
,
enum
machine_mode
vmode_
)
{
smode
=
smode_
;
vmode
=
vmode_
;
chain_id
=
++
max_id
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Created a new instruction chain #%d\n"
,
chain_id
)
;
bitmap_obstack_initialize
(
)
;
insns
=
BITMAP_ALLOC
(
)
;
defs
=
BITMAP_ALLOC
(
)
;
defs_conv
=
BITMAP_ALLOC
(
)
;
insns_conv
=
BITMAP_ALLOC
(
)
;
queue
=
;
n_sse_to_integer
=
0
;
n_integer_to_sse
=
0
;
max_visits
=
x86_stv_max_visits
;
}
</s>


<s> int num_insns_constant_wide ( HOST_WIDE_INT value ) { if ( ( ( unsigned HOST_WIDE_INT ) value + 0x8000 ) < 0x10000 ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_wide ( low ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } else return 2 ; } </s>

Return the number of instructions it takes to form a constant in an integer register .


<s> static bool sparc_can_output_mi_thunk ( tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta ATTRIBUTE_UNUSED , HOST_WIDE_INT vcall_offset , tree function ATTRIBUTE_UNUSED ) { return ( vcall_offset >= - 32768 || ! fixed_regs [ 5 ] ) ; } </s>

Return true if sparc_output_mi_thunk would be able to output the assembler code for the thunk function specified by the arguments it is passed , and false otherwise .


<s> bool aarch64_simd_shift_imm_p ( rtx x , machine_mode mode , bool left ) { int bit_width = GET_MODE_UNIT_SIZE ( mode ) * BITS_PER_UNIT ; if ( left ) return aarch64_const_vec_all_same_in_range_p ( x , 0 , bit_width - 1 ) ; else return aarch64_const_vec_all_same_in_range_p ( x , 1 , bit_width ) ; } </s>

Check of immediate shift constants are within range .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s>
void
CSKYInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
SrcReg
,
bool
IsKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
CSKYMachineFunctionInfo
*
CFI
=
MF
.
getInfo
<
CSKYMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
ST32W
;
}
else
if
(
CSKY
::
CARRYRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
SPILL_CARRY
;
CFI
->
setSpillsCR
(
)
;
}
else
if
(
v2sf
&&
CSKY
::
sFPR32RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
FST_S
;
else
if
(
v2df
&&
CSKY
::
sFPR64RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
FST_D
;
else
if
(
v3sf
&&
CSKY
::
FPR32RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
f2FST_S
;
else
if
(
v3df
&&
CSKY
::
FPR64RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
f2FST_D
;
else
{
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
IsKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s> MCSymbol * AArch64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ 0 ] ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> bool AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA57 ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_rtx_VEC_DUPLICATE ( mode , x ) ; } </s>

If VALS is a vector constant that can be loaded into a register using DUP , generate instructions to do so and return an RTX to assign to the register . Otherwise return NULL_RTX .


<s> static bool is_branch_slot_insn ( rtx insn ) { if ( ! insn || ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ; return false ; } return false ; } </s>

The function returns true if INSN can be issued only from the branch slot .


"local variable memory requirements exceed capacity"

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling . Also any insns generated here should have RTX_FRAME_RELATED_P ( insn ) = 1 so that the debug info generation code can handle them properly .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) return true ; return ( RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


A subroutine that checks multiple load and store using consecutive registers . OP is a parallel rtx we would like to check . LOAD_P indicates whether we are checking load operation . PAR_INDEX is starting element of parallel rtx . FIRST_ELT_REGNO is used to tell starting register number . COUNT helps us to check consecutive register numbers .


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s> void rs6000_expand_vector_extract ( rtx target , rtx vec , rtx elt ) { machine_mode mode = GET_MODE ( vec ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx mem ; if ( VECTOR_MEM_VSX_P ( mode ) && CONST_INT_P ( elt ) ) { switch ( mode ) { default : break ; case V1TImode : gcc_assert ( INTVAL ( elt ) == 0 && inner_mode == TImode ) ; emit_move_insn ( target , gen_lowpart ( TImode , vec ) ) ; break ; case V2DFmode : emit_insn ( gen_vsx_extract_v2df ( target , vec , elt ) ) ; return ; case V2DImode : emit_insn ( gen_vsx_extract_v2di ( target , vec , elt ) ) ; return ; case V4SFmode : emit_insn ( gen_vsx_extract_v4sf ( target , vec , elt ) ) ; return ; case V16QImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v16qi ( target , vec , elt ) ) ; return ; } else break ; case V8HImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v8hi ( target , vec , elt ) ) ; return ; } else break ; case V4SImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v4si ( target , vec , elt ) ) ; return ; } break ; } } else if ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( elt ) && TARGET_DIRECT_MOVE_64BIT ) { if ( GET_MODE ( elt ) != DImode ) { rtx tmp = gen_reg_rtx ( DImode ) ; convert_move ( tmp , elt , 0 ) ; elt = tmp ; } else if ( ! REG_P ( elt ) ) elt = force_reg ( DImode , elt ) ; switch ( mode ) { case V2DFmode : emit_insn ( gen_vsx_extract_v2df_var ( target , vec , elt ) ) ; return ; case V2DImode : emit_insn ( gen_vsx_extract_v2di_var ( target , vec , elt ) ) ; return ; case V4SFmode : emit_insn ( gen_vsx_extract_v4sf_var ( target , vec , elt ) ) ; return ; case V4SImode : emit_insn ( gen_vsx_extract_v4si_var ( target , vec , elt ) ) ; return ; case V8HImode : emit_insn ( gen_vsx_extract_v8hi_var ( target , vec , elt ) ) ; return ; case V16QImode : emit_insn ( gen_vsx_extract_v16qi_var ( target , vec , elt ) ) ; return ; default : gcc_unreachable ( ) ; } } gcc_assert ( CONST_INT_P ( elt ) ) ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , vec ) ; mem = adjust_address_nv ( mem , inner_mode , INTVAL ( elt ) * GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , 0 ) ) ; } </s>

Extract field ELT from VEC into TARGET .


<s> int ix86_min_insn_size ( rtx_insn * insn ) { int l = 0 , len ; if ( ! INSN_P ( insn ) || ! active_insn_p ( insn ) ) return 0 ; if ( GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPECV_ALIGN ) return 0 ; if ( CALL_P ( insn ) && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) && ! SIBLING_CALL_P ( insn ) ) return 5 ; len = get_attr_length ( insn ) ; if ( len <= 1 ) return 1 ; if ( ! JUMP_P ( insn ) ) { enum attr_type type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MULTI : if ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= 0 ) return 0 ; break ; case TYPE_OTHER : case TYPE_FCMP : break ; default : return len ; } l = get_attr_length_address ( insn ) ; if ( l < 4 && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) ) l = 4 ; } if ( l ) return 1 + l ; else return 2 ; } </s>

We do n't have exact information about the insn sizes , but we may assume quite safely that we are informed about all 1 byte insns and memory address sizes . This is enough to eliminate unnecessary padding in 99 % of cases .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsUnalignedMemoryAccesses ( MVT :: v2f64 , 0 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsUnalignedMemoryAccesses ( MVT :: f64 , 0 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } if ( Size >= 4 ) return MVT :: i32 ; else if ( Size >= 2 ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> const char * F2003fTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( F2003fISD :: NodeType ) Opcode ) { case F2003fISD :: FIRST_NUMBER : break ; case F2003fISD :: Wrapper : return "F2003fISD::Wrapper" ; case F2003fISD :: FENXEO : return "F2003fISD::FENXEO" ; case F2003fISD :: DOSNUD : return "F2003fISD::DOSNUD" ; case F2003fISD :: SELECT_CC : return "F2003fISD::SELECT_CC" ; case F2003fISD :: BR_CC : return "F2003fISD::BR_CC" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned Mips16InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> const SystemZInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static bool use_rsqrt_p ( machine_mode mode ) { return ( ( mode == HFmode || ( TARGET_SSE && TARGET_SSE_MATH ) ) && flag_finite_math_only && ! flag_trapping_math && flag_unsafe_math_optimizations ) ; } </s>

Return true if it is safe to use the rsqrt optabs to optimize 1.0/sqrt .