<s> void nds32_asm_file_start_for_isr ( void ) { int i ; for ( i = 0 ; i < NDS32_N_ISR_VECTORS ; i ++ ) { nds32_isr_vectors [ i ] . category = NDS32_ISR_NONE ; strcpy ( nds32_isr_vectors [ i ] . func_name , "" ) ; nds32_isr_vectors [ i ] . save_reg = NDS32_PARTIAL_SAVE ; nds32_isr_vectors [ i ] . nested_type = NDS32_NOT_NESTED ; nds32_isr_vectors [ i ] . security_level = 0 ; nds32_isr_vectors [ i ] . total_n_vectors = 0 ; strcpy ( nds32_isr_vectors [ i ] . nmi_name , "" ) ; strcpy ( nds32_isr_vectors [ i ] . warm_name , "" ) ; } } </s>

A helper function to handle isr stuff at the beginning of asm file .


<s> bool mips_const_vector_shuffle_set_p ( rtx op , machine_mode mode ) { int nunits = GET_MODE_NUNITS ( mode ) ; int nsets = nunits / 4 ; int set = 0 ; int i , j ; for ( j = 0 ; j < nsets ; j ++ , set = 4 * j ) for ( i = 0 ; i < 4 ; i ++ ) if ( ( INTVAL ( XVECEXP ( op , 0 , i ) ) != ( INTVAL ( XVECEXP ( op , 0 , set + i ) ) - set ) ) || ! IN_RANGE ( INTVAL ( XVECEXP ( op , 0 , set + i ) ) , 0 , set + 3 ) ) return false ; return true ; } </s>

Return true if OP is a constant vector with repeated 4-element sets in mode MODE .


<s>
bool
ARMCodeGenPrepare
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
||
DisableCGP
)
return
false
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
return
false
;
const
TargetMachine
&
TM
=
TPC
->
getTM
<
TargetMachine
>
(
)
;
ST
=
&
TM
.
getSubtarget
<
ARMSubtarget
>
(
F
)
;
bool
MadeChange
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Running on "
<<
F
.
getName
(
)
<<
"\n"
)
;
for
(
BasicBlock
&
BB
:
F
)
{
auto
&
Insts
=
BB
.
getInstList
(
)
;
for
(
auto
&
I
:
Insts
)
{
if
(
AllVisited
.
count
(
&
I
)
)
continue
;
if
(
isa
<
ICmpInst
>
(
I
)
)
{
auto
&
CI
=
cast
<
ICmpInst
>
(
I
)
;
if
(
CI
.
isSigned
(
)
||
!
isa
<
IntegerType
>
(
CI
.
getOperand
(
0
)
->
getType
(
)
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Searching from: "
<<
CI
<<
"\n"
)
;
for
(
auto
&
Op
:
CI
.
operands
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
Op
)
)
{
if
(
isa
<
ZExtInst
>
(
I
)
)
MadeChange
|=
TryToPromote
(
I
->
getOperand
(
0
)
)
;
else
MadeChange
|=
TryToPromote
(
I
)
;
}
}
}
}
Promoter
->
Cleanup
(
)
;
LLVM_DEBUG
(
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
{
dbgs
(
)
;
report_fatal_error
(
"Broken function after type promotion"
)
;
}
)
;
}
if
(
MadeChange
)
LLVM_DEBUG
(
dbgs
(
)
<<
"After ARMCodeGenPrepare: "
<<
F
<<
"\n"
)
;
return
MadeChange
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

ARM
ARM
ARM
"ARM CGP: Running on "
"\n"
0
"ARM CGP: Searching from: "
"\n"
0
"Broken function after type promotion"
"After ARMCodeGenPrepare: "
"\n"


"Attempting to lower call as tail call\n"

"... Cannot handle tail calls with swifterror yet.\n"

"... Cannot handle non-void return types yet.\n"

"... Calling convention cannot be tail called.\n"

"... Tail calling varargs not supported yet.\n"

"... Cannot tail call from callers with byval or "

"... Cannot tail call externally-defined function "

"Unexpected variadic calling convention"

"... Cannot tail call with mismatched calling conventions yet.\n"

"... Cannot tail call callees with outgoing arguments yet.\n"

"... Call is eligible for tail call optimization.\n"

Returns true if the call can be lowered as a tail call .


<s> const TargetRegisterClass * MipsSETargetLowering :: getRepRegClassFor ( MVT VT ) const { if ( VT == MVT :: Untyped ) return Subtarget -> hasDSP ( ) ? & Mips :: ACC64DSPRegClass : & Mips :: ACC64RegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; bool hasAVX2 = Subtarget . hasAVX2 ( ) ; uint16_t validDomains = 0 ; if ( domain && lookup ( MI . getOpcode ( ) , domain ) ) validDomains = 0xe ; else if ( domain && lookupAVX2 ( MI . getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? 0xe : 0x6 ; else if ( domain && lookupAVX512 ( MI . getOpcode ( ) , domain ) ) validDomains = 0xe ; return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> bool MipsInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { switch ( MI . getOpcode ( ) ) { case Mips :: EXT : case Mips :: EXT_MM : case Mips :: INS : case Mips :: INS_MM : case Mips :: DINS : case Mips :: DINS_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 0 , 32 , 0 , 32 ) ; case Mips :: DINSM : case Mips :: DINSM_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 1 , 64 , 32 , 64 ) ; case Mips :: DINSU : case Mips :: DINSU_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 32 , 64 , 1 , 32 , 32 , 64 ) ; case Mips :: DEXT : case Mips :: DEXT_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 0 , 32 , 0 , 63 ) ; case Mips :: DEXTM : case Mips :: DEXTM_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 32 , 64 , 32 , 64 ) ; case Mips :: DEXTU : case Mips :: DEXTU_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 32 , 64 , 0 , 32 , 32 , 64 ) ; default : return true ; } return true ; } </s>

Perform target-specific instruction verification .


<s> bool ix86_pre_reload_split ( void ) { return ( can_create_pseudo_p ( ) && ! ( cfun -> curr_properties & PROP_rtl_split_insns ) ) ; } </s>

Predicate for pre-reload splitters with associated instructions , which can match any time before the split1 pass ( usually combine ) , then are unconditionally split in that pass and should not be matched again afterwards .


<s>
unsigned
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
unsigned
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
unsigned
char
X86Subtarget
::
classifyLocalReference
(
const
GlobalValue
*
GV
)
const
{
if
(
!
isPositionIndependent
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
is64Bit
(
)
)
{
if
(
isTargetELF
(
)
)
{
switch
(
TM
.
getCodeModel
(
)
)
{
case
CodeModel
::
Small
:
case
CodeModel
::
Kernel
:
return
X86II
::
MO_NO_FLAG
;
case
CodeModel
::
Large
:
return
X86II
::
MO_GOTOFF
;
case
CodeModel
::
Medium
:
if
(
isa
<
Function
>
(
GV
)
)
return
X86II
::
MO_NO_FLAG
;
return
X86II
::
MO_GOTOFF
;
}
llvm_unreachable
(
"invalid code model"
)
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isTargetCOFF
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
&&
(
GV
->
isDeclarationForLinker
(
)
||
GV
->
hasCommonLinkage
(
)
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
return
X86II
::
MO_GOTOFF
;
}
</s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool isConstantSplat ( SDValue Op , APInt & SplatVal ) { APInt UndefElts ; SmallVector < APInt , 16 > EltBits ; if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , false ) ) { int SplatIndex = - 1 ; for ( int i = 0 , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) continue ; if ( 0 <= SplatIndex && EltBits [ i ] != EltBits [ SplatIndex ] ) { SplatIndex = - 1 ; break ; } SplatIndex = i ; } if ( 0 <= SplatIndex ) { SplatVal = EltBits [ SplatIndex ] ; return true ; } } return false ; } </s>

Check if this is a constant splat , and if so , find the smallest element size that splats the vector .


<s> bool VERegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return false ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> int AArch64TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; APInt ImmVal = Imm ; if ( BitSize & 0x3f ) ImmVal = Imm . sext ( ( BitSize + 63 ) & ~ 0x3fU ) ; int Cost = 0 ; for ( unsigned ShiftVal = 0 ; ShiftVal < BitSize ; ShiftVal += 64 ) { APInt Tmp = ImmVal . ashr ( ShiftVal ) . sextOrTrunc ( 64 ) ; int64_t Val = Tmp . getSExtValue ( ) ; Cost += getIntImmCost ( Val ) ; } return std :: max ( 1 , Cost ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static rtx ix86_expand_unop_builtin ( enum insn_code icode , tree arglist , rtx target , int do_load ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of unop insns .


<s> int mips_const_insns ( rtx x ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; enum mips_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case HIGH : if ( ! mips_symbolic_constant_p ( XEXP ( x , 0 ) , SYMBOL_CONTEXT_LEA , & symbol_type ) || ! mips_split_p [ symbol_type ] ) return 0 ; return TARGET_MIPS16 ? 4 : 1 ; case CONST_INT : if ( TARGET_MIPS16 ) return ( IN_RANGE ( INTVAL ( x ) , 0 , 255 ) ? 1 : SMALL_OPERAND_UNSIGNED ( INTVAL ( x ) ) ? 2 : IN_RANGE ( - INTVAL ( x ) , 0 , 255 ) ? 2 : SMALL_OPERAND_UNSIGNED ( - INTVAL ( x ) ) ? 3 : 0 ) ; return mips_build_integer ( codes , INTVAL ( x ) ) ; case CONST_DOUBLE : case CONST_VECTOR : return ! TARGET_MIPS16 && x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( CONST_GP_P ( x ) ) return 1 ; if ( mips_symbolic_constant_p ( x , SYMBOL_CONTEXT_LEA , & symbol_type ) ) return mips_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = mips_const_insns ( x ) ; if ( n != 0 ) { if ( SMALL_INT ( offset ) ) return n + 1 ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + 1 + mips_build_integer ( codes , INTVAL ( offset ) ) ; } } return 0 ; case SYMBOL_REF : case LABEL_REF : return mips_symbol_insns ( mips_classify_symbol ( x , SYMBOL_CONTEXT_LEA ) , MAX_MACHINE_MODE ) ; default : return 0 ; } } </s>


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s>
bool
ARMTargetLowering
::
allowTruncateForTailCall
(
Type
*
Ty1
,
Type
*
Ty2
)
const
{
if
(
!
Ty1
->
isIntegerTy
(
)
||
!
Ty2
->
isIntegerTy
(
)
)
return
false
;
if
(
!
isTypeLegal
(
EVT
::
getEVT
(
Ty1
)
)
)
return
false
;
assert
(
Ty1
->
getPrimitiveSizeInBits
(
)
<=
64
&&
"i128 is probably not a noop"
)
;
return
true
;
}
</s>

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position .

ARM
ARM
64
"i128 is probably not a noop"


<s> static bool mips_has_long_branch_p ( void ) { rtx_insn * insn , * subinsn ; int normal_length ; shorten_branches ( get_insns ( ) ) ; normal_length = ( TARGET_MIPS16 ? 4 : 8 ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( JUMP_P ( subinsn ) && get_attr_length ( subinsn ) > normal_length && ( any_condjump_p ( subinsn ) || any_uncondjump_p ( subinsn ) ) ) return true ; return false ; } </s>

Return true if the function has a long branch instruction .


<s> rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( REG_P ( XEXP ( addr , 0 ) ) && REGNO ( XEXP ( addr , 0 ) ) != 0 ) addr = XEXP ( addr , 0 ) ; else if ( REG_P ( XEXP ( addr , 1 ) ) && REGNO ( XEXP ( addr , 1 ) ) != 0 ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 0 ) ) ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; else gcc_unreachable ( ) ; } gcc_assert ( REG_P ( addr ) && REGNO ( addr ) != 0 ) ; return addr ; } </s>

Return a REG that occurs in ADDR with coefficient 1 . ADDR can be effectively incremented by incrementing REG . r0 is special and we must not select it as an address register by this routine since our caller will try to increment the returned register via an `` la '' instruction .


<s> int uns_arith_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) == CONST_INT && SMALL_INT_UNSIGNED ( op ) ) return 1 ; return register_operand ( op , mode ) ; } </s>

Return truth value of whether OP can be used as an operands where a register or 16 bit unsigned integer is needed .


"type %qT with %<[[no_unique_address]]%> members "

"type %qT when C++17 is enabled changed to match "

"argument of type %qT not permitted with %<-mgeneral-regs-only%>"

Return true if an argument whose type is TYPE , or mode is MODE , is suitable for passing or returning in VFP registers for the PCS variant selected . If it is , then * BASE_MODE is updated to contain a machine mode describing each element of the argument 's type and * COUNT to hold the number of such elements .


<s> const uint32_t * AArch64CA53ErratumStub :: getData ( ) const { return m_pData ; } </s>

Get the data pointed to by this extractor .


<s> tree aarch64_builtin_rsqrt ( unsigned int fn ) { if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2df ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2DF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2SF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V4SF ] ; return NULL_TREE ; } </s>

Return builtin for reciprocal square root .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static rtx gen_push ( rtx arg ) { return gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( Pmode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , arg ) ; } </s>

Code to generate prologue and epilogue sequences


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"switch -mcpu=%s conflicts with -march=%s switch"

Parse the TO_PARSE string and put the architecture struct that it selects into RES and the architectural features into ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> bool X86TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasFnAttr ( Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> static void arm_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr , mem , a_tramp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; if ( TARGET_FDPIC ) { rtx funcdesc = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx fnaddr = gen_rtx_MEM ( Pmode , funcdesc ) ; rtx gotaddr = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , funcdesc , 4 ) ) ; rtx trampoline_code_start = plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , TARGET_THUMB2 ? 9 : 8 ) ; mem = adjust_address ( m_tramp , SImode , 0 ) ; emit_move_insn ( mem , trampoline_code_start ) ; mem = adjust_address ( m_tramp , SImode , 4 ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , PIC_OFFSET_TABLE_REGNUM ) ) ; mem = adjust_address ( m_tramp , SImode , 20 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 24 ) ; emit_move_insn ( mem , gotaddr ) ; mem = adjust_address ( m_tramp , SImode , 28 ) ; emit_move_insn ( mem , fnaddr ) ; } else { mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 8 : 12 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 12 : 16 ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_move_insn ( mem , fnaddr ) ; } a_tramp = XEXP ( m_tramp , 0 ) ; maybe_emit_call_builtin___clear_cache ( a_tramp , plus_constant ( ptr_mode , a_tramp , TRAMPOLINE_SIZE ) ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>


<s>
static
void
segv_crash_handler
(
int
sig
ATTRIBUTE_UNUSED
)
{
internal_error
(
"Segmentation Fault (code)"
)
;
}
</s>

On Darwin/powerpc , hitting the stack limit turns into a SIGSEGV . This code detects the difference between hitting the stack limit and a true wild pointer dereference by looking at the instruction that faulted ; only a few kinds of instruction are used to access below the previous bottom of the stack .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"extended registers have no high halves"

"unsupported operand size for extended register"


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: X86_FastCall ) ; F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } return ; } StringRef GuardMode = M . getStackProtectorGuard ( ) ; if ( ( GuardMode == "tls" || GuardMode . empty ( ) ) && hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> void LC2200PassConfig :: addPreEmitPass ( ) { } </s>


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

Mips
0
"RelaxInstruction() unimplemented"


<s>
SDNode
*
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
std
::
pair
<
bool
,
SDNode
*
>
Ret
=
selectNode
(
Node
)
;
if
(
Ret
.
first
)
return
Ret
.
second
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"Selecting: "
"\n"
"== "
"\n"
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."
"=> "
"\n"


<s> const char * output_387_reg_move ( rtx insn , rtx * operands ) { if ( REG_P ( operands [ 1 ] ) && find_regno_note ( insn , REG_DEAD , REGNO ( operands [ 1 ] ) ) ) { if ( REGNO ( operands [ 0 ] ) == FIRST_STACK_REG && TARGET_USE_FFREEP ) return "ffreep\t%y0" ; return "fstp\t%y0" ; } if ( STACK_TOP_P ( operands [ 0 ] ) ) return "fld%z1\t%y1" ; return "fst\t%y0" ; } </s>

Output code to perform an x87 FP register move , from OPERANDS [ 1 ] to OPERANDS [ 0 ] .


<s> static rtx sparc_tls_got ( void ) { rtx temp ; if ( flag_pic ) { current_function_uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } if ( ! global_offset_table ) global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; temp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( temp , global_offset_table ) ; return temp ; } </s>

Return the Global Offset Table to be used in TLS mode .


<s> const Cpu0FrameLowering * Cpu0FrameLowering :: create ( const Cpu0Subtarget & ST ) { return llvm :: createCpu0SEFrameLowering ( ST ) ; } </s>


<s> bool isToken ( ) const override { return Kind == TOKEN ; } </s>


<s> void addLOHDirective ( MCLOHType Kind , const MILOHArgs & Args ) { LOHContainerSet . push_back ( MILOHDirective ( Kind , Args ) ) ; LOHRelated . insert ( Args . begin ( ) , Args . end ( ) ) ; } </s>

Add a LOH directive of this Kind and this Args .


<s> static unsigned long arm_compute_save_reg0_reg12_mask ( void ) { unsigned long func_type = arm_current_func_type ( ) ; unsigned long save_reg_mask = 0 ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = 7 ; else max_reg = 12 ; for ( reg = 0 ; reg <= max_reg ; reg ++ ) if ( regs_ever_live [ reg ] || ( ! current_function_is_leaf && call_used_regs [ reg ] ) ) save_reg_mask |= ( 1 << reg ) ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && current_function_uses_pic_offset_table ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } else { for ( reg = 0 ; reg <= 10 ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; if ( ! TARGET_APCS_FRAME && ! frame_pointer_needed && regs_ever_live [ HARD_FRAME_POINTER_REGNUM ] && ! call_used_regs [ HARD_FRAME_POINTER_REGNUM ] ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && ( regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] || current_function_uses_pic_offset_table ) ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } if ( current_function_calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; i ++ ) { reg = EH_RETURN_DATA_REGNO ( i ) ; if ( reg == INVALID_REGNUM ) break ; save_reg_mask |= 1 << reg ; } } return save_reg_mask ; } </s>

Compute the register save mask for registers 0 through 12 inclusive . This code is used by arm_compute_save_reg_mask .


"function versions cannot be marked as gnu_inline,"

"virtual function multiversioning not supported"

This function changes the assembler name for functions that are versions . If DECL is a function version and has a `` target '' attribute , it appends the attribute string to its assembler name .


<s> static rtx mips_dwarf_register_span ( rtx reg ) { rtx high , low ; machine_mode mode ; mode = GET_MODE ( reg ) ; if ( FP_REG_P ( REGNO ( reg ) ) && TARGET_FLOATXX && GET_MODE_SIZE ( mode ) > UNITS_PER_FPREG ) { return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , reg ) ) ; } else if ( FP_REG_P ( REGNO ( reg ) ) && TARGET_BIG_ENDIAN && MAX_FPRS_PER_FMT > 1 && GET_MODE_SIZE ( mode ) > UNITS_PER_FPREG ) { gcc_assert ( GET_MODE_SIZE ( mode ) == UNITS_PER_HWFPVALUE ) ; high = mips_subword ( reg , true ) ; low = mips_subword ( reg , false ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , high , low ) ) ; } return NULL_RTX ; } </s>


<s> bool PPCCTRLoops :: isDead ( const MachineInstr * MI , SmallVector < MachineInstr * , 1 > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( ! MRI -> use_nodbg_empty ( Reg ) ) { MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) ; if ( llvm :: next ( I ) == MRI -> use_end ( ) && I . getOperand ( ) . getParent ( ) -> isPHI ( ) ) { MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( OPO . isReg ( ) && OPO . isDef ( ) ) { unsigned OPReg = OPO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextJ ; for ( MachineRegisterInfo :: use_iterator J = MRI -> use_begin ( OPReg ) , E = MRI -> use_end ( ) ; J != E ; J = nextJ ) { nextJ = llvm :: next ( J ) ; MachineOperand & Use = J . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) { return false ; } } } } DeadPhis . push_back ( OnePhi ) ; } else { return false ; } } } } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s> static int sparc_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { bool need_memory = false ; if ( from == FPCC_REGS || to == FPCC_REGS ) need_memory = true ; else if ( ( FP_REG_CLASS_P ( from ) && general_or_i64_p ( to ) ) || ( general_or_i64_p ( from ) && FP_REG_CLASS_P ( to ) ) ) { if ( TARGET_VIS3 ) { int size = GET_MODE_SIZE ( mode ) ; if ( size == 8 || size == 4 ) { if ( ! TARGET_ARCH32 || size == 4 ) return 4 ; else return 6 ; } } need_memory = true ; } if ( need_memory ) { if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 ) return 12 ; return 6 ; } return 2 ; } </s>


<s> PLTEntryBase * MipsPLT :: create ( ) { return new MipsPLTA ( * m_pSectionData ) ; } </s>


<s> static rsqrts_type get_rsqrts_type ( machine_mode mode ) { switch ( mode ) { case E_DFmode : return gen_aarch64_rsqrtsdf ; case E_SFmode : return gen_aarch64_rsqrtssf ; case E_V2DFmode : return gen_aarch64_rsqrtsv2df ; case E_V2SFmode : return gen_aarch64_rsqrtsv2sf ; case E_V4SFmode : return gen_aarch64_rsqrtsv4sf ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root series step insn depending on machine mode .


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) || vzeroall_pattern ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn ) ) { bool avx_upper_reg_found = false ; note_stores ( pat , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; } return mode ; } </s>

Calculate mode of upper 128bit AVX registers after the insn .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static unsigned long arm_compute_save_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; unsigned int reg ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % 2 ) != 0 ) { for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == 0 ) { reg = thumb_find_work_register ( 1 << 4 ) ; if ( ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; } return save_reg_mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function . This is used by arm_get_frame_offsets , which may add extra registers .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> void UnwindOpcodeAssembler :: EmitSetSP ( uint16_t Reg ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_SET_VSP | Reg ) ; } </s>

Emit unwind opcodes to copy address from source register to $ sp .


<s> uint64_t PPCFrameLowering :: getBasePointerSaveOffset ( ) const { return BasePointerSaveOffset ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> const char * umips_output_save_restore ( bool save_p , rtx pattern ) { static char buffer [ 300 ] ; char * s ; int n ; HOST_WIDE_INT offset ; rtx base , mem , set , last_set , last_reg ; gcc_assert ( umips_save_restore_pattern_p ( save_p , pattern ) ) ; s = strcpy ( buffer , save_p ? "swm\t" : "lwm\t" ) ; s += strlen ( s ) ; n = XVECLEN ( pattern , 0 ) ; set = XVECEXP ( pattern , 0 , 0 ) ; mem = save_p ? SET_DEST ( set ) : SET_SRC ( set ) ; mips_split_plus ( XEXP ( mem , 0 ) , & base , & offset ) ; last_set = XVECEXP ( pattern , 0 , n - 1 ) ; last_reg = save_p ? SET_SRC ( last_set ) : SET_DEST ( last_set ) ; if ( REGNO ( last_reg ) == 31 ) n -- ; gcc_assert ( n <= 9 ) ; if ( n == 0 ) ; else if ( n == 1 ) s += sprintf ( s , "%s," , reg_names [ 16 ] ) ; else if ( n < 9 ) s += sprintf ( s , "%s-%s," , reg_names [ 16 ] , reg_names [ 15 + n ] ) ; else if ( n == 9 ) s += sprintf ( s , "%s-%s,%s," , reg_names [ 16 ] , reg_names [ 23 ] , reg_names [ 30 ] ) ; if ( REGNO ( last_reg ) == 31 ) s += sprintf ( s , "%s," , reg_names [ 31 ] ) ; s += sprintf ( s , "%d(%s)" , ( int ) offset , reg_names [ REGNO ( base ) ] ) ; return buffer ; } </s>

Return the assembly instruction for microMIPS LWM or SWM . SAVE_P and PATTERN are as for umips_save_restore_pattern_p .


<s>
void
mips_output_filename
(
FILE
*
stream
,
const
char
*
name
)
{
if
(
write_symbols
==
DWARF2_DEBUG
)
return
;
else
if
(
mips_output_filename_first_time
)
{
mips_output_filename_first_time
=
0
;
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
else
if
(
write_symbols
==
DBX_DEBUG
)
return
;
else
if
(
name
!=
current_function_file
&&
strcmp
(
name
,
current_function_file
)
!=
0
)
{
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
}
</s>

Emit a new filename to a stream . If we are smuggling stabs , try to put out a MIPS ECOFF file and a stab .


<s> static bool rs6000_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p ) { extern int in_toc_section ( void ) ; static int recurse = 0 ; if ( TARGET_RELOCATABLE && ! in_toc_section ( ) && ! in_text_section ( ) && ! in_unlikely_text_section ( ) && ! recurse && GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_DOUBLE && CONSTANT_P ( x ) ) { char buf [ 256 ] ; recurse = 1 ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , fixuplabelno ) ; fixuplabelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\t.long\t(" ) ; output_addr_const ( asm_out_file , x ) ; fprintf ( asm_out_file , ")@fixup\n" ) ; fprintf ( asm_out_file , "\t.section\t\".fixup\",\"aw\"\n" ) ; ASM_OUTPUT_ALIGN ( asm_out_file , 2 ) ; fprintf ( asm_out_file , "\t.long\t" ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\n\t.previous\n" ) ; recurse = 0 ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , 0 ) [ 0 ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , 0 ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , "\t.long\t%s\n" , name ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The powerpc version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined . It also needs to handle DI-mode objects on 64-bit targets .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isSVR4ABI ( ) ) { if ( Subtarget . isPPC64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool isOffsetOfLocal ( ) const override { return isImm ( ) && Imm . LocalRef ; } </s>

isOffsetOfLocal - Do we need to emit code to get the offset of the local variable , rather than its value ? Only valid when parsing MS-style inline assembly .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , LittleEndian ) , InstrInfo ( Subtarget ) , DL ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { initAsmInfo ( ) ; } </s>


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI . getOpcode ( ) , Subtarget ) ) return 0 ; const MachineOperand & MO = MI . getOperand ( 0 ) ; Register Reg = MO . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return 0 ; } return PartialRegUpdateClearance ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> static void add_insn_window ( rtx_insn * insn , dispatch_windows * window_list , int num_uops ) { int byte_len = ix86_min_insn_size ( insn ) ; int num_insn = window_list -> num_insn ; int imm_size ; sched_insn_info * window = window_list -> window ; enum dispatch_group group = get_insn_group ( insn ) ; enum insn_path path = get_insn_path ( insn ) ; int num_imm_operand ; int num_imm32_operand ; int num_imm64_operand ; if ( ! window_list -> violation && group != disp_cmp && ! fits_dispatch_window ( insn ) ) window_list -> violation = true ; imm_size = get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; window [ num_insn ] . insn = insn ; window [ num_insn ] . byte_len = byte_len ; window [ num_insn ] . group = group ; window [ num_insn ] . path = path ; window [ num_insn ] . imm_bytes = imm_size ; window_list -> window_size += byte_len ; window_list -> num_insn = num_insn + 1 ; window_list -> num_uops = window_list -> num_uops + num_uops ; window_list -> imm_size += imm_size ; window_list -> num_imm += num_imm_operand ; window_list -> num_imm_32 += num_imm32_operand ; window_list -> num_imm_64 += num_imm64_operand ; if ( group == disp_store ) window_list -> num_stores += 1 ; else if ( group == disp_load || group == disp_prefetch ) window_list -> num_loads += 1 ; else if ( group == disp_load_store ) { window_list -> num_stores += 1 ; window_list -> num_loads += 1 ; } } </s>

Add an instruction INSN with NUM_UOPS micro-operations to the dispatch window WINDOW_LIST .


<s>
void
ARMHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
ITBlockSize
)
{
ITBlockSize
;
}
else
if
(
Opcode
==
ARM
::
t2IT
)
{
unsigned
Mask
=
MI
->
getOperand
(
1
)
.
getImm
(
)
;
unsigned
NumTZ
=
CountTrailingZeros_32
(
Mask
)
;
assert
(
NumTZ
<=
3
&&
"Invalid IT mask!"
)
;
ITBlockSize
=
4
NumTZ
;
MachineBasicBlock
::
iterator
I
=
MI
;
for
(
unsigned
i
=
0
;
i
<
ITBlockSize
;
++
i
)
{
do
{
++
I
;
}
while
(
I
->
isDebugValue
(
)
)
;
ITBlockMIs
[
ITBlockSize
1
i
]
=
&
*
I
;
}
}
if
(
!
MI
->
isDebugValue
(
)
)
{
LastMI
=
MI
;
Stalls
=
0
;
}
ScoreboardHazardRecognizer
::
EmitInstruction
(
SU
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static rtx stv_expand_builtin ( insn_code icode , rtx * op , machine_mode tmode , machine_mode smode ) { op [ 2 ] = copy_to_mode_reg ( Pmode , op [ 2 ] ) ; if ( icode == CODE_FOR_altivec_stvx_v2df || icode == CODE_FOR_altivec_stvx_v2di || icode == CODE_FOR_altivec_stvx_v4sf || icode == CODE_FOR_altivec_stvx_v4si || icode == CODE_FOR_altivec_stvx_v8hi || icode == CODE_FOR_altivec_stvx_v16qi ) { rtx rawaddr ; if ( op [ 1 ] == const0_rtx ) rawaddr = op [ 2 ] ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; rawaddr = gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ; } rtx addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - 16 ) ) ; addr = gen_rtx_MEM ( tmode , addr ) ; op [ 0 ] = copy_to_mode_reg ( tmode , op [ 0 ] ) ; emit_insn ( gen_rtx_SET ( addr , op [ 0 ] ) ) ; } else if ( icode == CODE_FOR_vsx_stxvrbx || icode == CODE_FOR_vsx_stxvrhx || icode == CODE_FOR_vsx_stxvrwx || icode == CODE_FOR_vsx_stxvrdx ) { rtx truncrtx = gen_rtx_TRUNCATE ( tmode , op [ 0 ] ) ; op [ 0 ] = copy_to_mode_reg ( E_TImode , truncrtx ) ; rtx addr ; if ( op [ 1 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 2 ] ) ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ 0 ] ) ; if ( pat ) emit_insn ( pat ) ; } else { if ( ! insn_data [ icode ] . operand [ 1 ] . predicate ( op [ 0 ] , smode ) ) op [ 0 ] = copy_to_mode_reg ( smode , op [ 0 ] ) ; rtx addr ; if ( op [ 1 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 2 ] ) ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ 0 ] ) ; if ( pat ) emit_insn ( pat ) ; } return NULL_RTX ; } </s>

Expand an AltiVec vector store builtin , and return the expanded rtx .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static bool mips_mode_ok_for_mov_fmt_p ( machine_mode mode ) { switch ( mode ) { case CCFmode : case SFmode : return TARGET_HARD_FLOAT ; case DFmode : return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ; case V2SFmode : return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT ; default : return MSA_SUPPORTED_MODE_P ( mode ) ; } } </s>

Return true if moves in mode MODE can use the FPU 's mov.fmt instruction .


<s>
bool
SystemZInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
SystemZII
::
Branch
Branch
(
getBranchInfo
(
*
I
)
)
;
if
(
!
Branch
.
Target
->
isMBB
(
)
)
return
true
;
if
(
Branch
.
Type
!=
SystemZII
::
BranchNormal
)
return
true
;
if
(
Branch
.
CCMask
==
SystemZ
::
CCMASK_ANY
)
{
if
(
!
AllowModify
)
{
TBB
=
Branch
.
Target
->
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
Branch
.
Target
->
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
Branch
.
Target
->
getMBB
(
)
;
continue
;
}
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
Branch
.
Target
->
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCValid
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCMask
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
2
&&
TBB
&&
"Should have seen a conditional branch"
)
;
if
(
TBB
!=
Branch
.
Target
->
getMBB
(
)
)
return
true
;
unsigned
OldCCValid
=
Cond
[
0
]
.
getImm
(
)
;
unsigned
OldCCMask
=
Cond
[
1
]
.
getImm
(
)
;
if
(
OldCCValid
==
Branch
.
CCValid
&&
OldCCMask
==
Branch
.
CCMask
)
continue
;
return
false
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = TREE_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; enum machine_mode mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && host_integerp ( bit_position ( f ) , 1 ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode , ftype ) ) { switch ( mode ) { case SCmode : mode = SFmode ; break ; case DCmode : mode = DFmode ; break ; case TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( mode == TFmode ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , ftype , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


<s>
bool
CSKYMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_RegisterMask
:
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MCSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
MO
.
getMCSymbol
(
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> void aarch64_general_init_builtins ( void ) { aarch64_init_fpsr_fpcr_builtins ( ) ; aarch64_init_fp16_types ( ) ; aarch64_init_bf16_types ( ) ; { aarch64_simd_switcher simd ; aarch64_init_simd_builtins ( ) ; } aarch64_init_crc32_builtins ( ) ; aarch64_init_builtin_rsqrt ( ) ; aarch64_init_rng_builtins ( ) ; tree ftype_jcvt = build_function_type_list ( intSI_type_node , double_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_JSCVT ] = aarch64_general_add_builtin ( "__builtin_aarch64_jcvtzs" , ftype_jcvt , AARCH64_JSCVT ) ; if ( ! TARGET_ILP32 ) aarch64_init_pauth_hint_builtins ( ) ; if ( TARGET_TME ) aarch64_init_tme_builtins ( ) ; if ( TARGET_MEMTAG ) aarch64_init_memtag_builtins ( ) ; } </s>

Initialize all builtins in the AARCH64_BUILTIN_GENERAL group .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool MandarinAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
static
void
process_cfa_register
(
FILE
*
out_file
,
rtx
pat
,
bool
unwind
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
int
dest_regno
=
REGNO
(
dest
)
;
int
src_regno
;
if
(
src
==
pc_rtx
)
{
if
(
unwind
)
fprintf
(
out_file
,
"\t.save rp, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
return
;
}
src_regno
=
REGNO
(
src
)
;
switch
(
src_regno
)
{
case
PR_REG
(
0
)
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_pr
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save pr, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
break
;
case
AR_UNAT_REGNUM
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_unat
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.unat, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
break
;
case
AR_LC_REGNUM
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_lc
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.lc, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

This function processes a SET pattern for REG_CFA_REGISTER .

ia64
"\t.save rp, r%d\n"
0
"\t.save pr, r%d\n"
"\t.save ar.unat, r%d\n"
"\t.save ar.lc, r%d\n"


<s>
rtx
iq2000_legitimize_address
(
rtx
xinsn
,
rtx
old_x
ATTRIBUTE_UNUSED
,
machine_mode
mode
)
{
if
(
TARGET_DEBUG_B_MODE
)
{
GO_PRINTF
(
"\n========== LEGITIMIZE_ADDRESS\n"
)
;
GO_DEBUG_RTX
(
xinsn
)
;
}
if
(
iq2000_check_split
(
xinsn
,
mode
)
)
{
return
gen_rtx_LO_SUM
(
Pmode
,
copy_to_mode_reg
(
Pmode
,
gen_rtx_HIGH
(
Pmode
,
xinsn
)
)
,
xinsn
)
;
}
if
(
GET_CODE
(
xinsn
)
==
PLUS
)
{
rtx
xplus0
=
XEXP
(
xinsn
,
0
)
;
rtx
xplus1
=
XEXP
(
xinsn
,
1
)
;
enum
rtx_code
code0
=
GET_CODE
(
xplus0
)
;
enum
rtx_code
code1
=
GET_CODE
(
xplus1
)
;
if
(
code0
!=
REG
&&
code1
==
REG
)
{
xplus0
=
XEXP
(
xinsn
,
1
)
;
xplus1
=
XEXP
(
xinsn
,
0
)
;
code0
=
GET_CODE
(
xplus0
)
;
code1
=
GET_CODE
(
xplus1
)
;
}
if
(
code0
==
REG
&&
REG_MODE_OK_FOR_BASE_P
(
xplus0
,
mode
)
&&
code1
==
CONST_INT
&&
!
SMALL_INT
(
xplus1
)
)
{
rtx
int_reg
=
gen_reg_rtx
(
Pmode
)
;
rtx
ptr_reg
=
gen_reg_rtx
(
Pmode
)
;
emit_move_insn
(
int_reg
,
GEN_INT
(
INTVAL
(
xplus1
)
&
~
0x7fff
)
)
;
emit_insn
(
gen_rtx_SET
(
VOIDmode
,
ptr_reg
,
gen_rtx_PLUS
(
Pmode
,
xplus0
,
int_reg
)
)
)
;
return
plus_constant
(
Pmode
,
ptr_reg
,
INTVAL
(
xplus1
)
&
0x7fff
)
;
}
}
if
(
TARGET_DEBUG_B_MODE
)
GO_PRINTF
(
"LEGITIMIZE_ADDRESS could not fix.\n"
)
;
return
xinsn
;
}
</s>

For the IQ2000 , transform : memory ( X + < large int > ) into : Y = < large int > & ~0x7fff ; Z = X + Y memory ( Z + ( < large int > & 0x7fff ) ) ;


<s> bool PPCLowerMASSVEntries :: runOnModule ( Module & M ) { bool Changed = false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return Changed ; auto & TM = TPC -> getTM < PPCTargetMachine > ( ) ; const PPCSubtarget * Subtarget ; for ( Function & Func : M ) { if ( ! Func . isDeclaration ( ) ) continue ; if ( ! isMASSVFunc ( Func . getName ( ) ) ) continue ; SmallVector < User * , 4 > MASSVUsers ; for ( auto * User : Func . users ( ) ) MASSVUsers . push_back ( User ) ; for ( auto * User : MASSVUsers ) { auto * CI = dyn_cast < CallInst > ( User ) ; if ( ! CI ) continue ; Subtarget = & TM . getSubtarget < PPCSubtarget > ( * CI -> getParent ( ) -> getParent ( ) ) ; Changed |= lowerMASSVCall ( CI , Func , M , Subtarget ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool aarch64_bti_enabled ( void ) { return ( aarch64_enable_bti == 1 ) ; } </s>

Return TRUE if Branch Target Identification Mechanism is enabled .


"Couldn't assign to global base register!"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( VT == MVT :: v64i1 && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && CC != CallingConv :: X86_RegCall ) return 2 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> bool Thumb1FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int shmedia_cleanup_truncate ( rtx * p , void * n_changes ) { rtx x = * p , reg ; if ( GET_CODE ( x ) != TRUNCATE ) return 0 ; reg = XEXP ( x , 0 ) ; if ( GET_MODE_SIZE ( GET_MODE ( reg ) ) > 8 && GET_CODE ( reg ) == REG ) { enum machine_mode reg_mode = GET_MODE ( reg ) ; XEXP ( x , 0 ) = simplify_subreg ( DImode , reg , reg_mode , subreg_lowpart_offset ( DImode , reg_mode ) ) ; * ( int * ) n_changes += 1 ; return - 1 ; } return 0 ; } </s>

Look through X cleaning up truncates of registers that span multiple actual hard registers . Return the number of changes made .


<s> bool enablePostRAScheduler ( ) const override { return isGeneric ( ) || isCortexA53 ( ) || isCortexA57 ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MipsABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Opc = ABI . GetPtrAdduOp ( ) ; if ( Amount < 0 ) { Opc = ABI . GetPtrSubuOp ( ) ; Amount = - Amount ; } unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( Opc ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s>
const
char
*
output_adjust_stack_and_probe
(
rtx
reg
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"sub%z0\t{%1, %0|%0, %1}"
,
xops
)
;
xops
[
1
]
=
const0_rtx
;
output_asm_insn
(
"or%z0\t{%1, (%0)|DWORD PTR [%0], %1}"
,
xops
)
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
reg
;
output_asm_insn
(
"cmp%z0\t{%1, %0|%0, %1}"
,
xops
)
;
fputs
(
"\tjne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Adjust the stack pointer up to REG while probing it .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static rtx mips_return_fpr_single ( machine_mode type_mode , machine_mode value_mode ) { rtx x ; x = gen_rtx_REG ( value_mode , FP_RETURN ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , const0_rtx ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( 1 , x ) ) ; } return x ; } </s>

Return the representation of an FPR return register when the value being returned in FP_RETURN has mode VALUE_MODE and the return type itself has mode TYPE_MODE . On NewABI targets , the two modes may be different for structures like : struct __attribute__ ( ( packed ) ) foo { float f ; } where we return the SFmode value of `` f '' in FP_RETURN , but where the structure itself has mode BLKmode .


<s>
const
char
*
fpuv3_output_move
(
rtx
*
operands
)
{
rtx
reg
,
mem
,
addr
,
ops
[
2
]
;
bool
isload
=
REG_P
(
operands
[
0
]
)
;
const
char
*
templ
=
"f%s%s.%s\t%%0, %%1"
;
char
buff
[
50
]
;
machine_mode
mode
;
reg
=
operands
[
isload
0
:
1
]
;
mem
=
operands
[
isload
1
:
0
]
;
gcc_assert
(
REG_P
(
reg
)
)
;
gcc_assert
(
CSKY_VREG_P
(
REGNO
(
reg
)
)
)
;
gcc_assert
(
MEM_P
(
mem
)
)
;
mode
=
GET_MODE
(
reg
)
;
const
char
*
type
=
mode
==
DFmode
"64"
:
mode
==
SFmode
"32"
:
mode
==
HFmode
"16"
:
;
gcc_assert
(
type
!=
)
;
addr
=
XEXP
(
mem
,
0
)
;
struct
csky_address
caddr
;
decompose_csky_address
(
addr
,
&
caddr
)
;
ops
[
0
]
=
reg
;
ops
[
1
]
=
mem
;
sprintf
(
buff
,
templ
,
isload
"ld"
:
"st"
,
caddr
.
index
"r"
:
""
,
type
)
;
output_asm_insn
(
buff
,
ops
)
;
return
""
;
}
</s>

Output float point load/store instructions for fpuv3 .


<s> void mips_expand_vec_unpack ( rtx operands [ 2 ] , bool unsigned_p , bool high_p ) { machine_mode imode = GET_MODE ( operands [ 1 ] ) ; rtx ( * unpack ) ( rtx , rtx , rtx ) ; rtx ( * cmpFunc ) ( rtx , rtx , rtx ) ; rtx tmp , dest , zero ; if ( MSA_SUPPORTED_MODE_P ( imode ) ) { switch ( imode ) { case E_V4SImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_w ; else unpack = gen_msa_ilvr_w ; cmpFunc = gen_msa_clt_s_w ; break ; case E_V8HImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_h ; else unpack = gen_msa_ilvr_h ; cmpFunc = gen_msa_clt_s_h ; break ; case E_V16QImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_b ; else unpack = gen_msa_ilvr_b ; cmpFunc = gen_msa_clt_s_b ; break ; default : gcc_unreachable ( ) ; break ; } if ( ! unsigned_p ) { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , operands [ 1 ] , CONST0_RTX ( imode ) ) ) ; } else tmp = force_reg ( imode , CONST0_RTX ( imode ) ) ; dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; return ; } switch ( imode ) { case E_V8QImode : if ( high_p ) unpack = gen_loongson_punpckhbh ; else unpack = gen_loongson_punpcklbh ; cmpFunc = gen_loongson_pcmpgtb ; break ; case E_V4HImode : if ( high_p ) unpack = gen_loongson_punpckhhw ; else unpack = gen_loongson_punpcklhw ; cmpFunc = gen_loongson_pcmpgth ; break ; default : gcc_unreachable ( ) ; } zero = force_reg ( imode , CONST0_RTX ( imode ) ) ; if ( unsigned_p ) tmp = zero ; else { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , zero , operands [ 1 ] ) ) ; } dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; } </s>

Expand an integral vector unpack operation .


Internal method for ix86_init_builtins .


<s> inline static rtx emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI . getOpcode ( ) , Subtarget ) ) return 0 ; const MachineOperand & MO = MI . getOperand ( 0 ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return 0 ; } return PartialRegUpdateClearance ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


Function to tell the preprocessor about the defines for the current target .


<s> bool WinEHStatePass :: doFinalization ( Module & M ) { assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy = nullptr ; SEHRegistrationTy = nullptr ; SetJmp3 = nullptr ; CxxLongjmpUnwind = nullptr ; SehLongjmpUnwind = nullptr ; Cookie = nullptr ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void mips_expand_prologue ( void ) { HOST_WIDE_INT size ; if ( cfun -> machine -> global_pointer > 0 ) REGNO ( pic_offset_table_rtx ) = cfun -> machine -> global_pointer ; size = compute_frame_size ( get_frame_size ( ) ) ; if ( ( cfun -> machine -> frame . mask | cfun -> machine -> frame . fmask ) != 0 ) { HOST_WIDE_INT step1 ; step1 = MIN ( size , MIPS_MAX_FIRST_STACK_STEP ) ; RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ) ) = 1 ; size -= step1 ; mips_for_each_saved_reg ( size , mips_save_reg ) ; } if ( size > 0 ) { if ( SMALL_OPERAND ( - size ) ) RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ) = 1 ; else { emit_move_insn ( MIPS_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( size ) ) ; if ( TARGET_MIPS16 ) { gcc_assert ( frame_pointer_needed ) ; emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; emit_insn ( gen_sub3_insn ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; } else emit_insn ( gen_sub3_insn ( stack_pointer_rtx , stack_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; mips_set_frame_expr ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( stack_pointer_rtx , - size ) ) ) ; } } if ( frame_pointer_needed ) { if ( TARGET_MIPS16 && cfun -> machine -> frame . args_size != 0 ) { rtx offset = GEN_INT ( cfun -> machine -> frame . args_size ) ; if ( SMALL_OPERAND ( cfun -> machine -> frame . args_size ) ) RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , offset ) ) ) = 1 ; else { emit_move_insn ( MIPS_PROLOGUE_TEMP ( Pmode ) , offset ) ; emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; mips_set_frame_expr ( gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( stack_pointer_rtx , cfun -> machine -> frame . args_size ) ) ) ; } } else RTX_FRAME_RELATED_P ( emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) = 1 ; } if ( TARGET_ABICALLS && ! TARGET_NEWABI && ! current_function_is_leaf ) emit_insn ( gen_cprestore ( GEN_INT ( current_function_outgoing_args_size ) ) ) ; mips_emit_loadgp ( ) ; if ( current_function_profile ) emit_insn ( gen_blockage ( ) ) ; } </s>

Expand the prologue into a bunch of separate insns .


<s> static tree ix86_veclibabi_acml ( enum built_in_function fn , tree type_out , tree type_in ) { char name [ 20 ] = "__vr.._" ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! TARGET_64BIT || ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { case BUILT_IN_SIN : case BUILT_IN_COS : case BUILT_IN_EXP : case BUILT_IN_LOG : case BUILT_IN_LOG2 : case BUILT_IN_LOG10 : name [ 4 ] = 'd' ; name [ 5 ] = '2' ; if ( el_mode != DFmode || n != 2 ) return NULL_TREE ; break ; case BUILT_IN_SINF : case BUILT_IN_COSF : case BUILT_IN_EXPF : case BUILT_IN_POWF : case BUILT_IN_LOGF : case BUILT_IN_LOG2F : case BUILT_IN_LOG10F : name [ 4 ] = 's' ; name [ 5 ] = '4' ; if ( el_mode != SFmode || n != 4 ) return NULL_TREE ; break ; default : return NULL_TREE ; } bname = IDENTIFIER_POINTER ( DECL_NAME ( builtin_decl_implicit ( fn ) ) ) ; sprintf ( name + 7 , "%s" , bname + 10 ) ; arity = 0 ; for ( args = DECL_ARGUMENTS ( builtin_decl_implicit ( fn ) ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an ACML-style interface to a library with vectorized intrinsics .


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM


<s> static void mips_avoid_hazard ( rtx_insn * after , rtx_insn * insn , int * hilo_delay , rtx * delayed_reg , rtx lo_reg , bool * fs_delay ) { rtx pattern , set ; int nops , ninsns ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= 0 ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / 4 ; if ( ninsns == 0 ) return ; if ( * hilo_delay < 2 && reg_set_p ( lo_reg , pattern ) ) nops = 2 - * hilo_delay ; else if ( * delayed_reg != 0 && reg_referenced_p ( * delayed_reg , pattern ) ) nops = 1 ; else if ( * fs_delay && get_attr_can_delay ( insn ) == CAN_DELAY_NO && GET_CODE ( PATTERN ( after ) ) != SEQUENCE && GET_CODE ( pattern ) != ASM_INPUT && asm_noperands ( pattern ) < 0 ) nops = 1 ; else if ( TUNE_P6600 && TARGET_CB_MAYBE && ! optimize_size && ( ( mips_classify_branch_p6600 ( after ) == UC_BALC && mips_classify_branch_p6600 ( insn ) == UC_OTHER ) || ( mips_classify_branch_p6600 ( insn ) == UC_BALC && mips_classify_branch_p6600 ( after ) == UC_OTHER ) ) ) nops = 1 ; else nops = 0 ; * hilo_delay += nops ; rtx_insn * real_after = after ; if ( real_after && nops && CALL_P ( real_after ) ) while ( real_after && ( NOTE_P ( NEXT_INSN ( real_after ) ) || BARRIER_P ( NEXT_INSN ( real_after ) ) ) ) real_after = NEXT_INSN ( real_after ) ; while ( nops -- > 0 ) emit_insn_after ( gen_hazard_nop ( ) , real_after ) ; * hilo_delay += ninsns ; * delayed_reg = 0 ; * fs_delay = false ; if ( INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : if ( TUNE_P6600 && ! optimize_size && TARGET_CB_MAYBE && mips_classify_branch_p6600 ( insn ) == UC_OTHER ) * fs_delay = true ; break ; case HAZARD_FORBIDDEN_SLOT : if ( TARGET_CB_MAYBE ) * fs_delay = true ; break ; case HAZARD_HILO : * hilo_delay = 0 ; break ; case HAZARD_DELAY : set = single_set ( insn ) ; gcc_assert ( set ) ; * delayed_reg = SET_DEST ( set ) ; break ; } } </s>

Subroutine of mips_reorg . If there is a hazard between INSN and a previous instruction , avoid it by inserting nops after instruction AFTER . * DELAYED_REG and * HILO_DELAY describe the hazards that apply at this point . If * DELAYED_REG is non-null , INSN must wait a cycle before using the value of that register . * HILO_DELAY counts the number of instructions since the last hilo hazard ( that is , the number of instructions since the last mflo or mfhi ) . After inserting nops for INSN , update * DELAYED_REG and * HILO_DELAY for the next instruction . LO_REG is an rtx for the LO register , used in dependence checking .


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR , dconsthalf , half_minus_pred_half ) ; half = const_double_from_real_value ( pred_half , mode ) ; e1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_copysign ( e1 , half , op1 ) ) ; e2 = expand_simple_binop ( mode , PLUS , op1 , e1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; res = gen_reg_rtx ( mode ) ; emit_insn ( gen_round ( res , e2 , GEN_INT ( ROUND_TRUNC ) ) ) ; emit_move_insn ( op0 , res ) ; } </s>

Expand SSE sequence for computing round from OP1 storing into OP0 using sse4 round insn .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & LC2200 :: GRRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case 128 : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case 256 : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } if ( ! ! ( Flags & MachineMemOperand :: MONonTemporal ) && VT . isVector ( ) ) { if ( ! ! ( Flags & MachineMemOperand :: MOLoad ) ) return ( Alignment < 16 || ! Subtarget . hasSSE41 ( ) ) ; return false ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool Cpu0AsmParser :: ParseDirective ( AsmToken DirectiveID ) { if ( DirectiveID . getString ( ) == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".end" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".set" ) { return parseDirectiveSet ( ) ; } if ( DirectiveID . getString ( ) == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"OR1K PIC Global Base Reg Initialization"

getPassName - Return a nice clean name for a pass .


<s> TargetPassConfig * DCPU16TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new DCPU16PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> unsigned SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ; } </s>


<s> static int find_r0_life_regions ( basic_block b ) { bool live ; int set ; int death = 0 ; if ( REGNO_REG_SET_P ( df_get_live_in ( b ) , R0_REG ) ) { set = 1 ; live = true ; } else { set = 0 ; live = false ; } rtx_insn * insn = BB_HEAD ( b ) ; rtx_insn * end = BB_END ( b ) ; rtx r0_reg = gen_rtx_REG ( SImode , R0_REG ) ; while ( 1 ) { if ( INSN_P ( insn ) ) { if ( find_regno_note ( insn , REG_DEAD , R0_REG ) ) { death ++ ; live = false ; } rtx pset ; if ( ! live && ( pset = single_set ( insn ) ) && reg_overlap_mentioned_p ( r0_reg , SET_DEST ( pset ) ) && ! find_regno_note ( insn , REG_UNUSED , R0_REG ) ) { set ++ ; live = true ; } } if ( insn == end ) break ; insn = NEXT_INSN ( insn ) ; } return set - death ; } </s>


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function * F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; unsigned OptimizationGoal ; if ( F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = 6 ; else if ( F -> optForMinSize ( ) ) OptimizationGoal = 4 ; else if ( F -> optForSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer -> EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


"After expanding ARM pseudo instructions."


<s>
enum
calling_abi
ix86_function_type_abi
(
const_tree
fntype
)
{
enum
calling_abi
abi
=
ix86_abi
;
if
(
fntype
==
NULL_TREE
||
TYPE_ATTRIBUTES
(
fntype
)
==
NULL_TREE
)
return
abi
;
if
(
abi
==
SYSV_ABI
&&
lookup_attribute
(
"ms_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
{
if
(
TARGET_X32
)
error
(
"X32 does not support ms_abi attribute"
)
;
abi
=
MS_ABI
;
}
else
if
(
abi
==
MS_ABI
&&
lookup_attribute
(
"sysv_abi"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
abi
=
SYSV_ABI
;
return
abi
;
}
</s>

Returns value SYSV_ABI , MS_ABI dependent on fntype , specifying the call abi used .


<s> bool X86TTIImpl :: isLegalNTStore ( Type * DataType , unsigned Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < 4 || DataSize > 32 || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == 32 ) return ST -> hasAVX ( ) ; else if ( DataSize == 16 ) return ST -> hasSSE1 ( ) ; return true ; } </s>

Return true if the target supports nontemporal store .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: ILP ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( MCID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( MCID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: ILP ; return Sched :: RegPressure ; } </s>


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && VT . getSizeInBits ( ) == 128 ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT , Subtarget -> hasAVX ( ) ) || isSHUFPMask ( Mask , VT , Subtarget -> hasAVX ( ) , true ) ) ; } return false ; } </s>


<s> bool MipsTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createMipsDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx legitimize_pe_coff_extern_decl ( rtx symbol , bool want_reg ) { tree imp_decl ; rtx x ; gcc_assert ( SYMBOL_REF_DECL ( symbol ) ) ; imp_decl = get_dllimport_decl ( SYMBOL_REF_DECL ( symbol ) , false ) ; x = DECL_RTL ( imp_decl ) ; if ( want_reg ) x = force_reg ( Pmode , x ) ; return x ; } </s>

Expand SYMBOL into its corresponding far-addresse symbol . WANT_REG is true if we require the result be a register .


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
Register
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
MI
.
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s> SDValue getStoredValue ( SDValue Op ) { switch ( Op -> getOpcode ( ) ) { case ISD :: EXPERIMENTAL_VP_STRIDED_STORE : case VEISD :: VVP_STORE : return Op -> getOperand ( 1 ) ; } if ( auto * StoreN = dyn_cast < StoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < MaskedStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < VPStridedStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < VPStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < MaskedScatterSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < VPScatterSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; return SDValue ( ) ; } </s>

Return the address accessed by this recipe .


<s> bool aarch64_sve_mode_p ( machine_mode mode ) { return aarch64_classify_vector_mode ( mode ) & VEC_ANY_SVE ; } </s>

Return true if MODE is any form of SVE mode , including predicates , vectors and structures .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( ! HasNopl ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool sh_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( SPECIAL_REGISTER_P ( regno ) ) return mode == SImode ; if ( regno == FPUL_REG ) return ( mode == SImode || mode == SFmode ) ; if ( FP_REGISTER_P ( regno ) && mode == SFmode ) return true ; if ( mode == V2SFmode ) { if ( ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 2 == 0 ) || GENERAL_REGISTER_P ( regno ) ) ) return true ; else return false ; } if ( mode == V4SFmode ) { if ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 4 == 0 ) || GENERAL_REGISTER_P ( regno ) ) return true ; else return false ; } if ( mode == V16SFmode ) return regno == FIRST_XD_REG ; if ( FP_REGISTER_P ( regno ) ) { if ( mode == SFmode || mode == SImode || ( ( TARGET_SH2E ) && mode == SCmode ) || ( ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & 1 ) == 0 ) || ( TARGET_SH4 && mode == TImode && ( ( regno - FIRST_FP_REG ) & 3 ) == 0 ) ) return true ; else return false ; } if ( XD_REGISTER_P ( regno ) ) return mode == DFmode ; if ( regno == PR_REG ) return mode == SImode ; if ( regno == FPSCR_REG ) return mode == SImode ; return true ; } </s>

Return true if hard register REGNO can hold a value of machine-mode MODE . We can allow any mode in any general register . The special registers only allow SImode . Do n't allow any mode in the PR . We can not hold DCmode values in the XD registers because alter_reg handles subregs of them incorrectly . We could work around this by spacing the XD registers like the DR registers , but this would require additional memory in every compilation to hold larger register vectors . We could hold SFmode / SCmode values in XD registers , but that would require a tertiary reload when reloading from / to memory , and a secondary reload to reload from / to general regs ; that seems to be a losing proposition . We want to allow TImode FP regs so that when V4SFmode is loaded as TImode , it wo n't be ferried through GP registers first .


<s>
const
ArrayRef
<
MCPhysReg
>
SICABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsS32
(
)
)
return
makeArrayRef
(
S32IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


<s> bool function_resolver :: scalar_argument_p ( unsigned int i ) { tree type = get_argument_type ( i ) ; return ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || SCALAR_FLOAT_TYPE_P ( type ) ) ; } </s>

Return true if argument I is some form of scalar value .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { short imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) ) return false ; APInt LHSKnownZero , LHSKnownOne ; APInt RHSKnownZero , RHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( 0 ) , APInt :: getAllOnesValue ( N . getOperand ( 0 ) . getValueSizeInBits ( ) ) , LHSKnownZero , LHSKnownOne ) ; if ( LHSKnownZero . getBoolValue ( ) ) { DAG . ComputeMaskedBits ( N . getOperand ( 1 ) , APInt :: getAllOnesValue ( N . getOperand ( 1 ) . getValueSizeInBits ( ) ) , RHSKnownZero , RHSKnownOne ) ; if ( ~ ( LHSKnownZero | RHSKnownZero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> const X86Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createX86LowerAMXIntrinsicsPass ( ) ) ; addPass ( createX86LowerAMXTypePass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createX86PreAMXConfigPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
void
SystemZRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
const
TargetFrameInfo
&
TFI
=
*
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SystemZMachineFunctionInfo
*
SystemZMFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
StackSize
-=
SystemZMFI
->
getCalleeSavedFrameSize
(
)
;
uint64_t
NumBytes
=
StackSize
TFI
.
getOffsetOfLocalArea
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mr
||
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mrm
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
StackSize
||
MFI
->
hasCalls
(
)
)
{
assert
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
SystemZ
::
R15D
)
&&
"Invalid stack frame calculation!"
)
;
emitSPUpdate
(
MBB
,
MBBI
,
(
int64_t
)
NumBytes
,
TII
)
;
}
if
(
hasFP
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
SystemZ
::
MOV64rr
)
,
SystemZ
::
R11D
)
.
addReg
(
SystemZ
::
R15D
)
;
for
(
MachineFunction
::
iterator
I
=
llvm
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
SystemZ
::
R11D
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> static void iq2000_emit_frame_related_store ( rtx mem , rtx reg , HOST_WIDE_INT offset ) { rtx dwarf_address = plus_constant ( stack_pointer_rtx , offset ) ; rtx dwarf_mem = gen_rtx_MEM ( GET_MODE ( reg ) , dwarf_address ) ; iq2000_annotate_frame_insn ( emit_move_insn ( mem , reg ) , gen_rtx_SET ( GET_MODE ( reg ) , dwarf_mem , reg ) ) ; } </s>

Emit a move instruction that stores REG in MEM . Make the instruction frame related and note that it stores REG at ( SP + OFFSET ) .


<s> void ix86_emit_fp_unordered_jump ( rtx label ) { rtx reg = gen_reg_rtx ( HImode ) ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_USE_SAHF ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( reg , GEN_INT ( 0x04 ) ) ) ; temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( VOIDmode , pc_rtx , temp ) ; emit_jump_insn ( temp ) ; } </s>

Output code to perform a conditional jump to LABEL , if C2 flag in FP status register is set .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void ARMTargetLowering :: HandleByVal ( CCState * State , unsigned & Size , unsigned Align ) const { Align = std :: max ( Align , 4U ) ; unsigned Reg = State -> AllocateReg ( GPRArgRegs ) ; if ( ! Reg ) return ; unsigned AlignInRegs = Align / 4 ; unsigned Waste = ( ARM :: R4 - Reg ) % AlignInRegs ; for ( unsigned i = 0 ; i < Waste ; ++ i ) Reg = State -> AllocateReg ( GPRArgRegs ) ; if ( ! Reg ) return ; unsigned Excess = 4 * ( ARM :: R4 - Reg ) ; const unsigned NSAAOffset = State -> getNextStackOffset ( ) ; if ( NSAAOffset != 0 && Size > Excess ) { while ( State -> AllocateReg ( GPRArgRegs ) ) ; return ; } unsigned ByValRegBegin = Reg ; unsigned ByValRegEnd = std :: min < unsigned > ( Reg + Size / 4 , ARM :: R4 ) ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ; for ( unsigned i = Reg + 1 ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs ) ; Size = std :: max < int > ( Size - Excess , 0 ) ; } </s>

Target-specific cleanup for formal ByVal parameters .