<s> void aarch64_expand_sve_mem_move ( rtx dest , rtx src , machine_mode pred_mode ) { machine_mode mode = GET_MODE ( dest ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) aarch64_emit_sve_pred_move ( tmp , ptrue , src ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } aarch64_emit_sve_pred_move ( dest , ptrue , src ) ; } </s>

Expand a pre-RA SVE data move from SRC to DEST in which at least one operand is in memory . In this case we need to use the predicated LD1 and ST1 instead of LDR and STR , both for correctness on big-endian targets and because LD1 and ST1 support a wider range of addressing modes . PRED_MODE is the mode of the predicate . See the comment at the head of aarch64-sve.md for details about the big-endian handling .


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = TFI -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * this , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void aarch64_option_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; selected_tune = aarch64_get_tune_cpu ( ptr -> x_explicit_tune_core ) ; opts -> x_explicit_arch = ptr -> x_explicit_arch ; selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ; opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ; opts -> x_aarch64_branch_protection_string = ptr -> x_aarch64_branch_protection_string ; if ( opts -> x_aarch64_branch_protection_string ) { aarch64_parse_branch_protection ( opts -> x_aarch64_branch_protection_string , NULL ) ; } aarch64_override_options_internal ( opts ) ; } </s>

Implements TARGET_OPTION_RESTORE . Restore the backend codegen decisions using the information saved in PTR .


<s> bool LEGPassConfig :: addInstSelector ( ) { addPass ( createLEGISelDag ( getLEGTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool X86TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 32 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; AArch64PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>

runOnMachineFunction - Emit the function body .


"execute-only should not generate constant pools"

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool X86CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const X86TargetLowering & TLI = * getTLI < X86TargetLowering > ( ) ; LLVMContext & Context = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( SplitVTs . size ( ) != 1 ) { return false ; } EVT VT = SplitVTs [ 0 ] ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return true ; } SmallVector < unsigned , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; SplitRegs . push_back ( Info . Reg ) ; } PerformArgSplit ( SplitRegs ) ; return true ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


" was Pass-through, is now Dirty-out.\n"


<s> bool OR1KPassConfig :: addInstSelector ( ) { addPass ( createOR1KISelDag ( getTM < OR1KTargetMachine > ( ) ) ) ; addPass ( createOR1KGlobalBaseRegPass ( ) ) ; return false ; } </s>


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> void MipsSEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

Mips Mips Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips::SP_64 Mips::SP


<s> static bool arm_9e_rtx_costs ( rtx x , int code , int outer_code , int * total ) { enum machine_mode mode = GET_MODE ( x ) ; int nonreg_cost ; int cost ; if ( TARGET_THUMB ) { switch ( code ) { case MULT : * total = COSTS_N_INSNS ( 3 ) ; return true ; default : * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = 3 ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { * total = 30 ; return true ; } if ( mode == DImode ) { cost = 7 ; nonreg_cost = 8 ; } else { cost = 2 ; nonreg_cost = 4 ; } * total = cost + ( REG_OR_SUBREG_REG ( XEXP ( x , 0 ) ) ? 0 : nonreg_cost ) + ( REG_OR_SUBREG_REG ( XEXP ( x , 1 ) ) ? 0 : nonreg_cost ) ; return true ; default : * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; } } </s>


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
LLVM_FALLTHROUGH
;
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
if
(
!
selectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool MipsMCCodeEmitter :: isMicroMips ( const MCSubtargetInfo & STI ) const { return STI . getFeatureBits ( ) [ Mips :: FeatureMicroMips ] ; } </s>

Check whether a given symbol has been flagged with MICROMIPS flag .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == 0 && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> bool PPCCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { return VRegs . empty ( ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { int Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1


<s> static void aarch64_test_loading_full_dump ( ) { rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "aarch64/times-two.rtl" ) ) ; ASSERT_STREQ ( "times_two" , IDENTIFIER_POINTER ( DECL_NAME ( cfun -> decl ) ) ) ; rtx_insn * insn_1 = get_insn_by_uid ( 1 ) ; ASSERT_EQ ( NOTE , GET_CODE ( insn_1 ) ) ; rtx_insn * insn_15 = get_insn_by_uid ( 15 ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_15 ) ) ; ASSERT_EQ ( USE , GET_CODE ( PATTERN ( insn_15 ) ) ) ; ASSERT_EQ ( REG , GET_CODE ( crtl -> return_rtx ) ) ; ASSERT_EQ ( 0 , REGNO ( crtl -> return_rtx ) ) ; ASSERT_EQ ( SImode , GET_MODE ( crtl -> return_rtx ) ) ; } </s>

Selftest for the RTL loader . Verify that the RTL loader copes with a dump from print_rtx_function . This is essentially just a test that class function_reader can handle a real dump , but it also verifies that lookup_reg_by_dump_name correctly handles hard regs . The presence of hard reg names in the dump means that the test is target-specific , hence it is in this file .


<s> static std :: unique_ptr < MipsOperand > CreateMem ( std :: unique_ptr < MipsOperand > Base , const MCExpr * Off , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = make_unique < MipsOperand > ( k_Memory , Parser ) ; Op -> Mem . Base = Base . release ( ) ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> static int ix86_address_cost ( rtx x , machine_mode , addr_space_t , bool ) { struct ix86_address parts ; int cost = 1 ; int ok = ix86_decompose_address ( x , & parts ) ; gcc_assert ( ok ) ; if ( parts . base && SUBREG_P ( parts . base ) ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && SUBREG_P ( parts . index ) ) parts . index = SUBREG_REG ( parts . index ) ; if ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . base ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . base ) ) ) cost ++ ; if ( parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . index ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . index ) ) ) cost ++ ; if ( TARGET_CPU_P ( K6 ) && ( ( ! parts . disp && parts . base && parts . index && parts . scale != 1 ) || ( parts . disp && ! parts . base && parts . index && parts . scale != 1 ) || ( ! parts . disp && parts . base && parts . index && parts . scale == 1 ) ) ) cost += 10 ; return cost ; } </s>

Return cost of the memory address x . For i386 , it is better to use a complex address than let gcc copy the address into a reg and make a new pseudo . But not if the address requires to two regs - that would mean more pseudos with longer lifetimes .


<s> static rtx aarch64_convert_mult_to_shift ( rtx value , rtx_code & code ) { if ( GET_CODE ( value ) != CONST_VECTOR ) return NULL_RTX ; rtx_vector_builder builder ; if ( ! builder . new_unary_operation ( GET_MODE ( value ) , value , false ) ) return NULL_RTX ; scalar_mode int_mode = GET_MODE_INNER ( GET_MODE ( value ) ) ; int negate = - 1 ; unsigned int encoded_nelts = const_vector_encoded_nelts ( value ) ; for ( unsigned int i = 0 ; i < encoded_nelts ; ++ i ) { rtx elt = CONST_VECTOR_ENCODED_ELT ( value , i ) ; if ( ! CONST_SCALAR_INT_P ( elt ) ) return NULL_RTX ; rtx_mode_t val ( elt , int_mode ) ; wide_int pow2 = wi :: neg ( val ) ; if ( val != pow2 ) { if ( negate == ! wi :: neg_p ( val ) ) return NULL_RTX ; negate = wi :: neg_p ( val ) ; if ( ! negate ) pow2 = val ; } int shift = wi :: exact_log2 ( pow2 ) ; if ( shift < 0 ) return NULL_RTX ; builder . quick_push ( gen_int_mode ( shift , int_mode ) ) ; } if ( negate == - 1 ) code = PLUS ; else if ( negate == 1 ) code = code == PLUS ? MINUS : PLUS ; return builder . build ( ) ; } </s>

Check whether VALUE is a vector constant in which every element is either a power of 2 or a negated power of 2 . If so , return a constant vector of log2s , and flip CODE between PLUS and MINUS if VALUE contains negated powers of 2 . Return NULL_RTX otherwise .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Token
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
k_Register
:
OS
<<
"Reg: #"
<<
getReg
(
)
<<
"\n"
;
break
;
case
k_Immediate
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
k_MemoryRegRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+#"
<<
getMemIndexReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryRegImmImm
:
assert
(
getMemIndex
(
)
!=
nullptr
&&
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+"
<<
*
getMemIndex
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+#"
<<
getMemIndexReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroImmImm
:
assert
(
getMemIndex
(
)
!=
nullptr
&&
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+"
<<
*
getMemIndex
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> DecodeStatus VEDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { uint64_t Insn ; bool isLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; DecodeStatus Result = readInstruction64 ( Bytes , Address , Size , Insn , isLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableVE64 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 8 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> static int function_arg_slotno ( const struct sparc_args * cum , machine_mode mode , const_tree type , bool named , bool incoming , int * pregno , int * ppadding ) { int regbase = ( incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = 0 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != 0 ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) slotno ++ , * ppadding = 1 ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) != RECORD_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } else { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { classify_data_t data = { false , false } ; traverse_record_type < classify_data_t , classify_registers > ( type , named , & data ) ; if ( data . fp_regs ) { if ( slotno >= SPARC_FP_ARG_MAX - 1 && ! data . fp_regs_in_first_word ) return - 1 ; } else { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; } } return slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s> void Cpu0TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { ARM64FunctionInfo * AFI = MF . getInfo < ARM64FunctionInfo > ( ) ; if ( AFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> static HOST_WIDE_INT get_label_padding ( rtx label ) { HOST_WIDE_INT align , min_insn_size ; align = 1 << label_to_alignment ( label ) . levels [ 0 ] . log ; min_insn_size = TARGET_THUMB ? 2 : 4 ; return align > min_insn_size ? align - min_insn_size : 0 ; } </s>

Return the maximum amount of padding that will be inserted before label LABEL .


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilderBase & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntValTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( Val -> getType ( ) ) ) ; Val = Builder . CreateBitCast ( Val , IntValTy ) ; CallInst * CI = Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; CI -> addParamAttr ( 1 , Attribute :: get ( Builder . getContext ( ) , Attribute :: ElementType , Val -> getType ( ) ) ) ; return CI ; } </s>

Perform a store-conditional operation to Addr .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: STXVD2X : case PPC :: STXVX : case PPC :: QVSTFDX : case PPC :: QVSTFSXs : case PPC :: QVSTFDXb : case PPC :: SPILL_VRSAVE : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> int ARMTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static int safe_group_barrier_needed ( rtx_insn * insn ) { int saved_first_instruction ; int t ; saved_first_instruction = first_instruction ; in_safe_group_barrier = 1 ; t = group_barrier_needed ( insn ) ; first_instruction = saved_first_instruction ; in_safe_group_barrier = 0 ; return t ; } </s>

Like group_barrier_needed , but do not clobber the current state .


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
MipsRegisterInfo
::
getRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
Mips
"Unable to encode MachineOperand!"
0


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ! BYTES_BIG_ENDIAN && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; if ( TARGET_HAVE_MVE && ! BYTES_BIG_ENDIAN && VALID_MVE_MODE ( mode ) && ( nelems == 2 || nelems == 4 ) ) return true ; return false ; } </s>

Implements target hook array_mode_supported_p .


"getJumpTargetOpValue expects only expressions or an immediate"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> void xstormy16_expand_move ( enum machine_mode mode , rtx dest , rtx src ) { if ( ( GET_CODE ( dest ) == MEM ) && ( GET_CODE ( XEXP ( dest , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( dest , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( Pmode , dest_reg , dest_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , 16 ) ) ; dest = gen_rtx_MEM ( mode , dest_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else if ( ( GET_CODE ( src ) == MEM ) && ( GET_CODE ( XEXP ( src , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( src , 0 ) ; rtx src_reg = XEXP ( pmv , 0 ) ; rtx src_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( Pmode , src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , 16 ) ) ; src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && GET_CODE ( dest ) == MEM && ( GET_CODE ( XEXP ( dest , 0 ) ) != CONST_INT || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , 0 ) , 0 ) ) && ! xstormy16_below100_operand ( dest , mode ) && GET_CODE ( src ) != REG && GET_CODE ( src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ; if ( reload_completed && mode != HImode && mode != QImode ) { xstormy16_split_move ( mode , dest , src ) ; return ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; } </s>

Expander for the 'move ' patterns . Emit insns to copy a value of mode MODE from SRC to DEST .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static inline tree def_builtin_pure ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin ( mask , name , tcode , code ) ; if ( decl ) DECL_PURE_P ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . pure_p = true ; return decl ; } </s>

Like def_builtin , but also marks the function decl `` pure '' .


<s> bool ARMTargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { bool has64BitAtomicStore ; if ( Subtarget -> isMClass ( ) ) has64BitAtomicStore = false ; else if ( Subtarget -> isThumb ( ) ) has64BitAtomicStore = Subtarget -> hasV7Ops ( ) ; else has64BitAtomicStore = Subtarget -> hasV6Ops ( ) ; unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == 64 && has64BitAtomicStore ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s>
static
unsigned
getScalarSizeInBits
(
Type
*
Ty
)
{
unsigned
Size
=
(
Ty
->
isPtrOrPtrVectorTy
(
)
64U
:
Ty
->
getScalarSizeInBits
(
)
)
;
assert
(
Size
>
0
&&
"Element must have non-zero size."
)
;
return
Size
;
}
</s>

If this is a vector type , return the getPrimitiveSizeInBits value for the element type .


<s>
static
std
::
pair
<
SDValue
,
SDValue
>
splitVector
(
SDValue
Op
,
SelectionDAG
&
DAG
,
const
SDLoc
&
dl
)
{
EVT
VT
=
Op
.
getValueType
(
)
;
unsigned
NumElems
=
VT
.
getVectorNumElements
(
)
;
unsigned
SizeInBits
=
VT
.
getSizeInBits
(
)
;
assert
(
(
NumElems
%
2
)
==
0
&&
(
SizeInBits
%
2
)
==
0
&&
"Can't split odd sized vector"
)
;
SDValue
Lo
=
extractSubVector
(
Op
,
0
,
DAG
,
dl
,
SizeInBits
/
2
)
;
if
(
DAG
.
isSplatValue
(
Op
,
false
)
)
return
std
::
make_pair
(
Lo
,
Lo
)
;
SDValue
Hi
=
extractSubVector
(
Op
,
NumElems
/
2
,
DAG
,
dl
,
SizeInBits
/
2
)
;
return
std
::
make_pair
(
Lo
,
Hi
)
;
}
</s>

Split a vector value into two parts of types LoVT and HiVT .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: R2 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool MipsTargetLowering :: IsEligibleForTailCallOptimization ( const MipsCC & MipsCCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! EnableMipsTailCalls ) return false ; if ( Subtarget -> inMips16Mode ( ) ) return false ; if ( MipsCCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . nextStackOffset ( ) ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> bool MipsSEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( Subtarget . inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void gen_ashift ( int type , int n , rtx reg ) { if ( n < 0 ) { if ( type == ASHIFT ) type = LSHIFTRT ; else type = ASHIFT ; n = - n ; } switch ( type ) { case ASHIFTRT : emit_insn ( gen_ashrsi3_k ( reg , reg , GEN_INT ( n ) ) ) ; break ; case LSHIFTRT : if ( n == 1 ) emit_insn ( gen_lshrsi3_m ( reg , reg , GEN_INT ( n ) ) ) ; else emit_insn ( gen_lshrsi3_k ( reg , reg , GEN_INT ( n ) ) ) ; break ; case ASHIFT : emit_insn ( gen_ashlsi3_std ( reg , reg , GEN_INT ( n ) ) ) ; break ; } } </s>


<s> static bool insn_references_regno_p ( rtx_insn * insn , unsigned int regno , enum attr_type type ) { struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref ref ; for ( ref = DF_INSN_INFO_DEFS ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( DF_REF_REGNO ( ref ) == regno ) return true ; if ( type == TYPE_LOAD || type == TYPE_FPLOAD || type == TYPE_VECLOAD ) for ( ref = DF_INSN_INFO_USES ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( DF_REF_REGNO ( ref ) == regno ) return true ; return false ; } </s>

Check whether INSN contains a reference to REGNO that will inhibit the PCREL_OPT optimization . If TYPE is a load or store instruction , return true if there is a definition of REGNO . If TYPE is a load instruction , then return true of there is a use of REGNO .


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return ABI . IsN64 ( ) ? Mips :: A1_64 : Mips :: A1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; InsertVRSaveCode ( MF ) ; return true ; } </s>


<s> rtx expand ( function_expander & e ) const OVERRIDE { int unspec = ( e . type_suffix ( 1 ) . unsigned_p ? m_unspec_for_uint : m_unspec_for_sint ) ; machine_mode pred_mode = e . vector_mode ( 0 ) ; scalar_mode reg_mode = GET_MODE_INNER ( e . vector_mode ( 1 ) ) ; return e . use_exact_insn ( code_for_while ( unspec , reg_mode , pred_mode ) ) ; } </s>


<s> bool systemSupportsUnalignedAccess ( ) const { return hasMips32r6 ( ) ; } </s>

Does the system support unaligned memory access .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = MF -> begin ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
static
tree
ix86_handle_struct_attribute
(
tree
*
node
,
tree
name
,
tree
,
int
,
bool
*
no_add_attrs
)
{
tree
*
type
=
;
if
(
DECL_P
(
*
node
)
)
{
if
(
TREE_CODE
(
*
node
)
==
TYPE_DECL
)
type
=
&
TREE_TYPE
(
*
node
)
;
}
else
type
=
node
;
if
(
!
(
type
&&
RECORD_OR_UNION_TYPE_P
(
*
type
)
)
)
{
warning
(
OPT_Wattributes
,
"%qE attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
else
if
(
(
is_attribute_p
(
"ms_struct"
,
name
)
&&
lookup_attribute
(
"gcc_struct"
,
TYPE_ATTRIBUTES
(
*
type
)
)
)
||
(
(
is_attribute_p
(
"gcc_struct"
,
name
)
&&
lookup_attribute
(
"ms_struct"
,
TYPE_ATTRIBUTES
(
*
type
)
)
)
)
)
{
warning
(
OPT_Wattributes
,
"%qE incompatible attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle a `` ms_struct '' or `` gcc_struct '' attribute ; arguments as in struct attribute_spec.handler .


<s> void AArch64TTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { UP . PartialOptSizeThreshold = 0 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> const char * csky_output_casesi ( rtx * operands ) { rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ 0 ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; switch ( GET_MODE ( diff_vec ) ) { case E_QImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "jbsr\t___gnu_csky_case_uqi" : "jbsr\t___gnu_csky_case_sqi" ) ; case E_HImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "jbsr\t___gnu_csky_case_uhi" : "jbsr\t___gnu_csky_case_shi" ) ; case E_SImode : return "jbsr\t___gnu_csky_case_si" ; default : gcc_unreachable ( ) ; } } </s>

Emit assembly code for CASESI . This is only used on CK801 and CK802 when optimizing for size , and uses helper functions in libgcc instead of doing the control transfer inline .


<s> unsigned ARMBaseInstrInfo :: getNumLDMAddresses ( const MachineInstr & MI ) const { unsigned Size = 0 ; for ( MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) , E = MI . memoperands_end ( ) ; I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ; } return Size / 4 ; } </s>

Get the number of addresses by LDM or VLDM or zero for unknown .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = false ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function :: ArgumentListType & Args , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; SmallVector < MVT , 8 > ArgTys ; for ( auto & Arg : Args ) ArgTys . push_back ( MVT :: getVT ( Arg . getType ( ) ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; return handleAssignments ( MIRBuilder , AssignFn , ArgTys , VRegs , [ ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ; MIRBuilder . buildCopy ( ValReg , PhysReg ) ; } ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"reloc_pcrel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_pcrel_1byte"
,
0
,
1
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static int ix86_reassociation_width ( unsigned int , machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) { if ( TARGET_VECTOR_PARALLEL_EXECUTION ) return 2 ; else return 1 ; } if ( INTEGRAL_MODE_P ( mode ) && TARGET_REASSOC_INT_TO_PARALLEL ) return 2 ; else if ( FLOAT_MODE_P ( mode ) && TARGET_REASSOC_FP_TO_PARALLEL ) return ( ( TARGET_64BIT && ix86_tune == PROCESSOR_HASWELL ) ? 4 : 2 ) ; else return 1 ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> SDValue SICTargetLowering :: getTargetNode ( JumpTableSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , 1 ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
MatchRegisterName
(
RegName
)
;
if
(
AArch64
::
X1
<=
Reg
&&
Reg
<=
AArch64
::
X28
)
{
const
MCRegisterInfo
*
MRI
=
Subtarget
->
getRegisterInfo
(
)
;
unsigned
DwarfRegNum
=
MRI
->
getDwarfRegNum
(
Reg
,
false
)
;
if
(
!
Subtarget
->
isXRegisterReserved
(
DwarfRegNum
)
)
Reg
=
0
;
}
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> static SDValue WidenVector ( SDValue V64Reg , SelectionDAG & DAG ) { EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = MVT :: getVectorVT ( EltTy , 2 * NarrowSize ) ; SDLoc DL ( V64Reg ) ; return DAG . getNode ( ISD :: INSERT_SUBVECTOR , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( 0 , MVT :: i32 ) ) ; } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s> CCAssignFn * X86FastISel :: CCAssignFnForCall ( CallingConv :: ID CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( CC == CallingConv :: GHC ) return CC_X86_64_GHC ; else if ( Subtarget -> isTargetWin64 ( ) ) return CC_X86_Win64_C ; else return CC_X86_64_C ; } if ( CC == CallingConv :: X86_FastCall ) return CC_X86_32_FastCall ; else if ( CC == CallingConv :: X86_ThisCall ) return CC_X86_32_ThisCall ; else if ( CC == CallingConv :: Fast ) return CC_X86_32_FastCC ; else if ( CC == CallingConv :: GHC ) return CC_X86_32_GHC ; else return CC_X86_32_C ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> SDNode * LC3DAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectMoveImmediate ( N ) ; case ISD :: BR_CC : return SelectConditionalBranch ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool SystemZElimCompare :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( * F . getFunction ( ) ) ) return false ; TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool rs6000_builtin_valid_without_lhs ( enum rs6000_builtins fn_code ) { if ( rs6000_builtin_info [ fn_code ] . attr & RS6000_BTC_VOID ) return true ; switch ( fn_code ) { case ALTIVEC_BUILTIN_STVX_V16QI : case ALTIVEC_BUILTIN_STVX_V8HI : case ALTIVEC_BUILTIN_STVX_V4SI : case ALTIVEC_BUILTIN_STVX_V4SF : case ALTIVEC_BUILTIN_STVX_V2DI : case ALTIVEC_BUILTIN_STVX_V2DF : case VSX_BUILTIN_STXVW4X_V16QI : case VSX_BUILTIN_STXVW4X_V8HI : case VSX_BUILTIN_STXVW4X_V4SF : case VSX_BUILTIN_STXVW4X_V4SI : case VSX_BUILTIN_STXVD2X_V2DF : case VSX_BUILTIN_STXVD2X_V2DI : return true ; default : return false ; } } </s>

Helper function to sort out which built-ins may be valid without having a LHS .


<s> bool PPCRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCInstrInfo * InstrInfo = Subtarget . getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & Info = MFI . getCalleeSavedInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) ) return true ; unsigned FrameSize = MFI . getStackSize ( ) ; if ( FrameSize & ~ 0x7FFF ) return true ; for ( unsigned i = 0 ; i < Info . size ( ) ; i ++ ) { int FrIdx = Info [ i ] . getFrameIdx ( ) ; unsigned Reg = Info [ i ] . getReg ( ) ; unsigned Opcode = InstrInfo -> getStoreOpcodeForSpill ( Reg ) ; if ( ! MFI . isFixedObjectIndex ( FrIdx ) ) { if ( offsetMinAlignForOpcode ( Opcode ) > 1 ) return true ; } if ( InstrInfo -> isXFormMemOp ( Opcode ) ) return true ; } return false ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> static const char * sparc_mangle_fundamental_type ( tree type ) { if ( ! TARGET_64BIT && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( - 1 , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getIndirectSymViaGOTPCRel ( const MCSymbol * Sym , const MCValue & MV , int64_t Offset , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { unsigned FinalOff = Offset + MV . getConstant ( ) + 4 ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Off = MCConstantExpr :: create ( FinalOff , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Off , getContext ( ) ) ; } </s>

Get the target specific PC relative GOT entry relocation .


<s> unsigned LanaiInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == Lanai :: SW_RI ) if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
SDValue
LanaiTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SETCCE
:
return
LowerSETCCE
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
return
LowerSRL_PARTS
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Lanai
Lanai
ISD::MUL
ISD::BR_CC
ISD::ConstantPool
ISD::GlobalAddress
ISD::BlockAddress
ISD::JumpTable
ISD::SELECT_CC
ISD::SETCC
ISD::SETCCE
ISD::SRL_PARTS
ISD::VASTART
ISD::DYNAMIC_STACKALLOC
ISD::RETURNADDR
ISD::FRAMEADDR
"unimplemented operand"


<s> static void mips_output_args_xfer ( int fp_code , char direction ) { unsigned int gparg , fparg , f ; CUMULATIVE_ARGS cum ; gcc_assert ( TARGET_OLDABI ) ; mips_init_cumulative_args ( & cum , NULL ) ; for ( f = ( unsigned int ) fp_code ; f != 0 ; f >>= 2 ) { machine_mode mode ; struct mips_arg_info info ; if ( ( f & 3 ) == 1 ) mode = SFmode ; else if ( ( f & 3 ) == 2 ) mode = DFmode ; else gcc_unreachable ( ) ; mips_get_arg_info ( & info , & cum , mode , NULL , true ) ; gparg = mips_arg_regno ( & info , false ) ; fparg = mips_arg_regno ( & info , true ) ; if ( mode == SFmode ) mips_output_32bit_xfer ( direction , gparg , fparg ) ; else mips_output_64bit_xfer ( direction , gparg , fparg ) ; function_arg_info arg ( mode , true ) ; mips_function_arg_advance ( pack_cumulative_args ( & cum ) , arg ) ; } } </s>

Write out code to move floating-point arguments into or out of general registers . FP_CODE is the code describing which arguments are present ( see the comment above the definition of CUMULATIVE_ARGS in mips.h ) . DIRECTION is as for mips_output_32bit_xfer .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( Type * Ty ) const { if ( Subtarget -> is64Bit ( ) ) { unsigned TyAlign = TD -> getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget -> hasSSE1 ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> unsigned TeeRISCInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { TeeRISCMachineFunctionInfo * TeeRISCFI = MF -> getInfo < TeeRISCMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = TeeRISCFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & TeeRISC :: IntRegsRegClass ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( TeeRISC :: ADD ) , GlobalBaseReg ) . addReg ( TeeRISC :: R10 ) ; RegInfo . addLiveIn ( TeeRISC :: R10 ) ; TeeRISCFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC 0 TeeRISC::IntRegsRegClass TeeRISC::ADD TeeRISC::R10 TeeRISC::R10 TeeRISC


<s> const MipsGNULDBackend & getTarget ( ) const { return m_Target ; } </s>

getTarget - Return the target machine this machine code is compiled with


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) ; Offset += MI . getOperand ( FIOperandNum + offsetToDisp ( MI ) ) . getImm ( ) ; if ( MI . getOpcode ( ) == VE :: STQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 3 ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , VE :: sub_even ) ; Register SrcLoReg = getSubReg ( SrcReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: STrii ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( SrcLoReg ) ; replaceFI ( MF , II , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: STrii ) ) ; MI . getOperand ( 3 ) . setReg ( SrcHiReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == VE :: LDQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , VE :: sub_even ) ; Register DestLoReg = getSubReg ( DestReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: LDrii ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) ; replaceFI ( MF , II , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: LDrii ) ) ; MI . getOperand ( 0 ) . setReg ( DestHiReg ) ; Offset += 8 ; } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool ShouldShrinkFPConstant ( EVT VT ) const { return VT != MVT :: f128 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> void ELFAArch64AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { const MCSection * Sec = Fixup . getValue ( ) -> FindAssociatedSection ( ) ; const MCSectionELF * SecELF = static_cast < const MCSectionELF * > ( Sec ) ; if ( SecELF -> getSectionName ( ) == ".eh_frame" ) Value = ByteSwap_32 ( unsigned ( Value ) ) ; } AArch64AsmBackend :: applyFixup ( Fixup , Data , DataSize , Value , IsPCRel ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool X86IntelAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : return printAsmMRegister ( MI -> getOperand ( OpNo ) , ExtraCode [ 0 ] ) ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


Emit : ( set TMP1 ( unspec : PRED_MODE [ PTRUE OP0 OP1 ] UNSPEC_COND_ < X1 > ) ) ( set TMP2 ( unspec : PRED_MODE [ PTRUE OP0 OP1 ] UNSPEC_COND_ < X2 > ) ) ( set TARGET ( and : PRED_MODE ( ior : PRED_MODE TMP1 TMP2 ) PTRUE ) ) where < Xi > is the operation associated with comparison CODEi .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned PPCTTI :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) const { if ( DisablePPCConstHoist ) return TargetTransformInfo :: getIntImmCost ( Opcode , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TCC_Basic ; return TCC_Free ; case Instruction :: And : RunFree = true ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TCC_Free ; } return PPCTTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool AArch64TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return true ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> static void aarch64_option_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; selected_tune = aarch64_get_tune_cpu ( ptr -> x_explicit_tune_core ) ; opts -> x_explicit_arch = ptr -> x_explicit_arch ; selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ; opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ; aarch64_override_options_internal ( opts ) ; } </s>

Implements TARGET_OPTION_RESTORE . Restore the backend codegen decisions using the information saved in PTR .


<s> const AArch64TargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> static void ix86_emit_restore_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return , true ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; unsigned int align = GET_MODE_ALIGNMENT ( V4SFmode ) ; mem = choose_baseaddr ( cfa_offset , & align ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; align = MIN ( GET_MODE_ALIGNMENT ( V4SFmode ) , align ) ; gcc_assert ( ! ( cfa_offset & ( align / BITS_PER_UNIT - 1 ) ) ) ; set_mem_align ( mem , align ) ; emit_insn ( gen_rtx_SET ( reg , mem ) ) ; ix86_add_cfa_restore_note ( NULL , reg , cfa_offset ) ; cfa_offset -= GET_MODE_SIZE ( V4SFmode ) ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from CFA - CFA_OFFSET .


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , class loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( ix86_unroll_only_small_loops && ! loop -> unroll ) { if ( loop -> ninsns <= ix86_cost -> small_unroll_ninsns ) return MIN ( nunroll , ix86_cost -> small_unroll_factor ) ; else return 1 ; } if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > 4 ) mem_count += 2 ; else mem_count += 1 ; } free ( bbs ) ; if ( mem_count && mem_count <= 32 ) return MIN ( nunroll , 32 / mem_count ) ; return nunroll ; } </s>

This function adjusts the unroll factor based on the hardware capabilities . For ex , bdver3 has a loop buffer which makes unrolling of smaller loops less important . This function decides the unroll factor using number of memory references ( value 32 is used ) as a heuristic .


<s> bool MipsAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo ) ; return false ; } </s>


Return an appropriate const instance of xlogue_layout based upon values in cfun- > machine and crtl .


"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> unsigned ARMBaseRegisterInfo :: getRARegister ( ) const { return ARM :: LR ; } </s>

This method should return the register where the return address can be found .


<s>
SDValue
ARM64TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
CCAssignFn
*
RetCC
=
CallConv
==
CallingConv
::
WebKit_JS
RetCC_ARM64_WebKit_JS
:
RetCC_ARM64_AAPCS
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
realRVLocIdx
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
,
++
realRVLocIdx
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
realRVLocIdx
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Arg
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
ARM64ISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool AArch64InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } else { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isIndirectBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static bool rs6000_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict ) { bool reg_offset_p = reg_offset_addressing_ok_p ( mode ) ; if ( VECTOR_MEM_ALTIVEC_P ( mode ) && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == - 16 ) x = XEXP ( x , 0 ) ; if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return 0 ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) ) return 1 ; if ( virtual_stack_registers_memory_p ( x ) ) return 1 ; if ( reg_offset_p && legitimate_small_data_p ( mode , x ) ) return 1 ; if ( reg_offset_p && legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return 1 ; if ( reg_offset_p && reg_addr [ mode ] . fused_toc && GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_FUSION_ADDIS ) return 1 ; if ( mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE ) return 0 ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == REG && ( XEXP ( x , 0 ) == virtual_stack_vars_rtx || XEXP ( x , 0 ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) return 1 ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return 1 ; if ( ! FLOAT128_2REG_P ( mode ) && ( ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) || ( TARGET_E500_DOUBLE && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , 1 ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , 1 ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) return 1 ; if ( reg_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return 1 ; return 0 ; } </s>

TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . On the RS/6000 , there are four valid address : a SYMBOL_REF that refers to a constant pool entry of an address ( or the sum of it plus a constant ) , a short ( 16-bit signed ) constant plus a register , the sum of two registers , or a register indirect , possibly with an auto-increment . For DFmode , DDmode and DImode with a constant plus register , we must ensure that both words are addressable or PowerPC64 with offset word aligned . For modes spanning multiple registers ( DFmode and DDmode in 32-bit GPRs , 32-bit DImode , TImode , TFmode , TDmode ) , indexed addressing can not be used because adjacent memory cells are accessed by adding word-sized offsets during assembly output .


<s> static rtx rs6000_spe_function_arg ( const CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type ) { int gregno = cum -> sysv_gregno ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == TFmode || mode == DCmode || mode == TCmode ) ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( mode == DFmode ) gregno += ( 1 - gregno ) & 1 ; if ( gregno + n_words - 1 > GP_ARG_MAX_REG ) return NULL_RTX ; return spe_build_register_parallel ( mode , gregno ) ; } if ( cum -> stdarg ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( n_words == 2 && ( gregno & 1 ) == 0 ) gregno += 1 ; if ( gregno + n_words - 1 <= GP_ARG_MAX_REG ) { rtx r1 , r2 ; machine_mode m = SImode ; r1 = gen_rtx_REG ( m , gregno ) ; r1 = gen_rtx_EXPR_LIST ( m , r1 , const0_rtx ) ; r2 = gen_rtx_REG ( m , gregno + 1 ) ; r2 = gen_rtx_EXPR_LIST ( m , r2 , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } else return NULL_RTX ; } else { if ( gregno <= GP_ARG_MAX_REG ) return gen_rtx_REG ( mode , gregno ) ; else return NULL_RTX ; } } </s>

Determine where to put a SIMD argument on the SPE .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_lo16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_ha16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_lo14"
,
16
,
14
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> rtx parallel_element ( rtx parallel_rtx , int nth ) { parallel_rtx = extract_pattern_from_insn ( parallel_rtx ) ; gcc_assert ( GET_CODE ( parallel_rtx ) == PARALLEL ) ; int len = parallel_elements ( parallel_rtx ) ; if ( nth >= 0 ) { if ( nth >= len ) return NULL_RTX ; return XVECEXP ( parallel_rtx , 0 , nth ) ; } else { if ( len + nth < 0 ) return NULL_RTX ; return XVECEXP ( parallel_rtx , 0 , len + nth ) ; } } </s>

Extract an rtx from a parallel rtx with index NTH . If NTH is a negative value , the function returns the last NTH rtx .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr * MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , MVT :: i64 ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI -> getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ; switch ( LQR ) { case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI -> killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( ! I -> hasOneUse ( ) ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const DataLayout & DL = I -> getModule ( ) -> getDataLayout ( ) ; EVT VT = getValueType ( DL , User -> getOperand ( 0 ) -> getType ( ) ) ; return ! ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( ISD :: FMA , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
if
(
DisableAddressingModeFolder
)
return
false
;
InstrInfo
=
MF
.
getSubtarget
<
MipsSubtarget
>
(
)
.
getInstrInfo
(
)
;
bool
modified
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
unsigned
NumIterations
=
0
;
while
(
foldMachineFunction
(
MF
,
MLI
,
MDT
)
)
{
modified
=
true
;
NumIterations
++
;
assert
(
NumIterations
<
1000
&&
"Infinite loop in CheriAddrModeFolder?"
)
;
}
if
(
modified
)
{
MF
.
verify
(
)
;
}
return
modified
;
}
</s>

runOnMachineFunction - Emit the function body .


"MMIX Internal: Last named vararg would not fit in a register"


<s>
void
mt_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
switch
(
code
)
{
case
'#'
:
if
(
dbr_sequence_length
(
)
==
0
)
fputs
(
"\n\tnop"
,
file
)
;
return
;
case
'H'
:
fprintf
(
file
,
"#%%hi16("
)
;
output_addr_const
(
file
,
x
)
;
fprintf
(
file
,
")"
)
;
return
;
case
'L'
:
fprintf
(
file
,
"#%%lo16("
)
;
output_addr_const
(
file
,
x
)
;
fprintf
(
file
,
")"
)
;
return
;
case
'N'
:
fprintf
(
file
,
"#%ld"
,
~
INTVAL
(
x
)
)
;
return
;
case
'z'
:
if
(
GET_CODE
(
x
)
==
CONST_INT
&&
INTVAL
(
x
)
==
0
)
{
fputs
(
reg_names
[
GPR_R0
]
,
file
)
;
return
;
}
case
0
:
break
;
default
:
fprintf
(
file
,
"unknown code"
)
;
return
;
}
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
fputs
(
reg_names
[
REGNO
(
x
)
]
,
file
)
;
break
;
case
CONST
:
case
CONST_INT
:
fprintf
(
file
,
"#%ld"
,
INTVAL
(
x
)
)
;
break
;
case
MEM
:
mt_print_operand_address
(
file
,
XEXP
(
x
,
0
)
)
;
break
;
case
LABEL_REF
:
case
SYMBOL_REF
:
output_addr_const
(
file
,
x
)
;
break
;
default
:
fprintf
(
file
,
"Uknown code: %d"
,
GET_CODE
(
x
)
)
;
break
;
}
return
;
}
</s>


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! Subtarget -> hasVFP3Base ( ) ) return false ; if ( VT == MVT :: f16 && Subtarget -> hasFullFP16 ( ) ) return ARM_AM :: getFP16Imm ( Imm ) != - 1 ; if ( VT == MVT :: f32 && Subtarget -> hasFullFP16 ( ) && ARM_AM :: getFP32FP16Imm ( Imm ) != - 1 ) return true ; if ( VT == MVT :: f32 ) return ARM_AM :: getFP32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 && Subtarget -> hasFP64 ( ) ) return ARM_AM :: getFP64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static inline bool ix86_using_red_zone ( void ) { return TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI ; } </s>


<s> const unsigned * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned SingleFloatOnlyCalleeSavedRegs [ ] = { Mips :: S0 , Mips :: S1 , Mips :: S2 , Mips :: S3 , Mips :: S4 , Mips :: S5 , Mips :: S6 , Mips :: S7 , Mips :: F20 , Mips :: F21 , Mips :: F22 , Mips :: F23 , Mips :: F24 , Mips :: F25 , Mips :: F26 , Mips :: F27 , Mips :: F28 , Mips :: F29 , Mips :: F30 , 0 } ; static const unsigned BitMode32CalleeSavedRegs [ ] = { Mips :: S0 , Mips :: S1 , Mips :: S2 , Mips :: S3 , Mips :: S4 , Mips :: S5 , Mips :: S6 , Mips :: S7 , Mips :: F20 , Mips :: F22 , Mips :: F24 , Mips :: F26 , Mips :: F28 , Mips :: F30 , 0 } ; if ( Subtarget . isSingleFloat ( ) ) return SingleFloatOnlyCalleeSavedRegs ; else return BitMode32CalleeSavedRegs ; } </s>


<s> const SparcSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
bool
ARM64AddressTypePromotion
::
runOnFunction
(
Function
&
F
)
{
if
(
!
EnableAddressTypePromotion
||
F
.
isDeclaration
(
)
)
return
false
;
Func
=
&
F
;
ConsideredSExtType
=
Type
::
getInt64Ty
(
Func
->
getContext
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"*** "
<<
getPassName
(
)
<<
": "
<<
Func
->
getName
(
)
<<
'\n'
)
;
Instructions
SExtInsts
;
analyzeSExtension
(
SExtInsts
)
;
return
propagateSignExtension
(
SExtInsts
)
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
bool
PPCDarwinAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
F
)
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
assert
(
0
&&
"Unknown linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
InternalLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
O
<<
"\t.weak_definition\t"
<<
CurrentFnName
<<
'\n'
;
break
;
}
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
EmitAlignment
(
F
->
hasFnAttr
(
Attribute
::
OptimizeForSize
)
2
:
4
,
F
)
;
O
<<
CurrentFnName
<<
":\n"
;
DW
->
BeginFunction
(
&
MF
)
;
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
;
if
(
++
I
==
MF
.
end
(
)
&&
MF
.
front
(
)
.
empty
(
)
)
O
<<
"\tnop\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
IE
=
I
->
end
(
)
;
II
!=
IE
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableMips6432 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } Result = decodeInstruction ( DecoderTableMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( X86 :: RSP ) ; Reserved . set ( X86 :: ESP ) ; Reserved . set ( X86 :: SP ) ; Reserved . set ( X86 :: SPL ) ; Reserved . set ( X86 :: RIP ) ; Reserved . set ( X86 :: EIP ) ; Reserved . set ( X86 :: IP ) ; if ( hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; Reserved . set ( X86 :: EBP ) ; Reserved . set ( X86 :: BP ) ; Reserved . set ( X86 :: BPL ) ; } Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void mips_restore_reg ( rtx reg , rtx mem ) { if ( TARGET_MIPS16 && REGNO ( reg ) == GP_REG_FIRST + 31 ) reg = gen_rtx_REG ( GET_MODE ( reg ) , 7 ) ; if ( TARGET_MIPS16 && ! M16_REG_P ( REGNO ( reg ) ) ) { emit_move_insn ( MIPS_EPILOGUE_TEMP ( GET_MODE ( reg ) ) , mem ) ; emit_move_insn ( reg , MIPS_EPILOGUE_TEMP ( GET_MODE ( reg ) ) ) ; } else emit_move_insn ( reg , mem ) ; } </s>

Emit instructions to restore register REG from slot MEM .


<s> void AArch64TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { AArch64FunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < AArch64FunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> bool n8_consumed_by_ex_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( INSN_CODE ( consumer ) == CODE_FOR_divmodsi4 || INSN_CODE ( consumer ) == CODE_FOR_udivmodsi4 ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_BRANCH : use_rtx = extract_branch_condition_rtx ( consumer ) ; break ; case TYPE_STORE : if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; default : gcc_unreachable ( ) ; } return reg_overlap_p ( def_reg , use_rtx ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> static int ix86_multiplication_cost ( const struct processor_costs * cost , enum machine_mode mode ) { machine_mode inner_mode = mode ; if ( VECTOR_MODE_P ( mode ) ) inner_mode = GET_MODE_INNER ( mode ) ; if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) return inner_mode == DFmode ? cost -> mulsd : cost -> mulss ; else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fmul ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> mulsd : cost -> mulss , true ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { if ( TARGET_AVX512DQ ) return ix86_vec_cost ( mode , cost -> mulss , true ) ; if ( mode == V16QImode || mode == V32QImode ) { int extra = 11 ; if ( TARGET_XOP && mode == V16QImode ) extra = 5 ; else if ( TARGET_SSSE3 ) extra = 6 ; return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * extra , true ) ; } else if ( mode == V2DImode || mode == V4DImode ) { if ( TARGET_XOP && mode == V2DImode ) return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * 3 , true ) ; else return ix86_vec_cost ( mode , cost -> mulss * 3 + cost -> sse_op * 5 , true ) ; } else if ( mode == V4SImode && ! ( TARGET_SSE4_1 || TARGET_AVX ) ) return ix86_vec_cost ( mode , cost -> mulss * 2 + cost -> sse_op * 5 , true ) ; else return ix86_vec_cost ( mode , cost -> mulss , true ) ; } else return ( cost -> mult_init [ MODE_INDEX ( mode ) ] + cost -> mult_bit * 7 ) ; } </s>


<s>
void
xstormy16_asm_output_aligned_common
(
FILE
*
stream
,
tree
decl
,
const
char
*
name
,
int
size
,
int
align
,
int
global
)
{
rtx
mem
=
decl
==
NULL_TREE
NULL_RTX
:
DECL_RTL
(
decl
)
;
rtx
symbol
;
if
(
mem
!=
NULL_RTX
&&
MEM_P
(
mem
)
&&
GET_CODE
(
symbol
=
XEXP
(
mem
,
0
)
)
==
SYMBOL_REF
&&
SYMBOL_REF_FLAGS
(
symbol
)
&
SYMBOL_FLAG_XSTORMY16_BELOW100
)
{
const
char
*
name2
;
int
p2align
=
0
;
switch_to_section
(
bss100_section
)
;
while
(
align
>
8
)
{
align
/=
2
;
p2align
++
;
}
name2
=
default_strip_name_encoding
(
name
)
;
if
(
global
)
fprintf
(
stream
,
"\t.globl\t%s\n"
,
name2
)
;
if
(
p2align
)
fprintf
(
stream
,
"\t.p2align %d\n"
,
p2align
)
;
fprintf
(
stream
,
"\t.type\t%s, @object\n"
,
name2
)
;
fprintf
(
stream
,
"\t.size\t%s, %d\n"
,
name2
,
size
)
;
fprintf
(
stream
,
"%s:\n\t.space\t%d\n"
,
name2
,
size
)
;
return
;
}
if
(
!
global
)
{
fprintf
(
stream
,
"\t.local\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
fprintf
(
stream
,
"\t.comm\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
",%u,%u\n"
,
size
,
align
/
BITS_PER_UNIT
)
;
}
</s>

The purpose of this function is to override the default behavior of BSS objects . Normally , they go into .bss or .sbss via `` .common '' directives , but we need to override that and put them in .bss_below100 . We ca n't just use a section override ( like we do for .data_below100 ) , because that makes them initialized rather than uninitialized .


<s> bool PPCTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_lvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_lvewx : VT = MVT :: i32 ; break ; case Intrinsic :: ppc_vsx_lxvd2x : VT = MVT :: v2f64 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = Align ( 1 ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_stvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_stvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_stvewx : VT = MVT :: i32 ; break ; case Intrinsic :: ppc_vsx_stxvd2x : VT = MVT :: v2f64 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = Align ( 1 ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static int csky_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int cost , unsigned int dw ATTRIBUTE_UNUSED ) { if ( dep_type == REG_DEP_ANTI || dep_type == REG_DEP_OUTPUT ) return 0 ; else if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { enum attr_type insn_type = get_attr_type ( insn ) ; if ( CSKY_TARGET_ARCH ( CK803 ) ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_STORE ) { rtx pattern = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; rtx addr = ( insn_type == TYPE_LOAD ? SET_SRC ( pattern ) : SET_DEST ( pattern ) ) ; enum rtx_code code = GET_CODE ( addr ) ; if ( code == ZERO_EXTEND || code == SIGN_EXTEND ) addr = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( addr ) == MEM ) ; rtx base = XEXP ( addr , 0 ) ; rtx reg = NULL_RTX ; if ( REG_P ( base ) ) reg = base ; if ( GET_CODE ( base ) == PLUS && GET_CODE ( XEXP ( base , 0 ) ) == REG ) reg = XEXP ( base , 0 ) ; if ( ( reg != NULL_RTX ) && reg_set_p ( reg , PATTERN ( dep ) ) ) return 2 ; } } else if ( CSKY_TARGET_ARCH ( CK802 ) ) { if ( ( insn_type == TYPE_CALL_JSR || insn_type == TYPE_BRANCH_JMP ) && get_attr_type ( dep ) != TYPE_LOAD ) return 1 ; if ( insn_type == TYPE_LOAD || insn_type == TYPE_STORE ) { rtx pattern = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; rtx addr = ( insn_type == TYPE_LOAD ? SET_SRC ( pattern ) : SET_DEST ( pattern ) ) ; enum rtx_code code = GET_CODE ( addr ) ; if ( code == ZERO_EXTEND || code == SIGN_EXTEND ) addr = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( addr ) == MEM ) ; rtx base = XEXP ( addr , 0 ) ; rtx reg = NULL_RTX ; if ( REG_P ( base ) ) reg = base ; if ( GET_CODE ( base ) == PLUS && GET_CODE ( XEXP ( base , 0 ) ) == REG ) reg = XEXP ( base , 0 ) ; if ( ( reg != NULL_RTX ) && reg_set_p ( reg , PATTERN ( dep ) ) && get_attr_type ( dep ) != TYPE_LOAD ) return 1 ; if ( insn_type == TYPE_STORE && reg_referenced_p ( SET_SRC ( pattern ) , PATTERN ( dep ) ) ) return 1 ; } } } return cost ; } </s>

This function implements the target macro TARGET_SCHED_ADJUST_COST . It corrects the value of COST based on the relationship between INSN and DEP through the dependence DEP_TYPE . It returns the new value .


<s> static rtx_insn * vax_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , VAX_PSL_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , VAX_PSL_REGNUM ) ; return NULL ; } </s>

Mark PSL as clobbered for compatibility with the CC0 representation .


<s>
const
char
*
nds32_output_casesi_pc_relative
(
rtx
*
operands
)
{
machine_mode
mode
;
rtx
diff_vec
;
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
1
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
output_asm_insn
(
"la\t$ta, %l1"
,
operands
)
;
mode
=
GET_MODE
(
diff_vec
)
;
switch
(
mode
)
{
case
E_QImode
:
output_asm_insn
(
"lb\t%2, [$ta + %0 << 0]"
,
operands
)
;
break
;
case
E_HImode
:
output_asm_insn
(
"lh\t%2, [$ta + %0 << 1]"
,
operands
)
;
break
;
case
E_SImode
:
output_asm_insn
(
"lw\t%2, [$ta + %0 << 2]"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
output_asm_insn
(
"add\t$ta, %2, $ta"
,
operands
)
;
if
(
TARGET_16_BIT
)
return
"jr5\t$ta"
;
else
return
"jr\t$ta"
;
}
</s>

Function to generate PC relative jump table . Refer to nds32.md for more details . The following is the sample for the case that diff value can be presented in '.short ' size . addi $ r1 , $ r1 , - ( case_lower_bound ) slti $ ta , $ r1 , ( case_number ) beqz $ ta , .L_skip_label la $ ta , .L35 ! get jump table address lh $ r1 , [ $ ta + $ r1 < < 1 ] ! load symbol diff from jump table entry addi $ ta , $ r1 , $ ta jr5 $ ta ! jump table entry L35 : .short .L25-.L35 .short .L26-.L35 .short .L27-.L35 .short .L28-.L35 .short .L29-.L35 .short .L30-.L35 .short .L31-.L35 .short .L32-.L35 .short .L33-.L35 .short .L34-.L35


<s> void ix86_split_copysign_var ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , scratch , op0 , op1 , mask , nmask , x ; dest = operands [ 0 ] ; scratch = operands [ 1 ] ; op0 = operands [ 2 ] ; op1 = operands [ 3 ] ; nmask = operands [ 4 ] ; mask = operands [ 5 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; if ( rtx_equal_p ( op0 , op1 ) ) { emit_move_insn ( dest , op0 ) ; return ; } if ( REG_P ( mask ) && REGNO ( dest ) == REGNO ( mask ) ) { gcc_assert ( REGNO ( op1 ) == REGNO ( scratch ) ) ; x = gen_rtx_AND ( vmode , scratch , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; dest = mask ; op0 = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_NOT ( vmode , dest ) ; x = gen_rtx_AND ( vmode , x , op0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } else { if ( REGNO ( op1 ) == REGNO ( scratch ) ) { x = gen_rtx_AND ( vmode , scratch , mask ) ; } else { gcc_assert ( REGNO ( mask ) == REGNO ( scratch ) ) ; op1 = simplify_gen_subreg ( vmode , op1 , mode , 0 ) ; x = gen_rtx_AND ( vmode , scratch , op1 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; if ( REGNO ( op0 ) == REGNO ( dest ) ) { dest = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , nmask ) ; } else { gcc_assert ( REGNO ( nmask ) == REGNO ( dest ) ) ; dest = nmask ; op0 = simplify_gen_subreg ( vmode , op0 , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , op0 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } x = gen_rtx_IOR ( vmode , dest , scratch ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is variable , so we have to do two masks .


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = "ve" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( F . getFunction ( ) ) ) return false ; const SystemZSubtarget & ST = F . getSubtarget < SystemZSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( * TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>


"MIPS16 PIC for ABIs other than o32 and o64"

"%<hard-float%> MIPS16 code for ABIs other than o32 and o64"

Set up the target-dependent global state for ISA mode COMPRESSION_MODE , which is either MASK_MIPS16 or MASK_MICROMIPS .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
int
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> void aarch64_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode , cmp_mode ; typedef rtx ( * gen_cas_fn ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; int idx ; gen_cas_fn gen ; const gen_cas_fn split_cas [ ] = { gen_aarch64_compare_and_swapqi , gen_aarch64_compare_and_swaphi , gen_aarch64_compare_and_swapsi , gen_aarch64_compare_and_swapdi } ; const gen_cas_fn atomic_cas [ ] = { gen_aarch64_compare_and_swapqi_lse , gen_aarch64_compare_and_swaphi_lse , gen_aarch64_compare_and_swapsi_lse , gen_aarch64_compare_and_swapdi_lse } ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; cmp_mode = mode ; if ( is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : cmp_mode = SImode ; rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : case E_DImode : if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( cmp_mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case E_QImode : idx = 0 ; break ; case E_HImode : idx = 1 ; break ; case E_SImode : idx = 2 ; break ; case E_DImode : idx = 3 ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_LSE ) gen = atomic_cas [ idx ] ; else gen = split_cas [ idx ] ; emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } </s>