<s> void Mips16InstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildAddiuSpImm ( MBB , I , Amount ) ; else adjustStackPtrBigUnrestricted ( SP , Amount , MBB , I ) ; } </s>


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> unsigned Cpu0MachineFunctionInfo :: getGlobalBaseReg ( ) { return GlobalBaseReg = Cpu0 :: GP ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void loongarch_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , temp1 , temp2 , fnaddr ; rtx_insn * insn ; bool use_sibcall_p ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = XEXP ( DECL_RTL ( function ) , 0 ) ; use_sibcall_p = const_call_insn_operand ( fnaddr , Pmode ) ; temp1 = gen_rtx_REG ( Pmode , 12 ) ; temp2 = gen_rtx_REG ( Pmode , 13 ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != 0 ) { rtx offset = GEN_INT ( delta ) ; if ( ! IMM12_OPERAND ( delta ) ) { loongarch_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != 0 ) { rtx addr ; loongarch_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = loongarch_add_offset ( temp2 , temp1 , vcall_offset ) ; loongarch_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } if ( use_sibcall_p ) { insn = emit_call_insn ( gen_sibcall_internal ( fnaddr , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; } else { loongarch_emit_move ( temp1 , fnaddr ) ; emit_jump_insn ( gen_indirect_jump ( temp1 ) ) ; } insn = get_insns ( ) ; split_all_insns_noflow ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; } </s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Generate rtl rather than asm text in order to avoid duplicating too much logic from elsewhere .


<s> unsigned AArch64InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return 0 ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { if ( BytesRemoved ) * BytesRemoved = 4 ; return 1 ; } -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( BytesRemoved ) * BytesRemoved = 4 ; return 1 ; } I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved = 8 ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"X86 Support for return instruction protection"

getPassName - Return a nice clean name for a pass .


<s> const MCExpr * ARMElfTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_ARM_TLSLDO , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
OPTION_SET_P
(
rs6000_cpu_index
)
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
OPTION_SET_P
(
rs6000_tune_index
)
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
rs6000_machine
=
rs6000_machine_from_flags
(
)
;
emit_asm_machine
(
)
;
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
}
</s>

Do anything needed at the start of the asm file .

rs6000
80
"\n%s rs6000/powerpc options:"
0
0
"%s --with-cpu=%s"
""
"%s -mcpu=%s"
""
"%s -mtune=%s"
""
"%s PPC405CR_ERRATUM77"
""
"%s -msdata=none"
""
"%s -msdata=data"
""
"%s -msdata=sysv"
""
"%s -msdata=eabi"
""
"%s -G %d"
""
"\t.abiversion 2\n"


<s> static void * ia64_alloc_sched_context ( void ) { return xmalloc ( sizeof ( struct _ia64_sched_context ) ) ; } </s>


<s> EVT ARMTargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> unsigned SparcAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { SparcOperand & Op = ( SparcOperand & ) GOp ; if ( Op . isFloatOrDoubleReg ( ) ) { switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op . isFloatReg ( ) || SparcOperand :: MorphToDoubleReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( SparcOperand :: MorphToQuadReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Sparc Sparc Sparc Sparc SparcOperand::MorphToDoubleReg SparcOperand::MorphToQuadReg


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tSpill
0


<s> tree function_resolver :: lookup_form ( mode_suffix_index mode , type_suffix_index type0 , type_suffix_index type1 ) { type_suffix_pair types = { type0 , type1 } ; function_instance instance ( base_name , base , shape , mode , types , pred ) ; registered_function * rfn = function_table -> find_with_hash ( instance , instance . hash ( ) ) ; return rfn ? rfn -> decl : NULL_TREE ; } </s>

Silently check whether there is an instance of the function with the mode suffix given by MODE and the type suffixes given by TYPE0 and TYPE1 . Return its function decl if so , otherwise return null .


<s> int rs6000_loop_align ( rtx label ) { basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops_log ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > 4 && ninsns <= 8 && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 ) ) return 5 ; else return align_loops_log ; } </s>


<s> static void mips_emit_loadgp ( void ) { if ( TARGET_ABICALLS && TARGET_NEWABI && cfun -> machine -> global_pointer > 0 ) { rtx addr , offset , incoming_address ; addr = XEXP ( DECL_RTL ( current_function_decl ) , 0 ) ; offset = mips_unspec_address ( addr , SYMBOL_GOTOFF_LOADGP ) ; incoming_address = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; emit_insn ( gen_loadgp ( offset , incoming_address ) ) ; if ( ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_loadgp_blockage ( ) ) ; } } </s>

If we 're generating n32 or n64 abicalls , emit instructions to set up the global pointer .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; unsigned Flags = MI -> getFlags ( ) ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\t" ; if ( ! ( TSFlags & X86II :: LOCK ) && Flags & X86 :: IP_HAS_LOCK ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && ( STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) ) { MCInst Data32MI ( * MI ) ; Data32MI . setOpcode ( X86 :: DATA32_PREFIX ) ; printInstruction ( & Data32MI , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
void
AArch64RegisterInfo
::
getOffsetOpcodes
(
const
StackOffset
&
Offset
,
SmallVectorImpl
<
uint64_t
>
&
Ops
)
const
{
assert
(
Offset
.
getScalable
(
)
%
2
==
0
&&
"Invalid frame offset"
)
;
DIExpression
::
appendOffset
(
Ops
,
Offset
.
getFixed
(
)
)
;
unsigned
VG
=
getDwarfRegNum
(
AArch64
::
VG
,
true
)
;
int64_t
VGSized
=
Offset
.
getScalable
(
)
/
2
;
if
(
VGSized
>
0
)
{
Ops
.
push_back
(
dwarf
::
DW_OP_constu
)
;
Ops
.
push_back
(
VGSized
)
;
Ops
.
append
(
{
dwarf
::
DW_OP_bregx
,
VG
,
0ULL
}
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_mul
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_plus
)
;
}
else
if
(
VGSized
<
0
)
{
Ops
.
push_back
(
dwarf
::
DW_OP_constu
)
;
Ops
.
push_back
(
VGSized
)
;
Ops
.
append
(
{
dwarf
::
DW_OP_bregx
,
VG
,
0ULL
}
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_mul
)
;
Ops
.
push_back
(
dwarf
::
DW_OP_minus
)
;
}
}
</s>

Gets the DWARF expression opcodes for Offset .


<s>
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


<s> const uint16_t * DCPU16RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const Function * F = MF -> getFunction ( ) ; static const uint16_t CalleeSavedRegs [ ] = { DCPU16 :: X , DCPU16 :: Y , DCPU16 :: Z , DCPU16 :: I , DCPU16 :: J , 0 } ; static const uint16_t CalleeSavedRegsIntr [ ] = { DCPU16 :: EX , DCPU16 :: B , DCPU16 :: C , DCPU16 :: X , DCPU16 :: Y , DCPU16 :: Z , DCPU16 :: I , DCPU16 :: J , 0 } ; return ( F -> getCallingConv ( ) == CallingConv :: DCPU16_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ; } </s>


<s> bool isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == MVT :: f64 && Subtarget -> hasSSE2 ( ) ) || ( VT == MVT :: f32 && Subtarget -> hasSSE1 ( ) ) || ( VT == MVT :: f16 && Subtarget -> hasFP16 ( ) ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC


<s> bool X86TTIImpl :: isLegalBroadcastLoad ( Type * ElementTy , unsigned NumElements ) const { return ST -> hasSSE3 ( ) && NumElements == 2 && ElementTy == Type :: getDoubleTy ( ElementTy -> getContext ( ) ) ; } </s>

\Returns true if the target supports broadcasting a load to a vector of type < NumElements x ElementTy > .


<s> static std :: unique_ptr < MipsOperand > CreateReg ( unsigned Index , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = make_unique < MipsOperand > ( k_RegisterIndex , Parser ) ; Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool nds32_n9_3r2w_mm_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( INSN_CODE ( producer ) == CODE_FOR_divmodsi4 || INSN_CODE ( producer ) == CODE_FOR_udivmodsi4 ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , 0 ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , 1 ) ) ; return ( n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg1 ) || n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg ) ; } </s>


<s> unsigned getMaxInlineSizeThreshold ( ) const { return 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> int AArch64AsmParser :: tryParseRegister ( ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = matchRegisterNameAlias ( lowerCase , RegKind :: Scalar ) ; if ( RegNum == 0 ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "fp" , AArch64 :: FP ) . Case ( "lr" , AArch64 :: LR ) . Case ( "x31" , AArch64 :: XZR ) . Case ( "w31" , AArch64 :: WZR ) . Default ( 0 ) ; if ( RegNum == 0 ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> bool ARM64TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! EnableARM64TailCalls ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool isThumb ( ) const { return ( STI . getFeatureBits ( ) & ARM :: ModeThumb ) != 0 ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> unsigned MipsFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? 0 : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return materializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> struct xstormy16_stack_layout xstormy16_compute_stack_layout ( void ) { struct xstormy16_stack_layout layout ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; layout . locals_size = get_frame_size ( ) ; layout . register_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) layout . register_save_size += UNITS_PER_WORD ; if ( current_function_stdarg ) layout . stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ; else layout . stdarg_save_size = 0 ; layout . frame_size = ( layout . locals_size + layout . register_save_size + layout . stdarg_save_size ) ; if ( current_function_args_size <= 2048 && current_function_args_size != - 1 ) { if ( layout . frame_size + INCOMING_FRAME_SP_OFFSET + current_function_args_size <= 2048 ) layout . fp_minus_ap = layout . frame_size + INCOMING_FRAME_SP_OFFSET ; else layout . fp_minus_ap = 2048 - current_function_args_size ; } else layout . fp_minus_ap = ( layout . stdarg_save_size + layout . register_save_size + INCOMING_FRAME_SP_OFFSET ) ; layout . sp_minus_fp = ( layout . frame_size + INCOMING_FRAME_SP_OFFSET - layout . fp_minus_ap ) ; layout . first_local_minus_ap = layout . sp_minus_fp - layout . locals_size ; return layout ; } </s>


<s> static bool ck807_ck810_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case MULT : if ( REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , 1 ) ) ; if ( val % 2 == 0 && val < 0xffffffff && val > 0 ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } return false ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 3 ) ; return true ; default : return false ; } } </s>

TARGET_RTX_COSTS helper for ck807/ck810 arches .


<s> bool arm_pad_reg_upward ( machine_mode mode , tree type , int first ATTRIBUTE_UNUSED ) { if ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN ) { if ( type ) { if ( ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || FIXED_POINT_TYPE_P ( type ) ) && int_size_in_bytes ( type ) <= 4 ) return true ; } else { if ( ( COMPLEX_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) && GET_MODE_SIZE ( mode ) <= 4 ) return true ; } } return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . For non-AAPCS , return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does . For AAPCS , small aggregates and small complex types are always padded upwards .


<s> void CAHPPassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool MipsMulMulBugFix :: runOnMachineFunction ( MachineFunction & MF ) { const MipsInstrInfo & MipsII = * static_cast < const MipsInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= fixMulMulBB ( MBB , MipsII ) ; return Modified ; } </s>


<s> static rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( "no_split_stack" , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = 1 ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , 12 ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } return plus_constant ( Pmode , cfun -> machine -> split_stack_arg_pointer , FIRST_PARM_OFFSET ( current_function_decl ) ) ; } return virtual_incoming_args_rtx ; } </s>

Return the internal arg pointer used for function incoming arguments . When -fsplit-stack , the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls and suchlike . We 'd really like to use a pseudo here for the internal arg pointer but data-flow analysis is not prepared to accept pseudos as live at the beginning of a function .


<s> static sbitmap aarch64_get_separate_components ( void ) { sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { machine_mode mode = aarch64_reg_save_mode ( regno ) ; if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) continue ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( flag_stack_clash_protection && maybe_ne ( cfun -> machine -> frame . below_hard_fp_saved_regs_size , 0 ) && known_eq ( offset , 0 ) ) continue ; if ( frame_pointer_needed ) offset -= cfun -> machine -> frame . below_hard_fp_saved_regs_size ; else offset += crtl -> outgoing_args_size ; if ( aarch64_sve_mode_p ( mode ) ? offset_9bit_signed_scaled_p ( mode , offset ) : offset_12bit_unsigned_scaled_p ( mode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( cfun -> machine -> frame . spare_pred_reg != INVALID_REGNUM ) bitmap_clear_bit ( components , cfun -> machine -> frame . spare_pred_reg ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg2 ) ; if ( reg1 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg1 ) ; bitmap_clear_bit ( components , LR_REGNUM ) ; bitmap_clear_bit ( components , SP_REGNUM ) ; return components ; } </s>


<s> bool hasAndNot ( SDValue Y ) const override { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return hasAndNotCompare ( Y ) ; return VT . getSizeInBits ( ) >= 64 ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> void DLXPassConfig :: addPreSched2 ( ) { addPass ( createDLXMemAluCombinerPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static void mt_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { int regno ; int regs = MT_NUM_ARG_REGS - * cum ; * pretend_size = regs < 0 ? 0 : GET_MODE_SIZE ( SImode ) * regs ; if ( no_rtl ) return ; for ( regno = * cum ; regno < MT_NUM_ARG_REGS ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , FIRST_ARG_REGNUM + regno ) ; rtx slot = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( SImode , ARG_POINTER_REGNUM ) , GEN_INT ( UNITS_PER_WORD * regno ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , slot ) , reg ) ; } } </s>

Do what is necessary for ` va_start ' . We look at the current function to determine if stdarg or varargs is used and return the address of the first unnamed parameter .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool rs6000_reg_live_or_pic_offset_p ( int reg ) { return ( ( ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) ) && ( ! call_used_regs [ reg ] || ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) || ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != 0 ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) ) ) ) ; } </s>

Determine whether the gp REG is really used .


<s> unsigned PPCInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { if ( ! ItinData || UseOldLatencyCalc ) return PPCGenInstrInfo :: getInstrLatency ( ItinData , MI , PredCost ) ; unsigned Latency = 1 ; unsigned DefClass = MI . getDesc ( ) . getSchedClass ( ) ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isImplicit ( ) ) continue ; int Cycle = ItinData -> getOperandCycle ( DefClass , i ) ; if ( Cycle < 0 ) continue ; Latency = std :: max ( Latency , ( unsigned ) Cycle ) ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


<s> bool X86PassConfig :: addPreISel ( ) { Triple TT ( TM -> getTargetTriple ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86 ) addPass ( createX86WinEHStatePass ( ) ) ; return true ; } </s>


"insertBranch must not be told to insert a fallthrough"

"CJG branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr : return selectGetElementPtr ( I ) ; case Instruction :: AtomicCmpXchg : return selectAtomicCmpXchg ( cast < AtomicCmpXchgInst > ( I ) ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; ( void ) & CC_AArch64_DarwinPCS_VarArg ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> static bool is_microcoded_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_cpu_attr == CPU_CELL ) return get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ; if ( rs6000_sched_groups && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_update ( insn ) == UPDATE_YES && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) || ( ( type == TYPE_LOAD || type == TYPE_STORE ) && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) || type == TYPE_MFCR ) return true ; } return false ; } </s>

The function returns a true if INSN is microcoded . Return false otherwise .


<s> static bool ix86_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const machine_mode mode = type_natural_mode ( type , NULL , true ) ; HOST_WIDE_INT size ; if ( TARGET_64BIT ) { if ( ix86_function_type_abi ( fntype ) == MS_ABI ) { size = int_size_in_bytes ( type ) ; if ( ( ! type || VECTOR_INTEGER_TYPE_P ( type ) || INTEGRAL_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( SCALAR_INT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) && ! COMPLEX_MODE_P ( mode ) && ( GET_MODE_SIZE ( mode ) == 16 || size == 16 ) ) return false ; return size != 1 && size != 2 && size != 4 && size != 8 ; } else { int needed_intregs , needed_sseregs ; return examine_argument ( mode , type , 1 , & needed_intregs , & needed_sseregs ) ; } } else { size = int_size_in_bytes ( type ) ; if ( TARGET_IAMCU ) return VECTOR_MODE_P ( mode ) || size < 0 || size > 8 ; if ( mode == BLKmode ) return true ; if ( MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P ( type ) && size <= 8 ) return false ; if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { if ( size < 8 ) return false ; if ( size == 8 ) return TARGET_VECT8_RETURNS || ! TARGET_MMX ; if ( size == 16 ) return ! TARGET_SSE ; if ( size == 32 ) return ! TARGET_AVX ; if ( size == 64 ) return ! TARGET_AVX512F ; } if ( mode == XFmode ) return false ; if ( size > 12 ) return true ; gcc_assert ( mode != OImode ) ; return false ; } } </s>

Return false iff type is returned in memory .


<s> static unsigned getFramePointerSaveOffset ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI ) return isPPC64 ? 40 : 20 ; return - 4U ; } </s>

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
}
</s>

ARM
ARM::tMOVr
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"


<s> static pad_direction arm_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! TARGET_AAPCS_BASED ) return default_function_arg_padding ( mode , type ) ; if ( type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P ( type ) ) return PAD_DOWNWARD ; return PAD_UPWARD ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING ; return PAD_UPWARD if the lowest byte of a stack argument has useful data . For legacy APCS ABIs we use the default . For AAPCS based ABIs small aggregate types are placed in the lowest memory address .


<s>
uint64_t
SystemZMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
uint64_t
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unexpected operand type!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

SystemZ
SystemZ
"Unexpected operand type!"


<s> bool MINA32PassConfig :: addInstSelector ( ) { addPass ( createMINA32ISelDag ( getMINA32TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , const_tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = DECL_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; machine_mode mode ; if ( ftype == error_mark_node ) continue ; mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && tree_fits_uhwi_p ( bit_position ( f ) ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode ) ) { unsigned n_fpreg = ( GET_MODE_SIZE ( mode ) + 7 ) >> 3 ; switch ( mode ) { case SCmode : mode = SFmode ; break ; case DCmode : mode = DFmode ; break ; case TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + 1 ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack = 1 ; } rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( FLOAT128_2REG_P ( mode ) ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


<s> void MipsTargetStreamer :: emitGPRestore ( int Offset , SMLoc IDLoc , const MCSubtargetInfo * STI ) { emitLoadWithImmOffset ( Mips :: LW , GPReg , Mips :: SP , Offset , GPReg , IDLoc , STI ) ; } </s>

Emit the $ gp restore operation for .cprestore .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static void vr4130_avoid_branch_rt_conflict ( rtx insn ) { rtx first , second ; first = SEQ_BEGIN ( insn ) ; second = SEQ_END ( insn ) ; if ( JUMP_P ( first ) && NONJUMP_INSN_P ( second ) && GET_CODE ( PATTERN ( first ) ) == SET && GET_CODE ( SET_DEST ( PATTERN ( first ) ) ) == PC && GET_CODE ( SET_SRC ( PATTERN ( first ) ) ) == IF_THEN_ELSE ) { rtx cond = XEXP ( SET_SRC ( PATTERN ( first ) ) , 0 ) ; if ( ( GET_CODE ( cond ) == EQ || GET_CODE ( cond ) == NE ) && REG_P ( XEXP ( cond , 0 ) ) && REG_P ( XEXP ( cond , 1 ) ) && reg_referenced_p ( XEXP ( cond , 1 ) , PATTERN ( second ) ) && ! reg_referenced_p ( XEXP ( cond , 0 ) , PATTERN ( second ) ) ) { rtx tmp = XEXP ( cond , 0 ) ; XEXP ( cond , 0 ) = XEXP ( cond , 1 ) ; XEXP ( cond , 1 ) = tmp ; } } } </s>

The VR4130 pipeline issues aligned pairs of instructions together , but it stalls the second instruction if it depends on the first . In order to cut down the amount of logic required , this dependence check is not based on a full instruction decode . Instead , any non-SPECIAL instruction is assumed to modify the register specified by bits 20-16 ( which is usually the `` rt '' field ) . In beq , beql , bne and bnel instructions , the rt field is actually an input , so we can end up with a false dependence between the branch and its delay slot . If this situation occurs in instruction INSN , try to avoid it by swapping rs and rt .


<s> static bool ix86_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = FLAGS_REG ; * p2 = FPSR_REG ; return true ; } </s>

Return the fixed registers used for condition codes .


<s> bool rs6000_is_valid_and_mask ( rtx mask , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; if ( mode == DImode ) return ( ne == 0 || nb == 63 || ( nb < 32 && ne <= nb ) ) ; if ( mode == SImode ) return ( nb < 32 && ne < 32 ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwinm , rldicl , or rldicr instruction , to implement an AND with it in mode MODE .


<s> static bool sparc_strict_argument_naming ( cumulative_args_t ca ATTRIBUTE_UNUSED ) { return TARGET_ARCH64 ? true : false ; } </s>

Handle the TARGET_STRICT_ARGUMENT_NAMING target hook .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> bool ARMFrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> bool X86TargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { APInt MulC ; if ( ! ISD :: isConstantSplatVector ( C . getNode ( ) , MulC ) ) return false ; while ( getTypeAction ( Context , VT ) != TypeLegal ) VT = getTypeToTransformTo ( Context , VT ) ; if ( isOperationLegal ( ISD :: MUL , VT ) ) return false ; return ( MulC + 1 ) . isPowerOf2 ( ) || ( MulC - 1 ) . isPowerOf2 ( ) || ( 1 - MulC ) . isPowerOf2 ( ) || ( - ( MulC + 1 ) ) . isPowerOf2 ( ) ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( decl == NULL || TARGET_THUMB ) return false ; if ( lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_SHORT ; else if ( lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_LONG ; if ( call_type == CALL_LONG && ( flag_pic || ! TREE_ASM_WRITTEN ( decl ) ) ) return false ; if ( TARGET_INTERWORK && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; if ( IS_INTERRUPT ( arm_current_func_type ( ) ) ) return false ; return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


<s> bool ARM64RegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { EVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static void ix86_seh_fixup_eh_fallthru ( void ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) { rtx_insn * insn , * next ; for ( insn = BB_END ( e -> src ) ; insn != NULL ; insn = PREV_INSN ( insn ) ) if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_EPILOGUE_BEG ) break ; if ( insn == NULL ) continue ; insn = prev_active_insn ( insn ) ; if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P ( next ) && ( NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION || NOTE_KIND ( next ) == NOTE_INSN_CALL_ARG_LOCATION ) ) insn = next ; else break ; emit_insn_after ( gen_nops ( const1_rtx ) , insn ) ; } } </s>

Fix up a Windows system unwinder issue . If an EH region falls through into the epilogue , the Windows system unwinder will apply epilogue logic and produce incorrect offsets . This can be avoided by adding a nop between the last insn that can throw and the first insn of the epilogue .


<s> bool X86TargetLowering :: useLoadStackGuardNode ( ) const { return Subtarget -> getTargetTriple ( ) . getObjectFormat ( ) == Triple :: MachO && Subtarget -> is64Bit ( ) ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> const char * OR1KTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( OR1KISD :: NodeType ) Opcode ) { default : return NULL ; case OR1KISD :: ADJDYNALLOC : return "OR1KISD::ADJDYNALLOC" ; case OR1KISD :: RET_FLAG : return "OR1KISD::RET_FLAG" ; case OR1KISD :: CALL : return "OR1KISD::CALL" ; case OR1KISD :: SELECT_CC : return "OR1KISD::SELECT_CC" ; case OR1KISD :: SET_FLAG : return "OR1KISD::SET_FLAG" ; case OR1KISD :: BR_CC : return "OR1KISD::BR_CC" ; case OR1KISD :: Wrapper : return "OR1KISD::Wrapper" ; case OR1KISD :: FF1 : return "OR1KISD::FF1" ; case OR1KISD :: FL1 : return "OR1KISD::FL1" ; case OR1KISD :: HI : return "OR1KISD::HI" ; case OR1KISD :: LO : return "OR1KISD::LO" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static void arm32_output_mi_thunk ( FILE * file , tree , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ? R1_REGNUM : R0_REGNUM ) ; rtx temp = gen_rtx_REG ( Pmode , IP_REGNUM ) ; rtx this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( delta != 0 ) arm_split_constant ( PLUS , Pmode , NULL_RTX , delta , this_rtx , this_rtx , false ) ; if ( vcall_offset != 0 ) { emit_move_insn ( temp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; arm_split_constant ( PLUS , Pmode , NULL_RTX , vcall_offset , temp , temp , false ) ; emit_move_insn ( temp , gen_rtx_MEM ( Pmode , temp ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } rtx funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx_insn * insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> uint64_t MipsGNUInfo :: flags ( ) const { return m_ElfFlags ; } </s>

Get the flags for this GlobalValue ( see struct GVFlags ) .


<s> StringRef MipsInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s> Register PPCTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget . isPPC64 ( ) ? PPC :: X4 : PPC :: R4 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> static bool set_to_load_agen ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set ; out_set = single_set ( out_insn ) ; if ( out_set ) { in_set = single_set ( in_insn ) ; if ( in_set ) return reg_mentioned_p ( SET_DEST ( out_set ) , SET_SRC ( in_set ) ) ; } return false ; } </s>

The function returns true if out_inst sets a value that is used in the address generation computation of in_insn


<s> static rtx mips_expand_builtin_compare ( enum mips_builtin_type builtin_type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree exp ) { rtx offset , condition , cmp_result ; if ( target == 0 || GET_MODE ( target ) != SImode ) target = gen_reg_rtx ( SImode ) ; cmp_result = mips_expand_builtin_compare_1 ( icode , cond , exp , call_expr_nargs ( exp ) ) ; switch ( builtin_type ) { case MIPS_BUILTIN_CMP_ALL : condition = gen_rtx_NE ( VOIDmode , cmp_result , constm1_rtx ) ; return mips_builtin_branch_and_move ( condition , target , const0_rtx , const1_rtx ) ; case MIPS_BUILTIN_CMP_UPPER : case MIPS_BUILTIN_CMP_LOWER : offset = GEN_INT ( builtin_type == MIPS_BUILTIN_CMP_UPPER ) ; condition = gen_single_cc ( cmp_result , offset ) ; return mips_builtin_branch_and_move ( condition , target , const1_rtx , const0_rtx ) ; default : condition = gen_rtx_NE ( VOIDmode , cmp_result , const0_rtx ) ; return mips_builtin_branch_and_move ( condition , target , const1_rtx , const0_rtx ) ; } } </s>

Expand a comparison builtin of type BUILTIN_TYPE . ICODE is the code of the comparison instruction and COND is the condition it should test . ARGLIST is the list of function arguments and TARGET , if nonnull , suggests a good place to put the boolean result .


<s> bool loongarch_legitimize_move ( machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { loongarch_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( ! register_operand ( dest , mode ) && ! register_operand ( src , mode ) && ! const_0_operand ( src , mode ) ) { loongarch_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { loongarch_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false ; } </s>

If ( set DEST SRC ) is not a valid move instruction , emit an equivalent sequence that is valid .


<s> bool X86TargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { int ShiftAmountOpNum = - 1 ; if ( I -> isShift ( ) ) ShiftAmountOpNum = 1 ; else if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( II -> getIntrinsicID ( ) == Intrinsic :: fshl || II -> getIntrinsicID ( ) == Intrinsic :: fshr ) ShiftAmountOpNum = 2 ; } if ( ShiftAmountOpNum == - 1 ) return false ; auto * Shuf = dyn_cast < ShuffleVectorInst > ( I -> getOperand ( ShiftAmountOpNum ) ) ; if ( Shuf && getSplatIndex ( Shuf -> getShuffleMask ( ) ) >= 0 && isVectorShiftByScalarCheap ( I -> getType ( ) ) ) { Ops . push_back ( & I -> getOperandUse ( ShiftAmountOpNum ) ) ; return true ; } return false ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


"RISC-V backend can't currently handle functions that need stack "

"realignment and have variable sized objects"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool nds32_float_mem_operand_p ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; rtx addr = XEXP ( op , 0 ) ; if ( GET_CODE ( addr ) == SYMBOL_REF || GET_CODE ( addr ) == CONST || GET_CODE ( addr ) == LO_SUM ) return false ; if ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF ) return false ; if ( GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT ) { if ( ( mode == SImode || mode == SFmode ) && NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( XEXP ( addr , 1 ) ) ) && ! satisfies_constraint_Is14 ( XEXP ( addr , 1 ) ) ) return false ; if ( ( mode == DImode || mode == DFmode ) && NDS32_DOUBLE_WORD_ALIGN_P ( INTVAL ( XEXP ( addr , 1 ) ) ) && ! satisfies_constraint_Is14 ( XEXP ( addr , 1 ) ) ) return false ; } } return true ; } </s>

Vaild memory operand for floating-point loads and stores


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> bool PPCTargetLowering :: SelectAddressRegRegOnly ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { if ( SelectAddressRegReg ( N , Base , Index , DAG ) ) return true ; if ( N . getOpcode ( ) == ISD :: ADD ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } Base = DAG . getRegister ( PPCSubTarget . isPPC64 ( ) ? PPC :: ZERO8 : PPC :: ZERO , N . getValueType ( ) ) ; Index = N ; return true ; } </s>

SelectAddressRegRegOnly - Given the specified addressed , force it to be represented as an indexed [ r+r ] operation .

PowerPC PPC ISD::ADD 0 1 PPC PPC PPC::ZERO8 PPC::ZERO


<s> void changedInstr ( MachineInstr & MI ) override { } </s>

This instruction was mutated in some way .


<s>
int
scalar_chain
::
convert
(
)
{
bitmap_iterator
bi
;
unsigned
id
;
int
converted_insns
=
0
;
if
(
!
dbg_cnt
(
stv_conversion
)
)
return
0
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Converting chain #%d...\n"
,
chain_id
)
;
convert_registers
(
)
;
EXECUTE_IF_SET_IN_BITMAP
(
insns
,
0
,
id
,
bi
)
{
rtx_insn
*
insn
=
DF_INSN_UID_GET
(
id
)
->
insn
;
convert_insn_common
(
insn
)
;
convert_insn
(
insn
)
;
converted_insns
++
;
}
return
converted_insns
;
}
</s>

Convert whole chain creating required register conversions and copies .


<s> static machine_mode mips_dwarf_frame_reg_mode ( int regno ) { machine_mode mode = default_dwarf_frame_reg_mode ( regno ) ; if ( FP_REG_P ( regno ) && mips_abi == ABI_32 && ! TARGET_FLOAT32 ) mode = SImode ; return mode ; } </s>


<s> void X86TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( ! Subtarget . is64Bit ( ) ) return ; X86MachineFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < X86MachineFunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s>
Register
LanaiTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
,
const
MachineFunction
&
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"pc"
,
Lanai
::
PC
)
.
Case
(
"sp"
,
Lanai
::
SP
)
.
Case
(
"fp"
,
Lanai
::
FP
)
.
Case
(
"rr1"
,
Lanai
::
RR1
)
.
Case
(
"r10"
,
Lanai
::
R10
)
.
Case
(
"rr2"
,
Lanai
::
RR2
)
.
Case
(
"r11"
,
Lanai
::
R11
)
.
Case
(
"rca"
,
Lanai
::
RCA
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> int mips_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct mips_address_info addr ; int factor ; if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; else factor = 1 ; if ( mips_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : if ( TARGET_MIPS16 && ! mips16_unextended_reference_p ( mode , addr . reg , UINTVAL ( addr . offset ) ) ) return factor * 2 ; return factor ; case ADDRESS_LO_SUM : return TARGET_MIPS16 ? factor * 2 : factor ; case ADDRESS_CONST_INT : return factor ; case ADDRESS_SYMBOLIC : return factor * mips_symbol_insns ( addr . symbol_type , mode ) ; } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at X . Return 0 if X is n't valid for MODE . For mips16 code , count extended instructions as two instructions .


<s>
bool
ARM64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
if
(
!
BranchRelaxation
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"***** ARM64BranchRelaxation *****\n"
)
;
TII
=
(
const
ARM64InstrInfo
*
)
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
)
;
DEBUG
(
dumpBBs
(
)
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n"
)
;
DEBUG
(
dbgs
(
)
<<
'\n'
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void paired_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 ; rtx x , new_rtx , tmp , constant_op , op1 , op2 ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONST_FIXED_P ( x ) ) ) ++ n_var ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( n_var == 2 ) { new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , XVECEXP ( vals , 0 , 0 ) , XVECEXP ( vals , 0 , 1 ) ) ; emit_move_insn ( target , new_rtx ) ; return ; } op1 = XVECEXP ( vals , 0 , 0 ) ; op2 = XVECEXP ( vals , 0 , 1 ) ; constant_op = ( CONSTANT_P ( op1 ) ) ? op1 : op2 ; tmp = gen_reg_rtx ( GET_MODE ( constant_op ) ) ; emit_move_insn ( tmp , constant_op ) ; if ( CONSTANT_P ( op1 ) ) new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , tmp , op2 ) ; else new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , op1 , tmp ) ; emit_move_insn ( target , new_rtx ) ; } </s>

Initialize TARGET of vector PAIRED to VALS .


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: tLDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( const GlobalValue * Val ) { const MipsCallEntry * & E = GlobalCallEntries [ Val ] ; if ( ! E ) E = new MipsCallEntry ( Val ) ; return MachinePointerInfo ( E ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Ins ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) ; const MipsABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , 1 ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"mips16 and nomips16 specified on the same function"

Reset the subtarget for the Mips target .


<s> static int shcompact_byref ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ) { unsigned HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( cum -> arg_count [ SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! named || GET_SH_ARG_CLASS ( mode ) == SH_ARG_INT || ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT && cum -> arg_count [ SH_ARG_FLOAT ] >= NPARM_REGS ( SFmode ) ) ) && size > 4 && ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) return size ; else return 0 ; } </s>

Whether an argument must be passed by reference . On SHcompact , we pretend arguments wider than 32-bits that would have been passed in registers are passed by reference , so that an SHmedia trampoline loads them into the full 64-bits registers .


Hook to validate the current # pragma GCC target and set the arch custom mode state . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> void ix86_override_options_after_change ( void ) { ix86_default_align ( & global_options ) ; ix86_recompute_optlev_based_flags ( & global_options , & global_options_set ) ; if ( ( OPTION_SET_P ( flag_unroll_loops ) ) || ( OPTION_SET_P ( flag_unroll_all_loops ) && flag_unroll_all_loops ) ) { if ( ! OPTION_SET_P ( ix86_unroll_only_small_loops ) ) ix86_unroll_only_small_loops = 0 ; if ( ! OPTION_SET_P ( flag_web ) ) flag_web = flag_unroll_loops ; if ( ! OPTION_SET_P ( flag_rename_registers ) ) flag_rename_registers = flag_unroll_loops ; if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = flag_unroll_loops || flag_peel_loops || optimize >= 3 ; } else { if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = flag_peel_loops || optimize >= 3 ; } } </s>

Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook .


<s> static scalar_int_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ? SImode : word_mode ; } </s>


<s> unsigned getMappedIdxOpcForImmOpc ( unsigned ImmOpcode ) const { if ( ! ImmToIdxMap . count ( ImmOpcode ) ) return PPC :: INSTRUCTION_LIST_END ; return ImmToIdxMap . find ( ImmOpcode ) -> second ; } </s>

getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode for a given imm form load/store opcode ImmFormOpcode .


<s>
bool
PPCCTRLoopsVerify
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
if
(
!
MDT
->
isReachableFromEntry
(
&
MBB
)
)
continue
;
for
(
MachineBasicBlock
::
iterator
MII
=
MBB
.
getFirstTerminator
(
)
,
MIIE
=
MBB
.
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
unsigned
Opc
=
MII
->
getOpcode
(
)
;
if
(
Opc
==
PPC
::
BDNZ8
||
Opc
==
PPC
::
BDNZ
||
Opc
==
PPC
::
BDZ8
||
Opc
==
PPC
::
BDZ
)
if
(
!
verifyCTRBranch
(
&
MBB
,
MII
)
)
llvm_unreachable
(
"Invalid PPC CTR loop!"
)
;
}
}
return
false
;
}
</s>

PowerPC
PPC
PPC::BDNZ8
PPC::BDNZ
PPC::BDZ8
PPC::BDZ
"Invalid PPC CTR loop!"


<s> bool PPCTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createPPCISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool AArch64InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; unsigned ExtraCondLat = Cond . size ( ) != 1 ; if ( AArch64 :: GPR64allRegClass . hasSubClassEq ( RC ) || AArch64 :: GPR32allRegClass . hasSubClassEq ( RC ) ) { CondCycles = 1 + ExtraCondLat ; TrueCycles = FalseCycles = 1 ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = 0 ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = 0 ; return true ; } if ( AArch64 :: FPR64RegClass . hasSubClassEq ( RC ) || AArch64 :: FPR32RegClass . hasSubClassEq ( RC ) ) { CondCycles = 5 + ExtraCondLat ; TrueCycles = FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool X86TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 || BitSize > 64 ) return false ; return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> void ARMAsmPrinter :: emitFunctionEntryLabel ( ) { if ( AFI -> isThumbFunction ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; OutStreamer -> emitThumbFunc ( CurrentFnSym ) ; } else { OutStreamer -> emitAssemblerFlag ( MCAF_Code32 ) ; } OutStreamer -> emitLabel ( CurrentFnSym ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s> const F2003fRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int ARMTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ST -> hasMVEIntegerOps ( ) && ICA . getID ( ) == Intrinsic :: get_active_lane_mask ) return 0 ; return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> static unsigned int aarch64_sve_in_loop_reduction_latency ( vec_info * vinfo , stmt_vec_info stmt_info , tree vectype , const sve_vec_cost * sve_costs ) { switch ( aarch64_reduc_type ( vinfo , stmt_info ) ) { case EXTRACT_LAST_REDUCTION : return sve_costs -> clast_cost ; case FOLD_LEFT_REDUCTION : switch ( GET_MODE_INNER ( TYPE_MODE ( vectype ) ) ) { case E_HFmode : case E_BFmode : return sve_costs -> fadda_f16_cost ; case E_SFmode : return sve_costs -> fadda_f32_cost ; case E_DFmode : return sve_costs -> fadda_f64_cost ; default : break ; } break ; } return 0 ; } </s>

We are considering implementing STMT_INFO using SVE vector type VECTYPE . If STMT_INFO is an in-loop reduction that SVE supports directly , return its latency in cycles , otherwise return zero . SVE_COSTS specifies the latencies of the relevant instructions .


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << "[" << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << "]" ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum , O ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNum ) . isReg ( ) || OpNum + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNum + 1 ) . isReg ( ) ) return true ; ++ OpNum ; } } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { for ( MachineFunction :: iterator MBBi = MF . begin ( ) ; MBBi != MF . end ( ) ; MBBi ++ ) { MachineBasicBlock & MBB = * MBBi ; for ( MachineBasicBlock :: iterator MIi = MBB . begin ( ) ; MIi != MBB . end ( ) ; MIi ++ ) { MachineInstr & MI = * MIi ; for ( int i = 0 ; i < MI . getNumOperands ( ) ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isMetadata ( ) ) { const MDNode * mdn = MO . getMetadata ( ) ; mdn -> dump ( ) ; errs ( ) << MI << "\n" ; } } } } return false ; } </s>

runOnMachineFunction - Emit the function body .


Like arm_compute_initial_elimination offset . Simpler because there is n't an ABI specified frame pointer for Thumb . Instead , we set it to point at the base of the local variables after static stack space for a function has been allocated .


<s> static ARMOperand * CreateMem ( unsigned BaseRegNum , bool OffsetIsReg , const MCExpr * Offset , unsigned OffsetRegNum , bool OffsetRegShifted , enum ShiftType ShiftType , const MCExpr * ShiftAmount , bool Preindexed , bool Postindexed , bool Negative , bool Writeback , SMLoc S , SMLoc E ) { ARMOperand * Op = new ARMOperand ( Memory ) ; Op -> Mem . BaseRegNum = BaseRegNum ; Op -> Mem . OffsetIsReg = OffsetIsReg ; Op -> Mem . Offset = Offset ; Op -> Mem . OffsetRegNum = OffsetRegNum ; Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> static void replace_swapped_aligned_store ( swap_web_entry * insn_entry , rtx_insn * store_insn ) { unsigned uid = INSN_UID ( store_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && insn_entry [ uid ] . is_store ) ; rtx body = PATTERN ( store_insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , 0 ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , 0 ) ; gcc_assert ( REG_P ( dest_address ) || rs6000_sum_of_two_registers_p ( dest_address ) ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( store_insn ) ; df_ref use ; rtx_insn * swap_insn = NULL ; unsigned uid2 = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= 128 ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_DEST ( new_body ) ) ) ; basic_block bb = BLOCK_FOR_INSN ( store_insn ) ; set_block_for_insn ( new_insn , bb ) ; if ( cfun -> can_throw_non_call_exceptions && BB_END ( bb ) == store_insn ) { rtx note = find_reg_note ( store_insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) add_reg_note ( new_insn , REG_EH_REGION , XEXP ( note , 0 ) ) ; } df_insn_rescan ( new_insn ) ; df_insn_delete ( store_insn ) ; remove_insn ( store_insn ) ; store_insn -> set_deleted ( ) ; uid2 = INSN_UID ( swap_insn ) ; mark_swaps_for_removal ( insn_entry , uid2 ) ; replace_swap_with_copy ( insn_entry , uid2 ) ; } </s>

Given that STORE_INSN represents an aligned store-with-swap of a swapped value , replace the store with an aligned store ( without swap ) and replace the swap with a copy insn .


<s> static rtx csky_legitimize_address ( rtx x , rtx orig_x ATTRIBUTE_UNUSED , machine_mode mode ) { if ( csky_tls_symbol_p ( x ) ) return csky_legitimize_tls_address ( x , NULL_RTX ) ; if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; if ( is_csky_address_register_rtx_p ( xop0 , 0 ) && CONST_INT_P ( xop1 ) ) { HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset > CSKY_LD16_MAX_OFFSET ( mode ) && offset <= ( CSKY_ADDI16_MAX_IMM + CSKY_LD16_MAX_OFFSET ( mode ) ) ) { HOST_WIDE_INT new_ld_offset = offset & CSKY_LD16_OFFSET_MASK ( mode ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - new_ld_offset ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , new_ld_offset ) ; } else if ( offset < 0 && offset >= ( - CSKY_SUBI16_MAX_IMM ) ) x = force_operand ( x , NULL_RTX ) ; else if ( offset > CSKY_LD16_MAX_OFFSET ( mode ) || offset < 0 ) { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } if ( is_csky_address_register_rtx_p ( xop1 , 0 ) && ! is_csky_address_register_rtx_p ( xop0 , 0 ) ) { xop0 = force_operand ( xop0 , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( CONST_INT_P ( x ) && optimize > 0 ) { HOST_WIDE_INT mask , base , index ; rtx base_reg ; mask = CSKY_LD16_OFFSET_MASK ( mode ) ; base = INTVAL ( x ) & ~ mask ; index = INTVAL ( x ) & mask ; base_reg = force_reg ( SImode , GEN_INT ( base ) ) ; x = plus_constant ( Pmode , base_reg , index ) ; } return x ; } </s>


<s> bool SystemZInstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( SystemZ :: FP64RegClass . contains ( Reg ) ) loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , & SystemZ :: FP64RegClass , & RI ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64rm : SystemZ :: MOV64rmm ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Define ) ; MIB . addReg ( ( RegInfo -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ) ) ; MIB . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void arm_init_acle_builtins ( void ) { unsigned int i , fcode = ARM_BUILTIN_ACLE_PATTERN_START ; for ( i = 0 ; i < ARRAY_SIZE ( acle_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & acle_builtin_data [ i ] ; arm_init_builtin ( fcode , d , "__builtin_arm" ) ; } } </s>

Set up ACLE builtins , even builtins for instructions that are not in the current target ISA to allow the user to compile particular modules with different target specific options that differ from the command line options . Such builtins will be rejected in arm_expand_builtin .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { LIS = & getAnalysis < LiveIntervals > ( ) ; TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const AArch64Subtarget & ST = C -> MF -> getSubtarget < AArch64Subtarget > ( ) ; if ( ST . hasFuseLiterals ( ) ) { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } return nullptr ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , 0 ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 16 0


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s> bool AArch64TargetLowering :: isLegalAddImmediate ( int64_t Immed ) const { if ( Immed == std :: numeric_limits < int64_t > :: min ( ) ) return false ; Immed = std :: abs ( Immed ) ; return ( ( Immed >> 12 ) == 0 || ( ( Immed & 0xfff ) == 0 && Immed >> 24 == 0 ) ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> bool PPCTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( Ty -> isVectorTy ( ) && AM . BaseOffs != 0 && ! Subtarget . hasP9Vector ( ) ) return false ; if ( AM . BaseOffs <= - ( 1LL << 16 ) || AM . BaseOffs >= ( 1LL << 16 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void MipsPassConfig :: addPreRegAlloc ( ) { addPass ( createMipsOptimizePICCallPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool mep_vliw_function_p ( tree decl ) { return lookup_attribute ( "vliw" , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) != 0 ; } </s>

Return true if function DECL was declared with the vliw attribute .


<s> bool ARMPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> std :: unique_ptr < MCObjectWriter > LanaiAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createLanaiELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static void function_arg_record_value_2 ( tree type , HOST_WIDE_INT startbitpos , struct function_arg_record_value_parms * parms , bool packed_p ) { tree field ; if ( ! packed_p ) for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && DECL_PACKED ( field ) ) { packed_p = true ; break ; } } for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; if ( DECL_SIZE ( field ) != 0 ) { if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( host_integerp ( bit_position ( field ) , 1 ) ) bitpos += int_bit_position ( field ) ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) function_arg_record_value_2 ( TREE_TYPE ( field ) , bitpos , parms , packed_p ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU && parms -> named && ! packed_p ) { int this_slotno = parms -> slotno + bitpos / BITS_PER_WORD ; int regno , nregs , pos ; enum machine_mode mode = DECL_MODE ( field ) ; rtx reg ; function_arg_record_value_3 ( bitpos , parms ) ; if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = 2 ; } else nregs = 1 ; regno = SPARC_FP_ARG_FIRST + this_slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 && ( bitpos & 32 ) != 0 ) regno ++ ; reg = gen_rtx_REG ( mode , regno ) ; pos = bitpos / BITS_PER_UNIT ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; parms -> nregs += 1 ; while ( -- nregs > 0 ) { regno += GET_MODE_SIZE ( mode ) / 4 ; reg = gen_rtx_REG ( mode , regno ) ; pos += GET_MODE_SIZE ( mode ) ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; parms -> nregs += 1 ; } } else { if ( parms -> intoffset == - 1 ) parms -> intoffset = bitpos ; } } } } </s>

A subroutine of function_arg_record_value . Traverse the structure recursively and assign bits to floating point registers . Track which bits in between need integer registers ; invoke function_arg_record_value_3 to make that happen .


<s> bool insertEdge ( Register Reg ) { return Edges . insert ( Reg ) . second ; } </s>

Update the call graph after inserting a new edge .


<s>
SDValue
LoongArchTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
break
;
}
SmallVector
<
CCValAssign
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeInputArgs
(
CCInfo
,
Ins
,
CC_LoongArch
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
InVals
.
push_back
(
unpackFromRegLoc
(
DAG
,
Chain
,
ArgLocs
[
i
]
,
DL
,
*
this
)
)
;
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

LoongArch
LoongArch
ISD::InputArg
"Unsupported calling convention"
LoongArch
0


<s> int regs_used ( rtx x , int is_dest ) { enum rtx_code code ; const char * fmt ; int used = 0 ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < 16 ) return ( ( ( 1 << hard_regno_nregs ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( x ) + is_dest ) ) ; return 0 ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < 16 ) return ( ( ( 1 << hard_regno_nregs ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return 0 ; } case SET : return regs_used ( SET_SRC ( x ) , 0 ) | regs_used ( SET_DEST ( x ) , 16 ) ; case RETURN : return 0x00ffff00 ; case CLOBBER : is_dest = 1 ; break ; case MEM : is_dest = 0 ; break ; case CALL : used |= 0x00ff00f0 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( int i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { for ( int j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return used ; } </s>

Given a X , a pattern of an insn or a part of it , return a mask of used general registers . Bits 0 .. 15 mean that the respective registers are used as inputs in the instruction . Bits 16 .. 31 mean that the registers 0 .. 15 , respectively , are used as outputs , or are clobbered . IS_DEST should be set to 16 if X is the destination of a SET , else to 0 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 LEA Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int arm_cpymemqi_unaligned ( rtx * operands ) { HOST_WIDE_INT length = INTVAL ( operands [ 2 ] ) ; if ( optimize_size ) { bool src_aligned = MEM_ALIGN ( operands [ 1 ] ) >= BITS_PER_WORD ; bool dst_aligned = MEM_ALIGN ( operands [ 0 ] ) >= BITS_PER_WORD ; unsigned int interleave_factor = ( src_aligned || dst_aligned ) ? 2 : 1 ; HOST_WIDE_INT bytes_per_iter = ( src_aligned || dst_aligned ) ? 8 : 4 ; if ( length > 12 ) arm_block_move_unaligned_loop ( operands [ 0 ] , operands [ 1 ] , length , interleave_factor , bytes_per_iter ) ; else arm_block_move_unaligned_straight ( operands [ 0 ] , operands [ 1 ] , length , interleave_factor ) ; } else { if ( length > 32 ) arm_block_move_unaligned_loop ( operands [ 0 ] , operands [ 1 ] , length , 4 , 16 ) ; else arm_block_move_unaligned_straight ( operands [ 0 ] , operands [ 1 ] , length , 4 ) ; } return 1 ; } </s>

Emit a block move when either the source or destination is unaligned ( not aligned to a four-byte boundary ) . This may need further tuning depending on core type , optimize_size setting , etc .


<s> static bool sh_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) && ( mode1 != SFmode && mode2 != SFmode ) ) ) ; } </s>

Implement TARGET_MODES_TIEABLE_P . If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2 , for any hard reg , then this must be false for correct output . That 's the case for xd registers : we do n't hold SFmode values in them , so we ca n't tie an SFmode pseudos with one in another floating-point mode .


<s> static void replace_constant_pool_with_broadcast ( rtx_insn * insn ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , & PATTERN ( insn ) , ALL ) { rtx * loc = * iter ; rtx x = * loc ; rtx broadcast_mem , vec_dup , constant , first ; machine_mode mode ; if ( ! MEM_P ( x ) || ! SYMBOL_REF_P ( XEXP ( x , 0 ) ) || ! CONSTANT_POOL_ADDRESS_P ( XEXP ( x , 0 ) ) ) continue ; mode = GET_MODE ( x ) ; if ( ! VECTOR_MODE_P ( mode ) ) return ; constant = get_pool_constant ( XEXP ( x , 0 ) ) ; if ( GET_CODE ( constant ) != CONST_VECTOR ) return ; if ( GET_MODE ( constant ) != mode ) { constant = simplify_subreg ( mode , constant , GET_MODE ( constant ) , 0 ) ; if ( constant == NULL_RTX || GET_CODE ( constant ) != CONST_VECTOR ) return ; } first = XVECEXP ( constant , 0 , 0 ) ; for ( int i = 1 ; i < GET_MODE_NUNITS ( mode ) ; ++ i ) { rtx tmp = XVECEXP ( constant , 0 , i ) ; if ( ! rtx_equal_p ( tmp , first ) ) return ; } broadcast_mem = force_const_mem ( GET_MODE_INNER ( mode ) , first ) ; vec_dup = gen_rtx_VEC_DUPLICATE ( mode , broadcast_mem ) ; validate_change ( insn , loc , vec_dup , 0 ) ; return ; } } </s>

Replace all one-value const vector that are referenced by SYMBOL_REFs in x with embedded broadcast . i.e.transform vpaddq .LC0 ( % rip ) , % zmm0 , % zmm0 ret .LC0 : .quad 3 .quad 3 .quad 3 .quad 3 .quad 3 .quad 3 .quad 3 .quad 3 to vpaddq .LC0 ( % rip ) { 1to8 } , % zmm0 , % zmm0 ret .LC0 : .quad 3


<s> static int gen_v9_scc ( rtx dest , enum rtx_code compare_code , rtx x , rtx y ) { if ( ! TARGET_ARCH64 && ( GET_MODE ( x ) == DImode || GET_MODE ( dest ) == DImode ) ) return 0 ; if ( TARGET_ARCH64 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_INT && y == const0_rtx && v9_regcmp_p ( compare_code ) ) { rtx op0 = x ; rtx temp ; if ( compare_code == NE && GET_MODE ( dest ) == DImode && rtx_equal_p ( op0 , dest ) ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_fmt_ee ( compare_code , DImode , op0 , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } if ( reg_overlap_mentioned_p ( dest , op0 ) ) { op0 = gen_reg_rtx ( GET_MODE ( x ) ) ; emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , 0 ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } else { x = gen_compare_reg_1 ( compare_code , x , y ) ; y = const0_rtx ; gcc_assert ( GET_MODE ( x ) != CC_NOOVmode && GET_MODE ( x ) != CCX_NOOVmode ) ; emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , GET_MODE ( x ) , x , y ) , const1_rtx , dest ) ) ) ; return 1 ; } } </s>

This function is used for v9 only . CODE is the code for an Scc 's comparison . OPERANDS [ 0 ] is the target of the Scc insn . OPERANDS [ 1 ] is the value we compare against const0_rtx ( which has n't been generated yet ) . This function is needed to turn ( set ( reg : SI 110 ) ( gt ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) into ( set ( reg : SI 110 ) ( gt : DI ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) IE : The instruction recognizer needs to see the mode of the comparison to find the right instruction . We could use `` gt : DI '' right in the define_expand , but leaving it out allows us to handle DI , SI , etc . We refer to the global sparc compare operands sparc_compare_op0 and sparc_compare_op1 .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> rtx sh_load_function_descriptor ( rtx funcdesc ) { rtx r1 = gen_rtx_REG ( Pmode , R1_REG ) ; rtx pic_reg = gen_rtx_REG ( Pmode , PIC_REG ) ; rtx fnaddr = gen_rtx_MEM ( Pmode , funcdesc ) ; rtx gotaddr = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , funcdesc , 4 ) ) ; emit_move_insn ( r1 , fnaddr ) ; emit_insn ( gen_blockage ( ) ) ; emit_move_insn ( pic_reg , gotaddr ) ; return r1 ; } </s>

Emit insns to load the function address from FUNCDESC ( an FDPIC function descriptor ) into r1 and the GOT address into r12 , returning an rtx for r1 .


<s> void PPCTargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( ! Subtarget . isPPC64 ( ) ) return ; PPCFunctionInfo * PFI = Entry -> getParent ( ) -> getInfo < PPCFunctionInfo > ( ) ; PFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MipsSubtarget & Subtarget = MF -> getSubtarget < MipsSubtarget > ( ) ; const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( "interrupt" ) ) { if ( Subtarget . hasMips64 ( ) ) return Subtarget . hasMips64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . hasMips32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>

Mips Mips Mips Mips "interrupt" Mips Mips Mips


<s> static int ix86_simd_clone_usable ( struct cgraph_node * node ) { switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) return - 1 ; if ( ! TARGET_AVX ) return 0 ; return TARGET_AVX2 ? 2 : 1 ; case 'c' : if ( ! TARGET_AVX ) return - 1 ; return TARGET_AVX2 ? 1 : 0 ; break ; case 'd' : if ( ! TARGET_AVX2 ) return - 1 ; return 0 ; default : gcc_unreachable ( ) ; } } </s>

If SIMD clone NODE ca n't be used in a vectorized loop in current function , return -1 , otherwise return a badness of using it ( 0 if it is most desirable from vecsize_mangle point of view , 1 slightly less desirable , etc . ) .


<s> bool X86ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const X86Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FL = STI -> getFrameLowering ( ) ; bool Modified = ExpandPseudosWhichAffectControlFlow ( MF ) ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .