<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
const
TargetRegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i64
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static bool aarch64_legitimate_address_hook_p ( machine_mode mode , rtx x , bool strict_p ) { struct aarch64_address_info addr ; return aarch64_classify_address ( & addr , x , mode , strict_p ) ; } </s>

Return TRUE if X is a legitimate address for accessing memory in mode MODE .


<s> unsigned getSlotSize ( ) const { return SlotSize ; } </s>

getSlotSize - Stack slot size in bytes .


<s> MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( Kind . isMergeableConst ( ) && C ) { const unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_MEM_WRITE | COFF :: IMAGE_SCN_LNK_COMDAT ; std :: string COMDATSymName ; if ( Kind . isMergeableConst4 ( ) ) { if ( Align <= 4 ) { COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; Align = 4 ; } } else if ( Kind . isMergeableConst8 ( ) ) { if ( Align <= 8 ) { COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; Align = 8 ; } } else if ( Kind . isMergeableConst16 ( ) ) { if ( Align <= 16 ) { COMDATSymName = "__xmm@" + scalarConstantToHexString ( C ) ; Align = 16 ; } } else if ( Kind . isMergeableConst32 ( ) ) { if ( Align <= 32 ) { COMDATSymName = "__ymm@" + scalarConstantToHexString ( C ) ; Align = 32 ; } } if ( ! COMDATSymName . empty ( ) ) return getContext ( ) . getCOFFSection ( "sgxg_pub" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } return TargetLoweringObjectFile :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base.Reg "
;
if
(
Base
.
Reg
.
getNode
(
)
!=
0
)
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
<<
" Scale"
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base.Reg "
0
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
0
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" JT"
" Align"


<s> static section * loongarch_function_rodata_section ( tree decl , bool ) { return default_function_rodata_section ( decl , false ) ; } </s>

Implement TARGET_ASM_FUNCTION_RODATA_SECTION . The complication here is that jump tables will use absolute addresses , and should therefore not be included in the read-only part of a DSO . Handle such cases by selecting a normal data section instead of a read-only one . The logic apes that in default_function_rodata_section .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool OptimizePICCall :: runOnMachineFunction ( MachineFunction & F ) { if ( static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) . inMips16Mode ( ) ) return false ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , 8 > WorkList ( 1 , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode ( MBBI ) ; const MachineDomTreeNode * Node = MBBI . getNode ( ) ; const std :: vector < MachineDomTreeNode * > & Children = Node -> getChildren ( ) ; WorkList . append ( Children . begin ( ) , Children . end ( ) ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , IsLittleEndian ( LittleEndian ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> BaseKind getKind ( ) const { return Kind ; } </s>


<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { auto I = MemOp2RegOpTable . find ( Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return 0 ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I -> second . second & TB_FOLDED_STORE ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; if ( LoadRegIndex ) * LoadRegIndex = I -> second . second & TB_INDEX_MASK ; return I -> second . first ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s> static void aarch64_expand_vec_series ( rtx dest , rtx base , rtx step ) { machine_mode mode = GET_MODE ( dest ) ; scalar_mode inner = GET_MODE_INNER ( mode ) ; if ( ! aarch64_sve_index_immediate_p ( base ) ) base = force_reg ( inner , base ) ; if ( ! aarch64_sve_index_immediate_p ( step ) ) step = force_reg ( inner , step ) ; emit_set_insn ( dest , gen_rtx_VEC_SERIES ( mode , base , step ) ) ; } </s>


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . hasEHFunclets ( ) ) return true ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> EVT MipsTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != CONST_INT ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s>
const
char
*
arm_output_iwmmxt_tinsr
(
rtx
*
operands
)
{
int
mask
=
INTVAL
(
operands
[
3
]
)
;
int
i
;
char
templ
[
50
]
;
int
units
=
mode_nunits
[
GET_MODE
(
operands
[
0
]
)
]
;
gcc_assert
(
(
mask
&
(
mask
1
)
)
==
0
)
;
for
(
i
=
0
;
i
<
units
;
++
i
)
{
if
(
(
mask
&
0x01
)
==
1
)
{
break
;
}
mask
>>=
1
;
}
gcc_assert
(
i
<
units
)
;
{
switch
(
GET_MODE
(
operands
[
0
]
)
)
{
case
V8QImode
:
sprintf
(
templ
,
"tinsrb%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
case
V4HImode
:
sprintf
(
templ
,
"tinsrh%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
case
V2SImode
:
sprintf
(
templ
,
"tinsrw%%?\t%%0, %%2, #%d"
,
i
)
;
break
;
default
:
gcc_unreachable
(
)
;
break
;
}
output_asm_insn
(
templ
,
operands
)
;
}
return
""
;
}
</s>

Output assembly for a WMMX tinsr instruction .


<s>
const
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


<s> unsigned ARMInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STR : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: FSTD : case ARM :: FSTS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: tSpill : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineBasicBlock :: iterator MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( MI -> killsRegister ( Reg , TRI ) ) return ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { unsigned Opc = Subtarget . hasAVX ( ) ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI -> addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI -> addRegisterKilled ( Reg , TRI , true ) ; } } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> int aarch64_uxt_size ( int shift , HOST_WIDE_INT mask ) { if ( shift >= 0 && shift <= 3 ) { int size ; for ( size = 8 ; size <= 32 ; size *= 2 ) { HOST_WIDE_INT bits = ( ( HOST_WIDE_INT ) 1U << size ) - 1 ; if ( mask == bits << shift ) return size ; } } return 0 ; } </s>

Return size in bits of an arithmetic operand which is shifted/scaled and masked such that it is suitable for a UXTB , UXTH , or UXTW extend operator .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( ! EnablePPCPreinc ) return false ; SDValue Ptr ; EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
if
(
!
Value
)
return
;
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Kind
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
AArch64MCExpr
::
VariantKind
RefKind
=
static_cast
<
AArch64MCExpr
::
VariantKind
>
(
Target
.
getRefKind
(
)
)
;
if
(
AArch64MCExpr
::
getSymbolLoc
(
RefKind
)
==
AArch64MCExpr
::
VK_SABS
)
{
if
(
SignedValue
<
0
)
Data
[
Offset
+
3
]
&=
~
(
1
<<
6
)
;
else
Data
[
Offset
+
3
]
|=
(
1
<<
6
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) this -> Options . TrapUnreachable = true ; if ( getOptLevel ( ) <= EnableGlobalISelAtO ) setGlobalISel ( true ) ; } </s>


<s> bool SystemZAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { SystemZInstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + 1 ) . getImm ( ) , MI -> getOperand ( OpNo + 2 ) . getReg ( ) , OS ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static bool aarch64_register_saved_on_entry ( int regno ) { return cfun -> machine -> frame . reg_offset [ regno ] >= 0 ; } </s>

Return true if the register REGNO is saved on entry to the current function .


<s> void arm_emit_call_insn ( rtx pat , rtx addr , bool sibcall ) { rtx insn ; insn = emit_call_insn ( pat ) ; if ( TARGET_VXWORKS_RTP && flag_pic && ! sibcall && SYMBOL_REF_P ( addr ) && ( SYMBOL_REF_DECL ( addr ) ? ! targetm . binds_local_p ( SYMBOL_REF_DECL ( addr ) ) : ! SYMBOL_REF_LOCAL_P ( addr ) ) ) { require_pic_register ( NULL_RTX , false ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , cfun -> machine -> pic_reg ) ; } if ( TARGET_FDPIC ) { rtx fdpic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , fdpic_reg ) ; } if ( TARGET_AAPCS_BASED ) { rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP_REGNUM ) ) ; } } </s>

Emit a call instruction with pattern PAT . ADDR is the address of the call target .


"Lanai branch conditions should have one component."

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


"passing %wd to argument %d of %qE, which expects"

Report that LOCATION has a call to FNDECL in which argument ARGNO has the value ACTUAL , whereas the function requires either VALUE0 or VALUE1 . ARGNO counts from zero .


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool SystemZMCAsmInfoGOFF :: isAcceptableChar ( char C ) const { return MCAsmInfo :: isAcceptableChar ( C ) || C == '#' ; } </s>

Return true if C is an acceptable character inside a symbol name .


<s> OperandMatchResultTy CSKYAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Sparc Sparc 0 SPISD::CMPICC "SPISD::CMPICC" SPISD::CMPFCC "SPISD::CMPFCC" SPISD::BRICC "SPISD::BRICC" SPISD::BRFCC "SPISD::BRFCC" SPISD::SELECT_ICC "SPISD::SELECT_ICC" SPISD::SELECT_FCC "SPISD::SELECT_FCC" SPISD::Hi "SPISD::Hi" SPISD::Lo "SPISD::Lo" SPISD::FTOI "SPISD::FTOI" SPISD::ITOF "SPISD::ITOF" SPISD::CALL "SPISD::CALL" SPISD::RET_FLAG "SPISD::RET_FLAG" SPISD::GLOBAL_BASE_REG "SPISD::GLOBAL_BASE_REG" SPISD::FLUSHW "SPISD::FLUSHW"


<s> static void arm_set_fixed_optab_libfunc ( optab optable , machine_mode mode , const char * funcname , const char * modename , int num_suffix ) { char buffer [ 50 ] ; if ( num_suffix == 0 ) sprintf ( buffer , "__gnu_%s%s" , funcname , modename ) ; else sprintf ( buffer , "__gnu_%s%s%d" , funcname , modename , num_suffix ) ; set_optab_libfunc ( optable , mode , buffer ) ; } </s>

A small helper for setting fixed-point library libfuncs .


Constant pools are per function only when PC relative literal loads are true or we are in the large memory model .


<s> static inline void atomic_free ( unsigned int * mask , int bit ) { __sync_xor_and_fetch ( mask , 1 << bit ) ; } </s>


<s> static rtx rs6000_emit_vector_compare_inner ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx mask ; machine_mode mode = GET_MODE ( op0 ) ; switch ( code ) { default : break ; case GE : if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) return NULL_RTX ; case EQ : case GT : case GTU : case ORDERED : case UNORDERED : case UNEQ : case LTGT : mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( mask , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return mask ; } return NULL_RTX ; } </s>

Return insn for VSX or Altivec comparisons .


<s> bool AArch64InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns ) const { if ( getMaddPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> void buildLoad ( unsigned Val , unsigned Addr , uint64_t Size , unsigned Alignment , MachinePointerInfo & MPO ) { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; MIRBuilder . buildLoad ( Val , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s> bool hasFusion ( ) const { return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseLiterals ( ) ; } </s>

Return true if the CPU supports any kind of instruction fusion .


<s> int getOffset ( ) const { return Offset ; } </s>

Get the offest of a string in the string table .


<s>
bool
AArch64InstrInfo
::
isGPRZero
(
const
MachineInstr
&
MI
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
MOVZWi
:
case
AArch64
::
MOVZXi
:
if
(
MI
.
getOperand
(
1
)
.
isImm
(
)
&&
MI
.
getOperand
(
1
)
.
getImm
(
)
==
0
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
2
)
.
getImm
(
)
==
0
&&
"invalid MOVZi operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ANDWri
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
case
AArch64
::
ANDXri
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
;
case
TargetOpcode
::
COPY
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
}
return
false
;
}
</s>

Does this instruction set its full destination register to zero ?


<s> bool OR1KPassConfig :: addInstSelector ( ) { addPass ( createOR1KISelDag ( getOR1KTargetMachine ( ) ) ) ; addPass ( createOR1KGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool rx_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : case POST_INC : return true ; case MINUS : case PLUS : if ( ! REG_P ( XEXP ( addr , 0 ) ) ) return true ; addr = XEXP ( addr , 1 ) ; switch ( GET_CODE ( addr ) ) { case REG : return true ; case CONST_INT : if ( ( ( INTVAL ( addr ) & 3 ) == 0 ) && IN_RANGE ( INTVAL ( addr ) , 4 , 0xfffc ) ) return false ; return true ; case SYMBOL_REF : case LABEL_REF : return true ; case MULT : return true ; default : return true ; } case CONST_INT : case SYMBOL_REF : case LABEL_REF : case REG : return false ; default : return true ; } } </s>


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int Cost = 0 ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: SDIV : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case ISD :: UDIV : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( ISD :: MULHU , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * 2 + AddCost * 2 + ShrCost * 2 + 1 ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return ( Cost + 1 ) * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> enum rtx_code pru_noteq_condition ( enum rtx_code code ) { switch ( code ) { case GT : return GT ; case GTU : return GTU ; case GE : return GT ; case GEU : return GTU ; case LT : return LT ; case LTU : return LTU ; case LE : return LT ; case LEU : return LTU ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison CODE , return a similar comparison but without the `` equals '' condition . In other words , it strips GE/GEU/LE/LEU and instead returns GT/GTU/LT/LTU .


<s>
SDValue
SystemZTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

SystemZ
SystemZ
ISD::InputArg
"Unsupported calling convention"


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
virtual
const
char
*
getPassName
(
)
const
LLVM_OVERRIDE
{
return
"ARM Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Insert Cache Prefetches"
;
}
</s>


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
II
->
getRegisterInfo
(
)
.
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isFPImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getFPImm
(
)
->
getValueAPF
(
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
MCID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool X86InstrInfo :: getMemOperandsWithOffsetWidth ( const MachineInstr & MemOp , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable , unsigned & Width , const TargetRegisterInfo * TRI ) const { const MCInstrDesc & Desc = MemOp . getDesc ( ) ; int MemRefBegin = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( MemRefBegin < 0 ) return false ; MemRefBegin += X86II :: getOperandBias ( Desc ) ; const MachineOperand * BaseOp = & MemOp . getOperand ( MemRefBegin + X86 :: AddrBaseReg ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + X86 :: AddrScaleAmt ) . getImm ( ) != 1 ) return false ; if ( MemOp . getOperand ( MemRefBegin + X86 :: AddrIndexReg ) . getReg ( ) != X86 :: NoRegister ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + X86 :: AddrDisp ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; OffsetIsScalable = false ; Width = ! MemOp . memoperands_empty ( ) ? MemOp . memoperands ( ) . front ( ) -> getSize ( ) : 0 ; BaseOps . push_back ( BaseOp ) ; return true ; } </s>

Get zero or more base operands and the byte offset of an instruction that reads/writes memory .


<s> void F2003fInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> int const_ok_for_op ( HOST_WIDE_INT i , enum rtx_code code ) { if ( const_ok_for_arm ( i ) ) return 1 ; switch ( code ) { case SET : if ( arm_arch_thumb2 && ( i & 0xffff0000 ) == 0 ) return 1 ; else return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; case PLUS : if ( TARGET_THUMB2 && ( ( i & 0xfffff000 ) == 0 || ( ( - i ) & 0xfffff000 ) == 0 ) ) return 1 ; case COMPARE : case EQ : case NE : case GT : case LE : case LT : case GE : case GEU : case LTU : case GTU : case LEU : case UNORDERED : case ORDERED : case UNEQ : case UNGE : case UNLT : case UNGT : case UNLE : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : return 0 ; case IOR : if ( TARGET_THUMB2 ) return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; return 0 ; case AND : return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if I is a valid constant for the operation CODE .


<s> void sparc_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , retval , mem , oldval , newval ; machine_mode mode ; enum memmodel model ; bval = operands [ 0 ] ; retval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; model = ( enum memmodel ) INTVAL ( operands [ 6 ] ) ; mode = GET_MODE ( mem ) ; sparc_emit_membar_for_model ( model , 3 , 1 ) ; if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; if ( mode == QImode || mode == HImode ) sparc_expand_compare_and_swap_12 ( bval , retval , mem , oldval , newval ) ; else { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx x ; if ( mode == SImode ) gen = gen_atomic_compare_and_swapsi_1 ; else gen = gen_atomic_compare_and_swapdi_1 ; emit_insn ( gen ( retval , mem , oldval , newval ) ) ; x = emit_store_flag ( bval , EQ , retval , oldval , mode , 1 , 1 ) ; if ( x != bval ) convert_move ( bval , x , 1 ) ; } sparc_emit_membar_for_model ( model , 3 , 2 ) ; } </s>

Expand code to perform a compare-and-swap .


<s> void ARMELFStreamer :: reset ( ) { MCTargetStreamer & TS = * getTargetStreamer ( ) ; ARMTargetStreamer & ATS = static_cast < ARMTargetStreamer & > ( TS ) ; ATS . reset ( ) ; MappingSymbolCounter = 0 ; MCELFStreamer :: reset ( ) ; getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_ARM_EABI_VER5 ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicRMWIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicRMWInst
*
AI
,
Value
*
AlignedAddr
,
Value
*
Incr
,
Value
*
Mask
,
Value
*
ShiftAmt
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
AlignedAddr
->
getType
(
)
->
getPointerElementType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
RMW
=
Intrinsic
::
getDeclaration
(
M
,
getIntrinsicForAtomicRMWBinOp128
(
AI
->
getOperation
(
)
)
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
IncrLo
=
Builder
.
CreateTrunc
(
Incr
,
Int64Ty
,
"incr_lo"
)
;
Value
*
IncrHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Incr
,
64
)
,
Int64Ty
,
"incr_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
RMW
,
{
Addr
,
IncrLo
,
IncrHi
}
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void ix86_split_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { enum rtx_code absneg_op ; rtx dst , set ; gcc_assert ( operands_match_p ( operands [ 0 ] , operands [ 1 ] ) ) ; switch ( mode ) { case E_SFmode : dst = gen_lowpart ( SImode , operands [ 0 ] ) ; if ( code == ABS ) { set = gen_int_mode ( 0x7fffffff , SImode ) ; absneg_op = AND ; } else { set = gen_int_mode ( 0x80000000 , SImode ) ; absneg_op = XOR ; } set = gen_rtx_fmt_ee ( absneg_op , SImode , dst , set ) ; break ; case E_DFmode : if ( TARGET_64BIT ) { dst = gen_lowpart ( DImode , operands [ 0 ] ) ; dst = gen_rtx_ZERO_EXTRACT ( DImode , dst , const1_rtx , GEN_INT ( 63 ) ) ; if ( code == ABS ) set = const0_rtx ; else set = gen_rtx_NOT ( DImode , dst ) ; } else { dst = gen_highpart ( SImode , operands [ 0 ] ) ; if ( code == ABS ) { set = gen_int_mode ( 0x7fffffff , SImode ) ; absneg_op = AND ; } else { set = gen_int_mode ( 0x80000000 , SImode ) ; absneg_op = XOR ; } set = gen_rtx_fmt_ee ( absneg_op , SImode , dst , set ) ; } break ; case E_XFmode : dst = gen_rtx_REG ( SImode , REGNO ( operands [ 0 ] ) + ( TARGET_64BIT ? 1 : 2 ) ) ; if ( code == ABS ) { set = GEN_INT ( 0x7fff ) ; absneg_op = AND ; } else { set = GEN_INT ( 0x8000 ) ; absneg_op = XOR ; } set = gen_rtx_fmt_ee ( absneg_op , SImode , dst , set ) ; break ; default : gcc_unreachable ( ) ; } set = gen_rtx_SET ( dst , set ) ; rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; rtvec par = gen_rtvec ( 2 , set , clob ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } </s>

Deconstruct a floating point ABS or NEG operation with integer registers into integer operations .


<s> bool ARMAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb" ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arm" ) return parseDirectiveARM ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb_func" ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".code" ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".syntax" ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arch" ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".eabi_attribute" ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".fnstart" ) return parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".fnend" ) return parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".cantunwind" ) return parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".personality" ) return parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".handlerdata" ) return parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".setfp" ) return parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".pad" ) return parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".save" ) return parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == ".vsave" ) return parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; return true ; } </s>


<s>
bool
SystemZInstrInfo
::
verifyInstruction
(
const
MachineInstr
&
MI
,
StringRef
&
ErrInfo
)
const
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
for
(
unsigned
I
=
0
,
E
=
MI
.
getNumOperands
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
>=
MCID
.
getNumOperands
(
)
)
break
;
const
MachineOperand
&
Op
=
MI
.
getOperand
(
I
)
;
const
MCOperandInfo
&
MCOI
=
MCID
.
OpInfo
[
I
]
;
if
(
MCOI
.
OperandType
==
MCOI
::
OPERAND_MEMORY
&&
(
(
MCOI
.
RegClass
!=
1
&&
!
Op
.
isReg
(
)
&&
!
Op
.
isFI
(
)
)
||
(
MCOI
.
RegClass
==
1
&&
!
Op
.
isImm
(
)
)
)
)
{
ErrInfo
=
"Addressing mode operands corrupt!"
;
return
false
;
}
}
return
true
;
}
</s>

Perform target-specific instruction verification .


<s> virtual const MCObjectFormat & getObjectFormat ( ) const { return Format ; } </s>


<s> static int sh_address_cost ( rtx x , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return 2 ; if ( REG_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return 1 ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == GBR_REG && gbr_displacement ( XEXP ( x , 1 ) , mode ) ) return 2 ; const HOST_WIDE_INT offset = INTVAL ( XEXP ( x , 1 ) ) ; if ( offset == 0 ) return 1 ; if ( offset > 0 && offset <= sh_max_mov_insn_displacement ( mode , false ) ) return ( mode == HImode || mode == QImode ) ? 2 : 1 ; if ( TARGET_SH2A && offset > 0 && offset <= sh_max_mov_insn_displacement ( mode , true ) ) return 2 ; return 3 ; } if ( GET_CODE ( x ) == PLUS && ! CONSTANT_P ( XEXP ( x , 1 ) ) ) return 3 ; return 10 ; } </s>

Compute the cost of an address . For the SH , all valid addresses are the same cost . Use a slightly higher cost for reg + reg addressing , since it increases pressure on r0 .


<s> bool PPCTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( Val ) ) { EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( MemVT == MVT :: i1 || MemVT == MVT :: i8 || MemVT == MVT :: i16 || ( Subtarget . isPPC64 ( ) && MemVT == MVT :: i32 ) ) && ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD || LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) ) return true ; } return TargetLowering :: isZExtFree ( Val , VT2 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> void ix86_expand_v1ti_shift ( enum rtx_code code , rtx operands [ ] ) { rtx op1 = force_reg ( V1TImode , operands [ 1 ] ) ; if ( ! CONST_INT_P ( operands [ 2 ] ) ) { rtx tmp1 = ix86_expand_v1ti_to_ti ( op1 ) ; rtx tmp2 = gen_reg_rtx ( TImode ) ; rtx ( * shift ) ( rtx , rtx , rtx ) = ( code == ASHIFT ) ? gen_ashlti3 : gen_lshrti3 ; emit_insn ( shift ( tmp2 , tmp1 , operands [ 2 ] ) ) ; rtx tmp3 = ix86_expand_ti_to_v1ti ( tmp2 ) ; emit_move_insn ( operands [ 0 ] , tmp3 ) ; return ; } HOST_WIDE_INT bits = INTVAL ( operands [ 2 ] ) & 127 ; if ( bits == 0 ) { emit_move_insn ( operands [ 0 ] , op1 ) ; return ; } if ( ( bits & 7 ) == 0 ) { rtx tmp = gen_reg_rtx ( V1TImode ) ; if ( code == ASHIFT ) emit_insn ( gen_sse2_ashlv1ti3 ( tmp , op1 , GEN_INT ( bits ) ) ) ; else emit_insn ( gen_sse2_lshrv1ti3 ( tmp , op1 , GEN_INT ( bits ) ) ) ; emit_move_insn ( operands [ 0 ] , tmp ) ; return ; } rtx tmp1 = gen_reg_rtx ( V1TImode ) ; if ( code == ASHIFT ) emit_insn ( gen_sse2_ashlv1ti3 ( tmp1 , op1 , GEN_INT ( 64 ) ) ) ; else emit_insn ( gen_sse2_lshrv1ti3 ( tmp1 , op1 , GEN_INT ( 64 ) ) ) ; rtx tmp2 = force_reg ( V2DImode , gen_lowpart ( V2DImode , tmp1 ) ) ; rtx tmp3 = gen_reg_rtx ( V2DImode ) ; if ( bits > 64 ) { if ( code == ASHIFT ) emit_insn ( gen_ashlv2di3 ( tmp3 , tmp2 , GEN_INT ( bits - 64 ) ) ) ; else emit_insn ( gen_lshrv2di3 ( tmp3 , tmp2 , GEN_INT ( bits - 64 ) ) ) ; } else { rtx tmp4 = force_reg ( V2DImode , gen_lowpart ( V2DImode , op1 ) ) ; rtx tmp5 = gen_reg_rtx ( V2DImode ) ; if ( code == ASHIFT ) emit_insn ( gen_ashlv2di3 ( tmp5 , tmp4 , GEN_INT ( bits ) ) ) ; else emit_insn ( gen_lshrv2di3 ( tmp5 , tmp4 , GEN_INT ( bits ) ) ) ; rtx tmp6 = gen_reg_rtx ( V2DImode ) ; if ( code == ASHIFT ) emit_insn ( gen_lshrv2di3 ( tmp6 , tmp2 , GEN_INT ( 64 - bits ) ) ) ; else emit_insn ( gen_ashlv2di3 ( tmp6 , tmp2 , GEN_INT ( 64 - bits ) ) ) ; emit_insn ( gen_iorv2di3 ( tmp3 , tmp5 , tmp6 ) ) ; } rtx tmp7 = force_reg ( V1TImode , gen_lowpart ( V1TImode , tmp3 ) ) ; emit_move_insn ( operands [ 0 ] , tmp7 ) ; } </s>

Expand V1TI mode shift ( of rtx_code CODE ) by constant .


<s> MachineInstr * SystemZInstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { auto cloneIfNew = [ NewMI ] ( MachineInstr & MI ) -> MachineInstr & { if ( NewMI ) return * MI . getParent ( ) -> getParent ( ) -> CloneMachineInstr ( & MI ) ; return MI ; } ; switch ( MI . getOpcode ( ) ) { case SystemZ :: SELRMux : case SystemZ :: SELFHR : case SystemZ :: SELR : case SystemZ :: SELGR : case SystemZ :: LOCRMux : case SystemZ :: LOCFHR : case SystemZ :: LOCR : case SystemZ :: LOCGR : { auto & WorkingMI = cloneIfNew ( MI ) ; unsigned CCValid = WorkingMI . getOperand ( 3 ) . getImm ( ) ; unsigned CCMask = WorkingMI . getOperand ( 4 ) . getImm ( ) ; WorkingMI . getOperand ( 4 ) . setImm ( CCMask ^ CCValid ) ; return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ; } default : return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

SystemZ SystemZ SystemZ::SELRMux SystemZ::SELFHR SystemZ::SELR SystemZ::SELGR SystemZ::LOCRMux SystemZ::LOCFHR SystemZ::LOCR SystemZ::LOCGR 3 4 4


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned NumOps = Inst . getNumOperands ( ) ; if ( NumOps == 0 ) return false ; switch ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ NumOps - 1 ] . OperandType ) { case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_IMMEDIATE : { uint64_t Region = Addr & ~ uint64_t ( 0xfffffff ) ; Target = Region + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; } case MCOI :: OPERAND_PCREL : Target = Addr + Inst . getOperand ( NumOps - 1 ) . getImm ( ) ; return true ; default : return false ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> static bool isShift ( MachineInstr * MI , int Opcode , int64_t Imm ) { return ( MI -> getOpcode ( ) == Opcode && ! MI -> getOperand ( 2 ) . getReg ( ) && MI -> getOperand ( 3 ) . getImm ( ) == Imm ) ; } </s>

Determine if the Opcode is one of the shift instructions .


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
machine_mode
mode
,
unsigned
width
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
=
{
NULL_RTX
,
0
,
0
,
false
,
false
}
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
mode
,
false
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
info
.
element_width
)
;
lane_count
=
width
/
info
.
element_width
;
mode
=
GET_MODE_INNER
(
mode
)
;
if
(
mode
==
SFmode
||
mode
==
DFmode
)
{
gcc_assert
(
info
.
shift
==
0
&&
!
info
.
mvn
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
REAL_VALUE_TYPE
r
;
REAL_VALUE_FROM_CONST_DOUBLE
(
r
,
info
.
value
)
;
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
&
r
,
buf_size
,
buf_size
,
1
,
mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
mnemonic
=
info
.
mvn
"mvni"
:
"movi"
;
shift_op
=
info
.
msl
"msl"
:
"lsl"
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
value
)
)
;
else
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
shift_op
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == 0 || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) * 4 ; Target = Addr + Imm ; return true ; } </s>


<s> static int zero_all_st_registers ( HARD_REG_SET need_zeroed_hardregs ) { if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) return 0 ; unsigned int num_of_st = 0 ; for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( STACK_REGNO_P ( regno ) || MMX_REGNO_P ( regno ) ) && TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { num_of_st ++ ; break ; } if ( num_of_st == 0 ) return 0 ; bool return_with_x87 = false ; return_with_x87 = ( crtl -> return_rtx && ( STACK_REG_P ( crtl -> return_rtx ) ) ) ; bool complex_return = false ; complex_return = ( crtl -> return_rtx && COMPLEX_MODE_P ( GET_MODE ( crtl -> return_rtx ) ) ) ; if ( return_with_x87 ) if ( complex_return ) num_of_st = 6 ; else num_of_st = 7 ; else num_of_st = 8 ; rtx st_reg = gen_rtx_REG ( XFmode , FIRST_STACK_REG ) ; for ( unsigned int i = 0 ; i < num_of_st ; i ++ ) emit_insn ( gen_rtx_SET ( st_reg , CONST0_RTX ( XFmode ) ) ) ; for ( unsigned int i = 0 ; i < num_of_st ; i ++ ) { rtx insn ; insn = emit_insn ( gen_rtx_SET ( st_reg , st_reg ) ) ; add_reg_note ( insn , REG_DEAD , st_reg ) ; } return num_of_st ; } </s>

Generate insns to zero all st registers together . Return true when zeroing instructions are generated . Assume the number of st registers that are zeroed is num_of_st , we will emit the following sequence to zero them together : fldz ; \ fldz ; \ ... fldz ; \ fstp % % st ( 0 ) ; \ fstp % % st ( 0 ) ; \ ... fstp % % st ( 0 ) ; i.e. , num_of_st fldz followed by num_of_st fstp to clear the stack mark stack slots empty . How to compute the num_of_st : There is no direct mapping from stack registers to hard register numbers . If one stack register needs to be cleared , we do n't know where in the stack the value remains . So , if any stack register needs to be cleared , the whole stack should be cleared . However , x87 stack registers that hold the return value should be excluded . x87 returns in the top ( two for complex values ) register , so num_of_st should be 7/6 when x87 returns , otherwise it will be 8 .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static rtx neon_vdup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( GET_CODE ( vals ) != CONST_VECTOR || GET_MODE_SIZE ( inner_mode ) > 4 ) return NULL_RTX ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_rtx_VEC_DUPLICATE ( mode , x ) ; } </s>

Return a non-NULL RTX iff VALS is a vector constant that can be loaded into a register using VDUP . If this is the case , and GENERATE is set , we also generate instructions to do this and return an RTX to assign to the register .


<s> void ARMRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; bool isThumb = AFI -> isThumbFunction ( ) ; ARMCC :: CondCodes Pred = isThumb ? ARMCC :: AL : ( ARMCC :: CondCodes ) Old -> getOperand ( 1 ) . getImm ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { unsigned PredReg = isThumb ? 0 : Old -> getOperand ( 2 ) . getReg ( ) ; emitSPUpdate ( MBB , I , - Amount , Pred , PredReg , isThumb , TII , * this , dl ) ; } else { unsigned PredReg = isThumb ? 0 : Old -> getOperand ( 3 ) . getReg ( ) ; assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , Amount , Pred , PredReg , isThumb , TII , * this , dl ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s> static void pa_init_libfuncs ( void ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( sqrt_optab , TFmode , "_U_Qfsqrt" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; set_optab_libfunc ( unord_optab , TFmode , "_U_Qfunord" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" : "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_usgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_udbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , SImode , "_U_Qfcnvxf_usgl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , "_U_Qfcnvxf_udbl_to_quad" ) ; } if ( TARGET_SYNC_LIBCALLS ) init_sync_libfuncs ( MAX_SYNC_LIBFUNC_SIZE ) ; } </s>

Initialize optabs to point to emulation routines .


<s> int pru_get_ctable_base_offset ( unsigned HOST_WIDE_INT caddr ) { int i ; i = pru_get_ctable_base_index ( caddr ) ; gcc_assert ( i >= 0 ) ; return caddr - pru_ctable [ i ] . base ; } </s>

Return the offset from some CTABLE base for this address .


<s> ARMSubtarget :: ARMSubtarget ( const Module & M , const std :: string & FS , bool isThumb ) : ARMArchVersion ( V4T ) , ARMFPUType ( None ) , IsThumb ( isThumb ) , ThumbMode ( Thumb1 ) , UseThumbBacktraces ( false ) , IsR9Reserved ( false ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; const std :: string & TT = M . getTargetTriple ( ) ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 6 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer > '4' && SubVer <= '9' ) { if ( SubVer >= '7' ) ARMArchVersion = V7A ; else if ( SubVer == '6' ) ARMArchVersion = V6 ; else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } } } if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } else if ( TT . empty ( ) ) { TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) { UseThumbBacktraces = true ; IsR9Reserved = true ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> MachineInstr * X86FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { return emitStackProbeInlineStub ( MF , MBB , MBBI , DL , true ) ; } else { return emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { return emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog ) ; } } </s>


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveX86CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } if ( TT . getArch ( ) == Triple :: x86_64 ) setMachineOutliner ( true ) ; initAsmInfo ( ) ; } </s>


<s> static unsigned long arm_compute_func_type ( void ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > 0 && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && ! USING_SJLJ_EXCEPTIONS ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; return type ; } </s>

Computes the type of the current function .


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_cleared_alloc < machine_function > ( ) ; f -> call_abi = ix86_abi ; return f ; } </s>

Clear stack slot assignments remembered from previous functions . This is called from INIT_EXPANDERS once before RTL is emitted for each function .


<s> void LC3RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case LC3 :: LDR : case LC3 :: STR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) + ImmOp . getImm ( ) ; FIOp . ChangeToRegister ( LC3 :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> int crx_interrupt_function_p ( void ) { tree attributes ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return lookup_attribute ( "interrupt" , attributes ) != NULL_TREE ; } </s>

Return nonzero if the current function being compiled is an interrupt * function as specified by the `` interrupt '' attribute .


<s> bool ARMBaseTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createARMISelDag ( * this , OptLevel ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> bool aarch64_emit_approx_sqrt ( rtx dst , rtx src , bool recp ) { machine_mode mode = GET_MODE ( dst ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) { gcc_assert ( ! recp ) ; return false ; } if ( ! recp ) { if ( ! ( flag_mlow_precision_sqrt || ( aarch64_tune_params . approx_modes -> sqrt & AARCH64_APPROX_MODE ( mode ) ) ) ) return false ; if ( flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) ) return false ; } else gcc_assert ( use_rsqrt_p ( mode ) ) ; machine_mode mmsk = mode_for_int_vector ( mode ) . require ( ) ; rtx xmsk = gen_reg_rtx ( mmsk ) ; if ( ! recp ) emit_insn ( gen_rtx_SET ( xmsk , gen_rtx_NEG ( mmsk , gen_rtx_EQ ( mmsk , src , CONST0_RTX ( mode ) ) ) ) ) ; rtx xdst = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , xdst , xdst ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x1 , src , x2 ) ) ; if ( iterations > 0 ) emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; } if ( ! recp ) { rtx xtmp = gen_reg_rtx ( mmsk ) ; emit_set_insn ( xtmp , gen_rtx_AND ( mmsk , gen_rtx_NOT ( mmsk , xmsk ) , gen_rtx_SUBREG ( mmsk , xdst , 0 ) ) ) ; emit_move_insn ( xdst , gen_rtx_SUBREG ( mode , xtmp , 0 ) ) ; emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , src ) ) ; } emit_set_insn ( dst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; return true ; } </s>

Emit instruction sequence to compute either the approximate square root or its approximate reciprocal , depending on the flag RECP , and return whether the sequence was emitted or not .


<s> TargetPassConfig * LC3bTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LC3bPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> CCAssignFn * CSKYTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC , bool IsVarArg ) const { if ( IsVarArg || ! Subtarget . useHardFloatABI ( ) ) return RetCC_CSKY_ABIV2_SOFT ; else return RetCC_CSKY_ABIV2_FP ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> unsigned getOffsetReg ( ) const { return OffsetReg ; } </s>

Get the offset register of the pointer value .


<s> const LegalizerInfo * ARMSubtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> static bool sh_asm_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_PIC : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; break ; case UNSPEC_GOT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOT" , file ) ; break ; case UNSPEC_GOTOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTOFF" , file ) ; break ; case UNSPEC_PLT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@PLT" , file ) ; break ; case UNSPEC_GOTPLT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTPLT" , file ) ; break ; case UNSPEC_PCREL : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@PCREL" , file ) ; break ; case UNSPEC_DTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@DTPOFF" , file ) ; break ; case UNSPEC_GOTTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTTPOFF" , file ) ; break ; case UNSPEC_TPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@TPOFF" , file ) ; break ; case UNSPEC_CALLER : { char name [ 32 ] ; targetm . asm_out . generate_internal_label ( name , "LPCS" , INTVAL ( XVECEXP ( x , 0 , 0 ) ) ) ; assemble_name ( file , name ) ; } break ; case UNSPEC_SYMOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputc ( '-' , file ) ; if ( GET_CODE ( XVECEXP ( x , 0 , 1 ) ) == CONST ) { fputc ( '(' , file ) ; output_addr_const ( file , XVECEXP ( x , 0 , 1 ) ) ; fputc ( ')' , file ) ; } else output_addr_const ( file , XVECEXP ( x , 0 , 1 ) ) ; break ; case UNSPEC_PCREL_SYMOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "-(" , file ) ; output_addr_const ( file , XVECEXP ( x , 0 , 1 ) ) ; fputs ( "-.)" , file ) ; break ; case UNSPEC_GOTFUNCDESC : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTFUNCDESC" , file ) ; break ; case UNSPEC_GOTOFFFUNCDESC : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTOFFFUNCDESC" , file ) ; break ; default : return false ; } return true ; } else return false ; } </s>


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = F . getFnAttribute ( "use-soft-float" ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> virtual bool runOnFunction ( Function & Fn ) { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnFunction ( Fn ) ; InsertVRSaveCode ( Fn ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
static
int
rs6000_sched_reorder2
(
FILE
*
dump
,
int
sched_verbose
,
rtx_insn
*
*
ready
,
int
*
pn_ready
,
int
clock_var
ATTRIBUTE_UNUSED
)
{
if
(
sched_verbose
)
fprintf
(
dump
,
"// rs6000_sched_reorder2 :\n"
)
;
if
(
rs6000_tune
==
PROCESSOR_POWER6
&&
last_scheduled_insn
)
return
power6_sched_reorder2
(
ready
,
*
pn_ready
1
)
;
if
(
rs6000_tune
==
PROCESSOR_POWER9
&&
last_scheduled_insn
&&
recog_memoized
(
last_scheduled_insn
)
>=
0
)
return
power9_sched_reorder2
(
ready
,
*
pn_ready
1
)
;
if
(
rs6000_tune
==
PROCESSOR_POWER10
&&
last_scheduled_insn
)
return
power10_sched_reorder
(
ready
,
*
pn_ready
1
)
;
return
cached_can_issue_more
;
}
</s>

Like rs6000_sched_reorder , but called after issuing each insn .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MipsSubtarget & Subtarget = MF -> getSubtarget < MipsSubtarget > ( ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( Subtarget . hasMips64 ( ) ) return Subtarget . hasMips64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . hasMips32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>

Mips Mips Mips Mips "interrupt" Mips Mips Mips


<s> void ARMHazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugInstr ( ) ) { LastMI = MI ; FpMLxStalls = 0 ; } ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool X86InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> static rtx altivec_expand_ld_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 ; machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_load_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_load_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_vector_altivec_load_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_load_v4sf ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2df : icode = CODE_FOR_vector_altivec_load_v2df ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2di : icode = CODE_FOR_vector_altivec_load_v2di ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_load_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ 0 ] . mode ; mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> void Mips16FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TII . adjustStackPtr ( Mips :: SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips Mips Mips::SP


<s> void MipsFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; unsigned NewReg = 0 ; int NewImm = 0 ; bool ATUsed = false ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; ATUsed = expandRegLargeImmPair ( Mips :: SP , FPOffset , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: FP ) . addImm ( NewImm ) . addReg ( NewReg ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ATMACRO ) ) ; } if ( MFI -> adjustsStack ( ) ) { expandRegLargeImmPair ( Mips :: SP , RAOffset , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) , Mips :: RA ) . addImm ( NewImm ) . addReg ( NewReg ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ATMACRO ) ) ; } if ( NumBytes ) { expandRegLargeImmPair ( Mips :: SP , NumBytes , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( NewReg ) . addImm ( NewImm ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ATMACRO ) ) ; } } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 0 Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::SP Mips::LW Mips::FP Mips::ATMACRO Mips::SP Mips::LW Mips::RA Mips::ATMACRO Mips::SP Mips::ADDiu Mips::SP Mips::ATMACRO


<s>
void
PPCDispatchGroupSBHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCInstrDesc
*
MCID
=
DAG
->
getInstrDesc
(
SU
)
;
if
(
MCID
)
{
if
(
CurSlots
==
5
||
(
MCID
->
isBranch
(
)
&&
CurBranches
==
1
)
)
{
CurGroup
.
clear
(
)
;
CurSlots
=
CurBranches
=
0
;
}
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"**** Adding to dispatch group: "
)
;
LLVM_DEBUG
(
DAG
->
dumpNode
(
*
SU
)
)
;
unsigned
NSlots
;
bool
MustBeFirst
=
mustComeFirst
(
MCID
,
NSlots
)
;
if
(
MustBeFirst
&&
CurSlots
)
{
CurSlots
=
CurBranches
=
0
;
CurGroup
.
clear
(
)
;
}
CurSlots
+=
NSlots
;
CurGroup
.
push_back
(
SU
)
;
if
(
MCID
->
isBranch
(
)
)
++
CurBranches
;
}
}
return
ScoreboardHazardRecognizer
::
EmitInstruction
(
SU
)
;
}
</s>


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


"All AArch64 cmps should have 2 operands"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> const TargetRegisterClass * ThumbRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ) return ARMBaseRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; if ( ARM :: tGPRRegClass . hasSubClassEq ( RC ) ) return & ARM :: tGPRRegClass ; return ARMBaseRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM ARM::tGPRRegClass ARM::tGPRRegClass ARM


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static unsigned rs6000_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { if ( unroll_only_small_loops ) { if ( loop -> ninsns <= 6 ) return MIN ( 4 , nunroll ) ; if ( loop -> ninsns <= 10 ) return MIN ( 2 , nunroll ) ; return 0 ; } return nunroll ; } </s>


<s> rtx rs6000_gen_stvx ( enum machine_mode mode , rtx dest_exp , rtx src_exp ) { rtx stvx ; if ( mode == V16QImode ) stvx = gen_altivec_stvx_v16qi ( src_exp , dest_exp ) ; else if ( mode == V8HImode ) stvx = gen_altivec_stvx_v8hi ( src_exp , dest_exp ) ; else if ( mode == V8HFmode ) stvx = gen_altivec_stvx_v8hf ( src_exp , dest_exp ) ; else if ( mode == V4SImode ) stvx = gen_altivec_stvx_v4si ( src_exp , dest_exp ) ; else if ( mode == V4SFmode ) stvx = gen_altivec_stvx_v4sf ( src_exp , dest_exp ) ; else if ( mode == V2DImode ) stvx = gen_altivec_stvx_v2di ( src_exp , dest_exp ) ; else if ( mode == V2DFmode ) stvx = gen_altivec_stvx_v2df ( src_exp , dest_exp ) ; else if ( mode == V1TImode ) stvx = gen_altivec_stvx_v1ti ( src_exp , dest_exp ) ; else gcc_unreachable ( ) ; rtx new_mem_exp = SET_DEST ( PATTERN ( stvx ) ) ; mimic_memory_attributes_and_flags ( new_mem_exp , dest_exp ) ; return stvx ; } </s>

Generate an rtx expression to represent use of the stvx insn to store the value represented by register SRC_EXP into the memory at address DEST_EXP , with vector mode MODE .


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 0 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


"Unexpected instruction type for reassociation"

"Must have dead EFLAGS operand in reassociable instruction"

"Unexpected operand in reassociable instruction"

This is an architecture-specific helper function of reassociateOps .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool xstormy16_rtx_costs ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : if ( INTVAL ( x ) < 16 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) / 2 ; else if ( INTVAL ( x ) < 256 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( 2 ) ; return true ; case MULT : * total = COSTS_N_INSNS ( 35 + 6 ) ; return true ; case DIV : * total = COSTS_N_INSNS ( 51 - 6 ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s>
bool
SparcAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
static
unsigned
BBNumber
=
0
;
O
<<
"\n\n"
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
F
)
)
;
EmitAlignment
(
4
,
F
)
;
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.type\t"
<<
CurrentFnName
<<
", #function\n"
;
O
<<
CurrentFnName
<<
":\n"
;
NumberForBB
.
clear
(
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
NumberForBB
[
I
->
getBasicBlock
(
)
]
=
BBNumber
++
;
}
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printInstruction
(
II
)
;
++
EmittedInsts
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,4]"

"immediate operand must be in the range [0,15]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case 'x' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( Is64Bit ) ; else Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = NULL ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> const TargetRegisterClass * MipsRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return Subtarget . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool isLiveIn ( int FI ) { for ( unsigned i = 0 , e = LiveInFI . size ( ) ; i < e ; ++ i ) if ( FI == LiveInFI [ i ] ) return true ; return false ; } </s>

Returns true if this VPValue is a live-in , i.e . defined outside the VPlan .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMachObjectWriter ( OS , false , object :: mach :: CTM_ARM , object :: mach :: CSARM_V7 , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static struct machine_function * rs6000_init_machine_status ( void ) { return ggc_alloc_cleared ( sizeof ( machine_function ) ) ; } </s>

Functions to init , mark and free struct machine_function . These will be called , via pointer variables , from push_function_context and pop_function_context .


<s>
int
ARM64AsmParser
::
tryParseRegister
(
)
{
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
unsigned
RegNum
=
MatchRegisterName
(
lowerCase
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
ARM64
::
FP
)
.
Case
(
"lr"
,
ARM64
::
LR
)
.
Case
(
"x31"
,
ARM64
::
XZR
)
.
Case
(
"w31"
,
ARM64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


<s> unsigned getPrefetchDistance ( ) const override { return PrefetchDistance ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> static void mips_move_integer ( rtx dest , unsigned HOST_WIDE_INT value ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; enum machine_mode mode ; unsigned int i , cost ; rtx x ; mode = GET_MODE ( dest ) ; cost = mips_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < cost ; i ++ ) { if ( no_new_pseudos ) emit_move_insn ( dest , x ) , x = dest ; else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } </s>


<s> unsigned FISCAsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> StringRef getPassName ( ) const override { return AARCH64_LOAD_STORE_OPT_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static rtx loongarch_got_load_tls_ie ( rtx dest , rtx sym ) { return gen_got_load_tls_ie ( Pmode , dest , sym ) ; } </s>

Load an entry from the GOT for a TLS IE access .


Return a register that is zero if CMP0 and CMP1 are equal . The register will have the same mode as CMP0 .


<s> int mmix_reversible_cc_mode ( enum machine_mode mode ) { return mode != CC_FPmode ; } </s>


<s> enum reg_class nds32_regno_reg_class ( int regno ) { if ( regno >= 0 && regno <= 7 ) return LOW_REGS ; else if ( regno >= 8 && regno <= 11 ) return MIDDLE_REGS ; else if ( regno >= 12 && regno <= 14 ) return HIGH_REGS ; else if ( regno == 15 ) return R15_TA_REG ; else if ( regno >= 16 && regno <= 19 ) return MIDDLE_REGS ; else if ( regno >= 20 && regno <= 31 ) return HIGH_REGS ; else if ( regno == 32 || regno == 33 ) { return GENERAL_REGS ; } else if ( regno >= 34 && regno <= 97 ) return FP_REGS ; else return NO_REGS ; } </s>


<s> virtual const MandarinSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool PPCRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { return PhysReg != PPC :: R1 && PhysReg != PPC :: X1 ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s>
void
CSKYAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Kind
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
bool
IsLittleEndian
=
(
Endian
==
support
::
little
)
;
bool
IsInstFixup
=
(
Kind
>=
FirstTargetFixupKind
)
;
if
(
IsLittleEndian
&&
IsInstFixup
&&
(
NumBytes
==
4
)
)
{
Data
[
Offset
+
0
]
|=
uint8_t
(
(
Value
>>
16
)
&
0xff
)
;
Data
[
Offset
+
1
]
|=
uint8_t
(
(
Value
>>
24
)
&
0xff
)
;
Data
[
Offset
+
2
]
|=
uint8_t
(
Value
&
0xff
)
;
Data
[
Offset
+
3
]
|=
uint8_t
(
(
Value
>>
8
)
&
0xff
)
;
}
else
{
for
(
unsigned
I
=
0
;
I
!=
NumBytes
;
I
++
)
{
unsigned
Idx
=
IsLittleEndian
I
:
(
NumBytes
1
I
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
I
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool PPCInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , unsigned ExtraT , MachineBasicBlock & FMBB , unsigned NumF , unsigned ExtraF , const BranchProbability & Probability ) const { return ! ( MBBDefinesCTR ( TMBB ) && MBBDefinesCTR ( FMBB ) ) ; } </s>