<s> static sbitmap aarch64_get_separate_components ( void ) { aarch64_layout_frame ( ) ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { HOST_WIDE_INT offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg2 ) ; if ( reg1 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg1 ) ; bitmap_clear_bit ( components , LR_REGNUM ) ; bitmap_clear_bit ( components , SP_REGNUM ) ; return components ; } </s>


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
LLVM_FALLTHROUGH
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Um
:
case
InlineAsm
::
Constraint_Un
:
case
InlineAsm
::
Constraint_Uq
:
case
InlineAsm
::
Constraint_Us
:
case
InlineAsm
::
Constraint_Ut
:
case
InlineAsm
::
Constraint_Uv
:
case
InlineAsm
::
Constraint_Uy
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"Unexpected asm memory constraint"


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { return ( IsGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } if ( Constraint [ 0 ] == '{' ) { if ( Constraint [ 1 ] == 'r' ) { if ( VT == MVT :: i32 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR32BitRegClass , SystemZMC :: GR32Regs ) ; if ( VT == MVT :: i128 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR128BitRegClass , SystemZMC :: GR128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: GR64BitRegClass , SystemZMC :: GR64Regs ) ; } if ( Constraint [ 1 ] == 'f' ) { if ( VT == MVT :: f32 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP32BitRegClass , SystemZMC :: FP32Regs ) ; if ( VT == MVT :: f128 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP128BitRegClass , SystemZMC :: FP128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: FP64BitRegClass , SystemZMC :: FP64Regs ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"RESTORE_ACC does not define its destination"

lowerACCRestore - Generate the code to restore the accumulator register .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ARMISD :: VMOVRRD : return PerformVMOVRRDCombine ( N , DCI ) ; case ARMISD :: VMOVDRR : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case ISD :: BUILD_VECTOR : return PerformBUILD_VECTORCombine ( N , DCI . DAG ) ; case ISD :: VECTOR_SHUFFLE : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case ARMISD :: VDUPLANE : return PerformVDUPLANECombine ( N , DCI ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SELECT_CC : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
bool
X86InstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid X86 branch condition!"
)
;
X86
::
CondCode
CC
=
static_cast
<
X86
::
CondCode
>
(
Cond
[
0
]
.
getImm
(
)
)
;
Cond
[
0
]
.
setImm
(
GetOppositeBranchCondition
(
CC
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> void split_ti ( rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { while ( num -- ) { rtx op = operands [ num ] ; if ( GET_CODE ( op ) == MEM ) { lo_half [ num ] = adjust_address ( op , DImode , 0 ) ; hi_half [ num ] = adjust_address ( op , DImode , 8 ) ; } else { lo_half [ num ] = simplify_gen_subreg ( DImode , op , TImode , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( DImode , op , TImode , 8 ) ; } } } </s>

Split one or more TImode RTL references into pairs of DImode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of DImode RTL to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


"the ABI for passing parameters with %d-byte"

Gives the alignment boundary , in bits , of an argument with the specified mode and type .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = DistributeIncrements ( ) ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool originalTypeIsF128 ( const Type * Ty , const SDNode * CallNode ) { if ( Ty -> isFP128Ty ( ) ) return true ; const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( CallNode ) ; return ( ES && Ty -> isIntegerTy ( 128 ) && isF128SoftLibCall ( ES -> getSymbol ( ) ) ) ; } </s>

This function returns true if Ty is fp128 , { f128 } or i128 which was originally a fp128 .


<s> static bool arm_block_set_non_vect_profit_p ( rtx val , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT align , bool unaligned_p , bool use_strd_p ) { int num = 0 ; const int leftover [ 8 ] = { 0 , 1 , 1 , 2 , 1 , 2 , 2 , 3 } ; if ( unaligned_p ) { num = arm_const_inline_cost ( SET , val ) ; num += length / align + length % align ; } else if ( use_strd_p ) { num = arm_const_double_inline_cost ( val ) ; num += ( length >> 3 ) + leftover [ length & 7 ] ; } else { num = arm_const_inline_cost ( SET , val ) ; num += ( length >> 2 ) + leftover [ length & 3 ] ; } if ( unaligned_access && length > 3 && ( length & 3 ) == 3 ) num -- ; return ( num <= arm_block_set_max_insns ( ) ) ; } </s>

Return TRUE if it 's profitable to set block of memory for non-vectorized case . VAL is the value to set the memory with . LENGTH is the number of bytes to set . ALIGN is the alignment of the destination memory in bytes . UNALIGNED_P is TRUE if we can only set the memory with instructions meeting alignment requirements . USE_STRD_P is TRUE if we can use strd to set the memory .


<s> static rtx_insn * calculate_pic_address_constant ( rtx reg , rtx pic_reg , rtx orig ) { rtx pat ; rtx mem ; pat = gen_calculate_pic_address ( reg , pic_reg , orig ) ; mem = SET_SRC ( pat ) ; gcc_assert ( MEM_P ( mem ) && ! MEM_VOLATILE_P ( mem ) ) ; MEM_READONLY_P ( mem ) = 1 ; MEM_NOTRAP_P ( mem ) = 1 ; return emit_insn ( pat ) ; } </s>

Generate insns to calculate the address of ORIG in pic mode .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool ix86_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( must_pass_in_stack_var_size_or_pad ( mode , type ) ) return true ; return ( ! TARGET_64BIT && mode == TImode && type && TREE_CODE ( type ) != VECTOR_TYPE ) ; } </s>

Return if we do not know how to pass TYPE solely in registers .


<s> static bool have_compare_and_set_mask ( machine_mode mode ) { switch ( mode ) { case E_SFmode : case E_DFmode : return TARGET_P9_MINMAX ; default : break ; } return false ; } </s>

Helper function to return true if the target has instructions to do a compare and set mask instruction that can be used with XXSEL to implement a conditional move . It is also assumed that such a target also supports the `` C '' minimum and maximum instructions .


<s> void PPCAsmPrinter :: PrintSymbolOperand ( const MachineOperand & MO , raw_ostream & O ) { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( Subtarget -> hasLazyResolverStub ( GV ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } SymToPrint -> print ( O , MAI ) ; printOffset ( MO . getOffset ( ) , O ) ; } </s>


<s> void mmix_setup_frame_addresses ( ) { } </s>


<s> BitVector SHUXIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SHUXI :: SR ) ; Reserved . set ( SHUXI :: PC ) ; Reserved . set ( SHUXI :: SP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

SHUXI SHUXI SHUXI::SR SHUXI::PC SHUXI::SP


<s> SDValue X86TargetLowering :: getSqrtEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) && Reciprocal ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE2 ( ) && ! Reciprocal ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) || ( VT == MVT :: v16f32 && Subtarget . useAVX512Regs ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; UseOneConstNR = false ; unsigned Opcode = VT == MVT :: v16f32 ? X86ISD :: RSQRT14 : X86ISD :: FRSQRT ; return DAG . getNode ( Opcode , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> void AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) { addPass ( createAArch64AdvSIMDScalar ( ) ) ; addPass ( & PeepholeOptimizerID ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"; WARNING: The following code is valid only with MASM v8.x"

"; This version of MASM is usually shipped with Microsoft "

"; or (possible) further versions. Unfortunately, there is no "

"; dllexported symbols in the earlier versions of MASM in fully "

"_drectve\t segment info alias('.drectve')\n"

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool lwsp_swsp_address_p ( rtx x , machine_mode mode ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && REGNO ( addr . reg ) == STACK_POINTER_REGNUM && uw5_operand ( addr . offset , mode ) ) ; } </s>

Return true if X is a legitimate address that conforms to the requirements for a microMIPS LWSP or SWSP insn .


<s> static rtx_insn * arm_pic_static_addr ( rtx orig , rtx reg ) { rtx l1 , labelno , offset_rtx ; rtx_insn * insn ; gcc_assert ( flag_pic ) ; bool is_readonly = false ; bool info_known = false ; if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ! SYMBOL_REF_FUNCTION_P ( orig ) ) info_known = arm_is_segment_info_known ( orig , & is_readonly ) ; if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ! SYMBOL_REF_FUNCTION_P ( orig ) && ! info_known ) { rtx pic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; insn = calculate_pic_address_constant ( reg , pic_reg , orig ) ; } else if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ( SYMBOL_REF_FUNCTION_P ( orig ) || ! is_readonly ) ) { rtx pic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; rtx l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , orig ) , UNSPEC_PIC_SYM ) ; emit_insn ( gen_movsi ( reg , l1 ) ) ; insn = emit_insn ( gen_addsi3 ( reg , reg , pic_reg ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; offset_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; offset_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , orig , offset_rtx ) , UNSPEC_SYMBOL_OFFSET ) ; offset_rtx = gen_rtx_CONST ( Pmode , offset_rtx ) ; insn = emit_insn ( gen_pic_load_addr_unified ( reg , offset_rtx , labelno ) ) ; } return insn ; } </s>

Generate code to load the address of a static var when flag_pic is set .


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createX86ISelDag ( * this , getOptLevel ( ) ) ) ; if ( ! Subtarget . is64Bit ( ) ) PM . add ( createGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( VECTOR_MEM_VSX_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


<s> bool rs6000_builtin_is_supported_p ( enum rs6000_builtins fncode ) { HOST_WIDE_INT fnmask = rs6000_builtin_info [ fncode ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) return false ; else return true ; } </s>

Check whether a builtin function is supported in this target configuration .


<s> void PPCRegisterInfo :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = PPCFrameInfo :: getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> bool PPCTTIImpl :: canSaveCmp ( Loop * L , BranchInst * * BI , ScalarEvolution * SE , LoopInfo * LI , DominatorTree * DT , AssumptionCache * AC , TargetLibraryInfo * LibInfo ) { for ( Loop * I : * L ) if ( canSaveCmp ( I , BI , SE , LI , DT , AC , LibInfo ) ) return false ; HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) return false ; if ( ! isHardwareLoopProfitable ( L , * SE , * AC , LibInfo , HWLoopInfo ) ) return false ; if ( ! HWLoopInfo . isHardwareLoopCandidate ( * SE , * LI , * DT ) ) return false ; * BI = HWLoopInfo . ExitBranch ; return true ; } </s>

Return true if the target can save a compare for loop count , for example hardware loop saves a compare .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_APCS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( Subtarget ) { } </s>


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( C ) ) return PPCMaterializeInt ( CI , VT , false ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s>
unsigned
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
}
else
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool AArch64FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static void emit_split_stack_prologue ( rs6000_stack_t * info , rtx_insn * sp_adjust , HOST_WIDE_INT frame_off , rtx frame_reg_rtx ) { cfun -> machine -> split_stack_argp_used = true ; if ( sp_adjust ) { rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx sp_reg_rtx = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx set_r12 = gen_rtx_SET ( r12 , sp_reg_rtx ) ; emit_insn_before ( set_r12 , sp_adjust ) ; } else if ( frame_off != 0 || REGNO ( frame_reg_rtx ) != 12 ) { rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; if ( frame_off == 0 ) emit_move_insn ( r12 , frame_reg_rtx ) ; else emit_insn ( gen_add3_insn ( r12 , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; } if ( info -> push_p ) { rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx r29 = gen_rtx_REG ( Pmode , 29 ) ; rtx cr7 = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; rtx not_more = gen_label_rtx ( ) ; rtx jump ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , cr7 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , not_more ) , pc_rtx ) ; jump = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( jump ) = not_more ; LABEL_NUSES ( not_more ) += 1 ; emit_move_insn ( r12 , r29 ) ; emit_label ( not_more ) ; } } </s>

Set up the arg pointer ( r12 ) for -fsplit-stack code . If __morestack was called , it left the arg pointer to the old stack in r29 . Otherwise , the arg pointer is the top of the current frame .


<s> bool nds32_n10_ex_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { gcc_assert ( get_attr_type ( producer ) == TYPE_FLOAD || get_attr_type ( producer ) == TYPE_FSTORE ) ; gcc_assert ( get_attr_type ( consumer ) == TYPE_FLOAD || get_attr_type ( consumer ) == TYPE_FSTORE ) ; if ( ! post_update_insn_p ( producer ) ) return false ; return reg_overlap_p ( extract_base_reg ( producer ) , extract_mem_rtx ( consumer ) ) ; } </s>

Check dependencies from EX to EX ( ADDR_OUT - > ADDR_IN ) .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> static bool cortex_a9_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { switch ( REG_NOTE_KIND ( link ) ) { case REG_DEP_ANTI : * cost = 0 ; return false ; case REG_DEP_TRUE : case REG_DEP_OUTPUT : if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { if ( GET_MODE_CLASS ( GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ) == MODE_FLOAT || GET_MODE_CLASS ( GET_MODE ( SET_SRC ( PATTERN ( insn ) ) ) ) == MODE_FLOAT ) { enum attr_type attr_type_insn = get_attr_type ( insn ) ; enum attr_type attr_type_dep = get_attr_type ( dep ) ; if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - 3 ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + 1 ; else * cost = insn_default_latency ( dep ) ; } return false ; } } } } break ; default : gcc_unreachable ( ) ; } return true ; } </s>


<s> rtx sh_get_fdpic_reg_initial_val ( void ) { return get_hard_reg_initial_val ( Pmode , PIC_REG ) ; } </s>

Return an rtx holding the initial value of the FDPIC register ( the FDPIC pointer passed in from the caller ) .


<s> static void ia64_vms_init_libfuncs ( void ) { set_optab_libfunc ( sdiv_optab , SImode , "OTS$DIV_I" ) ; set_optab_libfunc ( sdiv_optab , DImode , "OTS$DIV_L" ) ; set_optab_libfunc ( udiv_optab , SImode , "OTS$DIV_UI" ) ; set_optab_libfunc ( udiv_optab , DImode , "OTS$DIV_UL" ) ; set_optab_libfunc ( smod_optab , SImode , "OTS$REM_I" ) ; set_optab_libfunc ( smod_optab , DImode , "OTS$REM_L" ) ; set_optab_libfunc ( umod_optab , SImode , "OTS$REM_UI" ) ; set_optab_libfunc ( umod_optab , DImode , "OTS$REM_UL" ) ; MEM_LIBFUNCS_INIT ; } </s>

Rename the division and modulus functions in VMS .


<s> void LC3bAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MCInst TmpInst0 ; MCInstLowering . Lower ( MI , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void xstormy16_expand_call ( rtx retval , rtx dest , rtx counter ) { rtx call , temp ; machine_mode mode ; gcc_assert ( MEM_P ( dest ) ) ; dest = XEXP ( dest , 0 ) ; if ( ! CONSTANT_P ( dest ) && ! REG_P ( dest ) ) dest = force_reg ( Pmode , dest ) ; if ( retval == NULL ) mode = VOIDmode ; else mode = GET_MODE ( retval ) ; call = gen_rtx_CALL ( mode , gen_rtx_MEM ( FUNCTION_MODE , dest ) , counter ) ; if ( retval ) call = gen_rtx_SET ( retval , call ) ; if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode ) ; emit_move_insn ( temp , const0_rtx ) ; } else temp = const0_rtx ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , call , gen_rtx_USE ( VOIDmode , temp ) ) ) ; emit_call_insn ( call ) ; } </s>

Expander for the ` call ' patterns . INDEX is the index of the switch statement . LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding to the first table entry . RANGE is the number of table entries . TABLE is an ADDR_VEC that is the jump table . DEFAULT_LABEL is the address to branch to if INDEX is outside the range LOWER_BOUND to LOWER_BOUND+RANGE-1 .


<s> MachineBasicBlock :: instr_iterator skip ( MachineBasicBlock * MBB , unsigned Index ) { auto I = MBB -> instr_begin ( ) ; auto E = MBB -> instr_end ( ) ; unsigned Cur = 0 ; while ( I != E && Cur != Index ) ++ I , ++ Cur ; return ++ I ; } </s>

Advance the Cursor position by the given number of bytes .


<s> unsigned postKnownBits ( Align Align = llvm :: Align ( 1 ) ) const { return std :: max ( Log2 ( std :: max ( PostAlign , Align ) ) , internalKnownBits ( ) ) ; } </s>

Compute the number of known low bits of postOffset .


<s> bool PPCSubtarget :: isPPC64 ( ) const { return TM . isPPC64 ( ) ; } </s>

Tests whether the target is 64-bit PowerPC ( little and big endian ) .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . readMem = false ; Info . writeMem = false ; Info . vol = false ; Info . offset = 0 ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = 1 ; Info . readMem = true ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case STOREANT : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = Info . memVT . getSizeInBits ( ) / 8 ; Info . writeMem = true ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { struct cl_target_option cl_opts ; if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; cl_target_option_save ( & cl_opts , opts , opts_set ) ; arm_configure_build_target ( & arm_active_target , & cl_opts , false ) ; arm_option_check_internal ( opts ) ; arm_option_reconfigure_globals ( ) ; arm_options_perform_arch_sanity_checks ( ) ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts , opts_set ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s> bool SystemZInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumCyclesT , unsigned ExtraPredCyclesT , MachineBasicBlock & FMBB , unsigned NumCyclesF , unsigned ExtraPredCyclesF , const BranchProbability & Probability ) const { return false ; } </s>


<s> const char * mips16e_output_save_restore ( rtx pattern , HOST_WIDE_INT adjust ) { static char buffer [ 300 ] ; struct mips16e_save_restore_info info ; unsigned int i , end ; char * s ; if ( ! mips16e_save_restore_pattern_p ( pattern , adjust , & info ) ) gcc_unreachable ( ) ; s = strcpy ( buffer , adjust > 0 ? "restore\t" : "save\t" ) ; s += strlen ( s ) ; if ( info . nargs > 1 ) s += sprintf ( s , "%s-%s," , reg_names [ GP_ARG_FIRST ] , reg_names [ GP_ARG_FIRST + info . nargs - 1 ] ) ; else if ( info . nargs == 1 ) s += sprintf ( s , "%s," , reg_names [ GP_ARG_FIRST ] ) ; s += sprintf ( s , "%d" , ( int ) info . size ) ; if ( BITSET_P ( info . mask , 16 ) ) s += sprintf ( s , ",%s" , reg_names [ GP_REG_FIRST + 16 ] ) ; if ( BITSET_P ( info . mask , 17 ) ) s += sprintf ( s , ",%s" , reg_names [ GP_REG_FIRST + 17 ] ) ; end = ARRAY_SIZE ( mips16e_s2_s8_regs ) ; i = mips16e_find_first_register ( info . mask , mips16e_s2_s8_regs , end ) ; if ( i < end ) s = mips16e_add_register_range ( s , mips16e_s2_s8_regs [ end - 1 ] , mips16e_s2_s8_regs [ i ] ) ; end = ARRAY_SIZE ( mips16e_a0_a3_regs ) ; i = mips16e_find_first_register ( info . mask , mips16e_a0_a3_regs , end ) ; if ( i < end ) s = mips16e_add_register_range ( s , mips16e_a0_a3_regs [ i ] , mips16e_a0_a3_regs [ end - 1 ] ) ; if ( BITSET_P ( info . mask , RETURN_ADDR_REGNUM ) ) s += sprintf ( s , ",%s" , reg_names [ RETURN_ADDR_REGNUM ] ) ; return buffer ; } </s>

Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction . PATTERN and ADJUST are as for mips16e_save_restore_pattern_p .


<s> static tree ix86_builtin_mpx_function ( unsigned fcode ) { switch ( fcode ) { case BUILT_IN_CHKP_BNDMK : return ix86_builtins [ IX86_BUILTIN_BNDMK ] ; case BUILT_IN_CHKP_BNDSTX : return ix86_builtins [ IX86_BUILTIN_BNDSTX ] ; case BUILT_IN_CHKP_BNDLDX : return ix86_builtins [ IX86_BUILTIN_BNDLDX ] ; case BUILT_IN_CHKP_BNDCL : return ix86_builtins [ IX86_BUILTIN_BNDCL ] ; case BUILT_IN_CHKP_BNDCU : return ix86_builtins [ IX86_BUILTIN_BNDCU ] ; case BUILT_IN_CHKP_BNDRET : return ix86_builtins [ IX86_BUILTIN_BNDRET ] ; case BUILT_IN_CHKP_INTERSECT : return ix86_builtins [ IX86_BUILTIN_BNDINT ] ; case BUILT_IN_CHKP_NARROW : return ix86_builtins [ IX86_BUILTIN_BNDNARROW ] ; case BUILT_IN_CHKP_SIZEOF : return ix86_builtins [ IX86_BUILTIN_SIZEOF ] ; case BUILT_IN_CHKP_EXTRACT_LOWER : return ix86_builtins [ IX86_BUILTIN_BNDLOWER ] ; case BUILT_IN_CHKP_EXTRACT_UPPER : return ix86_builtins [ IX86_BUILTIN_BNDUPPER ] ; default : return NULL_TREE ; } gcc_unreachable ( ) ; } </s>

Return function decl for target specific builtin for given MPX builtin passed i FCODE .


<s> void XNCMAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { XNCMMCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>


"Pseudo opcode found in emitInstruction()"

Targets should implement this to emit instructions .


<s> const F2003fSubtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static rtx aarch64_expand_fpsr_fpcr_getter ( enum insn_code icode , machine_mode mode , rtx target ) { expand_operand op ; create_output_operand ( & op , target , mode ) ; expand_insn ( icode , 1 , & op ) ; return op . value ; } </s>

Expand a fpsr or fpcr getter ( depending on UNSPEC ) using MODE . Return the target .


<s> const SICTargetMachine & getTargetMachine ( ) { return static_cast < const SICTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( PPC :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> void sparc_emit_call_insn ( rtx pat , rtx addr ) { rtx_insn * insn ; insn = emit_call_insn ( pat ) ; if ( TARGET_VXWORKS_RTP && flag_pic && GET_CODE ( addr ) == SYMBOL_REF && ( SYMBOL_REF_DECL ( addr ) ? ! targetm . binds_local_p ( SYMBOL_REF_DECL ( addr ) ) : ! SYMBOL_REF_LOCAL_P ( addr ) ) ) { use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , pic_offset_table_rtx ) ; crtl -> uses_pic_offset_table = 1 ; } } </s>

Emit a call instruction with the pattern given by PAT . ADDR is the address of the call target .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
&
STI
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
llvm
::
none_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
->
begin
(
)
,
MLI
->
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static bool is_branch ( rtx_insn * insn ) { return ( CALL_P ( insn ) || JUMP_P ( insn ) ) ; } </s>

Return true if insn is a branch instruction .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> void aarch64_expand_sve_vec_perm ( rtx target , rtx op0 , rtx op1 , rtx sel ) { machine_mode data_mode = GET_MODE ( target ) ; machine_mode sel_mode = GET_MODE ( sel ) ; int nunits = GET_MODE_NUNITS ( sel_mode ) . to_constant ( ) ; rtx sel_reg = force_reg ( sel_mode , sel ) ; if ( GET_CODE ( sel ) == CONST_VECTOR && aarch64_const_vec_all_in_range_p ( sel , 0 , nunits - 1 ) ) { emit_unspec2 ( target , UNSPEC_TBL , op0 , sel_reg ) ; return ; } if ( rtx_equal_p ( op0 , op1 ) ) { rtx max_sel = aarch64_simd_gen_const_vector_dup ( sel_mode , nunits - 1 ) ; rtx sel_mod = expand_simple_binop ( sel_mode , AND , sel_reg , max_sel , NULL , 0 , OPTAB_DIRECT ) ; emit_unspec2 ( target , UNSPEC_TBL , op0 , sel_mod ) ; return ; } rtx res0 = gen_reg_rtx ( data_mode ) ; rtx res1 = gen_reg_rtx ( data_mode ) ; rtx neg_num_elems = aarch64_simd_gen_const_vector_dup ( sel_mode , - nunits ) ; if ( GET_CODE ( sel ) != CONST_VECTOR || ! aarch64_const_vec_all_in_range_p ( sel , 0 , 2 * nunits - 1 ) ) { rtx max_sel = aarch64_simd_gen_const_vector_dup ( sel_mode , 2 * nunits - 1 ) ; sel_reg = expand_simple_binop ( sel_mode , AND , sel_reg , max_sel , NULL , 0 , OPTAB_DIRECT ) ; } emit_unspec2 ( res0 , UNSPEC_TBL , op0 , sel_reg ) ; rtx sel_sub = expand_simple_binop ( sel_mode , PLUS , sel_reg , neg_num_elems , NULL , 0 , OPTAB_DIRECT ) ; emit_unspec2 ( res1 , UNSPEC_TBL , op1 , sel_sub ) ; if ( GET_MODE_CLASS ( data_mode ) == MODE_VECTOR_INT ) emit_insn ( gen_rtx_SET ( target , gen_rtx_IOR ( data_mode , res0 , res1 ) ) ) ; else emit_unspec2 ( target , UNSPEC_IORF , res0 , res1 ) ; } </s>

Expand an SVE vec_perm with the given operands .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s>
static
void
rs6000_sched_finish
(
FILE
*
dump
,
int
sched_verbose
)
{
int
n_groups
;
if
(
sched_verbose
)
fprintf
(
dump
,
"=== Finishing schedule.\n"
)
;
if
(
reload_completed
&&
rs6000_sched_groups
)
{
if
(
sel_sched_p
(
)
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_none
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_pad_groups
)
n_groups
=
pad_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
else
n_groups
=
redefine_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
if
(
sched_verbose
>=
6
)
{
fprintf
(
dump
,
"ngroups = %d\n"
,
n_groups
)
;
print_rtl
(
dump
,
current_sched_info
->
prev_head
)
;
fprintf
(
dump
,
"Done finish_sched\n"
)
;
}
}
}
</s>

The following function is called at the end of scheduling BB . After reload , it inserts nops at insn group bundling .

powerpcspe
"=== Finishing schedule.\n"
6
"ngroups = %d\n"
"Done finish_sched\n"


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; DebugLoc DL = MI . getDebugLoc ( ) ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( Size ) BuildMI ( MBB , I , DL , TII . get ( SP :: ADDri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( Size ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Sparc Sparc 0 SP::ADJCALLSTACKDOWN Sparc Sparc SP::ADDri SP::O6 SP::O6


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Conditional Compares"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool ia64_expand_vecint_compare ( enum rtx_code code , enum machine_mode mode , rtx dest , rtx op0 , rtx op1 ) { bool negate = false ; rtx x ; switch ( code ) { case EQ : case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = op0 , op0 = op1 , op1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V2SImode : { rtx t1 , t2 , mask ; t1 = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_subv2si3 ( t1 , op0 , op1 ) ) ; mask = GEN_INT ( - 0x80000000 ) ; mask = gen_rtx_CONST_VECTOR ( V2SImode , gen_rtvec ( 2 , mask , mask ) ) ; mask = force_reg ( V2SImode , mask ) ; t2 = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_andv2si3 ( t2 , op0 , mask ) ) ; x = gen_reg_rtx ( V2SImode ) ; emit_insn ( gen_xorv2si3 ( x , t1 , t2 ) ) ; code = GT ; op0 = x ; op1 = CONST0_RTX ( mode ) ; } break ; case V8QImode : case V4HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_US_MINUS ( mode , op0 , op1 ) ) ) ; code = EQ ; op0 = x ; op1 = CONST0_RTX ( mode ) ; negate = ! negate ; break ; default : gcc_unreachable ( ) ; } } x = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; return negate ; } </s>

Generate an integral vector comparison . Return true if the condition has been reversed , and so the sense of the comparison should be inverted .


<s> static void ix86_adjust_stack_and_probe ( const HOST_WIDE_INT size ) { const int dope = 4 * UNITS_PER_WORD ; rtx size_rtx = GEN_INT ( size ) , last ; if ( size <= 4 * PROBE_INTERVAL ) { HOST_WIDE_INT i , adjust ; bool first_probe = true ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { if ( first_probe ) { adjust = 2 * PROBE_INTERVAL + dope ; first_probe = false ; } else adjust = PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - adjust ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } if ( first_probe ) adjust = size + PROBE_INTERVAL + dope ; else adjust = size + PROBE_INTERVAL - i ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - adjust ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; last = emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; } else { HOST_WIDE_INT rounded_size ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( PROBE_INTERVAL + dope ) ) ) ) ; if ( rounded_size <= ( HOST_WIDE_INT_1 << 31 ) ) emit_insn ( gen_rtx_SET ( sr . reg , plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; } emit_insn ( ix86_gen_adjust_stack_and_probe ( sr . reg , sr . reg , size_rtx ) ) ; if ( size != rounded_size ) { emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , rounded_size - size ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } last = emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; release_scratch_register_on_entry ( & sr ) ; } if ( size > 0 ) { rtx expr = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( expr , 0 , 0 ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - size ) ) ; XVECEXP ( expr , 0 , 1 ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope + size ) ) ; add_reg_note ( last , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( last ) = 1 ; cfun -> machine -> fs . sp_offset += size ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to adjust the stack pointer by SIZE bytes while probing it .


<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicRMWInIR ( AI ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> rtx rs6000_address_for_fpconvert ( rtx x ) { int strict_p = ( reload_in_progress || reload_completed ) ; rtx addr ; gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , 0 ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) && ! legitimate_indexed_address_p ( addr , strict_p ) ) { if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , copy_addr_to_reg ( addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX that only take reg+reg addressing .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Assembly Printer"
;
}
</s>


<s> int VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const VESubtarget & Subtarget = MF . getSubtarget < VESubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP = true ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> unsigned getNumFixupKinds ( ) const override { return MMIX :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = Subtarget ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 0 16


<s>
const
char
*
emit_fusion_p9_store
(
rtx
mem
,
rtx
reg
,
rtx
tmp_reg
)
{
enum
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
store_string
;
int
r
;
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_store, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
store_string
=
"stfs"
;
else
if
(
mode
==
DFmode
)
store_string
=
"stfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
QImode
:
store_string
=
"stb"
;
break
;
case
HImode
:
store_string
=
"sth"
;
break
;
case
SImode
:
case
SFmode
:
store_string
=
"stw"
;
break
;
case
DImode
:
case
DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
store_string
=
"std"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_store, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_store not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 store fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
store_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a store using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
"emit_fusion_p9_store, bad reg #1"
"stfs"
"stfd"
"stb"
"sth"
"stw"
"std"
"emit_fusion_p9_store, bad reg #2"
"emit_fusion_p9_store not MEM"
0
"power9 store fusion"
""


<s>
unsigned
X86VectorTargetTransformInfo
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
)
const
{
std
::
pair
<
unsigned
,
MVT
>
LT
=
getTypeLegalizationCost
(
Ty
)
;
int
ISD
=
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
const
X86Subtarget
&
ST
=
TLI
->
getTargetMachine
(
)
.
getSubtarget
<
X86Subtarget
>
(
)
;
static
const
X86CostTblEntry
AVX1CostTable
[
]
=
{
{
ISD
::
MUL
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
MUL
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v4i64
,
4
}
,
}
;
if
(
ST
.
hasAVX
(
)
)
{
int
Idx
=
FindInTable
(
AVX1CostTable
,
array_lengthof
(
AVX1CostTable
)
,
ISD
,
LT
.
second
)
;
if
(
Idx
!=
1
)
return
LT
.
first
*
AVX1CostTable
[
Idx
]
.
Cost
;
}
return
VectorTargetTransformImpl
::
getArithmeticInstrCost
(
Opcode
,
Ty
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s>
StringRef
getPassName
(
)
const
override
{
return
"DLX Delay Slot Filler"
;
}
</s>


<s> llvm :: FastISel * ARM64 :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new ARM64FastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static rtx load_cr_save ( int regno , rtx frame_reg_rtx , int offset , bool exit_func ) { rtx mem = gen_frame_mem_offset ( SImode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx_insn * insn = emit_move_insn ( reg , mem ) ; if ( ! exit_func && DEFAULT_ABI == ABI_V4 ) { rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; rtx set = gen_rtx_SET ( reg , cr ) ; add_reg_note ( insn , REG_CFA_REGISTER , set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return reg ; } </s>

Restoring cr is a two step process : loading a reg from the frame save , then moving the reg to cr . For ABI_V4 we must let the unwinder know that the stack location is no longer valid at or before the stack deallocation , but we ca n't emit a cfa_restore for cr at the stack deallocation like we do for other registers . The trouble is that it is possible for the move to cr to be scheduled after the stack deallocation . So say exactly where cr is located on each of the two insns .


<s> static rtx aarch64_sve_move_pred_via_while ( rtx target , machine_mode mode , unsigned int vl ) { rtx limit = force_reg ( DImode , gen_int_mode ( vl , DImode ) ) ; target = aarch64_target_reg ( target , mode ) ; emit_insn ( gen_while ( UNSPEC_WHILELO , DImode , mode , target , const0_rtx , limit ) ) ; return target ; } </s>

Use WHILE to set a predicate register of mode MODE in which the first VL bits are set and the rest are clear . Use TARGET for the register if it 's nonnull and convenient .


<s>
const
char
*
output_call
(
rtx
*
operands
)
{
gcc_assert
(
!
arm_arch5t
)
;
if
(
REGNO
(
operands
[
0
]
)
==
LR_REGNUM
)
{
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
IP_REGNUM
)
;
output_asm_insn
(
"mov%?\t%0, %|lr"
,
operands
)
;
}
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
if
(
TARGET_INTERWORK
||
arm_arch4t
)
output_asm_insn
(
"bx%?\t%0"
,
operands
)
;
else
output_asm_insn
(
"mov%?\t%|pc, %0"
,
operands
)
;
return
""
;
}
</s>

INSN is either a function call or a millicode call . It may have an unconditional jump in its delay slot . CALL_DEST is the routine we are calling .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , 16 ) ; bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) { if ( MI -> getOperand ( X86 :: AddrNumOperands ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 0 , FrameIndex ) ) return MI -> getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void sh_emit_scc_to_t ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx t_reg = get_t_reg_rtx ( ) ; enum rtx_code oldcode = code ; switch ( code ) { case NE : gcc_unreachable ( ) ; case LT : code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) std :: swap ( op0 , op1 ) ; machine_mode mode = GET_MODE ( op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( op1 ) ; op0 = force_reg ( mode , op0 ) ; if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; sh_emit_set_t_insn ( gen_rtx_SET ( t_reg , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) , mode ) ; } </s>

Prepare the operands for an scc instruction ; make sure that the compare has been done and the result is in T_REG .


<s> static int compute_cpymem_length ( rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; unsigned int align = INTVAL ( XEXP ( XVECEXP ( pat , 0 , 7 ) , 0 ) ) ; unsigned long n_bytes = INTVAL ( XEXP ( XVECEXP ( pat , 0 , 6 ) , 0 ) ) ; unsigned int n_insns = 0 ; if ( align > ( TARGET_64BIT ? 8 : 4 ) ) align = ( TARGET_64BIT ? 8 : 4 ) ; n_insns = 6 ; if ( n_bytes % ( 2 * align ) != 0 ) { if ( ( n_bytes % ( 2 * align ) ) >= align ) n_insns += 2 ; if ( ( n_bytes % align ) != 0 ) n_insns += 2 ; } return n_insns * 4 ; } </s>

Count the number of insns necessary to handle this block move . Basic structure is the same as emit_block_move , except that we count insns rather than emit them .


<s> int ia64_produce_address_p ( rtx insn ) { return insn -> call ; } </s>

The following function returns TRUE if INSN produces address for a load/store insn . We will place such insns into M slot because it decreases its latency time .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARM64FunctionInfo * AFI = MF . getInfo < ARM64FunctionInfo > ( ) ; if ( AFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_tlsreg"
,
0
,
0
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
void
pa_output_function_label
(
FILE
*
file
)
{
ASM_OUTPUT_LABEL
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
)
;
fputs
(
"\t.PROC\n"
,
file
)
;
fprintf
(
file
,
"\t.CALLINFO FRAME="
HOST_WIDE_INT_PRINT_DEC
,
actual_fsize
)
;
if
(
crtl
->
is_leaf
)
fputs
(
",NO_CALLS"
,
file
)
;
else
fputs
(
",CALLS"
,
file
)
;
if
(
rp_saved
)
fputs
(
",SAVE_RP"
,
file
)
;
if
(
frame_pointer_needed
)
fputs
(
",SAVE_SP"
,
file
)
;
if
(
gr_saved
)
fprintf
(
file
,
",ENTRY_GR=%d"
,
gr_saved
+
2
)
;
if
(
fr_saved
)
fprintf
(
file
,
",ENTRY_FR=%d"
,
fr_saved
+
11
)
;
fputs
(
"\n\t.ENTRY\n"
,
file
)
;
}
</s>

Output function label , and associated .PROC and .CALLINFO statements .


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static const char * detect_processor_aix ( void ) { switch ( _system_configuration . implementation ) { case 0x0008 : return "601" ; case 0x0020 : return "603" ; case 0x0010 : return "604" ; case 0x0040 : return "620" ; case 0x0080 : return "630" ; case 0x0100 : case 0x0200 : case 0x0400 : return "rs64" ; case 0x0800 : return "power4" ; case 0x2000 : if ( _system_configuration . version == 0x0F0000 ) return "power5" ; else return "power5+" ; case 0x4000 : return "power6" ; case 0x8000 : return "power7" ; case 0x10000 : return "power8" ; case 0x20000 : return "power9" ; case 0x40000 : return "power10" ; default : return "powerpc" ; } } </s>

Returns the processor implementation on AIX .


<s> static int ia64_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass , bool in ATTRIBUTE_UNUSED ) { if ( rclass == GENERAL_REGS || rclass == FR_REGS || rclass == FP_REGS || rclass == GR_AND_FR_REGS ) return 4 ; else return 10 ; } </s>

Calculate the cost of moving data of MODE from a register to or from memory .


<s> bool OR1KDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const OR1KSubtarget & > ( MF . getSubtarget ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> void arm_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname , tree fndecl ATTRIBUTE_UNUSED ) { if ( fntype ) pcum -> pcs_variant = arm_get_pcs_model ( fntype , fndecl ) ; else pcum -> pcs_variant = arm_pcs_default ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { if ( arm_libcall_uses_aapcs_base ( libname ) ) pcum -> pcs_variant = ARM_PCS_AAPCS ; pcum -> aapcs_ncrn = pcum -> aapcs_next_ncrn = 0 ; pcum -> aapcs_reg = NULL_RTX ; pcum -> aapcs_partial = 0 ; pcum -> aapcs_arg_processed = false ; pcum -> aapcs_cprc_slot = - 1 ; pcum -> can_split = true ; if ( pcum -> pcs_variant != ARM_PCS_AAPCS ) { int i ; for ( i = 0 ; i < ARM_NUM_COPROC_SLOTS ; i ++ ) { pcum -> aapcs_cprc_failed [ i ] = false ; aapcs_cp_arg_layout [ i ] . cum_init ( pcum , fntype , libname , fndecl ) ; } } return ; } pcum -> nregs = 0 ; pcum -> iwmmxt_nregs = 0 ; pcum -> can_split = true ; pcum -> named_count = 0 ; pcum -> nargs = 0 ; if ( TARGET_REALLY_IWMMXT && fntype ) { tree fn_arg ; for ( fn_arg = TYPE_ARG_TYPES ( fntype ) ; fn_arg ; fn_arg = TREE_CHAIN ( fn_arg ) ) pcum -> named_count += 1 ; if ( ! pcum -> named_count ) pcum -> named_count = INT_MAX ; } } </s>

Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is NULL .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
nullptr
,
IsLittleEndian
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void build_one ( function_builder & b , const char * signature , const function_group_info & group , mode_suffix_index mode_suffix_id , unsigned int ti , unsigned int pi , bool force_direct_overloads ) { auto_vec < tree , 16 > argument_types ; function_instance instance ( group . base_name , * group . base , * group . shape , mode_suffix_id , group . types [ ti ] , group . preds [ pi ] ) ; tree return_type = parse_signature ( instance , signature , argument_types ) ; apply_predication ( instance , return_type , argument_types ) ; b . add_unique_function ( instance , return_type , argument_types , group . required_extensions , force_direct_overloads ) ; } </s>

Add one function instance for GROUP , using operand suffix at index OI , mode suffix at index PAIR & & bi and predication suffix at index pred_idx .


<s>
bool
ARMTargetLowering
::
ExpandInlineAsm
(
CallInst
*
CI
)
const
{
if
(
!
Subtarget
->
hasV6Ops
(
)
)
return
false
;
InlineAsm
*
IA
=
cast
<
InlineAsm
>
(
CI
->
getCalledValue
(
)
)
;
std
::
string
AsmStr
=
IA
->
getAsmString
(
)
;
SmallVector
<
StringRef
,
4
>
AsmPieces
;
SplitString
(
AsmStr
,
AsmPieces
,
";\n"
)
;
switch
(
AsmPieces
.
size
(
)
)
{
default
:
return
false
;
case
1
:
AsmStr
=
AsmPieces
[
0
]
;
AsmPieces
.
clear
(
)
;
SplitString
(
AsmStr
,
AsmPieces
,
" \t,"
)
;
if
(
AsmPieces
.
size
(
)
==
3
&&
AsmPieces
[
0
]
==
"rev"
&&
AsmPieces
[
1
]
==
"$0"
&&
AsmPieces
[
2
]
==
"$1"
&&
IA
->
getConstraintString
(
)
.
compare
(
0
,
4
,
"=l,l"
)
==
0
)
{
IntegerType
*
Ty
=
dyn_cast
<
IntegerType
>
(
CI
->
getType
(
)
)
;
if
(
Ty
&&
Ty
->
getBitWidth
(
)
==
32
)
return
IntrinsicLowering
::
LowerToByteSwap
(
CI
)
;
}
break
;
}
return
false
;
}
</s>

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) const { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Directive = ST -> getCPUDirective ( ) ; if ( Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 || Directive == PPC :: DIR_PWR_FUTURE ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


<s> static bool single_def_chain_p ( rtx reg ) { df_ref ref = DF_REG_DEF_CHAIN ( REGNO ( reg ) ) ; if ( ! ref ) return false ; return DF_REF_NEXT_REG ( ref ) == nullptr ; } </s>

Return true if the register REG is defined in a single DEF chain . If it is defined in more than one DEF chains , we may not be able to convert it in all chains .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>


<s> void clear ( ) { Refs = AvailableDomains = Dist = 0 ; Instrs . clear ( ) ; } </s>


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return C_RegisterClass ; case 'I' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void AArch64TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { BaseT :: getUnrollingPreferences ( L , SE , UP , ORE ) ; UP . UpperBound = true ; if ( L -> getLoopDepth ( ) > 1 ) UP . PartialThreshold *= 2 ; UP . PartialOptSizeThreshold = 0 ; if ( ST -> getProcFamily ( ) == AArch64Subtarget :: Falkor && EnableFalkorHWPFUnrollFix ) getFalkorUnrollingPreferences ( L , SE , UP ) ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } } } if ( ST -> getProcFamily ( ) != AArch64Subtarget :: Others && ! ST -> getSchedModel ( ) . isOutOfOrder ( ) ) { UP . Runtime = true ; UP . Partial = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = 4 ; UP . UnrollAndJam = true ; UP . UnrollAndJamInnerLoopThreshold = 60 ; } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> Optional < MCFixupKind > SystemZMCAsmBackend :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_390_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_390_8 ) . Case ( "BFD_RELOC_16" , ELF :: R_390_16 ) . Case ( "BFD_RELOC_32" , ELF :: R_390_32 ) . Case ( "BFD_RELOC_64" , ELF :: R_390_64 ) . Default ( - 1u ) ; if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static bool rs6000_vectorize_vec_perm_const ( machine_mode vmode , machine_mode op_mode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( vmode != op_mode ) return false ; bool testing_p = ! target ; if ( TARGET_ALTIVEC && testing_p ) return true ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; if ( ( vmode == V2DFmode || vmode == V2DImode ) && VECTOR_MEM_VSX_P ( vmode ) ) { if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 1 ) ; op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 2 ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ 0 ] , sel [ 1 ] ) ) return true ; } if ( TARGET_ALTIVEC ) { if ( vmode != V16QImode ) return false ; if ( altivec_expand_vec_perm_const ( target , op0 , op1 , sel ) ) return true ; } return false ; } </s>


"Pseudo flag setting opcodes only exist in Selection DAG"

Perform target-specific instruction verification .


<s> bool X86TargetLowering :: isFsqrtCheap ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( DAG . getNodeIfExists ( X86ISD :: FRSQRT , DAG . getVTList ( VT ) , Op ) ) return false ; if ( VT . isVector ( ) ) return Subtarget . hasFastVectorFSQRT ( ) ; return Subtarget . hasFastScalarFSQRT ( ) ; } </s>

Return true if SQRT ( X ) should n't be replaced with X * RSQRT ( X ) .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s>
SDValue
VECustomDAG
::
getUnpack
(
EVT
DestVT
,
SDValue
Vec
,
PackElem
Part
,
SDValue
AVL
)
const
{
assert
(
getAnnotatedNodeAVL
(
AVL
)
.
second
&&
"Expected a pack-legalized AVL"
)
;
unsigned
OC
=
(
Part
==
PackElem
::
Lo
)
VEISD
::
VEC_UNPACK_LO
:
VEISD
::
VEC_UNPACK_HI
;
return
DAG
.
getNode
(
OC
,
DL
,
DestVT
,
Vec
,
AVL
)
;
}
</s>


<s> void sparc_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf && only_leaf_regs_used ( ) ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( size == 0 ) ; else if ( sparc_leaf_function_p ) { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) emit_window_save ( size_int_rtx ) ; else if ( size <= 8192 ) { emit_window_save ( GEN_INT ( - 4096 ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; if ( crtl -> uses_pic_offset_table ) load_got_register ( ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the PIC register if needed .


<s> static void sh_function_arg_advance ( cumulative_args_t ca_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ca -> force_mem ) ca -> force_mem = false ; if ( ( TARGET_HITACHI || ca -> renesas_abi ) && TARGET_FPU_DOUBLE ) { if ( arg . mode == SFmode && ca -> free_single_fp_reg ) { ca -> free_single_fp_reg = 0 ; return ; } if ( arg . mode == DFmode && sh_round_reg ( * ca , DFmode ) != sh_round_reg ( * ca , SFmode ) ) { ca -> free_single_fp_reg = ( sh_round_reg ( * ca , SFmode ) + BASE_ARG_REG ( arg . mode ) ) ; } } if ( ! ( ( TARGET_SH4 || TARGET_SH2A ) || ca -> renesas_abi ) || sh_pass_in_reg_p ( * ca , arg . mode , arg . type ) ) ( ca -> arg_count [ ( int ) get_sh_arg_class ( arg . mode ) ] = ( sh_round_reg ( * ca , arg . mode ) + CEIL ( arg . promoted_size_in_bytes ( ) , UNITS_PER_WORD ) ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> static void mips_set_frame_expr ( rtx frame_pattern ) { rtx insn ; insn = get_last_insn ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , frame_pattern , REG_NOTES ( insn ) ) ; } </s>

Make the last instruction frame related and note that it performs the operation described by FRAME_PATTERN .


<s> static pad_direction iq2000_function_arg_padding ( machine_mode mode , const_tree type ) { return ( ! BYTES_BIG_ENDIAN ? PAD_UPWARD : ( ( mode == BLKmode ? ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && int_size_in_bytes ( type ) < ( PARM_BOUNDARY / BITS_PER_UNIT ) ) : ( GET_MODE_BITSIZE ( mode ) < PARM_BOUNDARY && GET_MODE_CLASS ( mode ) == MODE_INT ) ) ? PAD_DOWNWARD : PAD_UPWARD ) ) ; } </s>


<s> static bool ix86_macro_fusion_p ( ) { return TARGET_FUSE_CMP_AND_BRANCH ; } </s>

Return true if target platform supports macro-fusion .


<s> void print_operand_address ( FILE * file , rtx x ) { if ( REG_P ( x ) ) fprintf ( file , "0(%s)" , reg_names [ REGNO ( x ) ] ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) { output_addr_const ( file , x ) ; if ( small_data_operand ( x , GET_MODE ( x ) ) ) fprintf ( file , "@%s(%s)" , SMALL_DATA_RELOC , reg_names [ SMALL_DATA_REG ] ) ; else gcc_assert ( ! TARGET_TOC ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REG_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == 0 ) fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC "(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { fprintf ( file , "lo16(" ) ; output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , ")(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "(%s)" , reg_names [ REGNO ( XVECEXP ( tocrel_base , 0 , 1 ) ) ] ) ; } else gcc_unreachable ( ) ; } </s>

Print the operand address represented by the rtx addr


<s> static unsigned rs6000_hash_constant ( rtx k ) { enum rtx_code code = GET_CODE ( k ) ; enum machine_mode mode = GET_MODE ( k ) ; unsigned result = ( code << 3 ) ^ mode ; const char * format ; int flen , fidx ; format = GET_RTX_FORMAT ( code ) ; flen = strlen ( format ) ; fidx = 0 ; switch ( code ) { case LABEL_REF : return result * 1231 + ( unsigned ) INSN_UID ( XEXP ( k , 0 ) ) ; case CONST_DOUBLE : if ( mode != VOIDmode ) return real_hash ( CONST_DOUBLE_REAL_VALUE ( k ) ) * result ; flen = 2 ; break ; case CODE_LABEL : fidx = 3 ; break ; default : break ; } for ( ; fidx < flen ; fidx ++ ) switch ( format [ fidx ] ) { case 's' : { unsigned i , len ; const char * str = XSTR ( k , fidx ) ; len = strlen ( str ) ; result = result * 613 + len ; for ( i = 0 ; i < len ; i ++ ) result = result * 613 + ( unsigned ) str [ i ] ; break ; } case 'u' : case 'e' : result = result * 1231 + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * 613 + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * 613 + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = 0 ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * 613 + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result ; } </s>


<s> unsigned getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , AArch64 :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; StackSize = std :: max ( StackSize , Size + Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> static void pru_elf_asm_constructor ( rtx symbol , int priority ) { char buf [ 23 ] ; section * s ; if ( priority == DEFAULT_INIT_PRIORITY ) snprintf ( buf , sizeof ( buf ) , ".init_array" ) ; else { snprintf ( buf , sizeof ( buf ) , ".init_array.%.5u" , priority ) ; } s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s ) ; assemble_aligned_integer ( INIT_ARRAY_ENTRY_BYTES , symbol ) ; } </s>


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> bool PPCLoopInstrFormPrep :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; SuccPrepCount = 0 ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void PPCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool preferZeroCompareBranch ( ) const override { return true ; } </s>

Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare .


<s> bool X86InstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI -> getOpcode ( ) ) ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> static unsigned int pru_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ! strcmp ( name , ".pru_irq_map" ) ) flags = SECTION_DEBUG | SECTION_RETAIN ; return flags ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64InstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const { return MF . getFunction ( ) . optForMinSize ( ) ; } </s>

Return true if the function should be outlined from by default .


<s> bool arm_output_addr_const_extra ( FILE * fp , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) return arm_emit_tls_decoration ( fp , x ) ; else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_PIC_LABEL ) { char label [ 256 ] ; int labelno = INTVAL ( XVECEXP ( x , 0 , 0 ) ) ; ASM_GENERATE_INTERNAL_LABEL ( label , "LPIC" , labelno ) ; assemble_name_raw ( fp , label ) ; return TRUE ; } else if ( GET_CODE ( x ) == CONST_VECTOR ) return arm_emit_vector_const ( fp , x ) ; return FALSE ; } </s>


<s> static void rs6000_setup_reg_addr_masks ( void ) { ssize_t rc , reg , m , nregs ; addr_mask_type any_addr_mask , addr_mask ; for ( m = 0 ; m < NUM_MACHINE_MODES ; ++ m ) { machine_mode m2 = ( machine_mode ) m ; bool indexed_only_p = ( m == SDmode && TARGET_NO_SDMODE_STACK ) ; any_addr_mask = 0 ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = 0 ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= 0 && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( nregs > 1 || m == BLKmode ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && GET_MODE_SIZE ( m2 ) <= 8 && ! VECTOR_MODE_P ( m2 ) && ! COMPLEX_MODE_P ( m2 ) && ! indexed_only_p && ! ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( m2 ) == 8 ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DFmode : case DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != 0 ) && ! indexed_only_p && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) ) addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_VMX && GET_MODE_SIZE ( m2 ) == 16 && ( addr_mask & RELOAD_REG_VALID ) != 0 ) addr_mask |= RELOAD_REG_AND_M16 ; reg_addr [ m ] . addr_mask [ rc ] = addr_mask ; any_addr_mask |= addr_mask ; } reg_addr [ m ] . addr_mask [ RELOAD_REG_ANY ] = any_addr_mask ; } } </s>

Update the addr mask bits in reg_addr to help secondary reload and go if legitimate address support to figure out the appropriate addressing to use .


<s> static bool classof ( const ARMConstantPoolMBB * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static bool mips_mult_move_p ( rtx dest , rtx src , enum mips_split_type split_type ) { return ( ( split_type != SPLIT_FOR_SPEED || mips_tuning_info . fast_mult_zero_zero_p ) && src == const0_rtx && REG_P ( dest ) && GET_MODE_SIZE ( GET_MODE ( dest ) ) == 2 * UNITS_PER_WORD && ( ISA_HAS_DSP_MULT ? ACC_REG_P ( REGNO ( dest ) ) : MD_REG_P ( REGNO ( dest ) ) ) ) ; } </s>

Return true if SRC should be moved into DEST using `` MULT $ 0 , $ 0 '' . SPLIT_TYPE is the condition under which moves should be split .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


<s> void PPCRegisterInfo :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> hasCalls ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = PPCFrameInfo :: getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isMachoABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> void emitAssignment ( MCSymbol * S , const MCExpr * Value ) override { auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( copyLocalEntry ( Symbol , Value ) ) UpdateOther . insert ( Symbol ) ; else UpdateOther . erase ( Symbol ) ; } </s>