<s> void neon_pairwise_reduce ( rtx op0 , rtx op1 , machine_mode mode , rtx ( * reduc ) ( rtx , rtx , rtx ) ) { unsigned int i , parts = GET_MODE_SIZE ( mode ) / GET_MODE_UNIT_SIZE ( mode ) ; rtx tmpsum = op1 ; for ( i = parts / 2 ; i >= 1 ; i /= 2 ) { rtx dest = ( i == 1 ) ? op0 : gen_reg_rtx ( mode ) ; emit_insn ( reduc ( dest , tmpsum , tmpsum ) ) ; tmpsum = dest ; } } </s>

Output a sequence of pairwise operations to implement a reduction . NOTE : We do `` too much work '' here , because pairwise operations work on two registers-worth of operands in one go . Unfortunately we ca n't exploit those extra calculations to do the full operation in fewer steps , I do n't think . Although all vector elements of the result but the first are ignored , we actually calculate the same result in each of the elements . An alternative such as initially loading a vector with zero to use as each of the second operands would use up an additional register and take an extra instruction , for no particular gain .


<s> static bool mep_store_data_bypass_1 ( rtx_insn * prev , rtx pat ) { if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( mep_store_data_bypass_p ( prev , as_a < rtx_insn * > ( XVECEXP ( pat , 0 , i ) ) ) ) return true ; return false ; } if ( GET_CODE ( pat ) != SET || GET_CODE ( SET_DEST ( pat ) ) != MEM ) return false ; if ( GET_CODE ( SET_SRC ( pat ) ) == UNSPEC ) { rtx src ; int i ; src = SET_SRC ( pat ) ; for ( i = 1 ; i < XVECLEN ( src , 0 ) ; i ++ ) if ( mep_store_find_set ( XVECEXP ( src , 0 , i ) , prev ) ) return false ; return true ; } return ! mep_store_find_set ( SET_DEST ( pat ) , prev ) ; } </s>

Like mep_store_bypass_p , but takes a pattern as the second argument , not the containing insn .


<s> static int compute_clrmem_length ( rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; unsigned int align = INTVAL ( XEXP ( XVECEXP ( pat , 0 , 4 ) , 0 ) ) ; unsigned long n_bytes = INTVAL ( XEXP ( XVECEXP ( pat , 0 , 3 ) , 0 ) ) ; unsigned int n_insns = 0 ; if ( align > ( TARGET_64BIT ? 8 : 4 ) ) align = ( TARGET_64BIT ? 8 : 4 ) ; n_insns = 4 ; if ( n_bytes % ( 2 * align ) != 0 ) { if ( ( n_bytes % ( 2 * align ) ) >= align ) n_insns ++ ; if ( ( n_bytes % align ) != 0 ) n_insns ++ ; } return n_insns * 4 ; } </s>

Count the number of insns necessary to handle this block move . Basic structure is the same as emit_block_move , except that we count insns rather than emit them .


<s> bool FineIBTHashesSection :: runOnModule ( Module & M ) { if ( ! M . getModuleFlag ( "cf-protection-fine" ) ) return false ; const TargetMachine * TM = & getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ; if ( ! TM ) return false ; for ( auto & F : M ) { if ( F . getName ( ) . startswith ( "__ibt_fine_plt" ) ) continue ; if ( ! F . doesNoCfCheck ( ) && ! F . doesCoarseCfCheck ( ) && ! F . hasLocalLinkage ( ) ) { if ( F . isIntrinsic ( ) && ! IsExternalIntrinsic ( & F ) ) continue ; CreatePLTTemplate ( M , & F ) ; } } return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> unsigned getMaxInlineSizeThreshold ( ) const { return 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> MVT MipsTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( ! VT . isVector ( ) ) return getRegisterType ( Context , VT ) ; return Subtarget . isABI_O32 ( ) || VT . getSizeInBits ( ) == 32 ? MVT :: i32 : MVT :: i64 ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> static int csky_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { enum rtx_code code = GET_CODE ( x ) ; if ( code == REG ) return COSTS_N_INSNS ( 1 ) ; if ( code == PLUS && REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) return COSTS_N_INSNS ( 1 ) ; return COSTS_N_INSNS ( 3 ) ; } </s>

Implement TARGET_ADDRESS_COST to estimate cost of the memory address X . For C-SKY , ( register ) and ( register + offset ) have the same cost . Other situations cost more .


<s> static void emit_vrsave_prologue ( rs6000_stack_t * info , int save_regno , HOST_WIDE_INT frame_off , rtx frame_reg_rtx ) { rtx reg = gen_rtx_REG ( SImode , save_regno ) ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; if ( TARGET_MACHO ) emit_insn ( gen_get_vrsave_internal ( reg ) ) ; else emit_insn ( gen_rtx_SET ( reg , vrsave ) ) ; int offset = info -> vrsave_save_offset + frame_off ; emit_insn ( gen_frame_store ( reg , frame_reg_rtx , offset ) ) ; emit_insn ( gen_iorsi3 ( reg , reg , GEN_INT ( info -> vrsave_mask ) ) ) ; emit_insn ( generate_set_vrsave ( reg , info , 0 ) ) ; } </s>

VRSAVE is a bit vector representing which AltiVec registers are used . The OS uses this to determine which vector registers to save on a context switch . We need to save VRSAVE on the stack frame , add whatever AltiVec registers we used in this function , and do the corresponding magic in the epilogue .


<s> bool LanaiTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Lanai32 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool SystemZMCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { for ( uint64_t I = 0 ; I != Count ; ++ I ) OS << '\x7' ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> const char * output_fix_trunc ( rtx_insn * insn , rtx * operands , bool fisttp ) { int stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) != 0 ; int dimode_p = GET_MODE ( operands [ 0 ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( "fld\t%y1" , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ 1 ] ) ) ; gcc_assert ( MEM_P ( operands [ 0 ] ) ) ; gcc_assert ( GET_MODE ( operands [ 1 ] ) != TFmode ) ; if ( fisttp ) output_asm_insn ( "fisttp%Z0\t%0" , operands ) ; else { if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%3" , operands ) ; if ( stack_top_dies || dimode_p ) output_asm_insn ( "fistp%Z0\t%0" , operands ) ; else output_asm_insn ( "fist%Z0\t%0" , operands ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%2" , operands ) ; } return "" ; } </s>

Output code for INSN to convert a float to a signed int . OPERANDS are the insn operands . The output may be [ HSD ] Imode and the input operand may be [ SDX ] Fmode .


<s> static int arm_barrier_cost ( rtx_insn * insn ) { int base_cost = 50 ; rtx_insn * next = next_nonnote_insn ( insn ) ; if ( next != NULL && LABEL_P ( next ) ) base_cost -= 20 ; switch ( GET_CODE ( insn ) ) { case CODE_LABEL : return 50 ; case INSN : case CALL_INSN : return base_cost ; case JUMP_INSN : return base_cost - 10 ; default : return base_cost + 10 ; } } </s>

Return the cost of forcibly inserting a barrier after INSN .


"warning: some functions compiled with BTI and some compiled "

"warning: not setting BTI in feature flags\n"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> static bool csky_tls_symbol_p ( rtx x ) { if ( ! TARGET_TLS ) return false ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; return SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return TRUE if X is a thread-local symbol .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
static
bool
aarch64_validate_mcpu
(
const
char
*
str
,
const
struct
processor
*
*
res
,
unsigned
long
*
isa_flags
)
{
enum
aarch64_parse_opt_result
parse_res
=
aarch64_parse_cpu
(
str
,
res
,
isa_flags
)
;
if
(
parse_res
==
AARCH64_PARSE_OK
)
return
true
;
switch
(
parse_res
)
{
case
AARCH64_PARSE_MISSING_ARG
:
error
(
"missing cpu name in -mcpu=%qs"
,
str
)
;
break
;
case
AARCH64_PARSE_INVALID_ARG
:
error
(
"unknown value %qs for -mcpu"
,
str
)
;
break
;
case
AARCH64_PARSE_INVALID_FEATURE
:
error
(
"invalid feature modifier in -mcpu=%qs"
,
str
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
false
;
}
</s>

Validate a command-line -mcpu option . Parse the cpu and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results if they are valid in RES and ISA_FLAGS . Return whether the option is valid .

aarch64
"missing cpu name in -mcpu=%qs"
"unknown value %qs for -mcpu"
"invalid feature modifier in -mcpu=%qs"


<s> void relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static unsigned int pa_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags ; flags = default_section_type_flags ( decl , name , reloc ) ; if ( strcmp ( name , ".data.rel.ro" ) == 0 || strcmp ( name , ".data.rel.ro.local" ) == 0 ) flags |= SECTION_WRITE | SECTION_RELRO ; return flags ; } </s>


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> bool OR1KDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool aarch64_return_address_signing_enabled ( void ) { gcc_assert ( cfun -> machine -> frame . laid_out ) ; return ( aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL || ( aarch64_ra_sign_scope == AARCH64_FUNCTION_NON_LEAF && known_ge ( cfun -> machine -> frame . reg_offset [ LR_REGNUM ] , 0 ) ) ) ; } </s>

Return TRUE if return address signing should be enabled for the current function , otherwise return FALSE .


<s> bool X86TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( GuaranteedTailCallOpt ) { if ( IsTailCallConvention ( CalleeCC ) && CallerF -> getCallingConv ( ) == CalleeCC ) return true ; return false ; } if ( isVarArg ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( MF . getInfo < X86MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) ) return false ; if ( Subtarget -> isTargetWin64 ( ) ) return false ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const X86InstrInfo * TII = ( ( X86TargetMachine & ) getTargetMachine ( ) ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = Outs [ i ] . Val ; ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } } return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> static bool sh_cannot_modify_jumps_p ( void ) { return ( TARGET_SHMEDIA && ( reload_in_progress || reload_completed ) ) ; } </s>

SHmedia requires registers for branches , so we ca n't generate new branches past reload .


<s> virtual bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { OutOps . push_back ( Op ) ; return false ; } </s>


"PPC DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
bool
CJGInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Xbranch condition!"
)
;
CJGCC
::
CondCodes
CC
=
static_cast
<
CJGCC
::
CondCodes
>
(
Cond
[
0
]
.
getImm
(
)
)
;
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Invalid branch condition!"
)
;
case
CJGCC
::
COND_C
:
CC
=
CJGCC
::
COND_NC
;
break
;
case
CJGCC
::
COND_N
:
CC
=
CJGCC
::
COND_NN
;
break
;
case
CJGCC
::
COND_V
:
CC
=
CJGCC
::
COND_NV
;
break
;
case
CJGCC
::
COND_Z
:
CC
=
CJGCC
::
COND_NZ
;
break
;
case
CJGCC
::
COND_GE
:
CC
=
CJGCC
::
COND_L
;
break
;
case
CJGCC
::
COND_NC
:
CC
=
CJGCC
::
COND_C
;
break
;
case
CJGCC
::
COND_NN
:
CC
=
CJGCC
::
COND_N
;
break
;
case
CJGCC
::
COND_NV
:
CC
=
CJGCC
::
COND_V
;
break
;
case
CJGCC
::
COND_NZ
:
CC
=
CJGCC
::
COND_Z
;
break
;
case
CJGCC
::
COND_L
:
CC
=
CJGCC
::
COND_GE
;
break
;
}
Cond
[
0
]
.
setImm
(
CC
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> DecodeStatus LanaiDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableLanai32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> StringRef getPassName ( ) const override { return AARCH64_BRANCH_TARGETS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static inline rtx force_mode ( machine_mode mode , rtx orig ) { if ( mode == GET_MODE ( orig ) ) return orig ; gcc_assert ( REGNO ( orig ) < FIRST_PSEUDO_REGISTER ) ; return gen_rtx_REG ( mode , REGNO ( orig ) ) ; } </s>

Ensure mode of ORIG , a REG rtx , is MODE . Returns either ORIG or a new rtx with the correct mode .


<s> void loongarch_set_return_address ( rtx address , rtx scratch ) { rtx slot_address ; gcc_assert ( BITSET_P ( cfun -> machine -> frame . mask , RETURN_ADDR_REGNUM ) ) ; if ( frame_pointer_needed ) slot_address = loongarch_add_offset ( scratch , hard_frame_pointer_rtx , - UNITS_PER_WORD ) ; else slot_address = loongarch_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset ) ; loongarch_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address ) , address ) ; } </s>

Emit code to change the current function 's return address to ADDRESS . SCRATCH is available as a scratch register , if needed . ADDRESS and SCRATCH are both word-mode GPRs .


<s> static int sh_issue_rate ( void ) { if ( TARGET_SUPERSCALAR ) return 2 ; else return 1 ; } </s>

This function returns `` 2 '' to indicate dual issue for the SH4 processor . To be used by the DFA pipeline description .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget -> is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! hasMFENCE ( * Subtarget ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> const ARMMCExpr * ARMMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) ARMMCExpr ( Kind , Expr ) ; } </s>


<s> void SHUXIFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool PPCRegisterInfo :: isCallerPreservedPhysReg ( MCRegister PhysReg , const MachineFunction & MF ) const { assert ( Register :: isPhysicalRegister ( PhysReg ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! TM . isPPC64 ( ) ) return false ; if ( ! Subtarget . isSVR4ABI ( ) ) return false ; if ( PhysReg == PPC :: X2 ) return ( getReservedRegs ( MF ) . test ( PPC :: X2 ) ) ; if ( StackPtrConst && ( PhysReg == PPC :: X1 ) && ! MFI . hasVarSizedObjects ( ) && ! MFI . hasOpaqueSPAdjustment ( ) ) return true ; return false ; } </s>

Physical registers that may be modified within a function but are guaranteed to be restored before any uses .


<s> static void restore_saved_cr ( rtx reg , int using_mfcr_multiple , bool exit_func ) { int count = 0 ; int i ; if ( using_mfcr_multiple ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) count ++ ; gcc_assert ( count ) ; } if ( using_mfcr_multiple && count > 1 ) { rtx_insn * insn ; rtvec p ; int ndx ; p = rtvec_alloc ( count ) ; ndx = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = reg ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } else for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn ( ) ; rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; add_reg_note ( insn , REG_CFA_RESTORE , cr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>


<s>
DecodeStatus
AArch64Disassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
Size
=
0
;
if
(
Bytes
.
size
(
)
<
4
)
return
Fail
;
Size
=
4
;
uint32_t
Insn
=
(
Bytes
[
3
]
<<
24
)
|
(
Bytes
[
2
]
<<
16
)
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
0
]
<<
0
)
;
const
uint8_t
*
Tables
[
]
=
{
DecoderTable32
,
DecoderTableFallback32
}
;
for
(
auto
Table
:
Tables
)
{
DecodeStatus
Result
=
decodeInstruction
(
Table
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDR_ZA
:
case
AArch64
::
STR_ZA
:
{
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZA
)
)
;
const
MCOperand
&
Imm4Op
=
MI
.
getOperand
(
2
)
;
assert
(
Imm4Op
.
isImm
(
)
&&
"Unexpected operand type!"
)
;
MI
.
addOperand
(
Imm4Op
)
;
break
;
}
case
AArch64
::
LD1_MXIPXX_H_B
:
case
AArch64
::
LD1_MXIPXX_V_B
:
case
AArch64
::
ST1_MXIPXX_H_B
:
case
AArch64
::
ST1_MXIPXX_V_B
:
case
AArch64
::
INSERT_MXIPZ_H_B
:
case
AArch64
::
INSERT_MXIPZ_V_B
:
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
EXTRACT_ZPMXI_H_B
:
case
AArch64
::
EXTRACT_ZPMXI_V_B
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
LD1_MXIPXX_H_Q
:
case
AArch64
::
LD1_MXIPXX_V_Q
:
case
AArch64
::
ST1_MXIPXX_H_Q
:
case
AArch64
::
ST1_MXIPXX_V_Q
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createImm
(
0
)
)
;
break
;
case
AArch64
::
INSERT_MXIPZ_H_Q
:
case
AArch64
::
INSERT_MXIPZ_V_Q
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createImm
(
0
)
)
;
break
;
case
AArch64
::
EXTRACT_ZPMXI_H_Q
:
case
AArch64
::
EXTRACT_ZPMXI_V_Q
:
MI
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
break
;
case
AArch64
::
SMOVvi8to32_idx0
:
case
AArch64
::
SMOVvi8to64_idx0
:
case
AArch64
::
SMOVvi16to32_idx0
:
case
AArch64
::
SMOVvi16to64_idx0
:
case
AArch64
::
SMOVvi32to64_idx0
:
case
AArch64
::
UMOVvi8_idx0
:
case
AArch64
::
UMOVvi16_idx0
:
case
AArch64
::
UMOVvi32_idx0
:
case
AArch64
::
UMOVvi64_idx0
:
MI
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
break
;
}
if
(
Result
!=
MCDisassembler
::
Fail
)
return
Result
;
}
return
MCDisassembler
::
Fail
;
}
</s>


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static int vax_address_cost_1 ( rtx addr ) { int reg = 0 , indexed = 0 , indir = 0 , offset = 0 , predec = 0 ; rtx plus_op0 = 0 , plus_op1 = 0 ; restart : switch ( GET_CODE ( addr ) ) { case PRE_DEC : predec = 1 ; case REG : case SUBREG : case POST_INC : reg = 1 ; break ; case MULT : case ASHIFT : indexed = 1 ; break ; case CONST_INT : if ( offset == 0 ) offset = ( unsigned HOST_WIDE_INT ) ( INTVAL ( addr ) + 128 ) > 256 ; break ; case CONST : case SYMBOL_REF : offset = 1 ; break ; case LABEL_REF : if ( offset == 0 ) offset = 1 ; break ; case PLUS : if ( plus_op0 ) plus_op1 = XEXP ( addr , 0 ) ; else plus_op0 = XEXP ( addr , 0 ) ; addr = XEXP ( addr , 1 ) ; goto restart ; case MEM : indir = 2 ; addr = XEXP ( addr , 0 ) ; goto restart ; default : break ; } if ( plus_op0 ) { addr = plus_op0 ; plus_op0 = 0 ; goto restart ; } if ( plus_op1 ) { addr = plus_op1 ; plus_op1 = 0 ; goto restart ; } if ( reg && indexed && offset ) return reg + indir + offset + predec ; return reg + indexed + indir + offset + predec ; } </s>

Return the cost in cycles of a memory address , relative to register indirect . Each of the following adds the indicated number of cycles : 1 - symbolic address 1 - pre-decrement 1 - indexing and/or offset ( register ) 2 - indirect


"Unable to build a return instruction?!"

"The insertion did not happen where we expected"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool ARMSubtarget :: isGVInGOT ( const GlobalValue * GV ) const { return isTargetELF ( ) && TM . isPositionIndependent ( ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; } </s>

Returns the constant pool modifier needed to access the GV .


<s> static void rs6000_emit_nmsub ( rtx dst , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( dst ) ; rtx r ; gcc_assert ( optab_handler ( fma_optab , mode ) != CODE_FOR_nothing ) ; r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1 , m2 , r ) ; r = gen_rtx_NEG ( mode , r ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dst , r ) ) ; } </s>

Generate a FNMSUB instruction : dst = -fma ( m1 , m2 , -a ) .


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: tLDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s>
static
void
rs6000_parse_abi_options
(
)
{
if
(
rs6000_abi_string
==
0
)
return
;
else
if
(
!
strcmp
(
rs6000_abi_string
,
"altivec"
)
)
rs6000_altivec_abi
=
1
;
else
if
(
!
strcmp
(
rs6000_abi_string
,
"no-altivec"
)
)
rs6000_altivec_abi
=
0
;
else
error
(
"unknown ABI specified: '%s'"
,
rs6000_abi_string
)
;
}
</s>


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return SP :: I0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ args = %d, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> const uint32_t * X86RegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> static bool mmix_pass_by_reference ( cumulative_args_t argsp_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * argsp = get_cumulative_args ( argsp_v ) ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > 8 && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ; return false ; } </s>

Returns nonzero for everything that goes by reference , 0 for everything that goes by value .


<s> bool X86FixupSetCCPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 4 > ToErase ; for ( auto & MBB : MF ) { MachineInstr * FlagsDefMI = nullptr ; for ( auto & MI : MBB ) { if ( MI . definesRegister ( X86 :: EFLAGS ) ) FlagsDefMI = & MI ; if ( MI . getOpcode ( ) != X86 :: SETCCr ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( 0 ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == X86 :: MOVZX32rr8 ) ZExt = & Use ; if ( ! ZExt ) continue ; if ( ! FlagsDefMI ) continue ; if ( FlagsDefMI -> readsRegister ( X86 :: EFLAGS ) ) continue ; const TargetRegisterClass * RC = MF . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? & X86 :: GR32RegClass : & X86 :: GR32_ABCDRegClass ; if ( ! MRI -> constrainRegClass ( ZExt -> getOperand ( 0 ) . getReg ( ) , RC ) ) { continue ; } ++ NumSubstZexts ; Changed = true ; Register ZeroReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( X86 :: MOV32r0 ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( X86 :: INSERT_SUBREG ) , ZExt -> getOperand ( 0 ) . getReg ( ) ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) ) . addImm ( X86 :: sub_8bit ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCAIXAsmPrinter :: doFinalization ( Module & M ) { bool Ret = PPCAsmPrinter :: doFinalization ( M ) ; for ( MCSymbol * Sym : ExtSymSDNodeSymbols ) OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Extern ) ; return Ret ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static rtx_insn * thumb1_emit_multi_reg_push ( unsigned long mask , unsigned long real_regs ) { unsigned long regno ; rtx par [ 10 ] , tmp , reg ; rtx_insn * insn ; int i , j ; for ( i = 0 ; mask ; ++ i , mask &= mask - 1 ) { regno = ctz_hwi ( mask ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( i == 0 ) tmp = gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ; else tmp = gen_rtx_USE ( VOIDmode , reg ) ; par [ i ] = tmp ; } tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; tmp = gen_frame_mem ( BLKmode , tmp ) ; tmp = gen_rtx_SET ( VOIDmode , tmp , par [ 0 ] ) ; par [ 0 ] = tmp ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( i , par ) ) ; insn = emit_insn ( tmp ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , tmp ) ; par [ 0 ] = tmp ; for ( j = 0 ; real_regs ; ++ j , real_regs &= real_regs - 1 ) { regno = ctz_hwi ( real_regs ) ; reg = gen_rtx_REG ( SImode , regno ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , j * 4 ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( VOIDmode , tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; par [ j + 1 ] = tmp ; } if ( j == 0 ) tmp = par [ 0 ] ; else { RTX_FRAME_RELATED_P ( par [ 0 ] ) = 1 ; tmp = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec_v ( j + 1 , par ) ) ; } add_reg_note ( insn , REG_FRAME_RELATED_EXPR , tmp ) ; return insn ; } </s>

Like emit_multi_reg_push , but allowing for a different set of registers to be described as saved . MASK is the set of registers to be saved ; REAL_REGS is the set of registers to be described as saved . If REAL_REGS is 0 , only describe the stack adjustment .


<s> void CSKYMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; ++ MCNumEmitted ; uint32_t Bin = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint16_t LO16 = static_cast < uint16_t > ( Bin ) ; uint16_t HI16 = static_cast < uint16_t > ( Bin >> 16 ) ; if ( Size == 4 ) support :: endian :: write < uint16_t > ( OS , HI16 , support :: little ) ; support :: endian :: write < uint16_t > ( OS , LO16 , support :: little ) ; } </s>

Encode the given Inst to bytes and append to CB .

CSKY CSKY 16 4 support::endian support::little support::endian support::little


<s> rtx aarch64_convert_sve_data_to_pred ( rtx target , machine_mode mode , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; return aarch64_sve_emit_int_cmp ( target , mode , NE , src_mode , src , CONST0_RTX ( src_mode ) ) ; } </s>

Use a comparison to convert integer vector SRC into MODE , which is the corresponding SVE predicate mode . Use TARGET for the result if it 's nonnull and convenient .


<s> static bool pa_callee_copies ( cumulative_args_t , const function_arg_info & ) { return ! TARGET_CALLER_COPIES ; } </s>

Implement TARGET_CALLEE_COPIES . The callee is responsible for copying arguments passed by hidden reference in the 32-bit HP runtime . Users can override this behavior for better compatibility with openmp at the risk of library incompatibilities . Arguments are always passed by value in the 64-bit HP runtime .


<s> void LanaiFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const LanaiRegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; unsigned StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> int nds32_alloc_relax_group_id ( ) { return relax_group_id ++ ; } </s>

Group the following pattern as relax candidates : 1. sethi $ ra , hi20 ( sym ) ori $ ra , $ ra , lo12 ( sym ) == > addi.gp $ ra , sym 2. sethi $ ra , hi20 ( sym ) lwi $ rb , [ $ ra + lo12 ( sym ) ] == > lwi.gp $ rb , [ ( sym ) ] 3. sethi $ ra , hi20 ( sym ) ori $ ra , $ ra , lo12 ( sym ) lwi $ rb , [ $ ra ] swi $ rc , [ $ ra ] == > lwi37 $ rb , [ ( sym ) ] swi37 $ rc , [ ( sym ) ]


<s> virtual const PPCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static bool ix86_pass_by_reference ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) { HOST_WIDE_INT msize = GET_MODE_SIZE ( arg . mode ) ; if ( tree type = arg . type ) { if ( TREE_CODE ( type ) == ARRAY_TYPE ) return true ; if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != 1 && msize != 2 && msize != 4 && msize != 8 ; } else if ( arg . type && int_size_in_bytes ( arg . type ) == - 1 ) return true ; } return false ; } </s>

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type .


"No MachineFunctionInfo for this function!"


"Thumb2 instruction size reduction pass"

getPassName - Return a nice clean name for a pass .


<s> static bool nds32_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( regno >= FIRST_PSEUDO_REGISTER ) return true ; if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) && NDS32_IS_FPR_REGNUM ( regno ) ) { if ( NDS32_IS_EXT_FPR_REGNUM ( regno ) ) return ( NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) && ( mode == DFmode ) ) ; else if ( mode == SFmode || mode == SImode ) return NDS32_FPR_REGNO_OK_FOR_SINGLE ( regno ) ; else if ( mode == DFmode ) return NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) ; return false ; } if ( regno <= NDS32_LAST_GPR_REGNUM ) return ( targetm . hard_regno_nregs ( regno , mode ) == 1 || ! ( ( regno ) & 1 ) ) ; return false ; } </s>


<s> int VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const VESubtarget & Subtarget = MF . getSubtarget < VESubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP = true ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> static bool aarch64_pass_by_reference ( cumulative_args_t pcum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; machine_mode dummymode ; int nregs ; if ( mode == BLKmode && type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( type && AGGREGATE_TYPE_P ( type ) ) { size = int_size_in_bytes ( type ) ; } if ( size < 0 ) return true ; if ( aarch64_vfp_is_call_or_return_candidate ( mode , type , & dummymode , & nregs , NULL ) ) return false ; return size > 2 * UNITS_PER_WORD ; } </s>


<s> static void arm_option_params_internal ( void ) { if ( TARGET_THUMB1 ) { targetm . min_anchor_offset = 0 ; targetm . max_anchor_offset = 127 ; } else if ( TARGET_THUMB2 ) { targetm . min_anchor_offset = - 248 ; targetm . max_anchor_offset = 4095 ; } else { targetm . min_anchor_offset = TARGET_MIN_ANCHOR_OFFSET ; targetm . max_anchor_offset = TARGET_MAX_ANCHOR_OFFSET ; } if ( optimize_size ) { max_insns_skipped = 6 ; if ( TARGET_THUMB2 ) max_insns_skipped = arm_restrict_it ? 1 : 4 ; } else max_insns_skipped = ( TARGET_THUMB2 && arm_restrict_it ) ? 1 : current_tune -> max_insns_skipped ; } </s>

Recompute the global settings depending on target attribute options .


<s>
static
void
mmix_output_octa
(
FILE
*
stream
,
int64_t
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\tOCTA "
)
;
if
(
(
value
<
(
int64_t
)
0
&&
value
>
(
int64_t
)
10000
)
||
(
value
>=
(
int64_t
)
0
&&
value
<=
(
int64_t
)
16384
)
)
fprintf
(
stream
,
"%d"
,
(
int
)
value
)
;
else
if
(
value
>
(
int64_t
)
0
&&
value
<
(
(
int64_t
)
1
<<
31
)
*
2
)
fprintf
(
stream
,
"#%x"
,
(
unsigned
int
)
value
)
;
else
if
(
sizeof
(
HOST_WIDE_INT
)
==
sizeof
(
int64_t
)
)
fprintf
(
stream
,
"#"
HOST_WIDE_INT_PRINT_HEX_PURE
,
(
HOST_WIDE_INT
)
value
)
;
else
fprintf
(
stream
,
"%"
PRIu64
,
value
)
;
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Print a 64-bit value , optionally prefixed by assembly pseudo .


<s> bool WinEHStatePass :: doFinalization ( Module & M ) { assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy = nullptr ; SEHRegistrationTy = nullptr ; FrameEscape = nullptr ; FrameRecover = nullptr ; FrameAddress = nullptr ; return false ; } </s>


<s> void KudeyarRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Kudeyar :: SUB_RR ) , Kudeyar :: SP ) . addReg ( Kudeyar :: SP ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Kudeyar :: ADD_RR ) , Kudeyar :: SP ) . addReg ( Kudeyar :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Kudeyar :: SUB_RR ) , Kudeyar :: SP ) . addReg ( Kudeyar :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
unsigned
MipsMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
getMipsRegisterNumbering
(
Reg
)
;
return
RegNo
;
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
else
if
(
MO
.
isExpr
(
)
)
{
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
unsigned
Ret
=
0
;
if
(
Kind
==
MCExpr
::
Binary
)
{
const
MCBinaryExpr
*
BE
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
;
Expr
=
BE
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
const
MCConstantExpr
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
BE
->
getRHS
(
)
)
;
assert
(
(
Kind
==
MCExpr
::
SymbolRef
)
&&
CE
&&
"Binary expression must be sym+const."
)
;
Ret
=
CE
->
getValue
(
)
;
}
if
(
Kind
==
MCExpr
::
SymbolRef
)
{
Mips
::
Fixups
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
case
MCSymbolRefExpr
::
VK_Mips_GPREL
:
FixupKind
=
Mips
::
fixup_Mips_GPREL16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOT_CALL
:
FixupKind
=
Mips
::
fixup_Mips_CALL16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOT
:
FixupKind
=
Mips
::
fixup_Mips_GOT16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
FixupKind
=
Mips
::
fixup_Mips_HI16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
FixupKind
=
Mips
::
fixup_Mips_LO16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TLSGD
:
FixupKind
=
Mips
::
fixup_Mips_TLSGD
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOTTPREL
:
FixupKind
=
Mips
::
fixup_Mips_GOTTPREL
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TPREL_HI
:
FixupKind
=
Mips
::
fixup_Mips_TPREL_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TPREL_LO
:
FixupKind
=
Mips
::
fixup_Mips_TPREL_LO
;
break
;
default
:
return
Ret
;
}
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
Expr
,
MCFixupKind
(
FixupKind
)
)
)
;
}
return
Ret
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> SDValue PPCTargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG , InVals ) ; } else { return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s> bool FPGATTIImpl :: hasBranchDivergence ( ) { return true ; } </s>

Return true if branch divergence exists .


<s> static void expand_strncmp_align_check ( rtx strncmp_label , rtx src , HOST_WIDE_INT bytes ) { rtx lab_ref = gen_rtx_LABEL_REF ( VOIDmode , strncmp_label ) ; rtx src_check = copy_addr_to_reg ( XEXP ( src , 0 ) ) ; if ( GET_MODE ( src_check ) == SImode ) emit_insn ( gen_andsi3 ( src_check , src_check , GEN_INT ( 0xfff ) ) ) ; else emit_insn ( gen_anddi3 ( src_check , src_check , GEN_INT ( 0xfff ) ) ) ; rtx cond = gen_reg_rtx ( CCmode ) ; emit_move_insn ( cond , gen_rtx_COMPARE ( CCmode , src_check , GEN_INT ( 4096 - bytes ) ) ) ; rtx cmp_rtx = gen_rtx_LT ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , pc_rtx , lab_ref ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = strncmp_label ; LABEL_NUSES ( strncmp_label ) += 1 ; } </s>

Generate page crossing check and branch code to set up for strncmp when we do n't have DI alignment . STRNCMP_LABEL is the label to branch if there is a page crossing . SRC_ADDR is the string address to be examined . BYTES is the max number of bytes to compare .


<s>
const
MCFixupKindInfo
&
SystemZMCAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SystemZ
::
NumTargetFixupKinds
]
=
{
{
"FK_390_PC16DBL"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC32DBL"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_TLS_CALL"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int arm_no_early_alu_shift_dep ( rtx producer , rtx consumer ) { rtx value , op ; rtx early_op ; if ( ! arm_get_set_operands ( producer , consumer , & value , & op ) ) return 0 ; if ( ( early_op = arm_find_shift_sub_rtx ( op ) ) ) { if ( REG_P ( early_op ) ) early_op = op ; return ! reg_overlap_mentioned_p ( value , early_op ) ; } return 0 ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value or amount dependency on the result of PRODUCER .


We are choosing insn from the ready queue . Return nonzero if INSN can be chosen .


<s>
bool
AArch64FrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
const
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterInfo
*
RegInfo
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
assert
(
!
RegInfo
->
needsStackRealignment
(
MF
)
&&
"No stack realignment on AArch64!"
)
;
return
(
MFI
->
hasCalls
(
)
||
MFI
->
hasVarSizedObjects
(
)
||
MFI
->
isFrameAddressTaken
(
)
||
MFI
->
hasStackMap
(
)
||
MFI
->
hasPatchPoint
(
)
)
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void AArch64AsmPrinter :: emitJumpTableInfo ( ) { const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; if ( ! MJTI ) return ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const Function & F = MF -> getFunction ( ) ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; bool JTInDiffSection = ! STI -> isTargetCOFF ( ) || ! TLOF . shouldPutJumpTableInFunctionSection ( MJTI -> getEntryKind ( ) == MachineJumpTableInfo :: EK_LabelDifference32 , F ) ; if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; } auto AFI = MF -> getInfo < AArch64FunctionInfo > ( ) ; for ( unsigned JTI = 0 , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; emitAlignment ( Align ( Size ) ) ; OutStreamer -> emitLabel ( GetJTISymbol ( JTI ) ) ; for ( auto * JTBB : JTBBs ) emitJumpTableEntry ( MJTI , JTBB , JTI ) ; } } </s>

Print assembly representations of the jump tables used by the current function to the current output stream .


<s> bool ARMPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> bool AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA57 ( ) && ! static_cast < const AArch64TargetMachine * > ( TM ) -> isPBQPUsed ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"\nnew fndecl target specific options:\n"

"\nold fndecl target specific options:\n"

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { unsigned MaxSize = Size * 8 ; if ( ! Arg . IsFixed ) MaxSize = 0 ; assert ( Arg . Regs . size ( ) == 1 ) ; Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ 0 ] , VA , MaxSize ) : Arg . Regs [ 0 ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ; assignValueToAddress ( ValVReg , Addr , Size , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool aarch64_sve_prefetch_operand_p ( rtx op , machine_mode mode ) { struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , op , mode , false , ADDR_QUERY_ANY ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return offset_6bit_signed_scaled_p ( mode , addr . const_offset ) ; return addr . type == ADDRESS_REG_REG ; } </s>

Return true if OP is a valid address for an SVE PRF [ BHWD ] instruction , addressing memory of mode MODE .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; for ( size_t i = 0 ; i < AArch64 :: GPR32commonRegClass . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < AArch64Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , AArch64 :: GPR32commonRegClass . getRegister ( i ) ) ; } if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) markSuperRegs ( Reserved , AArch64 :: W16 ) ; if ( MF . getFunction ( ) . isPagerando ( ) ) markSuperRegs ( Reserved , AArch64 :: W20 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> SDValue LanaiSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & , const SDLoc & , SDValue , SDValue , SDValue , SDValue Size , Align , bool , bool , MachinePointerInfo , MachinePointerInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> unsigned AArch64TTI :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , OperandValueKind Opd1Info , OperandValueKind Opd2Info , OperandValueProperties Opd1PropInfo , OperandValueProperties Opd2PropInfo ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static rtx_insn * mips_emit_call_insn ( rtx pattern , rtx orig_addr , rtx addr , bool lazy_p ) { rtx_insn * insn ; rtx reg ; insn = emit_call_insn ( pattern ) ; if ( TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p ( orig_addr ) ) { reg = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; emit_insn_before ( gen_move_insn ( reg , addr ) , insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , reg ) ; } if ( lazy_p ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , pic_offset_table_rtx ) ; if ( TARGET_USE_GOT ) { use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , GOT_VERSION_REGNUM ) ) ; emit_insn ( gen_update_got_version ( ) ) ; } if ( TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP ) { rtx post_call_tmp_reg = gen_rtx_REG ( word_mode , POST_CALL_TMP_REG ) ; clobber_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , post_call_tmp_reg ) ; } return insn ; } </s>

Emit a call sequence with call pattern PATTERN and return the call instruction itself ( which is not necessarily the last instruction emitted ) . ORIG_ADDR is the original , unlegitimized address , ADDR is the legitimized form , and LAZY_P is true if the call address is lazily-bound .


<s> static bool pru_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { if ( to == STACK_POINTER_REGNUM ) return ! frame_pointer_needed ; return true ; } </s>


<s> static void ix86_emit_restore_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { struct machine_function * m = cfun -> machine ; unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( word_mode , regno ) ; rtx insn , mem ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_frame_mem ( word_mode , mem ) ; insn = emit_move_insn ( reg , mem ) ; if ( m -> fs . cfa_reg == crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) ) { add_reg_note ( insn , REG_CFA_DEF_CFA , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . drap_valid = true ; } else ix86_add_cfa_restore_note ( NULL_RTX , reg , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from POINTER + OFFSET .


<s> void SparcTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> virtual const TOYInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> unsigned X86InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { return removeBranchImpl ( MBB , BytesRemoved , false ) ; } </s>

Remove the branching code at the end of the specific MBB .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static int aarch64_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { unsigned elements ; const cpu_vector_cost * costs = aarch64_tune_params . vec_costs ; bool fp = false ; if ( vectype != NULL ) fp = FLOAT_TYPE_P ( vectype ) ; switch ( type_of_cost ) { case scalar_stmt : return fp ? costs -> scalar_fp_stmt_cost : costs -> scalar_int_stmt_cost ; case scalar_load : return costs -> scalar_load_cost ; case scalar_store : return costs -> scalar_store_cost ; case vector_stmt : return fp ? costs -> vec_fp_stmt_cost : costs -> vec_int_stmt_cost ; case vector_load : return costs -> vec_align_load_cost ; case vector_store : return costs -> vec_store_cost ; case vec_to_scalar : return costs -> vec_to_scalar_cost ; case scalar_to_vec : return costs -> scalar_to_vec_cost ; case unaligned_load : return costs -> vec_unalign_load_cost ; case unaligned_store : return costs -> vec_unalign_store_cost ; case cond_branch_taken : return costs -> cond_taken_branch_cost ; case cond_branch_not_taken : return costs -> cond_not_taken_branch_cost ; case vec_perm : return costs -> vec_permute_cost ; case vec_promote_demote : return fp ? costs -> vec_fp_stmt_cost : costs -> vec_int_stmt_cost ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool X86InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == X86 :: ENDBR64 || Opcode == X86 :: ENDBR32 ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case FK_NONE : return true ; case PPC :: fixup_ppc_br24 : case PPC :: fixup_ppc_br24abs : if ( const MCSymbolRefExpr * A = Target . getSymA ( ) ) { if ( const auto * S = dyn_cast < MCSymbolELF > ( & A -> getSymbol ( ) ) ) { unsigned Other = S -> getOther ( ) << 2 ; if ( ( Other & ELF :: STO_PPC64_LOCAL_MASK ) != 0 ) return true ; } } return false ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
llvm_unreachable
(
"applyFixup() unimplemented"
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Condition Optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


runOnMachineFunction - Emit the function body .


<s> bool shouldBuildLookupTablesForConstant ( Constant * C ) const { if ( ST -> isROPI ( ) || ST -> isRWPI ( ) ) return ! C -> needsRelocation ( ) ; return true ; } </s>

Return true if switches should be turned into lookup tables containing this constant value for the target .


<s> static HOST_WIDE_INT aarch64_clamp_to_uimm12_shift ( HOST_WIDE_INT val ) { gcc_assert ( ( val & 0xffffff ) == val ) ; if ( ( ( val & 0xfff ) << 0 ) == val ) return val ; return val & ( 0xfff << 12 ) ; } </s>

Returns the nearest value to VAL that will fit as a 12-bit unsigned immediate that can be created with a left shift of 0 or 12 .


<s> static bool mips_use_anchors_for_symbol_p ( const_rtx symbol ) { switch ( mips_classify_symbol ( symbol , SYMBOL_CONTEXT_MEM ) ) { case SYMBOL_PC_RELATIVE : case SYMBOL_GP_RELATIVE : return false ; default : return default_use_anchors_for_symbol_p ( symbol ) ; } } </s>

Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P . We do n't want to use anchors for small data : the GP register acts as an anchor in that case . We also do n't want to use them for PC-relative accesses , where the PC acts as an anchor .


<s> rtx function_expander :: use_contiguous_prefetch_insn ( insn_code icode ) { add_input_operand ( icode , args [ 0 ] ) ; add_address_operand ( get_contiguous_base ( VNx16QImode ) ) ; for ( unsigned int i = args . length ( ) - 3 ; i < args . length ( ) ; ++ i ) add_input_operand ( icode , args [ i ] ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , which prefetches from address operand 1 under the control of predicate operand 0 . Operands 2 , 3 and 4 respectively specify the svprfop value , the PREFETCH rw flag and the PREFETCH locality .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FJ != FE ; ++ FI , ++ FJ ) Changed |= runOnMachineBasicBlock ( * FI , * FJ ) ; } return Changed ; } </s>


<s>
void
SystemZHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCSchedClassDesc
*
SC
=
getSchedClass
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"++ HazardRecognizer emitting "
;
dumpSU
(
SU
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
LLVM_DEBUG
(
dumpCurrGroup
(
"Decode group before emission"
)
;
)
;
if
(
!
fitsIntoCurrentGroup
(
SU
)
)
nextGroup
(
)
;
LLVM_DEBUG
(
raw_string_ostream
cgd
(
CurGroupDbg
)
;
if
(
CurGroupDbg
.
length
(
)
)
cgd
<<
", "
;
dumpSU
(
SU
,
cgd
)
;
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
if
(
SU
->
isCall
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"++ Clearing state after call.\n"
;
)
;
Reset
(
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
return
;
}
for
(
TargetSchedModel
::
ProcResIter
PI
=
SchedModel
->
getWriteProcResBegin
(
SC
)
,
PE
=
SchedModel
->
getWriteProcResEnd
(
SC
)
;
PI
!=
PE
;
++
PI
)
{
if
(
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
BufferSize
==
1
)
continue
;
int
&
CurrCounter
=
ProcResourceCounters
[
PI
->
ProcResourceIdx
]
;
CurrCounter
+=
PI
->
Cycles
;
if
(
(
CurrCounter
>
ProcResCostLim
)
&&
(
CriticalResourceIdx
==
UINT_MAX
||
(
PI
->
ProcResourceIdx
!=
CriticalResourceIdx
&&
CurrCounter
>
ProcResourceCounters
[
CriticalResourceIdx
]
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"++ New critical resource: "
<<
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
Name
<<
"\n"
;
)
;
CriticalResourceIdx
=
PI
->
ProcResourceIdx
;
}
}
if
(
SU
->
isUnbuffered
)
{
LastFPdOpCycleIdx
=
getCurrCycleIdx
(
SU
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"++ Last FPd cycle index: "
<<
LastFPdOpCycleIdx
<<
"\n"
;
)
;
}
CurrGroupSize
+=
getNumDecoderSlots
(
SU
)
;
CurrGroupHas4RegOps
|=
has4RegOps
(
SU
->
getInstr
(
)
)
;
unsigned
GroupLim
=
(
(
CurrGroupHas4RegOps
&&
getNumDecoderSlots
(
SU
)
<
3
)
2
:
3
)
;
assert
(
CurrGroupSize
<=
GroupLim
&&
"SU does not fit into decoder group!"
)
;
if
(
CurrGroupSize
==
GroupLim
||
SC
->
EndGroup
)
nextGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

SystemZ
SystemZ
"++ HazardRecognizer emitting "
"\n"
"Decode group before emission"
", "
"++ Clearing state after call.\n"
1
"++ New critical resource: "
"\n"
"++ Last FPd cycle index: "
"\n"
3
2
3
"SU does not fit into decoder group!"


<s> static bool is_store_insn1 ( rtx pat ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) return is_mem_ref ( SET_DEST ( pat ) ) ; if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_store_insn1 ( XVECEXP ( pat , 0 , i ) ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a store insn .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCContext & Context = MCA . getContext ( ) ; MCStreamer & OS = getStreamer ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; uint64_t Features = STI . getFeatureBits ( ) ; if ( T . isArch64Bit ( ) && ( Features & Mips :: FeatureN64 ) ) { const MCSectionELF * Sec = Context . getELFSection ( ".MIPS.options" , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 1 , 1 ) ; OS . EmitIntValue ( 40 , 1 ) ; OS . EmitIntValue ( 0 , 2 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 8 ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( ".reginfo" , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; } emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> bool Error ( SMLoc L , const Twine & Msg , SMRange Range = None , bool MatchingInlineAsm = false ) { MCAsmParser & Parser = getParser ( ) ; if ( MatchingInlineAsm ) { if ( ! getLexer ( ) . isAtStartOfStatement ( ) ) Parser . eatToEndOfStatement ( ) ; return false ; } return Parser . Error ( L , Msg , Range ) ; } </s>

Return an error at the location L , with the message Msg .


<s> TargetLowering :: ConstraintWeight Cpu0TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & Info , const char * Constraint ) const { ConstraintWeight Weight = CW_Invalid ; Value * CallOperandVal = Info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * T = CallOperandVal -> getType ( ) ; switch ( * Constraint ) { default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ; break ; case 'c' : if ( T -> isIntegerTy ( ) ) Weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; case 'R' : Weight = CW_Memory ; break ; } return Weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
bool
X86InstrInfo
::
classifyLEAReg
(
MachineInstr
&
MI
,
const
MachineOperand
&
Src
,
unsigned
Opc
,
bool
AllowSP
,
unsigned
&
NewSrc
,
bool
&
isKill
,
MachineOperand
&
ImplicitOp
,
LiveVariables
*
LV
)
const
{
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
TargetRegisterClass
*
RC
;
if
(
AllowSP
)
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64RegClass
:
&
X86
::
GR32RegClass
;
}
else
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64_NOSPRegClass
:
&
X86
::
GR32_NOSPRegClass
;
}
unsigned
SrcReg
=
Src
.
getReg
(
)
;
if
(
Opc
!=
X86
::
LEA64_32r
)
{
NewSrc
=
SrcReg
;
isKill
=
Src
.
isKill
(
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
NewSrc
)
&&
!
MF
.
getRegInfo
(
)
.
constrainRegClass
(
NewSrc
,
RC
)
)
return
false
;
return
true
;
}
if
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
)
{
ImplicitOp
=
Src
;
ImplicitOp
.
setImplicit
(
)
;
NewSrc
=
getX86SubSuperRegister
(
Src
.
getReg
(
)
,
64
)
;
isKill
=
Src
.
isKill
(
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
}
else
{
NewSrc
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MachineInstr
*
Copy
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
TargetOpcode
::
COPY
)
)
.
addReg
(
NewSrc
,
RegState
::
Define
|
RegState
::
Undef
,
X86
::
sub_32bit
)
.
add
(
Src
)
;
isKill
=
true
;
if
(
LV
)
LV
->
replaceKillInstruction
(
SrcReg
,
MI
,
*
Copy
)
;
}
return
true
;
}
</s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> unsigned ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) || MI . isImplicitDef ( ) ) return 1 ; if ( MI . isBundle ( ) ) { unsigned Latency = 0 ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != ARM :: t2IT ) Latency += getInstrLatency ( ItinData , * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) ) ) { * PredCost = 1 ; } if ( ! ItinData ) return MI . mayLoad ( ) ? 3 : 1 ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < 0 ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Adj = adjustDefLatency ( Subtarget , MI , MCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


<s> void XNCMRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { llvm_unreachable ( 0 ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static struct machine_function * pru_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> EVT ARMTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static bool mips_split_addresses_p ( void ) { return ( TARGET_SPLIT_ADDRESSES && optimize && ! TARGET_MIPS16 && ! flag_pic && ! ABI_HAS_64BIT_SYMBOLS ) ; } </s>

Return true if -msplit-addresses is selected and should be honored . -msplit-addresses is a half-way house between explicit relocations and the traditional assembler macros . It can split absolute 32-bit symbolic constants into a high/lo_sum pair but uses macros for other sorts of access . Like explicit relocation support for REL targets , it relies on GNU extensions in the assembler and the linker . Although this code should work for -O0 , it has traditionally been treated as an optimization .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
Modified
|=
runOnInstruction
(
&
MI
)
;
}
}
for
(
MachineInstr
*
MI
:
DeadInstr
)
{
MI
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>


<s> StringRef getPassName ( ) const override { return PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
AArch64
::
NumTargetFixupKinds
]
=
{
{
"fixup_aarch64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_movw"
,
5
,
16
,
0
}
,
{
"fixup_aarch64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_tlsdesc_call"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void ARMBankConflictHazardRecognizer :: AdvanceCycle ( ) { Accesses . clear ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( & getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16Pass ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloatPass ( getMipsTargetMachine ( ) ) ) ; if ( DirectToNaCl ) { addPass ( createExpandVarArgsPass ( ) ) ; addPass ( createExpandByValPass ( ) ) ; addPass ( createAddPNaClExternalDeclsPass ( ) ) ; addPass ( createResolvePNaClIntrinsicsPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> int ix86_local_alignment ( tree type , int align ) { if ( TARGET_64BIT ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= 16 || TREE_INT_CST_HIGH ( TYPE_SIZE ( type ) ) ) && align < 128 ) return 128 ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( TYPE_MODE ( type ) == XCmode && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> OperandMatchResultTy SparcAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = Parser . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_Success ; Parser . Lex ( ) ; unsigned regKind = SparcOperand :: rk_None ; if ( matchRegisterName ( Tok , RegNo , regKind ) ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


<s> static int gen_v9_scc ( rtx dest , enum rtx_code compare_code , rtx x , rtx y ) { if ( ! TARGET_ARCH64 && ( GET_MODE ( x ) == DImode || GET_MODE ( dest ) == DImode ) ) return 0 ; if ( TARGET_ARCH64 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_INT && y == const0_rtx && v9_regcmp_p ( compare_code ) ) { rtx op0 = x ; rtx temp ; if ( compare_code == NE && GET_MODE ( dest ) == DImode && rtx_equal_p ( op0 , dest ) ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_fmt_ee ( compare_code , DImode , op0 , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } if ( reg_overlap_mentioned_p ( dest , op0 ) ) { op0 = gen_reg_rtx ( GET_MODE ( x ) ) ; emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , 0 ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } else { x = gen_compare_reg_1 ( compare_code , x , y ) ; y = const0_rtx ; emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , GET_MODE ( x ) , x , y ) , const1_rtx , dest ) ) ) ; return 1 ; } } </s>

This function is used for v9 only . CODE is the code for an Scc 's comparison . OPERANDS [ 0 ] is the target of the Scc insn . OPERANDS [ 1 ] is the value we compare against const0_rtx ( which has n't been generated yet ) . This function is needed to turn ( set ( reg : SI 110 ) ( gt ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) into ( set ( reg : SI 110 ) ( gt : DI ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) IE : The instruction recognizer needs to see the mode of the comparison to find the right instruction . We could use `` gt : DI '' right in the define_expand , but leaving it out allows us to handle DI , SI , etc . We refer to the global sparc compare operands sparc_compare_op0 and sparc_compare_op1 .


<s> bool LEGPassConfig :: addPreEmitPass ( ) { return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void ix86_expand_binary_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx src1 , src2 , dst , op , clob ; dst = ix86_fixup_binary_operands ( code , mode , operands ) ; src1 = operands [ 1 ] ; src2 = operands [ 2 ] ; op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ; if ( reload_completed && code == PLUS && ! rtx_equal_p ( dst , src1 ) ) { emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a binary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 3 separate memory references ( one output , two input ) in a single insn .


<s> bool ARMTargetLowering :: alignLoopsWithOptSize ( ) const { return Subtarget -> isMClass ( ) ; } </s>

Should loops be aligned even when the function is marked OptSize ( but not MinSize ) .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> rtx ix86_build_signbit_mask ( machine_mode mode , bool vect , bool invert ) { machine_mode vec_mode , imode ; wide_int w ; rtx mask , v ; switch ( mode ) { case V16SImode : case V16SFmode : case V8SImode : case V4SImode : case V8SFmode : case V4SFmode : vec_mode = mode ; imode = SImode ; break ; case V8DImode : case V4DImode : case V2DImode : case V8DFmode : case V4DFmode : case V2DFmode : vec_mode = mode ; imode = DImode ; break ; case TImode : case TFmode : vec_mode = VOIDmode ; imode = TImode ; break ; default : gcc_unreachable ( ) ; } machine_mode inner_mode = GET_MODE_INNER ( mode ) ; w = wi :: set_bit_in_zero ( GET_MODE_BITSIZE ( inner_mode ) - 1 , GET_MODE_BITSIZE ( inner_mode ) ) ; if ( invert ) w = wi :: bit_not ( w ) ; mask = immed_wide_int_const ( w , imode ) ; mask = gen_lowpart ( inner_mode , mask ) ; if ( vec_mode == VOIDmode ) return force_reg ( inner_mode , mask ) ; v = ix86_build_const_vector ( vec_mode , vect , mask ) ; return force_reg ( vec_mode , v ) ; } </s>

A subroutine of ix86_expand_fp_absneg_operator and copysign expanders . Create a mask for the sign bit in MODE for an SSE register . If VECT is true , then replicate the mask for all elements of the vector register . If INVERT is true , then create a mask excluding the sign bit .


<s> rtx ix86_expand_adjust_ufix_to_sfix_si ( rtx val , rtx * xorp ) { REAL_VALUE_TYPE TWO31r ; rtx two31r , tmp [ 4 ] ; machine_mode mode = GET_MODE ( val ) ; machine_mode scalarmode = GET_MODE_INNER ( mode ) ; machine_mode intmode = GET_MODE_SIZE ( mode ) == 32 ? V8SImode : V4SImode ; rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = 0 ; i < 3 ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , 1 , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ 3 ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ 0 ] , two31r , val , tmp [ 3 ] ) ) ; tmp [ 1 ] = expand_simple_binop ( mode , AND , tmp [ 0 ] , two31r , tmp [ 1 ] , 0 , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ 0 ] ) , GEN_INT ( 31 ) , NULL_RTX , 0 , OPTAB_DIRECT ) ; else { rtx two31 = GEN_INT ( ( unsigned HOST_WIDE_INT ) 1 << 31 ) ; two31 = ix86_build_const_vector ( intmode , 1 , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [ 0 ] ) , two31 , NULL_RTX , 0 , OPTAB_DIRECT ) ; } return expand_simple_binop ( mode , MINUS , val , tmp [ 1 ] , tmp [ 2 ] , 0 , OPTAB_DIRECT ) ; } </s>

Adjust a V * SFmode/V * DFmode value VAL so that * sfix_trunc * resp . fix_trunc * pattern can be used on it instead of fixuns_trunc * . This is done by doing just signed conversion if < 0x1p31 , and otherwise by subtracting 0x1p31 first and xoring in 0x80000000 from * XORP afterwards .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createX86MachObjectWriter ( OS , true , MachO :: CPU_TYPE_X86_64 , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"Unexpected operand for inline assembly"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static void vr4130_align_insns ( void ) { struct mips_sim state ; rtx insn , subinsn , last , last2 , next ; bool aligned_p ; dfa_start ( ) ; last = 0 ; last2 = 0 ; aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; if ( USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn ) ; length = get_attr_length ( insn ) ; if ( length > 0 ) { if ( NONJUMP_INSN_P ( SEQ_BEGIN ( insn ) ) && ( recog_memoized ( insn ) < 0 || length >= 8 ) ) { next = emit_insn_after ( gen_align ( GEN_INT ( 3 ) ) , insn ) ; next = NEXT_INSN ( next ) ; mips_sim_next_cycle ( & state ) ; aligned_p = true ; } else if ( length & 4 ) aligned_p = ! aligned_p ; last2 = last ; last = insn ; } if ( LABEL_P ( insn ) && label_to_alignment ( insn ) >= 3 ) aligned_p = true ; } dfa_finish ( ) ; } </s>

Implement -mvr4130-align . Go through each basic block and simulate the processor pipeline . If we find that a pair of instructions could execute in parallel , and the first of those instruction is not 8-byte aligned , insert a nop to make it aligned .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MMI
=
&
getAnalysis
<
MachineModuleInfo
>
(
)
;
MCE
.
setModuleInfo
(
MMI
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
++
NumEmitted
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
Optional
<
DestSourcePair
>
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
int64_t
&
Offset
)
const
{
int
Sign
=
1
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
;
Offset
=
MI
.
getOperand
(
2
)
.
getImm
(
)
*
Sign
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Offset
<<
Shift
;
}
}
return
DestSourcePair
{
MI
.
getOperand
(
0
)
,
MI
.
getOperand
(
1
)
}
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { MIB . addUse ( PhysReg , RegState :: Implicit ) ; unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static fixed_size_mode mips_get_reg_raw_mode ( int regno ) { if ( TARGET_FLOATXX && FP_REG_P ( regno ) ) return DFmode ; return default_get_reg_raw_mode ( regno ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
bool
X86InsertPrefetch
::
doInitialization
(
Module
&
M
)
{
if
(
Filename
.
empty
(
)
)
return
false
;
LLVMContext
&
Ctx
=
M
.
getContext
(
)
;
ErrorOr
<
std
::
unique_ptr
<
SampleProfileReader
>>
ReaderOrErr
=
SampleProfileReader
::
create
(
Filename
,
Ctx
)
;
if
(
std
::
error_code
EC
=
ReaderOrErr
.
getError
(
)
)
{
std
::
string
Msg
=
"Could not open profile: "
+
EC
.
message
(
)
;
Ctx
.
diagnose
(
DiagnosticInfoSampleProfile
(
Filename
,
Msg
,
DiagnosticSeverity
::
DS_Warning
)
)
;
return
false
;
}
Reader
=
std
::
move
(
ReaderOrErr
.
get
(
)
)
;
Reader
->
read
(
)
;
return
true
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> static int pa_reloc_rw_mask ( void ) { return 3 ; } </s>


<s> bool PPCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MFI -> getStackSize ( ) ) && needsFP ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .