<s> static int mips_fp_div_cost ( machine_mode mode ) { return mode == DFmode ? mips_cost -> fp_div_df : mips_cost -> fp_div_sf ; } </s>

Return the cost of floating-point divisions of mode MODE .


<s> static inline bool save_global_or_fp_reg_p ( unsigned int regno , int leaf_function ATTRIBUTE_UNUSED ) { return ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ; } </s>

Return whether REGNO , a global or FP register , must be saved/restored .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : if ( ! Subtarget . is64Bit ( ) ) return false ; LLVM_FALLTHROUGH ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVSX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( EVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = ( Subtarget -> is64Bit ( ) ? X86 :: GR64RegisterClass : X86 :: GR32RegisterClass ) ; break ; case MVT :: x86mmx : RRC = X86 :: VR64RegisterClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = X86 :: VR128RegisterClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> unsigned SparcInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == SP :: STri || MI . getOpcode ( ) == SP :: STXri || MI . getOpcode ( ) == SP :: STFri || MI . getOpcode ( ) == SP :: STDFri || MI . getOpcode ( ) == SP :: STQFri ) { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
void
F2003fMCAsmStreamer
::
emitFill
(
const
MCExpr
&
NumValues
,
int64_t
Size
,
int64_t
Expr
,
SMLoc
Loc
)
{
llvm_unreachable
(
"2003lk doesn't support this directive"
)
;
}
</s>

Emit Size bytes worth of the value specified by FillValue .


<s>
static
void
or1k_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
'#'
:
if
(
final_sequence
==
)
fputs
(
"\n\t l.nop\n"
,
file
)
;
break
;
case
'r'
:
if
(
REG_P
(
x
)
)
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
else
if
(
x
==
CONST0_RTX
(
GET_MODE
(
x
)
)
)
fprintf
(
file
,
"r0"
)
;
else
output_operand_lossage
(
"invalid %%r value"
)
;
break
;
case
'H'
:
if
(
REG_P
(
x
)
)
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
+
1
]
)
;
else
output_operand_lossage
(
"invalid %%H value"
)
;
break
;
case
'h'
:
print_reloc
(
file
,
x
,
0
,
RKIND_HI
)
;
break
;
case
'L'
:
print_reloc
(
file
,
x
,
0
,
RKIND_LO
)
;
break
;
case
'P'
:
if
(
!
flag_pic
||
SYMBOL_REF_LOCAL_P
(
x
)
)
output_addr_const
(
file
,
x
)
;
else
output_addr_reloc
(
file
,
x
,
0
,
"plt"
)
;
break
;
case
0
:
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
if
(
REGNO
(
operand
)
>
31
)
internal_error
(
"internal error: bad register: %d"
,
REGNO
(
operand
)
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
break
;
case
MEM
:
output_address
(
GET_MODE
(
XEXP
(
operand
,
0
)
)
,
XEXP
(
operand
,
0
)
)
;
break
;
case
CODE_LABEL
:
case
LABEL_REF
:
output_asm_label
(
operand
)
;
break
;
default
:
if
(
CONSTANT_P
(
operand
)
)
output_addr_const
(
file
,
operand
)
;
else
internal_error
(
"unexpected operand: %d"
,
GET_CODE
(
operand
)
)
;
break
;
}
break
;
default
:
output_operand_lossage
(
"unknown operand letter: '%c'"
,
code
)
;
break
;
}
}
</s>

Worker for TARGET_PRINT_OPERAND . Print operand X , an RTX , to the file FILE . The output is formed as expected by the OpenRISC assember . CODE is the letter following a ' % ' in an instrunction template used to control the RTX output . Example ( s ) : CODE RTX OUTPUT COMMENT 0 ( reg : SI 3 ) r3 output an operand r ( reg : SI 3 ) r3 output a register or const zero H ( reg : SI 3 ) r4 output the high pair register h ( symbol_ref : SI ( `` x '' ) ) ha ( x ) output a signed high relocation L ( symbol_ref : SI ( `` x '' ) ) lo ( x ) output a low relocation Note , ' # ' is a special code used to fill the branch delay slot with an l.nop instruction . The l.nop ( no-op ) instruction is only outputted when the delay slot has not been filled .


<s> void ARMInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << markup ( "<reg:" ) << getRegisterName ( RegNo , DefaultAltIdx ) << markup ( ">" ) ; } </s>


<s> void DLXTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> virtual const KudeyarInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" || Constraint == "wi" || Constraint == "ww" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws" "wi" "ww"


<s>
void
MipsInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\t.set\tpush\n"
;
O
<<
"\t.set\tmips32r2\n"
;
break
;
case
Mips
::
Save16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
SaveX16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
case
Mips
::
Restore16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
RestoreX16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
O
)
;
O
<<
"\n"
;
return
;
}
if
(
!
printAliasInstr
(
MI
,
Address
,
O
)
&&
!
printAlias
(
*
MI
,
O
)
)
printInstruction
(
MI
,
Address
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\n\t.set\tpop"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s>
bool
SHUXIInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
I
->
getOpcode
(
)
==
SHUXI
::
JMP
)
{
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
I
->
getOpcode
(
)
==
SHUXI
::
JCC
&&
"Invalid conditional branch"
)
;
SHUXICC
::
CondCodes
BranchCode
=
static_cast
<
SHUXICC
::
CondCodes
>
(
I
->
getOperand
(
1
)
.
getImm
(
)
)
;
if
(
BranchCode
==
SHUXICC
::
COND_INVALID
)
return
true
;
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
1
)
;
assert
(
TBB
)
;
if
(
TBB
!=
I
->
getOperand
(
0
)
.
getMBB
(
)
)
return
true
;
SHUXICC
::
CondCodes
OldBranchCode
=
(
SHUXICC
::
CondCodes
)
Cond
[
0
]
.
getImm
(
)
;
if
(
OldBranchCode
==
BranchCode
)
continue
;
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> int ia64_st_address_bypass_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx dest , reg , mem ; gcc_assert ( producer && consumer ) ; dest = ia64_single_set ( producer ) ; gcc_assert ( dest ) ; reg = SET_DEST ( dest ) ; gcc_assert ( reg ) ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; gcc_assert ( GET_CODE ( reg ) == REG ) ; dest = ia64_single_set ( consumer ) ; gcc_assert ( dest ) ; mem = SET_DEST ( dest ) ; gcc_assert ( mem && GET_CODE ( mem ) == MEM ) ; return reg_mentioned_p ( reg , mem ) ; } </s>

The following function returns TRUE if PRODUCER ( of type ilog or ld ) produces address for CONSUMER ( of type st or stf ) .


<s> static void emit_cbcond_insn ( enum rtx_code code , rtx op0 , rtx op1 , rtx label ) { rtx if_then_else ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_then_else ) ) ; } </s>

Emit a conditional jump insn for the UA2011 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the UA2011 Compare and Branch insns .


<s> bool sh_can_use_simple_return_p ( void ) { if ( ! reload_completed || frame_pointer_needed ) return false ; if ( optimize_function_for_size_p ( cfun ) ) return false ; HARD_REG_SET live_regs_mask ; int d = calc_live_regs ( & live_regs_mask ) ; if ( rounded_frame_size ( d ) > 4 ) return false ; return true ; } </s>

Return true if it is appropriate to emit ` ret ' instructions in the body of a function .


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( EVT VT ) const { if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegClass MVT::v8i64 ARM::QQQQPRRegClass


<s> void CSKYInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s> bool AArch64Subtarget :: enableEarlyIfConversion ( ) const { return EnableEarlyIfConvert ; } </s>

Enable the use of the early if conversion pass .


<s> MachineBasicBlock :: iterator begin ( ) const { return getStart ( ) ; } </s>


<s>
bool
Cpu0DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static unsigned int aarch64_case_values_threshold ( void ) { if ( optimize > 2 && selected_cpu -> tune -> max_case_values != 0 ) return selected_cpu -> tune -> max_case_values ; else return default_case_values_threshold ( ) ; } </s>


<s> static int mips_register_priority ( int hard_regno ) { if ( TARGET_MIPS16 && TEST_HARD_REG_BIT ( reg_class_contents [ M16_REGS ] , hard_regno ) ) return 1 ; return 0 ; } </s>


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> void AnalyzeReturn ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { PreAnalyzeReturn ( Outs , Fn ) ; CCState :: AnalyzeReturn ( Outs , Fn ) ; } </s>

AnalyzeReturn - Analyze the returned values of a return , incorporating info about the result values into this state .


<s> unsigned ARMFastISel :: fastEmitInst_i ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , uint64_t Imm ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with a single immediate operand , and a result register in the given register class .


<s> static void mips_legitimize_const_move ( enum machine_mode mode , rtx dest , rtx src ) { rtx base ; HOST_WIDE_INT offset ; enum mips_symbol_type symbol_type ; if ( GET_CODE ( src ) == CONST_INT && ! TARGET_MIPS16 ) { mips_move_integer ( dest , INTVAL ( src ) ) ; return ; } if ( mips_tls_operand_p ( src ) ) { emit_move_insn ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } if ( ! TARGET_MIPS16 && mips_symbolic_constant_p ( src , & symbol_type ) && mips_split_p [ symbol_type ] ) { emit_move_insn ( dest , mips_split_symbol ( dest , src ) ) ; return ; } mips_split_const ( src , & base , & offset ) ; if ( ! TARGET_MIPS16 && offset != 0 && ( ! no_new_pseudos || SMALL_OPERAND ( offset ) ) ) { base = mips_force_temporary ( dest , base ) ; emit_move_insn ( dest , mips_add_offset ( 0 , base , offset ) ) ; return ; } src = force_const_mem ( mode , src ) ; if ( ! memory_operand ( src , VOIDmode ) ) src = replace_equiv_address ( src , mips_split_symbol ( dest , XEXP ( src , 0 ) ) ) ; emit_move_insn ( dest , src ) ; } </s>

Subroutine of mips_legitimize_move . Move constant SRC into register DEST given that SRC satisfies immediate_operand but does n't satisfy move_operand .


<s>
virtual
ScheduleHazardRecognizer
*
CreateTargetHazardRecognizer
(
)
{
const
TargetInstrInfo
*
II
=
TM
.
getInstrInfo
(
)
;
assert
(
II
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
II
)
;
}
</s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s>
void
insert
(
MachineInstr
*
MI
)
{
Insts
.
push_back
(
MI
)
;
assert
(
Insts
.
size
(
)
<=
5
&&
"Too many instructions in VPT block!"
)
;
}
</s>

insert - Append entry to the vector if it does n't already exist .

ARM
5
"Too many instructions in VPT block!"


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = 0 ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = 0 ; } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum -> force_bnd_pass = nregs ; if ( ! nregs ) cum -> bnds_in_bt = chkp_type_bounds_count ( type ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> TTI :: AddressingModeKind ARMTTIImpl :: getPreferredAddressingMode ( const Loop * L , ScalarEvolution * SE ) const { if ( ST -> hasMVEIntegerOps ( ) ) return TTI :: AMK_PostIndexed ; if ( L -> getHeader ( ) -> getParent ( ) -> hasOptSize ( ) ) return TTI :: AMK_None ; if ( ST -> isMClass ( ) && ST -> isThumb2 ( ) && L -> getNumBlocks ( ) == 1 ) return TTI :: AMK_PreIndexed ; return TTI :: AMK_None ; } </s>

Return the preferred addressing mode LSR should make efforts to generate .


<s> bool hasFusion ( ) const { return hasFuseAES ( ) ; } </s>

Return true if the CPU supports any kind of instruction fusion .


<s> void Mips16FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TII . adjustStackPtr ( Mips :: SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips Mips Mips::SP


<s> int mt_reg_ok_for_base_p ( rtx x , int strict ) { if ( strict ) return ( ( ( unsigned ) REGNO ( x ) ) < FIRST_PSEUDO_REGISTER ) ; return 1 ; } </s>


<s> static bool csky_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { if ( to == FRAME_POINTER_REGNUM ) return from != ARG_POINTER_REGNUM ; if ( to == STACK_POINTER_REGNUM ) return ! frame_pointer_needed ; return true ; } </s>


<s> static int ix86_reloc_rw_mask ( void ) { return ( flag_pic || ! ix86_direct_extern_access ) ? 3 : 0 ; } </s>

If flag_pic or ix86_direct_extern_access is false , then neither local nor global relocs should be placed in readonly memory .


<s> static void mips_record_lo_sums ( const_rtx x , mips_offset_table * htab ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( GET_CODE ( * iter ) == LO_SUM ) mips_lo_sum_offset_lookup ( htab , XEXP ( * iter , 1 ) , INSERT ) ; } </s>

Search X for LO_SUMs and record them in HTAB .


Function to check whether the OP is a valid load/store operation . This is a helper function for the predicates : 'nds32_load_multiple_operation ' and 'nds32_store_multiple_operation ' in predicates.md file . The OP is supposed to be a parallel rtx . For each element within this parallel rtx : ( set ( reg ) ( mem addr ) ) is the form for load operation . ( set ( mem addr ) ( reg ) ) is the form for store operation . We have to extract reg and mem of every element and check if the information is valid for multiple load/store operation .


<s> const SparcMCExpr * SparcMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) SparcMCExpr ( Kind , Expr ) ; } </s>


<s> bool PPCFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , ISD :: ADD ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , ISD :: OR ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , ISD :: SUB ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I ) ; default : break ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s>
static
void
xstormy16_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
switch
(
code
)
{
case
'B'
:
{
static
int
bits_set
[
8
]
=
{
0
,
1
,
1
,
2
,
1
,
2
,
2
,
3
}
;
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
if
(
bits_set
[
xx
&
7
]
<=
1
)
{
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
&=
0xff
;
else
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
&=
0xffff
;
l
=
exact_log2
(
xx
)
;
}
else
{
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xff
;
else
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xffff
;
l
=
exact_log2
(
~
xx
)
;
}
if
(
l
==
1
)
output_operand_lossage
(
"'B' operand has multiple bits set"
)
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
'C'
:
if
(
GET_CODE
(
x
)
==
SYMBOL_REF
)
assemble_name
(
file
,
XSTR
(
x
,
0
)
)
;
else
if
(
LABEL_P
(
x
)
)
output_asm_label
(
x
)
;
else
xstormy16_print_operand_address
(
file
,
x
)
;
return
;
case
'o'
:
case
'O'
:
{
HOST_WIDE_INT
xx
=
0
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'o' operand is not constant"
)
;
if
(
code
==
'O'
)
xx
=
xx
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
xx
1
)
;
return
;
}
case
'b'
:
{
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
l
=
7
xx
;
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
0
:
break
;
default
:
output_operand_lossage
(
"xstormy16_print_operand: unknown code"
)
;
return
;
}
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
fputs
(
reg_names
[
REGNO
(
x
)
]
,
file
)
;
break
;
case
MEM
:
xstormy16_print_operand_address
(
file
,
XEXP
(
x
,
0
)
)
;
break
;
default
:
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
output_addr_const
(
file
,
x
)
;
break
;
}
return
;
}
</s>

Print an operand to an assembler instruction .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return MCInstLowering . lowerOperand ( MO , MCOp ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> machine_mode arm_select_dominance_cc_mode ( rtx x , rtx y , HOST_WIDE_INT cond_or ) { enum rtx_code cond1 , cond2 ; int swapped = 0 ; if ( ( arm_select_cc_mode ( cond1 = GET_CODE ( x ) , XEXP ( x , 0 ) , XEXP ( x , 1 ) ) != CCmode ) || ( arm_select_cc_mode ( cond2 = GET_CODE ( y ) , XEXP ( y , 0 ) , XEXP ( y , 1 ) ) != CCmode ) ) return CCmode ; if ( cond_or == DOM_CC_NX_OR_Y ) cond1 = reverse_condition ( cond1 ) ; if ( cond1 != cond2 && ! comparison_dominates_p ( cond1 , cond2 ) && ( swapped = 1 , ! comparison_dominates_p ( cond2 , cond1 ) ) ) return CCmode ; if ( swapped ) std :: swap ( cond1 , cond2 ) ; switch ( cond1 ) { case EQ : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DEQmode ; switch ( cond2 ) { case EQ : return CC_DEQmode ; case LE : return CC_DLEmode ; case LEU : return CC_DLEUmode ; case GE : return CC_DGEmode ; case GEU : return CC_DGEUmode ; default : gcc_unreachable ( ) ; } case LT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTmode ; switch ( cond2 ) { case LT : return CC_DLTmode ; case LE : return CC_DLEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GT : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTmode ; switch ( cond2 ) { case GT : return CC_DGTmode ; case GE : return CC_DGEmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case LTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DLTUmode ; switch ( cond2 ) { case LTU : return CC_DLTUmode ; case LEU : return CC_DLEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case GTU : if ( cond_or == DOM_CC_X_AND_Y ) return CC_DGTUmode ; switch ( cond2 ) { case GTU : return CC_DGTUmode ; case GEU : return CC_DGEUmode ; case NE : return CC_DNEmode ; default : gcc_unreachable ( ) ; } case NE : gcc_assert ( cond1 == cond2 ) ; return CC_DNEmode ; case LE : gcc_assert ( cond1 == cond2 ) ; return CC_DLEmode ; case GE : gcc_assert ( cond1 == cond2 ) ; return CC_DGEmode ; case LEU : gcc_assert ( cond1 == cond2 ) ; return CC_DLEUmode ; case GEU : gcc_assert ( cond1 == cond2 ) ; return CC_DGEUmode ; default : gcc_unreachable ( ) ; } } </s>

Select a dominance comparison mode if possible for a test of the general form ( OP ( COND_OR ( X ) ( Y ) ) ( const_int 0 ) ) . We support three forms . COND_OR == DOM_CC_X_AND_Y = > ( X & & Y ) COND_OR == DOM_CC_NX_OR_Y = > ( ( ! X ) || Y ) COND_OR == DOM_CC_X_OR_Y = > ( X || Y ) In all cases OP will be either EQ or NE , but we do n't need to know which here . If we are unable to support a dominance comparison we return CC mode . This will then fail to match for the RTL expressions that generate this call .


<s>
static
void
handle_special_swappables
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
switch
(
insn_entry
[
i
]
.
special_handling
)
{
default
:
gcc_unreachable
(
)
;
case
SH_CONST_VECTOR
:
{
gcc_assert
(
GET_CODE
(
body
)
==
SET
)
;
swap_const_vector_halves
(
&
SET_SRC
(
body
)
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Swapping constant halves in insn %d\n"
,
i
)
;
break
;
}
case
SH_SUBREG
:
adjust_subreg_index
(
body
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Adjusting subreg in insn %d\n"
,
i
)
;
break
;
case
SH_NOSWAP_LD
:
permute_load
(
insn
)
;
break
;
case
SH_NOSWAP_ST
:
permute_store
(
insn
)
;
break
;
case
SH_EXTRACT
:
adjust_extract
(
insn
)
;
break
;
case
SH_SPLAT
:
adjust_splat
(
insn
)
;
break
;
case
SH_XXPERMDI
:
adjust_xxpermdi
(
insn
)
;
break
;
case
SH_CONCAT
:
adjust_concat
(
insn
)
;
break
;
case
SH_VPERM
:
adjust_vperm
(
insn
)
;
break
;
}
}
</s>

The insn described by INSN_ENTRY [ I ] can be swapped , but only with special handling . Take care of that here .

powerpcspe
"Swapping constant halves in insn %d\n"
"Adjusting subreg in insn %d\n"


<s> static bool ix86_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t regclass ) { if ( from == to ) return true ; if ( MAYBE_FLOAT_CLASS_P ( regclass ) ) return false ; if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P ( regclass ) ) { int mov_size = MAYBE_SSE_CLASS_P ( regclass ) && TARGET_SSE2 ? 2 : 4 ; if ( GET_MODE_SIZE ( from ) < mov_size ) return false ; } return true ; } </s>


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static tree sparc_gimplify_va_arg ( tree valist , tree type , tree * pre_p , tree * post_p ) { HOST_WIDE_INT size , rsize , align ; tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = 0 ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ( size + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ; align = 0 ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= 2 * ( unsigned ) BITS_PER_WORD ) align = 2 * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == 0 ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold ( build2 ( PLUS_EXPR , ptr_type_node , incr , ssize_int ( align - 1 ) ) ) ; incr = fold ( build2 ( BIT_AND_EXPR , ptr_type_node , incr , ssize_int ( - align ) ) ) ; } gimplify_expr ( & incr , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = incr ; if ( BYTES_BIG_ENDIAN && size < rsize ) addr = fold ( build2 ( PLUS_EXPR , ptr_type_node , incr , ssize_int ( rsize - size ) ) ) ; if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } else if ( align == 0 && TYPE_ALIGN ( type ) > BITS_PER_WORD ) { tree tmp = create_tmp_var ( type , "va_arg_tmp" ) ; tree dest_addr = build_fold_addr_expr ( tmp ) ; tree copy = build_function_call_expr ( implicit_built_in_decls [ BUILT_IN_MEMCPY ] , tree_cons ( NULL_TREE , dest_addr , tree_cons ( NULL_TREE , addr , tree_cons ( NULL_TREE , size_int ( rsize ) , NULL_TREE ) ) ) ) ; gimplify_and_add ( copy , pre_p ) ; addr = dest_addr ; } else addr = fold_convert ( ptrtype , addr ) ; incr = fold ( build2 ( PLUS_EXPR , ptr_type_node , incr , ssize_int ( rsize ) ) ) ; incr = build2 ( MODIFY_EXPR , ptr_type_node , valist , incr ) ; gimplify_and_add ( incr , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> SDValue VECustomDAG :: getConstant ( uint64_t Val , EVT VT , bool IsTarget , bool IsOpaque ) const { return DAG . getConstant ( Val , DL , VT , IsTarget , IsOpaque ) ; } </s>

Return the large constant at the given index .


<s> void arm_register_target_pragmas ( void ) { targetm . target_option . pragma_parse = arm_pragma_target_parse ; targetm . resolve_overloaded_builtin = arm_resolve_overloaded_builtin ; c_register_pragma ( "GCC" , "arm" , arm_pragma_arm ) ; REGISTER_SUBTARGET_PRAGMAS ( ) ; } </s>

Register target pragmas . We need to add the hook for parsing # pragma GCC option here rather than in arm.cc since it will pull in various preprocessor functions , and those are not present in languages like fortran without a preprocessor .


<s> EVT MipsTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Subtarget -> hasMips64 ( ) ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != NULL ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


runOnMachineFunction - Emit the function body .


<s>
void
rs6000_aix_asm_output_dwarf_table_ref
(
char
*
frame_table_label
)
{
fprintf
(
asm_out_file
,
"\t.ref %s\n"
,
(
*
targetm
.
strip_name_encoding
)
(
frame_table_label
)
)
;
}
</s>

Issue assembly directives that create a reference to the given DWARF FRAME_TABLE_LABEL from the current function section .


<s> static bool ix86_expand_vector_init_low_nonzero ( bool mmx_ok , enum machine_mode mode , rtx target , rtx var ) { enum machine_mode vsimode ; rtx x ; switch ( mode ) { case V2SFmode : case V2SImode : if ( ! mmx_ok && ! TARGET_SSE ) return false ; case V2DFmode : case V2DImode : var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; x = gen_rtx_VEC_CONCAT ( mode , var , CONST0_RTX ( GET_MODE_INNER ( mode ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return true ; case V4SFmode : case V4SImode : var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; x = gen_rtx_VEC_DUPLICATE ( mode , var ) ; x = gen_rtx_VEC_MERGE ( mode , x , CONST0_RTX ( mode ) , const1_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return true ; case V8HImode : case V16QImode : vsimode = V4SImode ; goto widen ; case V4HImode : case V8QImode : if ( ! mmx_ok ) return false ; vsimode = V2SImode ; goto widen ; widen : var = convert_modes ( SImode , GET_MODE_INNER ( mode ) , var , true ) ; x = gen_reg_rtx ( vsimode ) ; if ( ! ix86_expand_vector_init_low_nonzero ( mmx_ok , vsimode , x , var ) ) gcc_unreachable ( ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector whose low element is VAR , and other elements are zero . Return true if successful .


<s> static bool arm_slowmul_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = COSTS_N_INSNS ( 20 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 2 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; * total += rtx_cost ( XEXP ( x , 0 ) , mode , code , 0 , speed ) ; return true ; } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; ; } } </s>

RTX costs for cores with a slow MUL implementation . Thumb-2 is not supported on any `` slowmul '' cores , so it can be ignored .


<s>
void
aarch64_simd_lane_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
,
const_tree
exp
)
{
HOST_WIDE_INT
lane
;
gcc_assert
(
CONST_INT_P
(
operand
)
)
;
lane
=
INTVAL
(
operand
)
;
if
(
lane
<
low
||
lane
>=
high
)
{
if
(
exp
)
error
(
"%Klane %ld out of range %ld - %ld"
,
exp
,
lane
,
low
,
high
1
)
;
else
error
(
"lane %ld out of range %ld - %ld"
,
lane
,
low
,
high
1
)
;
}
}
</s>

Bounds-check lanes . Ensure OPERAND lies between LOW ( inclusive ) and HIGH ( exclusive ) .


<s> static void x86_64_elf_unique_section ( tree decl , int reloc ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && ix86_in_large_data_p ( decl ) ) { const char * prefix = NULL ; bool one_only = DECL_ONE_ONLY ( decl ) && ! HAVE_COMDAT_GROUP ; switch ( categorize_decl_for_section ( decl , reloc , flag_pic ) ) { case SECCAT_DATA : case SECCAT_DATA_REL : case SECCAT_DATA_REL_LOCAL : case SECCAT_DATA_REL_RO : case SECCAT_DATA_REL_RO_LOCAL : prefix = one_only ? ".gnu.linkonce.ld." : ".ldata." ; break ; case SECCAT_BSS : prefix = one_only ? ".gnu.linkonce.lb." : ".lbss." ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata." ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( prefix ) { const char * name ; size_t nlen , plen ; char * string ; plen = strlen ( prefix ) ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; nlen = strlen ( name ) ; string = alloca ( nlen + plen + 1 ) ; memcpy ( string , prefix , plen ) ; memcpy ( string + plen , name , nlen + 1 ) ; DECL_SECTION_NAME ( decl ) = build_string ( nlen + plen , string ) ; return ; } } default_unique_section ( decl , reloc ) ; } </s>

Build up a unique section name , expressed as a STRING_CST node , and assign it to DECL_SECTION_NAME ( decl ) . RELOC indicates whether the initial value of EXP requires link-time relocations .


<s> bool KudeyarTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; if ( N -> getOpcode ( ) == ISD :: LOAD ) { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; VT = LD -> getMemoryVT ( ) ; } else if ( N -> getOpcode ( ) == ISD :: STORE ) { StoreSDNode * ST = cast < StoreSDNode > ( N ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT != MVT :: i8 && VT != MVT :: i16 && VT != MVT :: i32 ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == MVT :: i32 && RHSC != 4 ) || ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> static void emit_store_conditional ( machine_mode mode , rtx res , rtx mem , rtx val ) { rtx ( * fn ) ( rtx , rtx , rtx ) = NULL ; switch ( mode ) { case E_QImode : fn = gen_store_conditionalqi ; break ; case E_HImode : fn = gen_store_conditionalhi ; break ; case E_SImode : fn = gen_store_conditionalsi ; break ; case E_DImode : fn = gen_store_conditionaldi ; break ; case E_TImode : fn = gen_store_conditionalti ; break ; default : gcc_unreachable ( ) ; } if ( PPC405_ERRATUM77 ) emit_insn ( gen_hwsync ( ) ) ; emit_insn ( fn ( res , mem , val ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a store-conditional instruction in MODE .


<s> static rtx mips_expand_builtin_movtf ( enum mips_builtin_type type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree exp ) { struct expand_operand ops [ 4 ] ; rtx cmp_result ; cmp_result = mips_expand_builtin_compare_1 ( icode , cond , exp , 2 ) ; create_output_operand ( & ops [ 0 ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; if ( type == MIPS_BUILTIN_MOVT ) { mips_prepare_builtin_arg ( & ops [ 2 ] , exp , 2 ) ; mips_prepare_builtin_arg ( & ops [ 1 ] , exp , 3 ) ; } else { mips_prepare_builtin_arg ( & ops [ 1 ] , exp , 2 ) ; mips_prepare_builtin_arg ( & ops [ 2 ] , exp , 3 ) ; } create_fixed_operand ( & ops [ 3 ] , cmp_result ) ; return mips_expand_builtin_insn ( CODE_FOR_mips_cond_move_tf_ps , 4 , ops , true ) ; } </s>

Expand a __builtin_mips_movt_ * _ps ( ) or __builtin_mips_movf_ * _ps ( ) function ( TYPE says which ) . ARGLIST is the list of arguments to the function , ICODE is the instruction that should be used to compare the first two arguments , and COND is the condition it should test . TARGET , if nonnull , suggests a good place to put the result .


<s> static void ix86_emit_leave ( rtx_insn * insn ) { struct machine_function * m = cfun -> machine ; if ( ! insn ) insn = emit_insn ( gen_leave ( word_mode ) ) ; ix86_add_queued_cfa_restore_notes ( insn ) ; gcc_assert ( m -> fs . fp_valid ) ; m -> fs . sp_valid = true ; m -> fs . sp_realigned = false ; m -> fs . sp_offset = m -> fs . fp_offset - UNITS_PER_WORD ; m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset ) ; } </s>

Emit code and notes for the LEAVE instruction .


<s> static void sparc64_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , GEN_INT ( trunc_int_for_mode ( 0x83414000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , GEN_INT ( trunc_int_for_mode ( 0xca586018 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , GEN_INT ( trunc_int_for_mode ( 0x81c14000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , GEN_INT ( trunc_int_for_mode ( 0xca586010 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 16 ) , cxt ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 24 ) , fnaddr ) ; emit_insn ( gen_flushdi ( validize_mem ( adjust_address ( m_tramp , DImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 && sparc_cpu != PROCESSOR_NIAGARA7 ) emit_insn ( gen_flushdi ( validize_mem ( adjust_address ( m_tramp , DImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

The 64 bit version is simpler because it makes more sense to load the values as `` immediate '' data out of the trampoline . It 's also easier since we can read the PC without clobbering a register .


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADD
:
if
(
Node
->
getSimpleValueType
(
0
)
.
isVector
(
)
&&
selectVecAddAsVecSubIfProfitable
(
Node
)
)
return
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
false
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
cast
<
MemSDNode
>
(
Node
)
->
getAddressSpace
(
)
)
||
(
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
)
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"== "
"\n"
1
ISD::ADD
0
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


Output return instrumentation for current function if needed .


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : case 'f' : case 'e' : return C_RegisterClass ; case 'I' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> rtx ix86_expand_adjust_ufix_to_sfix_si ( rtx val , rtx * xorp ) { REAL_VALUE_TYPE TWO31r ; rtx two31r , tmp [ 4 ] ; machine_mode mode = GET_MODE ( val ) ; machine_mode scalarmode = GET_MODE_INNER ( mode ) ; machine_mode intmode = GET_MODE_SIZE ( mode ) == 32 ? V8SImode : V4SImode ; rtx ( * cmp ) ( rtx , rtx , rtx , rtx ) ; int i ; for ( i = 0 ; i < 3 ; i ++ ) tmp [ i ] = gen_reg_rtx ( mode ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; two31r = const_double_from_real_value ( TWO31r , scalarmode ) ; two31r = ix86_build_const_vector ( mode , 1 , two31r ) ; two31r = force_reg ( mode , two31r ) ; switch ( mode ) { case E_V8SFmode : cmp = gen_avx_maskcmpv8sf3 ; break ; case E_V4SFmode : cmp = gen_sse_maskcmpv4sf3 ; break ; case E_V4DFmode : cmp = gen_avx_maskcmpv4df3 ; break ; case E_V2DFmode : cmp = gen_sse2_maskcmpv2df3 ; break ; default : gcc_unreachable ( ) ; } tmp [ 3 ] = gen_rtx_LE ( mode , two31r , val ) ; emit_insn ( cmp ( tmp [ 0 ] , two31r , val , tmp [ 3 ] ) ) ; tmp [ 1 ] = expand_simple_binop ( mode , AND , tmp [ 0 ] , two31r , tmp [ 1 ] , 0 , OPTAB_DIRECT ) ; if ( intmode == V4SImode || TARGET_AVX2 ) * xorp = expand_simple_binop ( intmode , ASHIFT , gen_lowpart ( intmode , tmp [ 0 ] ) , GEN_INT ( 31 ) , NULL_RTX , 0 , OPTAB_DIRECT ) ; else { rtx two31 = gen_int_mode ( HOST_WIDE_INT_1U << 31 , SImode ) ; two31 = ix86_build_const_vector ( intmode , 1 , two31 ) ; * xorp = expand_simple_binop ( intmode , AND , gen_lowpart ( intmode , tmp [ 0 ] ) , two31 , NULL_RTX , 0 , OPTAB_DIRECT ) ; } return expand_simple_binop ( mode , MINUS , val , tmp [ 1 ] , tmp [ 2 ] , 0 , OPTAB_DIRECT ) ; } </s>

Adjust a V * SFmode/V * DFmode value VAL so that * sfix_trunc * resp . fix_trunc * pattern can be used on it instead of fixuns_trunc * . This is done by doing just signed conversion if < 0x1p31 , and otherwise by subtracting 0x1p31 first and xoring in 0x80000000 from * XORP afterwards .


<s> static rtx aarch64_sve_emit_int_cmp ( rtx target , machine_mode pred_mode , rtx_code cmp , machine_mode data_mode , rtx op1 , rtx op2 ) { insn_code icode = code_for_aarch64_pred_cmp ( cmp , data_mode ) ; expand_operand ops [ 5 ] ; create_output_operand ( & ops [ 0 ] , target , pred_mode ) ; create_input_operand ( & ops [ 1 ] , CONSTM1_RTX ( pred_mode ) , pred_mode ) ; create_integer_operand ( & ops [ 2 ] , SVE_KNOWN_PTRUE ) ; create_input_operand ( & ops [ 3 ] , op1 , data_mode ) ; create_input_operand ( & ops [ 4 ] , op2 , data_mode ) ; expand_insn ( icode , 5 , ops ) ; return ops [ 0 ] . value ; } </s>

Emit a comparison CMP between OP0 and OP1 , both of which have mode DATA_MODE , and return the result in a predicate of mode PRED_MODE . Use TARGET as the target register if nonnull and convenient .


<s> bool arm_const_double_by_immediates ( rtx val ) { machine_mode mode = GET_MODE ( val ) ; rtx part ; if ( mode == VOIDmode ) mode = DImode ; part = gen_highpart_mode ( SImode , mode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( ! const_ok_for_arm ( INTVAL ( part ) ) ) return false ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( CONST_INT_P ( part ) ) ; if ( ! const_ok_for_arm ( INTVAL ( part ) ) ) return false ; return true ; } </s>

Return true if it is possible to inline both the high and low parts of a 64-bit constant into 32-bit data processing instructions .


<s> void MINA32MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint32_t > ( OS , Binary , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { if ( ! IsLP64 && convertArgMovsToPushes ( MF , MBB , I , Amount ) ) return ; New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const char * mips_output_jump ( rtx * operands , int target_opno , int size_opno , bool link_p ) { static char buffer [ 300 ] ; char * s = buffer ; bool reg_p = REG_P ( operands [ target_opno ] ) ; const char * and_link = link_p ? "al" : "" ; const char * reg = reg_p ? "r" : "" ; const char * compact = "" ; const char * nop = "%/" ; const char * short_delay = link_p ? "%!" : "" ; const char * insn_name = TARGET_CB_NEVER || reg_p ? "j" : "b" ; if ( ! final_sequence && ( TARGET_CB_MAYBE || ( ISA_HAS_JRC && ! link_p && reg_p ) ) ) { compact = "c" ; nop = "" ; } if ( TARGET_USE_GOT && ! TARGET_EXPLICIT_RELOCS ) sprintf ( s , "%%*%s%s\t%%%d%%/" , insn_name , and_link , target_opno ) ; else { if ( ! reg_p && TARGET_ABICALLS_PIC2 ) s += sprintf ( s , ".option\tpic0\n\t" ) ; if ( reg_p && mips_get_pic_call_symbol ( operands , size_opno ) ) s += sprintf ( s , "%%*.reloc\t1f,%s,%%%d\n1:\t" , TARGET_MICROMIPS ? "R_MICROMIPS_JALR" : "R_MIPS_JALR" , size_opno ) ; else s += sprintf ( s , "%%*" ) ; s += sprintf ( s , "%s%s%s%s%s\t%%%d%s" , insn_name , and_link , reg , compact , short_delay , target_opno , nop ) ; if ( ! reg_p && TARGET_ABICALLS_PIC2 ) s += sprintf ( s , "\n\t.option\tpic2" ) ; } return buffer ; } </s>

Return the asm template for a call . OPERANDS are the operands , TARGET_OPNO is the operand number of the target . SIZE_OPNO is the operand number of the argument size operand that can optionally hold the call attributes . If SIZE_OPNO is not -1 and the call is indirect , use the function symbol from the call attributes to attach a R_MIPS_JALR relocation to the call . LINK_P indicates whether the jump is a call and needs to set the link register . When generating GOT code without explicit relocation operators , all calls should use assembly macros . Otherwise , all indirect calls should use `` jr '' or `` jalr '' ; we will arrange to restore $ gp afterwards if necessary . Finally , we can only generate direct calls for -mabicalls by temporarily switching to non-PIC mode . For microMIPS jal ( r ) , we try to generate jal ( r ) s when a 16-bit instruction is in the delay slot of jal ( r ) . Where compact branches are available , we try to use them if the delay slot has a NOP ( or equivalently delay slots were not enabled for the instruction anyway ) .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static void ix86_init_large_pic_reg ( unsigned int tmp_regno ) { rtx_code_label * label ; rtx tmp_reg ; gcc_assert ( Pmode == DImode ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; LABEL_PRESERVE_P ( label ) = 1 ; tmp_reg = gen_rtx_REG ( Pmode , tmp_regno ) ; gcc_assert ( REGNO ( pic_offset_table_rtx ) != tmp_regno ) ; emit_insn ( gen_set_rip_rex64 ( pic_offset_table_rtx , label ) ) ; emit_insn ( gen_set_got_offset_rex64 ( tmp_reg , label ) ) ; emit_insn ( ix86_gen_add3 ( pic_offset_table_rtx , pic_offset_table_rtx , tmp_reg ) ) ; const char * name = LABEL_NAME ( label ) ; PUT_CODE ( label , NOTE ) ; NOTE_KIND ( label ) = NOTE_INSN_DELETED_LABEL ; NOTE_DELETED_LABEL_NAME ( label ) = name ; } </s>


<s> bool aarch64_sve_ldnf1_operand_p ( rtx op ) { struct aarch64_address_info addr ; return ( MEM_P ( op ) && aarch64_classify_address ( & addr , XEXP ( op , 0 ) , GET_MODE ( op ) , false ) && addr . type == ADDRESS_REG_IMM ) ; } </s>

Return true if OP is a valid MEM operand for an SVE LDNF1 instruction .


<s> void arm_register_target_pragmas ( void ) { targetm . target_option . pragma_parse = arm_pragma_target_parse ; REGISTER_SUBTARGET_PRAGMAS ( ) ; } </s>

Register target pragmas . We need to add the hook for parsing # pragma GCC option here rather than in arm.cc since it will pull in various preprocessor functions , and those are not present in languages like fortran without a preprocessor .


<s> static void sh_print_operand_address ( FILE * stream , machine_mode , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : fprintf ( stream , "@%s" , reg_names [ true_regnum ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "@(%d,%s)" , ( int ) INTVAL ( index ) , reg_names [ true_regnum ( base ) ] ) ; break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; if ( base_num == 0 && index_num != 0 ) std :: swap ( base_num , index_num ) ; fprintf ( stream , "@(%s,%s)" , reg_names [ index_num ] , reg_names [ base_num ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case PRE_DEC : fprintf ( stream , "@-%s" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( stream , "@%s+" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; default : x = mark_constant_pool_use ( x ) ; output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address in x to the stream .


<s> int MipsAsmParser :: tryParseRegister ( bool is64BitReg ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase , is64BitReg ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , is64BitReg ? Mips :: CPU64RegsRegClassID : Mips :: CPURegsRegClassID ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> bool MipsTargetObjectFile :: IsConstantInSmallSection ( const Constant * CN , const TargetMachine & TM ) const { return ( TM . getSubtarget < MipsSubtarget > ( ) . useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( CN -> getType ( ) ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> static void vector_init_faligndata ( rtx target , rtx elt ) { rtx t1 = gen_reg_rtx ( V4HImode ) ; int i ; elt = convert_modes ( SImode , HImode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; emit_insn ( gen_alignaddrsi_vis ( gen_reg_rtx ( SImode ) , force_reg ( SImode , GEN_INT ( 6 ) ) , const0_rtx ) ) ; for ( i = 0 ; i < 4 ; i ++ ) emit_insn ( gen_faligndatav4hi_vis ( target , t1 , target ) ) ; } </s>

Subroutine of sparc_expand_vector_init . Emit code to initialize all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn .


<s> void StackPU2AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { StackPU2MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst I ; MCInstLowering . lowerInstruction ( * MI , I ) ; EmitToStreamer ( * OutStreamer , I ) ; } </s>

Targets should implement this to emit instructions .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , bool IsLP64 , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( IsLP64 ) ; else Opc = isSub ? getSUBriOpcode ( IsLP64 , Offset ) : getADDriOpcode ( IsLP64 , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = nullptr ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> static HOST_WIDE_INT aarch64_estimated_poly_value ( poly_int64 val ) { enum aarch64_sve_vector_bits_enum width_source = aarch64_tune_params . sve_width ; if ( width_source == SVE_SCALABLE ) return default_estimated_poly_value ( val ) ; HOST_WIDE_INT over_128 = width_source - 128 ; return val . coeffs [ 0 ] + val . coeffs [ 1 ] * over_128 / 128 ; } </s>

Implement TARGET_ESTIMATED_POLY_VALUE . Look into the tuning structure for an estimate . KIND specifies the type of requested estimate : min , max or likely . For cores with a known SVE width all three estimates are the same . For generic SVE tuning we want to distinguish the maximum estimate from the minimum and likely ones . The likely estimate is the same as the minimum in that case to give a conservative behavior of auto-vectorizing with SVE when it is a win even for 128-bit SVE . When SVE width information is available VAL.coeffs [ 1 ] is multiplied by the number of VQ chunks over the initial Advanced SIMD 128 bits .


<s> static bool mep_reg_set_p ( rtx reg , rtx insn ) { if ( INSN_P ( insn ) ) { if ( FIND_REG_INC_NOTE ( insn , reg ) ) return true ; insn = PATTERN ( insn ) ; } if ( GET_CODE ( insn ) == SET && GET_CODE ( XEXP ( insn , 0 ) ) == REG && GET_CODE ( XEXP ( insn , 1 ) ) == REG && REGNO ( XEXP ( insn , 0 ) ) == REGNO ( XEXP ( insn , 1 ) ) ) return false ; return set_of ( reg , insn ) != NULL_RTX ; } </s>


<s> static void rs6000_elf_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( first && TREE_CODE ( decl ) == FUNCTION_DECL && ! TARGET_AIX && DEFAULT_ABI == ABI_AIX ) { rtx sym_ref = XEXP ( rtl , 0 ) ; size_t len = strlen ( XSTR ( sym_ref , 0 ) ) ; char * str = XALLOCAVEC ( char , len + 2 ) ; str [ 0 ] = '.' ; memcpy ( str + 1 , XSTR ( sym_ref , 0 ) , len + 1 ) ; XSTR ( sym_ref , 0 ) = ggc_alloc_string ( str , len + 1 ) ; } } </s>

For a SYMBOL_REF , set generic flags and then perform some target-specific processing . When the AIX ABI is requested on a non-AIX system , replace the function name with the real name ( with a leading . ) rather than the function descriptor name . This saves a lot of overriding code to read the prefixes .


<s>
const
char
*
ix86_output_ssemov
(
rtx_insn
*
insn
,
rtx
*
operands
)
{
machine_mode
mode
=
GET_MODE
(
operands
[
0
]
)
;
if
(
get_attr_type
(
insn
)
!=
TYPE_SSEMOV
||
mode
!=
GET_MODE
(
operands
[
1
]
)
)
gcc_unreachable
(
)
;
enum
attr_mode
insn_mode
=
get_attr_mode
(
insn
)
;
switch
(
insn_mode
)
{
case
MODE_XI
:
case
MODE_V8DF
:
case
MODE_V16SF
:
return
ix86_get_ssemov
(
operands
,
64
,
insn_mode
,
mode
)
;
case
MODE_OI
:
case
MODE_V4DF
:
case
MODE_V8SF
:
return
ix86_get_ssemov
(
operands
,
32
,
insn_mode
,
mode
)
;
case
MODE_TI
:
case
MODE_V2DF
:
case
MODE_V4SF
:
return
ix86_get_ssemov
(
operands
,
16
,
insn_mode
,
mode
)
;
case
MODE_DI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
{
if
(
HAVE_AS_IX86_INTERUNIT_MOVQ
)
return
"%vmovq\t{%1, %q0|%q0, %1}"
;
else
return
"%vmovd\t{%1, %q0|%q0, %1}"
;
}
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
{
if
(
HAVE_AS_IX86_INTERUNIT_MOVQ
)
return
"%vmovq\t{%q1, %0|%0, %q1}"
;
else
return
"%vmovd\t{%q1, %0|%0, %q1}"
;
}
else
return
"%vmovq\t{%1, %0|%0, %1}"
;
case
MODE_SI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
return
"%vmovd\t{%1, %k0|%k0, %1}"
;
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
return
"%vmovd\t{%k1, %0|%0, %k1}"
;
else
return
"%vmovd\t{%1, %0|%0, %1}"
;
case
MODE_HI
:
if
(
GENERAL_REG_P
(
operands
[
0
]
)
)
return
"vmovw\t{%1, %k0|%k0, %1}"
;
else
if
(
GENERAL_REG_P
(
operands
[
1
]
)
)
return
"vmovw\t{%k1, %0|%0, %k1}"
;
else
return
"vmovw\t{%1, %0|%0, %1}"
;
case
MODE_DF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovsd\t{%d1, %0|%0, %d1}"
;
else
return
"%vmovsd\t{%1, %0|%0, %1}"
;
case
MODE_SF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovss\t{%d1, %0|%0, %d1}"
;
else
return
"%vmovss\t{%1, %0|%0, %1}"
;
case
MODE_HF
:
if
(
REG_P
(
operands
[
0
]
)
&&
REG_P
(
operands
[
1
]
)
)
return
"vmovsh\t{%d1, %0|%0, %d1}"
;
else
return
"vmovsh\t{%1, %0|%0, %1}"
;
case
MODE_V1DF
:
gcc_assert
(
!
TARGET_AVX
)
;
return
"movlpd\t{%1, %0|%0, %1}"
;
case
MODE_V2SF
:
if
(
TARGET_AVX
&&
REG_P
(
operands
[
0
]
)
)
return
"vmovlps\t{%1, %d0|%d0, %1}"
;
else
return
"%vmovlps\t{%1, %0|%0, %1}"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return the template of the TYPE_SSEMOV instruction to move operands [ 1 ] into operands [ 0 ] .


<s> bool isUnconditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == AArch64 :: Bcc && Inst . getOperand ( 0 ) . getImm ( ) == A64CC :: AL ) return true ; return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> optForSize ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> rtx aarch64_atomic_ool_func ( machine_mode mode , rtx model_rtx , const atomic_ool_names * names ) { memmodel model = memmodel_base ( INTVAL ( model_rtx ) ) ; int mode_idx , model_idx ; switch ( mode ) { case E_QImode : mode_idx = 0 ; break ; case E_HImode : mode_idx = 1 ; break ; case E_SImode : mode_idx = 2 ; break ; case E_DImode : mode_idx = 3 ; break ; case E_TImode : mode_idx = 4 ; break ; default : gcc_unreachable ( ) ; } switch ( model ) { case MEMMODEL_RELAXED : model_idx = 0 ; break ; case MEMMODEL_CONSUME : case MEMMODEL_ACQUIRE : model_idx = 1 ; break ; case MEMMODEL_RELEASE : model_idx = 2 ; break ; case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : model_idx = 3 ; break ; default : gcc_unreachable ( ) ; } return init_one_libfunc_visibility ( names -> str [ mode_idx ] [ model_idx ] , VISIBILITY_HIDDEN ) ; } </s>

We store the names of the various atomic helpers in a 5x4 array . Return the libcall function given MODE , MODEL and NAMES .


<s> static inline machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_WIDER_MODE ( o ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * 2 ) ; gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return n ; } </s>

Get a vector mode of the same size as the original but with elements twice as wide . This is only guaranteed to apply to integral vectors .


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_SBFX
:
case
TargetOpcode
::
G_UBFX
:
return
legalizeBitfieldExtract
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ROTR
:
return
legalizeRotate
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTPOP
:
return
legalizeCTPOP
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpxchg128
(
MI
,
MRI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> void ix86_expand_vector_init ( bool mmx_ok , rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE || GET_CODE ( x ) == CONST_FIXED ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( n_var == 1 ) { if ( all_const_zero && ix86_expand_vector_init_one_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , 0 , one_var ) , one_var ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target , vals ) ; } </s>

Initialize vector TARGET via VALS . Suppress the use of MMX instructions unless MMX_OK is true .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> void AArch64PassConfig :: addPreSched2 ( ) { addPass ( createAArch64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; } addPass ( createAArch64SpeculationHardeningPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableFalkorHWPFFix ) addPass ( createFalkorHWPFFixPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { return F . arg_empty ( ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
while
(
!
vec_safe_is_empty
(
branch_islands
)
)
{
branch_island
*
bi
=
&
branch_islands
->
last
(
)
;
const
char
*
label
=
IDENTIFIER_POINTER
(
bi
->
label_name
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
bi
->
function_name
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
if
(
flag_pic
)
{
if
(
TARGET_LINK_STACK
)
{
char
name
[
32
]
;
get_ppc476_thunk_name
(
name
)
;
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbl "
)
;
strcat
(
tmp_buf
,
name
)
;
strcat
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
}
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\nlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
bi
->
line_number
)
;
branch_islands
->
pop
(
)
;
}
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = & ARM :: DPRRegClass ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = 2 ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = & ARM :: DPRRegClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = & ARM :: DPRRegClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = & ARM :: DPRRegClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static bool sh_handle_option ( size_t code , const char * arg ATTRIBUTE_UNUSED , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_m1 : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH1 ; return true ; case OPT_m2 : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2 ; return true ; case OPT_m2a : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2A ; return true ; case OPT_m2a_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2A_NOFPU ; return true ; case OPT_m2a_single : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2A_SINGLE ; return true ; case OPT_m2a_single_only : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2A_SINGLE_ONLY ; return true ; case OPT_m2e : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH2E ; return true ; case OPT_m3 : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH3 ; return true ; case OPT_m3e : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH3E ; return true ; case OPT_m4 : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4 ; return true ; case OPT_m4_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4_NOFPU ; return true ; case OPT_m4_single : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4_SINGLE ; return true ; case OPT_m4_single_only : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4_SINGLE_ONLY ; return true ; case OPT_m4a : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A ; return true ; case OPT_m4a_nofpu : case OPT_m4al : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_NOFPU ; return true ; case OPT_m4a_single : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_SINGLE ; return true ; case OPT_m4a_single_only : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH4A_SINGLE_ONLY ; return true ; case OPT_m5_32media : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_32MEDIA ; return true ; case OPT_m5_32media_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_32MEDIA_NOFPU ; return true ; case OPT_m5_64media : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_64MEDIA ; return true ; case OPT_m5_64media_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_64MEDIA_NOFPU ; return true ; case OPT_m5_compact : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_COMPACT ; return true ; case OPT_m5_compact_nofpu : target_flags = ( target_flags & ~ MASK_ARCH ) | SELECT_SH5_COMPACT_NOFPU ; return true ; default : return true ; } } </s>


<s> bool CSKYAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static bool is_costly_group ( rtx * group_insns , rtx next_insn ) { int i ; int issue_rate = rs6000_issue_rate ( ) ; for ( i = 0 ; i < issue_rate ; i ++ ) { sd_iterator_def sd_it ; dep_t dep ; rtx insn = group_insns [ i ] ; if ( ! insn ) continue ; FOR_EACH_DEP ( insn , SD_LIST_RES_FORW , sd_it , dep ) { rtx next = DEP_CON ( dep ) ; if ( next == next_insn && rs6000_is_costly_dependence ( dep , dep_cost ( dep ) , 0 ) ) return true ; } } return false ; } </s>

Return true if it is recommended to keep NEXT_INSN `` far '' ( in a separate dispatch group ) from the insns in GROUP_INSNS . Return false otherwise .


<s> const LoongArchRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> int mmix_local_regno ( int regno ) { return ( regno <= MMIX_LAST_STACK_REGISTER_REGNUM && ! call_used_or_fixed_reg_p ( regno ) ) ; } </s>

LOCAL_REGNO . All registers that are part of the register stack and that will be saved are local .


<s> bool ARM64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f128 ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> bool isReg ( ) const override { return Kind == k_Register && Reg . Kind == RegKind :: Scalar ; } </s>


<s> static unsigned int insn_is_store_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == MEM ) return 1 ; if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && GET_CODE ( SET_DEST ( set ) ) == MEM ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a store insn , including permuting stores that represent an stvxd2x instruction ; else return 0 .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return this -> TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool X86TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { for ( unsigned i = 0 , e = LegalFPImmediates . size ( ) ; i != e ; ++ i ) { if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s>
bool
PPCInstrInfo
::
getFMAPatterns
(
MachineInstr
&
Root
,
SmallVectorImpl
<
MachineCombinerPattern
>
&
Patterns
)
const
{
MachineBasicBlock
*
MBB
=
Root
.
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MBB
->
getParent
(
)
->
getRegInfo
(
)
;
auto
IsAllOpsVirtualReg
=
[
]
(
const
MachineInstr
&
Instr
)
{
for
(
const
auto
&
MO
:
Instr
.
explicit_operands
(
)
)
if
(
!
(
MO
.
isReg
(
)
&&
Register
::
isVirtualRegister
(
MO
.
getReg
(
)
)
)
)
return
false
;
return
true
;
}
;
auto
IsReassociable
=
[
&
]
(
const
MachineInstr
&
Instr
,
int16_t
&
AddOpIdx
,
bool
IsLeaf
,
bool
IsAdd
)
{
int16_t
Idx
=
1
;
if
(
!
IsAdd
)
{
Idx
=
getFMAOpIdxInfo
(
Instr
.
getOpcode
(
)
)
;
if
(
Idx
<
0
)
return
false
;
}
else
if
(
Instr
.
getOpcode
(
)
!=
FMAOpIdxInfo
[
getFMAOpIdxInfo
(
Root
.
getOpcode
(
)
)
]
[
InfoArrayIdxFAddInst
]
)
return
false
;
if
(
!
(
Instr
.
getFlag
(
MachineInstr
::
MIFlag
::
FmReassoc
)
&&
Instr
.
getFlag
(
MachineInstr
::
MIFlag
::
FmNsz
)
)
)
return
false
;
if
(
!
IsAllOpsVirtualReg
(
Instr
)
)
return
false
;
if
(
IsAdd
&&
IsLeaf
)
return
true
;
AddOpIdx
=
FMAOpIdxInfo
[
Idx
]
[
InfoArrayIdxAddOpIdx
]
;
const
MachineOperand
&
OpAdd
=
Instr
.
getOperand
(
AddOpIdx
)
;
MachineInstr
*
MIAdd
=
MRI
.
getUniqueVRegDef
(
OpAdd
.
getReg
(
)
)
;
if
(
!
MIAdd
||
MIAdd
->
getParent
(
)
!=
MBB
)
return
false
;
return
IsLeaf
true
:
MRI
.
hasOneNonDBGUse
(
OpAdd
.
getReg
(
)
)
;
}
;
int16_t
AddOpIdx
=
1
;
if
(
!
IsReassociable
(
Root
,
AddOpIdx
,
false
,
false
)
)
return
false
;
assert
(
(
AddOpIdx
>=
0
)
&&
"add operand index not right!"
)
;
Register
RegB
=
Root
.
getOperand
(
AddOpIdx
)
.
getReg
(
)
;
MachineInstr
*
Prev
=
MRI
.
getUniqueVRegDef
(
RegB
)
;
AddOpIdx
=
1
;
if
(
!
IsReassociable
(
*
Prev
,
AddOpIdx
,
false
,
false
)
)
return
false
;
assert
(
(
AddOpIdx
>=
0
)
&&
"add operand index not right!"
)
;
Register
RegA
=
Prev
->
getOperand
(
AddOpIdx
)
.
getReg
(
)
;
MachineInstr
*
Leaf
=
MRI
.
getUniqueVRegDef
(
RegA
)
;
AddOpIdx
=
1
;
if
(
IsReassociable
(
*
Leaf
,
AddOpIdx
,
true
,
false
)
)
{
Patterns
.
push_back
(
MachineCombinerPattern
::
REASSOC_XMM_AMM_BMM
)
;
return
true
;
}
if
(
IsReassociable
(
*
Leaf
,
AddOpIdx
,
true
,
true
)
)
{
Patterns
.
push_back
(
MachineCombinerPattern
::
REASSOC_XY_AMM_BMM
)
;
return
true
;
}
return
false
;
}
</s>

Return true when there is potentially a faster code sequence for a fma chain ending in Root .


<s>
const
char
*
rs6000_insn_for_shift_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
3
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
mode
==
DImode
&&
ne
==
0
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
64
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rld%I2cl. %0,%1,%2,%3"
;
return
"rld%I2cl %0,%1,%2,%3"
;
}
if
(
mode
==
DImode
&&
nb
==
63
)
{
operands
[
3
]
=
GEN_INT
(
63
ne
)
;
if
(
dot
)
return
"rld%I2cr. %0,%1,%2,%3"
;
return
"rld%I2cr %0,%1,%2,%3"
;
}
if
(
mode
==
DImode
&&
GET_CODE
(
operands
[
4
]
)
!=
LSHIFTRT
&&
CONST_INT_P
(
operands
[
2
]
)
&&
ne
==
INTVAL
(
operands
[
2
]
)
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rld%I2c. %0,%1,%2,%3"
;
return
"rld%I2c %0,%1,%2,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
32
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlw%I2nm. %0,%1,%h2,%3,%4"
;
return
"rlw%I2nm %0,%1,%h2,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for a shift with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


<s> int pa_fpstore_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { machine_mode store_mode ; machine_mode other_mode ; rtx set ; if ( recog_memoized ( in_insn ) < 0 || ( get_attr_type ( in_insn ) != TYPE_FPSTORE && get_attr_type ( in_insn ) != TYPE_FPSTORE_LOAD ) || recog_memoized ( out_insn ) < 0 ) return 0 ; store_mode = GET_MODE ( SET_SRC ( PATTERN ( in_insn ) ) ) ; set = single_set ( out_insn ) ; if ( ! set ) return 0 ; other_mode = GET_MODE ( SET_SRC ( set ) ) ; return ( GET_MODE_SIZE ( store_mode ) == GET_MODE_SIZE ( other_mode ) ) ; } </s>

Return nonzero if there is a bypass for the output of OUT_INSN and the fp store IN_INSN .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? STI . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> static void fold_compare_helper ( gimple_stmt_iterator * gsi , tree_code code , gimple * stmt ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree cmp = fold_build_vec_cmp ( code , TREE_TYPE ( lhs ) , arg0 , arg1 ) ; gimple * g = gimple_build_assign ( lhs , cmp ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the in-between steps for the vector compare built-ins .


<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
StackOffset
::
getFixed
(
Amount
)
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
StackOffset
::
getFixed
(
(
int64_t
)
CalleePopAmount
)
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> bool ARMTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! I -> getType ( ) -> isVectorTy ( ) ) return false ; if ( Subtarget -> hasNEON ( ) ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsSinker = [ ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : return true ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == 1 ; default : return false ; } } ; int Op = 0 ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = 1 ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_Zero ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( Op ) ) ; return true ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void core2i7_first_cycle_multipass_init ( void * _data ) { ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; data -> ifetch_block_len = 0 ; data -> ifetch_block_n_insns = 0 ; data -> ready_try_change = NULL ; data -> ready_try_change_size = 0 ; } </s>


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


<s> static int sparc_vis_mul8x16 ( int e8 , int e16 ) { return ( e8 * e16 + 128 ) / 256 ; } </s>

Return the upper 16 bits of the 8x16 multiplication .


<s> virtual const X86RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static rtx nds32_expand_scw_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ 1 ] . mode ) ; target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , 1 , op0 ) ; op1 = nds32_legitimize_argument ( icode , 2 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , addr_helper , target ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( 0 ) ) ; emit_move_insn ( target , op1 ) ; emit_insn ( pat ) ; return target ; } </s>


"\nrs6000_secondary_reload_class, return %s, rclass = %s, "

Debug version of rs6000_secondary_reload_class .


<s> const LegalizerInfo * MipsSubtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> static void pa_output_function_epilogue ( FILE * file ) { rtx_insn * insn = get_last_insn ( ) ; bool extra_nop ; if ( NOTE_P ( insn ) ) insn = prev_real_insn ( insn ) ; if ( insn && NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = as_a < rtx_sequence * > ( PATTERN ( insn ) ) -> insn ( 0 ) ; if ( insn && CALL_P ( insn ) ) { fputs ( "\tnop\n" , file ) ; extra_nop = true ; } else extra_nop = false ; fputs ( "\t.EXIT\n\t.PROCEND\n" , file ) ; if ( TARGET_SOM && TARGET_GAS ) { in_section = NULL ; cfun -> machine -> in_nsubspa = 2 ; } if ( cfun -> is_thunk ) return ; if ( INSN_ADDRESSES_SET_P ( ) ) { last_address = extra_nop ? 4 : 0 ; insn = get_last_nonnote_insn ( ) ; if ( insn ) { last_address += INSN_ADDRESSES ( INSN_UID ( insn ) ) ; if ( INSN_P ( insn ) ) last_address += insn_default_length ( insn ) ; } last_address = ( ( last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1 ) & ~ ( FUNCTION_BOUNDARY / BITS_PER_UNIT - 1 ) ) ; } else last_address = UINT_MAX ; update_total_code_bytes ( last_address ) ; } </s>

This function generates the assembly code for function exit . Args are as for output_function_prologue ( ) . The function epilogue should not depend on the current stack pointer ! It should use the frame pointer only . This is mandatory because of alloca ; we also take advantage of it to omit stack adjustments before returning .