<s> bool function_checker :: require_immediate_enum ( unsigned int rel_argno , tree type ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; for ( tree entry = TYPE_VALUES ( type ) ; entry ; entry = TREE_CHAIN ( entry ) ) { tree value = TREE_VALUE ( entry ) ; if ( TREE_CODE ( value ) == CONST_DECL ) value = DECL_INITIAL ( value ) ; if ( wi :: to_widest ( value ) == actual ) return true ; } report_not_enum ( location , fndecl , argno , actual , type ) ; return false ; } </s>

Check that argument REL_ARGNO is an integer constant expression that has a valid value for enumeration type TYPE . REL_ARGNO counts from the end of the predication arguments .


<s> static unsigned estimateStackSize ( MachineFunction & MF ) { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; int Offset = 0 ; for ( int i = FFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - FFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = FFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( FFI -> isDeadObjectIndex ( i ) ) continue ; Offset += FFI -> getObjectSize ( i ) ; unsigned Align = FFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; } return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s> bool aarch64_fusion_enabled_p ( enum aarch64_fusion_pairs op ) { return ( aarch64_tune_params . fusible_ops & op ) != 0 ; } </s>

Return true iff the instruction fusion described by OP is enabled .


<s> void func_fma_steering :: analyze ( ) { int i , n_blocks , * bb_dfs_preorder ; basic_block bb ; rtx_insn * insn ; bb_dfs_preorder = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n_blocks = pre_and_rev_post_order_compute ( bb_dfs_preorder , NULL , false ) ; for ( i = 0 ; i < n_blocks ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , bb_dfs_preorder [ i ] ) ; FOR_BB_INSNS ( bb , insn ) { operand_rr_info * dest_op_info ; struct du_chain * chain = NULL ; unsigned dest_regno ; fma_forest * forest = NULL ; du_head_p head = NULL ; int i ; if ( ! is_fmul_fmac_insn ( insn , true ) ) continue ; dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; dest_regno = REGNO ( SET_DEST ( PATTERN ( insn ) ) ) ; for ( i = 0 ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; forest = NULL ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * * fma_slot ; if ( ! is_fmul_fmac_insn ( chain -> insn , true ) ) continue ; if ( chain -> loc != & SET_DEST ( PATTERN ( chain -> insn ) ) ) continue ; if ( chain -> insn == insn ) break ; fma_slot = this -> m_insn_fma_head_map -> get ( chain -> insn ) ; if ( fma_slot && ( * fma_slot ) -> get_children ( ) ) forest = ( * fma_slot ) -> get_forest ( ) ; } if ( chain ) break ; } gcc_assert ( i < dest_op_info -> n_chains ) ; this -> analyze_fma_fmul_insn ( forest , chain , head ) ; } } free ( bb_dfs_preorder ) ; if ( dump_file ) this -> dfs ( dump_forest_info , dump_tree_root_info , dump_tree_node_info , false ) ; } </s>

Count how many times each regno is referenced as base address for a memory access .


<s> static unsigned int aarch64_adjust_stmt_cost ( vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , unsigned int stmt_cost ) { if ( vectype ) { const simd_vec_cost * simd_costs = aarch64_simd_vec_costs ( vectype ) ; switch ( aarch64_ld234_st234_vectors ( kind , stmt_info ) ) { case 2 : stmt_cost += simd_costs -> ld2_st2_permute_cost ; break ; case 3 : stmt_cost += simd_costs -> ld3_st3_permute_cost ; break ; case 4 : stmt_cost += simd_costs -> ld4_st4_permute_cost ; break ; } if ( kind == vector_stmt || kind == vec_to_scalar ) if ( tree cmp_type = aarch64_embedded_comparison_type ( stmt_info ) ) { if ( FLOAT_TYPE_P ( cmp_type ) ) stmt_cost += simd_costs -> fp_stmt_cost ; else stmt_cost += simd_costs -> int_stmt_cost ; } } if ( kind == scalar_stmt ) if ( tree cmp_type = aarch64_embedded_comparison_type ( stmt_info ) ) { if ( FLOAT_TYPE_P ( cmp_type ) ) stmt_cost += aarch64_tune_params . vec_costs -> scalar_fp_stmt_cost ; else stmt_cost += aarch64_tune_params . vec_costs -> scalar_int_stmt_cost ; } return stmt_cost ; } </s>

STMT_COST is the cost calculated for STMT_INFO , which has cost kind KIND and which when vectorized would operate on vector type VECTYPE . Add the cost of any embedded operations .


<s> static reg_class_t mips_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( mips_dangerous_for_la25_p ( x ) && reg_class_subset_p ( LEA_REGS , rclass ) ) return LEA_REGS ; if ( reg_class_subset_p ( FP_REGS , rclass ) && mips_mode_ok_for_mov_fmt_p ( GET_MODE ( x ) ) ) return FP_REGS ; if ( reg_class_subset_p ( GR_REGS , rclass ) ) rclass = GR_REGS ; if ( TARGET_MIPS16 && reg_class_subset_p ( M16_REGS , rclass ) ) rclass = M16_REGS ; return rclass ; } </s>


<s> const char * loongarch_output_division ( const char * division , rtx * operands ) { const char * s ; s = division ; if ( loongarch_check_zero_div_p ( ) ) { output_asm_insn ( s , operands ) ; s = "bne\t%2,%.,1f\n\tbreak\t7\n1:" ; } return s ; } </s>

Return the assembly code for DIV . { W/D } instruction DIVISION , which has the operands given by OPERANDS . Add in a divide-by-zero check if needed .


"Got non-GPR register in .cfi directive!"

tryParseRegister - parse one register if possible


<s> bool enableInterleavedAccessVectorization ( ) { return ! ST -> hasSVE ( ) ; } </s>

Enable matching of interleaved access groups .


<s> static void mips_load_call_address ( rtx dest , rtx addr , int sibcall_p ) { if ( TARGET_EXPLICIT_RELOCS && ! ( sibcall_p && TARGET_NEWABI ) && global_got_operand ( addr , VOIDmode ) ) { rtx high , lo_sum_symbol ; high = mips_unspec_offset_high ( dest , pic_offset_table_rtx , addr , SYMBOL_GOTOFF_CALL ) ; lo_sum_symbol = mips_unspec_address ( addr , SYMBOL_GOTOFF_CALL ) ; if ( Pmode == SImode ) emit_insn ( gen_load_callsi ( dest , high , lo_sum_symbol ) ) ; else emit_insn ( gen_load_calldi ( dest , high , lo_sum_symbol ) ) ; } else emit_move_insn ( dest , addr ) ; } </s>

Load function address ADDR into register DEST . SIBCALL_P is true if the address is needed for a sibling call .


<s>
MachineBasicBlock
*
MipsTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
*
TII
=
getTargetMachine
(
)
.
getInstrInfo
(
)
;
bool
isFPCmp
=
false
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
case
Mips
::
Select_FCC
:
case
Mips
::
Select_FCC_S32
:
case
Mips
::
Select_FCC_D32
:
isFPCmp
=
true
;
case
Mips
::
Select_CC
:
case
Mips
::
Select_CC_S32
:
case
Mips
::
Select_CC_D32
:
{
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
if
(
isFPCmp
)
{
Mips
::
CondCode
CC
=
(
Mips
::
CondCode
)
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
Opc
=
FPBranchCodeToOpc
(
GetFPBranchCodeFromCond
(
CC
)
)
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
Opc
)
)
.
addMBB
(
sinkMBB
)
;
}
else
BuildMI
(
BB
,
dl
,
TII
->
get
(
Mips
::
BNE
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addReg
(
Mips
::
ZERO
)
.
addMBB
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
->
get
(
Mips
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static unsigned getHashValue ( const SlotWithTag & V ) { return hash_combine ( DenseMapInfo < int > :: getHashValue ( V . FI ) , DenseMapInfo < int > :: getHashValue ( V . Tag ) ) ; } </s>

Using name and line to get hash value . It should already be mostly unique .


<s> bool ix86_expand_pextr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; unsigned int size = INTVAL ( operands [ 2 ] ) ; unsigned int pos = INTVAL ( operands [ 3 ] ) ; if ( SUBREG_P ( dst ) ) { if ( SUBREG_BYTE ( dst ) > 0 ) return false ; dst = SUBREG_REG ( dst ) ; } if ( SUBREG_P ( src ) ) { pos += SUBREG_BYTE ( src ) * BITS_PER_UNIT ; src = SUBREG_REG ( src ) ; } switch ( GET_MODE ( src ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V1TImode : case TImode : { machine_mode srcmode , dstmode ; rtx d , pat ; dstmode = mode_for_size ( size , MODE_INT , 0 ) ; switch ( dstmode ) { case QImode : if ( ! TARGET_SSE4_1 ) return false ; srcmode = V16QImode ; break ; case HImode : if ( ! TARGET_SSE2 ) return false ; srcmode = V8HImode ; break ; case SImode : if ( ! TARGET_SSE4_1 ) return false ; srcmode = V4SImode ; break ; case DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; srcmode = V2DImode ; break ; default : return false ; } if ( pos & ( size - 1 ) ) return false ; if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx ( dstmode ) ; pat = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , GEN_INT ( pos / size ) ) ) ; pat = gen_rtx_VEC_SELECT ( dstmode , gen_lowpart ( srcmode , src ) , pat ) ; if ( dstmode == QImode || dstmode == HImode ) { pat = gen_rtx_ZERO_EXTEND ( SImode , pat ) ; d = gen_lowpart ( SImode , d ) ; } emit_insn ( gen_rtx_SET ( d , pat ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an extract from a vector register through pextr insn . Return true if successful .


<s> static bool valid_bL_string_p ( const char * * core , const char * bL_string ) { return strstr ( bL_string , core [ 0 ] ) != NULL && strstr ( bL_string , core [ 1 ] ) != NULL ; } </s>

Check wether the string CORE contains the same CPU part numbers as BL_STRING . For example CORE= '' { 0xd03 , 0xd07 } '' and BL_STRING= '' 0xd07.0xd03 '' should return true .


<s> void ARMHazardRecognizer :: Reset ( ) { LastMI = 0 ; FpMLxStalls = 0 ; ITBlockSize = 0 ; ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> const MCExpr * X86LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_DTPOFF , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s>
bool
MipsAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"0($"
<<
MipsInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

Mips
Mips
0
"unexpected inline asm memory operand"
"0($"
Mips
")"


<s> static void emit_v9_brxx_insn ( enum rtx_code code , rtx op0 , rtx label ) { emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; } </s>

Emit a conditional jump insn for the v9 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the v9 brxx insns .


"Unable to create a unique discriminator "

"for instruction with memory operand in: "

". This is likely due to a large macro expansion. \n"

"New discriminator shouldn't be present in set"

runOnMachineFunction - Emit the function body .


<s> bool function_expander :: try_negating_argument ( unsigned int argno , machine_mode mode ) { rtx x = args [ argno ] ; if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) ) mode = GET_MODE_INNER ( mode ) ; x = simplify_unary_operation ( NEG , mode , x , mode ) ; if ( ! x ) return false ; args [ argno ] = x ; return true ; } </s>

Return true if the negation of argument ARGNO can be folded away , replacing it with the negated value if so . MODE is the associated vector mode , but the argument could be a single element . The main case this handles is constant arguments .


<s> bool CSKYTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > CSKYLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , CSKYLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn ( CallConv , IsVarArg ) ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI -> CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI -> CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = FI -> getPICBasePointerSaveIndex ( ) ; PBPSI = MFI -> CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI -> CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static bool ix86_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case asin_optab : case acos_optab : case log1p_optab : case exp_optab : case exp10_optab : case exp2_optab : case expm1_optab : case ldexp_optab : case scalb_optab : case round_optab : return opt_type == OPTIMIZE_FOR_SPEED ; case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_SSE4_1 && mode1 != HFmode ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( ( ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && TARGET_SSE4_1 ) || mode1 == HFmode ) && ! flag_trapping_math ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( mode1 ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getEnvironment ( ) != Triple :: GNUILP32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; if ( ! getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) setCFIFixup ( true ) ; } </s>


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void VEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( isLeafProc ( MF ) && ! hasBP ( MF ) ) { VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; FuncInfo -> setLeafProc ( true ) ; } } </s>


<s> static bool mips_in_small_data_p ( const_tree decl ) { unsigned HOST_WIDE_INT size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TARGET_ABICALLS || TARGET_VXWORKS_RTP ) return false ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_SECTION_NAME ( decl ) != 0 ) { const char * name ; name = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( name , ".sdata" ) != 0 && strcmp ( name , ".sbss" ) != 0 ) return false ; if ( mips_lo_relocs [ SYMBOL_GP_RELATIVE ] || ! DECL_EXTERNAL ( decl ) ) return true ; } else if ( TARGET_EMBEDDED_DATA ) { if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) return false ; } if ( ! TARGET_LOCAL_SDATA && ! TREE_PUBLIC ( decl ) ) return false ; if ( ! TARGET_EXTERN_SDATA && DECL_P ( decl ) ) { if ( DECL_EXTERNAL ( decl ) ) return false ; if ( DECL_COMMON ( decl ) && DECL_INITIAL ( decl ) == NULL ) return false ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return size > 0 && size <= mips_small_data_threshold ; } </s>

Implement TARGET_IN_SMALL_DATA_P . Return true if it would be safe to access DECL using % gp_rel ( ... ) ( $ gp ) .


<s> bool FISCRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> static enum internal_test map_test_to_internal_test ( enum rtx_code test_code ) { enum internal_test test = ITEST_MAX ; switch ( test_code ) { case EQ : test = ITEST_EQ ; break ; case NE : test = ITEST_NE ; break ; case GT : test = ITEST_GT ; break ; case GE : test = ITEST_GE ; break ; case LT : test = ITEST_LT ; break ; case LE : test = ITEST_LE ; break ; case GTU : test = ITEST_GTU ; break ; case GEU : test = ITEST_GEU ; break ; case LTU : test = ITEST_LTU ; break ; case LEU : test = ITEST_LEU ; break ; default : break ; } return test ; } </s>

Make normal rtx_code into something we can index from an array


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool ix86_function_ok_for_sibcall ( tree decl , tree exp ) { tree type , decl_or_type ; rtx a , b ; bool bind_global = decl && ! targetm . binds_local_p ( decl ) ; if ( ! TARGET_MACHO && ! TARGET_64BIT && flag_pic && flag_plt && bind_global ) return false ; if ( ix86_minimum_incoming_stack_boundary ( true ) < PREFERRED_STACK_BOUNDARY ) return false ; if ( decl ) { decl_or_type = decl ; type = TREE_TYPE ( decl ) ; } else { type = CALL_EXPR_FN ( exp ) ; type = TREE_TYPE ( type ) ; type = TREE_TYPE ( type ) ; decl_or_type = type ; } a = ix86_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT ) { if ( cfun -> machine -> call_abi == MS_ABI && ix86_function_type_abi ( type ) == SYSV_ABI ) return false ; } else { if ( ! decl || ( bind_global && flag_pic && ! flag_plt ) || ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P ( decl ) ) ) { if ( ix86_function_regparm ( type , NULL ) >= 3 && ! cfun -> machine -> arg_reg_available ) return false ; } } return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const X86RegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>


<s> bool x86_maybe_negate_const_int ( rtx * loc , machine_mode mode ) { HOST_WIDE_INT val ; if ( ! CONST_INT_P ( * loc ) ) return false ; switch ( mode ) { case E_DImode : gcc_assert ( x86_64_immediate_operand ( * loc , mode ) ) ; mode = SImode ; break ; case E_SImode : case E_HImode : case E_QImode : break ; default : gcc_unreachable ( ) ; } if ( mode_signbit_p ( mode , * loc ) ) return false ; val = INTVAL ( * loc ) ; if ( ( val < 0 && val != - 128 ) || val == 128 ) { * loc = GEN_INT ( - val ) ; return true ; } return false ; } </s>

If profitable , negate ( without causing overflow ) integer constant of mode MODE at location LOC . Return true in this case .


<s> bool and_operands_ok ( machine_mode mode , rtx op1 , rtx op2 ) { return ( memory_operand ( op1 , mode ) ? and_load_operand ( op2 , mode ) : and_reg_operand ( op2 , mode ) ) ; } </s>

Return true iff OP1 and OP2 are valid operands together for the * and < MODE > 3 and * and < MODE > 3_mips16 patterns . For the cases to consider , see the table in the comment before the pattern .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
return
true
;
}
{
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
}
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s> void xstormy16_print_operand_address ( FILE * file , rtx address ) { HOST_WIDE_INT offset ; int pre_dec , post_inc ; if ( GET_CODE ( address ) == CONST_INT ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( address ) & 0xFFFF ) ; return ; } if ( CONSTANT_P ( address ) || GET_CODE ( address ) == CODE_LABEL ) { output_addr_const ( file , address ) ; return ; } if ( GET_CODE ( address ) == PLUS ) { gcc_assert ( GET_CODE ( XEXP ( address , 1 ) ) == CONST_INT ) ; offset = INTVAL ( XEXP ( address , 1 ) ) ; address = XEXP ( address , 0 ) ; } else offset = 0 ; pre_dec = ( GET_CODE ( address ) == PRE_DEC ) ; post_inc = ( GET_CODE ( address ) == POST_INC ) ; if ( pre_dec || post_inc ) address = XEXP ( address , 0 ) ; gcc_assert ( GET_CODE ( address ) == REG ) ; fputc ( '(' , file ) ; if ( pre_dec ) fputs ( "--" , file ) ; fputs ( reg_names [ REGNO ( address ) ] , file ) ; if ( post_inc ) fputs ( "++" , file ) ; if ( offset != 0 ) fprintf ( file , "," HOST_WIDE_INT_PRINT_DEC , offset ) ; fputc ( ')' , file ) ; } </s>

Print a memory address as an operand to reference that memory location .


Expand movmem , as if from a __builtin_memcpy . Return true if we succeed , otherwise return false .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isAIXABI ( ) ) return LowerFormalArguments_AIX ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; if ( Subtarget . is64BitELFABI ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; if ( Subtarget . is32BitELFABI ( ) ) return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> virtual const OpenRISCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
bool
ARM64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** ARM64AdvSIMDScalar *****\n"
)
;
const
TargetMachine
&
TM
=
mf
.
getTarget
(
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARM64InstrInfo
*
>
(
TM
.
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool XNCMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>


<s> static std :: unique_ptr < ARMOperand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < ARMOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void rs6000_split_compare_and_swap ( rtx retval , rtx mem , rtx oldval , rtx newval , rtx scratch ) { enum machine_mode mode = GET_MODE ( mem ) ; rtx label1 , label2 , x , cond = gen_rtx_REG ( CCmode , CR0_REGNO ) ; emit_insn ( gen_memory_barrier ( ) ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; x = gen_rtx_COMPARE ( CCmode , retval , oldval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label2 ) ; emit_move_insn ( scratch , newval ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label1 ) ; emit_insn ( gen_isync ( ) ) ; emit_label ( XEXP ( label2 , 0 ) ) ; } </s>

Expand an atomic compare and swap operation . MEM is the memory on which to operate . OLDVAL is the old value to be compared . NEWVAL is the new value to be stored . SCRATCH is a scratch GPR .


"  r%d def in insn %d isn't convertible\n"

"  r%d use in insn %d isn't convertible\n"

Check REF 's chain to add new insns into a queue and find registers requiring conversion . Return true if OK , false if the analysis was aborted .


<s> int crx_initial_elimination_offset ( int from , int to ) { crx_compute_save_regs ( ) ; crx_compute_frame ( ) ; if ( ( from ) == FRAME_POINTER_REGNUM && ( to ) == STACK_POINTER_REGNUM ) return ( ACCUMULATE_OUTGOING_ARGS ? current_function_outgoing_args_size : 0 ) ; else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == FRAME_POINTER_REGNUM ) return ( sum_regs + local_vars_size ) ; else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == STACK_POINTER_REGNUM ) return ( sum_regs + local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? current_function_outgoing_args_size : 0 ) ) ; else abort ( ) ; } </s>

Implements the macro INITIAL_ELIMINATION_OFFSET , return the OFFSET .


<s> bool AArch64TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasFnAttribute ( Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> void rs6000_activate_target_options ( tree new_tree ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; rs6000_previous_fndecl = NULL_TREE ; } </s>

Restore target 's globals from NEW_TREE and invalidate the rs6000_previous_fndecl cache .


<s> static rtx aarch64_gen_compare_reg_maybe_ze ( RTX_CODE code , rtx x , rtx y , machine_mode y_mode ) { if ( y_mode == E_QImode || y_mode == E_HImode ) { if ( CONST_INT_P ( y ) ) { y = GEN_INT ( INTVAL ( y ) & GET_MODE_MASK ( y_mode ) ) ; y_mode = SImode ; } else { rtx t , cc_reg ; machine_mode cc_mode ; t = gen_rtx_ZERO_EXTEND ( SImode , y ) ; t = gen_rtx_COMPARE ( CC_SWPmode , t , x ) ; cc_mode = CC_SWPmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , t ) ; return cc_reg ; } } if ( ! aarch64_plus_operand ( y , y_mode ) ) y = force_reg ( y_mode , y ) ; return aarch64_gen_compare_reg ( code , x , y ) ; } </s>

Similarly , but maybe zero-extend Y if Y_MODE < SImode .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ 0 ] << 24 ) | ( Bytes [ 1 ] << 16 ) | ( Bytes [ 2 ] << 8 ) | ( Bytes [ 3 ] << 0 ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; MI . clear ( ) ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != 16 || Align <= 2 || Ty == LLT :: vector ( 2 , 64 ) ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static HOST_WIDE_INT rs6000_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ( STRICT_ALIGNMENT || ! optimize_size ) ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


"Can only insert epilog into returning blocks"

"Expected to see callee-save register restore code"


<s> bool isCall ( const MCInst & MI , bool * IsIndirectCall ) { unsigned Opcode = MI . getOpcode ( ) ; * IsIndirectCall = false ; switch ( Opcode ) { default : return false ; case Mips :: JAL : case Mips :: BAL : case Mips :: BAL_BR : case Mips :: BLTZAL : case Mips :: BGEZAL : return true ; case Mips :: JALR : assert ( MI . getOperand ( 0 ) . isReg ( ) ) ; if ( MI . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO ) return false ; * IsIndirectCall = true ; return true ; } } </s>

Mips Mips::JAL Mips::BAL Mips::BAL_BR Mips::BLTZAL Mips::BGEZAL Mips::JALR 0 0 Mips::ZERO


<s> void ia64_expand_compare ( rtx * expr , rtx * op0 , rtx * op1 ) { enum rtx_code code = GET_CODE ( * expr ) ; rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = 1 , QCMP_UNORD = 2 , QCMP_EQ = 4 , QCMP_LT = 8 , QCMP_GT = 16 } ; int magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , 0 , LCT_CONST , DImode , 3 , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code = NE ; } * expr = gen_rtx_fmt_ee ( code , VOIDmode , cmp , const0_rtx ) ; * op0 = cmp ; * op1 = const0_rtx ; } </s>

Emit comparison instruction if necessary , returning the expression that holds the compare result in the proper mode .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGlobalMergePass ( TM , 127 ) ) ; return false ; } </s>


<s> static bool aarch64_base_register_rtx_p ( rtx x , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG && contains_reg_of_mode [ GENERAL_REGS ] [ GET_MODE ( SUBREG_REG ( x ) ) ] ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && aarch64_regno_ok_for_base_p ( REGNO ( x ) , strict_p ) ) ; } </s>

Return true if X is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool AArch64TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == 128 ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> bool SICFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isUInt < 12 > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"64-bit code requested on a subtarget that doesn't support it!"

"Segmented stacks are only implemented on ELF."

This constructor initializes the data members to match that of the specified triple .


<s>
const
char
*
output_return
(
rtx_insn
*
insn
)
{
if
(
crtl
->
calls_eh_return
)
{
gcc_assert
(
!
final_sequence
)
;
if
(
flag_delayed_branch
)
{
if
(
!
TARGET_FLAT
&&
TARGET_V9
)
fputs
(
"\treturn\t%i7+8\n"
,
asm_out_file
)
;
else
{
if
(
!
TARGET_FLAT
)
fputs
(
"\trestore\n"
,
asm_out_file
)
;
fputs
(
"\tjmp\t%o7+8\n"
,
asm_out_file
)
;
}
fputs
(
"\t add\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
}
else
{
if
(
!
TARGET_FLAT
)
fputs
(
"\trestore\n"
,
asm_out_file
)
;
fputs
(
"\tadd\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
fputs
(
"\tjmp\t%o7+8\n\t nop\n"
,
asm_out_file
)
;
}
}
else
if
(
sparc_leaf_function_p
||
TARGET_FLAT
)
{
return
"jmp\t%%o7+%)%#"
;
}
else
{
if
(
final_sequence
)
{
rtx
delay
,
pat
;
delay
=
NEXT_INSN
(
insn
)
;
gcc_assert
(
delay
)
;
pat
=
PATTERN
(
delay
)
;
if
(
TARGET_V9
&&
!
epilogue_renumber
(
&
pat
,
1
)
)
{
epilogue_renumber
(
&
pat
,
0
)
;
return
"return\t%%i7+%)%#"
;
}
else
{
output_asm_insn
(
"jmp\t%%i7+%)"
,
)
;
output_restore
(
pat
)
;
PATTERN
(
delay
)
=
gen_blockage
(
)
;
INSN_CODE
(
delay
)
=
1
;
}
}
else
{
if
(
TARGET_V9
)
return
"return\t%%i7+%)\n\t nop"
;
else
if
(
flag_delayed_branch
)
return
"jmp\t%%i7+%)\n\t restore"
;
else
return
"restore\n\tjmp\t%%o7+%)\n\t nop"
;
}
}
return
""
;
}
</s>


<s>
bool
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
const
MachineOperand
*
&
Destination
,
const
MachineOperand
*
&
Source
,
int64_t
&
Offset
)
const
{
int
Sign
=
1
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
Source
=
&
MI
.
getOperand
(
1
)
;
Offset
=
MI
.
getOperand
(
2
)
.
getImm
(
)
*
Sign
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Offset
<<
Shift
;
}
}
Destination
=
&
MI
.
getOperand
(
0
)
;
return
true
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , 0 ) ; } } unsigned const Max = ( NumStores ? ( 12 / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"PowerPC Branch Selector"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void MandarinFrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MandarinMachineFunctionInfo * FuncInfo = MF . getInfo < MandarinMachineFunctionInfo > ( ) ; const MandarinInstrInfo & TII = * static_cast < const MandarinInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( - StackSize ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MD :: STORELri ) , MD :: R31 ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MD :: MOVrr ) , MD :: R31 ) . addReg ( MD :: R30 ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( MD :: R31 ) ; } if ( StackSize ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( MD :: ADDri ) , MD :: R30 ) . addReg ( MD :: R30 ) . addImm ( StackSize ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static inline bool general_or_i64_p ( reg_class_t rclass ) { return ( rclass == GENERAL_REGS || rclass == I64_REGS ) ; } </s>

Return true if CLASS is either GENERAL_REGS or I64_REGS .


<s> static tree mips_std_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { tree addr , t , type_size , rounded_size , valist_tmp ; unsigned HOST_WIDE_INT align , boundary ; bool indirect ; indirect = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( indirect ) type = build_pointer_type ( type ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = targetm . calls . function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; if ( boundary > align ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - 1 ) ) ; gimplify_and_add ( t , pre_p ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build2 ( BIT_AND_EXPR , TREE_TYPE ( valist ) , valist_tmp , build_int_cst ( TREE_TYPE ( valist ) , - boundary ) ) ) ; gimplify_and_add ( t , pre_p ) ; } else boundary = align ; boundary *= BITS_PER_UNIT ; if ( boundary < TYPE_ALIGN ( type ) ) { type = build_variant_type_copy ( type ) ; SET_TYPE_ALIGN ( type , boundary ) ; } type_size = size_in_bytes ( type ) ; rounded_size = round_up ( type_size , align ) ; gimplify_expr ( & rounded_size , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = valist_tmp ; if ( PAD_VARARGS_DOWN && ! integer_zerop ( rounded_size ) ) { t = fold_build2_loc ( input_location , GT_EXPR , sizetype , rounded_size , size_int ( align ) ) ; t = fold_build3 ( COND_EXPR , sizetype , t , size_zero_node , size_binop ( MINUS_EXPR , rounded_size , type_size ) ) ; addr = fold_build_pointer_plus ( addr , t ) ; } t = fold_build_pointer_plus ( valist_tmp , rounded_size ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( indirect ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>

Like std_gimplify_va_arg_expr , but apply alignment to zero-sized types as well .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfo > ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTree > ( ) ; TD = getAnalysisIfAvailable < DataLayout > ( ) ; LibInfo = getAnalysisIfAvailable < TargetLibraryInfo > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
,
end_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
)
;
ASM_GENERATE_INTERNAL_LABEL
(
end_lab
,
"LPSRE"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
reg2
;
if
(
TARGET_64BIT
)
output_asm_insn
(
"cmpd 0,%0,%1"
,
xops
)
;
else
output_asm_insn
(
"cmpw 0,%0,%1"
,
xops
)
;
fputs
(
"\tbeq 0,"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
end_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addi %0,%0,%1"
,
xops
)
;
xops
[
1
]
=
gen_rtx_REG
(
Pmode
,
0
)
;
output_asm_insn
(
"stw %1,0(%0)"
,
xops
)
;
fprintf
(
asm_out_file
,
"\tb "
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
end_lab
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> void Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"XNCM Assembly Printer"
;
}
</s>


<s> bool ARMTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( Val . getOpcode ( ) != ISD :: LOAD ) return false ; EVT VT1 = Val . getValueType ( ) ; if ( ! VT1 . isSimple ( ) || ! VT1 . isInteger ( ) || ! VT2 . isSimple ( ) || ! VT2 . isInteger ( ) ) return false ; switch ( VT1 . getSimpleVT ( ) . SimpleTy ) { default : break ; case MVT :: i1 : case MVT :: i8 : case MVT :: i16 : return true ; } return false ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { EVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } break ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"Unable to build a return instruction?!"

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool hasFPU ( ) const { return HasFPU ; } </s>


<s>
bool
ARMTargetLowering
::
ExpandInlineAsm
(
CallInst
*
CI
)
const
{
if
(
!
Subtarget
->
hasV6Ops
(
)
)
return
false
;
InlineAsm
*
IA
=
cast
<
InlineAsm
>
(
CI
->
getCalledOperand
(
)
)
;
std
::
string
AsmStr
=
IA
->
getAsmString
(
)
;
SmallVector
<
StringRef
,
4
>
AsmPieces
;
SplitString
(
AsmStr
,
AsmPieces
,
";\n"
)
;
switch
(
AsmPieces
.
size
(
)
)
{
default
:
return
false
;
case
1
:
AsmStr
=
std
::
string
(
AsmPieces
[
0
]
)
;
AsmPieces
.
clear
(
)
;
SplitString
(
AsmStr
,
AsmPieces
,
" \t,"
)
;
if
(
AsmPieces
.
size
(
)
==
3
&&
AsmPieces
[
0
]
==
"rev"
&&
AsmPieces
[
1
]
==
"$0"
&&
AsmPieces
[
2
]
==
"$1"
&&
IA
->
getConstraintString
(
)
.
compare
(
0
,
4
,
"=l,l"
)
==
0
)
{
IntegerType
*
Ty
=
dyn_cast
<
IntegerType
>
(
CI
->
getType
(
)
)
;
if
(
Ty
&&
Ty
->
getBitWidth
(
)
==
32
)
return
IntrinsicLowering
::
LowerToByteSwap
(
CI
)
;
}
break
;
}
return
false
;
}
</s>

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> rtx rs6000_darwin64_record_arg ( CUMULATIVE_ARGS * orig_cum , const_tree type , bool named , bool retval ) { rtx rvec [ FIRST_PSEUDO_REGISTER ] ; int k = 1 , kbase = 1 ; HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; CUMULATIVE_ARGS copy_cum = * orig_cum ; CUMULATIVE_ARGS * cum = & copy_cum ; if ( ! retval && TYPE_ALIGN ( type ) >= 2 * BITS_PER_WORD && ( cum -> words % 2 ) != 0 ) cum -> words ++ ; cum -> intoffset = 0 ; cum -> use_stack = 0 ; cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , 0 , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = 0 ; rvec [ 0 ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } if ( k > 1 || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( k - kbase , & rvec [ kbase ] ) ) ; else return NULL_RTX ; } </s>

For the darwin64 ABI , we want to construct a PARALLEL consisting of the register ( s ) to be used for each field and subfield of a struct being passed by value , along with the offset of where the register 's value may be found in the block . FP fields go in FP register , vector fields go in vector registers , and everything else goes in int registers , packed as in memory . This code is also used for function return values . RETVAL indicates whether this is the case . Much of this is taken from the SPARC V9 port , which has a similar calling convention .


<s> void mips_expand_vec_unpack ( rtx operands [ 2 ] , bool unsigned_p , bool high_p ) { machine_mode imode = GET_MODE ( operands [ 1 ] ) ; rtx ( * unpack ) ( rtx , rtx , rtx ) ; rtx ( * cmpFunc ) ( rtx , rtx , rtx ) ; rtx tmp , dest , zero ; if ( ISA_HAS_MSA ) { switch ( imode ) { case V4SImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_w ; else unpack = gen_msa_ilvr_w ; cmpFunc = gen_msa_clt_s_w ; break ; case V8HImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_h ; else unpack = gen_msa_ilvr_h ; cmpFunc = gen_msa_clt_s_h ; break ; case V16QImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_b ; else unpack = gen_msa_ilvr_b ; cmpFunc = gen_msa_clt_s_b ; break ; default : gcc_unreachable ( ) ; break ; } if ( ! unsigned_p ) { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , operands [ 1 ] , CONST0_RTX ( imode ) ) ) ; } else tmp = force_reg ( imode , CONST0_RTX ( imode ) ) ; dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; return ; } switch ( imode ) { case V8QImode : if ( high_p ) unpack = gen_loongson_punpckhbh ; else unpack = gen_loongson_punpcklbh ; cmpFunc = gen_loongson_pcmpgtb ; break ; case V4HImode : if ( high_p ) unpack = gen_loongson_punpckhhw ; else unpack = gen_loongson_punpcklhw ; cmpFunc = gen_loongson_pcmpgth ; break ; default : gcc_unreachable ( ) ; } zero = force_reg ( imode , CONST0_RTX ( imode ) ) ; if ( unsigned_p ) tmp = zero ; else { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , zero , operands [ 1 ] ) ) ; } dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; } </s>

Expand an integral vector unpack operation .


<s> static void ix86_emit_save_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to save registers using MOV insns . First register is restored from POINTER + OFFSET .


<s> void SystemZTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'J' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s>
unsigned
MipsMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
getMipsRegisterNumbering
(
Reg
)
;
return
RegNo
;
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
else
if
(
MO
.
isExpr
(
)
)
{
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
unsigned
Ret
=
0
;
if
(
Kind
==
MCExpr
::
Binary
)
{
const
MCBinaryExpr
*
BE
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
;
Expr
=
BE
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
const
MCConstantExpr
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
BE
->
getRHS
(
)
)
;
assert
(
(
Kind
==
MCExpr
::
SymbolRef
)
&&
CE
&&
"Binary expression must be sym+const."
)
;
Ret
=
CE
->
getValue
(
)
;
}
if
(
Kind
==
MCExpr
::
SymbolRef
)
{
Mips
::
Fixups
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
case
MCSymbolRefExpr
::
VK_Mips_GPREL
:
FixupKind
=
Mips
::
fixup_Mips_GPREL16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOT_CALL
:
FixupKind
=
Mips
::
fixup_Mips_CALL16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOT16
:
FixupKind
=
Mips
::
fixup_Mips_GOT_Global
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOT
:
FixupKind
=
Mips
::
fixup_Mips_GOT_Local
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
FixupKind
=
Mips
::
fixup_Mips_HI16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
FixupKind
=
Mips
::
fixup_Mips_LO16
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TLSGD
:
FixupKind
=
Mips
::
fixup_Mips_TLSGD
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TLSLDM
:
FixupKind
=
Mips
::
fixup_Mips_TLSLDM
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_DTPREL_HI
:
FixupKind
=
Mips
::
fixup_Mips_DTPREL_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_DTPREL_LO
:
FixupKind
=
Mips
::
fixup_Mips_DTPREL_LO
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_GOTTPREL
:
FixupKind
=
Mips
::
fixup_Mips_GOTTPREL
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TPREL_HI
:
FixupKind
=
Mips
::
fixup_Mips_TPREL_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_TPREL_LO
:
FixupKind
=
Mips
::
fixup_Mips_TPREL_LO
;
break
;
default
:
return
Ret
;
}
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
Expr
,
MCFixupKind
(
FixupKind
)
)
)
;
}
return
Ret
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool direct_move_p ( rtx op0 , rtx op1 ) { if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE ) return false ; int regno0 = REGNO ( op0 ) ; int regno1 = REGNO ( op1 ) ; if ( ! HARD_REGISTER_NUM_P ( regno0 ) || ! HARD_REGISTER_NUM_P ( regno1 ) ) return false ; if ( INT_REGNO_P ( regno0 ) && VSX_REGNO_P ( regno1 ) ) return true ; if ( VSX_REGNO_P ( regno0 ) && INT_REGNO_P ( regno1 ) ) return true ; return false ; } </s>

Return true if this is a move direct operation between GPR registers and floating point/VSX registers .


<s> bool X86ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FL = STI -> getFrameLowering ( ) ; bool Modified = ExpandPseudosWhichAffectControlFlow ( MF ) ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const PPCSubtarget * > ( STI ) -> getCPUDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = static_cast < const PPCSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new PPCScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

PowerPC PPC PPC PPC::DIR_440 PPC::DIR_A2 PPC


<s> bool AArch64PostRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand ) { bool OriginalResult = PostGenericScheduler :: tryCandidate ( Cand , TryCand ) ; if ( Cand . isValid ( ) ) { MachineInstr * Instr0 = TryCand . SU -> getInstr ( ) ; MachineInstr * Instr1 = Cand . SU -> getInstr ( ) ; if ( Instr0 && Instr1 && Instr0 -> getOpcode ( ) == Instr1 -> getOpcode ( ) && Instr0 -> getOpcode ( ) == AArch64 :: STPQi ) { MachineOperand & Base0 = Instr0 -> getOperand ( 2 ) ; MachineOperand & Base1 = Instr1 -> getOperand ( 2 ) ; int64_t Off0 = Instr0 -> getOperand ( 3 ) . getImm ( ) ; int64_t Off1 = Instr1 -> getOperand ( 3 ) . getImm ( ) ; if ( Base0 . isIdenticalTo ( Base1 ) && llabs ( Off0 - Off1 ) >= 2 ) { TryCand . Reason = NodeOrder ; return Off0 < Off1 ; } } } return OriginalResult ; } </s>

Apply a set of heuristics to a new candidate .


<s> static rtx xstormy16_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> bool OR1KAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OW -> write32 ( 0x15000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"This eliminateFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

"This code isn't needed if offset already handled!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void Cpu0FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; Cpu0FunctionInfo * Cpu0FI = MF . getInfo < Cpu0FunctionInfo > ( ) ; const Cpu0InstrInfo & TII = * static_cast < const Cpu0InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = Cpu0 :: SP ; unsigned FP = Cpu0 :: FP ; unsigned ZERO = Cpu0 :: ZERO ; unsigned ADDu = Cpu0 :: ADDu ; unsigned ADDiu = Cpu0 :: ADDiu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < 16 > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( StackSize ) ; else { Cpu0FI -> setEmitNOAT ( ) ; expandLargeImm ( SP , StackSize , TII , MBB , MBBI , dl ) ; } } </s>


<s> static bool aarch64_movw_imm ( HOST_WIDE_INT val , scalar_int_mode mode ) { if ( GET_MODE_SIZE ( mode ) > 4 ) { if ( ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 32 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 48 ) ) == val ) return 1 ; } else { val &= ( HOST_WIDE_INT ) 0xffffffff ; } return ( ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 0 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 16 ) ) == val ) ; } </s>

Return true if val is an immediate that can be loaded into a register by a MOVZ instruction .


<s> bool SystemZShortenInst :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; LiveRegs . clear ( ) ; LiveRegs . addLiveOuts ( & MBB ) ; for ( auto MBBI = MBB . rbegin ( ) , MBBE = MBB . rend ( ) ; MBBI != MBBE ; ++ MBBI ) { MachineInstr & MI = * MBBI ; switch ( MI . getOpcode ( ) ) { case SystemZ :: IILF : Changed |= shortenIIF ( MI , SystemZ :: LLILL , SystemZ :: LLILH ) ; break ; case SystemZ :: IIHF : Changed |= shortenIIF ( MI , SystemZ :: LLIHL , SystemZ :: LLIHH ) ; break ; case SystemZ :: WFADB : Changed |= shortenOn001AddCC ( MI , SystemZ :: ADBR ) ; break ; case SystemZ :: WFDDB : Changed |= shortenOn001 ( MI , SystemZ :: DDBR ) ; break ; case SystemZ :: WFIDB : Changed |= shortenFPConv ( MI , SystemZ :: FIDBRA ) ; break ; case SystemZ :: WLDEB : Changed |= shortenOn01 ( MI , SystemZ :: LDEBR ) ; break ; case SystemZ :: WLEDB : Changed |= shortenFPConv ( MI , SystemZ :: LEDBRA ) ; break ; case SystemZ :: WFMDB : Changed |= shortenOn001 ( MI , SystemZ :: MDBR ) ; break ; case SystemZ :: WFLCDB : Changed |= shortenOn01 ( MI , SystemZ :: LCDFR ) ; break ; case SystemZ :: WFLNDB : Changed |= shortenOn01 ( MI , SystemZ :: LNDFR ) ; break ; case SystemZ :: WFLPDB : Changed |= shortenOn01 ( MI , SystemZ :: LPDFR ) ; break ; case SystemZ :: WFSQDB : Changed |= shortenOn01 ( MI , SystemZ :: SQDBR ) ; break ; case SystemZ :: WFSDB : Changed |= shortenOn001AddCC ( MI , SystemZ :: SDBR ) ; break ; case SystemZ :: WFCDB : Changed |= shortenOn01 ( MI , SystemZ :: CDBR ) ; break ; case SystemZ :: VL32 : Changed |= shortenOn0 ( MI , SystemZ :: LDE32 ) ; break ; case SystemZ :: VST32 : Changed |= shortenOn0 ( MI , SystemZ :: STE ) ; break ; case SystemZ :: VL64 : Changed |= shortenOn0 ( MI , SystemZ :: LD ) ; break ; case SystemZ :: VST64 : Changed |= shortenOn0 ( MI , SystemZ :: STD ) ; break ; } LiveRegs . stepBackward ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ SystemZ::IILF SystemZ::LLILL SystemZ::LLILH SystemZ::IIHF SystemZ::LLIHL SystemZ::LLIHH SystemZ::WFADB SystemZ::ADBR SystemZ::WFDDB SystemZ::DDBR SystemZ::WFIDB SystemZ::FIDBRA SystemZ::WLDEB SystemZ::LDEBR SystemZ::WLEDB SystemZ::LEDBRA SystemZ::WFMDB SystemZ::MDBR SystemZ::WFLCDB SystemZ::LCDFR SystemZ::WFLNDB SystemZ::LNDFR SystemZ::WFLPDB SystemZ::LPDFR SystemZ::WFSQDB SystemZ::SQDBR SystemZ::WFSDB SystemZ::SDBR SystemZ::WFCDB SystemZ::CDBR SystemZ::VL32 SystemZ::LDE32 SystemZ::VST32 SystemZ::STE SystemZ::VL64 SystemZ::LD SystemZ::VST64 SystemZ::STD


"unexpected inline assembly memory operand"

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool aarch64_float_const_zero_rtx_p ( rtx x ) { if ( GET_MODE ( x ) == VOIDmode ) return false ; if ( REAL_VALUE_MINUS_ZERO ( * CONST_DOUBLE_REAL_VALUE ( x ) ) ) return ! HONOR_SIGNED_ZEROS ( GET_MODE ( x ) ) ; return real_equal ( CONST_DOUBLE_REAL_VALUE ( x ) , & dconst0 ) ; } </s>

Return TRUE if rtx X is immediate constant 0.0


<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( shouldInlineQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicRMWInIR ( AI ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool enableMachineScheduler ( ) const override { return isCheri ( ) || isBeri ( ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> const SystemZInstrInfo * getInstrInfo ( ) const { return Subtarget -> getInstrInfo ( ) ; } </s>


<s> void EmitInstruction ( uint32_t Val , raw_ostream & OS ) const { for ( unsigned i = 0 ; i != 4 ; ++ i ) { EmitByte ( Val & 0xff , OS ) ; Val >>= 8 ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned OR1KRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? OR1K :: R2 : OR1K :: R1 ; } </s>


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op1 , rtx op2 , rtx cond , rtx cc_op0 , rtx cc_op1 ) { enum machine_mode dest_mode = GET_MODE ( dest ) ; enum rtx_code rcode = GET_CODE ( cond ) ; rtx mask ; if ( ! TARGET_ALTIVEC ) return 0 ; mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , dest_mode ) ; rs6000_emit_vector_select ( dest , op1 , op2 , mask ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Case
(
"x18"
,
AArch64
::
X18
)
.
Case
(
"w18"
,
AArch64
::
W18
)
.
Default
(
0
)
;
if
(
(
Reg
==
AArch64
::
X18
||
Reg
==
AArch64
::
W18
)
&&
!
Subtarget
->
isX18Reserved
(
)
)
Reg
=
0
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool direct_move_p ( rtx op0 , rtx op1 ) { int regno0 , regno1 ; if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE && ! TARGET_MFPGPR ) return false ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; if ( regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 ) ) return true ; else if ( TARGET_DIRECT_MOVE && VSX_REGNO_P ( regno0 ) ) return true ; } return false ; } </s>

Return true if this is a move direct operation between GPR registers and floating point/VSX registers .


<s> bool AArch64TargetLowering :: isLegalInterleavedAccessType ( VectorType * VecTy , const DataLayout & DL , bool & UseScalable ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; unsigned NumElements = cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) ; UseScalable = false ; if ( NumElements < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 && ElSize != 64 ) return false ; if ( Subtarget -> useSVEForFixedLengthVectors ( ) && ( VecSize % Subtarget -> getMinSVEVectorSizeInBits ( ) == 0 || ( VecSize < Subtarget -> getMinSVEVectorSizeInBits ( ) && isPowerOf2_32 ( NumElements ) && VecSize > 128 ) ) ) { UseScalable = true ; return true ; } return VecSize == 64 || VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> unsigned PPCFastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 ) { const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_r ( MachineInstOpcode , UseRC , Op0 ) ; } </s>

Emit a MachineInstr with one register operand and a result register in the given register class .


<s> static void rs6000_free_sched_context ( void * _sc ) { gcc_assert ( _sc != NULL ) ; free ( _sc ) ; } </s>


<s> bool X86InstrInfo :: canMakeTailCallConditional ( SmallVectorImpl < MachineOperand > & BranchCond , const MachineInstr & TailCall ) const { if ( TailCall . getOpcode ( ) != X86 :: TCRETURNdi && TailCall . getOpcode ( ) != X86 :: TCRETURNdi64 ) { return false ; } if ( Subtarget . isTargetWin64 ( ) ) { return false ; } assert ( BranchCond . size ( ) == 1 ) ; if ( BranchCond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) { return false ; } const X86MachineFunctionInfo * X86FI = TailCall . getParent ( ) -> getParent ( ) -> getInfo < X86MachineFunctionInfo > ( ) ; if ( X86FI -> getTCReturnAddrDelta ( ) != 0 || TailCall . getOperand ( 1 ) . getImm ( ) != 0 ) { return false ; } return true ; } </s>

Returns true if the tail call can be made conditional on BranchCond .


<s> gimple * gimple_folder :: fold_to_cstu ( poly_uint64 val ) { return gimple_build_assign ( lhs , build_int_cstu ( TREE_TYPE ( lhs ) , val ) ) ; } </s>


<s> bool SparcTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> const_iterator end ( ) const { return m_SectToExData . end ( ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> bool X86TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == MVT :: f32 ) return X86ScalarSSEf32 ; if ( VT == MVT :: f64 ) return X86ScalarSSEf64 ; return true ; } </s>

Returns true if it 's safe to use load / store of the specified type to expand memcpy / memset inline .


<s> bool SystemZDAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { if ( N . getOpcode ( ) == ISD :: LOAD && U -> getOpcode ( ) == SystemZISD :: ICMP ) { if ( ! N . hasOneUse ( ) || ! U -> hasOneUse ( ) ) return false ; SDNode * CCUser = * U -> use_begin ( ) ; SDNode * CCRegUser = nullptr ; if ( CCUser -> getOpcode ( ) == ISD :: CopyToReg || cast < RegisterSDNode > ( CCUser -> getOperand ( 1 ) ) -> getReg ( ) == SystemZ :: CC ) { for ( auto * U : CCUser -> uses ( ) ) { if ( CCRegUser == nullptr ) CCRegUser = U ; else if ( CCRegUser != U ) return false ; } } if ( CCRegUser == nullptr ) return false ; if ( CCRegUser -> isMachineOpcode ( ) && CCRegUser -> getMachineOpcode ( ) == SystemZ :: BRC ) return ! N -> isPredecessorOf ( CCUser -> getOperand ( 0 ) . getNode ( ) ) ; if ( ! IsLegalToFold ( N , U , CCRegUser , OptLevel , false ) ) return false ; } return true ; } </s>

IsProfitableToFold - Returns true if it 's profitable to fold the specific operand node N of U during instruction selection that starts at Root .

SystemZ SystemZ ISD::LOAD SystemZISD::ICMP ISD::CopyToReg 1 SystemZ::CC SystemZ::BRC 0


<s> static const predefined_function_abi & aarch64_simd_abi ( void ) { predefined_function_abi & simd_abi = function_abis [ ARM_PCS_SIMD ] ; if ( ! simd_abi . initialized_p ( ) ) { HARD_REG_SET full_reg_clobbers = default_function_abi . full_reg_clobbers ( ) ; for ( int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( FP_SIMD_SAVED_REGNUM_P ( regno ) ) CLEAR_HARD_REG_BIT ( full_reg_clobbers , regno ) ; simd_abi . initialize ( ARM_PCS_SIMD , full_reg_clobbers ) ; } return simd_abi ; } </s>


<s> bool isMem ( ) const { return Kind == Memory ; } </s>


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) KnownZero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : KnownZero = ~ 1U ; break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; Subtarget = & F . getSubtarget < SparcSubtarget > ( ) ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createSparcELFObjectWriter ( OS , is64Bit ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> virtual const IA64Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void rs6000_emit_stack_tie ( ) { rtx mem = gen_rtx_MEM ( BLKmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set ) ; emit_insn ( gen_stack_tie ( mem ) ) ; } </s>

This ties together stack memory ( MEM with an alias set of rs6000_sr_alias_set ) and the change to the stack pointer .


<s>
void
SparcMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
unsigned
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
Ctx
.
getAsmInfo
(
)
->
isLittleEndian
(
)
support
::
little
:
support
::
big
)
;
unsigned
tlsOpNo
=
0
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
SP
::
TLS_CALL
:
tlsOpNo
=
1
;
break
;
case
SP
::
TLS_ADDrr
:
case
SP
::
TLS_ADDXrr
:
case
SP
::
TLS_LDrr
:
case
SP
::
TLS_LDXrr
:
tlsOpNo
=
3
;
break
;
}
if
(
tlsOpNo
!=
0
)
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
tlsOpNo
)
;
uint64_t
op
=
getMachineOpValue
(
MI
,
MO
,
Fixups
,
STI
)
;
assert
(
op
==
0
&&
"Unexpected operand value!"
)
;
(
void
)
op
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s>
bool
AArch64InstrInfo
::
shouldClusterMemOps
(
MachineInstr
*
FirstLdSt
,
MachineInstr
*
SecondLdSt
,
unsigned
NumLoads
)
const
{
if
(
NumLoads
>
1
)
return
false
;
unsigned
FirstOpc
=
FirstLdSt
->
getOpcode
(
)
;
unsigned
SecondOpc
=
SecondLdSt
->
getOpcode
(
)
;
if
(
!
canPairLdStOpc
(
FirstOpc
,
SecondOpc
)
)
return
false
;
if
(
!
isCandidateToMergeOrPair
(
FirstLdSt
)
||
!
isCandidateToMergeOrPair
(
SecondLdSt
)
)
return
false
;
int64_t
Offset1
=
FirstLdSt
->
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
FirstOpc
)
&&
!
scaleOffset
(
FirstOpc
,
Offset1
)
)
return
false
;
int64_t
Offset2
=
SecondLdSt
->
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
SecondOpc
)
&&
!
scaleOffset
(
SecondOpc
,
Offset2
)
)
return
false
;
if
(
Offset1
>
63
||
Offset1
<
64
)
return
false
;
assert
(
Offset1
<=
Offset2
&&
"Caller should have ordered offsets."
)
;
return
Offset1
+
1
==
Offset2
;
}
</s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> static rtx legitimize_dllimport_symbol ( rtx symbol , bool want_reg ) { tree imp_decl ; rtx x ; gcc_assert ( SYMBOL_REF_DECL ( symbol ) ) ; imp_decl = get_dllimport_decl ( SYMBOL_REF_DECL ( symbol ) , true ) ; x = DECL_RTL ( imp_decl ) ; if ( want_reg ) x = force_reg ( Pmode , x ) ; return x ; } </s>

Expand SYMBOL into its corresponding dllimport symbol . WANT_REG is true if we require the result be a register .


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel"


<s> bool isUnconditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == ARM :: Bcc && Inst . getOperand ( 1 ) . getImm ( ) == ARMCC :: AL ) return true ; return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( Op . getNode ( ) , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned Alignment , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == MVT :: i8 || Ty == MVT :: i16 || Ty == MVT :: i32 ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == MVT :: f64 || Ty == MVT :: v2f64 ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == MVT :: v16i1 || Ty == MVT :: v8i1 || Ty == MVT :: v4i1 ) ) { if ( Fast ) * Fast = true ; return true ; } if ( Ty != MVT :: v16i8 && Ty != MVT :: v8i16 && Ty != MVT :: v8f16 && Ty != MVT :: v4i32 && Ty != MVT :: v4f32 && Ty != MVT :: v2i64 && Ty != MVT :: v2f64 && Ty != MVT :: v4i8 && Ty != MVT :: v8i8 && Ty != MVT :: v4i16 ) return false ; if ( Subtarget -> isLittle ( ) ) { if ( Fast ) * Fast = true ; return true ; } else { if ( Ty == MVT :: v16i8 || ( ( Ty == MVT :: v8i16 || Ty == MVT :: v8f16 ) && Alignment >= 2 ) || ( ( Ty == MVT :: v4i32 || Ty == MVT :: v4f32 ) && Alignment >= 4 ) ) { if ( Fast ) * Fast = true ; return true ; } } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static tree ATTRIBUTE_UNUSED rs6000_stack_protect_fail ( void ) { return ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) ? default_hidden_stack_protect_fail ( ) : default_external_stack_protect_fail ( ) ; } </s>

For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register setup by using __stack_chk_fail_local hidden function instead of calling __stack_chk_fail directly . Otherwise it is better to call __stack_chk_fail directly .


<s> static int sparc_tls_symbol_ref_1 ( rtx * x , void * data ATTRIBUTE_UNUSED ) { return SPARC_SYMBOL_REF_TLS_P ( * x ) ; } </s>

Return 1 if * X is a thread-local symbol .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
FeatureBitset
MissingFeatures
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
MissingFeatures
.
any
(
)
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
for
(
unsigned
I
=
0
,
E
=
MissingFeatures
.
size
(
)
;
I
!=
E
;
++
I
)
{
if
(
MissingFeatures
[
I
]
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
I
)
;
}
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
SystemZMnemonicSpellCheck
(
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

SystemZ
SystemZ
"Unknown missing feature!"
"instruction requires:"
0
" "
0ULL
"too few operands for instruction"
SystemZ
"invalid operand for instruction"
SystemZ
SystemZ
0
"invalid instruction"
SystemZ
0
"Unexpected match type"


"  Copied r%d to a scalar register r%d for insn %d\n"

Convert all definitions of register REGNO and fix its uses . Scalar copies may be created in case register is used in not convertible insn .


"Can only put epilog before 'retl' instruction!"


<s> static bool zero_call_used_regno_p ( const unsigned int regno , bool all_sse_zeroed , bool need_zero_mmx ) { return GENERAL_REGNO_P ( regno ) || ( ! all_sse_zeroed && SSE_REGNO_P ( regno ) ) || MASK_REGNO_P ( regno ) || ( need_zero_mmx && MMX_REGNO_P ( regno ) ) ; } </s>

Check whether the register REGNO should be zeroed on X86 . When ALL_SSE_ZEROED is true , all SSE registers have been zeroed together , no need to zero it again . When NEED_ZERO_MMX is true , MMX registers should be cleared .


<s> static void ix86_emit_mode_set ( int entity , int mode , int prev_mode ATTRIBUTE_UNUSED , HARD_REG_SET regs_live ATTRIBUTE_UNUSED ) { switch ( entity ) { case X86_DIRFLAG : if ( mode == X86_DIRFLAG_RESET ) emit_insn ( gen_cld ( ) ) ; break ; case AVX_U128 : if ( mode == AVX_U128_CLEAN ) emit_insn ( gen_avx_vzeroupper ( ) ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Generate one or more insns to set ENTITY to MODE . HARD_REG_LIVE is the set of hard registers live at the point where the insn ( s ) are to be inserted .


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; rtx_insn * insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> static int pa_adjust_priority ( rtx_insn * insn , int priority ) { rtx set = single_set ( insn ) ; rtx src , dest ; if ( set ) { src = SET_SRC ( set ) ; dest = SET_DEST ( set ) ; if ( GET_CODE ( src ) == LO_SUM && symbolic_operand ( XEXP ( src , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( src , 1 ) , VOIDmode ) ) priority >>= 3 ; else if ( GET_CODE ( src ) == MEM && GET_CODE ( XEXP ( src , 0 ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( src , 0 ) , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( XEXP ( src , 0 ) , 1 ) , VOIDmode ) ) priority >>= 1 ; else if ( GET_CODE ( dest ) == MEM && GET_CODE ( XEXP ( dest , 0 ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( dest , 0 ) , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( XEXP ( dest , 0 ) , 1 ) , VOIDmode ) ) priority >>= 3 ; } return priority ; } </s>

Adjust scheduling priorities . We use this to try and keep addil and the next use of % r1 close together .


<s> void SystemZHazardRecognizer :: Reset ( ) { CurrGroupSize = 0 ; clearProcResCounters ( ) ; GrpCount = 0 ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ; LLVM_DEBUG ( CurGroupDbg = "" ; ) ; } </s>


<s>
void
Mips16InstrInfo
::
adjustStackPtr
(
unsigned
SP
,
int64_t
Amount
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
isInt
<
16
>
(
Amount
)
)
{
if
(
Amount
<
0
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SaveDecSpF16
)
)
.
addImm
(
Amount
)
;
else
if
(
Amount
>
0
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
RestoreIncSpF16
)
)
.
addImm
(
Amount
)
;
}
else
assert
(
false
&&
"adjust stack pointer amount exceeded"
)
;
}
</s>


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . getMMI ( ) . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void handleAssemblerFlag ( MCAssemblerFlag Flag ) override { switch ( Flag ) { default : break ; case MCAF_Code16 : setIsThumb ( true ) ; break ; case MCAF_Code32 : setIsThumb ( false ) ; break ; } } </s>

Handle any target-specific assembler flags . By default , do nothing .


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( GET_CODE ( XVECEXP ( x , 0 , 0 ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base_oac && tocrel_offset_oac != const0_rtx ) { if ( INTVAL ( tocrel_offset_oac ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset_oac ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s> rtx or1k_dynamic_chain_addr ( rtx frame ) { return plus_constant ( Pmode , frame , - 2 * UNITS_PER_WORD ) ; } </s>

Worker for DYNAMIC_CHAIN_ADDRESS . Returns the RTX representing the address of where the caller 's frame pointer may be stored on the stack .


<s> const uint16_t * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { SystemZ :: R6D , SystemZ :: R7D , SystemZ :: R8D , SystemZ :: R9D , SystemZ :: R10D , SystemZ :: R11D , SystemZ :: R12D , SystemZ :: R13D , SystemZ :: R14D , SystemZ :: R15D , SystemZ :: F8D , SystemZ :: F9D , SystemZ :: F10D , SystemZ :: F11D , SystemZ :: F12D , SystemZ :: F13D , SystemZ :: F14D , SystemZ :: F15D , 0 } ; return CalleeSavedRegs ; } </s>


<s> int AArch64TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 ) { int NumConstants = ( BitSize + 63 ) / 64 ; int Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> int short_memory_operand ( rtx x , enum machine_mode mode ) { if ( ! memory_operand ( x , mode ) ) return 0 ; return ( GET_CODE ( XEXP ( x , 0 ) ) != PLUS ) ; } </s>

Return 1 if OP is a valid operand for a ` short ' memory reference insn .


<s> static bool mt_pass_in_stack ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type ) { return ( ( ( type ) != 0 && ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || TREE_ADDRESSABLE ( type ) ) ) ) ; } </s>

Implement TARGET_MUST_PASS_IN_STACK hook .


<s> void ix86_expand_clear ( rtx dest ) { rtx tmp ; gcc_assert ( reload_completed ) ; if ( GET_MODE_SIZE ( GET_MODE ( dest ) ) < 4 ) dest = gen_rtx_REG ( SImode , REGNO ( dest ) ) ; tmp = gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ; if ( reload_completed && ( ! TARGET_USE_MOV0 || optimize_size ) ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , 17 ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , tmp , clob ) ) ; } emit_insn ( tmp ) ; } </s>

Generate either `` mov $ 0 , reg '' or `` xor reg , reg '' , as appropriate for the target .