<s> bool aarch64_mask_and_shift_for_ubfiz_p ( scalar_int_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) + 1 ) >= 0 && ( INTVAL ( mask ) & ( ( 1 << INTVAL ( shft_amnt ) ) - 1 ) ) == 0 ; } </s>

Return true if the mask and a shift amount from an RTX of the form ( x < < SHFT_AMNT ) & MASK are valid to combine into a UBFIZ instruction of mode MODE . See the * andim_ashift < mode > _bfiz pattern .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOCAL_ESCAPE
)
{
MachineOperand
&
FI
=
MI
.
getOperand
(
FIOperandNum
)
;
Offset
=
TFI
->
getNonLocalFrameIndexReference
(
MF
,
FrameIndex
)
;
FI
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
getFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static unsigned int ix86_minimum_incoming_stack_boundary ( bool sibcall ) { unsigned int incoming_stack_boundary ; if ( cfun -> machine -> func_type != TYPE_NORMAL ) incoming_stack_boundary = TARGET_64BIT ? 128 : MIN_STACK_BOUNDARY ; else if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == 128 ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ; if ( incoming_stack_boundary > MIN_STACK_BOUNDARY && lookup_attribute ( ix86_force_align_arg_pointer_string , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; if ( incoming_stack_boundary < crtl -> parm_stack_boundary ) incoming_stack_boundary = crtl -> parm_stack_boundary ; if ( incoming_stack_boundary > MAIN_STACK_BOUNDARY && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) incoming_stack_boundary = MAIN_STACK_BOUNDARY ; return incoming_stack_boundary ; } </s>

Return minimum incoming stack alignment .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
(
void
)
RetFastCC_ARM_APCS
;
(
void
)
FastCC_ARM_APCS
;
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
ARM_AAPCS_VFP
:
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM


<s> static bool rs6000_expand_vec_perm_const_1 ( rtx target , rtx op0 , rtx op1 , unsigned char perm0 , unsigned char perm1 ) { rtx x ; if ( ( perm0 & 2 ) == ( perm1 & 2 ) ) { if ( perm0 & 2 ) op0 = op1 ; else op1 = op0 ; } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & 1 ; perm1 = ( perm1 & 1 ) + 2 ; } else if ( perm0 & 2 ) { if ( perm1 & 2 ) return false ; perm0 -= 2 ; perm1 += 2 ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & 2 ) == 0 ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == 2 ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , 4 ) . require ( ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( 2 , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } return true ; } </s>

Expand a Paired Single or VSX Permute Doubleword constant permutation . Return true if we match an efficient implementation .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; } tocrel_base = op ; tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride ) , FrameLowering ( * this , Subtarget ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , DL ( computeDataLayout ( * getSubtargetImpl ( ) ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , JITInfo ( * this ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> unsigned ARMBaseInstrInfo :: predictBranchSizeForIfCvt ( MachineInstr & MI ) const { if ( MI . getOpcode ( ) == ARM :: t2Bcc && findCMPToFoldIntoCBZ ( & MI , & getRegisterInfo ( ) ) ) return 0 ; unsigned Size = getInstSizeInBytes ( MI ) ; if ( Subtarget . isThumb2 ( ) ) Size /= 2 ; return Size ; } </s>

Return an estimate for the code size reduction ( in bytes ) which will be caused by removing the given branch instruction during if-conversion .


<s> static bool mep_get_move_insn ( int intrinsic , const struct cgen_insn * * cgen_insn ) { size_t i ; if ( intrinsic == mep_cmov ) { for ( i = 0 ; i < ARRAY_SIZE ( mep_cmov_insns ) ; i ++ ) if ( mep_get_intrinsic_insn ( mep_cmov_insns [ i ] , cgen_insn ) ) return true ; return false ; } return mep_get_intrinsic_insn ( intrinsic , cgen_insn ) ; } </s>

Like mep_get_intrinsic_insn , but with extra handling for moves . If INTRINSIC is mep_cmov , but there is no pure CR < - CR move insn , try using a work-alike instead . In this case , the returned insn may have three operands rather than two .


<s>
bool
ARMTargetLowering
::
ExpandInlineAsm
(
CallInst
*
CI
)
const
{
if
(
!
Subtarget
->
hasV6Ops
(
)
)
return
false
;
InlineAsm
*
IA
=
cast
<
InlineAsm
>
(
CI
->
getCalledValue
(
)
)
;
std
::
string
AsmStr
=
IA
->
getAsmString
(
)
;
SmallVector
<
StringRef
,
4
>
AsmPieces
;
SplitString
(
AsmStr
,
AsmPieces
,
";\n"
)
;
switch
(
AsmPieces
.
size
(
)
)
{
default
:
return
false
;
case
1
:
AsmStr
=
std
::
string
(
AsmPieces
[
0
]
)
;
AsmPieces
.
clear
(
)
;
SplitString
(
AsmStr
,
AsmPieces
,
" \t,"
)
;
if
(
AsmPieces
.
size
(
)
==
3
&&
AsmPieces
[
0
]
==
"rev"
&&
AsmPieces
[
1
]
==
"$0"
&&
AsmPieces
[
2
]
==
"$1"
&&
IA
->
getConstraintString
(
)
.
compare
(
0
,
4
,
"=l,l"
)
==
0
)
{
IntegerType
*
Ty
=
dyn_cast
<
IntegerType
>
(
CI
->
getType
(
)
)
;
if
(
Ty
&&
Ty
->
getBitWidth
(
)
==
32
)
return
IntrinsicLowering
::
LowerToByteSwap
(
CI
)
;
}
break
;
}
return
false
;
}
</s>

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> void MipsAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { OutStreamer -> AddBlankLine ( ) ; getTargetStreamer ( ) . emitDirectiveSetPop ( ) ; } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> void LC3bMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return LowerRETURNADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN


<s> void LanaiFrameLowering :: emitEpilogue ( MachineFunction & , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const LanaiInstrInfo & LII = * static_cast < const LanaiInstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , LII . get ( Lanai :: ADD_I_LO ) , Lanai :: SP ) . addReg ( Lanai :: FP ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , DL , LII . get ( Lanai :: LDW_RI ) , Lanai :: FP ) . addReg ( Lanai :: FP ) . addImm ( - 8 ) . addImm ( LPAC :: ADD ) ; } </s>

Lanai Lanai Lanai Lanai Lanai::ADD_I_LO Lanai::SP Lanai::FP 0 Lanai::LDW_RI Lanai::FP Lanai::FP 8


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int standard_80387_constant_p ( rtx x ) { if ( GET_CODE ( x ) != CONST_DOUBLE || ! FLOAT_MODE_P ( GET_MODE ( x ) ) ) return - 1 ; if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) return 1 ; if ( x == CONST1_RTX ( GET_MODE ( x ) ) ) return 2 ; if ( GET_MODE ( x ) == XFmode && ( optimize_size || x86_ext_80387_constants & TUNEMASK ) ) { REAL_VALUE_TYPE r ; int i ; if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; for ( i = 0 ; i < 5 ; i ++ ) if ( real_identical ( & r , & ext_80387_constants_table [ i ] ) ) return i + 3 ; } return 0 ; } </s>

Return true if the constant is something that can be loaded with a special instruction .


<s> bool sparc_can_use_return_insn_p ( void ) { return sparc_prologue_data_valid_p && sparc_n_global_fp_regs == 0 && TARGET_FLAT ? ( sparc_frame_size == 0 && ! sparc_save_local_in_regs_p ) : ( sparc_frame_size == 0 || ! sparc_leaf_function_p ) ; } </s>

Return true if it is appropriate to emit ` return ' instructions in the body of a function .


<s> unsigned getBaseReg ( ) { return BaseReg ; } </s>

Get the base register of the pointer value .


<s>
void
UPTFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
">> FrameLowering::emitEpilogue <<\n"
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
uint64_t
StackSize
=
computeStackSize
(
MF
)
;
if
(
!
StackSize
)
{
return
;
}
unsigned
StackReg
=
UPT
::
SP
;
unsigned
OffsetReg
=
materializeOffset
(
MF
,
MBB
,
MBBI
,
(
unsigned
)
StackSize
)
;
if
(
OffsetReg
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
UPT
::
ADDR
)
,
StackReg
)
.
addReg
(
StackReg
)
.
addReg
(
OffsetReg
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
else
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
UPT
::
ADDI
)
,
StackReg
)
.
addReg
(
StackReg
)
.
addImm
(
StackSize
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
}
</s>

UPT
UPT
">> FrameLowering::emitEpilogue <<\n"
UPT::SP
UPT::ADDR
UPT::ADDI


<s> unsigned PPCAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = 0 ; break ; case MCK_1 : ImmVal = 1 ; break ; default : return Match_InvalidOperand ; } PPCOperand * Op = static_cast < PPCOperand * > ( AsmOp ) ; if ( Op -> isImm ( ) && Op -> getImm ( ) == ImmVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static tree rx_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= RX_BUILTIN_max ) return error_mark_node ; return rx_builtins [ code ] ; } </s>


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = 0 , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> rtx sh_dwarf_register_span ( rtx reg ) { unsigned regno = REGNO ( reg ) ; if ( WORDS_BIG_ENDIAN || GET_MODE ( reg ) != DFmode ) return NULL_RTX ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_REG ( SFmode , regno + 1 ) , gen_rtx_REG ( SFmode , regno ) ) ) ; } </s>

64 bit floating points memory transfers are paired single precision loads or store . So DWARF information needs fixing in little endian ( unless PR=SZ=1 in FPSCR ) .


<s> void arm_decompose_di_binop ( rtx op1 , rtx op2 , rtx * lo_op1 , rtx * hi_op1 , rtx * lo_op2 , rtx * hi_op2 ) { * lo_op1 = gen_lowpart ( SImode , op1 ) ; * hi_op1 = gen_highpart ( SImode , op1 ) ; * lo_op2 = simplify_gen_subreg ( SImode , op2 , DImode , subreg_lowpart_offset ( SImode , DImode ) ) ; * hi_op2 = simplify_gen_subreg ( SImode , op2 , DImode , subreg_highpart_offset ( SImode , DImode ) ) ; } </s>

Decompose operands for a 64-bit binary operation in OP1 and OP2 into its component 32-bit subregs . OP2 may be an immediate constant and we want to simplify it in that case .


<s> void erase ( iterator it ) { m_SectToExData . erase ( it ) ; } </s>

erase - Erases an element identified by Key , if it exists .


<s> static void aarch64_select_early_remat_modes ( sbitmap modes ) { for ( int i = 0 ; i < NUM_MACHINE_MODES ; ++ i ) { machine_mode mode = ( machine_mode ) i ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_ANY_SVE ) bitmap_set_bit ( modes , i ) ; } } </s>


<s> unsigned X86TTI :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TCC_Free ; switch ( IID ) { default : return TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( ( Idx == 1 ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; } return X86TTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void SystemZMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize ( ) ; unsigned ShiftValue = ( Size * 8 ) - 8 ; for ( unsigned I = 0 ; I != Size ; ++ I ) { OS << uint8_t ( Bits >> ShiftValue ) ; ShiftValue -= 8 ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> static bool expand_vec_perm_interleave3 ( struct expand_vec_perm_d * d ) { unsigned i , nelt ; rtx ( * gen ) ( rtx , rtx , rtx ) ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( d -> vmode ) == 32 ) ; else if ( TARGET_AVX && ( d -> vmode == V8SFmode || d -> vmode == V4DFmode ) ) ; else return false ; nelt = d -> nelt ; if ( d -> perm [ 0 ] != 0 && d -> perm [ 0 ] != nelt / 2 ) return false ; for ( i = 0 ; i < nelt ; i += 2 ) if ( d -> perm [ i ] != d -> perm [ 0 ] + i / 2 || d -> perm [ i + 1 ] != d -> perm [ 0 ] + i / 2 + nelt ) return false ; if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V32QImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv32qi ; else gen = gen_vec_interleave_lowv32qi ; break ; case V16HImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv16hi ; else gen = gen_vec_interleave_lowv16hi ; break ; case V8SImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv8si ; else gen = gen_vec_interleave_lowv8si ; break ; case V4DImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv4di ; else gen = gen_vec_interleave_lowv4di ; break ; case V8SFmode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv8sf ; else gen = gen_vec_interleave_lowv8sf ; break ; case V4DFmode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv4df ; else gen = gen_vec_interleave_lowv4df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( d -> target , d -> op0 , d -> op1 ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to simplify a two vector permutation using 2 intra-lane interleave insns and cross-lane shuffle for 32-byte vectors .


<s> void MipsAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx rs6000_expand_zeroop_builtin ( enum insn_code icode , rtx target ) { rtx pat ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; if ( icode == CODE_FOR_nothing ) return 0 ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Expand an expression EXP that calls a builtin without arguments .


<s> static bool arm_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '@' || code == '|' || code == '.' || code == '(' || code == ')' || code == '#' || ( TARGET_32BIT && ( code == '?' ) ) || ( TARGET_THUMB2 && ( code == '!' ) ) || ( TARGET_THUMB && ( code == '_' ) ) ) ; } </s>

Target hook for indicating whether a punctuation character for TARGET_PRINT_OPERAND is valid .


<s> bool Mips16InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> static bool sparc_print_operand_punct_valid_p ( unsigned char code ) { if ( code == '#' || code == '*' || code == '(' || code == ')' || code == '_' || code == '&' ) return true ; return false ; } </s>


<s> static void mips_sim_issue_insn ( struct mips_sim * state , rtx_insn * insn ) { curr_state = state -> dfa_state ; state_transition ( curr_state , insn ) ; state -> insns_left = targetm . sched . variable_issue ( 0 , false , insn , state -> insns_left ) ; mips_sim_insn = insn ; note_stores ( insn , mips_sim_record_set , state ) ; } </s>

Issue instruction INSN in scheduler state STATE . Assume that INSN can issue immediately ( i.e. , that mips_sim_wait_insn has already been called ) .


"function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, "

Advance the argument of type TYPE and mode MODE to the next argument position in CUM .


"invalid instruction when using jump guards!"

Perform target-specific instruction verification .


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
->
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
->
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
callRegIndirect
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void csky_set_eh_return_address ( rtx source , rtx scratch ) { HOST_WIDE_INT delta = 0 ; rtx basereg , addr ; unsigned int reg_mask ; csky_layout_stack_frame ( ) ; reg_mask = cfun -> machine -> reg_mask ; if ( reg_mask & ( 1 << CSKY_LR_REGNUM ) ) { int i = 0 ; if ( frame_pointer_needed ) { basereg = hard_frame_pointer_rtx ; delta = 0 ; } else { basereg = stack_pointer_rtx ; delta = cfun -> machine -> reg_offset ; } for ( i = 0 ; i < CSKY_LR_REGNUM ; i ++ ) if ( reg_mask & ( 1 << i ) ) delta += 4 ; if ( ( CSKY_TARGET_ARCH ( CK801 ) && delta >= CSKY_LD16_MAX_OFFSET ( Pmode ) ) || delta >= CSKY_LD32_MAX_OFFSET ( Pmode ) ) { emit_insn ( gen_movsi ( scratch , GEN_INT ( delta ) ) ) ; emit_insn ( gen_addsi3 ( scratch , scratch , basereg ) ) ; addr = scratch ; } else addr = plus_constant ( Pmode , basereg , delta ) ; emit_move_insn ( gen_frame_mem ( Pmode , addr ) , source ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , CSKY_LR_REGNUM ) , source ) ; } </s>

Helper for csky_eh_return splitter : store the call frame exception handler address in lr .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { unsigned NumBytes = 4 ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) { return ; } unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s>
void
Mips16InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOStore
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
SwRxSpImmX16
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"MachineModuleInfo should always be available"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool AArch64InstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case AArch64 :: FADDDrr : case AArch64 :: FADDSrr : case AArch64 :: FADDv2f32 : case AArch64 :: FADDv2f64 : case AArch64 :: FADDv4f32 : case AArch64 :: FMULDrr : case AArch64 :: FMULSrr : case AArch64 :: FMULX32 : case AArch64 :: FMULX64 : case AArch64 :: FMULXv2f32 : case AArch64 :: FMULXv2f64 : case AArch64 :: FMULXv4f32 : case AArch64 :: FMULv2f32 : case AArch64 :: FMULv2f64 : case AArch64 :: FMULv4f32 : return Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AArch64 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void require_pic_register ( rtx pic_reg , bool compute_now ) { gcc_assert ( compute_now == ( pic_reg != NULL_RTX ) ) ; if ( ! crtl -> uses_pic_offset_table || compute_now ) { gcc_assert ( can_create_pseudo_p ( ) || ( pic_reg != NULL_RTX && REG_P ( pic_reg ) && GET_MODE ( pic_reg ) == Pmode ) ) ; if ( arm_pic_register != INVALID_REGNUM && ! compute_now && ! ( TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM ) ) { if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_rtx_REG ( Pmode , arm_pic_register ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) crtl -> uses_pic_offset_table = 1 ; } else { rtx_insn * seq , * insn ; if ( pic_reg == NULL_RTX ) pic_reg = gen_reg_rtx ( Pmode ) ; if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = pic_reg ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) { crtl -> uses_pic_offset_table = 1 ; start_sequence ( ) ; if ( TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && ! compute_now ) emit_move_insn ( cfun -> machine -> pic_reg , gen_rtx_REG ( Pmode , arm_pic_register ) ) ; else arm_load_pic_register ( 0UL , pic_reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; for ( insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) INSN_LOCATION ( insn ) = prologue_location ; if ( currently_expanding_to_rtl ) insert_insn_on_edge ( seq , single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ) ; else emit_insn ( seq ) ; } } } } </s>

Record that the current function needs a PIC register . Initialize cfun- > machine- > pic_reg if we have not already done so .


<s> static int untangle_mova ( int * num_mova , rtx_insn * * first_mova , rtx_insn * new_mova ) { int n_addr = 0 ; int f_target , n_target = 0 ; if ( optimize ) { if ( INSN_ADDRESSES_SIZE ( ) <= ( unsigned ) INSN_UID ( new_mova ) ) return - 1 ; n_addr = INSN_ADDRESSES ( INSN_UID ( new_mova ) ) ; n_target = INSN_ADDRESSES ( INSN_UID ( XEXP ( MOVA_LABELREF ( new_mova ) , 0 ) ) ) ; if ( n_addr > n_target || n_addr + 1022 < n_target ) { fixup_mova ( new_mova ) ; return 1 ; } } if ( ! ( * num_mova ) ++ ) { * first_mova = new_mova ; return 2 ; } if ( ! optimize || ( ( f_target = INSN_ADDRESSES ( INSN_UID ( XEXP ( MOVA_LABELREF ( * first_mova ) , 0 ) ) ) ) >= n_target ) ) return - 1 ; ( * num_mova ) -- ; if ( f_target - INSN_ADDRESSES ( INSN_UID ( * first_mova ) ) > n_target - n_addr ) { fixup_mova ( * first_mova ) ; return 0 ; } else { fixup_mova ( new_mova ) ; return 1 ; } } </s>

NEW_MOVA is a mova we 've just encountered while scanning forward . Update * num_mova , and check if the new mova is not nested within the first one . return 0 if * first_mova was replaced , 1 if new_mova was replaced , 2 if new_mova has been assigned to * first_mova , -1 otherwise ..


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) ) ) return 0 ; OpNum = 1 ; const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isUndef ( ) && TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { return UndefRegClearance ; } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


"Lowering returned the wrong number of results!"

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> static bool tryAddingSymbolicOperand ( uint64_t Address , int32_t Value , bool isBranch , uint64_t InstSize , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , ( uint32_t ) Value , Address , isBranch , 0 , InstSize ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static rtx mips_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx base , addr ; HOST_WIDE_INT offset ; if ( mips_tls_symbol_p ( x ) ) return mips_legitimize_tls_address ( x ) ; if ( mips_split_symbol ( NULL , x , mode , & addr ) ) return mips_force_address ( addr , mode ) ; mips_split_plus ( x , & base , & offset ) ; if ( offset != 0 ) { if ( ! mips_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = mips_add_offset ( NULL , base , offset ) ; return mips_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If * XLOC can be legitimized in a way that the generic machinery might not expect , put the new address in * XLOC and return true . MODE is the mode of the memory being accessed .


<s> static bool flow_dependent_p ( rtx_insn * insn , rtx_insn * dep_insn ) { rtx tmp = PATTERN ( insn ) ; note_stores ( dep_insn , flow_dependent_p_1 , & tmp ) ; return tmp == NULL_RTX ; } </s>

Check if INSN is flow-dependent on DEP_INSN . Can also be used to check if DEP_INSN is anti-flow dependent on INSN .


<s> bool MipsBranchExpansion :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const MipsInstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; bool loadDelaySlotChanged = handleLoadDelaySlot ( ) ; bool Changed = longBranchChanged || forbiddenSlotChanged || fpuDelaySlotChanged || loadDelaySlotChanged ; while ( forbiddenSlotChanged ) { longBranchChanged = handlePossibleLongBranch ( ) ; fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; loadDelaySlotChanged = handleLoadDelaySlot ( ) ; if ( ! longBranchChanged && ! fpuDelaySlotChanged && ! loadDelaySlotChanged ) break ; forbiddenSlotChanged = handleForbiddenSlot ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Promote Constant"
;
}
</s>


<s> bool IA64TargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createIA64DAGToDAGInstructionSelector ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool SystemZInstrInfo :: isStackSlotCopy ( const MachineInstr & MI , int & DestFrameIndex , int & SrcFrameIndex ) const { const MachineFrameInfo & MFI = MI . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; if ( MI . getOpcode ( ) != SystemZ :: MVC || ! MI . getOperand ( 0 ) . isFI ( ) || MI . getOperand ( 1 ) . getImm ( ) != 0 || ! MI . getOperand ( 3 ) . isFI ( ) || MI . getOperand ( 4 ) . getImm ( ) != 0 ) return false ; int64_t Length = MI . getOperand ( 2 ) . getImm ( ) ; unsigned FI1 = MI . getOperand ( 0 ) . getIndex ( ) ; unsigned FI2 = MI . getOperand ( 3 ) . getIndex ( ) ; if ( MFI . getObjectSize ( FI1 ) != Length || MFI . getObjectSize ( FI2 ) != Length ) return false ; DestFrameIndex = FI1 ; SrcFrameIndex = FI2 ; return true ; } </s>

Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect .


<s> const CallLowering * AArch64Subtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s> int aarch64_fpconst_pow_of_2 ( rtx x ) { const REAL_VALUE_TYPE * r ; if ( ! CONST_DOUBLE_P ( x ) ) return - 1 ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_NEGATIVE ( * r ) || REAL_VALUE_ISNAN ( * r ) || REAL_VALUE_ISINF ( * r ) || ! real_isinteger ( r , DFmode ) ) return - 1 ; return exact_log2 ( real_to_integer ( r ) ) ; } </s>

If X is a positive CONST_DOUBLE with a value that is a power of 2 return the log2 of that value . Otherwise return -1 .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy , MaybeAlign Alignment ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && cast < VectorType > ( DataTy ) -> getNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s> void FISCPassConfig :: addPreEmitPass ( ) { addPass ( createFISCDelaySlotFillerPass ( getFISCTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align Alignment , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == MVT :: i8 || Ty == MVT :: i16 || Ty == MVT :: i32 ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == MVT :: f64 || Ty == MVT :: v2f64 ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( ( Ty == MVT :: v16i1 || Ty == MVT :: v8i1 || Ty == MVT :: v4i1 || Ty == MVT :: v2i1 ) ) { if ( Fast ) * Fast = true ; return true ; } if ( ( Ty == MVT :: v4i8 || Ty == MVT :: v8i8 || Ty == MVT :: v4i16 ) && Alignment >= VT . getScalarSizeInBits ( ) / 8 ) { if ( Fast ) * Fast = true ; return true ; } if ( Ty == MVT :: v16i8 || Ty == MVT :: v8i16 || Ty == MVT :: v8f16 || Ty == MVT :: v4i32 || Ty == MVT :: v4f32 || Ty == MVT :: v2i64 || Ty == MVT :: v2f64 ) { if ( Fast ) * Fast = true ; return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
virtual
void
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
Imm
.
Val
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
Mem
.
Off
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_PhysRegister
:
OS
<<
"PhysReg<"
<<
PhysReg
.
Num
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
AArch64MCExpr
::
VariantKind
RefKind
=
static_cast
<
AArch64MCExpr
::
VariantKind
>
(
Target
.
getRefKind
(
)
)
;
if
(
AArch64MCExpr
::
getSymbolLoc
(
RefKind
)
==
AArch64MCExpr
::
VK_SABS
)
{
if
(
SignedValue
<
0
)
Data
[
Offset
+
3
]
&=
~
(
1
<<
6
)
;
else
Data
[
Offset
+
3
]
|=
(
1
<<
6
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool ARM64PassConfig :: addInstSelector ( ) { addPass ( createARM64ISelDag ( getARM64TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getSubtarget < ARM64Subtarget > ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARM64CleanupLocalDynamicTLSPass ( ) ) ; return false ; } </s>


<s> rtx ix86_replace_reg_with_reg ( rtx x , rtx from , rtx to ) { gcc_checking_assert ( REG_P ( from ) && REG_P ( to ) && GET_MODE ( from ) == GET_MODE ( to ) ) ; if ( ! reg_overlap_mentioned_p ( from , x ) ) return x ; rtx ret = copy_rtx ( x ) ; subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , & ret , NONCONST ) { rtx * loc = * iter ; x = * loc ; if ( REG_P ( x ) && REGNO ( x ) == REGNO ( from ) ) { if ( x == from ) * loc = to ; else { gcc_checking_assert ( REG_NREGS ( x ) == 1 ) ; * loc = gen_rtx_REG ( GET_MODE ( x ) , REGNO ( to ) ) ; } } } return ret ; } </s>

Replace all occurrences of REG FROM with REG TO in X , including occurrences with different modes .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , SlotSize ) ; X86FI -> setHasSEHFramePtrSave ( true ) ; X86FI -> setSEHFramePtrSaveIndex ( FI ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == 64 ) { unsigned int nbits = GET_MODE_NUNITS ( cmp_ops_mode ) ; cmp_mode = int_mode_for_size ( nbits , 0 ) . require ( ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; int ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case E_V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case E_V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case E_V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case E_V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


<s> static const struct mips_cpu_info * mips_cpu_info_from_opt ( int opt ) { switch ( opt ) { case MIPS_ARCH_OPTION_FROM_ABI : return mips_cpu_info_from_isa ( ABI_NEEDS_32BIT_REGS ? 1 : ABI_NEEDS_64BIT_REGS ? 3 : ( TARGET_64BIT ? 3 : 1 ) ) ; case MIPS_ARCH_OPTION_NATIVE : gcc_unreachable ( ) ; default : return & mips_cpu_info_table [ opt ] ; } } </s>

Return a mips_cpu_info entry determined by an option valued OPT .


<s> MipsSubtarget & MipsSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = MIPS_MC :: selectMipsCPU ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( InMips16Mode && ! TM . Options . UseSoftFloat ) InMips16HardFloat = true ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

Mips Mips Mips MIPS_MC::selectMipsCPU Mips Mips


<s> int direct_return ( void ) { if ( reload_completed ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( info -> first_gp_reg_save == 32 && info -> first_fp_reg_save == 64 && info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 && ! info -> lr_save_p && ! info -> cr_save_p && info -> vrsave_mask == 0 && ! info -> push_p ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> static void aarch64_set_handled_components ( sbitmap components ) { for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( bitmap_bit_p ( components , regno ) ) cfun -> machine -> reg_is_wrapped_separately [ regno ] = true ; } </s>


<s> const Cpu0RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? ( const TargetRegisterClass * ) & X86 :: GR64RegClass : ( const TargetRegisterClass * ) & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static void aarch64_init_rng_builtins ( void ) { tree unsigned_ptr_type = build_pointer_type ( unsigned_intDI_type_node ) ; tree ftype = build_function_type_list ( integer_type_node , unsigned_ptr_type , NULL ) ; aarch64_builtin_decls [ AARCH64_BUILTIN_RNG_RNDR ] = aarch64_general_add_builtin ( "__builtin_aarch64_rndr" , ftype , AARCH64_BUILTIN_RNG_RNDR ) ; aarch64_builtin_decls [ AARCH64_BUILTIN_RNG_RNDRRS ] = aarch64_general_add_builtin ( "__builtin_aarch64_rndrrs" , ftype , AARCH64_BUILTIN_RNG_RNDRRS ) ; } </s>

Add builtins for Random Number instructions .


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ! BYTES_BIG_ENDIAN && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implements target hook array_mode_supported_p .


<s> int ARMAsmParser :: tryParseRegister ( ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r13" , ARM :: SP ) . Case ( "r14" , ARM :: LR ) . Case ( "r15" , ARM :: PC ) . Case ( "ip" , ARM :: R12 ) . Case ( "a1" , ARM :: R0 ) . Case ( "a2" , ARM :: R1 ) . Case ( "a3" , ARM :: R2 ) . Case ( "a4" , ARM :: R3 ) . Case ( "v1" , ARM :: R4 ) . Case ( "v2" , ARM :: R5 ) . Case ( "v3" , ARM :: R6 ) . Case ( "v4" , ARM :: R7 ) . Case ( "v5" , ARM :: R8 ) . Case ( "v6" , ARM :: R9 ) . Case ( "v7" , ARM :: R10 ) . Case ( "v8" , ARM :: R11 ) . Case ( "sb" , ARM :: R9 ) . Case ( "sl" , ARM :: R10 ) . Case ( "fp" , ARM :: R11 ) . Default ( 0 ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - 1 ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; } if ( hasD16 ( ) && RegNum >= ARM :: D16 && RegNum <= ARM :: D31 ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> int ARM64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> const MCPhysReg * MINA32RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return nullptr ; } </s>


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool MipsPreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; MipsPreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> Optional < MCFixupKind > AArch64AsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! TheTriple . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_AARCH64_NONE ) . Case ( "BFD_RELOC_16" , ELF :: R_AARCH64_ABS16 ) . Case ( "BFD_RELOC_32" , ELF :: R_AARCH64_ABS32 ) . Case ( "BFD_RELOC_64" , ELF :: R_AARCH64_ABS64 ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static bool chain_contains_only_swaps ( swap_web_entry * insn_entry , struct df_link * link , enum chain_purpose purpose ) { if ( ! link ) return false ; for ( ; link ; link = link -> next ) { if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( DF_REF_REG ( link -> ref ) ) ) ) continue ; if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx reached_insn = DF_REF_INSN ( link -> ref ) ; unsigned uid = INSN_UID ( reached_insn ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( reached_insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load || insn_entry [ uid ] . is_store ) return false ; if ( purpose == FOR_LOADS ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( use ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_def_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || ! insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } else if ( purpose == FOR_STORES ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( def ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_use_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_use_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } } return true ; } </s>

Return true if the UD or DU chain headed by LINK is non-empty , and every entry on the chain references an insn that is a register swap . Furthermore , if PURPOSE is FOR_LOADS , each such register swap must have only permuting loads as reaching defs . If PURPOSE is FOR_STORES , each such register swap must have only register swaps or permuting stores as reached uses .


<s> static bool ix86_nopic_noplt_attribute_p ( rtx call_op ) { if ( flag_pic || ix86_cmodel == CM_LARGE || ! TARGET_64BIT || TARGET_MACHO || TARGET_SEH || TARGET_PECOFF || SYMBOL_REF_LOCAL_P ( call_op ) ) return false ; tree symbol_decl = SYMBOL_REF_DECL ( call_op ) ; if ( ! flag_plt || ( symbol_decl != NULL_TREE && lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( symbol_decl ) ) ) ) return true ; return false ; } </s>

Return true if the function being called was marked with attribute `` noplt '' or using -fno-plt and we are compiling for non-PIC and x86_64 . We need to handle the non-PIC case in the backend because there is no easy interface for the front-end to force non-PLT calls to use the GOT . This is currently used only with 64-bit ELF targets to call the function marked `` noplt '' indirectly .


<s> void MipsAsmPrinter :: emitFrameDirective ( MachineFunction & MF ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; O << "\t.frame\t" << '$' << LowercaseString ( RI . get ( stackReg ) . AsmName ) << ',' << stackSize << ',' << '$' << LowercaseString ( RI . get ( returnReg ) . AsmName ) << '\n' ; } </s>


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlignment ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> int sh_dwarf_calling_convention ( tree func ) { if ( sh_attr_renesas_p ( func ) ) return DW_CC_GNU_renesas_sh ; return DW_CC_normal ; } </s>

Implements target hook dwarf_calling_convention . Return an enum of dwarf_calling_convention .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( Subtarget . getFrameLowering ( ) -> has128ByteRedZone ( MF ) ) { const X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( ! X86FI || X86FI -> getUsesRedZone ( ) ) return false ; } if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> bool aarch64_sve_arith_immediate_p ( rtx x , bool negate_p ) { rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER ( GET_MODE ( x ) ) ) ; if ( val & 0xff ) return IN_RANGE ( val , 0 , 0xff ) ; return IN_RANGE ( val , 0 , 0xff00 ) ; } </s>

Return true if X is a valid immediate for the SVE ADD and SUB instructions . Negate X first if NEGATE_P is true .


<s> static bool r10k_safe_mem_expr_p ( tree expr , unsigned HOST_WIDE_INT offset ) { poly_int64 bitoffset , bitsize ; tree inner , var_offset ; machine_mode mode ; int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi ( DECL_SIZE_UNIT ( inner ) ) ; } </s>

Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is an in-range access to an automatic variable , or to an object with a link-time-constant address .


<s> static section * mips_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( mips_rtx_constant_in_small_data_p ( mode ) ) return get_named_section ( NULL , ".sdata" , 0 ) ; return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Choose the section to use for the constant rtx expression X that has mode MODE .


<s>
void
fma_root_node
::
dump_info
(
fma_forest
*
forest
)
{
gcc_assert
(
dump_file
)
;
if
(
this
==
forest
->
get_roots
(
)
->
front
(
)
)
fprintf
(
dump_file
,
"Instruction(s) at root of forest #%d:"
,
forest
->
get_id
(
)
)
;
fprintf
(
dump_file
,
" %d"
,
INSN_UID
(
this
->
m_insn
)
)
;
if
(
this
==
forest
->
get_roots
(
)
->
back
(
)
)
fprintf
(
dump_file
,
"\n"
)
;
}
</s>

Dump information about the roots of forest FOREST .

aarch64
"Instruction(s) at root of forest #%d:"
" %d"
"\n"


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; const Function & F = MF . getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: Mono ) markSuperRegs ( Reserved , AArch64 :: W15 ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , AArch64 :: W18 ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void x86_initialize_trampoline ( rtx tramp , rtx fnaddr , rtx cxt ) { if ( ! TARGET_64BIT ) { rtx disp = expand_binop ( SImode , sub_optab , fnaddr , plus_constant ( tramp , 10 ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; emit_move_insn ( gen_rtx_MEM ( QImode , tramp ) , gen_int_mode ( 0xb9 , QImode ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 1 ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( QImode , plus_constant ( tramp , 5 ) ) , gen_int_mode ( 0xe9 , QImode ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 6 ) ) , disp ) ; } else { int offset = 0 ; if ( x86_64_zext_immediate_operand ( fnaddr , VOIDmode ) ) { fnaddr = copy_to_mode_reg ( DImode , fnaddr ) ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , offset ) ) , gen_int_mode ( 0xbb41 , HImode ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , offset + 2 ) ) , gen_lowpart ( SImode , fnaddr ) ) ; offset += 6 ; } else { emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , offset ) ) , gen_int_mode ( 0xbb49 , HImode ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( tramp , offset + 2 ) ) , fnaddr ) ; offset += 10 ; } emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , offset ) ) , gen_int_mode ( 0xba49 , HImode ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( tramp , offset + 2 ) ) , cxt ) ; offset += 10 ; emit_move_insn ( gen_rtx_MEM ( HImode , plus_constant ( tramp , offset ) ) , gen_int_mode ( 0xff49 , HImode ) ) ; emit_move_insn ( gen_rtx_MEM ( QImode , plus_constant ( tramp , offset + 2 ) ) , gen_int_mode ( 0xe3 , QImode ) ) ; offset += 3 ; gcc_assert ( offset <= TRAMPOLINE_SIZE ) ; } emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , tramp , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> bool toc_hasher :: equal ( toc_hash_struct * h1 , toc_hash_struct * h2 ) { rtx r1 = h1 -> key ; rtx r2 = h2 -> key ; if ( h1 -> key_mode != h2 -> key_mode ) return 0 ; return rtx_equal_p ( r1 , r2 ) ; } </s>


<s> void rs6000_set_handled_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> fpr_is_wrapped_separately [ i - 32 ] = true ; if ( bitmap_bit_p ( components , 0 ) ) cfun -> machine -> lr_is_wrapped_separately = true ; if ( bitmap_bit_p ( components , 2 ) ) cfun -> machine -> toc_is_wrapped_separately = true ; } </s>


"Can only put epilog before 'retl' instruction!"


<s>
SDValue
KudeyarTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
Kudeyar_INTR
:
if
(
Ins
.
empty
(
)
)
return
Chain
;
report_fatal_error
(
"ISRs cannot have arguments"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

Kudeyar
Kudeyar
ISD::InputArg
"Unsupported calling convention"
Kudeyar
"ISRs cannot have arguments"


<s> bool DLXAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * B = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( B -> getTerminator ( ) ) ) return false ; if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) { } return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void MipsELFStreamer :: emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) { MCELFStreamer :: emitValueImpl ( Value , Size , Loc ) ; Labels . clear ( ) ; } </s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .


<s> std :: pair < unsigned , const TargetRegisterClass * > DLXTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void emit_cfa_restores ( rtx cfa_restores ) { rtx_insn * insn = get_last_insn ( ) ; rtx * loc = & REG_NOTES ( insn ) ; while ( * loc ) loc = & XEXP ( * loc , 1 ) ; * loc = cfa_restores ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Append CFA_RESTORES to any existing REG_NOTES on the last insn .


<s> bool arm_valid_symbolic_address_p ( rtx addr ) { rtx xop0 , xop1 = NULL_RTX ; rtx tmp = addr ; if ( target_word_relocations ) return false ; if ( SYMBOL_REF_P ( tmp ) || LABEL_REF_P ( tmp ) ) return true ; if ( GET_CODE ( addr ) == CONST ) tmp = XEXP ( addr , 0 ) ; if ( GET_CODE ( tmp ) == PLUS ) { xop0 = XEXP ( tmp , 0 ) ; xop1 = XEXP ( tmp , 1 ) ; if ( GET_CODE ( xop0 ) == SYMBOL_REF && CONST_INT_P ( xop1 ) ) { if ( TARGET_THUMB1 && ! TARGET_HAVE_MOVT ) return IN_RANGE ( INTVAL ( xop1 ) , 0 , 0xff ) ; else return IN_RANGE ( INTVAL ( xop1 ) , - 0x8000 , 0x7fff ) ; } } return false ; } </s>

Returns true if the pattern is a valid symbolic address , which is either a symbol_ref or ( symbol_ref + addend ) . According to the ARM ELF ABI , the initial addend of REL-type relocations processing MOVW and MOVT instructions is formed by interpreting the 16-bit literal field of the instruction as a 16-bit signed value in the range -32768 < = A < 32768 . In Thumb-1 mode , we use upper/lower relocations which have an 8-bit unsigned range of 0 < = A < 256 as described in the AAELF32 relocation handling documentation : REL-type relocations are encoded as unsigned in this case .


<s>
SDNode
*
ARMTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallSDNode
*
TheCall
,
unsigned
CallingConv
,
SelectionDAG
&
DAG
)
{
DebugLoc
dl
=
TheCall
->
getDebugLoc
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
isVarArg
=
TheCall
->
isVarArg
(
)
;
CCState
CCInfo
(
CallingConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
)
;
CCInfo
.
AnalyzeCallResult
(
TheCall
,
RetCC_ARM
)
;
SmallVector
<
SDValue
,
8
>
ResultVals
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
VA
=
RVLocs
[
i
]
;
SDValue
Val
;
if
(
VA
.
needsCustom
(
)
)
{
SDValue
Lo
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i32
,
InFlag
)
;
Chain
=
Lo
.
getValue
(
1
)
;
InFlag
=
Lo
.
getValue
(
2
)
;
VA
=
RVLocs
[
++
i
]
;
SDValue
Hi
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i32
,
InFlag
)
;
Chain
=
Hi
.
getValue
(
1
)
;
InFlag
=
Hi
.
getValue
(
2
)
;
Val
=
DAG
.
getNode
(
ARMISD
::
FMDRR
,
dl
,
MVT
::
f64
,
Lo
,
Hi
)
;
}
else
{
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
assert
(
0
&&
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BIT_CONVERT
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
ResultVals
.
push_back
(
Val
)
;
}
ResultVals
.
push_back
(
Chain
)
;
return
DAG
.
getNode
(
ISD
::
MERGE_VALUES
,
dl
,
TheCall
->
getVTList
(
)
,
&
ResultVals
[
0
]
,
ResultVals
.
size
(
)
)
.
getNode
(
)
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> rtx sparc_legitimize_reload_address ( rtx x , machine_mode mode , int opnum , int type , int ind_levels ATTRIBUTE_UNUSED , int * win ) { if ( CONSTANT_P ( x ) && ( mode != TFmode || TARGET_ARCH64 ) && GET_MODE ( x ) == SImode && GET_CODE ( x ) != LO_SUM && GET_CODE ( x ) != HIGH && sparc_code_model <= CM_MEDLOW && ! ( flag_pic && ( symbolic_operand ( x , Pmode ) || pic_address_needs_scratch ( x ) ) ) ) { x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_HIGH ( GET_MODE ( x ) , x ) , x ) ; push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; * win = 1 ; return x ; } if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , 0 ) ) == HIGH ) { push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; * win = 1 ; return x ; } * win = 0 ; return x ; } </s>

SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS . Returns a value to replace the input X , or the original X if no replacement is called for . The output parameter * WIN is 1 if the calling macro should goto WIN , 0 if it should not . For SPARC , we wish to handle addresses by splitting them into HIGH+LO_SUM pairs , retaining the LO_SUM in the memory reference . This cuts the number of extra insns by one . Do nothing when generating PIC code and the address is a symbolic operand or requires a scratch register .


"// rs6000_variable_issue (more = %d) = %d\n"

Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle . Branches have their own dispatch slot which does not count against the GCC issue rate , but it changes the program flow so there are no other instructions to issue in this cycle .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void or1k_profile_hook ( void ) { rtx a1 = gen_rtx_REG ( Pmode , 3 ) ; rtx ra = get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; rtx fun = gen_rtx_SYMBOL_REF ( Pmode , "_mcount" ) ; cfun -> machine -> set_mcount_arg_insn = emit_move_insn ( a1 , ra ) ; emit_library_call ( fun , LCT_NORMAL , VOIDmode , a1 , Pmode ) ; } </s>

Worker for PROFILE_HOOK . The OpenRISC profile hook uses the link register which will get clobbered by the GOT setup RTX . This sets up a placeholder to allow injecting of the GOT setup RTX to avoid clobbering .


<s> unsigned X86TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( ( Idx == 1 ) && Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool enablePostRAScheduler ( ) const override { return isCortexA53 ( ) || isCortexA57 ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> bool ARMTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { int64_t AbsImm = std :: abs ( Imm ) ; if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( AbsImm ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( AbsImm ) != - 1 ; return AbsImm >= 0 && AbsImm <= 255 ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
bool
NeedSizeDir
=
false
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
NeedSizeDir
=
NeedSizeDir
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> Register getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void PPCELFStreamer :: emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { PPCMCCodeEmitter * Emitter = static_cast < PPCMCCodeEmitter * > ( getAssembler ( ) . getEmitterPtr ( ) ) ; if ( ! Emitter -> isPrefixedInstruction ( Inst ) ) { MCELFStreamer :: emitInstruction ( Inst , STI ) ; return ; } emitCodeAlignment ( 64 , 4 ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; MCFragment * InstructionFragment = getCurrentFragment ( ) ; SMLoc InstLoc = Inst . getLoc ( ) ; if ( LastLabel && ! LastLabel -> isUnset ( ) && LastLabelLoc . isValid ( ) && InstLoc . isValid ( ) ) { const SourceMgr * SourceManager = getContext ( ) . getSourceManager ( ) ; unsigned InstLine = SourceManager -> FindLineNumber ( InstLoc ) ; unsigned LabelLine = SourceManager -> FindLineNumber ( LastLabelLoc ) ; if ( InstLine == LabelLine ) { AssignFragment ( LastLabel , InstructionFragment ) ; LastLabel -> setOffset ( 0 ) ; } } } </s>

Targets should implement this to emit instructions .


<s>
void
SystemZRegisterInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
const
TargetFrameInfo
&
TFI
=
*
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SystemZMachineFunctionInfo
*
SystemZMFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
(
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
StackSize
-=
SystemZMFI
->
getCalleeSavedFrameSize
(
)
;
uint64_t
NumBytes
=
StackSize
TFI
.
getOffsetOfLocalArea
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mr
||
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mrm
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
StackSize
||
MFI
->
hasCalls
(
)
)
{
assert
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
SystemZ
::
R15D
)
&&
"Invalid stack frame calculation!"
)
;
emitSPUpdate
(
MBB
,
MBBI
,
(
int64_t
)
NumBytes
,
TII
)
;
}
if
(
hasFP
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
SystemZ
::
MOV64rr
)
,
SystemZ
::
R11D
)
.
addReg
(
SystemZ
::
R15D
)
;
for
(
MachineFunction
::
iterator
I
=
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
SystemZ
::
R11D
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static bool valid_bL_core_p ( unsigned int * core , unsigned int bL_core ) { return AARCH64_BIG_LITTLE ( core [ 0 ] , core [ 1 ] ) == bL_core || AARCH64_BIG_LITTLE ( core [ 1 ] , core [ 0 ] ) == bL_core ; } </s>

Check wether the CORE array is the same as the big.LITTLE BL_CORE . For an example CORE= { 0xd08 , 0xd03 } and BL_CORE=AARCH64_BIG_LITTLE ( 0xd08 , 0xd03 ) will return true .


"Only half, single and double precision supported"

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> bool FISCInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case FISC :: MOVi64 : { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; const unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; const bool DstIsDead = MI -> getOperand ( 0 ) . isDead ( ) ; const MachineOperand & MO = MI -> getOperand ( 1 ) ; auto Q1 = BuildMI ( MBB , MI , DL , get ( FISC :: MOVZ ) , DstReg ) ; auto Q2 = BuildMI ( MBB , MI , DL , get ( FISC :: MOVK ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; auto Q3 = BuildMI ( MBB , MI , DL , get ( FISC :: MOVK ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; auto Q4 = BuildMI ( MBB , MI , DL , get ( FISC :: MOVK ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const uint64_t Imm = MO . getImm ( ) ; Q1 = Q1 . addImm ( Imm & 0xffff ) . addImm ( 0 ) ; Q2 = Q2 . addImm ( ( Imm >> 16 ) & 0xffff ) . addImm ( 1 ) ; Q3 = Q3 . addImm ( ( Imm >> 32 ) & 0xffff ) . addImm ( 2 ) ; Q4 = Q4 . addImm ( ( Imm >> 48 ) & 0xffff ) . addImm ( 3 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; Q1 = Q1 . addGlobalAddress ( GV , MO . getOffset ( ) , FISCII :: MO_Q1 ) . addImm ( 0 ) ; Q2 = Q2 . addGlobalAddress ( GV , MO . getOffset ( ) , FISCII :: MO_Q2 ) . addImm ( 1 ) ; Q3 = Q3 . addGlobalAddress ( GV , MO . getOffset ( ) , FISCII :: MO_Q3 ) . addImm ( 2 ) ; Q4 = Q4 . addGlobalAddress ( GV , MO . getOffset ( ) , FISCII :: MO_Q4 ) . addImm ( 3 ) ; } MBB . erase ( MI ) ; return true ; } } } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static void arm_initialize_isa ( sbitmap isa , const enum isa_feature * isa_bits ) { bitmap_clear ( isa ) ; while ( * isa_bits != isa_nobit ) bitmap_set_bit ( isa , * ( isa_bits ++ ) ) ; } </s>

Convert a static initializer array of feature bits to sbitmap representation .


<s>
SDValue
OR1KTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> int64_t getFrameAdjustment ( const MachineInstr & I ) const { assert ( isFrameInstr ( I ) ) ; return I . getOperand ( 1 ) . getImm ( ) ; } </s>

Returns the stack pointer adjustment that happens inside the frame setup .. destroy sequence ( e.g .


<s>
void
CSKYInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
if
(
CSKY
::
GPRRegClass
.
contains
(
SrcReg
)
&&
CSKY
::
CARRYRegClass
.
contains
(
DestReg
)
)
{
if
(
STI
.
hasE2
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
BTSTI32
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
else
{
assert
(
SrcReg
<
CSKY
::
R8
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
BTSTI16
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
return
;
}
if
(
CSKY
::
CARRYRegClass
.
contains
(
SrcReg
)
&&
CSKY
::
GPRRegClass
.
contains
(
DestReg
)
)
{
if
(
STI
.
hasE2
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
MVC32
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
assert
(
DestReg
<
CSKY
::
R16
)
;
assert
(
DestReg
<
CSKY
::
R8
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
MOVI16
)
,
DestReg
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
ADDC16
)
)
.
addReg
(
DestReg
,
RegState
::
Define
)
.
addReg
(
SrcReg
,
RegState
::
Define
)
.
addReg
(
DestReg
,
getKillRegState
(
true
)
)
.
addReg
(
DestReg
,
getKillRegState
(
true
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
true
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CSKY
::
BTSTI16
)
)
.
addReg
(
SrcReg
,
RegState
::
Define
|
getDeadRegState
(
KillSrc
)
)
.
addReg
(
DestReg
)
.
addImm
(
0
)
;
}
return
;
}
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opcode
=
CSKY
::
MOV32
;
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"src = "
<<
SrcReg
<<
", dst = "
<<
DestReg
)
;
LLVM_DEBUG
(
I
->
dump
(
)
)
;
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool ix86_expand_vec_shift_qihi_constant ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { machine_mode qimode , himode ; HOST_WIDE_INT and_constant , xor_constant ; HOST_WIDE_INT shift_amount ; rtx vec_const_and , vec_const_xor ; rtx tmp , op1_subreg ; rtx ( * gen_shift ) ( rtx , rtx , rtx ) ; rtx ( * gen_and ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor ) ( rtx , rtx , rtx ) ; rtx ( * gen_sub ) ( rtx , rtx , rtx ) ; if ( ! CONST_INT_P ( op2 ) ) return false ; qimode = GET_MODE ( dest ) ; shift_amount = INTVAL ( op2 ) ; if ( shift_amount > 7 ) return false ; gcc_assert ( code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT ) ; xor_constant = 1 << ( 8 - shift_amount - 1 ) ; and_constant = ( code == ASHIFT ? 256 - ( 1 << shift_amount ) : ( 1 << ( 8 - shift_amount ) ) - 1 ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode = V16HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv16hi3 : ( code == ASHIFTRT ) ? gen_ashrv16hi3 : gen_lshrv16hi3 ) ; gen_and = gen_andv32qi3 ; gen_xor = gen_xorv32qi3 ; gen_sub = gen_subv32qi3 ; break ; case V64QImode : himode = V32HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv32hi3 : ( code == ASHIFTRT ) ? gen_ashrv32hi3 : gen_lshrv32hi3 ) ; gen_and = gen_andv64qi3 ; gen_xor = gen_xorv64qi3 ; gen_sub = gen_subv64qi3 ; break ; default : gcc_unreachable ( ) ; } tmp = gen_reg_rtx ( himode ) ; vec_const_and = gen_reg_rtx ( qimode ) ; op1_subreg = lowpart_subreg ( himode , op1 , qimode ) ; emit_insn ( gen_shift ( tmp , op1_subreg , op2 ) ) ; emit_move_insn ( dest , simplify_gen_subreg ( qimode , tmp , himode , 0 ) ) ; emit_move_insn ( vec_const_and , ix86_build_const_vector ( qimode , true , gen_int_mode ( and_constant , QImode ) ) ) ; emit_insn ( gen_and ( dest , dest , vec_const_and ) ) ; if ( code == ASHIFTRT ) { vec_const_xor = gen_reg_rtx ( qimode ) ; emit_move_insn ( vec_const_xor , ix86_build_const_vector ( qimode , true , gen_int_mode ( xor_constant , QImode ) ) ) ; emit_insn ( gen_xor ( dest , dest , vec_const_xor ) ) ; emit_insn ( gen_sub ( dest , dest , vec_const_xor ) ) ; } return true ; } </s>

Expand a vector operation shift by constant for a V * QImode in terms of the same operation on V * HImode . Return true if success .


<s> static inline int isa_base_compat_p ( const struct loongarch_isa * set1 , const struct loongarch_isa * set2 ) { switch ( set2 -> base ) { case ISA_BASE_LA64V100 : return ( set1 -> base == ISA_BASE_LA64V100 ) ; default : gcc_unreachable ( ) ; } } </s>


<s>
bool
MipsAsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getString
(
)
;
if
(
IDVal
==
".dword"
)
{
parseDataDirective
(
8
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".ent"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".end"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".frame"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".set"
)
{
return
parseDirectiveSet
(
)
;
}
if
(
IDVal
==
".fmask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".mask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".nan"
)
return
parseDirectiveNaN
(
)
;
if
(
IDVal
==
".gpword"
)
{
parseDirectiveGpWord
(
)
;
return
false
;
}
if
(
IDVal
==
".gpdword"
)
{
parseDirectiveGpDWord
(
)
;
return
false
;
}
if
(
IDVal
==
".word"
)
{
parseDataDirective
(
4
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".option"
)
return
parseDirectiveOption
(
)
;
if
(
IDVal
==
".abicalls"
)
{
getTargetStreamer
(
)
.
emitDirectiveAbiCalls
(
)
;
if
(
Parser
.
getTok
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Error
(
Parser
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in directive"
)
;
Parser
.
eatToEndOfStatement
(
)
;
}
return
false
;
}
if
(
IDVal
==
".cpsetup"
)
return
parseDirectiveCPSetup
(
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
auto
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
auto
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MIRBuilder
.
buildCopy
(
LLT
::
scalar
(
LocSize
)
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"
"Extensions not supported"


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x60000000 ) ; switch ( Count % 4 ) { default : break ; case 1 : OW -> Write8 ( 0 ) ; break ; case 2 : OW -> Write16 ( 0 ) ; break ; case 3 : OW -> Write16 ( 0 ) ; OW -> Write8 ( 0 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( isa < ScalableVectorType > ( Arg . getType ( ) ) ) return false ; if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .