<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
,
MCStreamer
&
Out
,
unsigned
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
unsigned
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
*
)
Operands
[
ErrorInfo
]
)
->
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>


<s> static int ck801_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ATTRIBUTE_UNUSED ) { enum rtx_code code = GET_CODE ( index ) ; if ( GET_MODE_SIZE ( mode ) >= 8 ) return ( code == CONST_INT && INTVAL ( index ) < CSKY_LD16_MAX_OFFSET ( SImode ) && INTVAL ( index ) >= 0 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( code == CONST_INT && GET_MODE_SIZE ( mode ) > 0 && INTVAL ( index ) <= CSKY_LD16_MAX_OFFSET ( mode ) && INTVAL ( index ) >= 0 ) return ( ( INTVAL ( index ) % GET_MODE_SIZE ( mode ) ) == 0 ) ; return 0 ; } </s>

Return nonzero if INDEX is valid for an address index operand . ck801 use 16 bits ld ck802 use 16 and 32 bits ld others use ld and ldr .


<s> void print_operand_address ( FILE * file , rtx x ) { if ( REG_P ( x ) ) fprintf ( file , "0(%s)" , reg_names [ REGNO ( x ) ] ) ; else if ( SYMBOL_REF_P ( x ) || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) { output_addr_const ( file , x ) ; if ( small_data_operand ( x , GET_MODE ( x ) ) ) fprintf ( file , "@%s(%s)" , SMALL_DATA_RELOC , reg_names [ SMALL_DATA_REG ] ) ; else gcc_assert ( ! TARGET_TOC ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && REG_P ( XEXP ( x , 1 ) ) ) { if ( REGNO ( XEXP ( x , 0 ) ) == 0 ) fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "%s,%s" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] , reg_names [ REGNO ( XEXP ( x , 1 ) ) ] ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC "(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { fprintf ( file , "lo16(" ) ; output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , ")(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , 0 ) ) && CONSTANT_P ( XEXP ( x , 1 ) ) ) { output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false , & tocrel_base_oac , & tocrel_offset_oac ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base_oac ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , "@l(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; else fprintf ( file , "(%s)" , reg_names [ REGNO ( XVECEXP ( tocrel_base_oac , 0 , 1 ) ) ] ) ; } else output_addr_const ( file , x ) ; } </s>

Print the operand address represented by the rtx addr


<s> bool SystemZMCAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const { Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ; return ( int16_t ) Value != ( int64_t ) Value ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"no expression found in stanza header.\n"

Parse one stanza of the input BIF file . linebuf already contains the first line to parse .


<s> static bool ia64_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( lookup_attribute ( "syscall_linkage" , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) return false ; return decl && ( * targetm . binds_local_p ) ( decl ) ; } </s>

True if it is OK to do sibling call optimization for the specified call expression EXP . DECL will be the called function , or NULL if this is an indirect call .


<s> static void mips_rewrite_small_data_1 ( rtx * loc , enum mips_symbol_context context ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { mips_rewrite_small_data_1 ( & XEXP ( * loc , 0 ) , SYMBOL_CONTEXT_MEM ) ; iter . skip_subrtxes ( ) ; } else if ( mips_rewrite_small_data_p ( * loc , context ) ) { * loc = gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , * loc ) ; iter . skip_subrtxes ( ) ; } else if ( GET_CODE ( * loc ) == LO_SUM ) iter . skip_subrtxes ( ) ; } } </s>

A for_each_rtx callback , used by mips_rewrite_small_data .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
SDValue
OpenRISCTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
doesNotRet
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

OpenRISC
OpenRISC
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; OptBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( & MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static short high_pressure ( enum machine_mode mode ) { if ( ( REG_N_SETS ( 0 ) - REG_N_DEATHS ( 0 ) ) >= R0_MAX_LIFE_REGIONS && REG_LIVE_LENGTH ( 0 ) >= R0_MAX_LIVE_LENGTH ) return 1 ; if ( mode == SFmode ) return ( CURR_REGMODE_PRESSURE ( SFmode ) > SFMODE_MAX_WEIGHT ) ; else return ( CURR_REGMODE_PRESSURE ( SImode ) > SIMODE_MAX_WEIGHT ) ; } </s>

Return true if the pressure is high for MODE .


<s> rtx thumb_legitimize_address ( rtx x , rtx orig_x , machine_mode mode ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && ( INTVAL ( XEXP ( x , 1 ) ) >= 32 * GET_MODE_SIZE ( mode ) || INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset >= 0 && offset < 256 + 31 * GET_MODE_SIZE ( mode ) ) { HOST_WIDE_INT delta ; if ( offset >= 256 ) delta = offset - ( 256 - GET_MODE_SIZE ( mode ) ) ; else if ( offset < 32 * GET_MODE_SIZE ( mode ) + 8 ) delta = 31 * GET_MODE_SIZE ( mode ) ; else delta = offset & ( ~ 31 * GET_MODE_SIZE ( mode ) ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - delta ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , delta ) ; } else if ( offset < 0 && offset > - 256 ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , 1 ) , SImode ) && ! s_register_operand ( XEXP ( x , 0 ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , 1 ) ) ; } if ( flag_pic ) { rtx new_x = legitimize_pic_address ( orig_x , mode , NULL_RTX , NULL_RTX , false ) ; if ( new_x != orig_x ) x = new_x ; } return x ; } </s>

Try machine-dependent ways of modifying an illegitimate Thumb address to be legitimate . If we find one , return the new , valid address .


<s>
static
bool
isReg
(
const
MCInst
&
MI
,
unsigned
OpNo
)
{
assert
(
MI
.
getOperand
(
OpNo
)
.
isReg
(
)
&&
"Register operand expected."
)
;
return
MI
.
getOperand
(
OpNo
)
.
getReg
(
)
==
R
;
}
</s>


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tRestore : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64Pseudo : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
bool
ARMConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
isThumb
4
:
8
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

ARM
ARM
4
8
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; Align Alignment = DL . getValueOrABITypeAlignment ( LI -> getAlign ( ) , LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s>
const
char
*
output_ubranch
(
rtx
dest
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
bool
v9_form
=
false
;
int
delta
;
char
*
p
;
delta
=
5000000
;
if
(
!
CROSSING_JUMP_P
(
insn
)
&&
INSN_ADDRESSES_SET_P
(
)
)
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
TARGET_V9
&&
delta
>=
260000
&&
delta
<
260000
)
v9_form
=
true
;
if
(
TARGET_CBCOND
)
{
bool
emit_nop
=
emit_cbcond_nop
(
insn
)
;
bool
far
=
false
;
const
char
*
rval
;
if
(
delta
<
500
||
delta
>
500
)
far
=
true
;
if
(
far
)
{
if
(
v9_form
)
rval
=
"ba,a,pt\t%%xcc, %l0"
;
else
rval
=
"b,a\t%l0"
;
}
else
{
if
(
emit_nop
)
rval
=
"cwbe\t%%g0, %%g0, %l0\n\tnop"
;
else
rval
=
"cwbe\t%%g0, %%g0, %l0"
;
}
return
rval
;
}
if
(
v9_form
)
strcpy
(
string
,
"ba%*,pt\t%%xcc, "
)
;
else
strcpy
(
string
,
"b%*\t"
)
;
p
=
strchr
(
string
,
'\0'
)
;
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
;
*
p
++
=
'%'
;
*
p
++
=
'('
;
*
p
=
'\0'
;
return
string
;
}
</s>

Output an unconditional branch to LABEL . INSN is the instruction .


"Suitable Machine Function for outlining must track liveness"

Optional target hook that returns true if MBB is safe to outline from , and returns any target-specific information in Flags .


<s> BitVector OR1KRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( OR1K :: R0 ) ; Reserved . set ( OR1K :: R1 ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( OR1K :: R2 ) ; Reserved . set ( OR1K :: R9 ) ; Reserved . set ( OR1K :: R10 ) ; Reserved . set ( OR1K :: R16 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( getBaseRegister ( ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool MipsCallEntry :: mayAlias ( const MachineFrameInfo * ) const { return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && ! EnableOldKNLABI ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static rtx ix86_expand_int_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { machine_mode cmpmode ; rtx tmp , flags ; if ( ( code == GTU || code == LEU ) && nonimmediate_operand ( op1 , VOIDmode ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( flags , tmp ) ) ; return gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; } </s>

Generate insn patterns to do an integer compare of OPERANDS .


<s>
const
MCPhysReg
*
LoongArchRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
auto
&
Subtarget
=
MF
->
getSubtarget
<
LoongArchSubtarget
>
(
)
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
LoongArchABI
::
ABI_ILP32S
:
case
LoongArchABI
::
ABI_LP64S
:
return
CSR_ILP32S_LP64S_SaveList
;
case
LoongArchABI
::
ABI_ILP32F
:
case
LoongArchABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_SaveList
;
case
LoongArchABI
::
ABI_ILP32D
:
case
LoongArchABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_SaveList
;
}
}
</s>


<s> static bool ix86_masked_all_ones ( unsigned HOST_WIDE_INT elems , tree arg_mask ) { if ( TREE_CODE ( arg_mask ) != INTEGER_CST ) return false ; unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW ( arg_mask ) ; if ( ( mask | ( HOST_WIDE_INT_M1U << elems ) ) != HOST_WIDE_INT_M1U ) return false ; return true ; } </s>

Return true if arg_mask is all ones , ELEMS is elements number of corresponding vector .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

Reset options between modes that the user has specified .


<s> static rtx loongarch_got_load_tls_gd ( rtx dest , rtx sym ) { return gen_got_load_tls_gd ( Pmode , dest , sym ) ; } </s>

Load an entry from the GOT for a TLS GD access .


<s> bool X86TTIImpl :: isLegalMaskedStore ( Type * DataType , Align Alignment ) { return isLegalMaskedLoad ( DataType , Alignment ) ; } </s>

Return true if the target supports masked store .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static bool sh_cannot_copy_insn_p ( rtx_insn * insn ) { rtx pat ; if ( ! reload_completed || ! flag_pic ) return false ; if ( ! NONJUMP_INSN_P ( insn ) ) return false ; if ( asm_noperands ( insn ) >= 0 ) return false ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) return false ; pat = SET_SRC ( pat ) ; if ( unspec_caller_rtx_p ( pat ) ) return true ; return false ; } </s>

Indicate that INSN can not be duplicated . This is true for insn that generates a unique label .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> static std :: unique_ptr < ARMOperand > CreateMem ( unsigned BaseRegNum , const MCConstantExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E , SMLoc AlignmentLoc = SMLoc ( ) ) { auto Op = std :: make_unique < ARMOperand > ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op ; } </s>


<s> static const char * ix86_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; switch ( TYPE_MODE ( type ) ) { case E_HFmode : return "DF16_" ; case E_TFmode : return "g" ; case E_XFmode : return "e" ; default : return NULL ; } } </s>

Return the mangling of TYPE if it is an extended fundamental type .


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> MachineBasicBlock :: iterator OR1KFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Darwin PPC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


A get_unnamed_decl callback , used for read-only sections . PTR points to the section string variable .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void mt_print_operand_address ( FILE * file , rtx addr ) { if ( GET_CODE ( addr ) == AND && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && INTVAL ( XEXP ( addr , 1 ) ) == - 3 ) mt_print_operand_simple_address ( file , XEXP ( addr , 0 ) ) ; else mt_print_operand_simple_address ( file , addr ) ; } </s>


<s> bool EvexToVexInstPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; ST = & MF . getSubtarget < X86Subtarget > ( ) ; if ( ! ST -> hasAVX512 ( ) ) return false ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) Changed |= CompressEvexToVexImpl ( MI ) ; } return Changed ; } </s>


<s> bool SystemZInstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & SystemZ :: FP64RegClass ) loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64rm : SystemZ :: MOV64rmm ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Define ) ; MIB . addReg ( ( RegInfo -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ) ) ; MIB . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> int fldi_ok ( void ) { return ! TARGET_SH4 || TARGET_FMOVD || reload_completed ; } </s>

For -m4 and -m4-single-only , mode switching is used . If we are compiling without -mfmovd , movsf_ie is n't taken into account for mode switching . We could check in machine_dependent_reorg for cases where we know we are in single precision mode , but there is interface to find that out during reload , so we must avoid choosing an fldi alternative during reload and thus failing to allocate a scratch register for the constant loading .


<s> bool arm_frame_pointer_required ( void ) { if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_ARM && TARGET_APCS_FRAME && ! crtl -> is_leaf ) return true ; if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= 0 ) return false ; if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += 32 * UNITS_PER_WORD ; if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) return true ; } else return true ; } return false ; } </s>


<s> bool MicroMipsSizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> inMicroMipsMode ( ) || ! Subtarget -> hasMips32r2 ( ) || Subtarget -> hasMips32r6 ( ) ) return false ; MipsII = static_cast < const MipsInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; bool Modified = false ; MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; for ( ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
mf
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
RDA
=
&
getAnalysis
<
ReachingDefAnalysis
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
*
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> int fp_mov_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long i ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , i ) ; return SPARC_SIMM13_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a single mov instruction .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
bool
IA64AsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
O
<<
"\n.ident \"LLVM-ia64\"\n\n"
<<
"\t.psr    lsb\n"
<<
"\t.radix  C\n"
<<
"\t.psr    abi64\n"
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

IA64
IA64
"\n.ident \"LLVM-ia64\"\n\n"
"\t.psr    lsb\n"
"\t.radix  C\n"
"\t.psr    abi64\n"


"alignment (%u) for %s exceeds maximum alignment "

Both the HP and GNU assemblers under HP-UX provide a .comm directive that does n't allow the alignment of global common storage to be directly specified . The SOM linker aligns common storage based on the rounded value of the NUM_BYTES parameter in the .comm directive . It 's not possible to use the .align directive as it does n't affect the alignment of the label associated with a .comm directive .


<s> void sparc_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( "SPARC64" ) ; else d_add_builtin_version ( "SPARC" ) ; if ( TARGET_V8PLUS ) d_add_builtin_version ( "SPARC_V8Plus" ) ; if ( TARGET_FPU ) { d_add_builtin_version ( "D_HardFloat" ) ; d_add_builtin_version ( "SPARC_HardFloat" ) ; } else { d_add_builtin_version ( "D_SoftFloat" ) ; d_add_builtin_version ( "SPARC_SoftFloat" ) ; } } </s>

Implement TARGET_D_CPU_VERSIONS for SPARC targets .


<s> int includes_lshift_p ( rtx shiftop , rtx andop ) { unsigned HOST_WIDE_INT shift_mask = ~ ( unsigned HOST_WIDE_INT ) 0 ; shift_mask <<= INTVAL ( shiftop ) ; return ( INTVAL ( andop ) & 0xffffffff & ~ shift_mask ) == 0 ; } </s>

Return 1 if ANDOP is a mask that has no bits on that are not in the mask required to convert the result of a rotate insn into a shift left insn of SHIFTOP bits . Both are known to be SImode CONST_INT .


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( NeedsWinCFI ) std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlign ( * RC ) ) ; int FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; if ( hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) && Reg == AArch64 :: FP ) { FrameIdx = MFI . CreateStackObject ( 8 , Alignment , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , const BranchProbability & Probability ) const { if ( ! TCycles || ! FCycles ) return false ; unsigned TUnpredCost = Probability . getNumerator ( ) * TCycles ; TUnpredCost /= Probability . getDenominator ( ) ; uint32_t Comp = Probability . getDenominator ( ) - Probability . getNumerator ( ) ; unsigned FUnpredCost = Comp * FCycles ; FUnpredCost /= Probability . getDenominator ( ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 ; UnpredCost += Subtarget . getMispredictionPenalty ( ) / 10 ; return ( TCycles + FCycles + TExtra + FExtra ) <= UnpredCost ; } </s>


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return LowerRETURNADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: ADD : return LowerADD ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::ADD


<s> void AArch64TargetStreamer :: emitInst ( uint32_t Inst ) { } </s>

Callback used to implement the .inst directive .


<s> static bool arm_slowmul_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = COSTS_N_INSNS ( 20 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 2 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; * total += rtx_cost ( XEXP ( x , 0 ) , code , 0 , speed ) ; return true ; } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; ; } } </s>

RTX costs for cores with a slow MUL implementation . Thumb-2 is not supported on any `` slowmul '' cores , so it can be ignored .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( Subtarget . hasVLX ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( Subtarget . hasAVX512 ( ) && getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; break ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512_0_15RegClassID : case X86 :: VR512RegClassID : if ( getRegSizeInBits ( * Super ) == getRegSizeInBits ( * RC ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) override { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"invalid name (\"%s\") in %<target(\"tune=\")%> pragma or attribute"

Handle the argument STR to the tune= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" || CPU == "pentium" || CPU == "pentium-mmx" || CPU == "geode" ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } const uint64_t OptimalCount = ( Count < 16 ) ? Count : 15 ; const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10 ; for ( uint64_t i = 0 , e = Prefixes ; i != e ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint64_t Rest = OptimalCount - Prefixes ; for ( uint64_t i = 0 , e = Rest ; i != e ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; for ( uint64_t i = OptimalCount , e = Count ; i != e ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void ix86_emit_swsqrtsf ( rtx res , rtx a , machine_mode mode , bool recip ) { rtx x0 , e0 , e1 , e2 , e3 , mthree , mhalf ; REAL_VALUE_TYPE r ; int unspec ; x0 = gen_reg_rtx ( mode ) ; e0 = gen_reg_rtx ( mode ) ; e1 = gen_reg_rtx ( mode ) ; e2 = gen_reg_rtx ( mode ) ; e3 = gen_reg_rtx ( mode ) ; real_from_integer ( & r , VOIDmode , - 3 , SIGNED ) ; mthree = CONST_DOUBLE_FROM_REAL_VALUE ( r , SFmode ) ; real_arithmetic ( & r , NEGATE_EXPR , & dconsthalf , NULL ) ; mhalf = CONST_DOUBLE_FROM_REAL_VALUE ( r , SFmode ) ; unspec = UNSPEC_RSQRT ; if ( VECTOR_MODE_P ( mode ) ) { mthree = ix86_build_const_vector ( mode , true , mthree ) ; mhalf = ix86_build_const_vector ( mode , true , mhalf ) ; if ( GET_MODE_SIZE ( mode ) == 64 ) unspec = UNSPEC_RSQRT14 ; } a = force_reg ( mode , a ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , a ) , unspec ) ) ) ; if ( ! recip ) { rtx zero , mask ; zero = gen_reg_rtx ( mode ) ; mask = gen_reg_rtx ( mode ) ; zero = force_reg ( mode , CONST0_RTX ( mode ) ) ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 64 ) { mask = gen_reg_rtx ( HImode ) ; emit_insn ( gen_avx512f_cmpv16sf3 ( mask , zero , a , GEN_INT ( 0x4 ) ) ) ; emit_insn ( gen_avx512f_blendmv16sf ( x0 , zero , x0 , mask ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , mask , gen_rtx_NE ( mode , zero , a ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_AND ( mode , x0 , mask ) ) ) ; } } emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MULT ( mode , x0 , a ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_MULT ( mode , e0 , x0 ) ) ) ; mthree = force_reg ( mode , mthree ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e2 , gen_rtx_PLUS ( mode , e1 , mthree ) ) ) ; mhalf = force_reg ( mode , mhalf ) ; if ( recip ) emit_insn ( gen_rtx_SET ( VOIDmode , e3 , gen_rtx_MULT ( mode , x0 , mhalf ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , e3 , gen_rtx_MULT ( mode , e0 , mhalf ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_MULT ( mode , e2 , e3 ) ) ) ; } </s>

Output code to perform a Newton-Rhapson approximation of a single precision floating point [ reciprocal ] square root .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static tree build_processor_model_struct ( void ) { const char * field_name [ ] = { "__cpu_vendor" , "__cpu_type" , "__cpu_subtype" , "__cpu_features" } ; tree field = NULL_TREE , field_chain = NULL_TREE ; int i ; tree type = make_node ( RECORD_TYPE ) ; for ( i = 0 ; i < 3 ; ++ i ) { field = build_decl ( UNKNOWN_LOCATION , FIELD_DECL , get_identifier ( field_name [ i ] ) , unsigned_type_node ) ; if ( field_chain != NULL_TREE ) DECL_CHAIN ( field ) = field_chain ; field_chain = field ; } field = build_decl ( UNKNOWN_LOCATION , FIELD_DECL , get_identifier ( field_name [ 3 ] ) , build_array_type ( unsigned_type_node , build_index_type ( size_one_node ) ) ) ; if ( field_chain != NULL_TREE ) DECL_CHAIN ( field ) = field_chain ; field_chain = field ; finish_builtin_struct ( type , "__processor_model" , field_chain , NULL_TREE ) ; return type ; } </s>

This builds the processor_model struct type defined in libgcc/config/i386/cpuinfo.c


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new PPCScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s>
static
SDValue
getTargetNode
(
SDValue
Op
,
SelectionDAG
&
DAG
,
unsigned
Flag
)
{
EVT
Ty
=
Op
.
getValueType
(
)
;
if
(
GlobalAddressSDNode
*
N
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
N
->
getGlobal
(
)
,
Op
.
getDebugLoc
(
)
,
Ty
,
0
,
Flag
)
;
if
(
ExternalSymbolSDNode
*
N
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
N
->
getSymbol
(
)
,
Ty
,
Flag
)
;
if
(
BlockAddressSDNode
*
N
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
N
->
getBlockAddress
(
)
,
Ty
,
0
,
Flag
)
;
if
(
JumpTableSDNode
*
N
=
dyn_cast
<
JumpTableSDNode
>
(
Op
)
)
return
DAG
.
getTargetJumpTable
(
N
->
getIndex
(
)
,
Ty
,
Flag
)
;
if
(
ConstantPoolSDNode
*
N
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
N
->
getConstVal
(
)
,
Ty
,
N
->
getAlignment
(
)
,
N
->
getOffset
(
)
,
Flag
)
;
llvm_unreachable
(
"Unexpected node type."
)
;
return
SDValue
(
)
;
}
</s>

Retrieve the target node this edge connects to .


<s> int sh_attr_renesas_p ( tree td ) { if ( TARGET_HITACHI ) return 1 ; if ( td == 0 ) return 0 ; if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return 0 ; return ( lookup_attribute ( "renesas" , TYPE_ATTRIBUTES ( td ) ) != NULL_TREE ) ; } </s>

True if __attribute__ ( ( renesas ) ) or -mrenesas .


<s> SDNode * MandarinDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return NULL ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: FrameIndex : if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) { return CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> void Cpu0SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( MF . getFrameInfo ( ) . hasCalls ( ) ) setAliasRegs ( MF , SavedRegs , Cpu0 :: LR ) ; return ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void mips_emit_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 , bool need_eq_ne_p ) { if ( GET_MODE_CLASS ( GET_MODE ( cmp_operands [ 0 ] ) ) == MODE_INT ) { if ( ! need_eq_ne_p && cmp_operands [ 1 ] == const0_rtx ) { * op0 = cmp_operands [ 0 ] ; * op1 = cmp_operands [ 1 ] ; } else if ( * code == EQ || * code == NE ) { if ( need_eq_ne_p ) { * op0 = mips_zero_if_equal ( cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; * op1 = const0_rtx ; } else { * op0 = cmp_operands [ 0 ] ; * op1 = force_reg ( GET_MODE ( * op0 ) , cmp_operands [ 1 ] ) ; } } else { bool invert = false ; * op0 = gen_reg_rtx ( GET_MODE ( cmp_operands [ 0 ] ) ) ; * op1 = const0_rtx ; mips_emit_int_relational ( * code , & invert , * op0 , cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; * code = ( invert ? EQ : NE ) ; } } else { enum rtx_code cmp_code ; switch ( * code ) { case NE : case LTGT : case ORDERED : cmp_code = reverse_condition_maybe_unordered ( * code ) ; * code = EQ ; break ; default : cmp_code = * code ; * code = NE ; break ; } * op0 = ( ISA_HAS_8CC ? gen_reg_rtx ( CCmode ) : gen_rtx_REG ( CCmode , FPSW_REGNUM ) ) ; * op1 = const0_rtx ; mips_emit_binary ( cmp_code , * op0 , cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; } } </s>

Convert a comparison into something that can be used in a branch or conditional move . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update * CODE , * OP0 and * OP1 so that they describe the final comparison . If NEED_EQ_NE_P , then only EQ or NE comparisons against zero are possible , otherwise any standard branch condition can be used . The standard branch conditions are : - EQ or NE between two registers . - any comparison between a register and zero .


<s> static void swap_const_vector_halves ( rtx * op_ptr ) { int i ; rtx op = * op_ptr ; enum rtx_code code = GET_CODE ( op ) ; if ( GET_CODE ( op ) == CONST_VECTOR ) { int units = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; rtx_vector_builder builder ( GET_MODE ( op ) , units , 1 ) ; for ( i = 0 ; i < units / 2 ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i + units / 2 ) ) ; for ( i = 0 ; i < units / 2 ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i ) ) ; * op_ptr = builder . build ( ) ; } else { int j ; const char * fmt = GET_RTX_FORMAT ( code ) ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) swap_const_vector_halves ( & XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( op , i ) ; ++ j ) swap_const_vector_halves ( & XVECEXP ( op , i , j ) ) ; } } </s>

OP is either a CONST_VECTOR or an expression containing one . Swap the first half of the vector with the second in the first case . Recurse to find it in the second .


<s> bool ARMTTIImpl :: isLegalMaskedLoad ( Type * DataTy , MaybeAlign Alignment ) { if ( ! EnableMaskedLoadStores || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( auto * VecTy = dyn_cast < FixedVectorType > ( DataTy ) ) { if ( VecTy -> getNumElements ( ) == 2 ) return false ; unsigned VecWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( VecWidth != 128 && VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return ( EltWidth == 32 && ( ! Alignment || * Alignment >= 4 ) ) || ( EltWidth == 16 && ( ! Alignment || * Alignment >= 2 ) ) || ( EltWidth == 8 ) ; } </s>

Return true if the target supports masked load .


<s> bool PPCGenScalarMASSEntries :: runOnModule ( Module & M ) { bool Changed = false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC || skipModule ( M ) ) return false ; for ( Function & Func : M ) { if ( ! Func . isDeclaration ( ) ) continue ; auto Iter = ScalarMASSFuncs . find ( Func . getName ( ) ) ; if ( Iter == ScalarMASSFuncs . end ( ) ) continue ; SmallVector < User * , 4 > TheUsers ; for ( auto * User : Func . users ( ) ) TheUsers . push_back ( User ) ; for ( auto * User : TheUsers ) if ( auto * CI = dyn_cast_or_null < CallInst > ( User ) ) { if ( isCandidateSafeToLower ( * CI ) ) Changed |= createScalarMASSCall ( Iter -> second , * CI , Func ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> BitVector ARM64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM64 :: SP ) ; Reserved . set ( ARM64 :: XZR ) ; Reserved . set ( ARM64 :: WSP ) ; Reserved . set ( ARM64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) { Reserved . set ( ARM64 :: FP ) ; Reserved . set ( ARM64 :: W29 ) ; } if ( STI -> isTargetDarwin ( ) ) { Reserved . set ( ARM64 :: X18 ) ; Reserved . set ( ARM64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( ARM64 :: X19 ) ; Reserved . set ( ARM64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> rtx mips_strip_unspec_address ( rtx op ) { rtx base , offset ; split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op ; } </s>

If OP is an UNSPEC address , return the address to which it refers , otherwise return OP itself .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI && ! TM . getSubtarget < ARMSubtarget > ( ) . isTargetNaCl ( ) ) { LSDASection = NULL ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> static void emit_cfa_restores ( rtx cfa_restores ) { rtx_insn * insn = get_last_insn ( ) ; rtx * loc = & REG_NOTES ( insn ) ; while ( * loc ) loc = & XEXP ( * loc , 1 ) ; * loc = cfa_restores ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Append CFA_RESTORES to any existing REG_NOTES on the last insn .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; Type * EltTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntEltTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( EltTy ) ) ; Value * Trunc = Builder . CreateTrunc ( Builder . CreateCall ( Ldxr , Addr ) , IntEltTy ) ; return Builder . CreateBitCast ( Trunc , EltTy ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> static void ix86_emit_move_max ( rtx dst , rtx src ) { ix86_emit_cmove ( dst , src , LTU , dst , src ) ; } </s>

Choose max of DST and SRC and put it to DST .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createPPCLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
*
BB
:
depth_first_ext
(
Entry
,
Processed
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
.
second
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
APInt
&
KnownZero
,
APInt
&
KnownOne
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
APInt
KnownZero2
,
KnownOne2
;
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
KnownZero
,
KnownOne
,
Depth
+
1
)
;
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
KnownZero2
,
KnownOne2
,
Depth
+
1
)
;
KnownZero
&=
KnownZero2
;
KnownOne
&=
KnownOne2
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
KnownOne
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
KnownZero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
KnownZero
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
KnownZero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
KnownZero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct gcc_options * opts , struct gcc_options * ) { ptr -> x_aarch64_override_tune_string = opts -> x_aarch64_override_tune_string ; ptr -> x_aarch64_branch_protection_string = opts -> x_aarch64_branch_protection_string ; } </s>


<s> static void fusion_split_address ( rtx addr , rtx * p_hi , rtx * p_lo ) { rtx hi , lo ; if ( GET_CODE ( addr ) == UNSPEC && XINT ( addr , 1 ) == UNSPEC_FUSION_ADDIS ) { lo = XVECEXP ( addr , 0 , 0 ) ; hi = gen_rtx_HIGH ( Pmode , lo ) ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) { hi = XEXP ( addr , 0 ) ; lo = XEXP ( addr , 1 ) ; } else gcc_unreachable ( ) ; * p_hi = hi ; * p_lo = lo ; } </s>

Given an address , convert it into the addis and load offset parts . Addresses created during the peephole2 process look like : ( lo_sum ( high ( unspec [ ( sym ) ] UNSPEC_TOCREL ) ) ( unspec [ ( ... ) ] UNSPEC_TOCREL ) )


<s> bool DLXPassConfig :: addInstSelector ( ) { addPass ( createDLXISelDag ( getDLXTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


"8-byte alignment required for for all register save slots"

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s>
unsigned
assignCustomValue
(
const
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
assert
(
Arg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
Register
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Regs
[
0
]
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s>
unsigned
X86InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
X86
::
JMP_1
&&
X86
::
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
==
X86
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
void
ARMBaseInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
unsigned
Align
=
MFI
.
getObjectAlignment
(
FI
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
0
,
MFI
.
getObjectSize
(
FI
)
,
Align
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
RC
=
ARM
::
GPRRegisterClass
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
LDR
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
||
RC
==
ARM
::
DPR_VFP2RegisterClass
||
RC
==
ARM
::
DPR_8RegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRD
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
SPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRS
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
{
assert
(
(
RC
==
ARM
::
QPRRegisterClass
||
RC
==
ARM
::
QPR_VFP2RegisterClass
||
RC
==
ARM
::
QPR_8RegisterClass
)
&&
"Unknown regclass!"
)
;
if
(
Align
>=
16
&&
(
getRegisterInfo
(
)
.
canRealignStack
(
MF
)
)
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLD1q64
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addImm
(
0
)
.
addImm
(
128
)
.
addMemOperand
(
MMO
)
)
;
}
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRQ
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static bool mips_expand_vpc_loongson_even_odd ( struct expand_vec_perm_d * d ) { unsigned i , odd , nelt = d -> nelt ; rtx t0 , t1 , t2 , t3 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( nelt < 4 ) return false ; odd = d -> perm [ 0 ] ; if ( odd > 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i * 2 + odd ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( d -> vmode ) ; t1 = gen_reg_rtx ( d -> vmode ) ; switch ( d -> vmode ) { case E_V4HImode : emit_insn ( gen_loongson_punpckhhw ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklhw ( t1 , d -> op0 , d -> op1 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhhw ( d -> target , t1 , t0 ) ) ; else emit_insn ( gen_loongson_punpcklhw ( d -> target , t1 , t0 ) ) ; break ; case E_V8QImode : t2 = gen_reg_rtx ( d -> vmode ) ; t3 = gen_reg_rtx ( d -> vmode ) ; emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t1 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpckhbh ( t2 , t1 , t0 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t3 , t1 , t0 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhbh ( d -> target , t3 , t2 ) ) ; else emit_insn ( gen_loongson_punpcklbh ( d -> target , t3 , t2 ) ) ; break ; default : gcc_unreachable ( ) ; } return true ; } </s>

Recognize patterns for even-odd extraction .


<s> static void arm_elf_asm_destructor ( rtx symbol , int priority ) { arm_elf_asm_cdtor ( symbol , priority , false ) ; } </s>

Add a function to the list of static destructors .


"interrupt and naked attributes are not compatible"

"Only DWARF debug format is supported for interrupt "

Set the func_type field from the function FNDECL .


<s> static void aarch64_asm_output_variant_pcs ( FILE * stream , const tree decl , const char * name ) { if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { arm_pcs pcs = ( arm_pcs ) fndecl_abi ( decl ) . id ( ) ; if ( pcs == ARM_PCS_SIMD || pcs == ARM_PCS_SVE ) { fprintf ( stream , "\t.variant_pcs\t" ) ; assemble_name ( stream , name ) ; fprintf ( stream , "\n" ) ; } } } </s>

Output .variant_pcs for aarch64_vector_pcs function symbols .


<s> static int mips_multipass_dfa_lookahead ( void ) { if ( TUNE_SB1 ) return 4 ; if ( TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E ) return 4 ; if ( TUNE_OCTEON || TUNE_GS264E ) return 2 ; if ( TUNE_P5600 || TUNE_P6600 || TUNE_I6400 ) return 4 ; return 0 ; } </s>


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
,
ISD
::
ArgFlagsTy
Flags
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
const
bool
IsImmutable
=
!
Flags
.
isByVal
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
IsImmutable
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
return
MIRBuilder
.
buildFrameIndex
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
,
FI
)
.
getReg
(
0
)
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> int PPCTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCost ( Imm , Ty , CostKind ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void ix86_expand_vector_logical_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx op1 = NULL_RTX , op2 = NULL_RTX ; if ( SUBREG_P ( operands [ 1 ] ) ) { op1 = operands [ 1 ] ; op2 = operands [ 2 ] ; } else if ( SUBREG_P ( operands [ 2 ] ) ) { op1 = operands [ 2 ] ; op2 = operands [ 1 ] ; } if ( op1 && ! TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL && ( SUBREG_P ( op2 ) || GET_CODE ( op2 ) == CONST_VECTOR ) && GET_MODE_CLASS ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == MODE_VECTOR_FLOAT && GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == GET_MODE_SIZE ( mode ) && SUBREG_BYTE ( op1 ) == 0 && ( GET_CODE ( op2 ) == CONST_VECTOR || ( GET_MODE ( SUBREG_REG ( op1 ) ) == GET_MODE ( SUBREG_REG ( op2 ) ) && SUBREG_BYTE ( op2 ) == 0 ) ) && can_create_pseudo_p ( ) ) { rtx dst ; switch ( GET_MODE ( SUBREG_REG ( op1 ) ) ) { case V4SFmode : case V8SFmode : case V16SFmode : case V2DFmode : case V4DFmode : case V8DFmode : dst = gen_reg_rtx ( GET_MODE ( SUBREG_REG ( op1 ) ) ) ; if ( GET_CODE ( op2 ) == CONST_VECTOR ) { op2 = gen_lowpart ( GET_MODE ( dst ) , op2 ) ; op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } else { op1 = operands [ 1 ] ; op2 = SUBREG_REG ( operands [ 2 ] ) ; if ( ! vector_operand ( op2 , GET_MODE ( dst ) ) ) op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } op1 = SUBREG_REG ( op1 ) ; if ( ! vector_operand ( op1 , GET_MODE ( dst ) ) ) op1 = force_reg ( GET_MODE ( dst ) , op1 ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , GET_MODE ( dst ) , op1 , op2 ) ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( mode , dst ) ) ; return ; default : break ; } } if ( ! vector_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; if ( ! vector_operand ( operands [ 2 ] , mode ) ) operands [ 2 ] = force_reg ( mode , operands [ 2 ] ) ; ix86_fixup_binary_operands_no_copy ( code , mode , operands ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_fmt_ee ( code , mode , operands [ 1 ] , operands [ 2 ] ) ) ) ; } </s>

Expand vector logical operation CODE ( AND , IOR , XOR ) in MODE with the given OPERANDS .


<s> const char * ix86_output_indirect_function_return ( rtx ret_op ) { if ( cfun -> machine -> function_return_type != indirect_branch_keep ) { char thunk_name [ 32 ] ; enum indirect_thunk_prefix need_prefix = indirect_thunk_need_prefix ( current_output_insn ) ; unsigned int regno = REGNO ( ret_op ) ; gcc_assert ( regno == CX_REG ) ; if ( cfun -> machine -> function_return_type != indirect_branch_thunk_inline ) { bool need_thunk = ( cfun -> machine -> function_return_type == indirect_branch_thunk ) ; indirect_thunk_name ( thunk_name , regno , need_prefix , true ) ; if ( need_thunk ) { indirect_return_via_cx = true ; SET_HARD_REG_BIT ( indirect_thunks_used , CX_REG ) ; } fprintf ( asm_out_file , "\tjmp\t" ) ; assemble_name ( asm_out_file , thunk_name ) ; putc ( '\n' , asm_out_file ) ; } else output_indirect_thunk ( regno ) ; } else { output_asm_insn ( "%!jmp\t%A0" , & ret_op ) ; if ( ix86_harden_sls & harden_sls_indirect_jmp ) fputs ( "\tint3\n" , asm_out_file ) ; } return "" ; } </s>

Output indirect function return . RET_OP is the function return target .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
Imm
.
Val
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
Mem
.
Off
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_PhysRegister
:
OS
<<
"PhysReg<"
<<
PhysReg
.
Num
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
case
k_RegPair
:
OS
<<
"RegPair<"
<<
RegIdx
.
Index
<<
","
<<
RegIdx
.
Index
+
1
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool SystemZFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> rtx rs6000_got_register ( rtx value ATTRIBUTE_UNUSED ) { if ( no_new_pseudos && ! regs_ever_live [ RS6000_PIC_OFFSET_TABLE_REGNUM ] ) regs_ever_live [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = 1 ; current_function_uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } </s>


<s> const unsigned * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return ( STI . isTargetIOS ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


<s> int arm_apply_result_size ( void ) { int size = 16 ; if ( TARGET_32BIT ) { if ( TARGET_HARD_FLOAT_ABI ) size += 32 ; if ( TARGET_IWMMXT_ABI ) size += 8 ; } return size ; } </s>

Determine the amount of memory needed to store the possible return registers of an untyped call .


<s> static bool rs6000_const_not_ok_for_debug_p ( rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) { rtx c = get_pool_constant ( x ) ; machine_mode cmode = get_pool_mode ( x ) ; if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( c , cmode ) ) return true ; } return false ; } </s>

Return true if X should n't be emitted into the debug info . The linker does n't like .toc section references from .debug_ * sections , so reject .toc section symbols .


<s> static void rs6000_option_override ( void ) { ( void ) rs6000_option_override_internal ( true ) ; opt_pass * pass_analyze_swaps = make_pass_analyze_swaps ( g ) ; struct register_pass_info analyze_swaps_info = { pass_analyze_swaps , "cse1" , 1 , PASS_POS_INSERT_BEFORE } ; register_pass ( & analyze_swaps_info ) ; } </s>

Implement TARGET_OPTION_OVERRIDE . On the RS/6000 this is used to define the target cpu type .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool isMem ( ) const override { return isMEMrr ( ) || isMEMri ( ) ; } </s>


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static int aarch64_sched_issue_rate ( void ) { return aarch64_tune_params . issue_rate ; } </s>

Return the number of instructions that can be issued per cycle .


<s> static unsigned long arm_compute_func_type ( void ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > 0 && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && arm_except_unwind_info ( & global_options ) != UI_SJLJ ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; return type ; } </s>

Computes the type of the current function .


<s> const MipsInstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>


<s> bool rs6000_return_in_msb ( const_tree valtype ) { return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && ( rs6000_function_arg_padding ( TYPE_MODE ( valtype ) , valtype ) == PAD_UPWARD ) ) ; } </s>

Specify whether values returned in registers should be at the most significant end of a register . We want aggregates returned by value to match the way aggregates are passed to functions .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_ELF : return "PPCISD::CALL_ELF" ; case PPCISD :: CALL_Macho : return "PPCISD::CALL_Macho" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Macho : return "PPCISD::BCTRL_Macho" ; case PPCISD :: BCTRL_ELF : return "PPCISD::BCTRL_ELF" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TAILCALL : return "PPCISD::TAILCALL" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

PowerPC PPC 0 PPCISD::FSEL "PPCISD::FSEL" PPCISD::FCFID "PPCISD::FCFID" PPCISD::FCTIDZ "PPCISD::FCTIDZ" PPCISD::FCTIWZ "PPCISD::FCTIWZ" PPCISD::STFIWX "PPCISD::STFIWX" PPCISD::VMADDFP "PPCISD::VMADDFP" PPCISD::VNMSUBFP "PPCISD::VNMSUBFP" PPCISD::VPERM "PPCISD::VPERM" PPCISD::Hi "PPCISD::Hi" PPCISD::Lo "PPCISD::Lo" PPCISD::DYNALLOC "PPCISD::DYNALLOC" PPCISD::GlobalBaseReg "PPCISD::GlobalBaseReg" PPCISD::SRL "PPCISD::SRL" PPCISD::SRA "PPCISD::SRA" PPCISD::SHL "PPCISD::SHL" PPCISD::EXTSW_32 "PPCISD::EXTSW_32" PPCISD::STD_32 "PPCISD::STD_32" PPCISD::CALL_ELF "PPCISD::CALL_ELF" PPCISD::CALL_Macho "PPCISD::CALL_Macho" PPCISD::MTCTR "PPCISD::MTCTR" PPCISD::BCTRL_Macho "PPCISD::BCTRL_Macho" PPCISD::BCTRL_ELF "PPCISD::BCTRL_ELF" PPCISD::RET_FLAG "PPCISD::RET_FLAG" PPCISD::MFCR "PPCISD::MFCR" PPCISD::VCMP "PPCISD::VCMP" PPCISD::VCMPo "PPCISD::VCMPo" PPCISD::LBRX "PPCISD::LBRX" PPCISD::STBRX "PPCISD::STBRX" PPCISD::LARX "PPCISD::LARX" PPCISD::STCX "PPCISD::STCX" PPCISD::COND_BRANCH "PPCISD::COND_BRANCH" PPCISD::MFFS "PPCISD::MFFS" PPCISD::MTFSB0 "PPCISD::MTFSB0" PPCISD::MTFSB1 "PPCISD::MTFSB1" PPCISD::FADDRTZ "PPCISD::FADDRTZ" PPCISD::MTFSF "PPCISD::MTFSF" PPCISD::TAILCALL "PPCISD::TAILCALL" PPCISD::TC_RETURN "PPCISD::TC_RETURN"


<s> static bool aarch64_evpc_sve_tbl ( struct expand_vec_perm_d * d ) { unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = mode_for_int_vector ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; if ( d -> one_vector_p ) emit_unspec2 ( d -> target , UNSPEC_TBL , d -> op0 , force_reg ( sel_mode , sel ) ) ; else aarch64_expand_sve_vec_perm ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

Try to implement D using an SVE TBL instruction .


<s> bool X86TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { SDValue BasePtr = cast < LoadSDNode > ( Load ) -> getBasePtr ( ) ; if ( BasePtr . getOpcode ( ) == X86ISD :: WrapperRIP ) if ( const auto * GA = dyn_cast < GlobalAddressSDNode > ( BasePtr . getOperand ( 0 ) ) ) return GA -> getTargetFlags ( ) != X86II :: MO_GOTTPOFF ; return true ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { return true ; } else { PrintMemReference ( MI , OpNo , O , "H" ) ; } return false ; case 'P' : if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { PrintIntelMemReference ( MI , OpNo , O , "disp-only" ) ; } else { PrintMemReference ( MI , OpNo , O , "disp-only" ) ; } return false ; } } if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { PrintIntelMemReference ( MI , OpNo , O , nullptr ) ; } else { PrintMemReference ( MI , OpNo , O , nullptr ) ; } return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static rtx aarch64_gen_store_pair ( machine_mode mode , rtx mem1 , rtx reg1 , rtx mem2 , rtx reg2 ) { switch ( mode ) { case E_DImode : return gen_store_pair_dw_didi ( mem1 , reg1 , mem2 , reg2 ) ; case E_DFmode : return gen_store_pair_dw_dfdf ( mem1 , reg1 , mem2 , reg2 ) ; case E_TFmode : return gen_store_pair_dw_tftf ( mem1 , reg1 , mem2 , reg2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return a store pair instruction of mode MODE to store register REG1 to MEM1 and register REG2 to MEM2 .


<s> static rtx emit_multi_reg_push ( unsigned long mask , unsigned long dwarf_regs_mask ) { int num_regs = 0 ; int num_dwarf_regs = 0 ; int i , j ; rtx par ; rtx dwarf ; int dwarf_par_index ; rtx tmp , reg ; dwarf_regs_mask &= ~ ( 1 << PC_REGNUM ) ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) num_regs ++ ; if ( dwarf_regs_mask & ( 1 << i ) ) num_dwarf_regs ++ ; } gcc_assert ( num_regs && num_regs <= 16 ) ; gcc_assert ( ( dwarf_regs_mask & ~ mask ) == 0 ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + 1 ) ) ; dwarf_par_index = 1 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } break ; } } for ( j = 1 , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } j ++ ; } } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; return par ; } </s>

Generate and emit an insn that we will recognize as a push_multi . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> bool X86FrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; bool isWin64 = STI . isTargetWin64 ( ) ; unsigned SlotSize = STI . is64Bit ( ) ? 8 : 4 ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned CalleeFrameSize = 0 ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( ! X86 :: VR128RegClass . contains ( Reg ) && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; } } X86FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool isMem ( ) const override { return false ; } </s>


<s>
bool
SystemZTargetLowering
::
splitValueIntoRegisterParts
(
SelectionDAG
&
DAG
,
const
SDLoc
&
DL
,
SDValue
Val
,
SDValue
*
Parts
,
unsigned
NumParts
,
MVT
PartVT
,
Optional
<
CallingConv
::
ID
>
CC
)
const
{
EVT
ValueVT
=
Val
.
getValueType
(
)
;
assert
(
(
ValueVT
!=
MVT
::
i128
||
(
(
NumParts
==
1
&&
PartVT
==
MVT
::
Untyped
)
||
(
NumParts
==
2
&&
PartVT
==
MVT
::
i64
)
)
)
&&
"Unknown handling of i128 value."
)
;
if
(
ValueVT
==
MVT
::
i128
&&
NumParts
==
1
)
{
Parts
[
0
]
=
lowerI128ToGR128
(
DAG
,
Val
)
;
return
true
;
}
return
false
;
}
</s>

Target-specific splitting of values into parts that fit a register storing a legal type .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case E_SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case E_DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; half = const_double_from_real_value ( pred_half , mode ) ; e1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_copysign ( e1 , half , op1 ) ) ; e2 = expand_simple_binop ( mode , PLUS , op1 , e1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; res = gen_reg_rtx ( mode ) ; emit_insn ( gen_round ( res , e2 , GEN_INT ( ROUND_TRUNC ) ) ) ; emit_move_insn ( op0 , res ) ; } </s>

Expand SSE sequence for computing round from OP1 storing into OP0 using sse4 round insn .


<s> tree find_instance ( bool * unsupported_builtin , ovlddata * * instance , rs6000_gen_builtins instance_code , rs6000_gen_builtins fcode , tree * types , tree * args ) { while ( * instance && ( * instance ) -> bifid != instance_code ) * instance = ( * instance ) -> next ; ovlddata * inst = * instance ; gcc_assert ( inst != NULL ) ; if ( ! inst -> fntype ) return error_mark_node ; tree fntype = rs6000_builtin_info [ inst -> bifid ] . fntype ; tree parmtype0 = TREE_VALUE ( TYPE_ARG_TYPES ( fntype ) ) ; tree parmtype1 = TREE_VALUE ( TREE_CHAIN ( TYPE_ARG_TYPES ( fntype ) ) ) ; if ( rs6000_builtin_type_compatible ( types [ 0 ] , parmtype0 ) && rs6000_builtin_type_compatible ( types [ 1 ] , parmtype1 ) ) { if ( rs6000_builtin_decl ( inst -> bifid , false ) != error_mark_node && rs6000_builtin_is_supported ( inst -> bifid ) ) { tree ret_type = TREE_TYPE ( inst -> fntype ) ; return altivec_build_resolved_builtin ( args , 2 , fntype , ret_type , inst -> bifid , fcode ) ; } else * unsupported_builtin = true ; } return error_mark_node ; } </s>

Look for a matching instance in a chain of instances . INSTANCE points to the chain of instances ; INSTANCE_CODE is the code identifying the specific built-in being searched for ; FCODE is the overloaded function code ; TYPES contains an array of two types that must match the types of the instance 's parameters ; and ARGS contains an array of two arguments to be passed to the instance . If found , resolve the built-in and return it , unless the built-in is not supported in context . In that case , set UNSUPPORTED_BUILTIN to true . If we do n't match , return error_mark_node and leave UNSUPPORTED_BUILTIN alone .


<s> static tree rs6000_md_asm_clobbers ( tree , tree , tree clobbers ) { tree s = build_string ( strlen ( reg_names [ CA_REGNO ] ) , reg_names [ CA_REGNO ] ) ; return tree_cons ( NULL_TREE , s , clobbers ) ; } </s>

Implement TARGET_MD_ASM_CLOBBERS . All asm statements are considered to clobber the XER [ CA ] bit because clobbering that bit without telling the compiler worked just fine with versions of GCC before GCC 5 , and breaking a lot of older code in ways that are hard to track down is not such a great idea .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new ARMHazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget , DAG ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> static bool mips_breakable_sequence_p ( rtx_insn * insn ) { return ( insn && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE && TARGET_CB_MAYBE && get_attr_compact_form ( SEQ_BEGIN ( insn ) ) != COMPACT_FORM_NEVER ) ; } </s>

A SEQUENCE is breakable iff the branch inside it has a compact form and the target has compact branches .


<s> void WinEHStatePass :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilderBase & Builder , Type * ValueTy , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValueTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValueTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValueTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValueTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; CallInst * CI = Builder . CreateCall ( Ldrex , Addr ) ; CI -> addParamAttr ( 0 , Attribute :: get ( M -> getContext ( ) , Attribute :: ElementType , ValueTy ) ) ; return Builder . CreateTruncOrBitCast ( CI , ValueTy ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s>
static
bool
aarch64_pass_by_reference
(
cumulative_args_t
pcum_v
,
const
function_arg_info
&
arg
)
{
CUMULATIVE_ARGS
*
pcum
=
get_cumulative_args
(
pcum_v
)
;
if
(
!
arg
.
type
)
return
aarch64_pass_by_reference_1
(
pcum
,
arg
)
;
pure_scalable_type_info
pst_info
;
switch
(
pst_info
.
analyze
(
arg
.
type
)
)
{
case
pure_scalable_type_info
::
IS_PST
:
if
(
pcum
&&
!
pcum
->
silent_p
&&
!
TARGET_SVE
)
fatal_error
(
input_location
,
"arguments of type %qT require"
" the SVE ISA extension"
,
arg
.
type
)
;
return
(
!
arg
.
named
||
pcum
->
aapcs_nvrn
+
pst_info
.
num_zr
(
)
>
NUM_FP_ARG_REGS
||
pcum
->
aapcs_nprn
+
pst_info
.
num_pr
(
)
>
NUM_PR_ARG_REGS
)
;
case
pure_scalable_type_info
::
DOESNT_MATTER
:
gcc_assert
(
aarch64_pass_by_reference_1
(
pcum
,
arg
)
)
;
return
true
;
case
pure_scalable_type_info
::
NO_ABI_IDENTITY
:
case
pure_scalable_type_info
::
ISNT_PST
:
return
aarch64_pass_by_reference_1
(
pcum
,
arg
)
;
}
gcc_unreachable
(
)
;
}
</s>

aarch64
"arguments of type %qT require"
" the SVE ISA extension"


<s> const SparcSubtarget * SparcTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SparcSubtarget > ( TargetTriple , CPU , FS , * this , this -> is64Bit ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Sparc Sparc Sparc "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" Sparc


<s> EVT X86TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget -> hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; if ( Subtarget -> hasAVX512 ( ) ) switch ( VT . getVectorNumElements ( ) ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> const LanaiSubtarget * getSubtargetImpl ( const llvm :: Function & Fn ) const override { return & Subtarget ; } </s>


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'f' : case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .