<s> static void assign_int_registers ( HOST_WIDE_INT bitpos , assign_data_t * data ) { int intoffset = data -> intoffset ; machine_mode mode ; int nregs ; if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != 0 ) mode = smallest_int_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; data -> nregs += 1 ; mode = word_mode ; regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign the bits of the structure between PARMS- > intoffset and BITPOS to integer registers .


Return true if the vector misalignment factor is supported by the target .


<s> bool SICAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! TM . getSubtargetImpl ( ) -> hasISEL ( ) ) return false ; if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 5 - HasFP ; } case ARM :: GPRRegClassID : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; return 10 - HasFP - STI . getNumGPRegistersReserved ( ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( 0 , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool constant_address_p ( rtx x ) { return CONSTANT_P ( x ) && legitimate_address_p ( Pmode , x , 1 ) ; } </s>

Determine if a given RTX is a valid constant address .


<s> bool VEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case VE :: EXTEND_STACK : { return expandExtendStackPseudo ( MI ) ; } case VE :: EXTEND_STACK_GUARD : { MI . eraseFromParent ( ) ; return true ; } } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static rtx sparc_legitimize_pic_address ( rtx orig , rtx reg ) { if ( GET_CODE ( orig ) == SYMBOL_REF || ( GET_CODE ( orig ) == LABEL_REF && ! can_use_mov_pic_label_ref ( orig ) ) ) { bool gotdata_op = false ; rtx pic_ref , address ; rtx_insn * insn ; if ( ! reg ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } if ( flag_pic == 2 ) { rtx temp_reg = can_create_pseudo_p ( ) ? gen_reg_rtx ( Pmode ) : reg ; if ( TARGET_ARCH64 ) { emit_insn ( gen_movdi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movdi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } else { emit_insn ( gen_movsi_high_pic ( temp_reg , orig ) ) ; emit_insn ( gen_movsi_lo_sum_pic ( temp_reg , temp_reg , orig ) ) ; } address = temp_reg ; gotdata_op = true ; } else address = orig ; crtl -> uses_pic_offset_table = 1 ; if ( gotdata_op ) { if ( TARGET_ARCH64 ) insn = emit_insn ( gen_movdi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; else insn = emit_insn ( gen_movsi_pic_gotdata_op ( reg , pic_offset_table_rtx , address , orig ) ) ; } else { pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; insn = emit_move_insn ( reg , pic_ref ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS && sparc_pic_register_p ( XEXP ( XEXP ( orig , 0 ) , 0 ) ) ) return orig ; if ( ! reg ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , reg ) ; offset = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , base == reg ? NULL_RTX : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( can_create_pseudo_p ( ) ) offset = force_reg ( Pmode , offset ) ; else gcc_unreachable ( ) ; } return gen_rtx_PLUS ( Pmode , base , offset ) ; } else if ( GET_CODE ( orig ) == LABEL_REF ) crtl -> uses_pic_offset_table = 1 ; return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s> static bool isAssociativeAndCommutative ( const MachineInstr & Inst ) { switch ( Inst . getOpcode ( ) ) { case X86 :: AND8rr : case X86 :: AND16rr : case X86 :: AND32rr : case X86 :: AND64rr : case X86 :: OR8rr : case X86 :: OR16rr : case X86 :: OR32rr : case X86 :: OR64rr : case X86 :: XOR8rr : case X86 :: XOR16rr : case X86 :: XOR32rr : case X86 :: XOR64rr : case X86 :: IMUL16rr : case X86 :: IMUL32rr : case X86 :: IMUL64rr : case X86 :: MAXCPDrr : case X86 :: MAXCPSrr : case X86 :: MAXCSDrr : case X86 :: MAXCSSrr : case X86 :: MINCPDrr : case X86 :: MINCPSrr : case X86 :: MINCSDrr : case X86 :: MINCSSrr : case X86 :: VMAXCPDrr : case X86 :: VMAXCPSrr : case X86 :: VMAXCPDYrr : case X86 :: VMAXCPSYrr : case X86 :: VMAXCSDrr : case X86 :: VMAXCSSrr : case X86 :: VMINCPDrr : case X86 :: VMINCPSrr : case X86 :: VMINCPDYrr : case X86 :: VMINCPSYrr : case X86 :: VMINCSDrr : case X86 :: VMINCSSrr : return true ; case X86 :: ADDPDrr : case X86 :: ADDPSrr : case X86 :: ADDSDrr : case X86 :: ADDSSrr : case X86 :: MULPDrr : case X86 :: MULPSrr : case X86 :: MULSDrr : case X86 :: MULSSrr : case X86 :: VADDPDrr : case X86 :: VADDPSrr : case X86 :: VADDPDYrr : case X86 :: VADDPSYrr : case X86 :: VADDSDrr : case X86 :: VADDSSrr : case X86 :: VMULPDrr : case X86 :: VMULPSrr : case X86 :: VMULPDYrr : case X86 :: VMULPSYrr : case X86 :: VMULSDrr : case X86 :: VMULSSrr : return Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM A15 S->D optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Hazard Schedule"
;
}
</s>


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static rtx gen_gpr_to_xmm_move_src ( enum machine_mode vmode , rtx gpr ) { switch ( GET_MODE_NUNITS ( vmode ) ) { case 1 : return gen_rtx_SUBREG ( vmode , gpr , 0 ) ; case 2 : return gen_rtx_VEC_CONCAT ( vmode , gpr , CONST0_RTX ( GET_MODE_INNER ( vmode ) ) ) ; default : return gen_rtx_VEC_MERGE ( vmode , gen_rtx_VEC_DUPLICATE ( vmode , gpr ) , CONST0_RTX ( vmode ) , GEN_INT ( HOST_WIDE_INT_1U ) ) ; } } </s>

Generate the canonical SET_SRC to move GPR to a VMODE vector register , zeroing the upper parts .


Return an array that contains the bitmask target flag values and their names .


<s> rtx sh_movrt_set_dest ( const_rtx pat ) { if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; return GET_CODE ( pat ) == SET && arith_reg_dest ( XEXP ( pat , 0 ) , SImode ) && negt_reg_operand ( XEXP ( pat , 1 ) , VOIDmode ) ? XEXP ( pat , 0 ) : NULL ; } </s>

Given an insn , check whether it 's a 'movrt ' kind of insn , i.e . an insn that stores the negated T bit in a register , and return the destination register rtx , or null .


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { if ( ST -> getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMALFWriterPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned getNumFixupKinds ( ) const { return 1 ; } </s>

Get the number of target specific fixup kinds .


<s> void DCPU16AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { DCPU16MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> rtx ix86_zero_extend_to_Pmode ( rtx exp ) { rtx r ; if ( GET_MODE ( exp ) == VOIDmode ) return force_reg ( Pmode , exp ) ; if ( GET_MODE ( exp ) == Pmode ) return copy_to_mode_reg ( Pmode , exp ) ; r = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_zero_extendsidi2 ( r , exp ) ) ; return r ; } </s>

Zero extend possibly SImode EXP to Pmode register .


<s> const uint16_t * FISCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { FISC :: LR , FISC :: X19 , FISC :: X20 , FISC :: X21 , FISC :: X22 , FISC :: X23 , FISC :: X24 , FISC :: X25 , FISC :: X26 , FISC :: X27 , 0 } ; return CalleeSavedRegs ; } </s>


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return LowerRETURNADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE


"frame pointer should not have been eliminated"


<s> static bool sparc_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { if ( TARGET_ARCH32 ) return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) || mode == SCmode || GET_MODE_SIZE ( mode ) > 8 || ( type && VECTOR_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_TYPE_P ( type ) ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 16 ) || GET_MODE_SIZE ( mode ) > 16 ) ; } </s>

Handle the TARGET_PASS_BY_REFERENCE target hook . Specify whether to pass the argument by reference .


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> bool pbsada_insn_ra_rb_dep_reg_p ( rtx pbsada_insn , rtx def_reg ) { rtx unspec_rtx = SET_SRC ( PATTERN ( pbsada_insn ) ) ; gcc_assert ( GET_CODE ( unspec_rtx ) == UNSPEC ) ; rtx pbsada_ra = XVECEXP ( unspec_rtx , 0 , 0 ) ; rtx pbsada_rb = XVECEXP ( unspec_rtx , 0 , 1 ) ; if ( rtx_equal_p ( def_reg , pbsada_ra ) || rtx_equal_p ( def_reg , pbsada_rb ) ) return true ; return false ; } </s>

Determine if the latency is occured when the consumer PBSADA_INSN uses the value of DEF_REG in its Ra or Rb fields .


<s> rtx function_expander :: convert_to_pmode ( rtx x ) { if ( ptr_mode == SImode ) x = simplify_gen_unary ( ZERO_EXTEND , DImode , x , SImode ) ; return x ; } </s>


<s> void relaxInstruction ( const MCInst & , const MCSubtargetInfo & , MCInst & ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> virtual uint32_t generateCompactUnwindEncoding ( ArrayRef < MCCFIInstruction > Instrs ) const { return SupportsCU ? generateCompactUnwindEncodingImpl ( Instrs ) : 0 ; } </s>

Generate compact unwind encoding for the function based on the CFI instructions .


<s> bool isPPC64 ( ) const { const Triple & TT = getTargetTriple ( ) ; return ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) ; } </s>

Tests whether the target is 64-bit PowerPC ( little and big endian ) .


<s> unsigned getPointerSize ( ) const { return 8 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> static int aarch64_build_constant ( int regnum , HOST_WIDE_INT val , bool generate ) { int insns = 0 ; if ( aarch64_bitmask_imm ( val , DImode ) ) { if ( generate ) emit_move_insn ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( val ) ) ; insns = 1 ; } else { int i ; int ncount = 0 ; int zcount = 0 ; HOST_WIDE_INT valp = val >> 16 ; HOST_WIDE_INT valm ; HOST_WIDE_INT tval ; for ( i = 16 ; i < 64 ; i += 16 ) { valm = ( valp & 0xffff ) ; if ( valm != 0 ) ++ zcount ; if ( valm != 0xffff ) ++ ncount ; valp >>= 16 ; } if ( ncount < zcount ) { if ( generate ) emit_move_insn ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( val | ~ ( HOST_WIDE_INT ) 0xffff ) ) ; tval = 0xffff ; insns ++ ; } else { if ( generate ) emit_move_insn ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( val & 0xffff ) ) ; tval = 0 ; insns ++ ; } val >>= 16 ; for ( i = 16 ; i < 64 ; i += 16 ) { if ( ( val & 0xffff ) != tval ) { if ( generate ) emit_insn ( gen_insv_immdi ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( i ) , GEN_INT ( val & 0xffff ) ) ) ; insns ++ ; } val >>= 16 ; } } return insns ; } </s>

Possibly output code to build up a constant in a register . For the benefit of the costs infrastructure , returns the number of instructions which would be emitted . GENERATE inhibits or enables code generation .


"Calling %qD with attribute sseregparm without "

"Calling %qT with attribute sseregparm without "

Return 1 or 2 , if we can pass up to SSE_REGPARM_MAX SFmode ( 1 ) and DFmode ( 2 ) arguments in SSE registers for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall . Otherwise return 0 .


"PPC pre-emit peephole: erasing instruction: "

runOnMachineFunction - Emit the function body .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
static_assert
(
X86
::
FP6
==
X86
::
FP0
+
6
,
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
*
BB
:
depth_first_ext
(
Entry
,
Processed
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
.
second
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


"cannot return value in vector register because"

" altivec instructions are disabled, use %qs"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> void ix86_emit_i387_tanh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx cst2 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_addxf3 ( e2 , op1 , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , e2 ) ) ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_insn ( gen_expm1xf2 ( e1 , e2 ) ) ; cst2 = force_reg ( XFmode , CONST2_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , cst2 ) ) ; emit_insn ( gen_divxf3 ( e2 , e1 , e2 ) ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; emit_move_insn ( op0 , e2 ) ; } </s>

Output code to perform an tanh XFmode calculation .


<s> bool enablePostRAScheduler ( ) const override { return usePostRAScheduler ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> bool MipsAsmParser :: ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return true ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void mips_emit_int_order_test ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { machine_mode mode ; mode = GET_MODE ( cmp0 ) ; if ( mips_canonicalize_int_order_test ( & code , & cmp1 , mode ) ) mips_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! mips_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; mips_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == 0 ) { rtx inv_target ; inv_target = mips_force_binary ( GET_MODE ( target ) , inv_code , cmp0 , cmp1 ) ; mips_emit_binary ( XOR , target , inv_target , const1_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; mips_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } } } </s>

Compare CMP0 and CMP1 using ordering test CODE and store the result in TARGET . CMP0 and TARGET are register_operands . If INVERT_PTR is nonnull , it 's OK to set TARGET to the inverse of the result and flip * INVERT_PTR instead .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static int loongarch_small_data_pattern_1 ( rtx x ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , ALL ) { rtx x = * iter ; if ( GET_CODE ( x ) == ASM_OPERANDS ) iter . skip_subrtxes ( ) ; else if ( MEM_P ( x ) ) { if ( loongarch_small_data_pattern_1 ( XEXP ( x , 0 ) ) ) return true ; iter . skip_subrtxes ( ) ; } } return false ; } </s>

Return true if OP refers to small data symbols directly .


<s> SDValue Cpu0TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
InfosBE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24_notoc"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_pcrel34"
,
0
,
34
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_imm34"
,
0
,
34
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
const
static
MCFixupKindInfo
InfosLE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24_notoc"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
2
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
2
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
2
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
2
,
14
,
0
}
,
{
"fixup_ppc_pcrel34"
,
0
,
34
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_imm34"
,
0
,
34
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
(
Endian
==
support
::
little
InfosLE
:
InfosBE
)
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == 0 ) return false ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ; } else { int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; if ( Imm == 0 ) return false ; Target = Imm ; return true ; } } </s>

Given a branch instruction try to get the address the branch targets .


<s> bool UPTInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s> static void sparc_va_start ( tree valist , rtx nextarg ) { nextarg = expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'U' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool sh_expand_strlen ( rtx * operands ) { rtx addr1 = operands [ 1 ] ; rtx current_addr = copy_addr_to_reg ( XEXP ( addr1 , 0 ) ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; rtx_code_label * L_return = gen_label_rtx ( ) ; rtx_code_label * L_loop_byte = gen_label_rtx ( ) ; rtx jump ; rtx_code_label * L_loop_long = gen_label_rtx ( ) ; rtx_code_label * L_end_loop_long = gen_label_rtx ( ) ; int align = INTVAL ( operands [ 3 ] ) ; emit_move_insn ( operands [ 0 ] , GEN_INT ( - 1 ) ) ; emit_move_insn ( start_addr , current_addr ) ; if ( align < 4 ) { emit_insn ( gen_tstsi_t ( current_addr , GEN_INT ( 3 ) ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_move_insn ( tmp0 , operands [ 2 ] ) ; addr1 = adjust_automodify_address ( addr1 , SImode , current_addr , 0 ) ; emit_label ( L_loop_long ) ; emit_move_insn ( tmp1 , addr1 ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 4 ) ) ; emit_insn ( gen_cmpstr_t ( tmp0 , tmp1 ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_long ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_end_loop_long ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , - 4 ) ) ; addr1 = adjust_address ( addr1 , QImode , 0 ) ; for ( int i = 0 ; i < 4 ; ++ i ) { emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 1 ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_true ( L_return ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_barrier_after ( jump ) ; emit_label ( L_loop_byte ) ; emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 1 ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_return ) ; emit_insn ( gen_addsi3 ( start_addr , start_addr , GEN_INT ( 1 ) ) ) ; emit_insn ( gen_subsi3 ( operands [ 0 ] , current_addr , start_addr ) ) ; return true ; } </s>

Emit code to perform a strlen . OPERANDS [ 0 ] is the destination . OPERANDS [ 1 ] is the string . OPERANDS [ 2 ] is the char to search . OPERANDS [ 3 ] is the alignment .


<s> bool CSKYAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MCP = MF . getConstantPool ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; Subtarget = & NewSTI ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> static bool sh_legitimize_address_displacement ( rtx * disp , rtx * offs , machine_mode mode ) { if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( * disp ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * disp = adj . mov_disp ; * offs = adj . offset_adjust ; return true ; } return false ; } </s>

Return true if DISP can be legitimized .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> ARMRelocator :: Result none ( Relocation & pReloc , ARMRelocator & pParent ) { return Relocator :: OK ; } </s>

Returns true if none of the bits are set .


<s> static void arm_option_restore ( struct gcc_options * , struct gcc_options * , struct cl_target_option * ptr ) { arm_configure_build_target ( & arm_active_target , ptr , false ) ; arm_option_reconfigure_globals ( ) ; } </s>


<s> MachinePointerInfo Cpu0MachineFunctionInfo :: callPtrInfo ( const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> void SparcAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; case SP :: GETPCX : LowerGETPCXAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerSparcMachineInstrToMCInst ( I , TmpInst , * this ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int shl_sext_kind ( rtx left_rtx , rtx size_rtx , int * costp ) { int left , size , insize , ext ; int cost = 0 , best_cost ; int kind ; left = INTVAL ( left_rtx ) ; size = INTVAL ( size_rtx ) ; insize = size - left ; gcc_assert ( insize > 0 ) ; kind = 0 ; best_cost = ashl_lshr_seq [ 32 - insize ] . insn_count + ashl_lshr_seq [ 32 - size ] . insn_count ; if ( size <= 16 ) { cost = ashl_lshr_seq [ 16 - insize ] . insn_count + 1 + ashl_lshr_seq [ 16 - size ] . insn_count ; if ( cost < best_cost ) { kind = 5 ; best_cost = cost ; } } for ( ext = 16 ; ext >= insize ; ext -= 8 ) { if ( ext <= size ) { cost = ext_ashl_lshr_seq [ ext - insize ] . insn_count + 1 + ashl_lshr_seq [ size - ext ] . insn_count ; if ( cost < best_cost ) { kind = ext / ( unsigned ) 8 ; best_cost = cost ; } } if ( EXT_SHIFT_SIGNED ( size - ext ) ) cost = ext_ashl_lshr_seq [ ext - insize ] . insn_count + ext_ashl_lshr_seq [ size - ext ] . insn_count + 1 ; else if ( size <= 16 ) cost = ext_ashl_lshr_seq [ ext - insize ] . insn_count + 1 + ext_ashl_lshr_seq [ size > ext ? size - ext : ext - size ] . insn_count + 1 ; else continue ; if ( cost < best_cost ) { kind = ext / ( unsigned ) 8 + 2 ; best_cost = cost ; } } if ( insize < 8 ) { cost = 3 + ashl_lshr_seq [ left ] . insn_count ; if ( cost < best_cost ) { kind = 6 ; best_cost = cost ; } if ( left < 31 ) { cost = 3 + ext_ashl_lshr_seq [ left + 1 ] . insn_count + 1 ; if ( cost < best_cost ) { kind = 7 ; best_cost = cost ; } } } if ( TARGET_DYNSHIFT ) { cost = ashl_lshr_seq [ 32 - insize ] . insn_count + 1 + SH_DYNAMIC_SHIFT_COST ; if ( cost < best_cost ) { kind = 0 ; best_cost = cost ; } } if ( costp ) * costp = cost ; return kind ; } </s>

Try to find a good way to implement the combiner pattern [ ( set ( match_operand : SI 0 `` register_operand '' `` =r '' ) ( sign_extract : SI ( ashift : SI ( match_operand : SI 1 `` register_operand '' `` r '' ) ( match_operand : SI 2 `` const_int_operand '' `` n '' ) ( match_operand : SI 3 `` const_int_operand '' `` n '' ) ( const_int 0 ) ) ) ( clobber ( reg : SI T_REG ) ) ] LEFT_RTX is operand 2 in the above pattern , and SIZE_RTX is operand 3. return 0 for simple left / right shift combination . return 1 for left shift / 8 bit sign extend / left shift . return 2 for left shift / 16 bit sign extend / left shift . return 3 for left shift / 8 bit sign extend / shift / sign extend . return 4 for left shift / 16 bit sign extend / shift / sign extend . return 5 for left shift / 16 bit sign extend / right shift return 6 for < 8 bit sign extend / left shift . return 7 for < 8 bit sign extend / left shift / single right shift . If COSTP is nonzero , assign the calculated cost to * COSTP .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool SystemZPassConfig :: addPreSched2 ( ) { if ( getSystemZTargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static rtx gen_sym_unspec ( rtx x , int kind ) { return gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , x ) , kind ) ; } </s>

Helper for or1k_legitimize_address_1 . Wrap X in an unspec .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_NoRegs_SaveList ; else return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


<s> bool SystemZInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Pred , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! STI . hasLoadStoreOnCond ( ) ) return false ; if ( Pred . size ( ) != 2 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && SystemZ :: GRX32BitRegClass . hasSubClassEq ( RC ) ) || SystemZ :: GR32BitRegClass . hasSubClassEq ( RC ) || SystemZ :: GR64BitRegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Thumb IT blocks insertion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static tree make_resolver_func ( const tree default_decl , const tree ifunc_alias_decl , basic_block * empty_bb ) { tree decl , type , t ; tree decl_name = clone_function_name ( default_decl , "resolver" ) ; const char * resolver_name = IDENTIFIER_POINTER ( decl_name ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( ifunc_alias_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } else TREE_PUBLIC ( ifunc_alias_decl ) = 0 ; t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl ) ) ; cgraph_node :: create_same_body_alias ( ifunc_alias_decl , decl ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s> static section * rs6000_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

A C statement or statements to switch to the appropriate section for output of RTX in mode MODE . You can assume that RTX is some kind of constant in RTL . The argument MODE is redundant except in the case of a ` const_int ' rtx . Select the section by calling ` text_section ' or one of the alternatives for other sections . Do not define this macro if you put all constants in the read-only data section .


<s> static void emit_soft_tfmode_binop ( enum rtx_code code , rtx * operands ) { const char * func ; switch ( code ) { case PLUS : func = "_Qp_add" ; break ; case MINUS : func = "_Qp_sub" ; break ; case MULT : func = "_Qp_mul" ; break ; case DIV : func = "_Qp_div" ; break ; default : gcc_unreachable ( ) ; } emit_soft_tfmode_libcall ( func , 3 , operands ) ; } </s>

Expand soft-float TFmode calls to sparc abi routines .


<s> int sh_max_mov_insn_displacement ( machine_mode mode , bool consider_sh2a ) { const int disp_scale = consider_sh2a ? ( 4095 / 15 ) : 1 ; if ( ! consider_sh2a && TARGET_FPU_ANY && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return 0 ; else { const int mov_insn_sz = mov_insn_size ( mode , consider_sh2a ) ; const int mode_sz = GET_MODE_SIZE ( mode ) ; int r = 15 * mov_insn_sz * disp_scale ; if ( mode_sz > mov_insn_sz ) r -= mode_sz - mov_insn_sz ; return r ; } } </s>

Determine the maximum possible displacement for a move insn for the specified mode .


<s> SDValue PPCTargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , unsigned CallConv , bool isVarArg , bool isTailCall , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG , InVals ) ; } else { return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s> static void loongarch_for_each_saved_reg ( HOST_WIDE_INT sp_offset , loongarch_save_restore_fn fn ) { HOST_WIDE_INT offset ; offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { loongarch_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; loongarch_save_restore_reg ( mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( mode ) ; } } </s>

Call FN for each register that is saved by the current function . SP_OFFSET is the offset of the current stack pointer from the start of the frame .


<s> static HOST_WIDE_INT aarch64_simd_vector_alignment ( const_tree type ) { HOST_WIDE_INT align = tree_to_shwi ( TYPE_SIZE ( type ) ) ; return MIN ( align , 128 ) ; } </s>

Implement target hook TARGET_VECTOR_ALIGNMENT . The AAPCS64 sets the maximum alignment of a vector to 128 bits .


<s> static void csky_function_arg_advance ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int * reg = & pcum -> reg ; machine_mode mode = arg . mode ; int param_size = csky_num_arg_regs ( mode , arg . type , pcum -> is_stdarg ) ; int param_regs_nums = CSKY_NPARM_REGS ; if ( FUNCTION_VARG_MODE_P ( mode ) && ! pcum -> is_stdarg ) { reg = & pcum -> freg ; param_regs_nums = CSKY_NPARM_FREGS ; } if ( * reg + param_size > param_regs_nums ) * reg = param_regs_nums ; else * reg += param_size ; } </s>


";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n"


"Mips pseudo instruction expansion pass"


<s>
SDValue
VETargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
assert
(
!
IsVarArg
&&
"TODO implement var args"
)
;
assert
(
Ins
.
empty
(
)
&&
"TODO implement input arguments"
)
;
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

VE
VE
ISD::InputArg
"TODO implement var args"
"TODO implement input arguments"


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Execution Dependency Fix"
;
}
</s>


<s> static rtx nds32_legitimize_argument ( enum insn_code icode , int opnum , rtx arg ) { enum machine_mode mode = insn_data [ icode ] . operand [ opnum ] . mode ; if ( ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( arg , mode ) ) return arg ; else if ( VECTOR_MODE_P ( mode ) && CONST_INT_P ( arg ) ) { int nunits = GET_MODE_NUNITS ( mode ) ; int i , shift = 0 ; rtvec v = rtvec_alloc ( nunits ) ; int val = INTVAL ( arg ) ; enum machine_mode val_mode = ( mode == V4QImode ) ? QImode : HImode ; int shift_acc = ( val_mode == QImode ) ? 8 : 16 ; int mask = ( val_mode == QImode ) ? 0xff : 0xffff ; int tmp_val = val ; if ( TARGET_BIG_ENDIAN ) for ( i = 0 ; i < nunits ; i ++ ) { tmp_val = ( val >> shift ) & mask ; RTVEC_ELT ( v , nunits - i - 1 ) = gen_int_mode ( tmp_val , val_mode ) ; shift += shift_acc ; } else for ( i = 0 ; i < nunits ; i ++ ) { tmp_val = ( val >> shift ) & mask ; RTVEC_ELT ( v , i ) = gen_int_mode ( tmp_val , val_mode ) ; shift += shift_acc ; } return copy_to_mode_reg ( mode , gen_rtx_CONST_VECTOR ( mode , v ) ) ; } else { rtx tmp_rtx = gen_reg_rtx ( mode ) ; convert_move ( tmp_rtx , arg , false ) ; return tmp_rtx ; } } </s>

Given that ARG is being passed as operand OPNUM to instruction ICODE , check whether ARG satisfies the operand 's constraints . If it does n't , copy ARG to a temporary register and return that . Otherwise return ARG itself .


<s> bool X86AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool ARMBaseInstrInfo :: isPredicated ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 && I -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ) return true ; } return false ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ; } </s>

Returns true if the instruction is already predicated .


<s> bool arm_pad_arg_upward ( machine_mode mode ATTRIBUTE_UNUSED , const_tree type ) { if ( ! TARGET_AAPCS_BASED ) return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) == upward ; if ( type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P ( type ) ) return false ; return true ; } </s>

For use by FUNCTION_ARG_PADDING ( MODE , TYPE ) . Return true if an argument passed on the stack should be padded upwards , i.e . if the least-significant byte has useful data . For legacy APCS ABIs we use the default . For AAPCS based ABIs small aggregate types are placed in the lowest memory address .


<s> static unsigned HOST_WIDE_INT aarch64_asan_shadow_offset ( void ) { if ( TARGET_ILP32 ) return ( HOST_WIDE_INT_1 << 29 ) ; else return ( HOST_WIDE_INT_1 << 36 ) ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> static bool rs6000_is_costly_dependence ( dep_t dep , int cost , int distance ) { rtx insn ; rtx next ; rtx load_mem , str_mem ; if ( rs6000_sched_costly_dep == no_dep_costly ) return false ; if ( rs6000_sched_costly_dep == all_deps_costly ) return true ; insn = DEP_PRO ( dep ) ; next = DEP_CON ( dep ) ; if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) && DEP_TYPE ( dep ) == REG_DEP_TRUE && mem_locations_overlap ( str_mem , load_mem ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return false ; } </s>

Returns whether the dependence between INSN and NEXT is considered costly by the given target .


<s> void aarch64_init_builtin_rsqrt ( void ) { tree fndecl = NULL ; tree ftype = NULL ; tree V2SF_type_node = build_vector_type ( float_type_node , 2 ) ; tree V2DF_type_node = build_vector_type ( double_type_node , 2 ) ; tree V4SF_type_node = build_vector_type ( float_type_node , 4 ) ; struct builtin_decls_data { tree type_node ; const char * builtin_name ; int function_code ; } ; builtin_decls_data bdda [ ] = { { double_type_node , "__builtin_aarch64_rsqrt_df" , AARCH64_BUILTIN_RSQRT_DF } , { float_type_node , "__builtin_aarch64_rsqrt_sf" , AARCH64_BUILTIN_RSQRT_SF } , { V2DF_type_node , "__builtin_aarch64_rsqrt_v2df" , AARCH64_BUILTIN_RSQRT_V2DF } , { V2SF_type_node , "__builtin_aarch64_rsqrt_v2sf" , AARCH64_BUILTIN_RSQRT_V2SF } , { V4SF_type_node , "__builtin_aarch64_rsqrt_v4sf" , AARCH64_BUILTIN_RSQRT_V4SF } } ; builtin_decls_data * bdd = bdda ; builtin_decls_data * bdd_end = bdd + ( sizeof ( bdda ) / sizeof ( builtin_decls_data ) ) ; for ( ; bdd < bdd_end ; bdd ++ ) { ftype = build_function_type_list ( bdd -> type_node , bdd -> type_node , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , TYPE_MODE ( bdd -> type_node ) ) ; fndecl = aarch64_general_add_builtin ( bdd -> builtin_name , ftype , bdd -> function_code , attrs ) ; aarch64_builtin_decls [ bdd -> function_code ] = fndecl ; } } </s>

Add builtins for reciprocal square root .


<s>
static
void
rx_print_operand_address
(
FILE
*
file
,
machine_mode
,
rtx
addr
)
{
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
addr
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
case
PRE_DEC
:
fprintf
(
file
,
"[-"
)
;
rx_print_operand
(
file
,
XEXP
(
addr
,
0
)
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
case
POST_INC
:
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
XEXP
(
addr
,
0
)
,
0
)
;
fprintf
(
file
,
"+]"
)
;
break
;
case
PLUS
:
{
rtx
arg1
=
XEXP
(
addr
,
0
)
;
rtx
arg2
=
XEXP
(
addr
,
1
)
;
rtx
base
,
index
;
if
(
REG_P
(
arg1
)
&&
RTX_OK_FOR_BASE
(
arg1
,
true
)
)
base
=
arg1
,
index
=
arg2
;
else
if
(
REG_P
(
arg2
)
&&
RTX_OK_FOR_BASE
(
arg2
,
true
)
)
base
=
arg2
,
index
=
arg1
;
else
{
rx_print_operand
(
file
,
arg1
,
0
)
;
fprintf
(
file
,
" + "
)
;
rx_print_operand
(
file
,
arg2
,
0
)
;
break
;
}
if
(
REG_P
(
index
)
||
GET_CODE
(
index
)
==
MULT
)
{
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
index
,
'A'
)
;
fprintf
(
file
,
","
)
;
}
else
{
rx_print_operand
(
file
,
index
,
'A'
)
;
fprintf
(
file
,
"["
)
;
}
rx_print_operand
(
file
,
base
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
}
case
CONST
:
if
(
GET_CODE
(
XEXP
(
addr
,
0
)
)
==
UNSPEC
)
{
addr
=
XEXP
(
addr
,
0
)
;
gcc_assert
(
XINT
(
addr
,
1
)
==
UNSPEC_CONST
)
;
addr
=
XVECEXP
(
addr
,
0
,
0
)
;
gcc_assert
(
CONST_INT_P
(
addr
)
)
;
fprintf
(
file
,
"#"
)
;
output_addr_const
(
file
,
addr
)
;
break
;
}
fprintf
(
file
,
"#"
)
;
output_addr_const
(
file
,
XEXP
(
addr
,
0
)
)
;
break
;
case
UNSPEC
:
addr
=
XVECEXP
(
addr
,
0
,
0
)
;
case
LABEL_REF
:
case
SYMBOL_REF
:
fprintf
(
file
,
"#"
)
;
default
:
output_addr_const
(
file
,
addr
)
;
break
;
}
}
</s>

A C compound statement to output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .


<s> bool AArch64TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { EVT VT1 = Val . getValueType ( ) ; if ( isZExtFree ( VT1 , VT2 ) ) { return true ; } if ( Val . getOpcode ( ) != ISD :: LOAD ) return false ; return ( VT1 . isSimple ( ) && ! VT1 . isVector ( ) && VT1 . isInteger ( ) && VT2 . isSimple ( ) && ! VT2 . isVector ( ) && VT2 . isInteger ( ) && VT1 . getSizeInBits ( ) <= 32 ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) || STI . isTargetWatchOS ( ) ) return true ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI . hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo . get ( ) ; } </s>

getRegInfo - Return information about the registers currently in use .


<s> static int aarch64_reduc_type ( vec_info * vinfo , stmt_vec_info stmt_info ) { if ( loop_vec_info loop_vinfo = dyn_cast < loop_vec_info > ( vinfo ) ) if ( STMT_VINFO_REDUC_DEF ( stmt_info ) ) { stmt_vec_info reduc_info = info_for_reduction ( loop_vinfo , stmt_info ) ; return int ( STMT_VINFO_REDUC_TYPE ( reduc_info ) ) ; } return - 1 ; } </s>

If STMT_INFO describes a reduction , return the type of reduction it describes , otherwise return -1 .


<s> unsigned PPCAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = 0 ; break ; case MCK_1 : ImmVal = 1 ; break ; case MCK_2 : ImmVal = 2 ; break ; case MCK_3 : ImmVal = 3 ; break ; default : return Match_InvalidOperand ; } PPCOperand & Op = static_cast < PPCOperand & > ( AsmOp ) ; if ( Op . isImm ( ) && Op . getImm ( ) == ImmVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


Value should be nonzero if functions must have frame pointers . Zero means the frame pointer need not be set up ( and parms may be accessed via the stack pointer ) in functions that seem suitable .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT ISD::AND ISD::OR


<s> static void csky_output_pic_addr_const ( FILE * stream , rtx x , int code ) { if ( GET_CODE ( x ) != UNSPEC ) return ; if ( UNSPEC_TLS == XINT ( x , 1 ) ) { return ; } csky_print_operand ( stream , XVECEXP ( x , 0 , 0 ) , code ) ; switch ( XINT ( x , 1 ) ) { case UNSPEC_PIC_SYMBOL_GOTOFF : fputs ( "@GOTOFF" , stream ) ; break ; case UNSPEC_PIC_SYMBOL_PLT : fputs ( "@PLT" , stream ) ; break ; case UNSPEC_PIC_SYMBOL_GOT : fputs ( "@GOT" , stream ) ; break ; case UNSPEC_PIC_SYMBOL_GOTPC : fputs ( "@GOTPC" , stream ) ; break ; case UNSPEC_PIC_SYMBOL_BSR : break ; default : break ; } } </s>

Print the UNSPEC operand in X to the STREAM .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: GPRCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) , PPC :: LR ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: G8RCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) , PPC :: LR8 ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


"virtual function multiversioning not supported"

Generate the dispatching code body to dispatch multi-versioned function DECL . The target hook is called to process the `` target '' attributes and provide the code to dispatch the right function at run-time . NODE points to the dispatcher decl whose body will be created .


<s> const MCSection * SystemZMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , MCSectionELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> void load_got_register ( void ) { if ( ! global_offset_table_rtx ) global_offset_table_rtx = gen_rtx_REG ( Pmode , GLOBAL_OFFSET_TABLE_REGNUM ) ; if ( TARGET_VXWORKS_RTP ) emit_insn ( gen_vxworks_load_got ( ) ) ; else { if ( ! got_helper_rtx ) { char name [ 32 ] ; get_pc_thunk_name ( name , GLOBAL_OFFSET_TABLE_REGNUM ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; } emit_insn ( gen_load_pcrel_sym ( global_offset_table_rtx , sparc_got ( ) , got_helper_rtx , GEN_INT ( GLOBAL_OFFSET_TABLE_REGNUM ) ) ) ; } emit_use ( global_offset_table_rtx ) ; } </s>


<s> static int find_gr_spill ( enum ia64_frame_regs r , int try_locals ) { int regno ; if ( emitted_frame_related_regs [ r ] != 0 ) { regno = emitted_frame_related_regs [ r ] ; if ( regno >= LOC_REG ( 0 ) && regno < LOC_REG ( 80 - frame_pointer_needed ) && current_frame_info . n_local_regs < regno - LOC_REG ( 0 ) + 1 ) current_frame_info . n_local_regs = regno - LOC_REG ( 0 ) + 1 ; else if ( crtl -> is_leaf && regno >= GR_REG ( 1 ) && regno <= GR_REG ( 31 ) ) current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } if ( crtl -> is_leaf ) { for ( regno = GR_REG ( 1 ) ; regno <= GR_REG ( 31 ) ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_used_regs [ regno ] && ! fixed_regs [ regno ] && ! global_regs [ regno ] && ( ( current_frame_info . gr_used_mask >> regno ) & 1 ) == 0 && ! is_emitted ( regno ) ) { current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } } if ( try_locals ) { regno = current_frame_info . n_local_regs ; while ( regno < ( 80 - frame_pointer_needed ) ) if ( ! is_emitted ( LOC_REG ( regno ++ ) ) ) { current_frame_info . n_local_regs = regno ; return LOC_REG ( regno - 1 ) ; } } return 0 ; } </s>

Helper function for ia64_compute_frame_size : find an appropriate general register to spill some special register to . SPECIAL_SPILL_MASK contains bits in GR0 to GR31 that have already been allocated by this routine . TRY_LOCALS is true if we should attempt to locate a local regnum .


<s> bool umips_load_store_pair_p ( bool load_p , rtx * operands ) { rtx reg1 , reg2 , mem1 , mem2 ; if ( load_p ) { reg1 = operands [ 0 ] ; reg2 = operands [ 2 ] ; mem1 = operands [ 1 ] ; mem2 = operands [ 3 ] ; } else { reg1 = operands [ 1 ] ; reg2 = operands [ 3 ] ; mem1 = operands [ 0 ] ; mem2 = operands [ 2 ] ; } if ( REGNO ( reg2 ) == REGNO ( reg1 ) + 1 ) return umips_load_store_pair_p_1 ( load_p , false , reg1 , mem1 , mem2 ) ; if ( REGNO ( reg1 ) == REGNO ( reg2 ) + 1 ) return umips_load_store_pair_p_1 ( load_p , true , reg2 , mem2 , mem1 ) ; return false ; } </s>

OPERANDS describes the operands to a pair of SETs , in the order dest1 , src1 , dest2 , src2 . Return true if the operands can be used in an LWP or SWP instruction ; LOAD_P says which .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
&&
GET_CODE
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
==
MEM
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
)
;
if
(
and_operation
!=
0
)
{
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
XEXP
(
mem
,
0
)
=
and_operation
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> bool VEFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>


<s> bool SparcTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createSparcISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static rtx push ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_push_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_push_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return NULL_RTX ; x = gen_push_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_push_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_push ( gen_rtx_REG ( SImode , rn ) ) ; x = frame_insn ( x ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) , 0 ) ; return x ; } </s>

Output RTL to push register RN onto the stack .


<s> static int rs6000_hard_regno_mode_ok_uncached ( int regno , machine_mode mode ) { int last_regno = regno + rs6000_hard_regno_nregs [ mode ] [ regno ] - 1 ; if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & 1 ) == 0 ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || mode == TImode || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) != 16 && ! reg_addr [ mode ] . scalar_in_vmx_p ) return 0 ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( FLOAT128_VECTOR_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % 2 ) == 0 ) && FP_REGNO_P ( last_regno ) ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return 1 ; if ( TARGET_P8_VECTOR && ( mode == SImode ) ) return 1 ; if ( TARGET_P9_VECTOR && ( mode == QImode || mode == HImode ) ) return 1 ; } if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return 1 ; return 0 ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> void Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool ARMTargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s>
void
mmix_asm_output_aligned_common
(
FILE
*
stream
,
const
char
*
name
,
int
size
,
int
align
)
{
fprintf
(
stream
,
"\t.comm\t"
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
",%u,%u ! mmixal-incompatible COMMON\n"
,
size
,
align
/
BITS_PER_UNIT
)
;
}
</s>

mmix
"\t.comm\t"
",%u,%u ! mmixal-incompatible COMMON\n"


<s> void rs6000_emit_popcount ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( dst ) ; rtx tmp1 , tmp2 ; if ( TARGET_POPCNTD ) { if ( mode == SImode ) emit_insn ( gen_popcntdsi2 ( dst , src ) ) ; else emit_insn ( gen_popcntddi2 ( dst , src ) ) ; return ; } tmp1 = gen_reg_rtx ( mode ) ; if ( mode == SImode ) { emit_insn ( gen_popcntbsi2 ( tmp1 , src ) ) ; tmp2 = expand_mult ( SImode , tmp1 , GEN_INT ( 0x01010101 ) , NULL_RTX , 0 ) ; tmp2 = force_reg ( SImode , tmp2 ) ; emit_insn ( gen_lshrsi3 ( dst , tmp2 , GEN_INT ( 24 ) ) ) ; } else { emit_insn ( gen_popcntbdi2 ( tmp1 , src ) ) ; tmp2 = expand_mult ( DImode , tmp1 , GEN_INT ( ( HOST_WIDE_INT ) 0x01010101 << 32 | 0x01010101 ) , NULL_RTX , 0 ) ; tmp2 = force_reg ( DImode , tmp2 ) ; emit_insn ( gen_lshrdi3 ( dst , tmp2 , GEN_INT ( 56 ) ) ) ; } } </s>

Emit popcount intrinsic on TARGET_POPCNTB ( Power5 ) and TARGET_POPCNTD ( Power7 ) targets . DST is the target , and SRC is the argument operand .


<s> Optional < uint64_t > X86MCInstrAnalysis :: evaluateMemoryOperandAddress ( const MCInst & Inst , uint64_t Addr , uint64_t Size ) const { const MCInstrDesc & MCID = Info -> get ( Inst . getOpcode ( ) ) ; int MemOpStart = X86II :: getMemoryOperandNo ( MCID . TSFlags ) ; if ( MemOpStart == - 1 ) return None ; MemOpStart += X86II :: getOperandBias ( MCID ) ; const MCOperand & SegReg = Inst . getOperand ( MemOpStart + X86 :: AddrSegmentReg ) ; const MCOperand & BaseReg = Inst . getOperand ( MemOpStart + X86 :: AddrBaseReg ) ; const MCOperand & IndexReg = Inst . getOperand ( MemOpStart + X86 :: AddrIndexReg ) ; const MCOperand & ScaleAmt = Inst . getOperand ( MemOpStart + X86 :: AddrScaleAmt ) ; const MCOperand & Disp = Inst . getOperand ( MemOpStart + X86 :: AddrDisp ) ; if ( SegReg . getReg ( ) != 0 || IndexReg . getReg ( ) != 0 || ScaleAmt . getImm ( ) != 1 || ! Disp . isImm ( ) ) return None ; if ( BaseReg . getReg ( ) == X86 :: RIP ) return Addr + Size + Disp . getImm ( ) ; return None ; } </s>

Given an instruction tries to get the address of a memory operand .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool LanaiMemAluCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( DisableMemAluCombiner ) return false ; TII = MF . getSubtarget < LanaiSubtarget > ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= combineMemAluInBasicBlock ( & MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
F2003fTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) && ! MF . getFunction ( ) -> hasAddressTaken ( ) ; } </s>

Return true if the function can safely be outlined from .


<s> static void nds32_emit_stack_push_multiple ( unsigned Rb , unsigned Re , bool save_fp_p , bool save_gp_p , bool save_lp_p , bool vaarg_p ) { unsigned regno ; int extra_count ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx push_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; rtx dwarf ; extra_count = 0 ; if ( save_fp_p ) extra_count ++ ; if ( save_gp_p ) extra_count ++ ; if ( save_lp_p ) extra_count ++ ; if ( Rb == SP_REGNUM && Re == SP_REGNUM ) num_use_regs = extra_count ; else num_use_regs = Re - Rb + 1 + extra_count ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = - ( num_use_regs * 4 ) ; for ( regno = Rb ; regno <= Re ; regno ++ ) { if ( regno == SP_REGNUM ) break ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } if ( save_fp_p ) { reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } if ( save_gp_p ) { reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } if ( save_lp_p ) { reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } offset = - ( num_use_regs * 4 ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; RTX_FRAME_RELATED_P ( adjust_sp_rtx ) = 1 ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; if ( vaarg_p ) { dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , copy_rtx ( adjust_sp_rtx ) , NULL_RTX ) ; REG_NOTES ( parallel_insn ) = dwarf ; } } </s>

Function to create a parallel rtx pattern which presents stack push multiple behavior . The overall concept are : `` push registers to memory '' , `` adjust stack pointer '' .


<s>
static
void
rs6000_output_savres_externs
(
FILE
*
file
)
{
rs6000_stack_t
*
info
=
rs6000_stack_info
(
)
;
if
(
TARGET_DEBUG_STACK
)
debug_stack_info
(
info
)
;
if
(
info
->
first_fp_reg_save
<
64
&&
!
TARGET_MACHO
&&
!
TARGET_ELF
)
{
char
*
name
;
int
regno
=
info
->
first_fp_reg_save
32
;
if
(
(
info
->
savres_strategy
&
SAVE_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
SAVE_NOINLINE_FPRS_SAVES_LR
)
!=
0
;
int
sel
=
SAVRES_SAVE
|
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
info
,
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
if
(
(
info
->
savres_strategy
&
REST_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
)
==
0
;
int
sel
=
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
info
,
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
}
}
</s>

Output .extern statements for the save/restore routines we use .


<s> static unsigned int rest_of_insert_bti ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx bti_insn ; rtx_insn * insn ; basic_block bb ; bb = 0 ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) { bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - 1 ; j >= 0 ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , 0 ) ) ; rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( aarch_bti_j_insn_p ( next ) ) continue ; bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch_pac_insn_p ( get_first_nonnote_insn ( ) ) ) { bti_insn = aarch_gen_bti_c ( ) ; emit_insn_before ( bti_insn , insn ) ; } } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>

This is implemented as a late RTL pass that runs before branch shortening and does the following .


"rs6000_can_change_mode_class, return %s, from = %s, "

Debug version of rs6000_can_change_mode_class .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> int pa_attr_length_millicode_call ( rtx_insn * insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) { if ( ! TARGET_LONG_CALLS && distance < 7600000 ) return 8 ; return 20 ; } else if ( TARGET_PORTABLE_RUNTIME ) return 24 ; else { if ( ! TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET ) return 8 ; if ( ! flag_pic ) return 12 ; return 24 ; } } </s>

Return the attribute length for the millicode call instruction INSN . The length must match the code generated by pa_output_millicode_call . We include the delay slot in the returned length as it is better to over estimate the length than to under estimate it .


<s> unsigned SparcInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: STri || MI -> getOpcode ( ) == SP :: STFri || MI -> getOpcode ( ) == SP :: STDFri ) { if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
static
void
x86_print_call_or_nop
(
FILE
*
file
,
const
char
*
target
)
{
if
(
flag_nop_mcount
)
fprintf
(
file
,
"1:\tnopl 0x00(%%eax,%%eax,1)\n"
)
;
else
fprintf
(
file
,
"1:\tcall\t%s\n"
,
target
)
;
}
</s>


<s> void aarch64_split_simd_move ( rtx dst , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { rtx ( * gen ) ( rtx , rtx ) ; gcc_assert ( VECTOR_MODE_P ( src_mode ) ) ; switch ( src_mode ) { case V16QImode : gen = gen_aarch64_split_simd_movv16qi ; break ; case V8HImode : gen = gen_aarch64_split_simd_movv8hi ; break ; case V4SImode : gen = gen_aarch64_split_simd_movv4si ; break ; case V2DImode : gen = gen_aarch64_split_simd_movv2di ; break ; case V4SFmode : gen = gen_aarch64_split_simd_movv4sf ; break ; case V2DFmode : gen = gen_aarch64_split_simd_movv2df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src ) ) ; return ; } } </s>


<s> void i386_pe_encode_section_info ( tree decl , rtx rtl , int first ) { rtx symbol ; int flags ; default_encode_section_info ( decl , rtl , first ) ; if ( ! MEM_P ( rtl ) ) return ; symbol = XEXP ( rtl , 0 ) ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; switch ( TREE_CODE ( decl ) ) { case FUNCTION_DECL : case VAR_DECL : break ; default : return ; } flags = ( SYMBOL_REF_FLAGS ( symbol ) & ~ ( SYMBOL_FLAG_DLLIMPORT | SYMBOL_FLAG_DLLEXPORT ) ) ; if ( i386_pe_determine_dllexport_p ( decl ) ) flags |= SYMBOL_FLAG_DLLEXPORT ; else if ( i386_pe_determine_dllimport_p ( decl ) ) flags |= SYMBOL_FLAG_DLLIMPORT ; SYMBOL_REF_FLAGS ( symbol ) = flags ; } </s>

Cover function to implement ENCODE_SECTION_INFO .


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == Lanai :: LDW_RI ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> int reg_unused_after ( rtx reg , rtx insn ) { enum rtx_code code , prev_code = UNKNOWN ; while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( prev_code == CALL_INSN && call_used_regs [ REGNO ( reg ) ] ) return 1 ; code = GET_CODE ( insn ) ; if ( GET_CODE ( insn ) == CODE_LABEL ) return 1 ; if ( INSN_P ( insn ) ) { rtx set = single_set ( insn ) ; int in_src = set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ; if ( set && in_src ) return 0 ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return 1 ; if ( set == 0 && reg_overlap_mentioned_p ( reg , PATTERN ( insn ) ) ) return 0 ; } prev_code = code ; } return 1 ; } </s>

Return nonzero if REG is not used after INSN . We assume REG is a reload reg , and therefore does not live past labels or calls or jumps .


<s> static void emit_soft_tfmode_libcall ( const char * func_name , int nargs , rtx * operands ) { rtx ret_slot = NULL , arg [ 3 ] , func_sym ; int i ; gcc_assert ( nargs == 2 || nargs == 3 ) ; for ( i = 0 ; i < nargs ; ++ i ) { rtx this_arg = operands [ i ] ; rtx this_slot ; if ( GET_MODE ( this_arg ) == TFmode ) { int force_stack_temp ; force_stack_temp = 0 ; if ( TARGET_BUGGY_QP_LIB && i == 0 ) force_stack_temp = 1 ; if ( GET_CODE ( this_arg ) == MEM && ! force_stack_temp ) { tree expr = MEM_EXPR ( this_arg ) ; if ( expr ) mark_addressable ( expr ) ; this_arg = XEXP ( this_arg , 0 ) ; } else if ( CONSTANT_P ( this_arg ) && ! force_stack_temp ) { this_slot = force_const_mem ( TFmode , this_arg ) ; this_arg = XEXP ( this_slot , 0 ) ; } else { this_slot = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; if ( i > 0 ) emit_move_insn ( this_slot , this_arg ) ; else ret_slot = this_slot ; this_arg = XEXP ( this_slot , 0 ) ; } } arg [ i ] = this_arg ; } func_sym = gen_rtx_SYMBOL_REF ( Pmode , func_name ) ; if ( GET_MODE ( operands [ 0 ] ) == TFmode ) { if ( nargs == 2 ) emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , 2 , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; else emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , 3 , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) , arg [ 2 ] , GET_MODE ( arg [ 2 ] ) ) ; if ( ret_slot ) emit_move_insn ( operands [ 0 ] , ret_slot ) ; } else { rtx ret ; gcc_assert ( nargs == 2 ) ; ret = emit_library_call_value ( func_sym , operands [ 0 ] , LCT_NORMAL , GET_MODE ( operands [ 0 ] ) , 1 , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; if ( ret != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , ret ) ; } } </s>

Generate a call to FUNC with OPERANDS . Operand 0 is the return value . Unlike normal calls , TFmode operands are passed by reference . It is assumed that no more than 3 operands are required .


"insertBranch must not be told to insert a fallthrough"

"Sparc branch conditions should have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> void rs6000_split_stack_space_check ( rtx size , rtx label ) { rtx sp = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx limit = gen_reg_rtx ( Pmode ) ; rtx requested = gen_reg_rtx ( Pmode ) ; rtx cmp = gen_reg_rtx ( CCUNSmode ) ; rtx jump ; emit_insn ( gen_load_split_stack_limit ( limit ) ) ; if ( CONST_INT_P ( size ) ) emit_insn ( gen_add3_insn ( requested , sp , GEN_INT ( - INTVAL ( size ) ) ) ) ; else { size = force_reg ( Pmode , size ) ; emit_move_insn ( requested , gen_rtx_MINUS ( Pmode , sp , size ) ) ; } emit_insn ( gen_rtx_SET ( cmp , gen_rtx_COMPARE ( CCUNSmode , requested , limit ) ) ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , cmp , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; jump = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( jump ) = label ; } </s>

Emit -fsplit-stack dynamic stack allocation space check .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> static rtx sparc_struct_value_rtx ( tree fndecl , int incoming ) { if ( TARGET_ARCH64 ) return NULL_RTX ; else { rtx mem ; if ( incoming ) mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; if ( incoming == 2 && sparc_std_struct_return && TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) && TREE_CODE ( TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ) == INTEGER_CST ) { rtx ret_reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx scratch = gen_reg_rtx ( SImode ) ; rtx_code_label * endlab = gen_label_rtx ( ) ; tree size = TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ; rtx size_rtx = GEN_INT ( TREE_INT_CST_LOW ( size ) & 0xfff ) ; rtx temp_val = assign_stack_local ( Pmode , TREE_INT_CST_LOW ( size ) , 0 ) ; emit_move_insn ( scratch , gen_rtx_MEM ( SImode , plus_constant ( Pmode , ret_reg , 8 ) ) ) ; emit_insn ( gen_add3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_cmp_and_jump_insns ( scratch , size_rtx , EQ , const0_rtx , SImode , 0 , endlab ) ; emit_insn ( gen_sub3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_move_insn ( mem , XEXP ( temp_val , 0 ) ) ; emit_label ( endlab ) ; } return mem ; } } </s>

Handle the TARGET_STRUCT_VALUE target hook . Return where to find the structure return value address .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( F . hasAvailableExternallyLinkage ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr & DefMI , unsigned DefIdx ) const override { return false ; } </s>

Compute operand latency of a def of 'Reg ' .


<s> static bool isAbsolute ( SDValue CmpOp , SDValue Pos , SDValue Neg ) { return ( Neg . getOpcode ( ) == ISD :: SUB && Neg . getOperand ( 0 ) . getOpcode ( ) == ISD :: Constant && cast < ConstantSDNode > ( Neg . getOperand ( 0 ) ) -> getZExtValue ( ) == 0 && Neg . getOperand ( 1 ) == Pos && ( Pos == CmpOp || ( Pos . getOpcode ( ) == ISD :: SIGN_EXTEND && Pos . getOperand ( 0 ) == CmpOp ) ) ) ; } </s>

Is this an absolute ( as opposed to relocatable ) value .


<s>
char
*
aarch64_output_sve_mov_immediate
(
rtx
const_vector
)
{
static
char
templ
[
40
]
;
struct
simd_immediate_info
info
;
char
element_char
;
bool
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
GET_MODE_BITSIZE
(
info
.
elt_mode
)
)
;
if
(
info
.
step
)
{
snprintf
(
templ
,
sizeof
(
templ
)
,
"index\t%%0.%c, #"
HOST_WIDE_INT_PRINT_DEC
", #"
HOST_WIDE_INT_PRINT_DEC
,
element_char
,
INTVAL
(
info
.
value
)
,
INTVAL
(
info
.
step
)
)
;
return
templ
;
}
if
(
GET_MODE_CLASS
(
info
.
elt_mode
)
==
MODE_FLOAT
)
{
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
const
int
buf_size
=
20
;
char
float_buf
[
buf_size
]
=
{
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
value
)
,
buf_size
,
buf_size
,
1
,
info
.
elt_mode
)
;
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%c, #%s"
,
element_char
,
float_buf
)
;
return
templ
;
}
}
snprintf
(
templ
,
sizeof
(
templ
)
,
"mov\t%%0.%c, #"
HOST_WIDE_INT_PRINT_DEC
,
element_char
,
INTVAL
(
info
.
value
)
)
;
return
templ
;
}
</s>

Return the output string to use for moving immediate CONST_VECTOR into an SVE register .


<s> static enum dispatch_group get_insn_group ( rtx_insn * insn ) { enum dispatch_group group = get_mem_group ( insn ) ; if ( group ) return group ; if ( is_branch ( insn ) ) return disp_branch ; if ( is_cmp ( insn ) ) return disp_cmp ; if ( has_immediate ( insn ) ) return disp_imm ; if ( is_prefetch ( insn ) ) return disp_prefetch ; return disp_no_group ; } </s>


<s> void Thumb2RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: t2LDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) ARMCC :: AL ) . addReg ( 0 ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void SystemZInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , Register SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( StoreOpcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool AArch64TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) return false ; if ( Ptr != Base ) return false ; AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> void xstormy16_expand_iorqi3 ( rtx * operands ) { rtx in , out , outsub , val ; out = operands [ 0 ] ; in = operands [ 1 ] ; val = operands [ 2 ] ; if ( xstormy16_onebit_set_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_iorqi3_internal ( out , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; return ; } if ( GET_CODE ( in ) != REG ) in = copy_to_mode_reg ( QImode , in ) ; if ( GET_CODE ( val ) != REG && GET_CODE ( val ) != CONST_INT ) val = copy_to_mode_reg ( QImode , val ) ; if ( GET_CODE ( out ) != REG ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , 0 ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , 0 ) ; if ( GET_CODE ( val ) != CONST_INT ) val = simplify_gen_subreg ( HImode , val , QImode , 0 ) ; emit_insn ( gen_iorhi3 ( outsub , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; } </s>

Expand an 8-bit IOR . This either detects the one case we can actually do , or uses a 16-bit IOR .


<s> static void arm_block_arith_comp_libfuncs_for_mode ( machine_mode mode ) { set_optab_libfunc ( add_optab , mode , NULL ) ; set_optab_libfunc ( sdiv_optab , mode , NULL ) ; set_optab_libfunc ( smul_optab , mode , NULL ) ; set_optab_libfunc ( neg_optab , mode , NULL ) ; set_optab_libfunc ( sub_optab , mode , NULL ) ; set_optab_libfunc ( eq_optab , mode , NULL ) ; set_optab_libfunc ( ne_optab , mode , NULL ) ; set_optab_libfunc ( lt_optab , mode , NULL ) ; set_optab_libfunc ( le_optab , mode , NULL ) ; set_optab_libfunc ( ge_optab , mode , NULL ) ; set_optab_libfunc ( gt_optab , mode , NULL ) ; set_optab_libfunc ( unord_optab , mode , NULL ) ; } </s>

Record that we have no arithmetic or comparison libfuncs for machine mode MODE .


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeAllocSizeInBits
(
SubVecTy
)
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> void aarch64_simd_emit_reg_reg_move ( rtx * operands , enum machine_mode mode , unsigned int count ) { unsigned int i ; int rdest = REGNO ( operands [ 0 ] ) ; int rsrc = REGNO ( operands [ 1 ] ) ; if ( ! reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) || rdest < rsrc ) for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + i ) , gen_rtx_REG ( mode , rsrc + i ) ) ; else for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + count - i - 1 ) , gen_rtx_REG ( mode , rsrc + count - i - 1 ) ) ; } </s>

Emit a register copy from operand to operand , taking care not to early-clobber source registers in the process . COUNT is the number of components into which the copy needs to be decomposed .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
RegName
=
[
]
(
unsigned
Reg
)
{
if
(
Reg
)
return
CSKYInstPrinter
::
getRegisterName
(
Reg
)
;
else
return
"noreg"
;
}
;
switch
(
Kind
)
{
case
CPOP
:
OS
<<
*
getConstpoolOp
(
)
;
break
;
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
KindTy
::
Register
:
OS
<<
"<register "
<<
RegName
(
getReg
(
)
)
<<
">"
;
break
;
case
RegisterSeq
:
OS
<<
"<register-seq "
;
OS
<<
RegName
(
getRegSeq
(
)
.
first
)
<<
"-"
<<
RegName
(
getRegSeq
(
)
.
second
)
<<
">"
;
break
;
case
RegisterList
:
OS
<<
"<register-list "
;
OS
<<
RegName
(
getRegList
(
)
.
List1From
)
<<
"-"
<<
RegName
(
getRegList
(
)
.
List1To
)
<<
","
;
OS
<<
RegName
(
getRegList
(
)
.
List2From
)
<<
"-"
<<
RegName
(
getRegList
(
)
.
List2To
)
<<
","
;
OS
<<
RegName
(
getRegList
(
)
.
List3From
)
<<
"-"
<<
RegName
(
getRegList
(
)
.
List3To
)
<<
","
;
OS
<<
RegName
(
getRegList
(
)
.
List4From
)
<<
"-"
<<
RegName
(
getRegList
(
)
.
List4To
)
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> const uint32_t * SHUXIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .