<s>
bool
AArch64InstrInfo
::
shouldClusterMemOps
(
MachineInstr
&
FirstLdSt
,
MachineInstr
&
SecondLdSt
,
unsigned
NumLoads
)
const
{
if
(
NumLoads
>
1
)
return
false
;
if
(
!
isPairableLdStInst
(
FirstLdSt
)
||
!
isPairableLdStInst
(
SecondLdSt
)
)
return
false
;
unsigned
FirstOpc
=
FirstLdSt
.
getOpcode
(
)
;
unsigned
SecondOpc
=
SecondLdSt
.
getOpcode
(
)
;
if
(
!
canPairLdStOpc
(
FirstOpc
,
SecondOpc
)
)
return
false
;
if
(
!
isCandidateToMergeOrPair
(
FirstLdSt
)
||
!
isCandidateToMergeOrPair
(
SecondLdSt
)
)
return
false
;
int64_t
Offset1
=
FirstLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
FirstOpc
)
&&
!
scaleOffset
(
FirstOpc
,
Offset1
)
)
return
false
;
int64_t
Offset2
=
SecondLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
SecondOpc
)
&&
!
scaleOffset
(
SecondOpc
,
Offset2
)
)
return
false
;
if
(
Offset1
>
63
||
Offset1
<
64
)
return
false
;
assert
(
Offset1
<=
Offset2
&&
"Caller should have ordered offsets."
)
;
return
Offset1
+
1
==
Offset2
;
}
</s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> int mips_idiv_insns ( machine_mode mode ) { int count ; count = 1 ; if ( TARGET_CHECK_ZERO_DIV ) { if ( GENERATE_DIVIDE_TRAPS && ! MSA_SUPPORTED_MODE_P ( mode ) ) count ++ ; else count += 2 ; } if ( TARGET_FIX_R4000 || TARGET_FIX_R4400 ) count ++ ; return count ; } </s>

Return the number of instructions needed for an integer division .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { DebugLoc DL = Orig -> getDebugLoc ( ) ; bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case X86 :: MOV8r0 : case X86 :: MOV16r0 : case X86 :: MOV32r0 : case X86 :: MOV64r0 : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : break ; case X86 :: MOV8r0 : Opc = X86 :: MOV8ri ; break ; case X86 :: MOV16r0 : Opc = X86 :: MOV16ri ; break ; case X86 :: MOV32r0 : Opc = X86 :: MOV32ri ; break ; case X86 :: MOV64r0 : Opc = X86 :: MOV64ri64i32 ; break ; } Clone = false ; } break ; } } if ( Clone ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } else { BuildMI ( MBB , I , DL , get ( Opc ) ) . addOperand ( Orig -> getOperand ( 0 ) ) . addImm ( 0 ) ; } MachineInstr * NewMI = prior ( I ) ; NewMI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> ignoreZeroFlag ( ) ) { addPass ( new IgnoreZeroFlag ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> performSDIVReplace ( ) ) { addPass ( new ReplaceSDIV ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixCallImmediates ( ) ) { addPass ( new FixCALL ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS ( ) ) { addPass ( new ReplaceFMULS ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> preventRoundChange ( ) ) { addPass ( new PreventRoundChange ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPsLoadStore ( ) ) { addPass ( new InsertNOPsLoadStore ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> flushCacheLineSWAP ( ) ) { addPass ( new FlushCacheLineSWAP ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPDoublePrecision ( ) ) { addPass ( new InsertNOPDoublePrecision ( getSparcTargetMachine ( ) ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc


"SIC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


"Trying MicroMips16 table (16-bit instructions):\n"

"Trying MicroMips32 table (32-bit instructions):\n"

"Trying COP3_ table (32-bit opcodes):\n"

"Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"

"Trying Mips32r6_64r6 table (32-bit opcodes):\n"

"Trying Mips64 (GPR64) table (32-bit opcodes):\n"

Returns the disassembly of a single instruction .


<s> static bool set_to_load_agen ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set ; out_set = single_set ( out_insn ) ; if ( out_set ) { in_set = single_set ( in_insn ) ; if ( in_set ) return reg_mentioned_p ( SET_DEST ( out_set ) , SET_SRC ( in_set ) ) ; } return false ; } </s>

The function returns true if out_inst sets a value that is used in the address generation computation of in_insn


<s> tree i386_pe_mangle_assembler_name ( const char * name ) { const char * skipped = name + ( * name == '*' ? 1 : 0 ) ; const char * stripped = targetm . strip_name_encoding ( skipped ) ; if ( * name != '*' && * user_label_prefix && * stripped != FASTCALL_PREFIX ) stripped = ACONCAT ( ( user_label_prefix , stripped , NULL ) ) ; return get_identifier ( stripped ) ; } </s>

This hook behaves the same as varasm.cc/assemble_name ( ) , but generates the name into memory rather than outputting it to a file stream .


<s> unsigned ARMBaseInstrInfo :: extraSizeToPredicateInstructions ( const MachineFunction & MF , unsigned NumInsts ) const { return Subtarget . isThumb2 ( ) ? divideCeil ( NumInsts , 4 ) * 2 : 0 ; } </s>

Return the increase in code size needed to predicate a contiguous run of NumInsts instructions .


<s> bool CAHPPassConfig :: addInstSelector ( ) { addPass ( createCAHPISelDag ( getCAHPTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void PPCOperand :: print ( raw_ostream & OS ) const { switch ( Kind ) { case Token : OS << "'" << getToken ( ) << "'" ; break ; case Immediate : OS << getImm ( ) ; break ; case Expression : getExpr ( ) -> print ( OS ) ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> int SystemZTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed ) { int Cost = getVectorIntrinsicInstrCost ( ID , RetTy ) ; if ( Cost != - 1 ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ProfileSummaryInfoWrapperPass > ( ) ; AU . addRequired < LazyMachineBlockFrequencyInfoPass > ( ) ; AU . addPreserved < LazyMachineBlockFrequencyInfoPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPPos ) ; Reserved . set ( Mips :: DSPSCount ) ; Reserved . set ( Mips :: DSPCarry ) ; Reserved . set ( Mips :: DSPEFI ) ; Reserved . set ( Mips :: DSPOutFlag ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VSTR_P0_off : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return ARM :: P0 ; } break ; case ARM :: VST1q64 : case ARM :: VST1d64TPseudo : case ARM :: VST1d64QPseudo : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


"rs6000_secondary_memory_needed, return: %s, from_class = %s, "

Debug version of rs6000_secondary_memory_needed .


<s> void MipsTargetELFStreamer :: emitDirectiveCpRestore ( SmallVector < MCInst , 3 > & StoreInsts , int Offset ) { MipsTargetStreamer :: emitDirectiveCpRestore ( StoreInsts , Offset ) ; if ( ! Pic || ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return ; for ( const MCInst & Inst : StoreInsts ) getStreamer ( ) . EmitInstruction ( Inst , STI ) ; } </s>


<s> bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const override { return true ; } </s>


<s> bool SparcTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { PM . add ( createSparcFPMoverPass ( * this ) ) ; PM . add ( createSparcDelaySlotFillerPass ( * this ) ) ; return true ; } </s>


<s> unsigned PPCFastISel :: fastEmit_i ( MVT Ty , MVT VT , unsigned Opc , uint64_t Imm ) { if ( Opc != ISD :: Constant ) return 0 ; if ( VT == MVT :: i1 && Subtarget -> useCRBits ( ) ) { Register ImmReg = createResultReg ( & PPC :: CRBITRCRegClass ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == 0 ? PPC :: CRUNSET : PPC :: CRSET ) , ImmReg ) ; return ImmReg ; } if ( VT != MVT :: i64 && VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 && VT != MVT :: i1 ) return 0 ; const TargetRegisterClass * RC = ( ( VT == MVT :: i64 ) ? & PPC :: G8RCRegClass : & PPC :: GPRCRegClass ) ; if ( VT == MVT :: i64 ) return PPCMaterialize64BitInt ( Imm , RC ) ; else return PPCMaterialize32BitInt ( Imm , RC ) ; } </s>

This method is called by target-independent code to request that an instruction with the given type , opcode , and immediate operand be emitted .


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: COND_S ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> void X86InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( X86 :: RET64 ) ) ; MBB . insert ( MBB . end ( ) , retq ) ; } </s>

Insert a custom frame for outlined functions .


<s> void OR1KTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( 0 , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == 0 ) { Result = DAG . getTargetConstant ( 0 , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < 16 > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= 31 ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < 32 > ( Val ) ) && ( ( Val & 0xffff ) == 0 ) ) { Result = DAG . getTargetConstant ( Val , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - 33554432 ) && ( Val <= 33554431 ) ) { Result = DAG . getTargetConstant ( Val , Op . getValueType ( ) ) ; break ; } } return ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createX86LowerAMXTypePass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
static
int
getMemScale
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
case
AArch64
::
STGOffset
:
case
AArch64
::
STZGOffset
:
case
AArch64
::
ST2GOffset
:
case
AArch64
::
STZ2GOffset
:
case
AArch64
::
STGPi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


runOnMachineFunction - Emit the function body .


<s> bool pa_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( from == to ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return true ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return true ; return false ; } </s>

Return true if a change from mode FROM to mode TO for a register in register class RCLASS is invalid .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getTarget ( ) . getTargetData ( ) ; TII = Fn . getTarget ( ) . getInstrInfo ( ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>


<s> static X86Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) ) { X86Operand * Res = new X86Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( this , nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; SmallVector < unsigned , 8 > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> static void ix86_avx256_split_vector_move_misalign ( rtx op0 , rtx op1 ) { rtx m ; rtx ( * extract ) ( rtx , rtx , rtx ) ; machine_mode mode ; if ( ( MEM_P ( op1 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_LOAD ) || ( MEM_P ( op0 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_STORE ) ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } rtx orig_op0 = NULL_RTX ; mode = GET_MODE ( op0 ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case E_V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case E_V16HFmode : extract = gen_avx_vextractf128v16hf ; mode = V8HFmode ; break ; case E_V8SFmode : extract = gen_avx_vextractf128v8sf ; mode = V4SFmode ; break ; case E_V4DFmode : extract = gen_avx_vextractf128v4df ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , 0 ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , 16 ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( MEM_P ( op0 ) ) { m = adjust_address ( op0 , mode , 0 ) ; emit_insn ( extract ( m , op1 , const0_rtx ) ) ; m = adjust_address ( op0 , mode , 16 ) ; emit_insn ( extract ( m , copy_rtx ( op1 ) , const1_rtx ) ) ; } else gcc_unreachable ( ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; } </s>

Split 32-byte AVX unaligned load and store if needed .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } if ( IDVal == ".mips_hack_stocg" ) return parseDirectiveMipsHackStocg ( ) ; if ( IDVal == ".mips_hack_elf_flags" ) return parseDirectiveMipsHackELFFlags ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : case CallingConv :: Swift : break ; } unsigned Idx = 1 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > 4 ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftSelf ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftError ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; Idx = 0 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & * I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> bool PPCTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < 16 > ( Imm ) || isUInt < 16 > ( Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> const MachineBasicBlock * getMBB ( ) const { return MBB ; } </s>

Return a reference to the basic block containing this bundle .


"inserting int3 after trailing call instruction:\n"


<s> bool X86OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) . hasOptSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool ix86_notrack_prefixed_insn_p ( rtx insn ) { if ( ! insn || ! ( ( flag_cf_protection & CF_BRANCH ) ) ) return false ; if ( CALL_P ( insn ) ) { rtx call = get_call_rtx_from ( insn ) ; gcc_assert ( call != NULL_RTX ) ; rtx addr = XEXP ( call , 0 ) ; if ( MEM_P ( addr ) && GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF ) return false ; else return find_reg_note ( insn , REG_CALL_NOCF_CHECK , 0 ) ; } if ( JUMP_P ( insn ) && ! flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) return false ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table ) ) return false ; else return true ; } return false ; } </s>

Return 1 if control tansfer instruction INSN should be encoded with notrack prefix .


<s> static int neon_endian_lane_map ( machine_mode mode , int lane ) { if ( BYTES_BIG_ENDIAN ) { int nelems = GET_MODE_NUNITS ( mode ) ; lane = ( nelems - 1 - lane ) ; if ( GET_MODE_SIZE ( mode ) == 16 ) lane = lane ^ ( nelems / 2 ) ; } return lane ; } </s>

Map lane ordering between architectural lane order , and GCC lane order , taking into account ABI . See comment above output_move_neon for details .


"List of x86 specific tuning parameter names:\n"

Helper function to set ix86_tune_features . IX86_TUNE is the processor type .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'Y' : case 'l' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_cpu_attr ) { case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return 2 ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return 5 ; case CPU_POWER8 : case CPU_POWER9 : return 7 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s> const MipsFrameLowering * MipsFrameLowering :: create ( const MipsSubtarget & ST ) { if ( ST . inMips16Mode ( ) ) return llvm :: createMips16FrameLowering ( ST ) ; return llvm :: createMipsSEFrameLowering ( ST ) ; } </s>


<s> virtual const MipsSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool Cpu0PassConfig :: addPreEmitPass ( ) { Cpu0TargetMachine & TM = getCpu0TargetMachine ( ) ; addPass ( createCpu0DelJmpPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> rtx extract_base_reg ( rtx_insn * insn ) { int post_update_rtx_index ; rtx mem_rtx ; rtx plus_rtx ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_SRC ( parallel_element ( insn , 0 ) ) ; break ; case TYPE_STORE_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_DEST ( parallel_element ( insn , 0 ) ) ; break ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case TYPE_FSTORE : mem_rtx = extract_mem_rtx ( insn ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( MEM_P ( mem_rtx ) ) ; if ( REG_P ( XEXP ( mem_rtx , 0 ) ) ) return XEXP ( mem_rtx , 0 ) ; plus_rtx = XEXP ( mem_rtx , 0 ) ; if ( GET_CODE ( plus_rtx ) == SYMBOL_REF || GET_CODE ( plus_rtx ) == CONST ) return NULL_RTX ; gcc_assert ( GET_CODE ( plus_rtx ) == PLUS || GET_CODE ( plus_rtx ) == POST_INC || GET_CODE ( plus_rtx ) == POST_DEC || GET_CODE ( plus_rtx ) == POST_MODIFY ) ; gcc_assert ( REG_P ( XEXP ( plus_rtx , 0 ) ) ) ; return XEXP ( plus_rtx , 0 ) ; } </s>

Extract the base register from load/store insns . The function returns NULL_RTX if the address is not consist of any registers .


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; APInt Mask = APInt :: getAllOnesValue ( VT . getScalarType ( ) . getSizeInBits ( ) ) ; DAG . ComputeMaskedBits ( SDValue ( N , 0 ) , Mask , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s> bool systemSupportsUnalignedAccess ( unsigned AS = 0 ) const { return hasMips32r6 ( ) ; } </s>

Does the system support unaligned memory access .


<s> outliner :: OutlinedFunction ARMBaseInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { outliner :: Candidate & FirstCand = RepeatedSequenceLocs [ 0 ] ; unsigned SequenceSize = std :: accumulate ( FirstCand . front ( ) , std :: next ( FirstCand . back ( ) ) , 0 , [ this ] ( unsigned Sum , const MachineInstr & MI ) { return Sum + getInstSizeInBytes ( MI ) ; } ) ; unsigned FlagsSetInAll = 0xF ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; std :: for_each ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ & FlagsSetInAll ] ( outliner :: Candidate & C ) { FlagsSetInAll &= C . Flags ; } ) ; auto CantGuaranteeValueAcrossCall = [ & TRI ] ( outliner :: Candidate & C ) { if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( ARM :: R12 ) || ! LRU . available ( ARM :: CPSR ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { RepeatedSequenceLocs . erase ( std :: remove_if ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , CantGuaranteeValueAcrossCall ) , RepeatedSequenceLocs . end ( ) ) ; if ( RepeatedSequenceLocs . size ( ) < 2 ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ 0 ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; auto Costs = std :: make_unique < OutlinerCosts > ( Subtarget ) ; unsigned FrameID = 0 ; unsigned NumBytesToCreateFrame = 0 ; if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs -> FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs -> CallTailCall ) ; } else if ( LastInstrOpcode == ARM :: BL || LastInstrOpcode == ARM :: BLX || LastInstrOpcode == ARM :: tBL || LastInstrOpcode == ARM :: tBLXr || LastInstrOpcode == ARM :: tBLXi ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs -> FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs -> CallThunk ) ; } else return outliner :: OutlinedFunction ( ) ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , NumBytesToCreateFrame , FrameID ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Lanai Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; HasPWRPSR = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"Unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
ParseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"Unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather ) Gathers . push_back ( II ) ; else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter ) Scatters . push_back ( II ) ; } } bool Changed = false ; for ( IntrinsicInst * I : Gathers ) Changed |= lowerGather ( I ) ; for ( IntrinsicInst * I : Scatters ) Changed |= lowerScatter ( I ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroName = ( V && V -> isNullValue ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> static unsigned int insn_is_load_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { if ( MEM_P ( SET_SRC ( body ) ) ) return 1 ; if ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 1 ; if ( pattern_is_rotate64 ( body ) && MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 1 ; return 0 ; } if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && MEM_P ( SET_SRC ( set ) ) ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a load insn , including permuting loads that represent an lvxd2x instruction ; else return 0 .


<s>
Register
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
else
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
static
void
record_loads
(
tag_map_t
&
tag_map
,
struct
loop
*
loop
)
{
rtx_insn
*
insn
;
basic_block
*
body
,
bb
;
body
=
get_loop_body
(
loop
)
;
for
(
unsigned
i
=
0
;
i
<
loop
->
num_nodes
;
i
++
)
{
bb
=
body
[
i
]
;
FOR_BB_INSNS
(
bb
,
insn
)
{
rtx
base
=
NULL_RTX
;
rtx
dest
=
NULL_RTX
;
rtx
offset
=
NULL_RTX
;
bool
writeback
=
false
;
bool
ldp
=
false
;
if
(
!
INSN_P
(
insn
)
||
DEBUG_INSN_P
(
insn
)
)
continue
;
if
(
get_load_info
(
insn
,
loop
,
&
dest
,
&
base
,
&
offset
,
&
writeback
,
&
ldp
)
)
{
tag_insn_info
*
i
=
new
tag_insn_info
(
insn
,
dest
,
base
,
offset
,
writeback
,
ldp
)
;
rtx
tag
=
GEN_INT
(
i
->
tag
(
)
)
;
tag_map
.
get_or_insert
(
tag
)
.
safe_push
(
i
)
;
}
}
}
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Loop %d: Tag map generated.\n"
,
loop
->
num
)
;
tag_map
.
traverse
<
void
*
,
dump_insn_list
>
(
)
;
}
tag_map
.
traverse
<
void
*
,
single_dest_per_chain
>
(
)
;
}
</s>

Record all loads in LOOP into TAG_MAP indexed by the falkor hardware prefetcher memory tags .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; TL = TM . getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; if ( isThumb1 ) { delete RS ; return false ; } bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ; int fp_reg_size = 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , gen_rtx_REG ( reg_mode , LR_REGNO ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , NULL ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } if ( bitmap_bit_p ( components , 2 ) ) { rtx reg = gen_rtx_REG ( reg_mode , TOC_REGNUM ) ; rtx sp_reg = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_frame_store ( reg , sp_reg , RS6000_TOC_SAVE_SLOT ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += fp_reg_size ; } } </s>


<s> rtx legitimize_tls_address ( rtx x , rtx reg ) { rtx dest , tp , label , labelno , sum , ret , eqv , addend ; rtx_insn * insns ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; } return dest ; case TLS_MODEL_LOCAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? 8 : 4 ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; reg = force_reg ( SImode , gen_rtx_CONST ( SImode , reg ) ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; default : abort ( ) ; } } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> static inline bool offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , HOST_WIDE_INT offset ) { return offset >= - 256 && offset < 256 ; } </s>

Return true if OFFSET is a signed 9-bit value .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! DefMI . getParent ( ) ) return Latency ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; Register Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( Register :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI . isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> unsigned constant_generates_xxspltidp ( vec_const_128bit_type * vsx_const ) { if ( ! TARGET_SPLAT_FLOAT_CONSTANT || ! TARGET_PREFIXED || ! TARGET_VSX ) return 0 ; if ( ! vsx_const -> all_double_words_same ) return 0 ; if ( vsx_const -> all_bytes_same || vsx_const -> all_half_words_same || vsx_const -> all_words_same ) return 0 ; unsigned HOST_WIDE_INT value = vsx_const -> double_words [ 0 ] ; if ( value != RS6000_CONST_DF_NAN && value != RS6000_CONST_DF_NANS && value != RS6000_CONST_DF_INF && value != RS6000_CONST_DF_NEG_INF ) { int df_exponent = ( value >> 52 ) & 0x7ff ; unsigned HOST_WIDE_INT df_mantissa = value & ( ( HOST_WIDE_INT_1U << 52 ) - HOST_WIDE_INT_1U ) ; if ( df_exponent == 0x7ff && df_mantissa != 0 ) return 0 ; if ( df_exponent == 0 && df_mantissa != 0 ) return 0 ; } long df_words [ 2 ] = { vsx_const -> words [ 0 ] , vsx_const -> words [ 1 ] } ; if ( ! BYTES_BIG_ENDIAN ) std :: swap ( df_words [ 0 ] , df_words [ 1 ] ) ; REAL_VALUE_TYPE rv_type ; real_from_target ( & rv_type , df_words , DFmode ) ; const REAL_VALUE_TYPE * rv = & rv_type ; if ( ! exact_real_truncate ( SFmode , rv ) ) return 0 ; long sf_value ; real_to_target ( & sf_value , rv , SFmode ) ; long sf_exponent = ( sf_value >> 23 ) & 0xFF ; long sf_mantissa = sf_value & 0x7FFFFF ; if ( sf_exponent == 0 && sf_mantissa != 0 ) return 0 ; return sf_value ; } </s>

Determine if a vector constant can be loaded with XXSPLTIDP . Return zero if the XXSPLTIDP instruction can not be used . Otherwise return the immediate value to be used with the XXSPLTIDP instruction .


<s> enum ix86_fpcmp_strategy ix86_fp_comparison_strategy ( enum rtx_code ) { if ( TARGET_CMOVE ) return IX86_FPCMP_COMI ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) return IX86_FPCMP_SAHF ; return IX86_FPCMP_ARITH ; } </s>

Return strategy to use for floating-point . We assume that fcomi is always preferrable where available , since that is also true when looking at size ( 2 bytes , vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test ) .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void VEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; DebugLoc DL ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VEInstrInfo & TII = * STI . getInstrInfo ( ) ; uint64_t NumBytes = MFI . getStackSize ( ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( VE :: ORri ) , VE :: SX11 ) . addReg ( VE :: SX9 ) . addImm ( 0 ) ; } else { emitSPAdjustment ( MF , MBB , MBBI , NumBytes , None ) ; } emitEpilogueInsns ( MF , MBB , MBBI , NumBytes , true ) ; } </s>

VE VE VE VE VE VE::ORri VE::SX11 VE::SX9 0


<s> static bool ix86_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) return true ; if ( TARGET_MMX && VALID_MMX_REG_MODE ( mode ) ) return true ; if ( TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW ( mode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Lanai load / store optimization pass"
;
}
</s>

Lanai
"Lanai load / store optimization pass"


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( cfun -> machine -> split_stack_argp_used ) add_to_hard_reg_set ( & set -> set , Pmode , 12 ) ; } </s>

Add r30 to hard reg set if the prologue sets it up and it is not pic_offset_table_rtx .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool AArch64TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return false ; int64_t Val = Imm . getSExtValue ( ) ; if ( Val == 0 || AArch64_AM :: isLogicalImmediate ( Val , BitSize ) ) return true ; if ( ( int64_t ) Val < 0 ) Val = ~ Val ; if ( BitSize == 32 ) Val &= ( 1LL << 32 ) - 1 ; unsigned LZ = countLeadingZeros ( ( uint64_t ) Val ) ; unsigned Shift = ( 63 - LZ ) / 16 ; return Shift < 3 ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> void AArch64PassConfig :: addPreEmitPass2 ( ) { addPass ( createUnpackMachineBundles ( nullptr ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case MVT :: f64 : case MVT :: v2f64 : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void rs6000_emit_swdivdf ( rtx res , rtx n , rtx d ) { rtx x0 , e0 , e1 , e2 , y1 , y2 , y3 , u0 , v0 , one ; x0 = gen_reg_rtx ( DFmode ) ; e0 = gen_reg_rtx ( DFmode ) ; e1 = gen_reg_rtx ( DFmode ) ; e2 = gen_reg_rtx ( DFmode ) ; y1 = gen_reg_rtx ( DFmode ) ; y2 = gen_reg_rtx ( DFmode ) ; y3 = gen_reg_rtx ( DFmode ) ; u0 = gen_reg_rtx ( DFmode ) ; v0 = gen_reg_rtx ( DFmode ) ; one = force_reg ( DFmode , CONST_DOUBLE_FROM_REAL_VALUE ( dconst1 , DFmode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( DFmode , gen_rtvec ( 1 , d ) , UNSPEC_FRES ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MINUS ( DFmode , one , gen_rtx_MULT ( SFmode , d , x0 ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , y1 , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , e0 , x0 ) , x0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_MULT ( DFmode , e0 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , y2 , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , e1 , y1 ) , y1 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e2 , gen_rtx_MULT ( DFmode , e1 , e1 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , y3 , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , e2 , y2 ) , y2 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , u0 , gen_rtx_MULT ( DFmode , n , y3 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , v0 , gen_rtx_MINUS ( DFmode , n , gen_rtx_MULT ( DFmode , d , u0 ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , v0 , y3 ) , u0 ) ) ) ; } </s>

Newton-Raphson approximation of double-precision floating point divide n/d . Assumes no trapping math and finite arguments .


"GCC does not currently support mixed size types "

"GCC does not currently support return type %qT "

"unsupported return type %qT for %<simd%> functions"

"GCC does not currently support argument type %qT "

"GCC does not currently support simdlen %d for type %qT"


"invalid argument to built-in function %s"

Return true if OPVAL can be used for operand OPNUM of instruction ICODE . The instruction should require a constant operand of some sort . The function prints an error if OPVAL is not valid .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
unsigned
Dialect
=
getMAIAssemblerDialect
(
)
;
FeatureBitset
MissingFeatures
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MissingFeatures
,
MatchingInlineAsm
,
Dialect
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
MissingFeatures
.
any
(
)
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
for
(
unsigned
I
=
0
,
E
=
MissingFeatures
.
size
(
)
;
I
!=
E
;
++
I
)
{
if
(
MissingFeatures
[
I
]
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
I
)
;
}
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
SystemZMnemonicSpellCheck
(
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
,
Dialect
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

SystemZ
SystemZ
"Unknown missing feature!"
"instruction requires:"
0
" "
0ULL
"too few operands for instruction"
SystemZ
"invalid operand for instruction"
SystemZ
SystemZ
0
"invalid instruction"
SystemZ
0
"Unexpected match type"


<s> virtual const MipsSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool ARMTargetLowering :: shouldFoldConstantShiftPairToMask ( const SDNode * N , CombineLevel Level ) const { if ( ! Subtarget -> isThumb1Only ( ) ) return true ; if ( Level == BeforeLegalizeTypes ) return true ; return false ; } </s>

Return true if it is profitable to fold a pair of shifts into a mask .


<s> static rtx safe_vector_operand ( rtx x , enum machine_mode mode ) { if ( x != const0_rtx ) return x ; x = gen_reg_rtx ( mode ) ; emit_insn ( gen_iwmmxt_clrdi ( mode == DImode ? x : gen_rtx_SUBREG ( DImode , x , 0 ) ) ) ; return x ; } </s>

Errors in the source file can cause expand_expr to return const0_rtx where we expect a vector . To avoid crashing , use one of the vector clear instructions .


<s> LLT AArch64TargetLowering :: getOptimalMemOpLLT ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = IsMemset && Size < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , 16 ) ) return LLT :: vector ( 2 , 64 ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , 16 ) ) return LLT :: scalar ( 128 ) ; if ( Size >= 8 && AlignmentIsAcceptable ( MVT :: i64 , 8 ) ) return LLT :: scalar ( 64 ) ; if ( Size >= 4 && AlignmentIsAcceptable ( MVT :: i32 , 4 ) ) return LLT :: scalar ( 32 ) ; return LLT ( ) ; } </s>


"After expanding ARM pseudo instructions."

runOnMachineFunction - Emit the function body .


"MMIX DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


"RelaxInstruction() is not implemented yet"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static bool arm_fdpic_local_funcdesc_p ( rtx fnx ) { tree fn ; enum symbol_visibility vis ; bool ret ; if ( ! TARGET_FDPIC ) return true ; if ( ! SYMBOL_REF_LOCAL_P ( fnx ) ) return false ; fn = SYMBOL_REF_DECL ( fnx ) ; if ( ! fn ) return false ; vis = DECL_VISIBILITY ( fn ) ; if ( vis == VISIBILITY_PROTECTED ) DECL_VISIBILITY ( fn ) = VISIBILITY_DEFAULT ; ret = default_binds_local_p_1 ( fn , flag_pic ) ; DECL_VISIBILITY ( fn ) = vis ; return ret ; } </s>

Test whether a local function descriptor is canonical , i.e. , whether we can use GOTOFFFUNCDESC to compute the address of the function .


<s> int loongarch_class_max_nregs ( enum reg_class rclass , machine_mode mode ) { int size ; HARD_REG_SET left ; size = 0x8000 ; left = reg_class_contents [ rclass ] ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FCC_REGS ] ) ) { if ( loongarch_hard_regno_mode_ok ( FCC_REG_FIRST , mode ) ) size = MIN ( size , 4 ) ; left &= ~ reg_class_contents [ FCC_REGS ] ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( loongarch_hard_regno_mode_ok ( FP_REG_FIRST , mode ) ) size = MIN ( size , UNITS_PER_FPREG ) ; left &= ~ reg_class_contents [ FP_REGS ] ; } if ( ! hard_reg_set_empty_p ( left ) ) size = MIN ( size , UNITS_PER_WORD ) ; return ( GET_MODE_SIZE ( mode ) + size - 1 ) / size ; } </s>

Implement CLASS_MAX_NREGS , taking the maximum of the cases in loongarch_hard_regno_nregs .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const ARMBaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , ARMCC :: CondCodes Pred = ARMCC :: AL , unsigned PredReg = 0 ) { if ( isARM ) emitARMRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARMCC::CondCodes ARMCC::AL 0 ARM ARM ARM::SP ARM::SP ARM::SP ARM::SP


"builtin function %qs is only valid for the cell processor"

"builtin function %qs requires the %qs option"

"builtin function %qs requires the %qs and %qs options"

"builtin function %qs requires ISA 3.0 IEEE 128-bit floating point"

"builtin function %qs requires the %qs (or newer), and "

"builtin function %qs is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , unsigned nelt , rtx perm [ ] ) { machine_mode imode ; rtx x ; imode = vmode ; if ( GET_MODE_CLASS ( vmode ) != MODE_VECTOR_INT ) { imode = GET_MODE_INNER ( vmode ) ; imode = mode_for_size ( GET_MODE_BITSIZE ( imode ) , MODE_INT , 0 ) ; imode = mode_for_vector ( imode , nelt ) ; } x = gen_rtx_CONST_VECTOR ( imode , gen_rtvec_v ( nelt , perm ) ) ; x = expand_vec_perm ( vmode , op0 , op1 , x , target ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave .


<s> int ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Imm . getActiveBits ( ) >= 64 ) return 4 ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( Bits == 8 || ( SImmVal >= 0 && SImmVal < 256 ) ) return 1 ; if ( ( ~ SImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static inline bool is_naked_func ( const_tree decl ) { return has_func_attr ( decl , "naked" ) ; } </s>

Returns true if the provided function has the `` naked '' attribute .


<s> bool ARMTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { if ( Level == BeforeLegalizeTypes ) return true ; if ( N -> getOpcode ( ) != ISD :: SHL ) return true ; if ( Subtarget -> isThumb1Only ( ) ) { if ( N -> getOpcode ( ) != ISD :: SHL ) return true ; SDValue N1 = N -> getOperand ( 0 ) ; if ( N1 -> getOpcode ( ) != ISD :: ADD && N1 -> getOpcode ( ) != ISD :: AND && N1 -> getOpcode ( ) != ISD :: OR && N1 -> getOpcode ( ) != ISD :: XOR ) return true ; if ( auto * Const = dyn_cast < ConstantSDNode > ( N1 -> getOperand ( 1 ) ) ) { if ( Const -> getAPIntValue ( ) . ult ( 256 ) ) return false ; if ( N1 -> getOpcode ( ) == ISD :: ADD && Const -> getAPIntValue ( ) . slt ( 0 ) && Const -> getAPIntValue ( ) . sgt ( - 256 ) ) return false ; } return true ; } return false ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s> InstructionCost AArch64TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( 1 ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF , I -> getFunction ( ) ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> static bool mips_expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt ) { machine_mode v2mode ; rtx x ; if ( ! GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) . exists ( & v2mode ) ) return false ; x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return mips_expand_vselect ( target , x , perm , nelt ) ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . hasStandardEncoding ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> void i386_pe_seh_init ( FILE * f ) { struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; gcc_assert ( ! stack_realign_drap ) ; seh = XCNEW ( struct seh_frame_state ) ; cfun -> machine -> seh = seh ; seh -> sp_offset = INCOMING_FRAME_SP_OFFSET ; seh -> cfa_offset = INCOMING_FRAME_SP_OFFSET ; seh -> cfa_reg = stack_pointer_rtx ; fputs ( "\t.seh_proc\t" , f ) ; assemble_name ( f , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( cfun -> decl ) ) ) ; fputc ( '\n' , f ) ; } </s>

Set up data structures beginning output for SEH .


<s>
void
rs6000_va_start
(
tree
valist
,
rtx
nextarg
)
{
HOST_WIDE_INT
words
,
n_gpr
,
n_fpr
;
tree
f_gpr
,
f_fpr
,
f_res
,
f_ovf
,
f_sav
;
tree
gpr
,
fpr
,
ovf
,
sav
,
t
;
if
(
DEFAULT_ABI
!=
ABI_V4
)
{
std_expand_builtin_va_start
(
valist
,
nextarg
)
;
return
;
}
f_gpr
=
TYPE_FIELDS
(
TREE_TYPE
(
va_list_type_node
)
)
;
f_fpr
=
TREE_CHAIN
(
f_gpr
)
;
f_res
=
TREE_CHAIN
(
f_fpr
)
;
f_ovf
=
TREE_CHAIN
(
f_res
)
;
f_sav
=
TREE_CHAIN
(
f_ovf
)
;
valist
=
build_va_arg_indirect_ref
(
valist
)
;
gpr
=
build
(
COMPONENT_REF
,
TREE_TYPE
(
f_gpr
)
,
valist
,
f_gpr
,
NULL_TREE
)
;
fpr
=
build
(
COMPONENT_REF
,
TREE_TYPE
(
f_fpr
)
,
valist
,
f_fpr
,
NULL_TREE
)
;
ovf
=
build
(
COMPONENT_REF
,
TREE_TYPE
(
f_ovf
)
,
valist
,
f_ovf
,
NULL_TREE
)
;
sav
=
build
(
COMPONENT_REF
,
TREE_TYPE
(
f_sav
)
,
valist
,
f_sav
,
NULL_TREE
)
;
words
=
current_function_args_info
.
words
;
n_gpr
=
MIN
(
current_function_args_info
.
sysv_gregno
GP_ARG_MIN_REG
,
GP_ARG_NUM_REG
)
;
n_fpr
=
MIN
(
current_function_args_info
.
fregno
FP_ARG_MIN_REG
,
FP_ARG_NUM_REG
)
;
if
(
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"va_start: words = "
HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
HOST_WIDE_INT_PRINT_DEC
", n_fpr = "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
words
,
n_gpr
,
n_fpr
)
;
if
(
cfun
->
va_list_gpr_size
)
{
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
gpr
)
,
gpr
,
build_int_cst
(
NULL_TREE
,
n_gpr
)
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
if
(
cfun
->
va_list_fpr_size
)
{
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
fpr
)
,
fpr
,
build_int_cst
(
NULL_TREE
,
n_fpr
)
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
t
=
make_tree
(
TREE_TYPE
(
ovf
)
,
virtual_incoming_args_rtx
)
;
if
(
words
!=
0
)
t
=
build
(
PLUS_EXPR
,
TREE_TYPE
(
ovf
)
,
t
,
build_int_cst
(
NULL_TREE
,
words
*
UNITS_PER_WORD
)
)
;
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
ovf
)
,
ovf
,
t
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
if
(
!
cfun
->
va_list_gpr_size
&&
!
cfun
->
va_list_fpr_size
&&
n_gpr
<
GP_ARG_NUM_REG
&&
n_fpr
<
FP_ARG_V4_MAX_REG
)
return
;
t
=
make_tree
(
TREE_TYPE
(
sav
)
,
virtual_stack_vars_rtx
)
;
if
(
cfun
->
machine
->
varargs_save_offset
)
t
=
build
(
PLUS_EXPR
,
TREE_TYPE
(
sav
)
,
t
,
build_int_cst
(
NULL_TREE
,
cfun
->
machine
->
varargs_save_offset
)
)
;
t
=
build
(
MODIFY_EXPR
,
TREE_TYPE
(
sav
)
,
sav
,
t
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
</s>


<s> static rtx aarch64_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST . Assume that the move expanders can handle all moves if ! can_create_pseudo_p ( ) . The distinction is important because , unlike emit_move_insn , the move expanders know how to force Pmode objects into the constant pool even when the constant pool address is not itself legitimate .


"Unable to generate load/store offset for fusion"

Emit a D-form load or store instruction that is the second instruction of a fusion sequence .


<s>
void
CSKYInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
SrcReg
,
bool
IsKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
CSKYMachineFunctionInfo
*
CFI
=
MF
.
getInfo
<
CSKYMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
ST32W
;
}
else
if
(
CSKY
::
CARRYRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
SPILL_CARRY
;
CFI
->
setSpillsCR
(
)
;
}
else
{
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
IsKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static unsigned int csky_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( regno >= CSKY_FIRST_VFP_REGNUM && ! CSKY_TARGET_ARCH ( CK803 ) ) return 1 ; else return CSKY_NUM_REGS ( mode ) ; } </s>


<s> static rtx mmix_function_arg_1 ( const cumulative_args_t argsp_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED , bool incoming ) { CUMULATIVE_ARGS * argsp = get_cumulative_args ( argsp_v ) ; if ( type == void_type_node ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS && ! targetm . calls . must_pass_in_stack ( mode , type ) && ( GET_MODE_BITSIZE ( mode ) <= 64 || argsp -> lib || TARGET_LIBFUNC ) ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; } </s>

Helper function for mmix_function_arg and mmix_function_incoming_arg .


<s> bool AArch64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> write32 ( 0xd503201f ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool AArch64InstrInfo :: isFpOrNEON ( const MachineInstr & MI ) { auto IsFPR = [ & ] ( const MachineOperand & Op ) { if ( ! Op . isReg ( ) ) return false ; auto Reg = Op . getReg ( ) ; if ( Reg . isPhysical ( ) ) return AArch64 :: FPR128RegClass . contains ( Reg ) || AArch64 :: FPR64RegClass . contains ( Reg ) || AArch64 :: FPR32RegClass . contains ( Reg ) || AArch64 :: FPR16RegClass . contains ( Reg ) || AArch64 :: FPR8RegClass . contains ( Reg ) ; const TargetRegisterClass * TRC = :: getRegClass ( MI , Reg ) ; return TRC == & AArch64 :: FPR128RegClass || TRC == & AArch64 :: FPR128_loRegClass || TRC == & AArch64 :: FPR64RegClass || TRC == & AArch64 :: FPR64_loRegClass || TRC == & AArch64 :: FPR32RegClass || TRC == & AArch64 :: FPR16RegClass || TRC == & AArch64 :: FPR8RegClass ; } ; return llvm :: any_of ( MI . operands ( ) , IsFPR ) ; } </s>

Returns whether the instruction is FP or NEON .


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) { if ( TARGET_POWERPC64 ) { if ( size == 8 ) return true ; if ( size == 16 && TARGET_P9_VECTOR && mode != TDmode ) return true ; } if ( TARGET_P8_VECTOR ) { if ( mode == SImode ) return true ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> static char * detect_caches_darwin ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; size_t len = 4 ; static int l1_size_name [ 2 ] = { CTL_HW , HW_L1DCACHESIZE } ; static int l1_line_name [ 2 ] = { CTL_HW , HW_CACHELINE } ; static int l2_size_name [ 2 ] = { CTL_HW , HW_L2CACHESIZE } ; sysctl ( l1_size_name , 2 , & l1_sizekb , & len , NULL , 0 ) ; sysctl ( l1_line_name , 2 , & l1_line , & len , NULL , 0 ) ; sysctl ( l2_size_name , 2 , & l2_sizekb , & len , NULL , 0 ) ; l1_assoc = 0 ; return describe_cache ( l1_sizekb / 1024 , l1_line , l1_assoc , l2_sizekb / 1024 ) ; } </s>

Returns the description of caches on Darwin .


"Unknown architecture specific memory model"

"HLE_ACQUIRE not used with ACQUIRE or stronger memory model"

"HLE_RELEASE not used with RELEASE or stronger memory model"

Validate target specific memory model bits in VAL .


"TRUE - Frame size is too large for D-Form.\n"

"TRUE - Not fixed frame object that requires "

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool SystemZTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( UseSoftFloat || ( VT != MVT :: f32 && VT != MVT :: f64 ) ) return false ; return Imm . isZero ( ) || Imm . isNegZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool ARMTargetLowering :: isTruncateFree ( EVT SrcVT , EVT DstVT ) const { if ( SrcVT . isVector ( ) || DstVT . isVector ( ) || ! SrcVT . isInteger ( ) || ! DstVT . isInteger ( ) ) return false ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; unsigned DestBits = DstVT . getSizeInBits ( ) ; return ( SrcBits == 64 && DestBits == 32 ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void neon_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true ; rtx x , mem ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONSTANT_P ( x ) ) ++ n_var , one_var = i ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { rtx constant = neon_make_constant ( vals ) ; if ( constant != NULL_RTX ) { emit_move_insn ( target , constant ) ; return ; } } if ( all_same && GET_MODE_SIZE ( inner_mode ) <= 4 ) { x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , 0 , 0 ) ) ; emit_insn ( gen_rtx_SET ( target , gen_vec_duplicate ( mode , x ) ) ) ; return ; } if ( n_var == 1 ) { rtx copy = copy_rtx ( vals ) ; rtx merge_mask = GEN_INT ( 1 << one_var ) ; XVECEXP ( copy , 0 , one_var ) = XVECEXP ( vals , 0 , ( one_var + 1 ) % n_elts ) ; neon_expand_vector_init ( target , copy ) ; x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , 0 , one_var ) ) ; emit_insn ( gen_vec_set_internal ( mode , target , x , merge_mask , target ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; for ( i = 0 ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , 0 , i ) ) ; emit_move_insn ( target , mem ) ; } </s>


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v32i8 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return MVT :: i8 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v16i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> static void sparc_emit_set_const64_longway ( rtx op0 , rtx temp , unsigned HOST_WIDE_INT high_bits , unsigned HOST_WIDE_INT low_bits ) { rtx sub_temp = op0 ; if ( can_create_pseudo_p ( ) ) sub_temp = gen_reg_rtx ( DImode ) ; if ( ( high_bits & 0xfffffc00 ) != 0 ) { emit_insn ( gen_safe_HIGH64 ( temp , high_bits ) ) ; if ( ( high_bits & ~ 0xfffffc00 ) != 0 ) emit_insn ( gen_rtx_SET ( sub_temp , gen_safe_OR64 ( temp , ( high_bits & 0x3ff ) ) ) ) ; else sub_temp = temp ; } else { emit_insn ( gen_safe_SET64 ( temp , high_bits ) ) ; sub_temp = temp ; } if ( can_create_pseudo_p ( ) ) { rtx temp2 = gen_reg_rtx ( DImode ) ; rtx temp3 = gen_reg_rtx ( DImode ) ; rtx temp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_SET ( temp4 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( 32 ) ) ) ) ; emit_insn ( gen_safe_HIGH64 ( temp2 , low_bits ) ) ; if ( ( low_bits & ~ 0xfffffc00 ) != 0 ) { emit_insn ( gen_rtx_SET ( temp3 , gen_safe_OR64 ( temp2 , ( low_bits & 0x3ff ) ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_PLUS ( DImode , temp4 , temp3 ) ) ) ; } else { emit_insn ( gen_rtx_SET ( op0 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; } } else { rtx low1 = GEN_INT ( ( low_bits >> ( 32 - 12 ) ) & 0xfff ) ; rtx low2 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 ) ) & 0xfff ) ; rtx low3 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 - 8 ) ) & 0x0ff ) ; int to_shift = 12 ; if ( low1 != const0_rtx ) { emit_insn ( gen_rtx_SET ( op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( DImode , op0 , low1 ) ) ) ; sub_temp = op0 ; to_shift = 12 ; } else { to_shift += 12 ; } if ( low2 != const0_rtx ) { emit_insn ( gen_rtx_SET ( op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( DImode , op0 , low2 ) ) ) ; sub_temp = op0 ; to_shift = 8 ; } else { to_shift += 8 ; } emit_insn ( gen_rtx_SET ( op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; if ( low3 != const0_rtx ) emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( DImode , op0 , low3 ) ) ) ; } } </s>

Full 64-bit constant decomposition . Even though this is the 'worst ' case , we still optimize a few things away .


<s> const MipsMCExpr * MipsMCExpr :: create ( MipsMCExpr :: MipsExprKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) MipsMCExpr ( Kind , Expr ) ; } </s>


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx_insn * rs6000_frame_related ( rtx_insn * insn , rtx reg , HOST_WIDE_INT val , rtx reg2 , rtx repl2 ) { rtx repl ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) { gcc_checking_assert ( val == 0 ) ; repl = NULL_RTX ; } else repl = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ; rtx pat = PATTERN ( insn ) ; if ( ! repl && ! reg2 ) { if ( GET_CODE ( pat ) == PARALLEL ) for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } set_used_flags ( pat ) ; if ( GET_CODE ( pat ) == SET ) { if ( repl ) pat = simplify_replace_rtx ( pat , reg , repl ) ; if ( reg2 ) pat = simplify_replace_rtx ( pat , reg2 , repl2 ) ; } else if ( GET_CODE ( pat ) == PARALLEL ) { pat = shallow_copy_rtx ( pat ) ; XVEC ( pat , 0 ) = shallow_copy_rtvec ( XVEC ( pat , 0 ) ) ; for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( repl ) set = simplify_replace_rtx ( set , reg , repl ) ; if ( reg2 ) set = simplify_replace_rtx ( set , reg2 , repl2 ) ; XVECEXP ( pat , 0 , i ) = set ; if ( ! REG_P ( SET_SRC ( set ) ) || ! fixed_reg_p ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } } else gcc_unreachable ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , copy_rtx_if_shared ( pat ) ) ; return insn ; } </s>

Add to 'insn ' a note which is PATTERN ( INSN ) but with REG replaced with ( plus : P ( reg 1 ) VAL ) , and with REG2 replaced with RREG if REG2 is not NULL . It would be nice if dwarf2out_frame_debug_expr could deduce these equivalences by itself so it was n't necessary to hold its hand so much . Do n't be tempted to always supply d2_f_d_e with the actual cfa register , ie . r31 when we are using a hard frame pointer . That fails when saving regs off r1 , and sched moves the r31 setup past the reg saves .


<s> const TargetRegisterClass * ARM64RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & ARM64 :: GPR64RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> int arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && TARGET_VFP && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; return FALSE ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return FALSE ; if ( TARGET_THUMB2 ) return TRUE ; return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return FALSE ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> TargetIRAnalysis LanaiTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( LanaiTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> bool X86InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV32rm : case X86 :: MOV64rm : case X86 :: LD_Fp64m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MOVAPSrm : case X86 :: MOVUPSrm : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: MOVDQUrm : case X86 :: VMOVSSrm : case X86 :: VMOVSDrm : case X86 :: VMOVAPSrm : case X86 :: VMOVUPSrm : case X86 :: VMOVAPDrm : case X86 :: VMOVDQArm : case X86 :: VMOVDQUrm : case X86 :: VMOVAPSYrm : case X86 :: VMOVUPSYrm : case X86 :: VMOVAPDYrm : case X86 :: VMOVDQAYrm : case X86 :: VMOVDQUYrm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : case X86 :: FsVMOVAPSrm : case X86 :: FsVMOVAPDrm : case X86 :: FsMOVAPSrm : case X86 :: FsMOVAPDrm : { if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 3 ) . getReg ( ) == 0 && MI -> isInvariantLoad ( AA ) ) { unsigned BaseReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( BaseReg == 0 || BaseReg == X86 :: RIP ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( 4 ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case X86 :: LEA32r : case X86 :: LEA64r : { if ( MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 3 ) . getReg ( ) == 0 && ! MI -> getOperand ( 4 ) . isReg ( ) ) { if ( ! MI -> getOperand ( 1 ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( BaseReg == 0 ) return true ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } } return true ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> void loongarch_init_builtins ( void ) { const struct loongarch_builtin_description * d ; unsigned int i ; tree type ; for ( i = 0 ; i < ARRAY_SIZE ( loongarch_builtins ) ; i ++ ) { d = & loongarch_builtins [ i ] ; if ( d -> avail ( ) ) { type = loongarch_build_function_type ( d -> function_type ) ; loongarch_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; loongarch_get_builtin_decl_index [ d -> icode ] = i ; } } } </s>


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != 16 || Alignment <= 2 || Ty == LLT :: vector ( 2 , 64 ) ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const LC3InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void gen_shifty_hi_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; void ( * gen_fun ) ( int , int , rtx ) ; value &= 31 ; if ( value == 0 ) { emit_insn ( gen_nop ( ) ) ; return ; } gen_fun = GET_MODE ( operands [ 0 ] ) == HImode ? gen_ashift_hi : gen_ashift ; if ( code == ASHIFT ) { max = ext_ashl_lshr_seq [ value ] . insn_count ; for ( i = 0 ; i < max ; i ++ ) gen_fun ( code , ext_ashl_lshr_seq [ value ] . amount [ i ] , operands [ 0 ] ) ; } else for ( i = ext_ashl_lshr_seq [ value ] . insn_count - 1 ; i >= 0 ; i -- ) gen_fun ( code , ext_ashl_lshr_seq [ value ] . amount [ i ] , operands [ 0 ] ) ; } </s>

Same as above , but optimized for values where the topmost bits do n't matter .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> InstructionCost ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Imm . getActiveBits ( ) >= 64 ) return 4 ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( Bits == 8 || ( SImmVal >= 0 && SImmVal < 256 ) ) return 1 ; if ( ( ~ SImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .