<s>
TargetLowering
::
AtomicExpansionKind
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
.
is64Bit
(
)
64
:
32
;
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
{
return
needsCmpXchgNb
(
MemType
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
}
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
return
AtomicExpansionKind
::
CmpXChg
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MipsSubtarget & Subtarget = MF -> getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_SaveList ; return CSR_O32_SaveList ; } </s>


<s> const MCExpr * X86_64MachoTargetObjectFile :: getIndirectSymViaGOTPCRel ( const MCSymbol * Sym , const MCValue & MV , int64_t Offset , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { unsigned FinalOff = Offset + MV . getConstant ( ) + 4 ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Off = MCConstantExpr :: Create ( FinalOff , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Off , getContext ( ) ) ; } </s>

Get the target specific PC relative GOT entry relocation .


<s> bool AArch64TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasFnAttr ( Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s>
static
void
adjust_extract
(
rtx_insn
*
insn
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
rtx
src
=
SET_SRC
(
pattern
)
;
rtx
sel
=
GET_CODE
(
src
)
==
VEC_DUPLICATE
XEXP
(
src
,
0
)
:
src
;
rtx
par
=
XEXP
(
sel
,
1
)
;
int
half_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
XEXP
(
sel
,
0
)
)
)
>>
1
;
int
lane
=
INTVAL
(
XVECEXP
(
par
,
0
,
0
)
)
;
lane
=
lane
>=
half_elts
lane
half_elts
:
lane
+
half_elts
;
XVECEXP
(
par
,
0
,
0
)
=
GEN_INT
(
lane
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lane for extract %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a vector extract operation , adjust the index of the extracted lane to account for the doubleword swap .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".cpu" ) return parseDirectiveCPU ( Loc ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == ".ltorg" || IDVal == ".pool" ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( Loc ) ; if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) return parseDirectiveInst ( Loc ) ; } return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void gen_shifty_hi_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; void ( * gen_fun ) ( int , int , rtx ) ; value &= 31 ; if ( value == 0 ) { emit_insn ( gen_nop ( ) ) ; return ; } gen_fun = GET_MODE ( operands [ 0 ] ) == HImode ? gen_ashift_hi : gen_ashift ; if ( code == ASHIFT ) { max = ext_shift_insns [ value ] ; for ( i = 0 ; i < max ; i ++ ) gen_fun ( code , ext_shift_amounts [ value ] [ i ] , operands [ 0 ] ) ; } else for ( i = ext_shift_insns [ value ] - 1 ; i >= 0 ; i -- ) gen_fun ( code , ext_shift_amounts [ value ] [ i ] , operands [ 0 ] ) ; } </s>

Same as above , but optimized for values where the topmost bits do n't matter .


"interrupt Service Routines cannot be coded in Thumb mode"

Generate the rest of a function 's prologue .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s>
void
PPCMIPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
MRI
=
&
MF
->
getRegInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
TII
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"*** PowerPC MI peephole pass ***\n\n"
)
;
DEBUG
(
MF
->
dump
(
)
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

PowerPC
PPC
PPC
"*** PowerPC MI peephole pass ***\n\n"


<s>
static
char
*
match_identifier
(
void
)
{
int
lastpos
=
pos
1
;
while
(
lastpos
<
LINELEN
1
&&
(
isalnum
(
linebuf
[
lastpos
+
1
]
)
||
linebuf
[
lastpos
+
1
]
==
'_'
)
)
++
lastpos
;
if
(
lastpos
>=
LINELEN
1
)
{
diag
(
lastpos
,
"line length overrun.\n"
)
;
exit
(
1
)
;
}
if
(
lastpos
<
pos
)
return
0
;
char
*
buf
=
(
char
*
)
malloc
(
lastpos
pos
+
2
)
;
memcpy
(
buf
,
&
linebuf
[
pos
]
,
lastpos
pos
+
1
)
;
buf
[
lastpos
pos
+
1
]
=
'\0'
;
pos
=
lastpos
+
1
;
return
buf
;
}
</s>

Match an identifier , returning NULL on failure , else a pointer to a buffer containing the identifier .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCSection * ARMElfTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { if ( isExecuteOnlyFunction ( GO , SK , TM ) ) SK = SectionKind :: getExecuteOnly ( ) ; return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK , TM ) ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


"%qE attribute only applies to interrupt functions"

Generate 'handle_interrupt ' attribute for decls


<s>
SDValue
LEGTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_LEG
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
LEGISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void load_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx dest = gen_rtx_REG ( word_mode , reg ) ; rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx src ; if ( VAL_14_BITS_P ( disp ) ) src = gen_rtx_MEM ( word_mode , plus_constant ( basereg , disp ) ) ; else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; if ( TARGET_DISABLE_INDEXING ) { emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; src = gen_rtx_MEM ( word_mode , tmpreg ) ; } else src = gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; } else { rtx delta = GEN_INT ( disp ) ; rtx high = gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , high ) ; src = gen_rtx_MEM ( word_mode , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; } emit_move_insn ( dest , src ) ; } </s>

Emit RTL to load REG from the memory location specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns .


<s> bool OR1KAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OW -> Write32 ( 0x15000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::POST_INC ISD::POST_DEC


Write PATCH_AREA_SIZE NOPs into the asm outfile FILE around a function entry . If RECORD_P is true and the target supports named sections , the location of the NOPs will be recorded in a special object section called `` __patchable_function_entries '' . This routine may be called twice per function to put NOPs before and after the function entry .


<s> bool X86PassConfig :: addPostRegAlloc ( ) { addPass ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool CJGFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static bool ix86_libgcc_floating_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case SFmode : case DFmode : case XFmode : return true ; case TFmode : return false ; return TARGET_LONG_DOUBLE_128 ; return true ; default : return false ; } } </s>

Implement target hook libgcc_floating_mode_supported_p .


<s> static const char * sparc_mangle_type ( const_tree type ) { if ( TARGET_ARCH32 && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


<s> Optional < uint64_t > ARMMCInstrAnalysis :: evaluateMemoryOperandAddress ( const MCInst & Inst , const MCSubtargetInfo * STI , uint64_t Addr , uint64_t Size ) const { const MCInstrDesc & Desc = Info -> get ( Inst . getOpcode ( ) ) ; if ( ! Desc . mayLoad ( ) ) return None ; uint64_t TSFlags = Desc . TSFlags ; unsigned IndexMode = ( TSFlags & ARMII :: IndexModeMask ) >> ARMII :: IndexModeShift ; if ( IndexMode != ARMII :: IndexModeNone ) return None ; unsigned OpIndex = Desc . NumDefs ; while ( OpIndex < Desc . getNumOperands ( ) && Desc . OpInfo [ OpIndex ] . OperandType != MCOI :: OPERAND_MEMORY ) ++ OpIndex ; if ( OpIndex == Desc . getNumOperands ( ) ) return None ; Addr &= ~ 0x3 ; switch ( Desc . TSFlags & ARMII :: FormMask ) { default : Addr += 8 ; break ; case ARMII :: ThumbFrm : Addr += 4 ; break ; case ARMII :: VFPLdStFrm : Addr += STI -> getFeatureBits ( ) [ ARM :: ModeThumb ] ? 4 : 8 ; break ; } unsigned AddrMode = ( TSFlags & ARMII :: AddrModeMask ) ; switch ( AddrMode ) { default : return None ; case ARMII :: AddrMode_i12 : return evaluateMemOpAddrForAddrMode_i12 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrMode3 : return evaluateMemOpAddrForAddrMode3 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrMode5 : return evaluateMemOpAddrForAddrMode5 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrMode5FP16 : return evaluateMemOpAddrForAddrMode5FP16 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrModeT2_i8s4 : return evaluateMemOpAddrForAddrModeT2_i8s4 ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrModeT2_pc : return evaluateMemOpAddrForAddrModeT2_pc ( Inst , Desc , OpIndex , Addr ) ; case ARMII :: AddrModeT1_s : return evaluateMemOpAddrForAddrModeT1_s ( Inst , Desc , OpIndex , Addr ) ; } } </s>

Given an instruction tries to get the address of a memory operand .


<s> bool Mips16FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isInt < 15 > ( MFI -> getMaxCallFrameSize ( ) ) && ! MFI -> hasVarSizedObjects ( ) ; } </s>


<s> bool PPCTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { if ( ! VT . isScalarInteger ( ) ) return false ; if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { if ( ! ConstNode -> getAPIntValue ( ) . isSignedIntN ( 64 ) ) return false ; int64_t Imm = ConstNode -> getSExtValue ( ) ; unsigned Shift = countTrailingZeros < uint64_t > ( Imm ) ; Imm >>= Shift ; if ( isInt < 16 > ( Imm ) ) return false ; uint64_t UImm = static_cast < uint64_t > ( Imm ) ; if ( isPowerOf2_64 ( UImm + 1 ) || isPowerOf2_64 ( UImm - 1 ) || isPowerOf2_64 ( 1 - UImm ) || isPowerOf2_64 ( - 1 - UImm ) ) return true ; } return false ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> static bool mips_reversed_fp_cond ( enum rtx_code * code ) { switch ( * code ) { case NE : case LTGT : case ORDERED : * code = reverse_condition_maybe_unordered ( * code ) ; return true ; default : return false ; } } </s>

Convert * CODE into a code that can be used in a floating-point scc instruction ( C.cond.fmt ) . Return true if the values of the condition code registers will be inverted , with 0 indicating that the condition holds .


<s> const char * Cpu0TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Cpu0ISD :: JmpLink : return "Cpu0ISD::JmpLink" ; case Cpu0ISD :: TailCall : return "Cpu0ISD::TailCall" ; case Cpu0ISD :: Hi : return "Cpu0ISD::Hi" ; case Cpu0ISD :: Lo : return "Cpu0ISD::Lo" ; case Cpu0ISD :: GPRel : return "Cpu0ISD::GPRel" ; case Cpu0ISD :: Ret : return "Cpu0ISD::Ret" ; case Cpu0ISD :: EH_RETURN : return "Cpu0ISD::EH_RETURN" ; case Cpu0ISD :: DivRem : return "Cpu0ISD::DivRem" ; case Cpu0ISD :: DivRemU : return "Cpu0ISD::DivRemU" ; case Cpu0ISD :: Wrapper : return "Cpu0ISD::Wrapper" ; case Cpu0ISD :: Sync : return "Cpu0ISD::Sync" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool rs6000_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict ) { bool reg_offset_p = reg_offset_addressing_ok_p ( mode ) ; bool quad_offset_p = mode_supports_vsx_dform_quad ( mode ) ; if ( VECTOR_MEM_ALTIVEC_P ( mode ) && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == - 16 ) x = XEXP ( x , 0 ) ; if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return 0 ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) ) return 1 ; if ( quad_offset_p ) { if ( quad_address_p ( x , mode , reg_ok_strict ) ) return 1 ; } else if ( virtual_stack_registers_memory_p ( x ) ) return 1 ; else if ( reg_offset_p ) { if ( legitimate_small_data_p ( mode , x ) ) return 1 ; if ( legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return 1 ; if ( reg_addr [ mode ] . fused_toc && GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_FUSION_ADDIS ) return 1 ; } if ( mode == TImode && TARGET_VSX ) return 0 ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == REG && ( XEXP ( x , 0 ) == virtual_stack_vars_rtx || XEXP ( x , 0 ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) return 1 ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return 1 ; if ( ! FLOAT128_2REG_P ( mode ) && ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , 1 ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , 1 ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) return 1 ; if ( reg_offset_p && ! quad_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return 1 ; return 0 ; } </s>

TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . On the RS/6000 , there are four valid address : a SYMBOL_REF that refers to a constant pool entry of an address ( or the sum of it plus a constant ) , a short ( 16-bit signed ) constant plus a register , the sum of two registers , or a register indirect , possibly with an auto-increment . For DFmode , DDmode and DImode with a constant plus register , we must ensure that both words are addressable or PowerPC64 with offset word aligned . For modes spanning multiple registers ( DFmode and DDmode in 32-bit GPRs , 32-bit DImode , TImode , TFmode , TDmode ) , indexed addressing can not be used because adjacent memory cells are accessed by adding word-sized offsets during assembly output .


<s> static int ia64_spec_check_src_p ( rtx src ) { if ( GET_CODE ( src ) == IF_THEN_ELSE ) { rtx t ; t = XEXP ( src , 0 ) ; if ( GET_CODE ( t ) == NE ) { t = XEXP ( t , 0 ) ; if ( GET_CODE ( t ) == UNSPEC ) { int code ; code = XINT ( t , 1 ) ; if ( code == UNSPEC_LDCCLR || code == UNSPEC_LDCNC || code == UNSPEC_CHKACLR || code == UNSPEC_CHKANC || code == UNSPEC_CHKS ) { gcc_assert ( code != 0 ) ; return code ; } } } } return 0 ; } </s>

Return nonzero , if SRC belongs to recovery check .


<s> static void compute_save_world_info ( rs6000_stack_t * info ) { info -> world_save_p = 1 ; info -> world_save_p = ( WORLD_SAVE_P ( info ) && DEFAULT_ABI == ABI_DARWIN && ! cfun -> has_nonlocal_label && info -> first_fp_reg_save == FIRST_SAVED_FP_REGNO && info -> first_gp_reg_save == FIRST_SAVED_GP_REGNO && info -> first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info -> cr_save_p ) ; if ( WORLD_SAVE_P ( info ) ) { rtx_insn * insn ; for ( insn = get_last_insn_anywhere ( ) ; insn ; insn = PREV_INSN ( insn ) ) if ( CALL_P ( insn ) && SIBLING_CALL_P ( insn ) ) { info -> world_save_p = 0 ; break ; } } if ( WORLD_SAVE_P ( info ) ) { info -> vrsave_size = 4 ; info -> lr_save_p = 1 ; if ( info -> vrsave_mask == 0 ) info -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info -> first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ; } return ; } </s>

For a very restricted set of circumstances , we can cut down the size of prologues/epilogues by calling our own save/restore-the-world routines .


<s>
void
PPCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
if
(
PPC
::
F8RCRegClass
.
contains
(
DestReg
)
&&
PPC
::
VSLRCRegClass
.
contains
(
SrcReg
)
)
{
unsigned
SuperReg
=
TRI
->
getMatchingSuperReg
(
DestReg
,
PPC
::
sub_64
,
&
PPC
::
VSRCRegClass
)
;
if
(
SrcReg
==
SuperReg
)
return
;
DestReg
=
SuperReg
;
}
else
if
(
PPC
::
VRRCRegClass
.
contains
(
DestReg
)
&&
PPC
::
VSHRCRegClass
.
contains
(
SrcReg
)
)
{
unsigned
SuperReg
=
TRI
->
getMatchingSuperReg
(
DestReg
,
PPC
::
sub_128
,
&
PPC
::
VSRCRegClass
)
;
if
(
SrcReg
==
SuperReg
)
return
;
DestReg
=
SuperReg
;
}
else
if
(
PPC
::
F8RCRegClass
.
contains
(
SrcReg
)
&&
PPC
::
VSLRCRegClass
.
contains
(
DestReg
)
)
{
unsigned
SuperReg
=
TRI
->
getMatchingSuperReg
(
SrcReg
,
PPC
::
sub_64
,
&
PPC
::
VSRCRegClass
)
;
if
(
DestReg
==
SuperReg
)
return
;
SrcReg
=
SuperReg
;
}
else
if
(
PPC
::
VRRCRegClass
.
contains
(
SrcReg
)
&&
PPC
::
VSHRCRegClass
.
contains
(
DestReg
)
)
{
unsigned
SuperReg
=
TRI
->
getMatchingSuperReg
(
SrcReg
,
PPC
::
sub_128
,
&
PPC
::
VSRCRegClass
)
;
if
(
DestReg
==
SuperReg
)
return
;
SrcReg
=
SuperReg
;
}
unsigned
Opc
;
if
(
PPC
::
GPRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR
;
else
if
(
PPC
::
G8RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR8
;
else
if
(
PPC
::
F4RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
FMR
;
else
if
(
PPC
::
CRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
MCRF
;
else
if
(
PPC
::
VRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
VOR
;
else
if
(
PPC
::
VSRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
XXLOR
;
else
if
(
PPC
::
CRBITRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
CROR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
const
MCInstrDesc
&
MCID
=
get
(
Opc
)
;
if
(
MCID
.
getNumOperands
(
)
==
3
)
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DestReg
)
.
addReg
(
SrcReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

PowerPC
PPC
PPC::F8RCRegClass
PPC::VSLRCRegClass
PPC::sub_64
PPC::VSRCRegClass
PPC::VRRCRegClass
PPC::VSHRCRegClass
PPC::sub_128
PPC::VSRCRegClass
PPC::F8RCRegClass
PPC::VSLRCRegClass
PPC::sub_64
PPC::VSRCRegClass
PPC::VRRCRegClass
PPC::VSHRCRegClass
PPC::sub_128
PPC::VSRCRegClass
PPC::GPRCRegClass
PPC::OR
PPC::G8RCRegClass
PPC::OR8
PPC::F4RCRegClass
PPC::FMR
PPC::CRRCRegClass
PPC::MCRF
PPC::VRRCRegClass
PPC::VOR
PPC::VSRCRegClass
PPC::XXLOR
PPC::CRBITRCRegClass
PPC::CROR
"Impossible reg-to-reg copy"
3


<s>
const
char
*
output_mov_long_double_arm_from_fpa
(
rtx
*
operands
)
{
int
arm_reg0
=
REGNO
(
operands
[
0
]
)
;
rtx
ops
[
3
]
;
gcc_assert
(
arm_reg0
!=
IP_REGNUM
)
;
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
arm_reg0
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
1
+
arm_reg0
)
;
ops
[
2
]
=
gen_rtx_REG
(
SImode
,
2
+
arm_reg0
)
;
output_asm_insn
(
"stf%?e\t%1, [%|sp, #-12]!"
,
operands
)
;
output_asm_insn
(
"ldm%?fd\t%|sp!, {%0, %1, %2}"
,
ops
)
;
return
""
;
}
</s>

Output a move from an fpa register to arm registers . OPERANDS [ 0 ] is the first registers of an arm register pair . OPERANDS [ 1 ] is an fpa register .


<s> bool PPCRegisterInfo :: isCallerPreservedPhysReg ( unsigned PhysReg , const MachineFunction & MF ) const { assert ( TargetRegisterInfo :: isPhysicalRegister ( PhysReg ) ) ; if ( TM . isELFv2ABI ( ) && PhysReg == PPC :: X2 ) { return ( getReservedRegs ( MF ) . test ( PPC :: X2 ) ) ; } else { return false ; } } </s>

Physical registers that may be modified within a function but are guaranteed to be restored before any uses .


<s> static bool ia64_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( reg_classes_intersect_p ( rclass , BR_REGS ) ) return from == to ; if ( SCALAR_FLOAT_MODE_P ( from ) != SCALAR_FLOAT_MODE_P ( to ) ) return ! reg_classes_intersect_p ( rclass , FR_REGS ) ; return true ; } </s>

Implement TARGET_CAN_CHANGE_MODE_CLASS . In BR regs , we ca n't change the DImode at all . In FP regs , we ca n't change FP values to integer values and vice versa , but we can change e.g . DImode to SImode , and V2SFmode into DImode .


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ) return false ; TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; const TargetRegisterClass * RC = & X86 :: VR256RegClass ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , 0 ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , 0 ) ; while ( 1 ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMipsExpandPseudoPass ( ) ) ; addPass ( createMicroMipsSizeReducePass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsBranchExpansion ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool insn_defines_reg ( unsigned int regno1 , unsigned int regno2 , rtx_insn * insn ) { df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) if ( DF_REF_REG_DEF_P ( def ) && ! DF_REF_IS_ARTIFICIAL ( def ) && ( regno1 == DF_REF_REGNO ( def ) || regno2 == DF_REF_REGNO ( def ) ) ) return true ; return false ; } </s>

Function checks if instruction INSN defines register number REGNO1 or REGNO2 .


<s> static void dump_constants ( struct mips16_constant * constants , rtx insn ) { struct mips16_constant * c , * next ; int align ; align = 0 ; for ( c = constants ; c != NULL ; c = next ) { if ( align < GET_MODE_SIZE ( c -> mode ) ) { int align_log = floor_log2 ( GET_MODE_SIZE ( c -> mode ) ) ; insn = emit_insn_after ( gen_align ( GEN_INT ( align_log ) ) , insn ) ; } align = GET_MODE_SIZE ( c -> mode ) ; insn = emit_label_after ( c -> label , insn ) ; insn = dump_constants_1 ( c -> mode , c -> value , insn ) ; next = c -> next ; free ( c ) ; } emit_barrier_after ( insn ) ; } </s>

Dump out the constants in CONSTANTS after INSN .


<s>
static
void
make_type_sizeless
(
tree
type
)
{
TYPE_ATTRIBUTES
(
type
)
=
tree_cons
(
get_identifier
(
"SVE sizeless type"
)
,
NULL_TREE
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>


<s> bool PPCTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { if ( AM . BaseOffs <= - ( 1LL << 16 ) || AM . BaseOffs >= ( 1LL << 16 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool X86TargetLowering :: decomposeMulByConstant ( EVT VT , SDValue C ) const { APInt MulC ; if ( ! ISD :: isConstantSplatVector ( C . getNode ( ) , MulC ) ) return false ; if ( isOperationLegal ( ISD :: MUL , VT ) ) return false ; return ( MulC + 1 ) . isPowerOf2 ( ) || ( MulC - 1 ) . isPowerOf2 ( ) ; } </s>


"JIT relocation model must be set to static or default!"


<s> void MipsSETargetLowering :: addMSAIntType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: ADD , Ty , Legal ) ; setOperationAction ( ISD :: CTLZ , Ty , Legal ) ; setOperationAction ( ISD :: MUL , Ty , Legal ) ; setOperationAction ( ISD :: SDIV , Ty , Legal ) ; setOperationAction ( ISD :: SHL , Ty , Legal ) ; setOperationAction ( ISD :: SRA , Ty , Legal ) ; setOperationAction ( ISD :: SRL , Ty , Legal ) ; setOperationAction ( ISD :: SUB , Ty , Legal ) ; setOperationAction ( ISD :: UDIV , Ty , Legal ) ; } </s>

Enable MSA support for the given integer type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::BITCAST ISD::LOAD ISD::STORE ISD::ADD ISD::CTLZ ISD::MUL ISD::SDIV ISD::SHL ISD::SRA ISD::SRL ISD::SUB ISD::UDIV


<s> bool PPCPostRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand ) { if ( ! Cand . isValid ( ) ) { TryCand . Reason = NodeOrder ; return true ; } if ( tryLess ( Top . getLatencyStallCycles ( TryCand . SU ) , Top . getLatencyStallCycles ( Cand . SU ) , TryCand , Cand , Stall ) ) return TryCand . Reason != NoCand ; if ( tryGreater ( TryCand . SU == DAG -> getNextClusterSucc ( ) , Cand . SU == DAG -> getNextClusterSucc ( ) , TryCand , Cand , Cluster ) ) return TryCand . Reason != NoCand ; if ( tryLess ( TryCand . ResDelta . CritResources , Cand . ResDelta . CritResources , TryCand , Cand , ResourceReduce ) ) return TryCand . Reason != NoCand ; if ( tryGreater ( TryCand . ResDelta . DemandedResources , Cand . ResDelta . DemandedResources , TryCand , Cand , ResourceDemand ) ) return TryCand . Reason != NoCand ; if ( Cand . Policy . ReduceLatency && tryLatency ( TryCand , Cand , Top ) ) { return TryCand . Reason != NoCand ; } if ( TryCand . SU -> NodeNum < Cand . SU -> NodeNum ) TryCand . Reason = NodeOrder ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return true ; if ( biasAddiCandidate ( Cand , TryCand ) ) return TryCand . Reason != NoCand ; return TryCand . Reason != NoCand ; } </s>

Apply a set of heuristics to a new candidate .


"AIX's linkage directives take a visibility setting."

"InternalLinkage should not have other visibility setting."

"CommonLinkage of XCOFF should not come to this path"

"Cannot not be both dllexport and non-default visibility"

This emits linkage information about GVSym based on GV , if this is supported by the target .


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( HasSoftFloat ) HasVector = false ; if ( ! HasVector ) { HasVectorEnhancements1 = false ; HasVectorEnhancements2 = false ; HasVectorPackedDecimal = false ; HasVectorPackedDecimalEnhancement = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static rtx aarch64_move_pointer ( rtx pointer , int amount ) { rtx next = plus_constant ( Pmode , XEXP ( pointer , 0 ) , amount ) ; return adjust_automodify_address ( pointer , GET_MODE ( pointer ) , next , amount ) ; } </s>

Return a new RTX holding the result of moving POINTER forward by AMOUNT bytes .


<s>
bool
F2003fFiMalkrz
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
const
F2003fInstrInfo
&
TII
=
*
static_cast
<
const
F2003fInstrInfo
*
>
(
F
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
for
(
auto
&
BB
:
F
)
{
for
(
MachineBasicBlock
::
iterator
I
=
BB
.
begin
(
)
;
I
!=
BB
.
end
(
)
;
)
{
MachineInstr
&
MI
=
*
I
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
Opc
=
MI
.
getOpcode
(
)
;
unsigned
FiOpc
=
TII
.
getFiFromFiMalkrz
(
Opc
)
;
if
(
FiOpc
!=
F2003f
::
INSTRUCTION_LIST_END
)
{
DEBUG
(
dbgs
(
)
<<
"Expand: "
)
;
DEBUG
(
MI
.
dump
(
)
)
;
MIBundleBuilder
Bundle
(
BB
,
I
)
;
unsigned
MalkrzOpc
=
TII
.
getMalkrzFromFiMalkrz
(
Opc
)
;
unsigned
MalkrzNumOperands
=
TII
.
get
(
MalkrzOpc
)
.
getNumOperands
(
)
;
MachineInstrBuilder
Malkrz
=
BuildMI
(
F
,
DL
,
TII
.
get
(
MalkrzOpc
)
)
;
for
(
unsigned
i
=
0
;
i
<
MalkrzNumOperands
;
i
++
)
{
Malkrz
.
add
(
MI
.
getOperand
(
i
)
)
;
}
Bundle
.
prepend
(
Malkrz
)
;
unsigned
FiNumOperands
=
TII
.
get
(
FiOpc
)
.
getNumOperands
(
)
;
MachineInstrBuilder
Fi
=
BuildMI
(
F
,
DL
,
TII
.
get
(
FiOpc
)
)
;
for
(
unsigned
i
=
0
;
i
<
FiNumOperands
;
i
++
)
{
Fi
.
add
(
MI
.
getOperand
(
i
+
MalkrzNumOperands
)
)
;
}
Bundle
.
prepend
(
Fi
)
;
I
=
BB
.
erase
(
MI
)
;
}
else
{
++
I
;
}
}
}
return
true
;
}
</s>


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . isPPC64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void mips_declare_common_object ( FILE * stream , const char * name , const char * init_string , unsigned HOST_WIDE_INT size , unsigned int align , bool takes_alignment_p ) { if ( ! takes_alignment_p ) { size += ( align / BITS_PER_UNIT ) - 1 ; size -= size % ( align / BITS_PER_UNIT ) ; mips_declare_object ( stream , name , init_string , "," HOST_WIDE_INT_PRINT_UNSIGNED "\n" , size ) ; } else mips_declare_object ( stream , name , init_string , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

Declare a common object of SIZE bytes using asm directive INIT_STRING . NAME is the name of the object and ALIGN is the required alignment in bytes . TAKES_ALIGNMENT_P is true if the directive takes a third alignment argument .


Change register usage conditional on target flags .


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , machine_mode omode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = omode ; HOST_WIDE_INT bytes , words ; rtx arg ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) { gcc_assert ( type != NULL_TREE ) ; if ( POINTER_TYPE_P ( type ) ) { gcc_assert ( TYPE_MODE ( type ) == Pmode ) ; arg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( type ) == INTEGER_TYPE && TYPE_MODE ( type ) == word_mode ) ; arg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , - 2 * UNITS_PER_WORD ) ) ; } return arg ; } if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) arg = NULL ; else if ( cum -> bnd_regno <= LAST_BND_REG ) arg = gen_rtx_REG ( BNDmode , cum -> bnd_regno ) ; else arg = GEN_INT ( cum -> bnd_regno - LAST_BND_REG - 1 ) ; return arg ; } if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else arg = function_arg_64 ( cum , mode , omode , type , named ) ; } else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ; if ( arg == NULL_RTX && cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; return arg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


"Basic block should contain at least a RET but is empty"


<s> SDValue ARMTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { if ( N -> getOpcode ( ) != ISD :: SDIV ) return SDValue ( ) ; const auto & ST = DAG . getSubtarget < ARMSubtarget > ( ) ; const bool MinSize = ST . hasMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideInARMMode ( ) ; if ( N -> getOperand ( 0 ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( ! ( MinSize && HasDivide ) ) return SDValue ( ) ; if ( ! ST . isThumb ( ) ) return SDValue ( N , 0 ) ; if ( Divisor . sgt ( 128 ) ) return SDValue ( ) ; return SDValue ( N , 0 ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> SDValue Cpu0TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Cpu0 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static rtx alignment_mask ( rtx_insn * insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != AND || ! REG_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 0 ; rtx mask = XEXP ( SET_SRC ( body ) , 1 ) ; if ( GET_CODE ( mask ) == CONST_INT ) { if ( INTVAL ( mask ) == - 16 ) return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; else return 0 ; } if ( ! REG_P ( mask ) ) return 0 ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; rtx real_mask = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( use ) , mask ) ) continue ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return 0 ; rtx_insn * const_insn = DF_REF_INSN ( def_link -> ref ) ; rtx const_body = PATTERN ( const_insn ) ; if ( GET_CODE ( const_body ) != SET ) return 0 ; real_mask = SET_SRC ( const_body ) ; if ( GET_CODE ( real_mask ) != CONST_INT || INTVAL ( real_mask ) != - 16 ) return 0 ; } if ( real_mask == 0 ) return 0 ; return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; } </s>

Check whether an rtx is an alignment mask , and if so , return a fully-expanded rtx for the masking operation .


<s> int mmix_local_regno ( int regno ) { return regno <= MMIX_LAST_STACK_REGISTER_REGNUM && ! call_used_regs [ regno ] ; } </s>

LOCAL_REGNO . All registers that are part of the register stack and that will be saved are local .


"\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "

"opno = %d, total = %d, speed = %s, x:\n"

Debug form of r6000_rtx_costs that is selected if -mdebug=cost .


<s> static bool no_global_regs_above ( int first_greg ) { int i ; for ( i = 0 ; i < 32 - first_greg ; i ++ ) if ( global_regs [ first_greg + i ] ) return false ; return true ; } </s>

Look for user-defined global regs . We should not save and restore these , and can not use stmw/lmw if there are any in its range .


<s> static rtx ix86_get_arg_address_for_bt ( rtx slot , rtx slot_no , rtx special_base ) { rtx addr = NULL ; if ( ! slot || REG_P ( slot ) ) { gcc_assert ( CONST_INT_P ( slot_no ) ) ; addr = plus_constant ( Pmode , special_base , - ( INTVAL ( slot_no ) + 1 ) * GET_MODE_SIZE ( Pmode ) ) ; } else if ( MEM_P ( slot ) ) { addr = XEXP ( slot , 0 ) ; if ( ! register_operand ( addr , Pmode ) ) addr = copy_addr_to_reg ( addr ) ; } else gcc_unreachable ( ) ; return addr ; } </s>

Helper function for ix86_load_bounds and ix86_store_bounds . Return an address to be used to load/store bounds for pointer passed in SLOT . SLOT_NO is an integer constant holding number of a target dependent special slot to be used in case SLOT is not a memory . SPECIAL_BASE is a pointer to be used as a base of fake address to access special slots in Bounds Table . SPECIAL_BASE [ -1 ] , SPECIAL_BASE [ -2 ] etc . will be used as fake pointer locations .


<s> sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; if ( bitmap_bit_p ( in , LR_REGNO ) || bitmap_bit_p ( gen , LR_REGNO ) || bitmap_bit_p ( kill , LR_REGNO ) ) bitmap_set_bit ( components , 0 ) ; if ( bitmap_bit_p ( in , TOC_REGNUM ) || bitmap_bit_p ( gen , TOC_REGNUM ) || bitmap_bit_p ( kill , TOC_REGNUM ) ) bitmap_set_bit ( components , 2 ) ; return components ; } </s>


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>


<s> static unsigned int compute_vrsave_mask ( void ) { unsigned int i , mask = 0 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) mask |= ALTIVEC_REG_BIT ( i ) ; if ( mask == 0 ) return mask ; for ( i = cfun -> args_info . vregno - 1 ; i >= ALTIVEC_ARG_MIN_REG ; -- i ) mask &= ~ ALTIVEC_REG_BIT ( i ) ; { bool yes = false ; diddle_return_value ( is_altivec_return_reg , & yes ) ; if ( yes ) mask &= ~ ALTIVEC_REG_BIT ( ALTIVEC_ARG_RETURN ) ; } return mask ; } </s>

Return a 32-bit mask of the AltiVec registers we need to set in VRSAVE . Bit n of the return value is 1 if Vn is live . The MSB in the 32-bit word is 0 .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_64BIT ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_64BIT ) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si ; } </s>

Return the correct ICODE value depending on whether we are setting or reading the HTM SPRs .


<s> void F2003fMCAsmStreamer :: emitRawComment ( const Twine & T , bool TabPrefix ) { OS << MAI -> getCommentString ( ) << T ; EmitEOL ( ) ; } </s>

Print T and prefix it with the comment string ( normally # ) and optionally a tab .


"Pointer Checker requires MPX support on this target."

Return mode to be used for bounds or VOIDmode if bounds are not supported .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool isReg ( ) const { return Kind == Register ; } </s>


<s> bool isFPImm ( ) const { return Kind == k_FPImm && AArch64_AM :: getFP64Imm ( getFPImm ( ) . bitcastToAPInt ( ) ) != - 1 ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> const char * loongarch_output_probe_stack_range ( rtx reg1 , rtx reg2 , rtx reg3 ) { static int labelno = 0 ; char loop_lab [ 32 ] , tmp [ 64 ] ; rtx xops [ 3 ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , "LPSRL" , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ 0 ] = reg1 ; xops [ 2 ] = reg3 ; if ( TARGET_64BIT ) output_asm_insn ( "sub.d\t%0,%0,%2" , xops ) ; else output_asm_insn ( "sub.w\t%0,%0,%2" , xops ) ; xops [ 1 ] = reg2 ; strcpy ( tmp , "bne\t%0,%1," ) ; if ( TARGET_64BIT ) output_asm_insn ( "st.d\t$r0,%0,0" , xops ) ; else output_asm_insn ( "st.w\t$r0,%0,0" , xops ) ; output_asm_insn ( strcat ( tmp , & loop_lab [ 1 ] ) , xops ) ; return "" ; } </s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s>
void
scalar_chain
::
add_insn
(
bitmap
candidates
,
unsigned
int
insn_uid
)
{
if
(
bitmap_bit_p
(
insns
,
insn_uid
)
)
return
;
if
(
dump_file
)
fprintf
(
dump_file
,
"  Adding insn %d to chain #%d\n"
,
insn_uid
,
chain_id
)
;
bitmap_set_bit
(
insns
,
insn_uid
)
;
rtx_insn
*
insn
=
DF_INSN_UID_GET
(
insn_uid
)
->
insn
;
rtx
def_set
=
single_set
(
insn
)
;
if
(
def_set
&&
REG_P
(
SET_DEST
(
def_set
)
)
&&
!
HARD_REGISTER_P
(
SET_DEST
(
def_set
)
)
)
bitmap_set_bit
(
defs
,
REGNO
(
SET_DEST
(
def_set
)
)
)
;
df_ref
ref
;
df_ref
def
;
for
(
ref
=
DF_INSN_UID_DEFS
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
HARD_REGISTER_P
(
DF_REF_REG
(
ref
)
)
)
for
(
def
=
DF_REG_DEF_CHAIN
(
DF_REF_REGNO
(
ref
)
)
;
def
;
def
=
DF_REF_NEXT_REG
(
def
)
)
analyze_register_chain
(
candidates
,
def
)
;
for
(
ref
=
DF_INSN_UID_USES
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
DF_REF_REG_MEM_P
(
ref
)
)
analyze_register_chain
(
candidates
,
ref
)
;
}
</s>

Add instruction into a chain . Return true if OK , false if the search was aborted .


<s> static machine_mode counter_mode ( rtx count_exp ) { if ( GET_MODE ( count_exp ) != VOIDmode ) return GET_MODE ( count_exp ) ; if ( ! CONST_INT_P ( count_exp ) ) return Pmode ; if ( TARGET_64BIT && ( INTVAL ( count_exp ) & ~ 0xffffffff ) ) return DImode ; return SImode ; } </s>

Return mode for the memcpy/memset loop counter . Prefer SImode over DImode for constant loop counts .


<s> static unsigned int rs6000_parm_offset ( void ) { return ( DEFAULT_ABI == ABI_V4 ? 2 : DEFAULT_ABI == ABI_ELFv2 ? 4 : 6 ) ; } </s>

The offset in words to the start of the parameter save area .


<s> void arm_expand_vcond ( rtx * operands , machine_mode cmp_result_mode ) { rtx mask = gen_reg_rtx ( cmp_result_mode ) ; bool inverted = arm_expand_vector_compare ( mask , GET_CODE ( operands [ 3 ] ) , operands [ 4 ] , operands [ 5 ] , true ) ; if ( inverted ) std :: swap ( operands [ 1 ] , operands [ 2 ] ) ; emit_insn ( gen_neon_vbsl ( GET_MODE ( operands [ 0 ] ) , operands [ 0 ] , mask , operands [ 1 ] , operands [ 2 ] ) ) ; } </s>

Expand a vcond or vcondu pattern with operands OPERANDS . CMP_RESULT_MODE is the mode of the comparison result .


<s> static rtx arm_expand_binop_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( GET_MODE ( op0 ) == mode0 && GET_MODE ( op1 ) == mode1 ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of binop insns .


<s> static char * make_name ( tree decl , const char * suffix , bool make_unique ) { char * global_var_name ; int name_len ; const char * name ; const char * unique_name = NULL ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; if ( make_unique ) unique_name = IDENTIFIER_POINTER ( get_file_function_name ( "\0" ) ) ; name_len = strlen ( name ) + strlen ( suffix ) + 2 ; if ( make_unique ) name_len += strlen ( unique_name ) + 1 ; global_var_name = XNEWVEC ( char , name_len ) ; if ( make_unique ) snprintf ( global_var_name , name_len , "%s.%s.%s" , name , unique_name , suffix ) ; else snprintf ( global_var_name , name_len , "%s.%s" , name , suffix ) ; return global_var_name ; } </s>

Return a new name by appending SUFFIX to the DECL name . If make_unique is true , append the full path name of the source file .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool PPCTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( ! getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return false ; if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = 0 ; i != Ins . size ( ) ; i ++ ) { ISD :: ArgFlagsTy Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

PowerPC PPC ISD::InputArg 0 ISD::ArgFlagsTy


<s> static bool classof ( const ARMMCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> InstructionCost AArch64TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; APInt ImmVal = Imm ; if ( BitSize & 0x3f ) ImmVal = Imm . sext ( ( BitSize + 63 ) & ~ 0x3fU ) ; InstructionCost Cost = 0 ; for ( unsigned ShiftVal = 0 ; ShiftVal < BitSize ; ShiftVal += 64 ) { APInt Tmp = ImmVal . ashr ( ShiftVal ) . sextOrTrunc ( 64 ) ; int64_t Val = Tmp . getSExtValue ( ) ; Cost += getIntImmCost ( Val ) ; } return std :: max < InstructionCost > ( 1 , Cost ) ; } </s>

Calculate the cost of materializing a 64-bit value .


Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> static inline int extract_17 ( unsigned word ) { return sign_extend ( GET_FIELD ( word , 19 , 28 ) | GET_FIELD ( word , 29 , 29 ) << 10 | GET_FIELD ( word , 11 , 15 ) << 11 | ( word & 0x1 ) << 16 , 17 ) ; } </s>

Extract a 17-bit signed constant from branch instructions .


"Cannot allocate free scratch registers for the "

runOnMachineFunction - Emit the function body .


<s> static bool ix86_check_avx_upper_register ( const_rtx exp ) { return ( SSE_REG_P ( exp ) && ! EXT_REX_SSE_REG_P ( exp ) && GET_MODE_BITSIZE ( GET_MODE ( exp ) ) > 128 ) ; } </s>

Check if a 256bit or 512 bit AVX register is referenced inside of EXP .


<s> static unsigned getSubRegIndex ( const TargetRegisterClass * RC ) { unsigned SubIdx = X86 :: NoSubRegister ; if ( RC == & X86 :: GR32RegClass ) { SubIdx = X86 :: sub_32bit ; } else if ( RC == & X86 :: GR16RegClass ) { SubIdx = X86 :: sub_16bit ; } else if ( RC == & X86 :: GR8RegClass ) { SubIdx = X86 :: sub_8bit ; } return SubIdx ; } </s>

Check if the given identifier is a name of a subregister index .


<s> void print ( std :: ostream * O ) const { if ( O ) print ( * O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool AArch64InstrInfo :: isLdStPairSuppressed ( const MachineInstr & MI ) const { return any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOSuppressPair ; } ) ; } </s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s> static void loongarch_print_operand_punctuation ( FILE * file , int ch ) { switch ( ch ) { case '.' : fputs ( reg_names [ GP_REG_FIRST + 0 ] , file ) ; break ; case '$' : fputs ( reg_names [ STACK_POINTER_REGNUM ] , file ) ; break ; default : gcc_unreachable ( ) ; break ; } } </s>

Print the text for PRINT_OPERAND punctation character CH to FILE . The punctuation characters are : ' . ' Print the name of the register with a hard-wired zero ( zero or $ r0 ) . ' $ ' Print the name of the stack pointer register ( sp or $ r3 ) . See also loongarch_init_print_operand_punct .


<s>
bool
SystemZAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SystemZOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

SystemZ
SystemZ
SystemZ
"unexpected token in argument list"


"The function works only with LEA instructions"


<s> unsigned MipsInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( ( MI -> getOpcode ( ) == Mips :: SW ) || ( MI -> getOpcode ( ) == Mips :: SWC1 ) || ( MI -> getOpcode ( ) == Mips :: SDC1 ) ) { if ( ( MI -> getOperand ( 2 ) . isFI ( ) ) && ( MI -> getOperand ( 1 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 1 ) ) ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
DecodeStatus
AArch64Disassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
Size
=
0
;
if
(
Bytes
.
size
(
)
<
4
)
return
Fail
;
Size
=
4
;
uint32_t
Insn
=
(
Bytes
[
3
]
<<
24
)
|
(
Bytes
[
2
]
<<
16
)
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
0
]
<<
0
)
;
const
uint8_t
*
Tables
[
]
=
{
DecoderTable32
,
DecoderTableFallback32
}
;
for
(
auto
Table
:
Tables
)
{
DecodeStatus
Result
=
decodeInstruction
(
Table
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
->
get
(
MI
.
getOpcode
(
)
)
;
for
(
unsigned
i
=
0
;
i
<
Desc
.
getNumOperands
(
)
;
i
++
)
{
if
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
MCOI
::
OPERAND_REGISTER
)
{
switch
(
Desc
.
OpInfo
[
i
]
.
RegClass
)
{
default
:
break
;
case
AArch64
::
MPRRegClassID
:
MI
.
insert
(
MI
.
begin
(
)
+
i
,
MCOperand
::
createReg
(
AArch64
::
ZA
)
)
;
break
;
case
AArch64
::
MPR8RegClassID
:
MI
.
insert
(
MI
.
begin
(
)
+
i
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
}
}
else
if
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
AArch64
::
OPERAND_IMPLICIT_IMM_0
)
{
MI
.
insert
(
MI
.
begin
(
)
+
i
,
MCOperand
::
createImm
(
0
)
)
;
}
}
if
(
MI
.
getOpcode
(
)
==
AArch64
::
LDR_ZA
||
MI
.
getOpcode
(
)
==
AArch64
::
STR_ZA
)
{
const
MCOperand
&
Imm4Op
=
MI
.
getOperand
(
2
)
;
assert
(
Imm4Op
.
isImm
(
)
&&
"Unexpected operand type!"
)
;
MI
.
addOperand
(
Imm4Op
)
;
}
if
(
Result
!=
MCDisassembler
::
Fail
)
return
Result
;
}
return
MCDisassembler
::
Fail
;
}
</s>

Returns the disassembly of a single instruction .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool ix86_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t regclass ) { if ( from == to ) return true ; if ( MAYBE_FLOAT_CLASS_P ( regclass ) ) return false ; if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P ( regclass ) ) { int mov_size = MAYBE_SSE_CLASS_P ( regclass ) && TARGET_SSE2 ? 2 : 4 ; if ( GET_MODE_SIZE ( from ) < mov_size || GET_MODE_SIZE ( to ) < mov_size ) return false ; } return true ; } </s>


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
(
void
)
RetFastCC_ARM_APCS
;
(
void
)
FastCC_ARM_APCS
;
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
FloatABIType
==
FloatABI
::
Hard
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
ARM_AAPCS_VFP
:
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s>
void
mmix_asm_output_ascii
(
FILE
*
stream
,
const
char
*
string
,
int
length
)
{
while
(
length
>
0
)
{
int
chunk_size
=
length
>
60
60
:
length
;
fprintf
(
stream
,
"\tBYTE "
)
;
mmix_output_quoted_string
(
stream
,
string
,
chunk_size
)
;
string
+=
chunk_size
;
length
-=
chunk_size
;
fprintf
(
stream
,
"\n"
)
;
}
}
</s>


<s> bool X86TargetLowering :: isCommutativeBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: PCMPEQ : case X86ISD :: PMULDQ : case X86ISD :: PMULUDQ : case X86ISD :: FMAXC : case X86ISD :: FMINC : case X86ISD :: FAND : case X86ISD :: FOR : case X86ISD :: FXOR : return true ; } return TargetLoweringBase :: isCommutativeBinOp ( Opcode ) ; } </s>

Returns true if the opcode is a commutative binary operation .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR64RegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
GPR32RegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
GPR64RegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO0
,
&
Mips
::
LO32RegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO0_64
,
&
Mips
::
LO64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
parseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
static
void
aarch64_print_hint_for_core_or_arch
(
const
char
*
str
,
bool
arch
)
{
auto_vec
<
const
char
*
>
candidates
;
const
struct
processor
*
entry
=
arch
all_architectures
:
all_cores
;
for
(
;
entry
->
name
!=
;
entry
++
)
candidates
.
safe_push
(
entry
->
name
)
;
if
(
arch
)
candidates
.
safe_push
(
"native"
)
;
char
*
s
;
const
char
*
hint
=
candidates_list_and_hint
(
str
,
s
,
candidates
)
;
if
(
hint
)
inform
(
input_location
,
"valid arguments are: %s;"
" did you mean %qs?"
,
s
,
hint
)
;
else
inform
(
input_location
,
"valid arguments are: %s"
,
s
)
;
XDELETEVEC
(
s
)
;
}
</s>

Print a hint with a suggestion for a core or architecture name that most closely resembles what the user passed in STR . ARCH is true if the user is asking for an architecture name . ARCH is false if the user is asking for a core name .

aarch64
"native"
"valid arguments are: %s;"
" did you mean %qs?"
"valid arguments are: %s"


<s> static int vfp_emit_fstmx ( int base_reg , int count ) { rtx par ; rtx dwarf ; rtx tmp , reg ; int i ; if ( count == 2 && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - 3 ) base_reg -= 2 ; count ++ ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_DEC ( BLKmode , stack_pointer_rtx ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - ( count * 8 + 4 ) ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 1 ) = tmp ; for ( i = 1 ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( i * 8 ) ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , i + 1 ) = tmp ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf , REG_NOTES ( par ) ) ; RTX_FRAME_RELATED_P ( par ) = 1 ; return count * 8 + 4 ; } </s>

Emit RTL to save block of VFP register pairs to the stack . Returns the number of bytes pushed .


"unable to compute real location of stacked parameter"

Handle a special case when computing the offset of an argument from the frame pointer .


<s> bool X86PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


<s> static void set_rop_modrm_reg_bits ( int base , HARD_REG_SET & in , HARD_REG_SET & out ) { SET_HARD_REG_BIT ( out , base ) ; SET_HARD_REG_BIT ( out , base + 1 ) ; SET_HARD_REG_BIT ( in , base + 2 ) ; SET_HARD_REG_BIT ( in , base + 3 ) ; } </s>

Given a register number BASE , the lowest of a group of registers , update regsets IN and OUT with the registers that should be avoided in input and output operands respectively when trying to avoid generating a modr/m byte for -mmitigate-rop .


<s> static unsigned int mips_multi_last_index ( void ) { return mips_multi_members . length ( ) - 1 ; } </s>

Return the index of the last member of the current multi-insn sequence .


<s>
void
SICInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
SIC
::
GPROutRegClass
.
contains
(
DestReg
)
&&
SIC
::
GPROutRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
SIC
::
RMO
;
}
else
if
(
SIC
::
GPROutRegClass
.
contains
(
DestReg
)
&&
SIC
::
SW
==
SrcReg
)
{
Opc
=
SIC
::
MVSW
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

SIC
SIC
0
SIC::GPROutRegClass
SIC::GPROutRegClass
SIC::RMO
SIC::GPROutRegClass
SIC::SW
SIC::MVSW
"Cannot copy registers"


Return true if destination of IN_INSN is used as add source in OUT_INSN . Both IN_INSN and OUT_INSN are of type fmadd . Example : madd.s dst , x , y , z madd.s a , dst , b , c


<s> bool ARM64TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_ARM64_WebKit_JS : RetCC_ARM64_AAPCS ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static void ia64_vms_init_libfuncs ( void ) { set_optab_libfunc ( sdiv_optab , SImode , "OTS$DIV_I" ) ; set_optab_libfunc ( sdiv_optab , DImode , "OTS$DIV_L" ) ; set_optab_libfunc ( udiv_optab , SImode , "OTS$DIV_UI" ) ; set_optab_libfunc ( udiv_optab , DImode , "OTS$DIV_UL" ) ; set_optab_libfunc ( smod_optab , SImode , "OTS$REM_I" ) ; set_optab_libfunc ( smod_optab , DImode , "OTS$REM_L" ) ; set_optab_libfunc ( umod_optab , SImode , "OTS$REM_UI" ) ; set_optab_libfunc ( umod_optab , DImode , "OTS$REM_UL" ) ; abort_libfunc = init_one_libfunc ( "decc$abort" ) ; memcmp_libfunc = init_one_libfunc ( "decc$memcmp" ) ; MEM_LIBFUNCS_INIT ; } </s>

Rename the division and modulus functions in VMS .


<s>
static
unsigned
getHashValue
(
const
MemOpKey
&
Val
)
{
assert
(
Val
.
Disp
!=
PtrInfo
::
getEmptyKey
(
)
&&
"Cannot hash the empty key"
)
;
assert
(
Val
.
Disp
!=
PtrInfo
::
getTombstoneKey
(
)
&&
"Cannot hash the tombstone key"
)
;
hash_code
Hash
=
hash_combine
(
*
Val
.
Operands
[
0
]
,
*
Val
.
Operands
[
1
]
,
*
Val
.
Operands
[
2
]
,
*
Val
.
Operands
[
3
]
)
;
switch
(
Val
.
Disp
->
getType
(
)
)
{
case
MachineOperand
::
MO_Immediate
:
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getIndex
(
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getSymbolName
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getGlobal
(
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getBlockAddress
(
)
)
;
break
;
case
MachineOperand
::
MO_MCSymbol
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getMCSymbol
(
)
)
;
break
;
default
:
llvm_unreachable
(
"Invalid address displacement operand"
)
;
}
return
(
unsigned
)
Hash
;
}
</s>

Using name and line to get hash value . It should already be mostly unique .


<s> const Cpu0TargetLowering * Cpu0TargetLowering :: create ( const Cpu0TargetMachine & TM , const Cpu0Subtarget & STI ) { return createCpu0SETargetLowering ( TM , STI ) ; } </s>


<s> int mve_vector_mem_operand ( machine_mode mode , rtx op , bool strict ) { enum rtx_code code ; int val , reg_no ; if ( REG_P ( op ) ) { int reg_no = REGNO ( op ) ; return ( ( ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ? reg_no <= LAST_LO_REGNUM : ( reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM ) ) || ( ! strict && reg_no >= FIRST_PSEUDO_REGISTER ) ) ; } code = GET_CODE ( op ) ; if ( code == POST_INC || code == PRE_DEC || code == PRE_INC || code == POST_DEC ) { reg_no = REGNO ( XEXP ( op , 0 ) ) ; return ( ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ? reg_no <= LAST_LO_REGNUM : ( reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM ) ) || reg_no >= FIRST_PSEUDO_REGISTER ; } else if ( ( ( code == POST_MODIFY || code == PRE_MODIFY ) && GET_CODE ( XEXP ( op , 1 ) ) == PLUS && XEXP ( op , 0 ) == XEXP ( XEXP ( op , 1 ) , 0 ) && REG_P ( XEXP ( op , 0 ) ) && GET_CODE ( XEXP ( XEXP ( op , 1 ) , 1 ) ) == CONST_INT ) || ( reload_completed && code == PLUS && REG_P ( XEXP ( op , 0 ) ) && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ) { reg_no = REGNO ( XEXP ( op , 0 ) ) ; if ( code == PLUS ) val = INTVAL ( XEXP ( op , 1 ) ) ; else val = INTVAL ( XEXP ( XEXP ( op , 1 ) , 1 ) ) ; switch ( mode ) { case E_V16QImode : case E_V8QImode : case E_V4QImode : if ( abs ( val ) > 127 ) return FALSE ; break ; case E_V8HImode : case E_V8HFmode : case E_V4HImode : case E_V4HFmode : if ( val % 2 != 0 || abs ( val ) > 254 ) return FALSE ; break ; case E_V4SImode : case E_V4SFmode : if ( val % 4 != 0 || abs ( val ) > 508 ) return FALSE ; break ; default : return FALSE ; } return reg_no >= FIRST_PSEUDO_REGISTER || ( MVE_STN_LDW_MODE ( mode ) ? reg_no <= LAST_LO_REGNUM : ( reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM ) ) ; } return FALSE ; } </s>

This function returns TRUE on matching mode and op.1 . For given modes , check for [ Rn ] , return TRUE for Rn < = LO_REGS.2 . For other modes , check for [ Rn ] , return TRUE for Rn < R15 ( expect R13 ) .


<s> void PPCAIXAsmPrinter :: emitEndOfAsmFile ( Module & M ) { if ( M . empty ( ) && TOCDataGlobalVars . empty ( ) ) return ; emitPGORefs ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) ; PPCTargetStreamer * TS = static_cast < PPCTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry ; if ( I . first . second == MCSymbolRefExpr :: VariantKind :: VK_PPC_AIX_TLSGDM ) { SmallString < 128 > Name ; StringRef Prefix = "." ; Name += Prefix ; Name += I . first . first -> getName ( ) ; MCSymbol * S = OutContext . getOrCreateSymbol ( Name ) ; TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( S , TM ) ) ; } else { TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first . first , TM ) ) ; } OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> emitLabel ( I . second ) ; if ( TS != nullptr ) TS -> emitTCEntry ( * I . first . first , I . first . second ) ; } for ( const auto * GV : TOCDataGlobalVars ) emitGlobalVariableHelper ( GV ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> void function_expander :: add_integer_operand ( HOST_WIDE_INT x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 ) ; create_integer_operand ( & m_ops . last ( ) , x ) ; } </s>


<s> static bool ix86_broadcast ( HOST_WIDE_INT v , unsigned int width , HOST_WIDE_INT & val_broadcast ) { wide_int val = wi :: uhwi ( v , HOST_BITS_PER_WIDE_INT ) ; val_broadcast = wi :: extract_uhwi ( val , 0 , width ) ; for ( unsigned int i = width ; i < HOST_BITS_PER_WIDE_INT ; i += width ) { HOST_WIDE_INT each = wi :: extract_uhwi ( val , i , width ) ; if ( val_broadcast != each ) return false ; } val_broadcast = sext_hwi ( val_broadcast , width ) ; return true ; } </s>

Return true if V can be broadcasted from an integer of WIDTH bits which is returned in VAL_BROADCAST . Otherwise , return false .


<s> static bool is_function_default_version ( const tree decl ) { if ( TREE_CODE ( decl ) != FUNCTION_DECL || ! DECL_FUNCTION_VERSIONED ( decl ) ) return false ; tree attr = lookup_attribute ( "target" , DECL_ATTRIBUTES ( decl ) ) ; gcc_assert ( attr ) ; attr = TREE_VALUE ( TREE_VALUE ( attr ) ) ; return ( TREE_CODE ( attr ) == STRING_CST && strcmp ( TREE_STRING_POINTER ( attr ) , "default" ) == 0 ) ; } </s>

Returns true if decl is multi-versioned and DECL is the default function , that is it is not tagged with target specific optimization .


<s> bool X86WinAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasWinAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = 4096 ; if ( MF . getFunction ( ) . hasFnAttribute ( "stack-probe-size" ) ) { MF . getFunction ( ) . getFnAttribute ( "stack-probe-size" ) . getValueAsString ( ) . getAsInteger ( 0 , StackProbeSize ) ; } NoStackArgProbe = MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ; if ( NoStackArgProbe ) StackProbeSize = INT64_MAX ; LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool sparc_vector_mode_supported_p ( enum machine_mode mode ) { return TARGET_VIS && VECTOR_MODE_P ( mode ) ? true : false ; } </s>

Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook . Specify whether the vector mode is supported by the hardware .


<s>
unsigned
VEMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
VEMCExpr
*
SExpr
=
dyn_cast
<
VEMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
evaluateAsAbsolute
(
Res
)
)
return
Res
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool CJGFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; CJGMachineFunctionInfo * MFI = MF . getInfo < CJGMachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( CJG :: PUSH ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


Define the ` __builtin_va_list ' type for the ABI .


<s> TargetLowering :: ConstraintWeight ARMTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'l' : if ( type -> isIntegerTy ( ) ) { if ( Subtarget -> isThumb ( ) ) weight = CW_SpecificReg ; else weight = CW_Register ; } break ; case 'w' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static rtx_insn * csky_call_tls_get_addr ( rtx x , rtx reg , rtx * valuep , int reloc ) { rtx label , labelno , unspec , tmp ; rtx_insn * insns ; start_sequence ( ) ; labelno = GEN_INT ( tls_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , x , GEN_INT ( reloc ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ; emit_move_insn ( tmp , label ) ; emit_insn ( gen_addsi3 ( reg , reg , tmp ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; return insns ; } </s>


<s> static void ix86_emit_restore_regs_using_pop ( void ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , false ) ) ix86_emit_restore_reg_using_pop ( gen_rtx_REG ( word_mode , regno ) ) ; } </s>

Emit code to restore saved registers using POP insns .


<s> bool xlogue_layout :: is_stub_managed_reg ( unsigned regno , unsigned count ) { bool hfp = frame_pointer_needed || stack_realign_fp ; unsigned i ; for ( i = 0 ; i < count ; ++ i ) { gcc_assert ( i < MAX_REGS ) ; if ( REG_ORDER [ i ] == BP_REG && hfp ) ++ count ; else if ( REG_ORDER [ i ] == regno ) return true ; } return false ; } </s>

Determine if register REGNO is a stub managed register given the total COUNT of stub managed registers .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getDataLayout
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
,
Subtarget
->
isLittle
(
)
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


"rs6000_builtin_md_vectorized_function (%s, %s, %s)\n"


<s> unsigned Cpu0MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget -> is64Bit ( ) ? 64 : 32 ; const Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! hasMFENCE ( * Subtarget ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


"Unknown fence ordering in emitLeadingFence"


<s> static unsigned selectBinaryOp ( unsigned GenericOpc , unsigned RegBankID , unsigned OpSize ) { switch ( RegBankID ) { case AArch64 :: GPRRegBankID : if ( OpSize == 32 ) { switch ( GenericOpc ) { case TargetOpcode :: G_SHL : return AArch64 :: LSLVWr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVWr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVWr ; default : return GenericOpc ; } } else if ( OpSize == 64 ) { switch ( GenericOpc ) { case TargetOpcode :: G_PTR_ADD : return AArch64 :: ADDXrr ; case TargetOpcode :: G_SHL : return AArch64 :: LSLVXr ; case TargetOpcode :: G_LSHR : return AArch64 :: LSRVXr ; case TargetOpcode :: G_ASHR : return AArch64 :: ASRVXr ; default : return GenericOpc ; } } break ; case AArch64 :: FPRRegBankID : switch ( OpSize ) { case 32 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDSrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBSrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULSrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVSrr ; default : return GenericOpc ; } case 64 : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return AArch64 :: FADDDrr ; case TargetOpcode :: G_FSUB : return AArch64 :: FSUBDrr ; case TargetOpcode :: G_FMUL : return AArch64 :: FMULDrr ; case TargetOpcode :: G_FDIV : return AArch64 :: FDIVDrr ; case TargetOpcode :: G_OR : return AArch64 :: ORRv8i8 ; default : return GenericOpc ; } } break ; } return GenericOpc ; } </s>

Select and emit code for a binary operator instruction , which has an opcode which directly corresponds to the given ISD opcode .


<s> unsigned PPCTTI :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) const { if ( DisablePPCConstHoist ) return TargetTransformInfo :: getIntImmCost ( IID , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; switch ( IID ) { default : return TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : if ( ( Idx == 1 ) && Imm . getBitWidth ( ) <= 64 && isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; break ; } return PPCTTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void mmix_make_decl_one_only ( tree decl ) { DECL_WEAK ( decl ) = 1 ; } </s>


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> bool PPCFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnablePEVectorSpills || MFI . hasCalls ( ) || ! Subtarget . hasP9Vector ( ) ) return false ; BitVector BVAllocatable = TRI -> getAllocatableSet ( MF ) ; BitVector BVCalleeSaved ( TRI -> getNumRegs ( ) ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) BVCalleeSaved . set ( CSRegs [ i ] ) ; for ( unsigned Reg : BVAllocatable . set_bits ( ) ) { if ( BVCalleeSaved [ Reg ] || ! PPC :: VSRCRegClass . contains ( Reg ) || MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) BVAllocatable . reset ( Reg ) ; } bool AllSpilledToReg = true ; unsigned LastVSRUsedForSpill = 0 ; for ( auto & CS : CSI ) { if ( BVAllocatable . none ( ) ) return false ; Register Reg = CS . getReg ( ) ; if ( ! PPC :: G8RCRegClass . contains ( Reg ) ) { AllSpilledToReg = false ; continue ; } if ( LastVSRUsedForSpill != 0 ) { CS . setDstReg ( LastVSRUsedForSpill ) ; BVAllocatable . reset ( LastVSRUsedForSpill ) ; LastVSRUsedForSpill = 0 ; continue ; } unsigned VolatileVFReg = BVAllocatable . find_first ( ) ; if ( VolatileVFReg < BVAllocatable . size ( ) ) { CS . setDstReg ( VolatileVFReg ) ; LastVSRUsedForSpill = VolatileVFReg ; } else { AllSpilledToReg = false ; } } return AllSpilledToReg ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> unsigned getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool isScalarFPTypeInSSEReg ( MVT VT ) const { return ( VT == MVT :: f64 && X86ScalarSSEf64 ) || ( VT == MVT :: f32 && X86ScalarSSEf32 ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Expand Pseudo"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void mips_avoid_hazards ( void ) { rtx insn , last_insn , lo_reg , delayed_reg ; int hilo_delay , i ; split_all_insns_noflow ( ) ; cfun -> machine -> ignore_hazard_length_p = true ; shorten_branches ( get_insns ( ) ) ; cfun -> machine -> all_noreorder_p = true ; if ( current_function_profile ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4120 ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4130 && ! ISA_HAS_MACCHI ) cfun -> machine -> all_noreorder_p = false ; last_insn = 0 ; hilo_delay = 2 ; delayed_reg = 0 ; lo_reg = gen_rtx_REG ( SImode , LO_REGNUM ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) mips_avoid_hazard ( last_insn , XVECEXP ( PATTERN ( insn ) , 0 , i ) , & hilo_delay , & delayed_reg , lo_reg ) ; else mips_avoid_hazard ( last_insn , insn , & hilo_delay , & delayed_reg , lo_reg ) ; last_insn = insn ; } } </s>

Go through the instruction stream and insert nops where necessary . See if the whole function can then be put into .set noreorder & .set nomacro .


<s> void ia64_vms_output_aligned_decl_common ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { tree attr = DECL_ATTRIBUTES ( decl ) ; if ( attr ) attr = lookup_attribute ( "common_object" , attr ) ; if ( attr ) { tree id = TREE_VALUE ( TREE_VALUE ( attr ) ) ; const char * name ; if ( TREE_CODE ( id ) == IDENTIFIER_NODE ) name = IDENTIFIER_POINTER ( id ) ; else if ( TREE_CODE ( id ) == STRING_CST ) name = TREE_STRING_POINTER ( id ) ; else abort ( ) ; fprintf ( file , "\t.vms_common\t\"%s\"," , name ) ; } else fprintf ( file , "%s" , COMMON_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u" , size , align / BITS_PER_UNIT ) ; fputc ( '\n' , file ) ; } </s>

Part of the low level implementation of DEC Ada pragma Common_Object .


<s>
const
char
*
output_return
(
rtx_insn
*
insn
)
{
if
(
crtl
->
calls_eh_return
)
{
gcc_assert
(
!
final_sequence
)
;
if
(
flag_delayed_branch
)
{
if
(
!
TARGET_FLAT
&&
TARGET_V9
)
fputs
(
"\treturn\t%i7+8\n"
,
asm_out_file
)
;
else
{
if
(
!
TARGET_FLAT
)
fputs
(
"\trestore\n"
,
asm_out_file
)
;
fputs
(
"\tjmp\t%o7+8\n"
,
asm_out_file
)
;
}
fputs
(
"\t add\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
}
else
{
if
(
!
TARGET_FLAT
)
fputs
(
"\trestore\n"
,
asm_out_file
)
;
fputs
(
"\tadd\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
fputs
(
"\tjmp\t%o7+8\n\t nop\n"
,
asm_out_file
)
;
}
}
else
if
(
sparc_leaf_function_p
||
TARGET_FLAT
)
{
return
"jmp\t%%o7+%)%#"
;
}
else
{
if
(
final_sequence
)
{
rtx_insn
*
delay
;
rtx
pat
;
delay
=
NEXT_INSN
(
insn
)
;
gcc_assert
(
delay
)
;
pat
=
PATTERN
(
delay
)
;
if
(
TARGET_V9
&&
!
epilogue_renumber
(
&
pat
,
1
)
)
{
epilogue_renumber
(
&
pat
,
0
)
;
return
"return\t%%i7+%)%#"
;
}
else
{
output_asm_insn
(
"jmp\t%%i7+%)"
,
)
;
PATTERN
(
delay
)
=
gen_blockage
(
)
;
INSN_CODE
(
delay
)
=
1
;
final_scan_insn
(
delay
,
asm_out_file
,
optimize
,
0
,
)
;
INSN_LOCATION
(
delay
)
=
UNKNOWN_LOCATION
;
output_restore
(
pat
)
;
}
}
else
{
if
(
TARGET_V9
)
return
"return\t%%i7+%)\n\t nop"
;
else
if
(
flag_delayed_branch
)
return
"jmp\t%%i7+%)\n\t restore"
;
else
return
"restore\n\tjmp\t%%o7+%)\n\t nop"
;
}
}
return
""
;
}
</s>


<s> static rtx_code_label * ix86_expand_sse_compare_and_jump ( enum rtx_code code , rtx op0 , rtx op1 , bool swap_operands ) { machine_mode fpcmp_mode = ix86_fp_compare_mode ( code ) ; rtx_code_label * label ; rtx tmp ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; label = gen_label_rtx ( ) ; tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) = label ; return label ; } </s>

Expands a comparison of OP0 with OP1 using comparison code CODE , swapping the operands if SWAP_OPERANDS is true . The expanded code is a forward jump to a newly created label in case the comparison is true . The generated label rtx is returned .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool sh_function_value_regno_p ( const unsigned int regno ) { return regno == FIRST_RET_REG || ( TARGET_SH2E && regno == FIRST_FP_RET_REG ) ; } </s>

Return true if N is a possible register number of function value .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return AArch64II :: MO_GOT | AArch64II :: MO_DLLIMPORT ; if ( getTargetTriple ( ) . isOSWindows ( ) ) return AArch64II :: MO_GOT | AArch64II :: MO_COFFSTUB ; return AArch64II :: MO_GOT ; } if ( ( useSmallAddressing ( ) || TM . getCodeModel ( ) == CodeModel :: Tiny ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> const MipsFrameLowering * MipsFrameLowering :: create ( const MipsSubtarget & ST ) { return llvm :: createMipsSEFrameLowering ( ST ) ; } </s>


<s> static rtx aarch64_expand_builtin_data_intrinsic ( unsigned int fcode , tree exp , rtx target ) { expand_operand ops [ 2 ] ; machine_mode mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; create_output_operand ( & ops [ 0 ] , target , mode ) ; create_input_operand ( & ops [ 1 ] , expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) , mode ) ; enum insn_code icode ; switch ( fcode ) { case AARCH64_REV16 : case AARCH64_REV16L : case AARCH64_REV16LL : icode = code_for_aarch64_rev16 ( mode ) ; break ; case AARCH64_RBIT : case AARCH64_RBITL : case AARCH64_RBITLL : icode = code_for_aarch64_rbit ( mode ) ; break ; default : gcc_unreachable ( ) ; } expand_insn ( icode , 2 , ops ) ; return ops [ 0 ] . value ; } </s>

Function to expand an expression EXP which calls one of the ACLE Data Intrinsic builtins FCODE with the result going to TARGET .