<s> static bool fa726te_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_TRUE && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 && get_attr_conds ( dep ) == CONDS_SET ) { if ( get_attr_conds ( insn ) == CONDS_USE && get_attr_type ( insn ) != TYPE_BRANCH ) { * cost = 3 ; return false ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC || get_attr_conds ( insn ) == CONDS_USE ) { * cost = 0 ; return false ; } } return true ; } </s>


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::Wrapper "MipsISD::Wrapper" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins" MipsISD::LWL "MipsISD::LWL" MipsISD::LWR "MipsISD::LWR" MipsISD::SWL "MipsISD::SWL" MipsISD::SWR "MipsISD::SWR" MipsISD::LDL "MipsISD::LDL" MipsISD::LDR "MipsISD::LDR" MipsISD::SDL "MipsISD::SDL" MipsISD::SDR "MipsISD::SDR"


<s> static void require_pic_register ( void ) { if ( ! crtl -> uses_pic_offset_table ) { gcc_assert ( can_create_pseudo_p ( ) ) ; if ( arm_pic_register != INVALID_REGNUM && ! ( TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM ) ) { if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_rtx_REG ( Pmode , arm_pic_register ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) crtl -> uses_pic_offset_table = 1 ; } else { rtx_insn * seq , * insn ; if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_reg_rtx ( Pmode ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) { crtl -> uses_pic_offset_table = 1 ; start_sequence ( ) ; if ( TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM ) emit_move_insn ( cfun -> machine -> pic_reg , gen_rtx_REG ( Pmode , arm_pic_register ) ) ; else arm_load_pic_register ( 0UL ) ; seq = get_insns ( ) ; end_sequence ( ) ; for ( insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) INSN_LOCATION ( insn ) = prologue_location ; insert_insn_on_edge ( seq , single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ) ; } } } } </s>

Record that the current function needs a PIC register . Initialize cfun- > machine- > pic_reg if we have not already done so .


<s> scalar_chain :: ~ scalar_chain ( ) { BITMAP_FREE ( insns ) ; BITMAP_FREE ( defs ) ; BITMAP_FREE ( defs_conv ) ; BITMAP_FREE ( insns_conv ) ; bitmap_obstack_release ( NULL ) ; } </s>


<s> bool isMem ( MemoryKind MemKind , RegisterKind RegKind ) const { return isMem ( MemKind ) && Mem . RegKind == RegKind ; } </s>


<s> void SystemZInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> int mmix_constant_alignment ( tree constant ATTRIBUTE_UNUSED , int basic_align ) { if ( basic_align < 32 ) return 32 ; return basic_align ; } </s>


<s> int loongarch_const_insns ( rtx x ) { enum loongarch_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case HIGH : if ( ! loongarch_symbolic_constant_p ( XEXP ( x , 0 ) , & symbol_type ) || ! loongarch_split_symbol_type ( symbol_type ) ) return 0 ; return 1 ; case CONST_INT : return loongarch_integer_cost ( INTVAL ( x ) ) ; case CONST_VECTOR : case CONST_DOUBLE : return x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( loongarch_symbolic_constant_p ( x , & symbol_type ) ) return loongarch_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = loongarch_const_insns ( x ) ; if ( n != 0 ) { if ( IMM12_INT ( offset ) ) return n + 1 ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + 1 + loongarch_integer_cost ( INTVAL ( offset ) ) ; } } return 0 ; case SYMBOL_REF : case LABEL_REF : return loongarch_symbol_insns ( loongarch_classify_symbol ( x ) , MAX_MACHINE_MODE ) ; default : return 0 ; } } </s>

Return the number of instructions needed to load constant X , Return 0 if X is n't a valid constant .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
FNEG
:
case
ISD
::
FABS
:
return
LowerF64Op
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::FNEG
ISD::FABS
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> void MipsFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . IsN64 ( ) ? Mips :: SP_64 : Mips :: SP ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips Mips::SP_64 Mips::SP 0 Mips::ADJCALLSTACKDOWN


<s> void PPCSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { if ( needsAggressiveScheduling ( DarwinDirective ) ) { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; } Policy . ShouldTrackPressure = true ; } </s>

Override generic scheduling policy within a region .


<s> StringRef getPassName ( ) const override { return PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
void
ARMConstantIslands
::
verify
(
)
{
for
(
MachineFunction
::
iterator
MBBI
=
MF
->
begin
(
)
,
E
=
MF
->
end
(
)
;
MBBI
!=
E
;
++
MBBI
)
{
MachineBasicBlock
*
MBB
=
MBBI
;
unsigned
Align
=
MBB
->
getAlignment
(
)
;
unsigned
MBBId
=
MBB
->
getNumber
(
)
;
assert
(
BBInfo
[
MBBId
]
.
Offset
%
(
1u
<<
Align
)
==
0
)
;
assert
(
!
MBBId
||
BBInfo
[
MBBId
1
]
.
postOffset
(
)
<=
BBInfo
[
MBBId
]
.
Offset
)
;
}
DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool aarch64_evpc_zip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; high = nelt / 2 ; if ( d -> perm [ 0 ] == high ) ; else if ( d -> perm [ 0 ] == 0 ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * 2 ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * 2 + 1 ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out = d -> target ; if ( high ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip2v16qi ; break ; case V8QImode : gen = gen_aarch64_zip2v8qi ; break ; case V8HImode : gen = gen_aarch64_zip2v8hi ; break ; case V4HImode : gen = gen_aarch64_zip2v4hi ; break ; case V4SImode : gen = gen_aarch64_zip2v4si ; break ; case V2SImode : gen = gen_aarch64_zip2v2si ; break ; case V2DImode : gen = gen_aarch64_zip2v2di ; break ; case V4SFmode : gen = gen_aarch64_zip2v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip2v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip1v16qi ; break ; case V8QImode : gen = gen_aarch64_zip1v8qi ; break ; case V8HImode : gen = gen_aarch64_zip1v8hi ; break ; case V4HImode : gen = gen_aarch64_zip1v4hi ; break ; case V4SImode : gen = gen_aarch64_zip1v4si ; break ; case V2SImode : gen = gen_aarch64_zip1v2si ; break ; case V2DImode : gen = gen_aarch64_zip1v2di ; break ; case V4SFmode : gen = gen_aarch64_zip1v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip1v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the ZIP instructions .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr * MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI -> getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ; switch ( LQR ) { case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI -> killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> static bool aarch64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( aarch64_vector_data_mode_p ( mode1 ) && aarch64_vector_data_mode_p ( mode2 ) ) return true ; if ( aarch64_vector_mode_supported_p ( mode1 ) || aarch64_vector_mode_supported_p ( mode2 ) ) return true ; return false ; } </s>

Implement MODES_TIEABLE_P . In principle we should always return true . However due to issues with register allocation it is preferable to avoid tieing integer scalar and FP scalar modes . Executing integer operations in general registers is better than treating them as scalar vector operations . This reduces latency and avoids redundant int < - > FP moves . So tie modes if they are either the same class , or vector modes with other vector modes , vector structs or any scalar mode .


<s> int uses_TOC ( void ) { rtx_insn * insn ; int ret = 1 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) { rtx sub = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , 0 ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , 1 ) == UNSPEC_TOC ) return ret ; } } } else if ( crtl -> has_bb_partition && NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) ret = 2 ; } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


"This eliminateCallFramePseudoInstr does not support Thumb1!"


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) && hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) ) return UndefRegClearance ; return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( LLT Ty , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || Ty . getSizeInBytes ( ) != 16 || Alignment <= 2 || Ty == LLT :: fixed_vector ( 2 , 64 ) ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool CSKYAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( Count % 2 ) return false ; while ( Count >= 4 ) { OS . write ( "\xc4\x00\x48\x20" , 4 ) ; Count -= 4 ; } if ( Count ) OS . write ( "\x6c\x03" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static inline bool save_reg_p ( int r ) { return ! call_used_regs [ r ] && df_regs_ever_live_p ( r ) ; } </s>

Determine whether the REG is really used .


<s> virtual const ARMSubtarget * getSubtarget ( ) { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> static bool isBranch ( const MCInst & Inst ) { unsigned Opcode = Inst . getOpcode ( ) ; switch ( Opcode ) { default : return false ; break ; case AArch64 :: B : case AArch64 :: Bcc : case AArch64 :: BR : case AArch64 :: BRAA : case AArch64 :: BRAAZ : case AArch64 :: BRAB : case AArch64 :: BRABZ : case AArch64 :: BL : case AArch64 :: BLR : case AArch64 :: BLRAA : case AArch64 :: BLRAAZ : case AArch64 :: BLRAB : case AArch64 :: BLRABZ : case AArch64 :: CBZW : case AArch64 :: CBZX : case AArch64 :: CBNZW : case AArch64 :: CBNZX : case AArch64 :: CCMPWr : case AArch64 :: CCMPXr : case AArch64 :: G_FCMP : case AArch64 :: G_ICMP : case AArch64 :: TBZW : case AArch64 :: TBZX : case AArch64 :: TBNZW : case AArch64 :: TBNZX : case AArch64 :: RET : case AArch64 :: RETAA : case AArch64 :: RETAB : case AArch64 :: SVC : return true ; break ; } return false ; } </s>

Returns true if this is a conditional , unconditional , or indirect branch .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool isZero ( ) const { return K == ConstZero ; } </s>

Return true if the expression is a constant zero .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void LanaiAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void moncontrol ( int mode ) { if ( mode ) { profil ( ( unsigned short * ) ( sbuf + sizeof ( struct phdr ) ) , ssiz - sizeof ( struct phdr ) , ( long ) s_lowpc , s_scale ) ; profiling = 0 ; } else { profil ( ( unsigned short * ) 0 , 0 , 0 , 0 ) ; profiling = 3 ; } } </s>

Control profiling * profiling is what mcount checks to see if * all the data structures are ready .


<s>
MCSymbol
*
XNCMMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .

XNCM
XNCM
"Unknown target flag on GV operand"
0


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> MachineInstr * PPCInstrInfo :: findLoopInstr ( MachineBasicBlock & PreHeader , SmallPtrSet < MachineBasicBlock * , 8 > & Visited ) const { unsigned LOOPi = ( Subtarget . isPPC64 ( ) ? PPC :: MTCTR8loop : PPC :: MTCTRloop ) ; for ( auto & I : PreHeader . instrs ( ) ) if ( I . getOpcode ( ) == LOOPi ) return & I ; return nullptr ; } </s>

Find the hardware loop instruction used to set-up the specified loop .

PowerPC PPC 8 PPC PPC::MTCTR8loop PPC::MTCTRloop


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>


<s> unsigned int mips_hard_regno_nregs ( int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; if ( FP_REG_P ( regno ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return 1 ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ; } return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


Return an array that contains the direct target flag values and their names .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0
ARMCC::AL


Emit the SVE equivalent of : ( set TMP1 ( CODE1 OP0 OP1 ) ) ( set TMP2 ( CODE2 OP0 OP1 ) ) ( set TARGET ( ior : PRED_MODE TMP1 TMP2 ) ) PTRUE is an all-true predicate with the same mode as TARGET .


" does NOT need to be EXPORTed [not a class]\n"

" does NOT need to be EXPORTed [no key function]\n"

" does NOT need to be EXPORTed [key function not defined]\n"

" does NOT need to be EXPORTed [no non-pure virtuals or ctors/dtors with dllimport]\n"

" does NOT need to be EXPORTed [no inline ctor/dtor]\n"

Decide if a class needs its vtable and rtti exporting .


<s> static bool rs6000_scalar_mode_supported_p ( machine_mode mode ) { if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( TARGET_FLOAT128_TYPE && ( mode == KFmode || mode == IFmode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> static void ia64_option_override ( void ) { unsigned int i ; cl_deferred_option * opt ; vec < cl_deferred_option > * v = ( vec < cl_deferred_option > * ) ia64_deferred_options ; if ( v ) FOR_EACH_VEC_ELT ( * v , i , opt ) { switch ( opt -> opt_index ) { case OPT_mfixed_range_ : fix_range ( opt -> arg ) ; break ; default : gcc_unreachable ( ) ; } } if ( TARGET_AUTO_PIC ) target_flags |= MASK_CONST_GP ; if ( optimize >= 3 ) flag_ira_loop_pressure = 1 ; ia64_section_threshold = ( global_options_set . x_g_switch_value ? g_switch_value : IA64_DEFAULT_GVALUE ) ; init_machine_status = ia64_init_machine_status ; if ( align_functions <= 0 ) align_functions = 64 ; if ( align_loops <= 0 ) align_loops = 32 ; if ( TARGET_ABI_OPEN_VMS ) flag_no_common = 1 ; ia64_override_options_after_change ( ) ; } </s>


<s> bool isLegalMaskedScatter ( Type * Ty , MaybeAlign Alignment ) { return isLegalMaskedGather ( Ty , Alignment ) ; } </s>

Return true if the target supports masked scatter .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( TM . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( TFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( PPC :: X2 ) ; else Reserved . reset ( PPC :: R2 ) ; } } if ( TFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool nds32_symbol_binds_local_p ( const_rtx x ) { return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

Return true if SYMBOL_REF X binds locally .


<s> int ARMAsmParser :: tryParseRegister ( ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r13" , ARM :: SP ) . Case ( "r14" , ARM :: LR ) . Case ( "r15" , ARM :: PC ) . Case ( "ip" , ARM :: R12 ) . Default ( 0 ) ; } if ( ! RegNum ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> const char * AArch64Relocator :: getName ( Relocator :: Type pType ) const { assert ( ApplyFunctions . find ( pType ) != ApplyFunctions . end ( ) ) ; return ApplyFunctions [ pType ] . name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; mode = mode_for_size ( bits , MODE_INT , 0 ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , 0 , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> static int feature_compare ( const void * v1 , const void * v2 ) { typedef struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } function_version_info ; const function_version_info c1 = * ( const function_version_info * ) v1 ; const function_version_info c2 = * ( const function_version_info * ) v2 ; return ( c2 . dispatch_priority - c1 . dispatch_priority ) ; } </s>

V1 and V2 point to function versions with different priorities based on the target ISA . This function compares their priorities .


<s> const uint32_t * LC3RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void ARMInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , const MachineInstr * Orig ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; if ( Orig -> getOpcode ( ) == ARM :: MOVi2pieces ) { RI . emitLoadConstPool ( MBB , I , DestReg , Orig -> getOperand ( 1 ) . getImm ( ) , Orig -> getOperand ( 2 ) . getImm ( ) , Orig -> getOperand ( 3 ) . getReg ( ) , this , false , dl ) ; return ; } MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> static bool vax_lra_p ( void ) { return TARGET_LRA ; } </s>

Return true if we use LRA instead of reload pass .


<s> bool mep_epilogue_uses ( int regno ) { if ( regno == LP_REGNO && ( profile_arc_flag > 0 || profile_flag > 0 ) ) return true ; return ( reload_completed && mep_interrupt_saved_reg ( regno ) ) ; } </s>

Return true if epilogue uses register REGNO .


<s> static const predefined_function_abi & aarch64_sve_abi ( void ) { predefined_function_abi & sve_abi = function_abis [ ARM_PCS_SVE ] ; if ( ! sve_abi . initialized_p ( ) ) { HARD_REG_SET full_reg_clobbers = default_function_abi . full_reg_clobbers ( ) ; for ( int regno = V8_REGNUM ; regno <= V23_REGNUM ; ++ regno ) CLEAR_HARD_REG_BIT ( full_reg_clobbers , regno ) ; for ( int regno = P4_REGNUM ; regno <= P15_REGNUM ; ++ regno ) CLEAR_HARD_REG_BIT ( full_reg_clobbers , regno ) ; sve_abi . initialize ( ARM_PCS_SVE , full_reg_clobbers ) ; } return sve_abi ; } </s>


<s> static void ix86_emit_leave ( void ) { struct machine_function * m = cfun -> machine ; rtx insn = emit_insn ( ix86_gen_leave ( ) ) ; ix86_add_queued_cfa_restore_notes ( insn ) ; gcc_assert ( m -> fs . fp_valid ) ; m -> fs . sp_valid = true ; m -> fs . sp_offset = m -> fs . fp_offset - UNITS_PER_WORD ; m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset ) ; } </s>

Emit code and notes for the LEAVE instruction .


<s> static void recombine_lvx_stvx_patterns ( function * fun ) { int i ; basic_block bb ; rtx_insn * insn ; int num_insns = get_max_uid ( ) ; del_info * to_delete = XCNEWVEC ( del_info , num_insns ) ; FOR_ALL_BB_FN ( bb , fun ) FOR_BB_INSNS ( bb , insn ) { if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( insn_is_load_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_lvx_pattern ( insn , to_delete ) ; else if ( insn_is_store_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_stvx_pattern ( insn , to_delete ) ; } for ( i = 0 ; i < num_insns ; i ++ ) if ( to_delete [ i ] . replace ) { rtx swap_body = PATTERN ( to_delete [ i ] . replace_insn ) ; rtx src_reg = XEXP ( SET_SRC ( swap_body ) , 0 ) ; rtx copy = gen_rtx_SET ( SET_DEST ( swap_body ) , src_reg ) ; rtx_insn * new_insn = emit_insn_before ( copy , to_delete [ i ] . replace_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( to_delete [ i ] . replace_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( to_delete [ i ] . replace_insn ) ; remove_insn ( to_delete [ i ] . replace_insn ) ; to_delete [ i ] . replace_insn -> set_deleted ( ) ; } free ( to_delete ) ; } </s>

Look for patterns created from builtin lvx and stvx calls , and canonicalize them to be properly recognized as such .


<s> bool SparcPassConfig :: addInstSelector ( ) { addPass ( createSparcISelDag ( getSparcTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || N -> getOpcode ( ) == X86ISD :: TC_RETURN ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , NULL , 0 , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , DstVT , dl , Store , MemTmp , NULL , 0 , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 || TargetTriple . getOS ( ) == Triple :: NaCl ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( ix86_use_mask_cmp_p ( mode , cmp_ops_mode , op_true , op_false ) ) { unsigned int nbits = GET_MODE_NUNITS ( cmp_ops_mode ) ; maskcmp = true ; cmp_mode = nbits > 8 ? int_mode_for_size ( nbits , 0 ) . require ( ) : E_QImode ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; int ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp ) { bool ok = ix86_expand_mask_vec_cmp ( dest , code , cmp_op0 , cmp_op1 ) ; gcc_assert ( ok ) ; return dest ; } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d64QPseudo : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> const TargetRegisterClass * X86RegisterInfo :: getGPRsForTailCall ( const MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( IsWin64 || ( F . getCallingConv ( ) == CallingConv :: Win64 ) ) return & X86 :: GR64_TCW64RegClass ; else if ( Is64Bit ) return & X86 :: GR64_TCRegClass ; bool hasHipeCC = ( F . getCallingConv ( ) == CallingConv :: HiPE ) ; if ( hasHipeCC ) return & X86 :: GR32RegClass ; return & X86 :: GR32_TCRegClass ; } </s>

getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls .


<s> DecodeStatus AArch64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { CommentStream = & cs ; uint8_t bytes [ 4 ] ; Size = 0 ; if ( Region . readBytes ( Address , 4 , ( uint8_t * ) bytes ) == - 1 ) return Fail ; Size = 4 ; uint32_t insn = ( bytes [ 3 ] << 24 ) | ( bytes [ 2 ] << 16 ) | ( bytes [ 1 ] << 8 ) | ( bytes [ 0 ] << 0 ) ; return decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> bool SystemZInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != SystemZ :: LHIMux && DefOpc != SystemZ :: LHI && DefOpc != SystemZ :: LGHI ) return false ; if ( DefMI . getOperand ( 0 ) . getReg ( ) != Reg ) return false ; int32_t ImmVal = ( int32_t ) DefMI . getOperand ( 1 ) . getImm ( ) ; unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc ; unsigned UseIdx ; int CommuteIdx = - 1 ; bool TieOps = false ; switch ( UseOpc ) { case SystemZ :: SELRMux : TieOps = true ; LLVM_FALLTHROUGH ; case SystemZ :: LOCRMux : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCHIMux ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; case SystemZ :: SELGR : TieOps = true ; LLVM_FALLTHROUGH ; case SystemZ :: LOCGR : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCGHI ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; default : return false ; } if ( CommuteIdx != - 1 ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; if ( TieOps ) UseMI . tieOperands ( 0 , 1 ) ; UseMI . getOperand ( UseIdx ) . ChangeToImmediate ( ImmVal ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } </s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> static bool aarch64_const_vec_all_in_range_p ( rtx vec , HOST_WIDE_INT minval , HOST_WIDE_INT maxval ) { if ( GET_CODE ( vec ) != CONST_VECTOR || GET_MODE_CLASS ( GET_MODE ( vec ) ) != MODE_VECTOR_INT ) return false ; int nunits ; if ( ! CONST_VECTOR_STEPPED_P ( vec ) ) nunits = const_vector_encoded_nelts ( vec ) ; else if ( ! CONST_VECTOR_NUNITS ( vec ) . is_constant ( & nunits ) ) return false ; for ( int i = 0 ; i < nunits ; i ++ ) { rtx vec_elem = CONST_VECTOR_ELT ( vec , i ) ; if ( ! CONST_INT_P ( vec_elem ) || ! IN_RANGE ( INTVAL ( vec_elem ) , minval , maxval ) ) return false ; } return true ; } </s>

Return true if VEC is a constant in which every element is in the range [ MINVAL , MAXVAL ] . The elements do not need to have the same value .


<s> bool ARMBaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return std :: unique_ptr < MCObjectWriter > ( createTOYELFObjectWriter ( OS , OSABI ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"frame pointer should not have been eliminated"


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && ( MI -> isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareAndBranch ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI -> definesRegister ( SystemZ :: CC ) ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( MI -> readsRegister ( SystemZ :: CC ) && CompleteCCUsers ) CCUsers . push_back ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ 4 SystemZ::CC SystemZ::CC


<s> void SICAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned MandarinInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { MI -> dump ( ) ; return 0 ; } </s>


<s> rtx expand ( function_expander & e ) const OVERRIDE { for ( unsigned int i = 0 ; i < 2 ; ++ i ) e . args [ i ] = e . convert_to_pmode ( e . args [ i ] ) ; return e . use_exact_insn ( code_for_while ( m_unspec , Pmode , e . gp_mode ( 0 ) ) ) ; } </s>


<s> X86GenInstrInfo :: MachineOutlinerInstrType X86InstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MIT , unsigned Flags ) const { MachineInstr & MI = * MIT ; if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( MI . isKill ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> void MipsOptimizeMathLibCalls :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetLibraryInfo > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void mips_expand_conditional_move ( rtx * operands ) { rtx cond ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = XEXP ( operands [ 1 ] , 0 ) ; rtx op1 = XEXP ( operands [ 1 ] , 1 ) ; mips_emit_compare ( & code , & op0 , & op1 , true ) ; cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; if ( ISA_HAS_SEL && INTEGRAL_MODE_P ( GET_MODE ( operands [ 2 ] ) ) && register_operand ( operands [ 2 ] , VOIDmode ) && register_operand ( operands [ 3 ] , VOIDmode ) ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; rtx temp = gen_reg_rtx ( mode ) ; rtx temp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ 2 ] , const0_rtx ) ) ) ; cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , GET_MODE ( op0 ) , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( temp2 , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ 3 ] , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IOR ( mode , temp , temp2 ) ) ) ; } else { if ( FLOAT_MODE_P ( GET_MODE ( operands [ 2 ] ) ) && ! ISA_HAS_SEL ) { operands [ 2 ] = force_reg ( GET_MODE ( operands [ 0 ] ) , operands [ 2 ] ) ; operands [ 3 ] = force_reg ( GET_MODE ( operands [ 0 ] ) , operands [ 3 ] ) ; } emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , cond , operands [ 2 ] , operands [ 3 ] ) ) ) ; } } </s>

Perform the comparison in OPERANDS [ 1 ] . Move OPERANDS [ 2 ] into OPERANDS [ 0 ] if the condition holds , otherwise move OPERANDS [ 3 ] into OPERANDS [ 0 ] .


<s>
unsigned
PPCTTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
)
const
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> SDNode * TOYDAGToDAGISel :: Select ( SDNode * N ) { return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s>
int
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
needsStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
if
(
!
IgnoreSPUpdates
&&
!
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
return
getFrameIndexReferenceSP
(
MF
,
FI
,
FrameReg
,
StackSize
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : break ; } unsigned Idx = 1 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > 4 ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; Idx = 0 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> static bool arm_needs_doubleword_align ( machine_mode mode , const_tree type ) { if ( ! type ) return PARM_BOUNDARY < GET_MODE_ALIGNMENT ( mode ) ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) return true ; return false ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


<s>
const
char
*
nds32_output_32bit_load_s
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
;
code
=
XEXP
(
operands
[
1
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
GET_CODE
(
code
)
)
{
case
REG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi\t%%0, %%1"
,
size
)
;
break
;
case
SYMBOL_REF
:
case
CONST
:
operands
[
1
]
=
XEXP
(
operands
[
1
]
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi.gp\t%%0, [ + %%1]"
,
size
)
;
break
;
case
POST_INC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi.bi\t%%0, %%1, %d"
,
size
,
byte
)
;
break
;
case
POST_DEC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi.bi\t%%0, %%1, -%d"
,
size
,
byte
)
;
break
;
case
POST_MODIFY
:
switch
(
GET_CODE
(
XEXP
(
XEXP
(
code
,
1
)
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%cs.bi\t%%0, %%1"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi.bi\t%%0, %%1"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
PLUS
:
switch
(
GET_CODE
(
XEXP
(
code
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%cs\t%%0, %%1"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi\t%%0, %%1"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
LO_SUM
:
operands
[
2
]
=
XEXP
(
code
,
1
)
;
operands
[
1
]
=
XEXP
(
code
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%csi\t%%0, [%%1 + lo12(%%2)]"
,
size
)
;
break
;
default
:
abort
(
)
;
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output 32-bit load with signed extension .


<s> bool LC2200InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return false ; } SmallVector < MachineInstr * , 4 > BranchInstrs ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return true ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! getAnalyzableBrOpc ( SecondLastOpc ) ) return true ; } if ( ! SecondLastOpc || ( SecondLastOpc != LC2200 :: JMP && SecondLastOpc != LC2200 :: CMP_JMP && SecondLastOpc != LC2200 :: GOTO ) ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return true ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) { return true ; } TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return false ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return true ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( MachineFunction & MF , const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> static bool or1k_legitimize_address_displacement ( rtx * off1 , rtx * off2 , poly_int64 poly_offset , machine_mode ) { HOST_WIDE_INT orig_offset = poly_offset ; HOST_WIDE_INT lo , hi ; if ( orig_offset >= 0 && orig_offset < 2 * 32767 ) { hi = 32767 ; lo = orig_offset - hi ; } else if ( orig_offset < 0 && orig_offset >= 2 * - 32768 ) { hi = - 32768 ; lo = orig_offset - hi ; } else { lo = sext_hwi ( orig_offset , 16 ) ; hi = orig_offset - lo ; } * off1 = GEN_INT ( hi ) ; * off2 = GEN_INT ( lo ) ; return true ; } </s>

Worker for TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT . Split an out-of-range address displacement into hi and lo parts . The hi part will have to be loaded into a register separately , but the low part will be folded into the memory operand .


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( ( FlagSfiLoad && N -> getOpcode ( ) == ISD :: LOAD ) || ( FlagSfiStore && N -> getOpcode ( ) == ISD :: STORE ) ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == ISD :: ADD && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::LOAD ISD::STORE ISD::SEXTLOAD ARM ISD::ADD ISD::POST_INC ISD::POST_DEC


<s> bool X86AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
int
AArch64AsmParser
::
tryParseRegister
(
)
{
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
unsigned
RegNum
=
matchRegisterNameAlias
(
lowerCase
,
false
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
AArch64
::
FP
)
.
Case
(
"lr"
,
AArch64
::
LR
)
.
Case
(
"x31"
,
AArch64
::
XZR
)
.
Case
(
"w31"
,
AArch64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s>
StringRef
getPassName
(
)
const
override
{
return
"LoongArch Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> virtual unsigned int execute ( function * fun ) { return pcrel_opt_pass ( fun ) ; } </s>


The darwin64 ABI calls for us to recurse down through structs , looking for elements passed in registers . Unfortunately , we have to track int register count here also because of misalignments in powerpc alignment mode .


<s> static bool rs6000_secondary_memory_needed ( machine_mode mode , reg_class_t from_class , reg_class_t to_class ) { enum rs6000_reg_type from_type , to_type ; bool altivec_p = ( ( from_class == ALTIVEC_REGS ) || ( to_class == ALTIVEC_REGS ) ) ; from_type = reg_class_to_reg_type [ ( int ) from_class ] ; to_type = reg_class_to_reg_type [ ( int ) to_class ] ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , ( secondary_reload_info * ) 0 , altivec_p ) ) return false ; if ( IS_FP_VECT_REG_TYPE ( from_type ) || IS_FP_VECT_REG_TYPE ( to_type ) ) return true ; return false ; } </s>

If we are copying between FP or AltiVec registers and anything else , we need a memory location . The exception is when we are targeting ppc64 and the move to/from fpr to gpr instructions are available . Also , under VSX , you can copy vector registers from the FP register set to the Altivec register set and vice versa .


<s>
TargetTransformInfo
::
PopcntSupportKind
PPCTTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
ST
->
hasPOPCNTD
(
)
!=
PPCSubtarget
::
POPCNTD_Unavailable
&&
TyWidth
<=
64
)
return
ST
->
hasPOPCNTD
(
)
==
PPCSubtarget
::
POPCNTD_Slow
TTI
::
PSK_SlowHardware
:
TTI
::
PSK_FastHardware
;
return
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .

PowerPC
PPC
"Ty width must be power of 2"
PPC
64
PPC


<s>
bool
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
const
X86Subtarget
&
Subtarget
=
getTargetMachine
(
)
.
getSubtarget
<
X86Subtarget
>
(
)
;
unsigned
NativeWidth
=
Subtarget
.
is64Bit
(
)
64
:
32
;
const
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
return
needsCmpXchgNb
(
MemType
)
;
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
false
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
return
true
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> bool aarch64_address_valid_for_prefetch_p ( rtx x , bool strict_p ) { struct aarch64_address_info addr ; bool res = aarch64_classify_address ( & addr , x , DImode , strict_p ) ; if ( ! res ) return false ; return addr . type != ADDRESS_REG_WB ; } </s>

Return true if the address X is valid for a PRFM instruction . STRICT_P is true if we should do strict checking with aarch64_classify_address .


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE && TREE_CODE ( type ) != OPAQUE_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_long_type_node ) return "U6__boolx" ; if ( type == float128_type_node || type == float64x_type_node ) return NULL ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return "g" ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return "u9__ieee128" ; if ( type == vector_pair_type_node ) return "u13__vector_pair" ; if ( type == vector_quad_type_node ) return "u13__vector_quad" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


<s> static void delete_output_files ( void ) { fclose ( header_file ) ; fclose ( init_file ) ; fclose ( defines_file ) ; remove ( header_path ) ; remove ( init_path ) ; remove ( defines_path ) ; } </s>

Close and delete output files after any failure , so that subsequent build dependencies will fail .


<s> unsigned AArch64TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case Intrinsic :: smin : case Intrinsic :: umin : case Intrinsic :: smax : case Intrinsic :: umax : { static const auto ValidMinMaxTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } default : break ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> void ix86_expand_convert_uns_sidf_sse ( rtx target , rtx input ) { REAL_VALUE_TYPE TWO31r ; rtx x , fp ; x = expand_simple_binop ( SImode , PLUS , input , GEN_INT ( - 2147483647 - 1 ) , NULL , 1 , OPTAB_DIRECT ) ; fp = gen_reg_rtx ( DFmode ) ; emit_insn ( gen_floatsidf2 ( fp , x ) ) ; real_ldexp ( & TWO31r , & dconst1 , 31 ) ; x = const_double_from_real_value ( TWO31r , DFmode ) ; x = expand_simple_binop ( DFmode , PLUS , fp , x , target , 0 , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( DFmode ) && flag_rounding_math ) x = ix86_expand_sse_fabs ( x , NULL ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Convert an unsigned SImode value into a DFmode . Only currently used for SSE , but applicable anywhere .


<s> void arm_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED ) { pcum -> nregs = ( ( fntype && aggregate_value_p ( TREE_TYPE ( fntype ) , fntype ) ) ? 1 : 0 ) ; pcum -> iwmmxt_nregs = 0 ; pcum -> can_split = true ; pcum -> call_cookie = CALL_NORMAL ; if ( TARGET_LONG_CALLS ) pcum -> call_cookie = CALL_LONG ; if ( fntype ) { if ( lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( fntype ) ) ) pcum -> call_cookie = CALL_SHORT ; else if ( lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( fntype ) ) ) pcum -> call_cookie = CALL_LONG ; } pcum -> named_count = 0 ; pcum -> nargs = 0 ; if ( TARGET_REALLY_IWMMXT && fntype ) { tree fn_arg ; for ( fn_arg = TYPE_ARG_TYPES ( fntype ) ; fn_arg ; fn_arg = TREE_CHAIN ( fn_arg ) ) pcum -> named_count += 1 ; if ( ! pcum -> named_count ) pcum -> named_count = INT_MAX ; } } </s>

Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is NULL .


<s>
SDValue
SystemZTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

SystemZ
SystemZ
ISD::BR_CC
ISD::SELECT_CC
ISD::GlobalAddress
ISD::JumpTable
ISD::ConstantPool
"Should not custom lower this!"


<s> bool MipsAsmBackend :: getFixupKind ( StringRef Name , MCFixupKind & MappedKind ) const { if ( Name == "R_MIPS_NONE" ) { MappedKind = ( MCFixupKind ) Mips :: fixup_Mips_NONE ; return true ; } if ( Name == "R_MIPS_32" ) { MappedKind = FK_Data_4 ; return true ; } return MCAsmBackend :: getFixupKind ( Name , MappedKind ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static int optimal_immediate_sequence ( enum rtx_code code , unsigned HOST_WIDE_INT val , struct four_ints * return_sequence ) { int best_consecutive_zeros = 0 ; int i ; int best_start = 0 ; int insns1 , insns2 ; struct four_ints tmp_sequence ; if ( TARGET_ARM ) { for ( i = 0 ; i < 32 ; i += 2 ) { int consecutive_zeros = 0 ; if ( ! ( val & ( 3 << i ) ) ) { while ( ( i < 32 ) && ! ( val & ( 3 << i ) ) ) { consecutive_zeros += 2 ; i += 2 ; } if ( consecutive_zeros > best_consecutive_zeros ) { best_consecutive_zeros = consecutive_zeros ; best_start = i - consecutive_zeros ; } i -= 2 ; } } } insns1 = optimal_immediate_sequence_1 ( code , val , return_sequence , best_start ) ; if ( best_start != 0 && ( ( ( ( unsigned HOST_WIDE_INT ) 1 ) << best_start ) < val ) ) { insns2 = optimal_immediate_sequence_1 ( code , val , & tmp_sequence , 0 ) ; if ( insns2 <= insns1 ) { * return_sequence = tmp_sequence ; insns1 = insns2 ; } } return insns1 ; } </s>

Return a sequence of integers , in RETURN_SEQUENCE that fit into ARM/THUMB2 immediates , and add up to VAL . Thr function return value gives the number of insns required .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool VEAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool fusion_gpr_load_p ( rtx addis_reg , rtx addis_value , rtx target , rtx mem ) { rtx addr ; rtx base_reg ; if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! base_reg_operand ( target , GET_MODE ( target ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( mem ) == ZERO_EXTEND || ( GET_CODE ( mem ) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN ) ) mem = XEXP ( mem , 0 ) ; if ( ! MEM_P ( mem ) ) return false ; if ( ! fusion_gpr_mem_load ( mem , GET_MODE ( mem ) ) ) return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) != PLUS && GET_CODE ( addr ) != LO_SUM ) return false ; if ( REGNO ( addis_reg ) != REGNO ( target ) ) { if ( reg_mentioned_p ( target , mem ) ) return false ; if ( ! peep2_reg_dead_p ( 2 , addis_reg ) ) return false ; if ( REG_P ( target ) && REGNO ( target ) == STACK_POINTER_REGNUM ) return false ; } base_reg = XEXP ( addr , 0 ) ; return REGNO ( addis_reg ) == REGNO ( base_reg ) ; } </s>

Return true if the peephole2 can combine a load involving a combination of an addis instruction and a load with an offset that can be fused together on a power8 .


<s> static void mips_for_each_saved_acc ( HOST_WIDE_INT sp_offset , mips_save_restore_fn fn ) { HOST_WIDE_INT offset ; int regno ; offset = cfun -> machine -> frame . acc_sp_offset - sp_offset ; if ( BITSET_P ( cfun -> machine -> frame . acc_mask , 0 ) ) { mips_save_restore_reg ( word_mode , LO_REGNUM , offset , fn ) ; offset -= UNITS_PER_WORD ; mips_save_restore_reg ( word_mode , HI_REGNUM , offset , fn ) ; offset -= UNITS_PER_WORD ; } for ( regno = DSP_ACC_REG_FIRST ; regno <= DSP_ACC_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . acc_mask , ( ( regno - DSP_ACC_REG_FIRST ) / 2 ) + 1 ) ) { mips_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } } </s>

Call FN for each accumlator that is saved by the current function . SP_OFFSET is the offset of the current stack pointer from the start of the frame .


<s> const uint16_t * LanaiRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { return CSR_SaveList ; } </s>


<s> void X86PassConfig :: addPreEmitPass2 ( ) { addPass ( createX86RetpolineThunksPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( ! TT . isOSDarwin ( ) && ! TT . isOSWindows ( ) ) addPass ( createCFIInstrInserter ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static bool quad_aligned_store_p ( swap_web_entry * insn_entry , rtx_insn * insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || ! insn_entry [ uid ] . is_store ) return false ; rtx body = PATTERN ( insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , 0 ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , 0 ) ; if ( ! REG_P ( dest_address ) && ! rs6000_sum_of_two_registers_p ( dest_address ) ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load || insn_entry [ uid2 ] . is_store ) return false ; break ; } rtx set = single_set ( insn ) ; if ( set ) { rtx dest = SET_DEST ( set ) ; if ( MEM_P ( dest ) ) return ( MEM_ALIGN ( dest ) >= 128 ) ; } return false ; } </s>

Return TRUE if INSN represents a store-with-swap of a swapped value and the memory address is quad-word aligned .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasAVX ( ) && Subtarget -> getStackAlignment ( ) >= 32 ) return MVT :: v8f32 ; if ( Subtarget -> hasXMMInt ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasXMM ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasXMMInt ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static void mips_output_64bit_xfer ( char direction , unsigned int gpreg , unsigned int fpreg ) { if ( TARGET_64BIT ) fprintf ( asm_out_file , "\tdm%cc1\t%s,%s\n" , direction , reg_names [ gpreg ] , reg_names [ fpreg ] ) ; else if ( ISA_HAS_MXHC1 ) { fprintf ( asm_out_file , "\tm%cc1\t%s,%s\n" , direction , reg_names [ gpreg + TARGET_BIG_ENDIAN ] , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , "\tm%chc1\t%s,%s\n" , direction , reg_names [ gpreg + TARGET_LITTLE_ENDIAN ] , reg_names [ fpreg ] ) ; } else if ( TARGET_FLOATXX && direction == 't' ) { fprintf ( asm_out_file , "\tsw\t%s,0($sp)\n" , reg_names [ gpreg ] ) ; fprintf ( asm_out_file , "\tsw\t%s,4($sp)\n" , reg_names [ gpreg + 1 ] ) ; fprintf ( asm_out_file , "\tldc1\t%s,0($sp)\n" , reg_names [ fpreg ] ) ; } else if ( TARGET_FLOATXX && direction == 'f' ) { fprintf ( asm_out_file , "\tsdc1\t%s,0($sp)\n" , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , "\tlw\t%s,0($sp)\n" , reg_names [ gpreg ] ) ; fprintf ( asm_out_file , "\tlw\t%s,4($sp)\n" , reg_names [ gpreg + 1 ] ) ; } else { fprintf ( asm_out_file , "\tm%cc1\t%s,%s\n" , direction , reg_names [ gpreg + TARGET_BIG_ENDIAN ] , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , "\tm%cc1\t%s,%s\n" , direction , reg_names [ gpreg + TARGET_LITTLE_ENDIAN ] , reg_names [ fpreg + 1 ] ) ; } } </s>


<s>
static
void
nds32_asm_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
int
r
;
const
char
*
func_name
;
tree
attrs
;
tree
name
;
fprintf
(
file
,
"\t! BEGIN PROLOGUE\n"
)
;
fprintf
(
file
,
"\t!     fp needed: %d\n"
,
frame_pointer_needed
)
;
fprintf
(
file
,
"\t!  pretend_args: %d\n"
,
cfun
->
machine
->
va_args_size
)
;
fprintf
(
file
,
"\t!    local_size: %d\n"
,
cfun
->
machine
->
local_size
)
;
fprintf
(
file
,
"\t! out_args_size: %d\n"
,
cfun
->
machine
->
out_args_size
)
;
fprintf
(
file
,
"\t! registers ever_live: "
)
;
for
(
r
=
0
;
r
<
32
;
r
++
)
{
if
(
df_regs_ever_live_p
(
r
)
)
fprintf
(
file
,
"%s, "
,
reg_names
[
r
]
)
;
}
fputc
(
'\n'
,
file
)
;
fprintf
(
file
,
"\t! function attributes: "
)
;
attrs
=
DECL_ATTRIBUTES
(
current_function_decl
)
;
if
(
!
attrs
)
fprintf
(
file
,
"None"
)
;
func_name
=
IDENTIFIER_POINTER
(
DECL_NAME
(
current_function_decl
)
)
;
nds32_construct_isr_vectors_information
(
attrs
,
func_name
)
;
while
(
attrs
)
{
name
=
TREE_PURPOSE
(
attrs
)
;
fprintf
(
file
,
"%s "
,
IDENTIFIER_POINTER
(
name
)
)
;
attrs
=
TREE_CHAIN
(
attrs
)
;
}
fputc
(
'\n'
,
file
)
;
}
</s>

The content produced from this function will be placed before prologue body .

nds32
"\t! BEGIN PROLOGUE\n"
"\t!     fp needed: %d\n"
"\t!  pretend_args: %d\n"
"\t!    local_size: %d\n"
"\t! out_args_size: %d\n"
"\t! registers ever_live: "
0
32
"%s, "
"\t! function attributes: "
"None"
"%s "


<s> bool AArch64PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> void ix86_expand_reduc ( rtx ( * fn ) ( rtx , rtx , rtx ) , rtx dest , rtx in ) { rtx half , dst , vec = in ; machine_mode mode = GET_MODE ( in ) ; int i ; if ( TARGET_SSE4_1 && mode == V8HImode && fn == gen_uminv8hi3 ) { emit_insn ( gen_sse4_1_phminposuw ( dest , in ) ) ; return ; } for ( i = GET_MODE_BITSIZE ( mode ) ; i > GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; i >>= 1 ) { half = gen_reg_rtx ( mode ) ; emit_reduc_half ( half , vec , i ) ; if ( i == GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) * 2 ) dst = dest ; else dst = gen_reg_rtx ( mode ) ; emit_insn ( fn ( dst , half , vec ) ) ; vec = dst ; } } </s>

Expand a vector reduction . FN is the binary pattern to reduce ; DEST is the destination ; IN is the input vector .


<s>
void
SystemZPostRASchedStrategy
::
enterMBB
(
MachineBasicBlock
*
NextMBB
)
{
assert
(
(
SchedStates
.
find
(
NextMBB
)
==
SchedStates
.
end
(
)
)
&&
"Entering MBB twice?"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Entering "
<<
printMBBReference
(
*
NextMBB
)
)
;
MBB
=
NextMBB
;
HazardRec
=
SchedStates
[
MBB
]
=
new
SystemZHazardRecognizer
(
TII
,
&
SchedModel
)
;
LLVM_DEBUG
(
const
MachineLoop
*
Loop
=
MLI
->
getLoopFor
(
MBB
)
;
if
(
Loop
&&
Loop
->
getHeader
(
)
==
MBB
)
dbgs
(
)
<<
" (Loop header)"
;
dbgs
(
)
<<
":\n"
;
)
;
MachineBasicBlock
*
SinglePredMBB
=
getSingleSchedPred
(
MBB
,
MLI
->
getLoopFor
(
MBB
)
)
;
if
(
SinglePredMBB
==
nullptr
||
SchedStates
.
find
(
SinglePredMBB
)
==
SchedStates
.
end
(
)
)
return
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Continued scheduling from "
<<
printMBBReference
(
*
SinglePredMBB
)
<<
"\n"
;
)
;
HazardRec
->
copyState
(
SchedStates
[
SinglePredMBB
]
)
;
LLVM_DEBUG
(
HazardRec
->
dumpState
(
)
;
)
;
for
(
MachineBasicBlock
::
iterator
I
=
SinglePredMBB
->
getFirstTerminator
(
)
;
I
!=
SinglePredMBB
->
end
(
)
;
I
++
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Emitting incoming branch: "
;
I
->
dump
(
)
;
)
;
bool
TakenBranch
=
(
I
->
isBranch
(
)
&&
(
TII
->
getBranchInfo
(
*
I
)
.
Target
->
isReg
(
)
||
TII
->
getBranchInfo
(
*
I
)
.
Target
->
getMBB
(
)
==
MBB
)
)
;
HazardRec
->
emitInstruction
(
&
*
I
,
TakenBranch
)
;
if
(
TakenBranch
)
break
;
}
}
</s>

Tell the strategy that MBB is about to be processed .

SystemZ
SystemZ
"Entering MBB twice?"
"** Entering "
SystemZ
" (Loop header)"
":\n"
"** Continued scheduling from "
"\n"
"** Emitting incoming branch: "


<s> static unsigned rs6000_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost += adjust_vectorization_cost ( kind , stmt_info ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; if ( ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec ) || ( where == vect_body && kind == vector_stmt ) ) rs6000_vect_nonmem = true ; } return retval ; } </s>


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Soft ; } </s>


<s> rtx crx_function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { last_parm_in_reg = 0 ; if ( type == void_type_node ) return NULL_RTX ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || ( cum -> ints < 0 ) ) return NULL_RTX ; if ( mode == BLKmode ) { if ( enough_regs_for_param ( cum , type , mode ) != 0 ) { last_parm_in_reg = 1 ; return gen_rtx_REG ( mode , MIN_REG_FOR_PASSING_ARGS + cum -> ints ) ; } } if ( MIN_REG_FOR_PASSING_ARGS + cum -> ints > MAX_REG_FOR_PASSING_ARGS ) return NULL_RTX ; else { if ( enough_regs_for_param ( cum , type , mode ) != 0 ) { last_parm_in_reg = 1 ; return gen_rtx_REG ( mode , MIN_REG_FOR_PASSING_ARGS + cum -> ints ) ; } } return NULL_RTX ; } </s>

Implements the macro FUNCTION_ARG defined in crx.h .


<s> bool SICAsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { MCOp = MCInstLowering . LowerOperand ( MO ) ; return MCOp . isValid ( ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> static bool aarch64_evpc_rev_local ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT diff ; unsigned int i , size , unspec ; machine_mode pred_mode ; if ( d -> vec_flags == VEC_SVE_PRED || ! d -> one_vector_p || ! d -> perm [ 0 ] . is_constant ( & diff ) || ! diff ) return false ; if ( d -> vec_flags & VEC_SVE_DATA ) size = ( diff + 1 ) * aarch64_sve_container_bits ( d -> vmode ) ; else size = ( diff + 1 ) * GET_MODE_UNIT_BITSIZE ( d -> vmode ) ; if ( size == 64 ) { unspec = UNSPEC_REV64 ; pred_mode = VNx2BImode ; } else if ( size == 32 ) { unspec = UNSPEC_REV32 ; pred_mode = VNx4BImode ; } else if ( size == 16 ) { unspec = UNSPEC_REV16 ; pred_mode = VNx8BImode ; } else return false ; unsigned int step = diff + 1 ; for ( i = 0 ; i < step ; ++ i ) if ( ! d -> perm . series_p ( i , step , diff - i , step ) ) return false ; if ( d -> testing_p ) return true ; if ( d -> vec_flags & VEC_SVE_DATA ) { rtx pred = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_sve_revbhw ( d -> vmode , pred_mode , d -> target , pred , d -> op0 ) ) ; return true ; } rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , unspec ) ; emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV { 64,32,16 } insns , which reverse elements within each 64-bit , 32-bit or 16-bit granule .


<s>
bool
WaitInsert
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
MF
.
getFunction
(
)
.
hasFnAttribute
(
Attribute
::
StrictFP
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MBB
.
begin
(
)
;
MI
!=
MBB
.
end
(
)
;
++
MI
)
{
if
(
!
isX87Instruction
(
*
MI
)
)
continue
;
if
(
!
(
MI
->
mayRaiseFPException
(
)
||
MI
->
mayLoadOrStore
(
)
)
||
isX87ControlInstruction
(
*
MI
)
)
continue
;
MachineBasicBlock
::
iterator
AfterMI
=
std
::
next
(
MI
)
;
if
(
AfterMI
!=
MBB
.
end
(
)
&&
isX87Instruction
(
*
AfterMI
)
&&
!
isX87NonWaitingControlInstruction
(
*
AfterMI
)
)
continue
;
BuildMI
(
MBB
,
AfterMI
,
MI
->
getDebugLoc
(
)
,
TII
->
get
(
X86
::
WAIT
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nInsert wait after:\t"
<<
*
MI
)
;
++
MI
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static rtx mips16e_build_save_restore ( bool restore_p , unsigned int * mask_ptr , HOST_WIDE_INT * offset_ptr , unsigned int nargs , HOST_WIDE_INT size ) { rtx pattern , set ; HOST_WIDE_INT offset , top_offset ; unsigned int i , regno ; int n ; gcc_assert ( cfun -> machine -> frame . num_fp == 0 ) ; n = 1 + nargs ; for ( i = 0 ; i < ARRAY_SIZE ( mips16e_save_restore_regs ) ; i ++ ) if ( BITSET_P ( * mask_ptr , mips16e_save_restore_regs [ i ] ) ) n ++ ; pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( n ) ) ; n = 0 ; set = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , restore_p ? size : - size ) ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; XVECEXP ( pattern , 0 , n ++ ) = set ; top_offset = restore_p ? size : 0 ; for ( i = 0 ; i < nargs ; i ++ ) { offset = top_offset + i * UNITS_PER_WORD ; set = mips16e_save_restore_reg ( restore_p , true , offset , GP_ARG_FIRST + i ) ; XVECEXP ( pattern , 0 , n ++ ) = set ; } offset = top_offset ; for ( i = 0 ; i < ARRAY_SIZE ( mips16e_save_restore_regs ) ; i ++ ) { regno = mips16e_save_restore_regs [ i ] ; if ( BITSET_P ( * mask_ptr , regno ) ) { offset -= UNITS_PER_WORD ; set = mips16e_save_restore_reg ( restore_p , false , offset , regno ) ; XVECEXP ( pattern , 0 , n ++ ) = set ; * mask_ptr &= ~ ( 1 << regno ) ; } } * offset_ptr = size + ( offset - top_offset ) ; gcc_assert ( n == XVECLEN ( pattern , 0 ) ) ; return pattern ; } </s>

Return RTL for a MIPS16e SAVE or RESTORE instruction ; RESTORE_P says which . The instruction must : - Allocate or deallocate SIZE bytes in total ; SIZE is known to be nonzero . - Save or restore as many registers in * MASK_PTR as possible . The instruction saves the first registers at the top of the allocated area , with the other registers below it . - Save NARGS argument registers above the allocated area . ( NARGS is always zero if RESTORE_P . ) The SAVE and RESTORE instructions can not save and restore all general registers , so there may be some registers left over for the caller to handle . Destructively modify * MASK_PTR so that it contains the registers that still need to be saved or restored . The caller can save these registers in the memory immediately below * OFFSET_PTR , which is a byte offset from the bottom of the allocated stack area .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> static tree rs6000_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { HOST_WIDE_INT fnmask ; if ( code >= RS6000_BUILTIN_COUNT ) return error_mark_node ; fnmask = rs6000_builtin_info [ code ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) { rs6000_invalid_builtin ( ( enum rs6000_builtins ) code ) ; return error_mark_node ; } return rs6000_builtin_decls [ code ] ; } </s>

Returns the rs6000 builtin decl for CODE .


Load the specified register of the given register class from the specified stack frame index .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .