<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
static_cast
<
const
AArch64FrameLowering
*
>
(
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> rtx rs6000_allocate_stack_temp ( machine_mode mode , bool offsettable_p , bool reg_reg_p ) { rtx stack = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; rtx addr = XEXP ( stack , 0 ) ; int strict_p = reload_completed ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) ) { if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; } return stack ; } </s>

Allocate a stack temp and fixup the address so it meets the particular memory requirements ( either offetable or REG+REG addressing ) .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::BlockAddress
ISD::GlobalAddress
ISD::VASTART
ISD::VAARG


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static bool ia64_expand_vecint_compare ( enum rtx_code code , machine_mode mode , rtx dest , rtx op0 , rtx op1 ) { bool negate = false ; rtx x ; switch ( code ) { case EQ : case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = op0 , op0 = op1 , op1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V2SImode : { rtx t1 , t2 , mask ; mask = gen_int_mode ( 0x80000000 , SImode ) ; mask = gen_rtx_CONST_VECTOR ( V2SImode , gen_rtvec ( 2 , mask , mask ) ) ; mask = force_reg ( mode , mask ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t1 , op0 , mask ) ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t2 , op1 , mask ) ) ; op0 = t1 ; op1 = t2 ; code = GT ; } break ; case V8QImode : case V4HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_US_MINUS ( mode , op0 , op1 ) ) ) ; code = EQ ; op0 = x ; op1 = CONST0_RTX ( mode ) ; negate = ! negate ; break ; default : gcc_unreachable ( ) ; } } x = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; return negate ; } </s>

Generate an integral vector comparison . Return true if the condition has been reversed , and so the sense of the comparison should be inverted .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { NumStores ++ ; Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; if ( ( MemAccessTy -> isIntegerTy ( ) || MemAccessTy -> isFloatingPointTy ( ) ) && ( getDataLayout ( ) . getTypeSizeInBits ( MemAccessTy ) == 128 ) ) NumStores ++ ; } } unsigned const Max = ( NumStores ? ( 12 / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const uint16_t * RegList = ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>


<s> static void mips_va_start ( tree valist , rtx nextarg ) { if ( EABI_FLOAT_VARARGS_P ) { const CUMULATIVE_ARGS * cum ; tree f_ovfl , f_gtop , f_ftop , f_goff , f_foff ; tree ovfl , gtop , ftop , goff , foff ; tree t ; int gpr_save_area_size ; int fpr_save_area_size ; int fpr_offset ; cum = & crtl -> args . info ; gpr_save_area_size = ( MAX_ARGS_IN_REGISTERS - cum -> num_gprs ) * UNITS_PER_WORD ; fpr_save_area_size = ( MAX_ARGS_IN_REGISTERS - cum -> num_fprs ) * UNITS_PER_FPREG ; f_ovfl = TYPE_FIELDS ( va_list_type_node ) ; f_gtop = DECL_CHAIN ( f_ovfl ) ; f_ftop = DECL_CHAIN ( f_gtop ) ; f_goff = DECL_CHAIN ( f_ftop ) ; f_foff = DECL_CHAIN ( f_goff ) ; ovfl = build3 ( COMPONENT_REF , TREE_TYPE ( f_ovfl ) , valist , f_ovfl , NULL_TREE ) ; gtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_gtop ) , valist , f_gtop , NULL_TREE ) ; ftop = build3 ( COMPONENT_REF , TREE_TYPE ( f_ftop ) , valist , f_ftop , NULL_TREE ) ; goff = build3 ( COMPONENT_REF , TREE_TYPE ( f_goff ) , valist , f_goff , NULL_TREE ) ; foff = build3 ( COMPONENT_REF , TREE_TYPE ( f_foff ) , valist , f_foff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( ovfl ) , virtual_incoming_args_rtx ) ; if ( cum -> stack_words > 0 ) t = fold_build_pointer_plus_hwi ( t , cum -> stack_words * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovfl ) , ovfl , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( gtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( gtop ) , gtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( ftop ) , virtual_incoming_args_rtx ) ; fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1 ; fpr_offset &= - UNITS_PER_FPVALUE ; if ( fpr_offset ) t = fold_build_pointer_plus_hwi ( t , - fpr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ftop ) , ftop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( goff ) , goff , build_int_cst ( TREE_TYPE ( goff ) , gpr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( foff ) , foff , build_int_cst ( TREE_TYPE ( foff ) , fpr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } else { nextarg = plus_constant ( Pmode , nextarg , - cfun -> machine -> varargs_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } } </s>


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
ATOMIC_LOAD_ADD
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMADD64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_AND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_NAND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMNAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_OR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_SUB
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSUB64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_XOR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMXOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSWAP64_DAG
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMCMPXCHG64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_MIN
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMMIN64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_UMIN
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMUMIN64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_MAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMMAX64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_UMAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMUMAX64_DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; PHINodeSet PromotablePHINodes = getPromotablePHINodes ( F ) ; B2IMap Bool2IntMap ; bool Changed = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { if ( ReturnInst * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( R -> getOperandUse ( 0 ) , PromotablePHINodes , Bool2IntMap ) ; if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> enum reg_class mep_preferred_reload_class ( rtx x , enum reg_class rclass ) { switch ( GET_CODE ( x ) ) { case CONST_INT : if ( INTVAL ( x ) >= 0x10000 && INTVAL ( x ) < 0x01000000 && ( INTVAL ( x ) & 0xffff ) != 0 && reg_class_subset_p ( TPREL_REGS , rclass ) ) rclass = TPREL_REGS ; break ; case CONST : case SYMBOL_REF : case LABEL_REF : if ( mep_section_tag ( x ) != 'f' && reg_class_subset_p ( TPREL_REGS , rclass ) ) rclass = TPREL_REGS ; break ; default : break ; } return rclass ; } </s>

Implement PREFERRED_RELOAD_CLASS . See whether X is a constant that can be moved directly into registers 0 to 7 , but not into the rest . If so , and if the required class includes registers 0 to 7 , restrict it to those registers .


<s> static unsigned long arm_compute_save_core_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; unsigned int reg ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( arm_current_function_pac_enabled_p ( ) ) save_reg_mask |= 1 << IP_REGNUM ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % 2 ) != 0 ) { for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == 0 ) { reg = thumb_find_work_register ( 1 << 4 ) ; if ( ! call_used_or_fixed_reg_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; } return save_reg_mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function . This is used by arm_compute_frame_layout , which may add extra registers .


<s> bool MipsSETargetLowering :: isEligibleForTailCallOptimization ( const MipsCC & MipsCCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! EnableMipsTailCalls ) return false ; if ( MipsCCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s>
void
arm_output_multireg_pop
(
rtx
*
operands
,
bool
return_pc
,
rtx
cond
,
bool
reverse
,
bool
update
)
{
int
i
;
char
pattern
[
100
]
;
int
offset
;
const
char
*
conditional
;
int
num_saves
=
XVECLEN
(
operands
[
0
]
,
0
)
;
unsigned
int
regno
;
unsigned
int
regno_base
=
REGNO
(
operands
[
1
]
)
;
bool
interrupt_p
=
IS_INTERRUPT
(
arm_current_func_type
(
)
)
;
offset
=
0
;
offset
+=
update
1
:
0
;
offset
+=
return_pc
1
:
0
;
for
(
i
=
offset
;
i
<
num_saves
;
i
++
)
{
regno
=
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
;
gcc_assert
(
(
regno
!=
SP_REGNUM
)
||
(
regno_base
==
SP_REGNUM
)
)
;
if
(
regno
==
regno_base
)
gcc_assert
(
!
update
)
;
}
conditional
=
reverse
"%?%D0"
:
"%?%d0"
;
if
(
(
regno_base
==
SP_REGNUM
)
&&
update
&&
!
(
interrupt_p
&&
return_pc
)
)
sprintf
(
pattern
,
"pop%s\t{"
,
conditional
)
;
else
{
if
(
regno_base
==
SP_REGNUM
)
sprintf
(
pattern
,
"ldmfd%s\t"
,
conditional
)
;
else
if
(
update
)
sprintf
(
pattern
,
"ldmia%s\t"
,
conditional
)
;
else
sprintf
(
pattern
,
"ldm%s\t"
,
conditional
)
;
strcat
(
pattern
,
reg_names
[
regno_base
]
)
;
if
(
update
)
strcat
(
pattern
,
"!, {"
)
;
else
strcat
(
pattern
,
", {"
)
;
}
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
offset
)
,
0
)
)
]
)
;
for
(
i
=
offset
+
1
;
i
<
num_saves
;
i
++
)
{
strcat
(
pattern
,
", "
)
;
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
]
)
;
}
strcat
(
pattern
,
"}"
)
;
if
(
interrupt_p
&&
return_pc
)
strcat
(
pattern
,
"^"
)
;
output_asm_insn
(
pattern
,
&
cond
)
;
}
</s>

OPERANDS [ 0 ] is the entire list of insns that constitute pop , OPERANDS [ 1 ] is the base register , RETURN_PC is true iff return insn is in the list , UPDATE is true iff the list contains explicit update of base register .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createSparcELFObjectWriter ( OS , Is64Bit , IsLittleEndian , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
static
void
rs6000_define_or_undefine_macro
(
bool
define_p
,
const
char
*
name
)
{
if
(
TARGET_DEBUG_BUILTIN
||
TARGET_DEBUG_TARGET
)
fprintf
(
stderr
,
"#%s %s\n"
,
(
define_p
)
"define"
:
"undef"
,
name
)
;
if
(
define_p
)
cpp_define
(
parse_in
,
name
)
;
else
cpp_undef
(
parse_in
,
name
)
;
}
</s>


<s> static rtx legitimize_pe_coff_symbol ( rtx addr , bool inreg ) { if ( ! TARGET_PECOFF ) return NULL_RTX ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES ) { if ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( addr ) ) return legitimize_dllimport_symbol ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ) { rtx t = legitimize_dllimport_symbol ( XEXP ( XEXP ( addr , 0 ) , 0 ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , 0 ) , 1 ) ) ; } } if ( ix86_cmodel != CM_LARGE_PIC && ix86_cmodel != CM_MEDIUM_PIC ) return NULL_RTX ; if ( GET_CODE ( addr ) == SYMBOL_REF && ! is_imported_p ( addr ) && SYMBOL_REF_EXTERNAL_P ( addr ) && SYMBOL_REF_DECL ( addr ) ) return legitimize_pe_coff_extern_decl ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF && ! is_imported_p ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) && SYMBOL_REF_EXTERNAL_P ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) && SYMBOL_REF_DECL ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ) { rtx t = legitimize_pe_coff_extern_decl ( XEXP ( XEXP ( addr , 0 ) , 0 ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , 0 ) , 1 ) ) ; } return NULL_RTX ; } </s>

Expand SYMBOL into its corresponding dllimport or refptr symbol . WANT_REG is true if we require the result be a register .


<s> bool arm_current_function_pac_enabled_p ( void ) { return ( aarch_ra_sign_scope == AARCH_FUNCTION_ALL || ( aarch_ra_sign_scope == AARCH_FUNCTION_NON_LEAF && ! crtl -> is_leaf ) ) ; } </s>

Return TRUE if return address signing mechanism is enabled .


<s> unsigned X86AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: EVEX ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: VEX ) return Match_Unsupported ; switch ( Opc ) { case X86 :: VCVTSD2SIZrm_Int : case X86 :: VCVTSD2SI64Zrm_Int : case X86 :: VCVTSS2SIZrm_Int : case X86 :: VCVTSS2SI64Zrm_Int : case X86 :: VCVTTSD2SIZrm : case X86 :: VCVTTSD2SIZrm_Int : case X86 :: VCVTTSD2SI64Zrm : case X86 :: VCVTTSD2SI64Zrm_Int : case X86 :: VCVTTSS2SIZrm : case X86 :: VCVTTSS2SIZrm_Int : case X86 :: VCVTTSS2SI64Zrm : case X86 :: VCVTTSS2SI64Zrm_Int : if ( ForcedVEXEncoding != VEXEncoding_EVEX ) return Match_Unsupported ; } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> static tree ix86_builtin_reciprocal ( tree fndecl ) { switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case IX86_BUILTIN_SQRTPS_NR : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR ) ; case IX86_BUILTIN_SQRTPS_NR256 : return ix86_get_builtin ( IX86_BUILTIN_RSQRTPS_NR256 ) ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> static const struct mips_cpu_info * mips_cpu_info_from_isa ( int isa ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_cpu_info_table ) ; i ++ ) if ( mips_cpu_info_table [ i ] . isa == isa ) return mips_cpu_info_table + i ; return NULL ; } </s>

Return the processor associated with the given ISA level , or null if the ISA is n't valid .


<s> const uint16_t * LEGRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { LEG :: R4 , LEG :: R5 , LEG :: R6 , LEG :: R7 , LEG :: R8 , LEG :: R9 , 0 } ; return CalleeSavedRegs ; } </s>


"ARM fix for Cortex-A57 AES Erratum 1742098"

getPassName - Return a nice clean name for a pass .


<s> static rtx_insn * add_parameter_dependencies ( rtx_insn * call , rtx_insn * head ) { rtx_insn * insn ; rtx_insn * last = call ; rtx_insn * first_arg = NULL ; bool is_spilled = false ; head = PREV_INSN ( head ) ; while ( true ) { last = PREV_INSN ( last ) ; if ( last == head ) return NULL ; if ( ! NONDEBUG_INSN_P ( last ) ) continue ; if ( insn_is_function_arg ( last , & is_spilled ) ) break ; return NULL ; } first_arg = last ; while ( true ) { insn = PREV_INSN ( last ) ; if ( ! INSN_P ( insn ) ) break ; if ( insn == head ) break ; if ( ! NONDEBUG_INSN_P ( insn ) ) { last = insn ; continue ; } if ( insn_is_function_arg ( insn , & is_spilled ) ) { if ( is_spilled ) add_dependence ( first_arg , insn , REG_DEP_OUTPUT ) ; first_arg = last = insn ; } else break ; } if ( ! is_spilled ) return NULL ; return first_arg ; } </s>

Add output dependencies for chain of function adjacent arguments if only there is a move to likely spilled HW register . Return first argument if at least one dependence was added or NULL otherwise .


<s> static rtx aarch64_replace_reg_mode ( rtx x , machine_mode mode ) { if ( GET_MODE ( x ) == mode ) return x ; x = shallow_copy_rtx ( x ) ; set_mode_and_regno ( x , mode , REGNO ( x ) ) ; return x ; } </s>

Return a copy of X with mode MODE , without changing its other attributes . Unlike gen_lowpart , this does n't care whether the mode change is valid .


<s> void PPCLinuxAsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( static_cast < const PPCTargetMachine & > ( TM ) . isELFv2ABI ( ) ) { PPCTargetStreamer * TS = static_cast < PPCTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitAbiVersion ( 2 ) ; } if ( static_cast < const PPCTargetMachine & > ( TM ) . isPPC64 ( ) || ! isPositionIndependent ( ) ) return AsmPrinter :: emitStartOfAsmFile ( M ) ; if ( M . getPICLevel ( ) == PICLevel :: SmallPIC ) return AsmPrinter :: emitStartOfAsmFile ( M ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ) ; MCSymbol * TOCSym = OutContext . getOrCreateSymbol ( Twine ( ".LTOC" ) ) ; MCSymbol * CurrentPos = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( CurrentPos ) ; const MCExpr * tocExpr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( CurrentPos , OutContext ) , MCConstantExpr :: create ( 0x8000 , OutContext ) , OutContext ) ; OutStreamer -> emitAssignment ( TOCSym , tocExpr ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s>
bool
AArch64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
Register
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
else
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool sparc_expand_conditional_move ( machine_mode mode , rtx * operands ) { enum rtx_code rc = GET_CODE ( operands [ 1 ] ) ; machine_mode cmp_mode ; rtx cc_reg , dst , cmp ; cmp = operands [ 1 ] ; if ( GET_MODE ( XEXP ( cmp , 0 ) ) == DImode && ! TARGET_ARCH64 ) return false ; if ( GET_MODE ( XEXP ( cmp , 0 ) ) == TFmode && ! TARGET_HARD_QUAD ) cmp = sparc_emit_float_lib_cmp ( XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) , rc ) ; cmp_mode = GET_MODE ( XEXP ( cmp , 0 ) ) ; rc = GET_CODE ( cmp ) ; dst = operands [ 0 ] ; if ( ! rtx_equal_p ( operands [ 2 ] , dst ) && ! rtx_equal_p ( operands [ 3 ] , dst ) ) { if ( reg_overlap_mentioned_p ( dst , cmp ) ) dst = gen_reg_rtx ( mode ) ; emit_move_insn ( dst , operands [ 3 ] ) ; } else if ( operands [ 2 ] == dst ) { operands [ 2 ] = operands [ 3 ] ; if ( GET_MODE_CLASS ( cmp_mode ) == MODE_FLOAT ) rc = reverse_condition_maybe_unordered ( rc ) ; else rc = reverse_condition ( rc ) ; } if ( XEXP ( cmp , 1 ) == const0_rtx && GET_CODE ( XEXP ( cmp , 0 ) ) == REG && cmp_mode == DImode && v9_regcmp_p ( rc ) ) cc_reg = XEXP ( cmp , 0 ) ; else cc_reg = gen_compare_reg_1 ( rc , XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) ) ; cmp = gen_rtx_fmt_ee ( rc , GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dst , gen_rtx_IF_THEN_ELSE ( mode , cmp , operands [ 2 ] , dst ) ) ) ; if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; return true ; } </s>

Emit code to conditionally move either OPERANDS [ 2 ] or OPERANDS [ 3 ] into OPERANDS [ 0 ] in MODE . OPERANDS [ 1 ] is the operator of the condition .


<s>
unsigned
CSKYMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( ( TSFlags & X86II :: NOTRACK ) || ( Flags & X86 :: IP_HAS_NOTRACK ) ) OS << "\tnotrack\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && ( STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) ) { MCInst Data32MI ( * MI ) ; Data32MI . setOpcode ( X86 :: DATA32_PREFIX ) ; printInstruction ( & Data32MI , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
const
char
*
getPassName
(
)
const
{
return
"AdvSIMD scalar operation optimization"
;
}
</s>


<s> static void find_regmode_weight ( int b , enum machine_mode mode ) { rtx insn , next_tail , head , tail ; get_block_head_tail ( b , & head , & tail ) ; next_tail = NEXT_INSN ( tail ) ; for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) ) continue ; if ( mode == SFmode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + 2 * find_insn_regmode_weight ( insn , DFmode ) ; else if ( mode == SImode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + 2 * find_insn_regmode_weight ( insn , DImode ) ; } } </s>

Calculate regmode weights for all insns of a basic block .


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned VTBits = Op . getScalarValueSizeInBits ( ) ; unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case X86ISD :: SETCC_CARRY : return VTBits ; case X86ISD :: VSEXT : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; Tmp += VTBits - Src . getScalarValueSizeInBits ( ) ; return Tmp ; } case X86ISD :: VSHLI : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ; if ( ShiftVal . uge ( VTBits ) ) return VTBits ; if ( ShiftVal . uge ( Tmp ) ) return 1 ; return Tmp - ShiftVal . getZExtValue ( ) ; } case X86ISD :: VSRAI : { SDValue Src = Op . getOperand ( 0 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getAPIntValue ( ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case X86ISD :: PCMPGT : case X86ISD :: PCMPEQ : case X86ISD :: CMPP : case X86ISD :: VPCOM : case X86ISD :: VPCOMU : return VTBits ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> bool Thumb1InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: CALL_TLS : return "PPCISD::CALL_TLS" ; case PPCISD :: CALL_NOP_TLS : return "PPCISD::CALL_NOP_TLS" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: PPC32_GOT : return "PPCISD::PPC32_GOT" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static machine_mode zero_call_used_regno_mode ( const unsigned int regno ) { if ( GENERAL_REGNO_P ( regno ) ) return SImode ; else if ( SSE_REGNO_P ( regno ) ) return V4SFmode ; else if ( MASK_REGNO_P ( regno ) ) return HImode ; else if ( MMX_REGNO_P ( regno ) ) return V4HImode ; else gcc_unreachable ( ) ; } </s>

Return the machine_mode that is used to zero register REGNO .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Register
:
OS
<<
"Reg<"
<<
Reg
.
Num
<<
">"
;
break
;
case
k_Immediate
:
OS
<<
"Imm<"
<<
Imm
.
Val
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
case
k_Memory
:
OS
<<
"Mem<Reg<"
<<
Mem
.
BaseNum
<<
">, "
<<
Mem
.
Off
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy ) { if ( isa < VectorType > ( DataTy ) ) { unsigned NumElts = DataTy -> getVectorNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth == 32 || DataWidth == 64 ) && ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ; } </s>

Return true if the target supports masked gather .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( Subtarget . hasMSA ( ) && type -> isVectorTy ( ) && cast < VectorType > ( type ) -> getBitWidth ( ) == 128 ) weight = CW_Register ; else if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static bool mips_call_may_need_jalx_p ( tree decl ) { if ( mips_get_compress_mode ( decl ) != TARGET_COMPRESSION ) return true ; if ( ! DECL_EXTERNAL ( decl ) && targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_INTERLINK_COMPRESSED ) { if ( ! TARGET_COMPRESSION && mips_get_compress_off_flags ( DECL_ATTRIBUTES ( decl ) ) == 0 ) return true ; if ( TARGET_COMPRESSION && mips_get_compress_on_flags ( DECL_ATTRIBUTES ( decl ) ) == 0 ) return true ; } return false ; } </s>

Return true if a call to DECL may need to use JALX .


<s> i960_print_operand_addr ( FILE , ADDR ) { \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x8C203000 ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x00000000 ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x8CE03000 ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x00000000 ) ) ; \ assemble_aligned_integer ( UNITS_PER_WORD , GEN_INT ( 0x84212000 ) ) ; \ } </s>

Print a memory address as an operand to reference that memory location . This is exactly the same as legitimate_address_p , except that it the prints addresses instead of recognizing them .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
VT
=
VA
.
getValVT
(
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VT
,
InFlag
)
.
getValue
(
1
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool ARMBaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == ARM :: VORRq && MI . getOperand ( 1 ) . getReg ( ) != MI . getOperand ( 2 ) . getReg ( ) ) ) return false ; Dest = MI . getOperand ( 0 ) ; Src = MI . getOperand ( 1 ) ; return true ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> rtx sh_function_arg ( CUMULATIVE_ARGS * ca , enum machine_mode mode , tree type , int named ) { if ( ! TARGET_SH5 && mode == VOIDmode ) return GEN_INT ( ca -> renesas_abi ? 1 : 0 ) ; if ( ! TARGET_SH5 && PASS_IN_REG_P ( * ca , mode , type ) && ( named || ! ( TARGET_HITACHI || ca -> renesas_abi ) ) ) { int regno ; if ( mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ( ! FUNCTION_ARG_SCmode_WART || ( ROUND_REG ( * ca , mode ) & 1 ) ) ) { rtx r1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ROUND_REG ( * ca , mode ) ^ 1 ) ) , const0_rtx ) ; rtx r2 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ( ROUND_REG ( * ca , mode ) + 1 ) ^ 1 ) ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( SCmode , gen_rtvec ( 2 , r1 , r2 ) ) ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && ca -> free_single_fp_reg && mode == SFmode ) return gen_rtx_REG ( mode , ca -> free_single_fp_reg ) ; regno = ( BASE_ARG_REG ( mode ) + ROUND_REG ( * ca , mode ) ) ^ ( mode == SFmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN != 0 && ! TARGET_HITACHI && ! ca -> renesas_abi ) ; return gen_rtx_REG ( mode , regno ) ; } if ( TARGET_SH5 ) { if ( mode == VOIDmode && TARGET_SHCOMPACT ) return GEN_INT ( ca -> call_cookie ) ; if ( mode == SFmode && ca -> free_single_fp_reg ) return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , ca -> free_single_fp_reg ) ; if ( ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT ) && ( named || ! ca -> prototype_p ) && ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { if ( ! ca -> prototype_p && TARGET_SHMEDIA ) return SH5_PROTOTYPELESS_FLOAT_ARG ( * ca , mode ) ; return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , FIRST_FP_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; } if ( ca -> arg_count [ ( int ) SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! TARGET_SHCOMPACT || ( ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * ca , mode , type , named ) ) ) ) { return gen_rtx_REG ( mode , ( FIRST_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_INT ] ) ) ; } return 0 ; } return 0 ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On SH the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . isTargetDarwin ( ) && STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_iOS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void rs6000_emit_swdiv ( rtx dst , rtx n , rtx d , bool note_p ) { machine_mode mode = GET_MODE ( dst ) ; rtx one , x0 , e0 , x1 , xprev , eprev , xnext , enext , u , v ; int i ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; one = rs6000_load_constant_and_splat ( mode , dconst1 ) ; x0 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , d ) , UNSPEC_FRES ) ) ) ; if ( passes > 1 ) { e0 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( e0 , d , x0 , one ) ; x1 = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( x1 , e0 , x0 , x0 ) ; for ( i = 0 , xprev = x1 , eprev = e0 ; i < passes - 2 ; ++ i , xprev = xnext , eprev = enext ) { enext = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( enext , eprev , eprev ) ) ; xnext = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( xnext , enext , xprev , xprev ) ; } } else xprev = x0 ; u = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , n , xprev ) ) ; v = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( v , d , u , n ) ; rs6000_emit_madd ( dst , v , xprev , u ) ; if ( note_p ) add_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_DIV ( mode , n , d ) ) ; } </s>

Newton-Raphson approximation of floating point divide DST = N/D . If NOTE_P , add a reg_note saying that this was a division . Support both scalar and vector divide . Assumes no trapping math and finite arguments .


<s>
const
char
*
nds32_output_casesi
(
rtx
*
operands
)
{
if
(
flag_pic
)
{
output_asm_insn
(
"sethi\t$ta, hi20(%l1@GOTOFF)"
,
operands
)
;
output_asm_insn
(
"ori\t$ta, $ta, lo12(%l1@GOTOFF)"
,
operands
)
;
output_asm_insn
(
"add\t$ta, $ta, $gp"
,
operands
)
;
}
else
output_asm_insn
(
"la\t$ta, %l1"
,
operands
)
;
output_asm_insn
(
"lw\t%2, [$ta + %0 << 2]"
,
operands
)
;
if
(
TARGET_16_BIT
)
return
"jr5\t%2"
;
else
return
"jr\t%2"
;
}
</s>

Function to generate normal jump table .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool PPCInstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : case PPC :: QVFADD : case PPC :: QVFADDS : case PPC :: QVFADDSs : case PPC :: QVFMUL : case PPC :: QVFMULS : case PPC :: QVFMULSs : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; case PPC :: MULHD : case PPC :: MULLD : case PPC :: MULHW : case PPC :: MULLW : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::QVFADD PPC::QVFADDS PPC::QVFADDSs PPC::QVFMUL PPC::QVFMULS PPC::QVFMULSs PPC::MULHD PPC::MULLD PPC::MULHW PPC::MULLW


<s> bool SystemZSubtarget :: enableSubRegLiveness ( ) const { return UseSubRegLiveness ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> void scalar_chain :: convert_insn ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; rtx subreg ; if ( MEM_P ( dst ) && ! REG_P ( src ) ) { rtx tmp = gen_reg_rtx ( DImode ) ; emit_conversion_insns ( gen_move_insn ( dst , tmp ) , insn ) ; dst = gen_rtx_SUBREG ( V2DImode , tmp , 0 ) ; } switch ( GET_CODE ( src ) ) { case PLUS : case MINUS : case IOR : case XOR : case AND : convert_op ( & XEXP ( src , 0 ) , insn ) ; convert_op ( & XEXP ( src , 1 ) , insn ) ; PUT_MODE ( src , V2DImode ) ; break ; case MEM : if ( ! REG_P ( dst ) ) convert_op ( & src , insn ) ; break ; case REG : if ( ! MEM_P ( dst ) ) convert_op ( & src , insn ) ; break ; case SUBREG : gcc_assert ( GET_MODE ( src ) == V2DImode ) ; break ; case COMPARE : src = SUBREG_REG ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ; gcc_assert ( ( REG_P ( src ) && GET_MODE ( src ) == DImode ) || ( SUBREG_P ( src ) && GET_MODE ( src ) == V2DImode ) ) ; if ( REG_P ( src ) ) subreg = gen_rtx_SUBREG ( V2DImode , src , 0 ) ; else subreg = copy_rtx_if_shared ( src ) ; emit_insn_before ( gen_vec_interleave_lowv2di ( copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) ) , insn ) ; dst = gen_rtx_REG ( CCmode , FLAGS_REG ) ; src = gen_rtx_UNSPEC ( CCmode , gen_rtvec ( 2 , copy_rtx_if_shared ( src ) , copy_rtx_if_shared ( src ) ) , UNSPEC_PTEST ) ; break ; default : gcc_unreachable ( ) ; } SET_SRC ( def_set ) = src ; SET_DEST ( def_set ) = dst ; PATTERN ( insn ) = def_set ; INSN_CODE ( insn ) = - 1 ; recog_memoized ( insn ) ; df_insn_rescan ( insn ) ; } </s>


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( funcInfo . MF -> getTarget ( ) ) ; bool UseFastISel = TM . Options . EnableFastISel && Subtarget . hasMips32 ( ) && ! Subtarget . hasMips32r6 ( ) && ! Subtarget . inMips16Mode ( ) && ! Subtarget . inMicroMipsMode ( ) ; if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) || Subtarget . useXGOT ( ) ) UseFastISel = false ; return UseFastISel ? Mips :: createFastISel ( funcInfo , libInfo ) : nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

Mips Mips Mips Mips Mips Mips Mips Mips Mips::createFastISel


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static inline void aarch64_adjust_sve_callee_save_base ( machine_mode mode , rtx & base_rtx , rtx & anchor_reg , poly_int64 & offset , rtx & ptrue ) { if ( maybe_ge ( offset , 8 * GET_MODE_SIZE ( mode ) ) ) { poly_int64 anchor_offset = 16 * GET_MODE_SIZE ( mode ) ; if ( ! anchor_reg ) { anchor_reg = gen_rtx_REG ( Pmode , STACK_CLASH_SVE_CFA_REGNUM ) ; emit_insn ( gen_add3_insn ( anchor_reg , base_rtx , gen_int_mode ( anchor_offset , Pmode ) ) ) ; } base_rtx = anchor_reg ; offset -= anchor_offset ; } if ( ! ptrue ) { int pred_reg = cfun -> machine -> frame . spare_pred_reg ; emit_move_insn ( gen_rtx_REG ( VNx16BImode , pred_reg ) , CONSTM1_RTX ( VNx16BImode ) ) ; ptrue = gen_rtx_REG ( VNx2BImode , pred_reg ) ; } } </s>

The caller is going to use ST1D or LD1D to save or restore an SVE register in mode MODE at BASE_RTX + OFFSET , where OFFSET is in the range [ 1 , 16 ] * GET_MODE_SIZE ( MODE ) . Prepare for this by : ( 1 ) updating BASE_RTX + OFFSET so that it is a legitimate ST1D or LD1D address ( 2 ) setting PRED to a valid predicate register for the ST1D or LD1D , if the variable is n't already nonnull ( 1 ) is needed when OFFSET is in the range [ 8 , 16 ] * GET_MODE_SIZE ( MODE ) . Handle this case using a temporary base register that is suitable for all offsets in that range . Use ANCHOR_REG as this base register if it is nonnull , otherwise create a new register and store it in ANCHOR_REG .


<s> static void arm_asm_emit_except_personality ( rtx personality ) { fputs ( "\t.personality\t" , asm_out_file ) ; output_addr_const ( asm_out_file , personality ) ; fputc ( '\n' , asm_out_file ) ; } </s>


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other , MVT :: Glue ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , DL , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( 1 ) ; SDValue Glue = End . getValue ( 2 ) ; SDValue Ops [ ] = { End , DAG . getConstant ( 0 , DL , PtrVT ) , DAG . getConstant ( SystemZ :: CCMASK_SRST , DL , MVT :: i32 ) , DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , DL , MVT :: i32 ) , Glue } ; VTs = DAG . getVTList ( PtrVT , MVT :: Glue ) ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , VTs , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: tMOVr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ; } </s>


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown Custom Instruction!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
case
SP
::
EH_SJLJ_SETJMP32ri
:
case
SP
::
EH_SJLJ_SETJMP32rr
:
return
emitEHSjLjSetJmp
(
MI
,
BB
)
;
case
SP
::
EH_SJLJ_LONGJMP32rr
:
case
SP
::
EH_SJLJ_LONGJMP32ri
:
return
emitEHSjLjLongJmp
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static std :: unique_ptr < MipsOperand > CreateMem ( std :: unique_ptr < MipsOperand > Base , const MCExpr * Off , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { auto Op = llvm :: make_unique < MipsOperand > ( k_Memory , Parser ) ; Op -> Mem . Base = Base . release ( ) ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s>
char
*
aarch64_output_sve_addvl_addpl
(
rtx
dest
,
rtx
base
,
rtx
offset
)
{
static
char
buffer
[
sizeof
(
"addpl\t%x0, %x1, #-"
)
+
3
*
sizeof
(
int
)
]
;
poly_int64
offset_value
=
rtx_to_poly_int64
(
offset
)
;
gcc_assert
(
aarch64_sve_addvl_addpl_immediate_p
(
offset_value
)
)
;
if
(
rtx_equal_p
(
dest
,
base
)
&&
GP_REGNUM_P
(
REGNO
(
dest
)
)
)
{
if
(
aarch64_sve_cnt_immediate_p
(
offset_value
)
)
return
aarch64_output_sve_cnt_immediate
(
"inc"
,
"%x0"
,
offset_value
.
coeffs
[
1
]
,
0
)
;
if
(
aarch64_sve_cnt_immediate_p
(
offset_value
)
)
return
aarch64_output_sve_cnt_immediate
(
"dec"
,
"%x0"
,
offset_value
.
coeffs
[
1
]
,
0
)
;
}
int
factor
=
offset_value
.
coeffs
[
1
]
;
if
(
(
factor
&
15
)
==
0
)
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"addvl\t%%x0, %%x1, #%d"
,
factor
/
16
)
;
else
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"addpl\t%%x0, %%x1, #%d"
,
factor
/
2
)
;
return
buffer
;
}
</s>

Return the asm string for adding ADDVL or ADDPL immediate X to operand 1 and storing the result in operand 0 .


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , 1 ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , MVT :: i32 ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , 0 ) ; OutOps . push_back ( NewOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void LEGFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == LEG :: ADJCALLSTACKUP || I -> getOpcode ( ) == LEG :: ADJCALLSTACKDOWN ) { MBB . erase ( I ) ; } return ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

LEG LEG LEG::ADJCALLSTACKUP LEG::ADJCALLSTACKDOWN


<s> bool runOnFunction ( Function & F ) override { this -> F = & F ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool Changed = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = po_begin ( * I ) , LE = po_end ( * I ) ; L != LE ; ++ L ) Changed |= runOnLoop ( * L ) ; VisitedBlocks . clear ( ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool ARM64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s>
static
void
ia64_asm_unwind_emit
(
FILE
*
out_file
,
rtx_insn
*
insn
)
{
bool
unwind
=
ia64_except_unwind_info
(
&
global_options
)
==
UI_TARGET
;
bool
frame
=
dwarf2out_do_frame
(
)
;
rtx
note
,
pat
;
bool
handled_one
;
if
(
!
unwind
&&
!
frame
)
return
;
if
(
NOTE_INSN_BASIC_BLOCK_P
(
insn
)
)
{
last_block
=
NOTE_BASIC_BLOCK
(
insn
)
->
next_bb
==
EXIT_BLOCK_PTR_FOR_FN
(
cfun
)
;
if
(
need_copy_state
)
{
if
(
unwind
)
{
fprintf
(
out_file
,
"\t.body\n"
)
;
fprintf
(
out_file
,
"\t.copy_state %d\n"
,
cfun
->
machine
->
state_num
)
;
}
need_copy_state
=
false
;
}
}
if
(
NOTE_P
(
insn
)
||
!
RTX_FRAME_RELATED_P
(
insn
)
)
return
;
if
(
INSN_CODE
(
insn
)
==
CODE_FOR_alloc
)
{
rtx
dest
=
SET_DEST
(
XVECEXP
(
PATTERN
(
insn
)
,
0
,
0
)
)
;
int
dest_regno
=
REGNO
(
dest
)
;
if
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_pfs
]
)
{
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.pfs, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
}
else
{
if
(
current_frame_info
.
total_size
==
0
&&
!
frame_pointer_needed
)
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.prologue\n"
)
;
}
return
;
}
handled_one
=
false
;
for
(
note
=
REG_NOTES
(
insn
)
;
note
;
note
=
XEXP
(
note
,
1
)
)
switch
(
REG_NOTE_KIND
(
note
)
)
{
case
REG_CFA_ADJUST_CFA
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_adjust_cfa
(
out_file
,
pat
,
insn
,
unwind
,
frame
)
;
handled_one
=
true
;
break
;
case
REG_CFA_OFFSET
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_offset
(
out_file
,
pat
,
unwind
)
;
handled_one
=
true
;
break
;
case
REG_CFA_REGISTER
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_register
(
out_file
,
pat
,
unwind
)
;
handled_one
=
true
;
break
;
case
REG_FRAME_RELATED_EXPR
:
case
REG_CFA_DEF_CFA
:
case
REG_CFA_EXPRESSION
:
case
REG_CFA_RESTORE
:
case
REG_CFA_SET_VDRAP
:
gcc_unreachable
(
)
;
default
:
break
;
}
gcc_assert
(
handled_one
)
;
}
</s>

This function looks at a single insn and emits any directives required to unwind this insn .


<s>
const
char
*
vfp_output_fstmx
(
rtx
*
operands
)
{
char
pattern
[
100
]
;
int
p
;
int
base
;
int
i
;
strcpy
(
pattern
,
"fstmfdx\t%m0!, {%P1"
)
;
p
=
strlen
(
pattern
)
;
gcc_assert
(
GET_CODE
(
operands
[
1
]
)
==
REG
)
;
base
=
(
REGNO
(
operands
[
1
]
)
FIRST_VFP_REGNUM
)
/
2
;
for
(
i
=
1
;
i
<
XVECLEN
(
operands
[
2
]
,
0
)
;
i
++
)
{
p
+=
sprintf
(
&
pattern
[
p
]
,
", d%d"
,
base
+
i
)
;
}
strcpy
(
&
pattern
[
p
]
,
"}"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output the assembly for a store multiple .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> static bool mips_hard_regno_mode_ok_uncached ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 2 == 0 ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 4 == 0 ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode && ! MSA_SUPPORTED_MODE_P ( mode ) ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && MSA_SUPPORTED_MODE_P ( mode ) ) return true ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == 0 || ( MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= 4 && ( regno & 1 ) != 0 ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & 1 ) != 0 ) ; if ( TARGET_LOONGSON_VECTORS && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * 2 ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * 2 && ( ( regno - DSP_ACC_REG_FIRST ) & 1 ) == 0 ) return true ; } } if ( ALL_COP_REG_P ( regno ) ) return mclass == MODE_INT && size <= UNITS_PER_WORD ; if ( regno == GOT_VERSION_REGNUM ) return mode == SImode ; return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in mips_hard_regno_mode_ok .


<s> static int arm_sched_reorder ( FILE * file , int verbose , rtx_insn * * ready , int * n_readyp , int clock ) { switch ( arm_tune ) { case cortexa7 : cortexa7_sched_reorder ( file , verbose , ready , n_readyp , clock ) ; break ; default : break ; } return arm_issue_rate ( ) ; } </s>


<s> unsigned TeeRISCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { assert ( 0 ) ; if ( MI -> getOpcode ( ) == TeeRISC :: ST ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void X86AsmInstrumentation :: EmitInstruction ( MCStreamer & Out , const MCInst & Inst ) { Out . EmitInstruction ( Inst , * STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Opcode has no flag setting equivalent!"

Return the opcode that set flags when possible .


<s> bool isReg ( ) const { if ( isGPRAsmReg ( ) && RegIdx . Index == 0 ) return true ; return Kind == k_PhysRegister ; } </s>


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool can_be_rotated_to_negative_15bits ( HOST_WIDE_INT c ) { int rot = 0 ; bool res = can_be_rotated_to_lowbits ( ~ c , 15 , & rot ) ; return res && rot > 0 ; } </s>

Check if C ( as 64bit integer ) can be rotated to a negative 15bits constant which contains 49bits leading ones and 15bits of any value .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return getParser ( ) . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static X86Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , SMLoc OffsetOfLoc = SMLoc ( ) ) { X86Operand * Res = new X86Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> OffsetOfLoc = OffsetOfLoc ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


EXP is a pointer argument to a Neon load or store intrinsic . Derive and return an expression for the accessed memory . The intrinsic function operates on a block of registers that has mode REG_MODE . This block contains vectors of type TYPE_MODE . The function references the memory at EXP of type TYPE and in mode MEM_MODE ; this mode may be BLKmode if no more suitable mode is available .


<s> bool Thumb2ITBlock :: runOnMachineFunction ( MachineFunction & Fn ) { const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; if ( ! STI . isThumb2 ( ) ) return false ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= InsertITInstructions ( MBB ) ; if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static machine_mode aarch64_preferred_simd_mode ( machine_mode mode ) { return aarch64_simd_container_mode ( mode , 128 ) ; } </s>

Return 128-bit container as the preferred SIMD mode for MODE .


<s> static bool arm_asm_elf_flags_numeric ( unsigned int flags , unsigned int * num ) { if ( flags & SECTION_ARM_PURECODE ) { * num = 0x20000000 ; if ( ! ( flags & SECTION_DEBUG ) ) * num |= 0x2 ; if ( flags & SECTION_EXCLUDE ) * num |= 0x80000000 ; if ( flags & SECTION_WRITE ) * num |= 0x1 ; if ( flags & SECTION_CODE ) * num |= 0x4 ; if ( flags & SECTION_MERGE ) * num |= 0x10 ; if ( flags & SECTION_STRINGS ) * num |= 0x20 ; if ( flags & SECTION_TLS ) * num |= 0x400 ; if ( HAVE_COMDAT_GROUP && ( flags & SECTION_LINKONCE ) ) * num |= 0x200 ; return true ; } return false ; } </s>

Implement the TARGET_ASM_ELF_FLAGS_NUMERIC hook . For pure-code sections there is no letter code for this attribute , so output all the section flags numerically when this is needed .


<s>
unsigned
MipsInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
reverse_iterator
I
=
MBB
.
rbegin
(
)
,
REnd
=
MBB
.
rend
(
)
;
unsigned
removed
=
0
;
while
(
I
!=
REnd
&&
removed
<
2
)
{
if
(
I
->
isDebugInstr
(
)
)
{
++
I
;
continue
;
}
if
(
!
getAnalyzableBrOpc
(
I
->
getOpcode
(
)
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
rbegin
(
)
;
++
removed
;
}
return
removed
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> void finish ( ) override { for ( auto * Sym : UpdateOther ) if ( Sym -> isVariable ( ) ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ; UpdateOther . clear ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> virtual void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , Register DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , Register PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , Align ( 4 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . add ( predOps ( Pred , PredReg ) ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> int shl_and_scr_length ( rtx insn ) { rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; int len = shift_insns [ INTVAL ( XEXP ( set_src , 1 ) ) ] ; rtx op = XEXP ( set_src , 0 ) ; len += shift_insns [ INTVAL ( XEXP ( op , 1 ) ) ] + 1 ; op = XEXP ( XEXP ( op , 0 ) , 0 ) ; return len + shift_insns [ INTVAL ( XEXP ( op , 1 ) ) ] ; } </s>

This is used in length attribute of the and_shl_scratch instruction .


<s> static unsigned int insn_is_load_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { if ( GET_CODE ( SET_SRC ( body ) ) == MEM ) return 1 ; if ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) == MEM ) return 1 ; return 0 ; } if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && GET_CODE ( SET_SRC ( set ) ) == MEM ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a load insn , including permuting loads that represent an lvxd2x instruction ; else return 0 .


<s> bool DLXInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s>
void
ARMInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
ARMFunctionInfo
*
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
AFI
->
isThumbFunction
(
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
else
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
LDR
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FLDD
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
{
assert
(
RC
==
ARM
::
SPRRegisterClass
&&
"Unknown regclass!"
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FLDS
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM
ARM::GPRRegisterClass
ARM
ARM
ARM::tRestore
0
ARM::LDR
0
0
ARM::DPRRegisterClass
ARM::FLDD
0
ARM::SPRRegisterClass
"Unknown regclass!"
ARM::FLDS
0


<s>
unsigned
getMaxNumElements
(
ElementCount
VF
)
const
{
if
(
!
VF
.
isScalable
(
)
)
return
VF
.
getFixedValue
(
)
;
Optional
<
unsigned
>
MaxNumVScale
=
getMaxVScale
(
)
;
assert
(
MaxNumVScale
&&
"Expected valid max vscale value"
)
;
return
*
MaxNumVScale
*
VF
.
getKnownMinValue
(
)
;
}
</s>

Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation for a vector with ElementCount VF .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; if ( VT . isSimple ( ) ) { MVT VVT = VT . getSimpleVT ( ) ; const unsigned NumElts = VVT . getVectorNumElements ( ) ; const MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget . hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget . hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( VVT . is256BitVector ( ) || VVT . is128BitVector ( ) ) { if ( Subtarget . hasVLX ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; case 32 : return MVT :: v32i1 ; } } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool SICDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const SICSubtarget & > ( MF . getSubtarget ( ) ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; return Ret ; } </s>


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int Cost = 0 ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: SDIV : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case ISD :: UDIV : Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return ( Cost + 1 ) * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; X86MachineFunctionInfo * MFI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned SystemZTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { if ( Op . getResNo ( ) != 0 ) return 1 ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == ISD :: INTRINSIC_WO_CHAIN ) { unsigned Id = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( Id ) { case Intrinsic :: s390_vpksh : case Intrinsic :: s390_vpksf : case Intrinsic :: s390_vpksg : case Intrinsic :: s390_vpkshs : case Intrinsic :: s390_vpksfs : case Intrinsic :: s390_vpksgs : case Intrinsic :: s390_vpklsh : case Intrinsic :: s390_vpklsf : case Intrinsic :: s390_vpklsg : case Intrinsic :: s390_vpklshs : case Intrinsic :: s390_vpklsfs : case Intrinsic :: s390_vpklsgs : case Intrinsic :: s390_vpdi : case Intrinsic :: s390_vsldb : case Intrinsic :: s390_vperm : return computeNumSignBitsBinOp ( Op , DemandedElts , DAG , Depth , 1 ) ; case Intrinsic :: s390_vuphb : case Intrinsic :: s390_vuphh : case Intrinsic :: s390_vuphf : case Intrinsic :: s390_vuplb : case Intrinsic :: s390_vuplhw : case Intrinsic :: s390_vuplf : { SDValue PackedOp = Op . getOperand ( 1 ) ; APInt SrcDemE = getDemandedSrcElements ( Op , DemandedElts , 1 ) ; unsigned Tmp = DAG . ComputeNumSignBits ( PackedOp , SrcDemE , Depth + 1 ) ; EVT VT = Op . getValueType ( ) ; unsigned VTBits = VT . getScalarSizeInBits ( ) ; Tmp += VTBits - PackedOp . getScalarValueSizeInBits ( ) ; return Tmp ; } default : break ; } } else { switch ( Opcode ) { case SystemZISD :: SELECT_CCMASK : return computeNumSignBitsBinOp ( Op , DemandedElts , DAG , Depth , 0 ) ; default : break ; } } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> int mt_function_arg_boundary ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED ) { return BITS_PER_WORD ; } </s>


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && I -> getNumOperands ( ) > 0 && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( 0 ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isEHLabel ( ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void PPCPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( createPPCVSXSwapRemovalPass ( ) ) ; if ( ! DisableMIPeephole ) { addPass ( createPPCMIPeepholePass ( ) ) ; addPass ( & DeadMachineInstructionElimID ) ; } } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> static bool callee_saved_regno_p ( int regno ) { if ( ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ) return true ; switch ( regno ) { case HARD_FRAME_POINTER_REGNUM : return frame_pointer_needed ; case LR_REGNUM : return ( frame_pointer_needed || ! crtl -> is_leaf || crtl -> uses_pic_offset_table || df_regs_ever_live_p ( regno ) ) ; case HW_TO_GCC_REGNO ( 25 ) : case HW_TO_GCC_REGNO ( 27 ) : case HW_TO_GCC_REGNO ( 29 ) : case HW_TO_GCC_REGNO ( 31 ) : return crtl -> calls_eh_return ; default : return false ; } } </s>

Returns true if REGNO must be saved for the current function .


<s> bool XNCMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> tree memory_scalar_type ( const function_instance & fi ) const OVERRIDE { return fi . scalar_type ( 0 ) ; } </s>

If the function addresses memory , return the type of a single scalar memory element .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tRestore
0


<s> enum direction function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! AGGREGATE_PADDING_FIXED ) { if ( BYTES_BIG_ENDIAN ) { HOST_WIDE_INT size = 0 ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == 1 || size == 2 || size == 4 ) return downward ; } return upward ; } if ( AGGREGATES_PAD_UPWARD_ALWAYS ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return upward ; } return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

Handle the FUNCTION_ARG_PADDING macro . For the 64 bit ABI structs are always stored left shifted in their argument slot .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> machreg_t inet_lnaof ( machreg_t in ) { return _inet_lnaof ( in << SHIFT_BITS ) ; } </s>

< arpa/inet.h > has unsigned long inet_lnaof ( struct in_addr ) ; ( IRIX 6.2 ) in_addr_t inet_lnaof ( struct in_addr ) ; ( IRIX 6.5 ) in_addr_t is a 32-bit int .


<s> MCObjectWriter * MipsAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createMipsELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static void moxie_option_override ( void ) { init_machine_status = moxie_init_machine_status ; target_flags |= MASK_HAS_MULX ; } </s>


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) const { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


<s> static void build_sv_index ( function_builder & b , const char * signature , const function_group_info & group ) { build_32_64 ( b , signature , group , MODE_s32index , MODE_s64index ) ; build_32_64 ( b , signature , group , MODE_u32index , MODE_u64index ) ; } </s>

For every type and predicate combination in GROUP , add one function that takes a scalar ( pointer ) base and a signed vector array index , and another that instead takes an unsigned vector array index . The vector array index has the same element size as the first function type suffix . SIGNATURE is as for build_all .


<s> bool offset_ok_for_ldrd_strd ( HOST_WIDE_INT offset ) { HOST_WIDE_INT max_offset ; if ( TARGET_THUMB2 && ( ( offset & 3 ) != 0 ) ) return false ; if ( TARGET_THUMB2 ) max_offset = 1020 ; else if ( TARGET_ARM ) max_offset = 255 ; else return false ; return ( ( offset <= max_offset ) && ( offset >= - max_offset ) ) ; } </s>

Returns true iff OFFSET is valid for use in an LDRD/STRD instruction , assuming that the address in the base register is word aligned .


<s> aarch64_print_operand_address ( STREAM , X ) { \ rtx fun , lr ; \ lr = get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; \ fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_NAME ) ; \ emit_library_call ( fun , LCT_NORMAL , VOIDmode , 1 , lr , Pmode ) ; \ } </s>

Print address ' x ' of a memory access with mode 'mode ' .


<s> static unsigned loongarch_pass_aggregate_num_fpr ( const_tree type , loongarch_aggregate_field fields [ 2 ] ) { int n = loongarch_flatten_aggregate_argument ( type , fields ) ; for ( int i = 0 ; i < n ; i ++ ) if ( ! SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ) return 0 ; return n > 0 ? n : 0 ; } </s>

See whether TYPE is a record whose fields should be returned in one or two floating-point registers . If so , populate FIELDS accordingly .


<s> unsigned X86InstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameStoreOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; const TargetRegisterClass * RC = & X86 :: VR256RegClass ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( MRI . isPhysRegUsed ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , 0 ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , 0 ) ; while ( 1 ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange ; } </s>


<s> void mips_output_load_label ( rtx target ) { mips_push_asm_switch ( & mips_noat ) ; if ( TARGET_EXPLICIT_RELOCS ) { mips_process_load_label ( target ) ; mips_multi_write ( ) ; } else { if ( Pmode == DImode ) output_asm_insn ( "dla\t%@,%0" , & target ) ; else output_asm_insn ( "la\t%@,%0" , & target ) ; } } </s>

Return an asm sequence to start a noat block and load the address of a label into $ 1 .


<s>
static
const
char
*
pru_output_gtge_signed_cbranch
(
rtx
*
operands
,
bool
is_near
)
{
static
char
buf
[
1024
]
;
enum
rtx_code
code
=
GET_CODE
(
operands
[
0
]
)
;
rtx
op1
;
rtx
op2
;
const
char
*
cmp_opstr
;
int
bufi
=
0
;
op1
=
operands
[
1
]
;
op2
=
operands
[
2
]
;
gcc_assert
(
GET_CODE
(
op1
)
==
REG
&&
GET_CODE
(
op2
)
==
REG
)
;
if
(
code
==
GT
)
cmp_opstr
=
"qbgt"
;
else
if
(
code
==
GE
)
cmp_opstr
=
"qbge"
;
else
gcc_unreachable
(
)
;
if
(
is_near
)
bufi
=
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+12, %%1, %d\n\t"
"qbbs\t%%l3, %%2, %d\n\t"
"%s\t%%l3, %%2, %%1\n\t"
"qbbc\t.+8, %%2, %d\n\t"
"%s\t%%l3, %%2, %%1"
,
sign_bit_position
(
op1
)
,
sign_bit_position
(
op2
)
,
cmp_opstr
,
sign_bit_position
(
op2
)
,
cmp_opstr
)
;
else
bufi
=
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+12, %%1, %d\n\t"
"qbbs\t.+20, %%2, %d\n\t"
"%s\t.+16, %%2, %%1\n\t"
"qbbc\t.+16, %%2, %d\n\t"
"%s\t.+8, %%2, %%1\n\t"
"jmp\t.+8\n\t"
"jmp\t%%%%label(%%l3)"
,
sign_bit_position
(
op1
)
,
sign_bit_position
(
op2
)
,
cmp_opstr
,
sign_bit_position
(
op2
)
,
cmp_opstr
)
;
gcc_assert
(
bufi
>
0
)
;
gcc_assert
(
(
unsigned
int
)
bufi
<
sizeof
(
buf
)
)
;
return
buf
;
}
</s>

Output asm code for a signed-compare GT/GE conditional branch .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> gimple * fold ( gimple_folder & f ) const override { poly_uint64 nelts = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( f . lhs ) ) ; poly_uint64 base = m_base * exact_div ( nelts , 2 ) ; vec_perm_builder builder ( nelts , 2 , 3 ) ; for ( unsigned int i = 0 ; i < 3 ; ++ i ) { builder . quick_push ( base + i ) ; builder . quick_push ( base + i + nelts ) ; } return fold_permute ( f , builder ) ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> rtx mmix_get_hard_reg_initial_val ( machine_mode mode , int regno ) { return get_hard_reg_initial_val ( mode , regno ) ; } </s>

Wrapper for get_hard_reg_initial_val since integrate.h is n't included from insn-emit.cc .


<s>
InstructionCost
AArch64TTIImpl
::
getMinMaxReductionCost
(
VectorType
*
Ty
,
VectorType
*
CondTy
,
bool
IsPairwise
,
bool
IsUnsigned
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
!
isa
<
ScalableVectorType
>
(
Ty
)
)
return
BaseT
::
getMinMaxReductionCost
(
Ty
,
CondTy
,
IsPairwise
,
IsUnsigned
,
CostKind
)
;
assert
(
(
isa
<
ScalableVectorType
>
(
Ty
)
&&
isa
<
ScalableVectorType
>
(
CondTy
)
)
&&
"Both vector needs to be scalable"
)
;
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
Ty
)
;
InstructionCost
LegalizationCost
=
0
;
if
(
LT
.
first
>
1
)
{
Type
*
LegalVTy
=
EVT
(
LT
.
second
)
.
getTypeForEVT
(
Ty
->
getContext
(
)
)
;
unsigned
CmpOpcode
=
Ty
->
isFPOrFPVectorTy
(
)
Instruction
::
FCmp
:
Instruction
::
ICmp
;
LegalizationCost
=
getCmpSelInstrCost
(
CmpOpcode
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
+
getCmpSelInstrCost
(
Instruction
::
Select
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
;
LegalizationCost
*=
LT
.
first
1
;
}
return
LegalizationCost
+
2
;
}
</s>

Try to calculate op costs for min/max reduction operations .


<s> static bool pa_can_eliminate ( const int from , const int to ) { if ( TARGET_64BIT && from == ARG_POINTER_REGNUM ) return false ; return ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled .


<s> static bool loongarch_can_change_mode_class ( machine_mode , machine_mode , reg_class_t rclass ) { return ! reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


<s> const uint32_t * FISCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
void
machopic_output_stub
(
FILE
*
file
,
const
char
*
symb
,
const
char
*
stub
)
{
unsigned
int
length
;
char
*
symbol_name
,
*
lazy_ptr_name
;
char
*
local_label_0
;
static
int
label
=
0
;
symb
=
(
*
targetm
.
strip_name_encoding
)
(
symb
)
;
length
=
strlen
(
symb
)
;
symbol_name
=
XALLOCAVEC
(
char
,
length
+
32
)
;
GEN_SYMBOL_NAME_FOR_SYMBOL
(
symbol_name
,
symb
,
length
)
;
lazy_ptr_name
=
XALLOCAVEC
(
char
,
length
+
32
)
;
GEN_LAZY_PTR_NAME_FOR_SYMBOL
(
lazy_ptr_name
,
symb
,
length
)
;
if
(
flag_pic
==
2
)
switch_to_section
(
darwin_sections
[
machopic_picsymbol_stub1_section
]
)
;
else
switch_to_section
(
darwin_sections
[
machopic_symbol_stub1_section
]
)
;
if
(
flag_pic
==
2
)
{
fprintf
(
file
,
"\t.align 5\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
label
++
;
local_label_0
=
XALLOCAVEC
(
char
,
sizeof
(
"\"L00000000000$spb\""
)
)
;
sprintf
(
local_label_0
,
"\"L%011d$spb\""
,
label
)
;
fprintf
(
file
,
"\tmflr r0\n"
)
;
if
(
TARGET_LINK_STACK
)
{
char
name
[
32
]
;
get_ppc476_thunk_name
(
name
)
;
fprintf
(
file
,
"\tbl %s\n"
,
name
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
}
else
{
fprintf
(
file
,
"\tbcl 20,31,%s\n"
,
local_label_0
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
}
fprintf
(
file
,
"\taddis r11,r11,ha16(%s-%s)\n"
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtlr r0\n"
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s-%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
else
{
fprintf
(
file
,
"\t.align 4\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"\tlis r11,ha16(%s)\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
switch_to_section
(
darwin_sections
[
machopic_lazy_symbol_ptr_section
]
)
;
fprintf
(
file
,
"%s:\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"%sdyld_stub_binding_helper\n"
,
(
TARGET_64BIT
DOUBLE_INT_ASM_OP
:
"\t.long\t"
)
)
;
}
</s>

Generate external symbol indirection stubs ( PIC and non-PIC ) .

powerpcspe
0
32
32
2
2
"\t.align 5\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"\"L00000000000$spb\""
"\"L%011d$spb\""
"\tmflr r0\n"
32
"\tbl %s\n"
"%s:\n\tmflr r11\n"
"\tbcl 20,31,%s\n"
"%s:\n\tmflr r11\n"
"\taddis r11,r11,ha16(%s-%s)\n"
"\tmtlr r0\n"
"\t%s r12,lo16(%s-%s)(r11)\n"
"ldu"
"lwzu"
"\tmtctr r12\n"
"\tbctr\n"
"\t.align 4\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"\tlis r11,ha16(%s)\n"
"\t%s r12,lo16(%s)(r11)\n"
"ldu"
"lwzu"
"\tmtctr r12\n"
"\tbctr\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"%sdyld_stub_binding_helper\n"
"\t.long\t"