<s>
void
SHUXIDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SDLoc
dl
(
Node
)
;
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
assert
(
Node
->
getValueType
(
0
)
==
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
SHUXI
::
ADDri
,
MVT
::
i32
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
SHUXI
::
ADDri
,
dl
,
MVT
::
i32
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
dl
,
MVT
::
i32
)
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; MinimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> int empty_delay_slot ( rtx insn ) { rtx seq ; if ( PREV_INSN ( insn ) == NULL ) return 1 ; seq = NEXT_INSN ( PREV_INSN ( insn ) ) ; if ( GET_CODE ( PATTERN ( seq ) ) == SEQUENCE ) return 0 ; return 1 ; } </s>

Return non-zero if a branch or call instruction will be emitting a nop into its delay slot .


<s> MachineBasicBlock :: iterator Cpu0FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tSpill
0


<s> void ix86_expand_convert_sign_didf_sse ( rtx target , rtx input ) { REAL_VALUE_TYPE TWO32r ; rtx fp_lo , fp_hi , x ; fp_lo = gen_reg_rtx ( DFmode ) ; fp_hi = gen_reg_rtx ( DFmode ) ; emit_insn ( gen_floatsidf2 ( fp_hi , gen_highpart ( SImode , input ) ) ) ; real_ldexp ( & TWO32r , & dconst1 , 32 ) ; x = const_double_from_real_value ( TWO32r , DFmode ) ; fp_hi = expand_simple_binop ( DFmode , MULT , fp_hi , x , fp_hi , 0 , OPTAB_DIRECT ) ; ix86_expand_convert_uns_sidf_sse ( fp_lo , gen_lowpart ( SImode , input ) ) ; x = expand_simple_binop ( DFmode , PLUS , fp_hi , fp_lo , target , 0 , OPTAB_DIRECT ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Convert a signed DImode value into a DFmode . Only used for SSE in 32-bit mode ; otherwise we have a direct convert instruction .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
tree
branch_island
;
for
(
branch_island
=
branch_island_list
;
branch_island
;
branch_island
=
TREE_CHAIN
(
branch_island
)
)
{
const
char
*
label
=
IDENTIFIER_POINTER
(
BRANCH_ISLAND_LABEL_NAME
(
branch_island
)
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
BRANCH_ISLAND_FUNCTION_NAME
(
branch_island
)
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
BRANCH_ISLAND_LINE_NUMBER
(
branch_island
)
)
;
if
(
flag_pic
)
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\nlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
dbxout_stabd
(
N_SLINE
,
BRANCH_ISLAND_LINE_NUMBER
(
branch_island
)
)
;
}
branch_island_list
=
0
;
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s> EVT X86TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; const TargetMachine & TM = getTargetMachine ( ) ; if ( ! TM . Options . UseSoftFloat && Subtarget -> hasAVX512 ( ) ) switch ( VT . getVectorNumElements ( ) ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void thumb2_final_prescan_insn ( rtx_insn * insn ) { rtx_insn * first_insn = insn ; rtx body = PATTERN ( insn ) ; rtx predicate ; enum arm_cond_code code ; int n ; int mask ; int max ; max = MAX_INSN_PER_IT_BLOCK ; if ( arm_condexec_count ) arm_condexec_count -- ; if ( arm_condexec_count ) return ; if ( GET_CODE ( body ) != COND_EXEC ) return ; if ( JUMP_P ( insn ) ) return ; predicate = COND_EXEC_TEST ( body ) ; arm_current_cc = get_arm_condition_code ( predicate ) ; n = get_attr_ce_count ( insn ) ; arm_condexec_count = 1 ; arm_condexec_mask = ( 1 << n ) - 1 ; arm_condexec_masklen = n ; for ( ; ; ) { insn = next_nonnote_insn ( insn ) ; if ( ! NONJUMP_INSN_P ( insn ) && ! JUMP_P ( insn ) ) break ; body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == USE || GET_CODE ( body ) == CLOBBER ) continue ; if ( GET_CODE ( body ) != COND_EXEC ) break ; n = get_attr_ce_count ( insn ) ; if ( arm_condexec_masklen + n > max ) break ; predicate = COND_EXEC_TEST ( body ) ; code = get_arm_condition_code ( predicate ) ; mask = ( 1 << n ) - 1 ; if ( arm_current_cc == code ) arm_condexec_mask |= ( mask << arm_condexec_masklen ) ; else if ( arm_current_cc != ARM_INVERSE_CONDITION_CODE ( code ) ) break ; arm_condexec_count ++ ; arm_condexec_masklen += n ; if ( JUMP_P ( insn ) ) break ; } extract_constrain_insn_cached ( first_insn ) ; } </s>

Tell arm_asm_output_opcode to output IT blocks for conditionally executed instructions .


<s> void ARMHazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == 0 ) LastMI = 0 ; ScoreboardHazardRecognizer :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> bool VETargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = RetCC_VE ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static void aarch64_add_cfa_expression ( rtx_insn * insn , rtx reg , rtx base , poly_int64 offset ) { rtx mem = gen_frame_mem ( GET_MODE ( reg ) , plus_constant ( Pmode , base , offset ) ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ; } </s>

Add a REG_CFA_EXPRESSION note to INSN to say that register REG is saved at BASE + OFFSET .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Enqueue Exit Blocks"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const PPCTargetMachine & TM ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , IsPPC64 ( TargetTriple . getArch ( ) == Triple :: ppc64 || TargetTriple . getArch ( ) == Triple :: ppc64le ) , TargetABI ( PPC_ABI_UNKNOWN ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( * this ) , TLInfo ( TM , * this ) , TSInfo ( TM . getDataLayout ( ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void LC3AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64 : case ARM :: VST1d64TPseudo : case ARM :: VST1d64QPseudo : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . init ( * TRI ) ; DomBBUsedRegs . init ( * TRI ) ; OptBBClobberedRegs . init ( * TRI ) ; OptBBUsedRegs . init ( * TRI ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( & MBB ) ; return Changed ; } </s>


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; HasPWRPSR = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool ARMSubtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return true ; if ( isTargetDarwin ( ) && TM . isPositionIndependent ( ) && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return true ; return false ; } </s>

True if the GV will be accessed via an indirect symbol .


<s>
bool
AArch64AddressTypePromotion
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
)
return
false
;
if
(
!
EnableAddressTypePromotion
||
F
.
isDeclaration
(
)
)
return
false
;
Func
=
&
F
;
ConsideredSExtType
=
Type
::
getInt64Ty
(
Func
->
getContext
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"*** "
<<
getPassName
(
)
<<
": "
<<
Func
->
getName
(
)
<<
'\n'
)
;
Instructions
SExtInsts
;
analyzeSExtension
(
SExtInsts
)
;
return
propagateSignExtension
(
SExtInsts
)
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasV8_2aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasPerfMon ( false ) , HasFullFP16 ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , StrictAlign ( false ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>


<s> void rs6000_emit_sCOND ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx ; machine_mode op_mode ; enum rtx_code cond_code ; rtx result = operands [ 0 ] ; condition_rtx = rs6000_generate_compare ( operands [ 1 ] , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; if ( FLOAT_MODE_P ( mode ) && ! TARGET_FPRS && TARGET_HARD_FLOAT ) { rtx t ; PUT_MODE ( condition_rtx , SImode ) ; t = XEXP ( condition_rtx , 0 ) ; gcc_assert ( cond_code == NE || cond_code == EQ ) ; if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , 0 ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , 0 ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 0 ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ 1 ] , 1 ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , 0 ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result , condition_rtx ) ) ; } } </s>


<s> const char * mips_output_order_conditional_branch ( rtx_insn * insn , rtx * operands , bool inverted_p ) { const char * branch [ 2 ] ; switch ( GET_CODE ( operands [ 1 ] ) ) { case LEU : inverted_p = ! inverted_p ; case GTU : branch [ ! inverted_p ] = MIPS_BRANCH ( "bne" , "%2,%.,%0" ) ; branch [ inverted_p ] = MIPS_BRANCH ( "beq" , "%2,%.,%0" ) ; break ; case LTU : inverted_p = ! inverted_p ; case GEU : branch [ ! inverted_p ] = MIPS_BRANCH ( "beq" , "%.,%.,%0" ) ; branch [ inverted_p ] = MIPS_BRANCH ( "bne" , "%.,%.,%0" ) ; break ; default : branch [ ! inverted_p ] = MIPS_BRANCH ( "b%C1z" , "%2,%0" ) ; branch [ inverted_p ] = MIPS_BRANCH ( "b%N1z" , "%2,%0" ) ; break ; } return mips_output_conditional_branch ( insn , operands , branch [ 1 ] , branch [ 0 ] ) ; } </s>

Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some ordering condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; its second is always zero .


<s> static tree get_prev_label ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return bi -> label_name ; return NULL_TREE ; } </s>

GET_PREV_LABEL gets the label name from the previous definition of the function .


"%qE attribute requires a string constant argument"

Part of the low level implementation of DEC Ada pragma Common_Object which enables the shared use of variables stored in overlaid linker areas corresponding to the use of Fortran COMMON .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; Register SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; Register SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; Register DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * LdMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , * LdMI , * LdMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM A15 S->D optimizer"
;
}
</s>


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , HOST_WIDE_INT offset ) { x = strip_salt ( x ) ; if ( LABEL_REF_P ( x ) ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( SYMBOL_REF_P ( x ) ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - 0x10000 , 0x10000 ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - 0x100000 , 0x100000 ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_LARGE : if ( ! aarch64_pcrelative_literal_loads && CONSTANT_POOL_ADDRESS_P ( x ) ) return SYMBOL_SMALL_ABSOLUTE ; else return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s>
char
*
xstormy16_output_cbranch_hi
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx
insn
)
{
static
char
string
[
64
]
;
int
need_longbranch
=
(
op
!=
NULL_RTX
get_attr_length
(
insn
)
==
8
:
get_attr_length
(
insn
)
==
4
)
;
int
really_reversed
=
reversed
^
need_longbranch
;
const
char
*
ccode
;
const
char
*
template
;
const
char
*
operands
;
enum
rtx_code
code
;
if
(
!
op
)
{
if
(
need_longbranch
)
ccode
=
"jmpf"
;
else
ccode
=
"br"
;
sprintf
(
string
,
"%s %s"
,
ccode
,
label
)
;
return
string
;
}
code
=
GET_CODE
(
op
)
;
if
(
GET_CODE
(
XEXP
(
op
,
0
)
)
!=
REG
)
{
code
=
swap_condition
(
code
)
;
operands
=
"%3,%2"
;
}
else
operands
=
"%2,%3"
;
if
(
really_reversed
)
code
=
reverse_condition
(
code
)
;
switch
(
code
)
{
case
EQ
:
ccode
=
"z"
;
break
;
case
NE
:
ccode
=
"nz"
;
break
;
case
GE
:
ccode
=
"ge"
;
break
;
case
LT
:
ccode
=
"lt"
;
break
;
case
GT
:
ccode
=
"gt"
;
break
;
case
LE
:
ccode
=
"le"
;
break
;
case
GEU
:
ccode
=
"nc"
;
break
;
case
LTU
:
ccode
=
"c"
;
break
;
case
GTU
:
ccode
=
"hi"
;
break
;
case
LEU
:
ccode
=
"ls"
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
need_longbranch
)
template
=
"b%s %s,.+8 | jmpf %s"
;
else
template
=
"b%s %s,%s"
;
sprintf
(
string
,
template
,
ccode
,
operands
,
label
)
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , which is the operand number of the label . OP is the conditional expression , or NULL for branch-always . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the insn .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> static bool sh_legitimize_address_displacement ( rtx * disp , rtx * offs , machine_mode mode ) { if ( TARGET_SHMEDIA ) return false ; if ( ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return false ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( * disp ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { * disp = adj . mov_disp ; * offs = adj . offset_adjust ; return true ; } return false ; } </s>

Return true if DISP can be legitimized .


<s> bool iq2000_can_eliminate ( const int from , const int to ) { return ( from == RETURN_ADDRESS_POINTER_REGNUM && ( ! leaf_function_p ( ) || ( to == GP_REG_FIRST + 31 && leaf_function_p ( ) ) ) ) || ( from != RETURN_ADDRESS_POINTER_REGNUM && ( to == HARD_FRAME_POINTER_REGNUM || ( to == STACK_POINTER_REGNUM && ! frame_pointer_needed ) ) ) ; } </s>

We can always eliminate to the frame pointer . We can eliminate to the stack pointer unless a frame pointer is needed .


<s> static void xstormy16_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx temp = gen_reg_rtx ( HImode ) ; rtx reg_fnaddr = gen_reg_rtx ( HImode ) ; rtx reg_addr , reg_addr_mem ; reg_addr = copy_to_reg ( XEXP ( m_tramp , 0 ) ) ; reg_addr_mem = adjust_automodify_address ( m_tramp , HImode , reg_addr , 0 ) ; emit_move_insn ( temp , GEN_INT ( 0x3130 | STATIC_CHAIN_REGNUM ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , 2 ) ; emit_move_insn ( temp , static_chain ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , 2 ) ; emit_move_insn ( reg_fnaddr , XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; emit_move_insn ( temp , reg_fnaddr ) ; emit_insn ( gen_andhi3 ( temp , temp , GEN_INT ( 0xFF ) ) ) ; emit_insn ( gen_iorhi3 ( temp , temp , GEN_INT ( 0x0200 ) ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , 2 ) ; emit_insn ( gen_lshrhi3 ( reg_fnaddr , reg_fnaddr , GEN_INT ( 8 ) ) ) ; emit_move_insn ( reg_addr_mem , reg_fnaddr ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


<s> unsigned int darwin_rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; if ( TYPE_PACKED ( type ) ) return align ; do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return align ; } </s>

Darwin increases record alignment to the natural alignment of the first field .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return getParser ( ) . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> void MipsCallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , unsigned OriginalIndex , SmallVectorImpl < ArgInfo > & SplitArgs , SmallVectorImpl < unsigned > & SplitArgsOrigIndices ) const { SplitArgs . push_back ( OrigArg ) ; SplitArgsOrigIndices . push_back ( OriginalIndex ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static bool rs6000_cannot_copy_insn_p ( rtx_insn * insn ) { return recog_memoized ( insn ) >= 0 && get_attr_cannot_copy ( insn ) ; } </s>

Return true if INSN should not be copied .


"Function versions cannot be marked as gnu_inline,"

"Virtual function multiversioning not supported"

This function changes the assembler name for functions that are versions . If DECL is a function version and has a `` target '' attribute , it appends the attribute string to its assembler name .


<s> const char * TOYTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case TOYISD :: CALL : return "TOYISD::CALL" ; case TOYISD :: BR_CC : return "TOYISD::BR_CC" ; case TOYISD :: CMPEQ : return "TOYISD::CMPEQ" ; case TOYISD :: CMPNE : return "TOYISD::CMPNE" ; case TOYISD :: CMPLT : return "TOYISD::CMPLT" ; case TOYISD :: CMPLE : return "TOYISD::CMPLE" ; case TOYISD :: CMPGT : return "TOYISD::CMPGT" ; case TOYISD :: CMPGE : return "TOYISD::CMPGE" ; case TOYISD :: RET_FLAG : return "TOYIDS::RET_FLAG" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

TOY TOY 0 TOYISD::CALL "TOYISD::CALL" TOYISD::BR_CC "TOYISD::BR_CC" TOYISD::CMPEQ "TOYISD::CMPEQ" TOYISD::CMPNE "TOYISD::CMPNE" TOYISD::CMPLT "TOYISD::CMPLT" TOYISD::CMPLE "TOYISD::CMPLE" TOYISD::CMPGT "TOYISD::CMPGT" TOYISD::CMPGE "TOYISD::CMPGE" TOYISD::RET_FLAG "TOYIDS::RET_FLAG"


<s> static void mips16_emit_constants ( struct mips16_constant * constants , rtx_insn * insn ) { struct mips16_constant * c , * next ; int align ; align = 0 ; for ( c = constants ; c != NULL ; c = next ) { if ( align < GET_MODE_SIZE ( c -> mode ) ) { int align_log = floor_log2 ( GET_MODE_SIZE ( c -> mode ) ) ; insn = emit_insn_after ( gen_align ( GEN_INT ( align_log ) ) , insn ) ; } align = GET_MODE_SIZE ( c -> mode ) ; insn = emit_label_after ( c -> label , insn ) ; insn = mips16_emit_constants_1 ( c -> mode , c -> value , insn ) ; next = c -> next ; free ( c ) ; } emit_barrier_after ( insn ) ; } </s>

Dump out the constants in CONSTANTS after INSN .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const DLXSubtarget & Subtarget = MF . getSubtarget < DLXSubtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADDCARRY
:
IsSelected
=
selectAddCarry
(
N
)
;
break
;
case
ISD
::
SUBCARRY
:
IsSelected
=
selectSubCarry
(
N
)
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
{
Register
GP
=
Subtarget
->
getInstrInfo
(
)
->
getGlobalBaseReg
(
*
MF
)
;
ReplaceNode
(
N
,
CurDAG
->
getRegister
(
GP
,
N
->
getValueType
(
0
)
)
.
getNode
(
)
)
;
IsSelected
=
true
;
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
Dl
,
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
N
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
ReplaceNode
(
N
,
CurDAG
->
getMachineNode
(
Subtarget
->
hasE2
(
)
CSKY
::
ADDI32
:
CSKY
::
ADDI16XZ
,
Dl
,
MVT
::
i32
,
TFI
,
Imm
)
)
;
IsSelected
=
true
;
break
;
}
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> void paired_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 ; rtx x , new_rtx , tmp , constant_op , op1 , op2 ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONST_FIXED_P ( x ) ) ) ++ n_var ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( n_var == 2 ) { new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , XVECEXP ( vals , 0 , 0 ) , XVECEXP ( vals , 0 , 1 ) ) ; emit_move_insn ( target , new_rtx ) ; return ; } op1 = XVECEXP ( vals , 0 , 0 ) ; op2 = XVECEXP ( vals , 0 , 1 ) ; constant_op = ( CONSTANT_P ( op1 ) ) ? op1 : op2 ; tmp = gen_reg_rtx ( GET_MODE ( constant_op ) ) ; emit_move_insn ( tmp , constant_op ) ; if ( CONSTANT_P ( op1 ) ) new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , tmp , op2 ) ; else new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , op1 , tmp ) ; emit_move_insn ( target , new_rtx ) ; } </s>

Initialize TARGET of vector PAIRED to VALS .


<s> bool legitimate_pic_operand_p ( rtx x ) { rtx inner ; switch ( GET_CODE ( x ) ) { case CONST : inner = XEXP ( x , 0 ) ; if ( GET_CODE ( inner ) == PLUS && GET_CODE ( XEXP ( inner , 1 ) ) == CONST_INT ) inner = XEXP ( inner , 0 ) ; if ( GET_CODE ( inner ) == UNSPEC ) switch ( XINT ( inner , 1 ) ) { case UNSPEC_GOTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : x = XVECEXP ( inner , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; default : return false ; } case SYMBOL_REF : case LABEL_REF : return legitimate_pic_address_disp_p ( x ) ; default : return true ; } } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> bool rs6000_pcrel_p ( ) { return ( DEFAULT_ABI == ABI_ELFv2 && ( rs6000_isa_flags & OPTION_MASK_PCREL ) != 0 && TARGET_CMODEL == CMODEL_MEDIUM ) ; } </s>

Return whether we should generate PC-relative code for the current function .


<s> static bool ix86_profile_before_prologue ( void ) { return flag_fentry != 0 ; } </s>

Return true , if profiling code should be emitted before prologue . Otherwise it returns false . Note : For x86 with `` hotfix '' it is sorried .


<s> static rtx mips16e_save_restore_reg ( bool restore_p , bool reg_parm_p , HOST_WIDE_INT offset , unsigned int regno ) { rtx reg , mem ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( restore_p ) { mips_add_cfa_restore ( reg ) ; return gen_rtx_SET ( reg , mem ) ; } if ( reg_parm_p ) return gen_rtx_SET ( mem , reg ) ; return mips_frame_set ( mem , reg ) ; } </s>

Return a move between register REGNO and memory location SP + OFFSET . REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE . Make the move a load if RESTORE_P , otherwise make it a store .


<s> int pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT && ! SMALL_INT ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) return 1 ; return 0 ; } </s>

Return true if X is an address which needs a temporary register when reloaded while generating PIC code .


<s> static unsigned int aarch64_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment = aarch64_function_arg_alignment ( mode , type ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return alignment ; } </s>

Implement FUNCTION_ARG_BOUNDARY . Every parameter gets at least PARM_BOUNDARY bits of alignment , but will be given anything up to STACK_BOUNDARY bits if the type requires it . This makes sure that both before and after the layout of each argument , the Next Stacked Argument Address ( NSAA ) will have a minimum alignment of 8 bytes .


<s> static void rs6000_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; if ( cost_data -> loop_info ) rs6000_density_test ( cost_data ) ; * prologue_cost = cost_data -> cost [ vect_prologue ] ; * body_cost = cost_data -> cost [ vect_body ] ; * epilogue_cost = cost_data -> cost [ vect_epilogue ] ; } </s>


"declaration as dllimport: attribute ignored"

"definition of static data member %q+D of dllimport'd class"

Return nonzero if DECL is a dllimport 'd object .


<s> SDValue SystemZTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_SystemZ ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool ix86_expand_vec_one_operand_perm_avx512 ( struct expand_vec_perm_d * d ) { machine_mode mode = GET_MODE ( d -> op0 ) ; machine_mode maskmode = mode ; rtx ( * gen ) ( rtx , rtx , rtx ) = NULL ; rtx target , op0 , mask ; rtx vec [ 64 ] ; if ( ! rtx_equal_p ( d -> op0 , d -> op1 ) ) return false ; if ( ! TARGET_AVX512F ) return false ; switch ( mode ) { case V16SImode : gen = gen_avx512f_permvarv16si ; break ; case V16SFmode : gen = gen_avx512f_permvarv16sf ; maskmode = V16SImode ; break ; case V8DImode : gen = gen_avx512f_permvarv8di ; break ; case V8DFmode : gen = gen_avx512f_permvarv8df ; maskmode = V8DImode ; break ; default : return false ; } target = d -> target ; op0 = d -> op0 ; for ( int i = 0 ; i < d -> nelt ; ++ i ) vec [ i ] = GEN_INT ( d -> perm [ i ] ) ; mask = gen_rtx_CONST_VECTOR ( maskmode , gen_rtvec_v ( d -> nelt , vec ) ) ; emit_insn ( gen ( target , op0 , force_reg ( maskmode , mask ) ) ) ; return true ; } </s>

Try to expand one-operand permutation with constant mask .


<s> bool X86TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; return ( CallerBits & CalleeBits ) == CalleeBits ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> bool X86TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isScalarInteger ( ) || ! VT2 . isScalarInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> MachineInstr * SparcInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned OpNum = Ops [ 0 ] ; bool isFloat = false ; MachineInstr * NewMI = NULL ; switch ( MI -> getOpcode ( ) ) { case SP :: ORrr : if ( MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 1 ) . getReg ( ) == SP :: G0 && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 2 ) . isReg ( ) ) { if ( OpNum == 0 ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: STri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SP :: LDri ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; case SP :: FMOVS : isFloat = true ; case SP :: FMOVD : if ( OpNum == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; bool isUndef = MI -> getOperand ( 1 ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: STFri : SP :: STDFri ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) | getUndefRegState ( isUndef ) ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; bool isUndef = MI -> getOperand ( 0 ) . isUndef ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? SP :: LDFri : SP :: LDDFri ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) | getUndefRegState ( isUndef ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
StringRef
Mnemonic
;
if
(
requestsDoubleOperand
(
Name
)
)
{
setFpFormat
(
FP_FORMAT_D
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
Mnemonic
=
Name
;
}
else
{
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
MipsOperand::CreateToken
0
MipsOperand::CreateToken
1
MipsOperand::CreateToken
"c."
MipsOperand::CreateToken
"."
1
"Invalid conditional code"
1
MipsOperand::CreateImm
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> static int nds32_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( ( from == FP_REGS && to != FP_REGS ) || ( from != FP_REGS && to == FP_REGS ) ) return 9 ; else if ( from == HIGH_REGS || to == HIGH_REGS ) return optimize_size ? 6 : 2 ; else return 2 ; } </s>

Describing Relative Costs of Operations .


<s> const TargetRegisterClass * AArch64RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & AArch64 :: FlagClassRegClass ) return & AArch64 :: GPR64RegClass ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> void MipsAsmPrinter :: emitInlineAsmStart ( const MCSubtargetInfo & StartInfo ) const { MipsTargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetPush ( ) ; TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; OutStreamer . AddBlankLine ( ) ; } </s>

Let the target do anything it needs to do before emitting inlineasm .


<s> int pa_attr_length_indirect_call ( rtx_insn * insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) return 12 ; if ( TARGET_FAST_INDIRECT_CALLS ) return 8 ; if ( TARGET_PORTABLE_RUNTIME ) return 16 ; if ( ( TARGET_NO_SPACE_REGS || TARGET_PA_20 ) && ! optimize_size ) return 20 ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) return 8 ; if ( ! flag_pic ) return 12 ; if ( TARGET_NO_SPACE_REGS || TARGET_PA_20 ) return 20 ; if ( ! optimize_size ) return 36 ; return 20 ; } </s>

Return the attribute length of the indirect call instruction INSN . The length must match the code generated by output_indirect call . The returned length includes the delay slot . Currently , the delay slot of an indirect call sequence is not exposed and it is used by the sequence itself .


<s> bool sh_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( SPECIAL_REGISTER_P ( regno ) ) return mode == SImode ; if ( regno == FPUL_REG ) return ( mode == SImode || mode == SFmode ) ; if ( FP_REGISTER_P ( regno ) && mode == SFmode ) return true ; if ( mode == V2SFmode ) { if ( ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 2 == 0 ) || GENERAL_REGISTER_P ( regno ) ) ) return true ; else return false ; } if ( mode == V4SFmode ) { if ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 4 == 0 ) || GENERAL_REGISTER_P ( regno ) ) return true ; else return false ; } if ( mode == V16SFmode ) { if ( TARGET_SHMEDIA ) { if ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 16 == 0 ) return true ; else return false ; } else return regno == FIRST_XD_REG ; } if ( FP_REGISTER_P ( regno ) ) { if ( mode == SFmode || mode == SImode || ( ( TARGET_SH2E || TARGET_SHMEDIA ) && mode == SCmode ) || ( ( ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && mode == DFmode ) || mode == DCmode || ( TARGET_SHMEDIA && ( mode == DFmode || mode == DImode || mode == V2SFmode || mode == TImode ) ) ) && ( ( regno - FIRST_FP_REG ) & 1 ) == 0 ) || ( ( TARGET_SH4 || TARGET_SHMEDIA ) && mode == TImode && ( ( regno - FIRST_FP_REG ) & 3 ) == 0 ) ) return true ; else return false ; } if ( XD_REGISTER_P ( regno ) ) return mode == DFmode ; if ( TARGET_REGISTER_P ( regno ) ) return ( mode == DImode || mode == SImode || mode == PDImode ) ; if ( regno == PR_REG ) return mode == SImode ; if ( regno == FPSCR_REG ) return mode == SImode ; if ( ! optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE ( mode ) > 4 ) { unsigned int n = GET_MODE_SIZE ( mode ) / 8 ; if ( regno >= FIRST_GENERAL_REG + 10 - n + 1 && regno <= FIRST_GENERAL_REG + 14 ) return false ; } return true ; } </s>

Return true if hard register REGNO can hold a value of machine-mode MODE . We can allow any mode in any general register . The special registers only allow SImode . Do n't allow any mode in the PR . We can not hold DCmode values in the XD registers because alter_reg handles subregs of them incorrectly . We could work around this by spacing the XD registers like the DR registers , but this would require additional memory in every compilation to hold larger register vectors . We could hold SFmode / SCmode values in XD registers , but that would require a tertiary reload when reloading from / to memory , and a secondary reload to reload from / to general regs ; that seems to be a losing proposition . We want to allow TImode FP regs so that when V4SFmode is loaded as TImode , it wo n't be ferried through GP registers first .


<s>
VE
::
Fixups
VEMCExpr
::
getFixupKind
(
VEMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Unhandled VEMCExpr::VariantKind"
)
;
case
VK_VE_HI32
:
return
VE
::
fixup_ve_hi32
;
case
VK_VE_LO32
:
return
VE
::
fixup_ve_lo32
;
case
VK_VE_PC_HI32
:
return
VE
::
fixup_ve_pc_hi32
;
case
VK_VE_PC_LO32
:
return
VE
::
fixup_ve_pc_lo32
;
case
VK_VE_GOT_HI32
:
return
VE
::
fixup_ve_got_hi32
;
case
VK_VE_GOT_LO32
:
return
VE
::
fixup_ve_got_lo32
;
case
VK_VE_GOTOFF_HI32
:
return
VE
::
fixup_ve_gotoff_hi32
;
case
VK_VE_GOTOFF_LO32
:
return
VE
::
fixup_ve_gotoff_lo32
;
case
VK_VE_PLT_HI32
:
return
VE
::
fixup_ve_plt_hi32
;
case
VK_VE_PLT_LO32
:
return
VE
::
fixup_ve_plt_lo32
;
case
VK_VE_TLS_GD_HI32
:
return
VE
::
fixup_ve_tls_gd_hi32
;
case
VK_VE_TLS_GD_LO32
:
return
VE
::
fixup_ve_tls_gd_lo32
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> static unsigned int ATTRIBUTE_UNUSED x86_64_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl == NULL_TREE && ( strcmp ( name , ".ldata.rel.ro" ) == 0 || strcmp ( name , ".ldata.rel.ro.local" ) == 0 ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , ".lbss" ) == 0 || strncmp ( name , ".lbss." , 5 ) == 0 || strncmp ( name , ".gnu.linkonce.lb." , 16 ) == 0 ) flags |= SECTION_BSS ; return flags ; } </s>

Select a set of attributes for section NAME based on the properties of DECL and whether or not RELOC indicates that DECL 's initializer might contain runtime relocations .


<s> unsigned get231Opcode ( ) const { return Opcodes [ Form231 ] ; } </s>


<s> static int indirectable_address_p ( rtx x , int strict ) { if ( indirectable_constant_address_p ( x ) ) return 1 ; if ( BASE_REGISTER_P ( x , strict ) ) return 1 ; if ( GET_CODE ( x ) == PLUS && BASE_REGISTER_P ( XEXP ( x , 0 ) , strict ) && indirectable_constant_address_p ( XEXP ( x , 1 ) ) ) return 1 ; return 0 ; } </s>

Nonzero if X is an address which can be indirected . External symbols could be in a sharable image library , so we disallow those .


<s> static void emit_frame_save ( rtx frame_reg , rtx frame_ptr , enum machine_mode mode , unsigned int regno , int offset , HOST_WIDE_INT total_size ) { rtx reg , offset_rtx , insn , mem , addr , int_rtx ; rtx replacea , replaceb ; int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) { offset_rtx = gen_rtx_REG ( Pmode , 11 ) ; emit_move_insn ( offset_rtx , int_rtx ) ; replacea = offset_rtx ; replaceb = int_rtx ; } else { offset_rtx = int_rtx ; replacea = NULL_RTX ; replaceb = NULL_RTX ; } reg = gen_rtx_REG ( mode , regno ) ; addr = gen_rtx_PLUS ( Pmode , frame_reg , offset_rtx ) ; mem = gen_rtx_MEM ( mode , addr ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set ) ; insn = emit_move_insn ( mem , reg ) ; rs6000_frame_related ( insn , frame_ptr , total_size , replacea , replaceb ) ; } </s>

Save a register into the frame , and emit RTX_FRAME_RELATED_P notes . Save REGNO into [ FRAME_REG + OFFSET ] in mode MODE .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .

ARM ARM::GPRRegClass ARM::tGPRRegClass ARM::tcGPRRegClass ARM::rGPRRegClass ARM::GPRnopcRegClass ARM::t2LDRi12 0 ARM


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createARMWinCOFFObjectWriter ( OS , false ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
void
xstormy16_output_addr_vec
(
FILE
*
file
,
rtx
label
ATTRIBUTE_UNUSED
,
rtx
table
)
{
int
vlen
,
idx
;
current_function_section
(
current_function_decl
)
;
vlen
=
XVECLEN
(
table
,
0
)
;
for
(
idx
=
0
;
idx
<
vlen
;
idx
++
)
{
fputs
(
"\tjmpf "
,
file
)
;
output_asm_label
(
XEXP
(
XVECEXP
(
table
,
0
,
idx
)
,
0
)
)
;
fputc
(
'\n'
,
file
)
;
}
}
</s>

Output an ADDR_VEC . It is output as a sequence of 'jmpf ' instructions , without label or alignment or any other special constructs . We know that the previous instruction will be the ` tablejump_pcrel ' output above . TODO : it might be nice to output 'br ' instructions if they could all reach .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


"dynamic alloca in the static alloca map?"

Emit an alloca address in a register using target-specific logic .


<s>
bool
AArch64PostLegalizerCombiner
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Legalized
)
&&
"Expected a legalized function?"
)
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
bool
EnableOpt
=
MF
.
getTarget
(
)
.
getOptLevel
(
)
!=
CodeGenOpt
::
&&
!
skipFunction
(
F
)
;
GISelKnownBits
*
KB
=
&
getAnalysis
<
GISelKnownBitsAnalysis
>
(
)
.
get
(
MF
)
;
MachineDominatorTree
*
MDT
=
IsOptNone
nullptr
:
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
AArch64PostLegalizerCombinerInfo
PCInfo
(
EnableOpt
,
F
.
hasOptSize
(
)
,
F
.
hasMinSize
(
)
,
KB
,
MDT
)
;
Combiner
C
(
PCInfo
,
TPC
)
;
return
C
.
combineMachineInstrs
(
MF
,
nullptr
)
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void ix86_add_cfa_restore_note ( rtx_insn * insn , rtx reg , HOST_WIDE_INT cfa_offset ) { if ( ! crtl -> shrink_wrapped && cfa_offset <= cfun -> machine -> fs . red_zone_offset ) return ; if ( insn ) { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else queued_cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , reg , queued_cfa_restores ) ; } </s>

Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack manipulation insn . The value is on the stack at CFA - CFA_OFFSET . Do n't add the note if the previously saved value will be left untouched within stack red-zone till return , as unwinders can find the same value in the register and on the stack .


<s> static bool ix86_scalar_mode_supported_p ( scalar_mode mode ) { if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( mode == TFmode ) return true ; else if ( ( mode == HFmode || mode == BFmode ) && TARGET_SSE2 ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> bool ARMCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const auto & TLI = * getTLI < ARMTargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( MF . getSubtarget < ARMSubtarget > ( ) . genLongCalls ( ) ) return false ; MIRBuilder . buildInstr ( ARM :: ADJCALLSTACKDOWN ) . addImm ( 0 ) . add ( predOps ( ARMCC :: AL ) ) ; auto CallConv = MF . getFunction ( ) -> getCallingConv ( ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( ARM :: BLX ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; splitToValueTypes ( Arg , ArgInfos , DL , MRI ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( OrigRet , ArgInfos , DL , MRI ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ; } MIRBuilder . buildInstr ( ARM :: ADJCALLSTACKUP ) . addImm ( 0 ) . addImm ( 0 ) . add ( predOps ( ARMCC :: AL ) ) ; return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .

ARM ARM ARM ARM ARM::ADJCALLSTACKDOWN 0 ARMCC::AL ARM::BLX 8 ARM::ADJCALLSTACKUP 0 0 ARMCC::AL


<s> static bool pa_expand_compare_and_swap_loop ( rtx mem , rtx old_reg , rtx new_reg , rtx seq ) { machine_mode mode = GET_MODE ( mem ) ; rtx_code_label * label ; rtx cmp_reg , success , oldval ; label = gen_label_rtx ( ) ; cmp_reg = gen_reg_rtx ( mode ) ; emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; emit_move_insn ( old_reg , cmp_reg ) ; if ( seq ) emit_insn ( seq ) ; success = NULL_RTX ; oldval = cmp_reg ; if ( ! expand_atomic_compare_and_swap ( & success , & oldval , mem , old_reg , new_reg , false , MEMMODEL_SYNC_SEQ_CST , MEMMODEL_RELAXED ) ) return false ; if ( oldval != cmp_reg ) emit_move_insn ( cmp_reg , oldval ) ; emit_cmp_and_jump_insns ( success , const0_rtx , EQ , const0_rtx , GET_MODE ( success ) , 1 , label , profile_probability :: guessed_never ( ) ) ; return true ; } </s>

This is a helper function for the other atomic operations . This function emits a loop that contains SEQ that iterates until a compare-and-swap operation at the end succeeds . MEM is the memory to be modified . SEQ is a set of instructions that takes a value from OLD_REG as an input and produces a value in NEW_REG as an output . Before SEQ , OLD_REG will be set to the current contents of MEM . After SEQ , a compare-and-swap will attempt to update MEM with NEW_REG . The function returns true when the loop was generated successfully .


"ARMHWLoops: Trip count does not fit into 32bits\n"

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> uint64_t flags ( ) const { return llvm :: ELF :: EF_ARM_EABI_VER5 ; } </s>

Get the flags for this GlobalValue ( see struct GVFlags ) .


"target_clones attribute needs GLIBC (2.23 and newer) that "

"multiversioning needs ifunc which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( createELFObjectTargetWriter ( ) , OS , true ) ; } </s>


<s> bool ARMTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( std :: abs ( Imm ) ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( std :: abs ( Imm ) ) != - 1 ; return Imm >= 0 && Imm <= 255 ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> static bool sh_return_in_memory ( tree type , tree fndecl ) { if ( TARGET_SH5 ) { if ( TYPE_MODE ( type ) == BLKmode ) return ( ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) ) > 8 ; else return GET_MODE_SIZE ( TYPE_MODE ( type ) ) > 8 ; } else { return ( TYPE_MODE ( type ) == BLKmode || ( ( TARGET_HITACHI || sh_attr_renesas_p ( fndecl ) ) && TREE_CODE ( type ) == RECORD_TYPE ) ) ; } } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> static unsigned char ix86_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( MAYBE_INTEGER_CLASS_P ( rclass ) ) { if ( mode == XFmode ) return ( TARGET_64BIT ? 2 : 3 ) ; else if ( mode == XCmode ) return ( TARGET_64BIT ? 4 : 6 ) ; else return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; } else { if ( COMPLEX_MODE_P ( mode ) ) return 2 ; else return 1 ; } } </s>

Implement the TARGET_CLASS_MAX_NREGS hook . On the 80386 , this is the size of MODE in words , except in the FP regs , where a single reg is always enough .


<s> bool FISCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) & 0xffff ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - 1 ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val ; else O << "xzr" ; return false ; } } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> int attr_length_millicode_call ( rtx insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) { if ( ! TARGET_LONG_CALLS && distance < 7600000 ) return 8 ; return 20 ; } else if ( TARGET_PORTABLE_RUNTIME ) return 24 ; else { if ( ! TARGET_LONG_CALLS && distance < 240000 ) return 8 ; if ( TARGET_LONG_ABS_CALL && ! flag_pic ) return 12 ; return 24 ; } } </s>

Return the attribute length for the millicode call instruction INSN . The length must match the code generated by output_millicode_call . We include the delay slot in the returned length as it is better to over estimate the length than to under estimate it .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { if ( usePreRAHazardRecognizer ( ) ) { const InstrItineraryData * II = static_cast < const ARMSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , "pre-RA-sched" ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> static tree arm_get_cookie_size ( tree type ) { tree size ; if ( ! TARGET_AAPCS_BASED ) return default_cxx_get_cookie_size ( type ) ; size = build_int_cst ( sizetype , 8 ) ; return size ; } </s>

The EABI specifies that all array cookies are 8 bytes long .


<s> static int ix86_enum_va_list ( int idx , const char * * pname , tree * ptree ) { if ( TARGET_64BIT ) { switch ( idx ) { default : break ; case 0 : * ptree = ms_va_list_type_node ; * pname = "__builtin_ms_va_list" ; return 1 ; case 1 : * ptree = sysv_va_list_type_node ; * pname = "__builtin_sysv_va_list" ; return 1 ; } } return 0 ; } </s>

Iterate through the target-specific builtin types for va_list . IDX denotes the iterator , * PTREE is set to the result type of the va_list builtin , and * PNAME to its internal type . Returns zero if there is no element for this index , otherwise IDX should be increased upon the next call . Note , do not iterate a base builtin 's name like __builtin_va_list . Used from c_common_nodes_and_builtins .


<s>
bool
AArch64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
assert
(
0
&&
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void rs6000_emit_le_vsx_load ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_mem , permute_reg ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , 0 ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; permute_mem = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_reg = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_mem ) ) ; emit_insn ( gen_rtx_SET ( dest , permute_reg ) ) ; } </s>

Emit a little-endian load from vector memory location SOURCE to VSX register DEST in mode MODE . The load is done with two permuting insn 's that represent an lxvd2x and xxpermdi .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , DL ( computeDataLayout ( is64bit ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s> static void arm_relayout_function ( tree fndecl ) { if ( DECL_USER_ALIGN ( fndecl ) ) return ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; struct cl_target_option * opts = TREE_TARGET_OPTION ( callee_tree ) ; SET_DECL_ALIGN ( fndecl , FUNCTION_ALIGNMENT ( FUNCTION_BOUNDARY_P ( opts -> x_target_flags ) ) ) ; } </s>

Hook to fix function 's alignment affected by target attribute .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! Subtarget . inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void setPersonality ( const MCSymbol * Per ) { HasPersonality = 1 ; } </s>


<s> bool ARMTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; bool MatchExact = ( CallerBits & ~ InlineFeaturesAllowed ) == ( CalleeBits & ~ InlineFeaturesAllowed ) ; bool MatchSubset = ( ( CallerBits & CalleeBits ) & InlineFeaturesAllowed ) == ( CalleeBits & InlineFeaturesAllowed ) ; return MatchExact && MatchSubset ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> static void mips_sim_wait_units ( struct mips_sim * state , rtx insn ) { state_t tmp_state ; tmp_state = alloca ( state_size ( ) ) ; while ( state -> insns_left == 0 || ( memcpy ( tmp_state , state -> dfa_state , state_size ( ) ) , state_transition ( tmp_state , insn ) >= 0 ) ) mips_sim_next_cycle ( state ) ; } </s>

Advance simulation state STATE until the units required by instruction INSN are available .


<s> static bool branch_needs_nop_p ( rtx_insn * insn ) { rtx_insn * jump_insn ; if ( dbr_sequence_length ( ) ) return FALSE ; jump_insn = next_active_insn ( JUMP_LABEL ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || jump_insn == insn ) return TRUE ; if ( ! ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || extract_asm_operands ( PATTERN ( insn ) ) != NULL_RTX ) && get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a forward jump insn , needs a nop in its delay slot . This occurs when INSN has an unfilled delay slot and is followed by an asm . Disaster can occur if the asm is empty and the jump branches into the delay slot . So , we add a nop in the delay slot when this occurs .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy , int Consecutive ) { int DataWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( ( DataWidth < 32 ) || ( Consecutive == 0 ) ) return false ; if ( ST -> hasAVX512 ( ) || ST -> hasAVX2 ( ) ) return true ; return false ; } </s>

Return true if the target supports masked load .


<s> gimple * gimple_folder :: fold_to_ptrue ( ) { tree svbool_type = TREE_TYPE ( lhs ) ; tree bool_type = TREE_TYPE ( svbool_type ) ; unsigned int element_bytes = type_suffix ( 0 ) . element_bytes ; tree_vector_builder builder ( svbool_type , element_bytes , 1 ) ; builder . quick_push ( build_all_ones_cst ( bool_type ) ) ; for ( unsigned int i = 1 ; i < element_bytes ; ++ i ) builder . quick_push ( build_zero_cst ( bool_type ) ) ; return gimple_build_assign ( lhs , builder . build ( ) ) ; } </s>

Fold the call to a PTRUE , taking the element size from type suffix 0 .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Sparc Assembly Printer"
;
}
</s>


<s> void OutgoingValueHandler :: assignValueToReg ( unsigned ValVReg , const CCValAssign & VA ) { unsigned PhysReg = VA . getLocReg ( ) ; unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
InfosBE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
const
static
MCFixupKindInfo
InfosLE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
2
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
2
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
2
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
2
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
(
Endian
==
support
::
little
InfosLE
:
InfosBE
)
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < CSKYSubtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool X86TargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return ! isa < ConstantSDNode > ( Y ) && hasAndNotCompare ( Y ) ; if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < 128 ) return false ; if ( VT == MVT :: v4i32 ) return true ; return Subtarget . hasSSE2 ( ) ; } </s>

Return true if the target has a bitwise and-not operation : X = ~A & B This can be used to simplify select or other instructions .


<s> SDNode * VEDAGToDAGISel :: getGlobalBaseReg ( ) { Register GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : return 2 ; case PROCESSOR_SB1 : return 3 ; default : return 1 ; } } </s>

Return the number of instructions that can be issued per cycle .


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> static void aarch64_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; int gr_saved = cfun -> va_list_gpr_size ; int vr_saved = cfun -> va_list_fpr_size ; local_cum = * cum ; aarch64_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; if ( cfun -> va_list_gpr_size ) gr_saved = MIN ( NUM_ARG_REGS - local_cum . aapcs_ncrn , cfun -> va_list_gpr_size / UNITS_PER_WORD ) ; if ( cfun -> va_list_fpr_size ) vr_saved = MIN ( NUM_FP_ARG_REGS - local_cum . aapcs_nvrn , cfun -> va_list_fpr_size / UNITS_PER_VREG ) ; if ( ! TARGET_FLOAT ) { gcc_assert ( local_cum . aapcs_nvrn == 0 ) ; vr_saved = 0 ; } if ( ! no_rtl ) { if ( gr_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > 0 ) { machine_mode mode = TImode ; int off , i , vr_start ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) ; off -= vr_saved * UNITS_PER_VREG ; vr_start = V0_REGNUM + local_cum . aapcs_nvrn ; for ( i = 0 ; i < vr_saved ; ++ i ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; aarch64_emit_move ( mem , gen_rtx_REG ( mode , vr_start + i ) ) ; off += UNITS_PER_VREG ; } } } cfun -> machine -> frame . saved_varargs_size = ( ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) + vr_saved * UNITS_PER_VREG ) ; } </s>


<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static section * rx_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( rx_small_data_limit > 0 && GET_MODE_SIZE ( mode ) <= rx_small_data_limit && align <= ( unsigned HOST_WIDE_INT ) rx_small_data_limit * BITS_PER_UNIT ) return sdata_section ; return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Return a section for X . The only special thing we do here is to honor small data .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUB : return performSUBCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::SHL ISD::SUB


"value of %<-mfixed-range%> must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , MVT :: Other , MVT :: Glue ) ; SDValue Unused = DAG . getNode ( SystemZISD :: STRCMP , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( 0 , MVT :: i32 ) ) ; Chain = Unused . getValue ( 1 ) ; SDValue Glue = Chain . getValue ( 2 ) ; return std :: make_pair ( addIPMSequence ( DL , Glue , DAG ) , Chain ) ; } </s>

Emit target-specific code that performs a strcmp , in cases where that is faster than a libcall .


<s> void mips_expand_vec_minmax ( rtx target , rtx op0 , rtx op1 , rtx ( * cmp ) ( rtx , rtx , rtx ) , bool min_p ) { machine_mode vmode = GET_MODE ( target ) ; rtx tc , t0 , t1 , x ; tc = gen_reg_rtx ( vmode ) ; t0 = gen_reg_rtx ( vmode ) ; t1 = gen_reg_rtx ( vmode ) ; emit_insn ( cmp ( tc , op0 , op1 ) ) ; x = gen_rtx_AND ( vmode , tc , ( min_p ? op1 : op0 ) ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_NOT ( vmode , tc ) ; x = gen_rtx_AND ( vmode , x , ( min_p ? op0 : op1 ) ) ; emit_insn ( gen_rtx_SET ( t1 , x ) ) ; x = gen_rtx_IOR ( vmode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; } </s>


<s> static const char * fp_const_from_val ( REAL_VALUE_TYPE * r ) { int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; for ( i = 0 ; i < 8 ; i ++ ) if ( REAL_VALUES_EQUAL ( * r , values_fp [ i ] ) ) return strings_fp [ i ] ; gcc_unreachable ( ) ; } </s>

As for fp_immediate_constant , but value is passed directly , not in rtx .


<s>
const
uint32_t
*
DCPU16RegisterInfo
::
getCallPreservedMask
(
CallingConv
::
ID
CallConv
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
CSR_DCPU16_RegMask
;
}
}
</s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCContext & Context = MCA . getContext ( ) ; MCStreamer & OS = getStreamer ( ) ; const MCObjectFileInfo & OFI = * Context . getObjectFileInfo ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; uint64_t Features = STI . getFeatureBits ( ) ; MCSectionData & TextSectionData = MCA . getOrCreateSectionData ( * OFI . getTextSection ( ) ) ; MCSectionData & DataSectionData = MCA . getOrCreateSectionData ( * OFI . getDataSection ( ) ) ; MCSectionData & BSSSectionData = MCA . getOrCreateSectionData ( * OFI . getBSSSection ( ) ) ; TextSectionData . setAlignment ( std :: max ( 16u , TextSectionData . getAlignment ( ) ) ) ; DataSectionData . setAlignment ( std :: max ( 16u , DataSectionData . getAlignment ( ) ) ) ; BSSSectionData . setAlignment ( std :: max ( 16u , BSSSectionData . getAlignment ( ) ) ) ; if ( T . isArch64Bit ( ) && ( Features & Mips :: FeatureN64 ) ) { const MCSectionELF * Sec = Context . getELFSection ( ".MIPS.options" , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) , 1 , "" ) ; MCA . getOrCreateSectionData ( * Sec ) . setAlignment ( 8 ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 1 , 1 ) ; OS . EmitIntValue ( 40 , 1 ) ; OS . EmitIntValue ( 0 , 2 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 8 ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( ".reginfo" , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) , 24 , "" ) ; MCA . getOrCreateSectionData ( * Sec ) . setAlignment ( Features & Mips :: FeatureN32 ? 8 : 4 ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; } emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> const X86InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> void AArch64TargetStreamer :: emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( char & C : Buffer ) { C = uint8_t ( Inst ) ; Inst >>= 8 ; } getStreamer ( ) . emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


"unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n"

"unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n"

"PIC code generation is not supported in the portable runtime model\n"

"PIC code generation is not compatible with fast indirect calls\n"

"-g is only supported when using GAS on this processor,"

Set global variables as needed for the options enabled .


<s> void X86FrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = 0 ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? X86 :: MOV64ri : X86 :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( isSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> void setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI ) ; MIB . setMF ( MF ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; processPHIs ( MF ) ; } </s>


<s> bool MipsFastISel :: fastSelectInstruction ( const Instruction * I ) { if ( ! TargetSupported ) return false ; switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPToSI : return selectFPToInt ( I , true ) ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ICmp : case Instruction :: FCmp : return selectCmp ( I ) ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> static struct machine_function * arm_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> func_type = ARM_FT_UNKNOWN ; machine -> static_chain_stack_bytes = - 1 ; machine -> pacspval_needed = 0 ; return machine ; } </s>

Functions to save and restore machine-specific function data .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { if ( ! Subtarget -> useReciprocalEst ( ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; if ( ( Subtarget -> hasSSE1 ( ) && ( VT == MVT :: f32 || VT == MVT :: v4f32 ) ) || ( Subtarget -> hasAVX ( ) && VT == MVT :: v8f32 ) ) { RefinementSteps = ReciprocalEstimateRefinementSteps ; return DCI . DAG . getNode ( X86ISD :: FRCP , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> int mem_min_alignment ( rtx mem , int desired ) { rtx addr , base , offset ; if ( GET_CODE ( mem ) != MEM ) return 0 ; if ( ! TARGET_UNALIGNED_DOUBLES && MEM_ALIGN ( mem ) / BITS_PER_UNIT >= ( unsigned ) desired ) return 1 ; addr = XEXP ( mem , 0 ) ; base = offset = NULL_RTX ; if ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) { base = XEXP ( addr , 0 ) ; if ( GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT ) offset = XEXP ( addr , 1 ) ; else offset = const0_rtx ; } } else if ( GET_CODE ( addr ) == REG ) { base = addr ; offset = const0_rtx ; } if ( base != NULL_RTX ) { int regno = REGNO ( base ) ; if ( regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM ) { if ( ( ( cfun != 0 && REGNO_POINTER_ALIGN ( regno ) >= desired * BITS_PER_UNIT ) || ( optimize && reload_completed ) ) && ( INTVAL ( offset ) & ( desired - 1 ) ) == 0 ) return 1 ; } else { if ( ( ( INTVAL ( offset ) - SPARC_STACK_BIAS ) & ( desired - 1 ) ) == 0 ) return 1 ; } } else if ( ! TARGET_UNALIGNED_DOUBLES || CONSTANT_P ( addr ) || GET_CODE ( addr ) == LO_SUM ) { return 1 ; } return 0 ; } </s>

Return 1 if RTX is a MEM which is known to be aligned to at least a DESIRED byte boundary .


<s> bool toc_hasher :: equal ( toc_hash_struct * h1 , toc_hash_struct * h2 ) { rtx r1 = h1 -> key ; rtx r2 = h2 -> key ; if ( h1 -> key_mode != h2 -> key_mode ) return 0 ; return rtx_equal_p ( r1 , r2 ) ; } </s>


<s> static void build_sv_uint_offset ( function_builder & b , const char * signature , const function_group_info & group ) { build_32_64 ( b , signature , group , MODE_none , MODE_s64offset ) ; build_32_64 ( b , signature , group , MODE_u32offset , MODE_u64offset ) ; } </s>

Like build_sv_offset , but exclude offsets that must be interpreted as signed ( i.e . s32offset ) .