<s> static void sparc_emit_set_const64_longway ( rtx op0 , rtx temp , unsigned HOST_WIDE_INT high_bits , unsigned HOST_WIDE_INT low_bits ) { rtx sub_temp = op0 ; if ( can_create_pseudo_p ( ) ) sub_temp = gen_reg_rtx ( DImode ) ; if ( ( high_bits & 0xfffffc00 ) != 0 ) { emit_insn ( gen_safe_HIGH64 ( temp , high_bits ) ) ; if ( ( high_bits & ~ 0xfffffc00 ) != 0 ) emit_insn ( gen_rtx_SET ( VOIDmode , sub_temp , gen_safe_OR64 ( temp , ( high_bits & 0x3ff ) ) ) ) ; else sub_temp = temp ; } else { emit_insn ( gen_safe_SET64 ( temp , high_bits ) ) ; sub_temp = temp ; } if ( can_create_pseudo_p ( ) ) { rtx temp2 = gen_reg_rtx ( DImode ) ; rtx temp3 = gen_reg_rtx ( DImode ) ; rtx temp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp4 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( 32 ) ) ) ) ; emit_insn ( gen_safe_HIGH64 ( temp2 , low_bits ) ) ; if ( ( low_bits & ~ 0xfffffc00 ) != 0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , temp3 , gen_safe_OR64 ( temp2 , ( low_bits & 0x3ff ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp3 ) ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; } } else { rtx low1 = GEN_INT ( ( low_bits >> ( 32 - 12 ) ) & 0xfff ) ; rtx low2 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 ) ) & 0xfff ) ; rtx low3 = GEN_INT ( ( low_bits >> ( 32 - 12 - 12 - 8 ) ) & 0x0ff ) ; int to_shift = 12 ; if ( low1 != const0_rtx ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low1 ) ) ) ; sub_temp = op0 ; to_shift = 12 ; } else { to_shift += 12 ; } if ( low2 != const0_rtx ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low2 ) ) ) ; sub_temp = op0 ; to_shift = 8 ; } else { to_shift += 8 ; } emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , sub_temp , GEN_INT ( to_shift ) ) ) ) ; if ( low3 != const0_rtx ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( DImode , op0 , low3 ) ) ) ; } } </s>

Full 64-bit constant decomposition . Even though this is the 'worst ' case , we still optimize a few things away .


<s> static int rs6000_emit_p9_fp_minmax ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return 0 ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return 0 ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) ) max_p = ! max_p ; else return 0 ; rs6000_emit_minmax ( dest , max_p ? SMAX : SMIN , op0 , op1 ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) -> hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips "interrupt"


<s> unsigned MipsInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SW_P8 ) || ( Opc == Mips :: SD ) || ( Opc == Mips :: SD_P8 ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SWC1_P8 ) || ( Opc == Mips :: SDC1 ) || ( Opc == Mips :: SDC164 ) || ( Opc == Mips :: SDC164_P8 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


"Unexpected base pointer for inline asm memory operand."

"Unexpected offset for inline asm memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static int sh_register_move_cost ( machine_mode mode , reg_class_t srcclass , reg_class_t dstclass ) { if ( dstclass == T_REGS || dstclass == PR_REGS ) return 10 ; if ( dstclass == MAC_REGS && srcclass == MAC_REGS ) return 4 ; if ( mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD && REGCLASS_HAS_FP_REG ( srcclass ) && REGCLASS_HAS_FP_REG ( dstclass ) ) return 4 ; if ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == T_REGS ) return ( ( TARGET_HARD_SH4 && ! optimize_size ) ? 10 : 7 ) ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == MAC_REGS ) || ( dstclass == MAC_REGS && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return 9 ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( REGCLASS_HAS_GENERAL_REG ( dstclass ) && REGCLASS_HAS_FP_REG ( srcclass ) ) ) { int addend = ( mode == Pmode ) ? 40 : 0 ; return ( ( ( TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12 ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 5 ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return 7 ; if ( ( srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( ( dstclass ) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 20 ; if ( TARGET_SHMEDIA && ( ( srcclass ) == TARGET_REGS || ( srcclass ) == SIBCALL_REGS ) ) { if ( sh_gettrcost >= 0 ) return sh_gettrcost ; else if ( ! TARGET_PT_FIXED ) return 100 ; } if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 4 ; if ( TARGET_SHMEDIA || ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 2 * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; return 2 * ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4U ) ; } </s>

If SECONDARY * _RELOAD_CLASS says something about the src/dst pair , regclass uses this information . Hence , the general register < - > floating point register information here is not used for SFmode .


<s> void PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCPreEmitPeepholePass ( ) ) ; addPass ( createPPCExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) , false ) ; addPass ( createPPCBranchSelectionPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void X86WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; EmitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


<s>
unsigned
ARMBaseInstrInfo
::
getPartialRegUpdateClearance
(
const
MachineInstr
&
MI
,
unsigned
OpNum
,
const
TargetRegisterInfo
*
TRI
)
const
{
auto
PartialUpdateClearance
=
Subtarget
.
getPartialUpdateClearance
(
)
;
if
(
!
PartialUpdateClearance
)
return
0
;
assert
(
TRI
&&
"Need TRI instance"
)
;
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OpNum
)
;
if
(
MO
.
readsReg
(
)
)
return
0
;
Register
Reg
=
MO
.
getReg
(
)
;
int
UseOp
=
1
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VLDRS
:
case
ARM
::
FCONSTS
:
case
ARM
::
VMOVSR
:
case
ARM
::
VMOVv8i8
:
case
ARM
::
VMOVv4i16
:
case
ARM
::
VMOVv2i32
:
case
ARM
::
VMOVv2f32
:
case
ARM
::
VMOVv1i64
:
UseOp
=
MI
.
findRegisterUseOperandIdx
(
Reg
,
false
,
TRI
)
;
break
;
case
ARM
::
VLD1LNd32
:
UseOp
=
3
;
break
;
default
:
return
0
;
}
if
(
UseOp
!=
1
&&
MI
.
getOperand
(
UseOp
)
.
readsReg
(
)
)
return
0
;
if
(
Register
::
isVirtualRegister
(
Reg
)
)
{
if
(
!
MO
.
getSubReg
(
)
||
MI
.
readsVirtualRegister
(
Reg
)
)
return
0
;
}
else
if
(
ARM
::
SPRRegClass
.
contains
(
Reg
)
)
{
unsigned
DReg
=
TRI
->
getMatchingSuperReg
(
Reg
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DReg
||
!
MI
.
definesRegister
(
DReg
,
TRI
)
)
return
0
;
}
return
PartialUpdateClearance
;
}
</s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> bool mips_cannot_change_mode_class ( enum machine_mode from , enum machine_mode to , enum reg_class class ) { if ( MIN ( GET_MODE_SIZE ( from ) , GET_MODE_SIZE ( to ) ) <= UNITS_PER_WORD && MAX ( GET_MODE_SIZE ( from ) , GET_MODE_SIZE ( to ) ) > UNITS_PER_WORD ) { if ( TARGET_BIG_ENDIAN ) { if ( FP_INC > 1 && reg_classes_intersect_p ( FP_REGS , class ) ) return true ; } else { if ( reg_classes_intersect_p ( ACC_REGS , class ) ) return true ; } } if ( TARGET_FLOAT64 && from == SImode && GET_MODE_SIZE ( to ) >= UNITS_PER_WORD && reg_classes_intersect_p ( FP_REGS , class ) ) return true ; return false ; } </s>


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , LI -> getAlign ( ) , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; Register IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } uint32_t Hash = MI -> getPrototypeHash ( ) ; if ( Hash ) Result -> setPrototypeHash ( MI -> getPrototypeHash ( ) ) ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> void ix86_split_fp_branch ( enum rtx_code code , rtx op1 , rtx op2 , rtx target1 , rtx target2 , rtx tmp , rtx pushed ) { rtx second , bypass ; rtx label = NULL_RTX ; rtx condition ; int bypass_probability = - 1 , second_probability = - 1 , probability = - 1 ; rtx i ; if ( target2 != pc_rtx ) { rtx tmp = target2 ; code = reverse_condition_maybe_unordered ( code ) ; target2 = target1 ; target1 = tmp ; } condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp , & second , & bypass ) ; if ( pushed ) ix86_free_from_memory ( GET_MODE ( pushed ) ) ; if ( split_branch_probability >= 0 ) { probability = split_branch_probability ; if ( bypass ) bypass_probability = 1 ; if ( second ) second_probability = 1 ; } if ( bypass != NULL_RTX ) { label = gen_label_rtx ( ) ; i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , bypass , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; if ( bypass_probability >= 0 ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( bypass_probability ) , REG_NOTES ( i ) ) ; } i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ; if ( probability >= 0 ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( probability ) , REG_NOTES ( i ) ) ; if ( second != NULL_RTX ) { i = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , second , target1 , target2 ) ) ) ; if ( second_probability >= 0 ) REG_NOTES ( i ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , GEN_INT ( second_probability ) , REG_NOTES ( i ) ) ; } if ( label != NULL_RTX ) emit_label ( label ) ; } </s>

Split branch based on floating point condition .


<s> bool aarch64_sve_ld1r_operand_p ( rtx op ) { struct aarch64_address_info addr ; scalar_mode mode ; return ( MEM_P ( op ) && is_a < scalar_mode > ( GET_MODE ( op ) , & mode ) && aarch64_classify_address ( & addr , XEXP ( op , 0 ) , mode , false ) && addr . type == ADDRESS_REG_IMM && offset_6bit_unsigned_scaled_p ( mode , addr . const_offset ) ) ; } </s>

Return true if OP is a valid MEM operand for an SVE LD1R instruction .


<s> int registers_ok_for_quad_peep ( rtx reg1 , rtx reg2 ) { if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return 0 ; if ( ! FP_REGNO_P ( REGNO ( reg1 ) ) || ! FP_REGNO_P ( REGNO ( reg2 ) ) ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) == REGNO ( reg2 ) - 1 making them candidates for lfq and stfq insns . Note reg1 and reg2 * must * be hard registers . To be sure we will abort if we are passed pseudo registers .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , AArch64 :: W18 ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void mark_swaps_for_removal ( swap_web_entry * insn_entry , unsigned int i ) { rtx insn = insn_entry [ i ] . insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; if ( insn_entry [ i ] . is_load ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; while ( link ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( use_insn ) ] . will_delete = 1 ; link = link -> next ; } } } else if ( insn_entry [ i ] . is_store ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REG ( use ) ) ; if ( ! VECTOR_MODE_P ( mode ) ) continue ; struct df_link * link = DF_REF_CHAIN ( use ) ; while ( link ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( def_insn ) ] . will_delete = 1 ; link = link -> next ; } } } } </s>

Mark the xxswapdi instructions associated with permuting loads and stores for removal . Note that we only flag them for deletion here , as there is a possibility of a swap being reached from multiple loads , etc .


<s> static void mips_swap_registers ( unsigned int i ) { int tmpi ; const char * tmps ; SWAP_INT ( fixed_regs [ i ] , fixed_regs [ i + 1 ] ) ; SWAP_INT ( call_used_regs [ i ] , call_used_regs [ i + 1 ] ) ; SWAP_STRING ( reg_names [ i ] , reg_names [ i + 1 ] ) ; } </s>

Swap the register information for registers I and I + 1 , which currently have the wrong endianness . Note that the registers ' fixedness and call-clobberedness might have been set on the command line .


Implements TARGET_ASM_FILE_START . Output the assembly header .


<s> static bool const_vector_equal_evenodd_p ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; int i , nunits = GET_MODE_NUNITS ( mode ) ; if ( GET_CODE ( op ) != CONST_VECTOR || nunits != CONST_VECTOR_NUNITS ( op ) ) return false ; for ( i = 0 ; i < nunits ; i += 2 ) if ( CONST_VECTOR_ELT ( op , i ) != CONST_VECTOR_ELT ( op , i + 1 ) ) return false ; return true ; } </s>

Helper function of ix86_expand_mul_widen_evenodd . Return true if op is CONST_VECTOR with all odd elements equal to their preceding element .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS ( ) ) { addPass ( new ReplaceFMULS ( getSparcTargetMachine ( ) ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( getSparcTargetMachine ( ) ) ) ; } } </s>

Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == Lanai :: LDW_RI ) if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
static
void
process_cfa_register
(
FILE
*
out_file
,
rtx
pat
,
bool
unwind
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
int
dest_regno
=
REGNO
(
dest
)
;
int
src_regno
;
if
(
src
==
pc_rtx
)
{
if
(
unwind
)
fprintf
(
out_file
,
"\t.save rp, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
return
;
}
src_regno
=
REGNO
(
src
)
;
switch
(
src_regno
)
{
case
PR_REG
(
0
)
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_pr
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save pr, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
break
;
case
AR_UNAT_REGNUM
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_unat
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.unat, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
break
;
case
AR_LC_REGNUM
:
gcc_assert
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_lc
]
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.lc, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

This function processes a SET pattern for REG_CFA_REGISTER .

ia64
"\t.save rp, r%d\n"
0
"\t.save pr, r%d\n"
"\t.save ar.unat, r%d\n"
"\t.save ar.lc, r%d\n"


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "min-legal-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "min-legal-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",min-legal-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
bool
PPCDarwinAsmPrinter
::
doInitialization
(
Module
&
M
)
{
static
const
char
*
const
CPUDirectives
[
]
=
{
""
,
"ppc"
,
"ppc601"
,
"ppc602"
,
"ppc603"
,
"ppc7400"
,
"ppc750"
,
"ppc970"
,
"ppc64"
}
;
unsigned
Directive
=
Subtarget
.
getDarwinDirective
(
)
;
if
(
Subtarget
.
isGigaProcessor
(
)
&&
Directive
<
PPC
::
DIR_970
)
Directive
=
PPC
::
DIR_970
;
if
(
Subtarget
.
hasAltivec
(
)
&&
Directive
<
PPC
::
DIR_7400
)
Directive
=
PPC
::
DIR_7400
;
if
(
Subtarget
.
isPPC64
(
)
&&
Directive
<
PPC
::
DIR_970
)
Directive
=
PPC
::
DIR_64
;
assert
(
Directive
<=
PPC
::
DIR_64
&&
"Directive out of range."
)
;
O
<<
"\t.machine "
<<
CPUDirectives
[
Directive
]
<<
'\n'
;
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
assert
(
MMI
)
;
TargetLoweringObjectFileMachO
&
TLOFMacho
=
static_cast
<
TargetLoweringObjectFileMachO
&
>
(
getObjFileLowering
(
)
)
;
OutStreamer
.
SwitchSection
(
TLOFMacho
.
getTextCoalSection
(
)
)
;
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
)
{
OutStreamer
.
SwitchSection
(
TLOFMacho
.
getMachOSection
(
"__TEXT"
,
"__picsymbolstub1"
,
MCSectionMachO
::
S_SYMBOL_STUBS
|
MCSectionMachO
::
S_ATTR_PURE_INSTRUCTIONS
,
32
,
SectionKind
::
getText
(
)
)
)
;
}
else
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
{
OutStreamer
.
SwitchSection
(
TLOFMacho
.
getMachOSection
(
"__TEXT"
,
"__symbol_stub1"
,
MCSectionMachO
::
S_SYMBOL_STUBS
|
MCSectionMachO
::
S_ATTR_PURE_INSTRUCTIONS
,
16
,
SectionKind
::
getText
(
)
)
)
;
}
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> int aarch64_ldrstr_offset_compare ( const void * x , const void * y ) { const rtx * operands_1 = ( const rtx * ) x ; const rtx * operands_2 = ( const rtx * ) y ; rtx mem_1 , mem_2 , base , offset_1 , offset_2 ; if ( MEM_P ( operands_1 [ 0 ] ) ) mem_1 = operands_1 [ 0 ] ; else mem_1 = operands_1 [ 1 ] ; if ( MEM_P ( operands_2 [ 0 ] ) ) mem_2 = operands_2 [ 0 ] ; else mem_2 = operands_2 [ 1 ] ; extract_base_offset_in_addr ( mem_1 , & base , & offset_1 ) ; extract_base_offset_in_addr ( mem_2 , & base , & offset_2 ) ; gcc_assert ( offset_1 != NULL_RTX && offset_2 != NULL_RTX ) ; return wi :: cmps ( INTVAL ( offset_1 ) , INTVAL ( offset_2 ) ) ; } </s>

Taking X and Y to be pairs of RTX , one pointing to a MEM rtx and the other pointing to a REG rtx containing an offset , compare the offsets of the two pairs . Return : 1 iff offset ( X ) > offset ( Y ) 0 iff offset ( X ) == offset ( Y ) -1 iff offset ( X ) < offset ( Y )


<s> static bool aarch64_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; machine_mode ag_mode ; int count ; if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != COMPLEX_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & ag_mode , & count , NULL ) ) return false ; size = int_size_in_bytes ( type ) ; return ( size < 0 || size > 2 * UNITS_PER_WORD ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY . If the type T of the result of a function is such that void func ( T arg ) would require that arg be passed as a value in a register ( or set of registers ) according to the parameter passing rules , then the result is returned in the same registers as would be used for such an argument .


<s> void X86AsmBackend :: emitInstructionBegin ( MCObjectStreamer & OS , const MCInst & Inst ) { CanPadInst = canPadInst ( Inst , OS ) ; if ( ! canPadBranches ( OS ) ) return ; if ( ! isMacroFused ( PrevInst , Inst ) ) PendingBA = nullptr ; if ( ! CanPadInst ) return ; if ( PendingBA && OS . getCurrentFragment ( ) -> getPrevNode ( ) == PendingBA ) { return ; } if ( needAlign ( Inst ) || ( ( AlignBranchType & X86 :: AlignBranchFused ) && isFirstMacroFusibleInst ( Inst , * MCII ) ) ) { OS . insert ( PendingBA = new MCBoundaryAlignFragment ( AlignBoundary ) ) ; } } </s>

Give the target a chance to manipulate state related to instruction alignment ( e.g .


<s> void VEInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { unsigned AltIdx = VE :: AsmName ; OS << '%' << getRegisterName ( RegNo , AltIdx ) ; } </s>


<s> static rtx_insn * loongarch_call_tls_get_addr ( rtx sym , enum loongarch_symbol_type type , rtx v0 ) { rtx loc , a0 ; rtx_insn * insn ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! loongarch_tls_symbol ) loongarch_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = loongarch_unspec_address ( sym , type ) ; start_sequence ( ) ; if ( type == SYMBOL_TLSLDM ) emit_insn ( loongarch_got_load_tls_ld ( a0 , loc ) ) ; else if ( type == SYMBOL_TLSGD ) emit_insn ( loongarch_got_load_tls_gd ( a0 , loc ) ) ; else gcc_unreachable ( ) ; insn = emit_call_insn ( gen_call_value_internal ( v0 , loongarch_tls_symbol , const0_rtx ) ) ; RTL_CONST_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Return an instruction sequence that calls __tls_get_addr . SYM is the TLS symbol we are referencing and TYPE is the symbol type to use ( either global dynamic or local dynamic ) . V0 is an RTX for the return value location .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } if ( IDVal == ".mips_hack_stocg" ) return parseDirectiveMipsHackStocg ( ) ; if ( IDVal == ".mips_hack_elf_flags" ) return parseDirectiveMipsHackELFFlags ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool Thumb1RegisterInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
bool
AArch64InstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
if
(
Cond
[
0
]
.
getImm
(
)
!=
1
)
{
AArch64CC
::
CondCode
CC
=
(
AArch64CC
::
CondCode
)
(
int
)
Cond
[
0
]
.
getImm
(
)
;
Cond
[
0
]
.
setImm
(
AArch64CC
::
getInvertedCondCode
(
CC
)
)
;
}
else
{
switch
(
Cond
[
1
]
.
getImm
(
)
)
{
default
:
llvm_unreachable
(
"Unknown conditional branch!"
)
;
case
AArch64
::
CBZW
:
Cond
[
1
]
.
setImm
(
AArch64
::
CBNZW
)
;
break
;
case
AArch64
::
CBNZW
:
Cond
[
1
]
.
setImm
(
AArch64
::
CBZW
)
;
break
;
case
AArch64
::
CBZX
:
Cond
[
1
]
.
setImm
(
AArch64
::
CBNZX
)
;
break
;
case
AArch64
::
CBNZX
:
Cond
[
1
]
.
setImm
(
AArch64
::
CBZX
)
;
break
;
case
AArch64
::
TBZW
:
Cond
[
1
]
.
setImm
(
AArch64
::
TBNZW
)
;
break
;
case
AArch64
::
TBNZW
:
Cond
[
1
]
.
setImm
(
AArch64
::
TBZW
)
;
break
;
case
AArch64
::
TBZX
:
Cond
[
1
]
.
setImm
(
AArch64
::
TBNZX
)
;
break
;
case
AArch64
::
TBNZX
:
Cond
[
1
]
.
setImm
(
AArch64
::
TBZX
)
;
break
;
}
}
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> virtual bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddrIdx ( Op , Op , Op0 , Op1 ) ) SelectAddrImm ( Op , Op , Op0 , Op1 ) ; break ; case 'o' : if ( ! SelectAddrImm ( Op , Op , Op0 , Op1 ) ) { Op0 = Op ; Op1 = getSmallIPtrImm ( 0 ) ; } break ; case 'v' : SelectAddrIdxOnly ( Op , Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void loongarch_expand_prologue ( void ) { struct loongarch_frame_info * frame = & cfun -> machine -> frame ; HOST_WIDE_INT size = frame -> total_size ; HOST_WIDE_INT tmp ; rtx insn ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) { tmp = size - get_stack_check_protect ( ) ; loongarch_emit_probe_stack_range ( get_stack_check_protect ( ) , tmp ) ; } } else if ( size > 0 ) loongarch_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( ( frame -> mask | frame -> fmask ) != 0 ) { HOST_WIDE_INT step1 = MIN ( size , loongarch_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; size -= step1 ; loongarch_for_each_saved_reg ( size , loongarch_save_reg ) ; } if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; loongarch_emit_stack_tie ( ) ; } if ( size > 0 ) { if ( IMM12_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; } else { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , LARCH_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; loongarch_set_frame_expr ( insn ) ; } } } </s>


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && MI -> isCompare ( ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareAndBranch ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> removeFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; CompleteCCUsers = true ; continue ; } Reference CCRefs ( getRegReferences ( MI , SystemZ :: CC ) ) ; if ( CCRefs . Def ) { CCUsers . clear ( ) ; CompleteCCUsers = ! CCRefs . IndirectDef ; } if ( CompleteCCUsers && CCRefs . Use ) CCUsers . push_back ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static rtx_insn * vax_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , VAX_PSL_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , VAX_PSL_REGNUM ) ; return NULL ; } </s>

Mark PSL as clobbered for compatibility with the CC0 representation .


<s> uint64_t AArch64PLT :: emit ( MemoryRegion & pRegion ) { uint64_t result = 0x0 ; iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < AArch64PLT0 > ( ( * it ) ) . getValue ( ) , AArch64PLT0 :: EntrySize ) ; result += AArch64PLT0 :: EntrySize ; ++ it ; AArch64PLT1 * plt1 = NULL ; AArch64PLT :: iterator ie = end ( ) ; while ( it != ie ) { plt1 = & ( llvm :: cast < AArch64PLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , AArch64PLT1 :: EntrySize ) ; result += AArch64PLT1 :: EntrySize ; ++ it ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> const AArch64AuthMCExpr * AArch64AuthMCExpr :: create ( const MCExpr * Expr , uint16_t Discriminator , AArch64PACKey :: ID Key , bool HasAddressDiversity , MCContext & Ctx ) { return new ( Ctx ) AArch64AuthMCExpr ( Expr , Discriminator , Key , HasAddressDiversity ) ; } </s>


<s> bool PPCInstrInfo :: getMemOperandsWithOffsetWidth ( const MachineInstr & LdSt , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable , unsigned & Width , const TargetRegisterInfo * TRI ) const { const MachineOperand * BaseOp ; OffsetIsScalable = false ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true ; } </s>

Get zero or more base operands and the byte offset of an instruction that reads/writes memory .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips PseudoInstrs Expansion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> bool PPCTTIImpl :: isHardwareLoopProfitable ( Loop * L , ScalarEvolution & SE , AssumptionCache & AC , TargetLibraryInfo * LibInfo , HardwareLoopInfo & HWLoopInfo ) { const PPCTargetMachine & TM = ST -> getTargetMachine ( ) ; TargetSchedModel SchedModel ; SchedModel . init ( ST ) ; unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , 32 > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( 6 * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo ) ) return false ; SmallVector < BasicBlock * , 4 > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = 0 , FalseWeight = 0 ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( 0 ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . isPPC64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , 1 ) ; return true ; } </s>

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> static void vector_init_fpmerge ( rtx target , rtx elt ) { rtx t1 , t2 , t2_low , t3 , t3_low ; t1 = gen_reg_rtx ( V4QImode ) ; elt = convert_modes ( SImode , QImode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; t2 = gen_reg_rtx ( V8QImode ) ; t2_low = gen_lowpart ( V4QImode , t2 ) ; emit_insn ( gen_fpmerge_vis ( t2 , t1 , t1 ) ) ; t3 = gen_reg_rtx ( V8QImode ) ; t3_low = gen_lowpart ( V4QImode , t3 ) ; emit_insn ( gen_fpmerge_vis ( t3 , t2_low , t2_low ) ) ; emit_insn ( gen_fpmerge_vis ( target , t3_low , t3_low ) ) ; } </s>

Subroutine of sparc_expand_vector_init . Emit code to initialize all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn .


<s> bool ARMIndirectThunks :: doInitialization ( Module & M ) { initTIs ( M , TIs ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool targetSchedulesPostRAScheduling ( ) const override { return true ; } </s>

True if subtarget inserts the final scheduling pass on its own .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
llvm_unreachable
(
"getFixupKindInfo() unimplemented"
)
;
}
</s>


<s>
__inline__
static
unsigned
long
long
sh_media_LDHI_L
(
void
*
p
,
int
s
)
{
unsigned
long
long
res
;
__asm__
(
"ldhi.l	%m1, %0"
:
"=r"
(
res
)
:
"o"
(
(
(
char
*
)
p
)
[
s
]
)
)
;
return
res
;
}
</s>


<s> static void pa_output_function_epilogue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { rtx insn = get_last_insn ( ) ; last_address = 0 ; if ( GET_CODE ( insn ) == NOTE ) insn = prev_real_insn ( insn ) ; if ( insn && GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ; if ( insn && GET_CODE ( insn ) == CALL_INSN ) { fputs ( "\tnop\n" , file ) ; last_address += 4 ; } fputs ( "\t.EXIT\n\t.PROCEND\n" , file ) ; if ( TARGET_SOM && TARGET_GAS ) { forget_section ( ) ; } if ( INSN_ADDRESSES_SET_P ( ) ) { insn = get_last_nonnote_insn ( ) ; last_address += INSN_ADDRESSES ( INSN_UID ( insn ) ) ; if ( INSN_P ( insn ) ) last_address += insn_default_length ( insn ) ; last_address = ( ( last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1 ) & ~ ( FUNCTION_BOUNDARY / BITS_PER_UNIT - 1 ) ) ; } update_total_code_bytes ( last_address ) ; } </s>

This function generates the assembly code for function exit . Args are as for output_function_prologue ( ) . The function epilogue should not depend on the current stack pointer ! It should use the frame pointer only . This is mandatory because of alloca ; we also take advantage of it to omit stack adjustments before returning .


<s> static int function_arg_slotno ( const struct sparc_args * cum , machine_mode mode , const_tree type , bool named , bool incoming , int * pregno , int * ppadding ) { int regbase = ( incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = 0 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != 0 ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) slotno ++ , * ppadding = 1 ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) != RECORD_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } else { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { classify_data_t data = { false , false , false } ; traverse_record_type < classify_data_t , classify_registers > ( type , named , & data ) ; if ( data . fp_regs && ! data . fp_regs_in_first_word && slotno >= SPARC_FP_ARG_MAX - 1 ) return - 1 ; if ( ! data . fp_regs && data . int_regs && slotno >= SPARC_INT_ARG_MAX ) return - 1 ; } return slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
.
getEncodingValue
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> rtx mmix_eh_return_handler_rtx ( ) { return gen_rtx_REG ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ; } </s>


<s> bool ARMInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ARM :: tPUSH ) ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , false , false , true ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool X86Subtarget :: isLegalToCallImmediateAddr ( ) const { if ( Is64Bit || isTargetWin32 ( ) ) return false ; return isTargetELF ( ) || TM . getRelocationModel ( ) == Reloc :: Static ; } </s>

Return true if the subtarget allows calls to immediate address .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsResolved
,
Ctx
,
STI
)
;
if
(
!
Value
)
return
;
const
unsigned
NumBytes
=
getFixupKindNumBytes
(
Kind
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
Endian
==
support
::
big
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Kind
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned AArch64AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { AArch64Operand & Op = static_cast < AArch64Operand & > ( AsmOp ) ; int64_t ExpectedVal ; switch ( Kind ) { default : return Match_InvalidOperand ; case MCK__35_0 : ExpectedVal = 0 ; break ; case MCK__35_1 : ExpectedVal = 1 ; break ; case MCK__35_12 : ExpectedVal = 12 ; break ; case MCK__35_16 : ExpectedVal = 16 ; break ; case MCK__35_2 : ExpectedVal = 2 ; break ; case MCK__35_24 : ExpectedVal = 24 ; break ; case MCK__35_3 : ExpectedVal = 3 ; break ; case MCK__35_32 : ExpectedVal = 32 ; break ; case MCK__35_4 : ExpectedVal = 4 ; break ; case MCK__35_48 : ExpectedVal = 48 ; break ; case MCK__35_6 : ExpectedVal = 6 ; break ; case MCK__35_64 : ExpectedVal = 64 ; break ; case MCK__35_8 : ExpectedVal = 8 ; break ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static const char * shift_op ( rtx op , HOST_WIDE_INT * amountp ) { const char * mnem ; enum rtx_code code = GET_CODE ( op ) ; switch ( GET_CODE ( XEXP ( op , 1 ) ) ) { case REG : case SUBREG : * amountp = - 1 ; break ; case CONST_INT : * amountp = INTVAL ( XEXP ( op , 1 ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFT : mnem = "asl" ; break ; case ASHIFTRT : mnem = "asr" ; break ; case LSHIFTRT : mnem = "lsr" ; break ; case ROTATE : gcc_assert ( * amountp != - 1 ) ; * amountp = 32 - * amountp ; case ROTATERT : mnem = "ror" ; break ; case MULT : gcc_assert ( * amountp != - 1 ) ; * amountp = int_log2 ( * amountp ) ; return "asl" ; default : gcc_unreachable ( ) ; } if ( * amountp != - 1 ) { if ( code == ROTATERT ) * amountp &= 31 ; else if ( * amountp != ( * amountp & 31 ) ) { if ( code == ASHIFT ) mnem = "lsr" ; * amountp = 32 ; } if ( * amountp == 0 ) return NULL ; } return mnem ; } </s>

Ensure valid constant shifts and return the appropriate shift mnemonic for the operation code . The returned result should not be overwritten . OP is the rtx code of the shift . On exit , * AMOUNTP will be -1 if the shift is by a register , or a constant shift .


<s> static unsigned bit_count ( unsigned long value ) { unsigned long count = 0 ; while ( value ) { count ++ ; value &= value - 1 ; } return count ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - CHILD |ret | return address -- | | \ | | call saved | | registers | | / -- | | \ | | local | | variables frame pointer - > | | / -- | | \ | | outgoing | Decreasing | | arguments | addresses current stack pointer - > | | / | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V | |


<s> static unsigned arm_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = arm_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost [ where ] += retval ; } return retval ; } </s>


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const ARMSubtarget & ARMMCInstLower :: getSubtarget ( ) const { return AsmPrinter . getSubtarget ( ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> rtx ix86_build_const_vector ( machine_mode mode , bool vect , rtx value ) { int i , n_elt ; rtvec v ; machine_mode scalar_mode ; switch ( mode ) { case E_V64QImode : case E_V32QImode : case E_V16QImode : case E_V32HImode : case E_V16HImode : case E_V8HImode : case E_V16SImode : case E_V8SImode : case E_V4SImode : case E_V8DImode : case E_V4DImode : case E_V2DImode : gcc_assert ( vect ) ; case E_V16SFmode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : n_elt = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( n_elt ) ; scalar_mode = GET_MODE_INNER ( mode ) ; RTVEC_ELT ( v , 0 ) = value ; for ( i = 1 ; i < n_elt ; ++ i ) RTVEC_ELT ( v , i ) = vect ? value : CONST0_RTX ( scalar_mode ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; default : gcc_unreachable ( ) ; } } </s>

A subroutine of ix86_build_signbit_mask . If VECT is true , then replicate the value for all elements of the vector register .


<s> static bool ix86_in_large_data_p ( tree exp ) { if ( ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && ! is_global_var ( exp ) ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , ".ldata" ) == 0 || strcmp ( section , ".lbss" ) == 0 ) return true ; return false ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( size <= 0 || size > ix86_section_threshold ) return true ; } return false ; } </s>

Return true if this goes in small data/bss .


<s>
const
char
*
vax_output_conditional_branch
(
enum
rtx_code
code
)
{
switch
(
code
)
{
case
EQ
:
return
"jeql %l0"
;
case
NE
:
return
"jneq %l0"
;
case
GT
:
return
"jgtr %l0"
;
case
LT
:
return
"jlss %l0"
;
case
GTU
:
return
"jgtru %l0"
;
case
LTU
:
return
"jlssu %l0"
;
case
GE
:
return
"jgeq %l0"
;
case
LE
:
return
"jleq %l0"
;
case
GEU
:
return
"jgequ %l0"
;
case
LEU
:
return
"jlequ %l0"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

vax
"jeql %l0"
"jneq %l0"
"jgtr %l0"
"jlss %l0"
"jgtru %l0"
"jlssu %l0"
"jgeq %l0"
"jleq %l0"
"jgequ %l0"
"jlequ %l0"


"Unexpected number of bits in the mask!"

Returns true if at least one of the register writes performed by .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , MVT :: Other , MVT :: Glue ) ; SDValue Unused = DAG . getNode ( SystemZISD :: STRCMP , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; Chain = Unused . getValue ( 1 ) ; SDValue Glue = Chain . getValue ( 2 ) ; return std :: make_pair ( addIPMSequence ( DL , Glue , DAG ) , Chain ) ; } </s>

Emit target-specific code that performs a strcmp , in cases where that is faster than a libcall .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function & F = MF -> getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F . getCallingConv ( ) == CallingConv :: CFGuard_Check ) { return CSR_Win_AAPCS_CFGuard_Check_SaveList ; } else if ( F . hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F . getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


<s>
MachineBasicBlock
::
iterator
AArch64InstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
outliner
::
Candidate
&
C
)
const
{
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
TCRETURNdi
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
.
addImm
(
0
)
)
;
return
It
;
}
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
return
It
;
}
MachineBasicBlock
::
iterator
CallPt
;
MachineInstr
*
Save
;
MachineInstr
*
Restore
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
Register
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
&&
"No callee-saved register available?"
)
;
if
(
!
MBB
.
isLiveIn
(
AArch64
::
LR
)
)
MBB
.
addLiveIn
(
AArch64
::
LR
)
;
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
Reg
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
AArch64
::
LR
)
.
addImm
(
0
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
ORRXrs
)
,
AArch64
::
LR
)
.
addReg
(
AArch64
::
XZR
)
.
addReg
(
Reg
)
.
addImm
(
0
)
;
}
else
{
Save
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
STRXpre
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
Restore
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
LDRXpost
)
)
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
16
)
;
}
It
=
MBB
.
insert
(
It
,
Save
)
;
It
++
;
It
=
MBB
.
insert
(
It
,
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
AArch64
::
BL
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
)
;
CallPt
=
It
;
It
++
;
It
=
MBB
.
insert
(
It
,
Restore
)
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .


<s> MachineInstr * SystemZInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 LEA Optimize"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void ix86_expand_floorceildf_32 ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; one = force_reg ( mode , const_double_from_real_value ( do_floor ? dconst1 : dconstm1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


<s>
bool
sh_symbian_dllexport_p
(
tree
decl
)
{
tree
exp
;
if
(
TREE_CODE
(
decl
)
!=
VAR_DECL
&&
TREE_CODE
(
decl
)
!=
FUNCTION_DECL
)
return
false
;
exp
=
lookup_attribute
(
"dllexport"
,
DECL_ATTRIBUTES
(
decl
)
)
;
if
(
exp
==
)
{
tree
class
=
sh_symbian_associated_type
(
decl
)
;
if
(
class
)
exp
=
lookup_attribute
(
"dllexport"
,
TYPE_ATTRIBUTES
(
class
)
)
;
}
if
(
exp
)
{
print_node_brief
(
stderr
,
"dllexport:"
,
decl
,
0
)
;
fprintf
(
stderr
,
"\n"
)
;
}
else
if
(
TREE_CODE
(
decl
)
!=
FUNCTION_DECL
)
{
print_node_brief
(
stderr
,
"no dllexport:"
,
decl
,
0
)
;
fprintf
(
stderr
,
"\n"
)
;
}
return
exp
true
:
false
;
}
</s>

Return nonzero if DECL is a dllexport 'd object .

sh
"dllexport"
"dllexport"
"dllexport:"
0
"\n"
"no dllexport:"
0
"\n"


<s>
static
void
build_mips16_function_stub
(
FILE
*
file
)
{
const
char
*
fnname
;
char
*
secname
,
*
stubname
;
tree
stubid
,
stubdecl
;
int
need_comma
;
unsigned
int
f
;
fnname
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
secname
=
(
char
*
)
alloca
(
strlen
(
fnname
)
+
20
)
;
sprintf
(
secname
,
".mips16.fn.%s"
,
fnname
)
;
stubname
=
(
char
*
)
alloca
(
strlen
(
fnname
)
+
20
)
;
sprintf
(
stubname
,
"__fn_stub_%s"
,
fnname
)
;
stubid
=
get_identifier
(
stubname
)
;
stubdecl
=
build_decl
(
FUNCTION_DECL
,
stubid
,
build_function_type
(
void_type_node
,
NULL_TREE
)
)
;
DECL_SECTION_NAME
(
stubdecl
)
=
build_string
(
strlen
(
secname
)
,
secname
)
;
fprintf
(
file
,
"\t# Stub function for %s ("
,
current_function_name
(
)
)
;
need_comma
=
0
;
for
(
f
=
(
unsigned
int
)
current_function_args_info
.
fp_code
;
f
!=
0
;
f
>>=
2
)
{
fprintf
(
file
,
"%s%s"
,
need_comma
", "
:
""
,
(
f
&
3
)
==
1
"float"
:
"double"
)
;
need_comma
=
1
;
}
fprintf
(
file
,
")\n"
)
;
fprintf
(
file
,
"\t.set\tnomips16\n"
)
;
function_section
(
stubdecl
)
;
ASM_OUTPUT_ALIGN
(
file
,
floor_log2
(
FUNCTION_BOUNDARY
/
BITS_PER_UNIT
)
)
;
if
(
!
FUNCTION_NAME_ALREADY_DECLARED
)
{
fputs
(
"\t.ent\t"
,
file
)
;
assemble_name
(
file
,
stubname
)
;
fputs
(
"\n"
,
file
)
;
}
assemble_name
(
file
,
stubname
)
;
fputs
(
":\n"
,
file
)
;
fprintf
(
file
,
"\t.set\tnoreorder\n"
)
;
mips16_fp_args
(
file
,
current_function_args_info
.
fp_code
,
1
)
;
fprintf
(
asm_out_file
,
"\t.set\tnoat\n"
)
;
fprintf
(
asm_out_file
,
"\tla\t%s,"
,
reg_names
[
GP_REG_FIRST
+
1
]
)
;
assemble_name
(
file
,
fnname
)
;
fprintf
(
file
,
"\n"
)
;
fprintf
(
asm_out_file
,
"\tjr\t%s\n"
,
reg_names
[
GP_REG_FIRST
+
1
]
)
;
fprintf
(
asm_out_file
,
"\t.set\tat\n"
)
;
fprintf
(
file
,
"\tnop\n"
)
;
fprintf
(
file
,
"\t.set\treorder\n"
)
;
if
(
!
FUNCTION_NAME_ALREADY_DECLARED
)
{
fputs
(
"\t.end\t"
,
file
)
;
assemble_name
(
file
,
stubname
)
;
fputs
(
"\n"
,
file
)
;
}
fprintf
(
file
,
"\t.set\tmips16\n"
)
;
function_section
(
current_function_decl
)
;
}
</s>

Build a mips16 function stub . This is used for functions which take arguments in the floating point registers . It is 32 bit code that moves the floating point args into the general registers , and then jumps to the 16 bit code .


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


<s> bool LC2200AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize ; } </s>

Return the maximum size of a call frame that must be allocated for an outgoing function call .


<s> virtual const AZPRInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool isLegalMaskedStore ( Type * DataTy , MaybeAlign Alignment ) { return isLegalMaskedLoad ( DataTy , Alignment ) ; } </s>

Return true if the target supports masked store .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
MipsMnemonicSpellCheck
(
Name
,
FBS
)
;
return
Error
(
NameLoc
,
"unknown instruction"
+
Suggestion
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
Mips
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> static void ix86_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned int ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = 1u << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( ix86_tune , false ) ; } </s>


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
k_Register
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> bool mem_operand_ds_form ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset , extra ) ; } </s>

As above , but for DS-FORM VSX insns . Unlike mem_operand_gpr , enforce an offset divisible by 4 even for 32-bit .


<s> rtx extract_branch_target_rtx ( rtx_insn * insn ) { gcc_assert ( CALL_P ( insn ) || JUMP_P ( insn ) ) ; rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { if ( GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE ) return NULL_RTX ; return SET_SRC ( body ) ; } if ( GET_CODE ( body ) == CALL ) return XEXP ( body , 0 ) ; if ( GET_CODE ( body ) == PARALLEL ) { rtx first_rtx = parallel_element ( body , 0 ) ; if ( GET_CODE ( first_rtx ) == SET ) return SET_SRC ( first_rtx ) ; if ( GET_CODE ( first_rtx ) == CALL ) return XEXP ( first_rtx , 0 ) ; } if ( GET_CODE ( body ) == COND_EXEC ) { rtx addr_rtx = XEXP ( body , 1 ) ; if ( GET_CODE ( addr_rtx ) == SET ) return SET_SRC ( addr_rtx ) ; if ( GET_CODE ( addr_rtx ) == PARALLEL ) { rtx first_rtx = parallel_element ( addr_rtx , 0 ) ; if ( GET_CODE ( first_rtx ) == SET ) { rtx call_rtx = SET_SRC ( first_rtx ) ; gcc_assert ( GET_CODE ( call_rtx ) == CALL ) ; return XEXP ( call_rtx , 0 ) ; } if ( GET_CODE ( first_rtx ) == CALL ) return XEXP ( first_rtx , 0 ) ; } } gcc_unreachable ( ) ; } </s>

Extract the rtx representing the branch target to help recognize data hazards .


<s> bool X86InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> bool ARMTargetLowering :: shouldInsertFencesForAtomic ( const Instruction * I ) const { return InsertFencesForAtomic ; } </s>

Helper functions for atomic operations .


Write an ( optimal ) nop sequence of Count bytes to the given output .


"\tnop // between mem op and mult-accumulate\n"


Return an array that contains the direct target flag values and their names .

Mips Mips Mips "mips-got" "mips-got-call" "mips-gprel" "mips-abs-hi" "mips-abs-lo" "mips-tlsgd" "mips-tlsldm" "mips-dtprel-hi" "mips-dtprel-lo" "mips-gottprel" "mips-tprel-hi" "mips-tprel-lo" "mips-gpoff-hi" "mips-gpoff-lo" "mips-got-disp" "mips-got-page" "mips-got-ofst" "mips-higher" "mips-highest" "mips-got-hi16" "mips-got-lo16" "mips-call-hi16" "mips-call-lo16"


<s>
const
ArrayRef
<
MCPhysReg
>
Cpu0ABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsS32
(
)
)
return
makeArrayRef
(
S32IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static rtx sparc_struct_value_rtx ( tree fndecl , int incoming ) { if ( TARGET_ARCH64 ) return 0 ; else { rtx mem ; if ( incoming ) mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; if ( incoming == 2 && sparc_std_struct_return && TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) && TREE_CODE ( TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ) == INTEGER_CST ) { rtx ret_reg = gen_rtx_REG ( Pmode , 31 ) ; rtx scratch = gen_reg_rtx ( SImode ) ; rtx_code_label * endlab = gen_label_rtx ( ) ; tree size = TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ; rtx size_rtx = GEN_INT ( TREE_INT_CST_LOW ( size ) & 0xfff ) ; rtx temp_val = assign_stack_local ( Pmode , TREE_INT_CST_LOW ( size ) , 0 ) ; emit_move_insn ( scratch , gen_rtx_MEM ( SImode , plus_constant ( Pmode , ret_reg , 8 ) ) ) ; emit_insn ( gen_add3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_cmp_and_jump_insns ( scratch , size_rtx , EQ , const0_rtx , SImode , 0 , endlab ) ; emit_insn ( gen_sub3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_move_insn ( mem , XEXP ( temp_val , 0 ) ) ; emit_label ( endlab ) ; } return mem ; } } </s>

Handle the TARGET_STRUCT_VALUE target hook . Return where to find the structure return value address .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getTargetData
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s> Optional < MCFixupKind > ELFPPCAsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . isOSBinFormatELF ( ) ) { unsigned Type ; if ( TT . isPPC64 ( ) ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_PPC64_NONE ) . Case ( "BFD_RELOC_16" , ELF :: R_PPC64_ADDR16 ) . Case ( "BFD_RELOC_32" , ELF :: R_PPC64_ADDR32 ) . Case ( "BFD_RELOC_64" , ELF :: R_PPC64_ADDR64 ) . Default ( - 1u ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_PPC_NONE ) . Case ( "BFD_RELOC_16" , ELF :: R_PPC_ADDR16 ) . Case ( "BFD_RELOC_32" , ELF :: R_PPC_ADDR32 ) . Default ( - 1u ) ; } if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool PPCTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! VT . isSimple ( ) || ! Subtarget . hasVSX ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: f32 : case MVT :: f64 : if ( Subtarget . hasPrefixInstrs ( ) ) { return true ; } LLVM_FALLTHROUGH ; case MVT :: ppcf128 : return Imm . isPosZero ( ) ; } } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static void sparc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno , padding ; function_arg_slotno ( cum , mode , type , named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += ( mode == BLKmode ? CEIL_NWORDS ( int_size_in_bytes ( type ) ) : CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ) ; else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size <= 8 ) ++ cum -> words ; else if ( size <= 16 ) cum -> words += 2 ; else ++ cum -> words ; } else cum -> words += ( mode == BLKmode ? CEIL_NWORDS ( int_size_in_bytes ( type ) ) : CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ) ; } } </s>

Handle the TARGET_FUNCTION_ARG_ADVANCE hook . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> static bool rs6000_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { return rs6000_mode_dependent_address_ptr ( addr ) ; } </s>


<s> Optional < DestSourcePair > AArch64InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == AArch64 :: ORRWrs && MI . getOperand ( 1 ) . getReg ( ) == AArch64 :: WZR && MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; } if ( MI . getOpcode ( ) == AArch64 :: ORRXrs && MI . getOperand ( 1 ) . getReg ( ) == AArch64 :: XZR && MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; } return None ; } </s>


<s> bool ARMTargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget -> hasV6T2Ops ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


This is just a placeholder to make linking work without having to add this to the generic Darwin EXTRA_SECTIONS . If -mcall-aix is ever needed for Darwin ( not too likely ! ) this would have to get a real definition .


<s> bool X86FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static inline bool offset_9bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , - 256 , 255 ) ) ; } </s>

Return true if OFFSET is a signed 9-bit value multiplied by the size of MODE .


<s> static void pa_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int arg_size = pa_function_arg_size ( mode , type ) ; cum -> nargs_prototype -- ; cum -> words += ( arg_size + ( ( cum -> words & 01 ) && type != NULL_TREE && arg_size > 1 ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> void sparc_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf && only_leaf_regs_used ( ) ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size - get_stack_check_protect ( ) ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( size == 0 ) ; else if ( sparc_leaf_function_p ) { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) emit_window_save ( size_int_rtx ) ; else if ( size <= 8192 ) { emit_window_save ( GEN_INT ( - 4096 ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the PIC register if needed .


<s> static void rs6000_live_on_entry ( bitmap regs ) { if ( flag_split_stack ) bitmap_set_bit ( regs , 12 ) ; } </s>

We may have to tell the dataflow pass that the split stack prologue is initializing a register .


<s> static int supersparc_adjust_cost ( rtx insn , rtx link , rtx dep_insn , int cost ) { enum attr_type insn_type ; if ( ! recog_memoized ( insn ) ) return 0 ; insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == 0 ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + 3 ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + 3 ; } if ( insn_type == TYPE_SHIFT ) return cost + 3 ; } else { if ( insn_type == TYPE_IALU || insn_type == TYPE_SHIFT ) return 0 ; } return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> static void ix86_destroy_cost_data ( void * data ) { free ( data ) ; } </s>


<s> unsigned X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> bool PPCTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget . isSVR4ABI ( ) || ! Subtarget . isPPC64 ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; const Function * Caller = CI -> getParent ( ) -> getParent ( ) ; auto Attr = Caller -> getFnAttribute ( "disable-tail-calls" ) ; if ( Attr . getValueAsString ( ) == "true" ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv ( ) ) ) return false ; return getTargetMachine ( ) . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , Callee ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .

PowerPC PPC PPC "disable-tail-calls" "true"


<s> bool FalkorHWPFFix :: runOnMachineFunction ( MachineFunction & Fn ) { auto & ST = static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; if ( ST . getProcFamily ( ) != AArch64Subtarget :: Falkor ) return false ; if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; Modified = false ; for ( MachineLoop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) if ( L -> isInnermost ( ) ) runOnLoop ( * * L , Fn ) ; return Modified ; } </s>


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tRestore
0


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
bool
X86TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
assert
(
SVI
->
getType
(
)
->
getNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
SmallVector
<
unsigned
,
4
>
Indices
;
auto
Mask
=
SVI
->
getShuffleMask
(
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Indices
.
push_back
(
Mask
[
i
]
)
;
ArrayRef
<
ShuffleVectorInst
*
>
Shuffles
=
makeArrayRef
(
SVI
)
;
IRBuilder
<
>
Builder
(
SI
)
;
X86InterleavedAccessGroup
Grp
(
SI
,
Shuffles
,
Indices
,
Factor
,
Subtarget
,
Builder
)
;
return
Grp
.
isSupported
(
)
&&
Grp
.
lowerIntoOptimizedSequence
(
)
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> unsigned ARMBaseInstrInfo :: getNumLDMAddresses ( const MachineInstr * MI ) const { unsigned Size = 0 ; for ( MachineInstr :: mmo_iterator I = MI -> memoperands_begin ( ) , E = MI -> memoperands_end ( ) ; I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ; } return Size / 4 ; } </s>

Get the number of addresses by LDM or VLDM or zero for unknown .


<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


<s> unsigned getNumFixupKinds ( ) const { return 3 ; } </s>

Get the number of target specific fixup kinds .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"OR1K Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createInsertDivideCheckPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"%s instructions aren't allowed in %s service routine"

"%s instructions aren't allowed in function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> bool MipsPassConfig :: addPreRegAlloc ( ) { if ( ! getMipsSubtarget ( ) . hasMips64 ( ) ) PM . add ( createMipsEmitGPRestorePass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> void SystemZTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { return LowerOperationWrapper ( N , Results , DAG ) ; } </s>


<s> bool PPCFastISel :: fastLowerArguments ( ) { return false ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


"expected larger existing stack allocation"

Target-specific cleanup for formal ByVal parameters .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
static
int
match_bracketed_pair
(
typeinfo
*
typedata
,
char
open
,
char
close
,
restriction
restr
)
{
if
(
linebuf
[
pos
]
==
open
)
{
safe_inc_pos
(
)
;
int
oldpos
=
pos
;
char
*
x
=
match_integer
(
)
;
if
(
x
==
)
{
diag
(
oldpos
,
"malformed integer.\n"
)
;
return
0
;
}
consume_whitespace
(
)
;
if
(
linebuf
[
pos
]
!=
','
)
{
diag
(
pos
,
"missing comma.\n"
)
;
return
0
;
}
safe_inc_pos
(
)
;
consume_whitespace
(
)
;
oldpos
=
pos
;
char
*
y
=
match_integer
(
)
;
if
(
y
==
)
{
diag
(
oldpos
,
"malformed integer.\n"
)
;
return
0
;
}
typedata
->
restr
=
restr
;
typedata
->
val1
=
x
;
typedata
->
val2
=
y
;
consume_whitespace
(
)
;
if
(
linebuf
[
pos
]
!=
close
)
{
diag
(
pos
,
"malformed restriction.\n"
)
;
return
0
;
}
safe_inc_pos
(
)
;
return
1
;
}
return
0
;
}
</s>

Helper routine for match_const_restriction .


<s> void rs6000_xcoff_declare_object_name ( FILE * file , const char * name , tree decl ) { struct declare_alias_data data = { file , false } ; RS6000_OUTPUT_BASENAME ( file , name ) ; fputs ( ":\n" , file ) ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; } </s>

This macro produces the initial definition of a object ( variable ) name . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s>
SDValue
MandarinTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
dump
(
)
;
DAG
.
dump
(
)
;
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
case
ISD
::
ConstantPool
:
return
LowerAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned int AArch64InstrInfo :: getTailDuplicateSize ( CodeGenOpt :: Level OptLevel ) const { return OptLevel >= CodeGenOpt :: Aggressive ? 6 : 2 ; } </s>

Returns the target-specific default value for tail duplication .