<s> void altivec_expand_vec_perm_le ( rtx operands [ 4 ] ) { rtx notx , iorx , unspec ; rtx target = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx sel = operands [ 3 ] ; rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target , unspec ) ; } </s>

Similarly to altivec_expand_vec_perm_const_le , we must adjust the permute control vector . But here it 's not a constant , so we must generate a vector NAND or NOR to do the adjustment .


<s> static bool sparc_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { if ( TARGET_ARCH32 ) return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) || mode == SCmode || GET_MODE_SIZE ( mode ) > 8 || ( type && TREE_CODE ( type ) == VECTOR_TYPE && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == VECTOR_TYPE ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 16 ) || GET_MODE_SIZE ( mode ) > 16 ) ; } </s>

Handle the TARGET_PASS_BY_REFERENCE target hook . Specify whether to pass the argument by reference .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Darwin PPC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool aarch64_use_new_vector_costs_p ( ) { return ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS ) ; } </s>

Return true if the current CPU should use the new costs defined in GCC 11 . This should be removed for GCC 12 and above , with the costs applying to all CPUs instead .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED , rtx pic_reg ) { rtx l1 , labelno , pic_tmp , pic_rtx ; if ( crtl -> uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE || TARGET_FDPIC ) return ; gcc_assert ( flag_pic ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; pic_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; pic_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pic_rtx ) , UNSPEC_GOTSYM_OFF ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; if ( TARGET_32BIT ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } else { if ( arm_pic_register != INVALID_REGNUM && REGNO ( pic_reg ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb1 ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_reg , pic_reg , labelno ) ) ; } else if ( arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && REGNO ( pic_reg ) <= LAST_LO_REGNUM ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; emit_move_insn ( gen_rtx_REG ( Pmode , arm_pic_register ) , pic_reg ) ; emit_use ( gen_rtx_REG ( Pmode , arm_pic_register ) ) ; } else emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } } emit_use ( pic_reg ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


<s>
void
Finish
(
)
{
const
size_t
VendorHeaderSize
=
4
+
CurrentVendor
.
size
(
)
+
1
;
const
size_t
TagHeaderSize
=
1
+
4
;
Streamer
.
EmitIntValue
(
VendorHeaderSize
+
TagHeaderSize
+
ContentsSize
,
4
)
;
Streamer
.
EmitBytes
(
CurrentVendor
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
Streamer
.
EmitIntValue
(
ARMBuildAttrs
::
File
,
1
)
;
Streamer
.
EmitIntValue
(
TagHeaderSize
+
ContentsSize
,
4
)
;
for
(
unsigned
int
i
=
0
;
i
<
Contents
.
size
(
)
;
++
i
)
{
AttributeItemType
item
=
Contents
[
i
]
;
Streamer
.
EmitULEB128IntValue
(
item
.
Tag
,
0
)
;
switch
(
item
.
Type
)
{
case
AttributeItemType
::
NumericAttribute
:
Streamer
.
EmitULEB128IntValue
(
item
.
IntValue
,
0
)
;
break
;
case
AttributeItemType
::
TextAttribute
:
Streamer
.
EmitBytes
(
UppercaseString
(
item
.
StringValue
)
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
break
;
default
:
assert
(
0
&&
"Invalid attribute type"
)
;
}
}
Contents
.
clear
(
)
;
}
</s>

Finish - Do final processing and write the object to the output stream .


<s> bool ARMBlockPlacement :: processPostOrderLoops ( MachineLoop * ML ) { bool Changed = false ; for ( auto * InnerML : * ML ) Changed |= processPostOrderLoops ( InnerML ) ; return Changed | fixBackwardsWLS ( ML ) ; } </s>

Updates ordering ( of WLS BB and their loopExits ) in inner loops first Returns true if any change was made in any of the loops .


<s> bool Mips16InstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = MI . getOperand ( 0 ) ; Src = MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> static void rs6000_elf_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( first && TREE_CODE ( decl ) == FUNCTION_DECL && ! TARGET_AIX && DEFAULT_ABI == ABI_AIX ) { rtx sym_ref = XEXP ( rtl , 0 ) ; size_t len = strlen ( XSTR ( sym_ref , 0 ) ) ; char * str = alloca ( len + 2 ) ; str [ 0 ] = '.' ; memcpy ( str + 1 , XSTR ( sym_ref , 0 ) , len + 1 ) ; XSTR ( sym_ref , 0 ) = ggc_alloc_string ( str , len + 1 ) ; } } </s>

For a SYMBOL_REF , set generic flags and then perform some target-specific processing . When the AIX ABI is requested on a non-AIX system , replace the function name with the real name ( with a leading . ) rather than the function descriptor name . This saves a lot of overriding code to read the prefixes .


<s>
static
void
arm_option_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
int
flags
=
ptr
->
x_target_flags
;
const
char
*
fpu_name
;
fpu_name
=
(
ptr
->
x_arm_fpu_index
==
TARGET_FPU_auto
"auto"
:
all_fpus
[
ptr
->
x_arm_fpu_index
]
.
name
)
;
fprintf
(
file
,
"%*sselected isa %s\n"
,
indent
,
""
,
TARGET_THUMB2_P
(
flags
)
"thumb2"
:
TARGET_THUMB_P
(
flags
)
"thumb1"
:
"arm"
)
;
if
(
ptr
->
x_arm_arch_string
)
fprintf
(
file
,
"%*sselected architecture %s\n"
,
indent
,
""
,
ptr
->
x_arm_arch_string
)
;
if
(
ptr
->
x_arm_cpu_string
)
fprintf
(
file
,
"%*sselected CPU %s\n"
,
indent
,
""
,
ptr
->
x_arm_cpu_string
)
;
if
(
ptr
->
x_arm_tune_string
)
fprintf
(
file
,
"%*sselected tune %s\n"
,
indent
,
""
,
ptr
->
x_arm_tune_string
)
;
fprintf
(
file
,
"%*sselected fpu %s\n"
,
indent
,
""
,
fpu_name
)
;
}
</s>

arm
"auto"
"%*sselected isa %s\n"
""
"thumb2"
"thumb1"
"arm"
"%*sselected architecture %s\n"
""
"%*sselected CPU %s\n"
""
"%*sselected tune %s\n"
""
"%*sselected fpu %s\n"
""


<s> rtx csky_legitimize_tls_address ( rtx x , rtx reg ) { rtx dest , tp , label , labelno , unspec , ret , eqv , addend , tmp ; rtx_insn * insns ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; if ( ! reg ) reg = gen_reg_rtx ( SImode ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : insns = csky_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; return dest ; case TLS_MODEL_LOCAL_DYNAMIC : insns = csky_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , addend ) ; return gen_rtx_PLUS ( Pmode , dest , addend ) ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( tls_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , x , GEN_INT ( TLS_IE32 ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ; emit_move_insn ( tmp , label ) ; emit_insn ( gen_addsi3 ( reg , reg , tmp ) ) ; emit_move_insn ( reg , gen_const_mem ( Pmode , reg ) ) ; tp = gen_rtx_REG ( SImode , CSKY_TLS_REGNUM ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; emit_move_insn ( reg , unspec ) ; tp = gen_rtx_REG ( SImode , CSKY_TLS_REGNUM ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; default : abort ( ) ; } } </s>

Helper function for csky_legitimize_address , to handle the TLS cases . REG is a scratch register and may be null .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { const auto & Desc = Info -> get ( Inst . getOpcode ( ) ) ; for ( unsigned i = 0 , e = Inst . getNumOperands ( ) ; i != e ; i ++ ) { if ( Desc . OpInfo [ i ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( i ) . getImm ( ) * 4 ; Target = Addr + Imm ; return true ; } } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> virtual bool isShuffleMaskLegal ( const SmallVectorImpl < int > & , EVT ) const { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> inline bool mips_lo_sum_offset_hasher :: equal ( const mips_lo_sum_offset * entry , const rtx_def * value ) { return rtx_equal_p ( entry -> base , value ) ; } </s>


<s> void PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , Register BaseReg , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = TM . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

PowerPC PPC PPC PPC::ADDI8 PPC::ADDI PPC PPC 0


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , HasNEON2 ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> SDValue ARMTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { if ( N -> getOpcode ( ) != ISD :: SDIV ) return SDValue ( ) ; const auto & ST = static_cast < const ARMSubtarget & > ( DAG . getSubtarget ( ) ) ; const bool MinSize = ST . optForMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideInARMMode ( ) ; if ( N -> getOperand ( 0 ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( ! ( MinSize && HasDivide ) ) return SDValue ( ) ; if ( ! ST . isThumb ( ) ) return SDValue ( N , 0 ) ; if ( Divisor . sgt ( 128 ) ) return SDValue ( ) ; return SDValue ( N , 0 ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void ix86_add_reg_usage_to_vzeroupper ( rtx_insn * insn , bitmap live_regs ) { rtx pattern = PATTERN ( insn ) ; unsigned int nregs = TARGET_64BIT ? 16 : 8 ; unsigned int npats = nregs ; for ( unsigned int i = 0 ; i < nregs ; ++ i ) { unsigned int regno = GET_SSE_REGNO ( i ) ; if ( ! bitmap_bit_p ( live_regs , regno ) ) npats -- ; } if ( npats == 0 ) return ; rtvec vec = rtvec_alloc ( npats + 1 ) ; RTVEC_ELT ( vec , 0 ) = XVECEXP ( pattern , 0 , 0 ) ; for ( unsigned int i = 0 , j = 0 ; i < nregs ; ++ i ) { unsigned int regno = GET_SSE_REGNO ( i ) ; if ( ! bitmap_bit_p ( live_regs , regno ) ) continue ; rtx reg = gen_rtx_REG ( V2DImode , regno ) ; ++ j ; RTVEC_ELT ( vec , j ) = gen_rtx_SET ( reg , reg ) ; } XVEC ( pattern , 0 ) = vec ; INSN_CODE ( insn ) = - 1 ; df_insn_rescan ( insn ) ; } </s>

Modify the vzeroupper pattern in INSN so that it describes the effect that the instruction has on the SSE registers . LIVE_REGS are the set of registers that are live across the instruction . For a live register R we use : ( set ( reg : V2DF R ) ( reg : V2DF R ) ) which preserves the low 128 bits but clobbers the upper bits .


<s> bool PPCTargetLowering :: useLoadStackGuardNode ( ) const { if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return true ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


<s> static unsigned int ix86_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( GENERAL_REGNO_P ( regno ) ) { if ( mode == XFmode ) return TARGET_64BIT ? 2 : 3 ; if ( mode == XCmode ) return TARGET_64BIT ? 4 : 6 ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } if ( COMPLEX_MODE_P ( mode ) ) return 2 ; if ( mode == P2QImode || mode == P2HImode ) return 2 ; if ( mode == V64SFmode || mode == V64SImode ) return 4 ; return 1 ; } </s>

Implement TARGET_HARD_REGNO_NREGS . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . Actually there are no two word move instructions for consecutive registers . And only registers 0-3 may have mov byte instructions applied to them .


<s>
bool
FalkorHWPFFix
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
auto
&
ST
=
static_cast
<
const
AArch64Subtarget
&
>
(
Fn
.
getSubtarget
(
)
)
;
if
(
ST
.
getProcFamily
(
)
!=
AArch64Subtarget
::
Falkor
)
return
false
;
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
assert
(
TRI
->
trackLivenessAfterRegAlloc
(
Fn
)
&&
"Register liveness not available!"
)
;
MachineLoopInfo
&
LI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
Modified
=
false
;
for
(
MachineLoop
*
I
:
LI
)
for
(
auto
L
=
df_begin
(
I
)
,
LE
=
df_end
(
I
)
;
L
!=
LE
;
++
L
)
if
(
L
->
empty
(
)
)
runOnLoop
(
*
*
L
,
Fn
)
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static bool arm_block_set_unaligned_non_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { unsigned int i ; rtx dst , addr , mem ; rtx val_exp , val_reg , reg ; machine_mode mode ; HOST_WIDE_INT v = value ; gcc_assert ( align == 1 || align == 2 ) ; if ( align == 2 ) v |= ( value << BITS_PER_UNIT ) ; v = sext_hwi ( v , BITS_PER_WORD ) ; val_exp = GEN_INT ( v ) ; if ( ! arm_block_set_non_vect_profit_p ( val_exp , length , align , true , false ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , 0 ) ) ; mode = ( align == 2 ? HImode : QImode ) ; val_reg = force_reg ( SImode , val_exp ) ; reg = gen_lowpart ( mode , val_reg ) ; for ( i = 0 ; ( i + GET_MODE_SIZE ( mode ) <= length ) ; i += GET_MODE_SIZE ( mode ) ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , mode , addr , i ) ; emit_move_insn ( mem , reg ) ; } if ( i + 1 == length ) { reg = gen_lowpart ( QImode , val_reg ) ; addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , QImode , addr , i ) ; emit_move_insn ( mem , reg ) ; i ++ ; } gcc_assert ( i == length ) ; return true ; } </s>

Set a block of memory using plain strh/strb instructions , only using instructions allowed by ALIGN on processor . We fill the first LENGTH bytes of the memory area starting from DSTBASE with byte constant VALUE . ALIGN is the alignment requirement of memory .


<s> bool aarch64_split_128bit_move_p ( rtx dst , rtx src ) { if ( FP_REGNUM_P ( REGNO ( dst ) ) ) return REG_P ( src ) && ! FP_REGNUM_P ( REGNO ( src ) ) ; return true ; } </s>

Return true if we should split a move from 128-bit value SRC to 128-bit register DEST .


<s> static tree sh_symbian_associated_type ( tree decl ) { tree t = NULL_TREE ; if ( TREE_CODE ( TREE_TYPE ( decl ) ) == METHOD_TYPE ) return t ; if ( DECL_CONTEXT ( decl ) && TYPE_P ( DECL_CONTEXT ( decl ) ) ) t = DECL_CONTEXT ( decl ) ; return t ; } </s>

Return the type that we should use to determine if DECL is imported or exported .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0


<s> static Cpu0ABIInfo Unknown ( ) { return Cpu0ABIInfo ( ABI :: Unknown ) ; } </s>

The kind of location description being produced . More ...


<s> void MipsFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { const MipsRegisterInfo * RegInfo = static_cast < const MipsRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; RegInfo -> processFunctionBeforeFrameFinalized ( MF ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
int
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
MFI
.
getObjectOffset
(
FI
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> int iq2000_initial_elimination_offset ( int from , int to ATTRIBUTE_UNUSED ) { int offset ; compute_frame_size ( get_frame_size ( ) ) ; if ( ( from ) == FRAME_POINTER_REGNUM ) ( offset ) = 0 ; else if ( ( from ) == ARG_POINTER_REGNUM ) ( offset ) = ( cfun -> machine -> total_size ) ; else if ( ( from ) == RETURN_ADDRESS_POINTER_REGNUM ) { if ( leaf_function_p ( ) ) ( offset ) = 0 ; else ( offset ) = cfun -> machine -> gp_sp_offset + ( ( UNITS_PER_WORD - ( POINTER_SIZE / BITS_PER_UNIT ) ) * ( BYTES_BIG_ENDIAN != 0 ) ) ; } else gcc_unreachable ( ) ; return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET . FROM is either the frame pointer , argument pointer , or return address pointer . TO is either the stack pointer or hard frame pointer .


<s> unsigned getLength ( ) const { return CurType . Length ; } </s>

Return the number of bytes of data in this stream .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
maybe_unlink
(
const
char
*
file
)
{
if
(
!
save_temps
)
{
if
(
unlink_if_ordinary
(
file
)
&&
errno
!=
ENOENT
)
fatal_error
(
input_location
,
"deleting file %s: %m"
,
file
)
;
}
else
if
(
verbose
)
fprintf
(
stderr
,
"[Leaving %s]\n"
,
file
)
;
}
</s>

Unlink a temporary file unless requested otherwise .

i386
"deleting file %s: %m"
"[Leaving %s]\n"


<s> static void mips_prepare_pch_save ( void ) { mips_set_compression_mode ( 0 ) ; mips16_globals = 0 ; micromips_globals = 0 ; } </s>


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> MipsInstrInfo :: BranchType MipsInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify , SmallVectorImpl < MachineInstr * > & BranchInstrs ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugValue ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return BT_NoBranch ; } MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugValue ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_CondUncond ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( X86 :: RSP ) ; Reserved . set ( X86 :: ESP ) ; Reserved . set ( X86 :: SP ) ; Reserved . set ( X86 :: SPL ) ; if ( hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; Reserved . set ( X86 :: EBP ) ; Reserved . set ( X86 :: BP ) ; Reserved . set ( X86 :: BPL ) ; } Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool VEAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'r' : case 'v' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static inline _Unwind_Control_Block * unwind_UCB_from_context ( _Unwind_Context * context ) { return ( _Unwind_Control_Block * ) _Unwind_GetGR ( context , R_IP ) ; } </s>

Get the _Unwind_Control_Block from an _Unwind_Context .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; if ( GV && GV -> isAbsoluteSymbolRef ( ) ) return X86II :: MO_NO_FLAG ; if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static void arm_emit_ldrd_pop ( unsigned long saved_regs_mask ) { int j = 0 ; int offset = 0 ; rtx par = NULL_RTX ; rtx dwarf = NULL_RTX ; rtx tmp , mem ; gcc_assert ( ! ( ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ) ) ; j = 0 ; while ( j <= LAST_ARM_REGNUM ) if ( saved_regs_mask & ( 1 << j ) ) { if ( ( j % 2 ) == 0 && ( saved_regs_mask & ( 1 << ( j + 1 ) ) ) && ( j + 1 ) != PC_REGNUM ) { if ( offset > 0 ) mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( gen_rtx_REG ( DImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j + 1 ) , dwarf ) ; REG_NOTES ( tmp ) = dwarf ; offset += 8 ; j += 2 ; } else if ( j != PC_REGNUM ) { if ( offset > 0 ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( gen_rtx_REG ( SImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; offset += 4 ; j += 1 ; } else j ++ ; } else j ++ ; if ( offset > 0 ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = emit_insn ( tmp ) ; arm_add_cfa_adjust_cfa_note ( tmp , offset , stack_pointer_rtx , stack_pointer_rtx ) ; offset = 0 ; } if ( saved_regs_mask & ( 1 << PC_REGNUM ) ) { par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; tmp = gen_rtx_SET ( gen_rtx_REG ( SImode , PC_REGNUM ) , gen_frame_mem ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 1 ) = tmp ; par = emit_jump_insn ( par ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , PC_REGNUM ) , NULL_RTX ) ; REG_NOTES ( par ) = dwarf ; arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD , stack_pointer_rtx , stack_pointer_rtx ) ; } } </s>

LDRD in ARM mode needs consecutive registers as operands . This function emits LDRD whenever possible , otherwise it emits single-word loads . It uses offset addressing and then generates one separate stack udpate . This provides more scheduling freedom , compared to writeback on every load . However , if the function returns using load into PC directly ( i.e. , if PC is in SAVED_REGS_MASK ) , the stack needs to be updated before the last load . TODO : Add a peephole optimization to recognize the new epilogue sequence as an LDM instruction whenever possible . TODO : Add peephole optimization to merge the load at stack-offset zero with the stack update instruction using load with writeback in post-index addressing mode .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_AArch64_CXX_TLS_Darwin_RegMask ; if ( CC == CallingConv :: AArch64_SVE_VectorCall ) return CSR_AArch64_SVE_AAPCS_RegMask ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_AArch64_AAPCS_SwiftError_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_AArch64_RT_MostRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"function_arg_pass_by_reference: V4 long double\n"

"non-standard ABI extension with no compatibility guarantee"

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isCall ( ) ) continue ; if ( IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool aarch64_scalar_mode_supported_p ( scalar_mode mode ) { return ( mode == HFmode ? true : default_scalar_mode_supported_p ( mode ) ) ; } </s>

Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE if MODE is HFmode , and punt to the generic implementation otherwise .


<s> SDValue Cpu0TargetLowering :: getTargetNode ( JumpTableSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> bool mep_mul_hilo_bypass_p ( rtx_insn * prev , rtx_insn * insn ) { rtx pat ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) != SET ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , SET_SRC ( pat ) , NONCONST ) { const_rtx x = * iter ; if ( REG_P ( x ) && REGNO ( x ) != LO_REGNO && REGNO ( x ) != HI_REGNO && reg_set_p ( x , prev ) ) return false ; } return true ; } </s>

Return true if , apart from HI/LO , there are no true dependencies between multiplication instructions PREV and INSN .


"%qs applied to type %qT, which already has a size"

"%qs requires an integer constant expression"

An attribute callback for the `` arm_sve_vector_bits '' attribute .


<s> bool ARMSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & ARM :: GPRRegClass ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> bool X86InstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return ! ( RC == & X86 :: CCRRegClass || RC == & X86 :: RFP32RegClass || RC == & X86 :: RFP64RegClass || RC == & X86 :: RFP80RegClass ) ; } </s>

isSafeToMoveRegClassDefs - Return true if it 's safe to move a machine instruction that defines the specified register class .


<s> rtx mips_unspec_address ( rtx address , enum mips_symbol_type symbol_type ) { rtx base , offset ; split_const ( address , & base , & offset ) ; return mips_unspec_address_offset ( base , offset , symbol_type ) ; } </s>

Return an UNSPEC address with underlying address ADDRESS and symbol type SYMBOL_TYPE .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & instr , uint64_t & size , const MemoryObject & region , uint64_t address , raw_ostream & vStream , raw_ostream & cStream ) const { CommentStream = & cStream ; InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = 0 ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * ) MII , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr , this ) ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || SUBREG_P ( dest ) ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode ) ; } } </s>

Emit a sequence representing a little-endian VSX load or store , moving data from SOURCE to DEST in mode MODE . This is done separately from rs6000_emit_move to ensure it is called only during expand . LE VSX loads and stores introduced later are handled with a split . The expand-time RTL generation allows us to optimize away redundant pairs of register-permutes .


"Expected a reg or frame index operand."

Return true if this is a load/store that can be potentially paired/merged .


<s> static bool xstormy16_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return mode1 != BImode && mode2 != BImode ; } </s>


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> DecodeStatus TeeRISCDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableTeeRISC32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> void ix86_emit_i387_log1p ( rtx op0 , rtx op1 ) { rtx_code_label * label1 = gen_label_rtx ( ) ; rtx_code_label * label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx tmp2 = gen_reg_rtx ( XFmode ) ; rtx test ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; test = gen_rtx_GE ( VOIDmode , tmp , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( "0.29289321881345247561810596348408353" , XFmode ) , XFmode ) ) ; emit_jump_insn ( gen_cbranchxf4 ( test , XEXP ( test , 0 ) , XEXP ( test , 1 ) , label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xp1xf3_i387 ( op0 , op1 , tmp2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( tmp , op1 , tmp ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xxf3_i387 ( op0 , tmp , tmp2 ) ) ; emit_label ( label2 ) ; } </s>

Output code to perform a log1p XFmode calculation .


<s> bool isReg ( ) const override { return Kind == REGISTER ; } </s>


<s> void Cpu0TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> rtx or1k_return_addr ( int , rtx frame ) { return gen_frame_mem ( Pmode , plus_constant ( Pmode , frame , - UNITS_PER_WORD ) ) ; } </s>

Worker for RETURN_ADDR_RTX . Returns the RTX representing the address of where the link register may be stored on the stack .


<s> bool X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * SI ) const { return false ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> rtx mips_loongson_ext2_prefetch_cookie ( rtx write , rtx ) { if ( INTVAL ( write ) == 1 ) return GEN_INT ( INTVAL ( write ) ) ; if ( INTVAL ( write ) == 0 ) return GEN_INT ( INTVAL ( write ) ) ; gcc_unreachable ( ) ; } </s>

Loongson EXT2 only implements pref hint=0 ( prefetch for load ) and hint=1 ( prefetch for store ) , other hint just scale to hint = 0 and hint = 1 .


<s> TargetLowering :: ConstraintWeight DLXTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & Info , const char * Constraint ) const { ConstraintWeight Weight = CW_Invalid ; return Weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void i386_pe_seh_end_prologue ( FILE * f ) { struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; seh = cfun -> machine -> seh ; XDELETE ( seh ) ; cfun -> machine -> seh = NULL ; fputs ( "\t.seh_endprologue\n" , f ) ; } </s>

Emit an assembler directive for the end of the prologue .


<s> bool MipsSEInstrInfo :: isBranchWithImm ( unsigned Opc ) const { switch ( Opc ) { default : return false ; case Mips :: BBIT0 : case Mips :: BBIT1 : case Mips :: BBIT032 : case Mips :: BBIT132 : return true ; } } </s>

isBranchWithImm - Return true if the branch contains an immediate operand (


"Unknown fence ordering in emitLeadingFence"


<s> inline set_of_reg sh_find_set_of_reg ( rtx reg , rtx_insn * insn , F stepfunc , bool ignore_reg_reg_copies = false ) { set_of_reg result ; result . insn = insn ; result . set_rtx = NULL_RTX ; result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_set_p ( reg , i ) ) { if ( CALL_P ( i ) ) break ; result . insn = i ; result . set_rtx = set_of ( reg , i ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , 1 ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; } if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) { reg = SUBREG_REG ( result . set_src ) ; continue ; } break ; } } if ( result . set_src != NULL ) gcc_assert ( result . insn != NULL && result . set_rtx != NULL ) ; return result ; } </s>

Given a reg rtx and a start insn , try to find the insn that sets the specified reg by using the specified insn stepping function , such as 'prev_nonnote_insn_bb ' . When the insn is found , try to extract the rtx of the reg set .


<s> bool X86TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? 64 : 32 ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCLoopPreIncPrepPass ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoops ( ) ) ; return false ; } </s>


<s>
bool
CSKYConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
BrOffset
=
getOffsetOf
(
MI
)
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

CSKY
CSKY
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> static HOST_WIDE_INT mips_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return 0 ; return crtl -> outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE ; } </s>

Implement TARGET_STARTING_FRAME_OFFSET . See mips_compute_frame_info for details about the frame layout .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; const bool IsDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! IsDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"-mcpu must be empty(default:cpu032II), cpu032I or cpu032II"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static int get_mode_no_for_insn ( rtx_insn * insn ) { rtx reg , mem , mode_rtx ; int mode_no ; bool extend_p ; extract_insn_cached ( insn ) ; if ( recog_data . n_operands != 2 ) return - 1 ; reg = recog_data . operand [ 0 ] ; mem = recog_data . operand [ 1 ] ; if ( get_attr_speculable1 ( insn ) == SPECULABLE1_YES ) { if ( ! reload_completed ) { if ( ! REG_P ( reg ) || AR_REGNO_P ( REGNO ( reg ) ) ) return - 1 ; if ( ! MEM_P ( mem ) ) return - 1 ; { rtx mem_reg = XEXP ( mem , 0 ) ; if ( ! REG_P ( mem_reg ) ) return - 1 ; } mode_rtx = mem ; } else if ( get_attr_speculable2 ( insn ) == SPECULABLE2_YES ) { gcc_assert ( REG_P ( reg ) && MEM_P ( mem ) ) ; mode_rtx = mem ; } else return - 1 ; } else if ( get_attr_data_speculative ( insn ) == DATA_SPECULATIVE_YES || get_attr_control_speculative ( insn ) == CONTROL_SPECULATIVE_YES || get_attr_check_load ( insn ) == CHECK_LOAD_YES ) { gcc_assert ( REG_P ( reg ) && MEM_P ( mem ) ) ; mode_rtx = mem ; } else { enum attr_itanium_class attr_class = get_attr_itanium_class ( insn ) ; if ( attr_class == ITANIUM_CLASS_CHK_A || attr_class == ITANIUM_CLASS_CHK_S_I || attr_class == ITANIUM_CLASS_CHK_S_F ) mode_rtx = reg ; else return - 1 ; } mode_no = ia64_mode_to_int ( GET_MODE ( mode_rtx ) ) ; if ( mode_no == SPEC_MODE_INVALID ) return - 1 ; extend_p = ( GET_MODE ( reg ) != GET_MODE ( mode_rtx ) ) ; if ( extend_p ) { if ( ! ( SPEC_MODE_FOR_EXTEND_FIRST <= mode_no && mode_no <= SPEC_MODE_FOR_EXTEND_LAST ) ) return - 1 ; mode_no += SPEC_GEN_EXTEND_OFFSET ; } return mode_no ; } </s>

If INSN is an appropriate load return its mode . Return -1 otherwise .


runOnMachineFunction - Emit the function body .


<s> static rtx aarch64_progress_pointer ( rtx pointer ) { return aarch64_move_pointer ( pointer , GET_MODE_SIZE ( GET_MODE ( pointer ) ) ) ; } </s>

Return a new RTX holding the result of moving POINTER forward by the size of the mode it points to .


<s>
void
assignValueToAddress
(
Register
ValVReg
,
Register
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
Size
=
4
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
auto
LoadVReg
=
buildLoad
(
LLT
::
scalar
(
32
)
,
Addr
,
Size
,
1
,
MPO
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
LoadVReg
)
;
}
else
{
buildLoad
(
ValVReg
,
Addr
,
Size
,
1
,
MPO
)
;
}
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> unsigned PPCTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCost ( Opcode , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> std :: pair < unsigned , const TargetRegisterClass * > CAHPTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & CAHP :: GPRRegClass ) ; default : break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> const char * LoongArchTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( LoongArchISD :: NodeType ) Opcode ) { case LoongArchISD :: FIRST_NUMBER : break ; case LoongArchISD :: node : \ return "LoongArchISD::" # node ; NODE_NAME_CASE ( RET ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

LoongArch LoongArch LoongArchISD::NodeType LoongArchISD::FIRST_NUMBER LoongArchISD::node "LoongArchISD::"


<s> void UPTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool aarch64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( aarch64_vector_mode_p ( mode1 ) && aarch64_vector_mode_p ( mode2 ) ) return true ; if ( aarch64_vector_mode_supported_p ( mode1 ) || aarch64_vector_mode_supported_p ( mode2 ) ) return true ; return false ; } </s>

Implement MODES_TIEABLE_P . In principle we should always return true . However due to issues with register allocation it is preferable to avoid tieing integer scalar and FP scalar modes . Executing integer operations in general registers is better than treating them as scalar vector operations . This reduces latency and avoids redundant int < - > FP moves . So tie modes if they are either the same class , or vector modes with other vector modes , vector structs or any scalar mode .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getEnvironment ( ) != Triple :: GNUILP32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> PLTEntryBase * X86PLT :: create ( ) { if ( LinkerConfig :: DynObj == m_Config . codeGenType ( ) ) return new X86_32DynPLT1 ( * m_pSectionData ) ; else return new X86_32ExecPLT1 ( * m_pSectionData ) ; } </s>


<s>
void
print
(
raw_ostream
&
Out
)
const
{
R
.
print
(
Out
)
;
Out
<<
", Matched="
<<
Matched
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


"Switch should handle all register classes"


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; for ( MachineFunction :: iterator mbbi = F . begin ( ) , mbbe = F . end ( ) ; mbbi != mbbe ; ++ mbbi ) { for ( MachineBasicBlock :: iterator mi = mbbi -> begin ( ) , me = mbbi -> end ( ) ; mi != me ; ) { MachineBasicBlock :: iterator MI = mi ; MachineBasicBlock * MBB = mbbi ; ++ mi ; if ( MI -> getDesc ( ) . getOpcode ( ) == Mips :: LOAD_IMM_PSEUDO ) { expandLoadImm ( * MBB , MI , TII ) ; MBB -> erase ( MI ) ; ++ ExpandPseudo ; continue ; } if ( MI -> getDesc ( ) . getOpcode ( ) == Mips :: IJMP_PSEUDO ) { expandIJmp ( * MBB , MI , TII ) ; MBB -> erase ( MI ) ; ++ ExpandPseudo ; } } } return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips::LOAD_IMM_PSEUDO Mips::IJMP_PSEUDO


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , Register BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDframe : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) . add ( condCodeOp ( ) ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDframe ARM::t2ADDri 0 ARMCC::AL


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMSET ) ; } </s>

Emit target-specific code that performs a memset .


<s> static rtx shifter_op_p ( rtx op , rtx * shift_reg ) { enum rtx_code code = GET_CODE ( op ) ; if ( code == MULT && CONST_INT_P ( XEXP ( op , 1 ) ) && exact_log2 ( INTVAL ( XEXP ( op , 1 ) ) ) > 0 ) return XEXP ( op , 0 ) ; else if ( code == ROTATE && CONST_INT_P ( XEXP ( op , 1 ) ) ) return XEXP ( op , 0 ) ; else if ( code == ROTATERT || code == ASHIFT || code == LSHIFTRT || code == ASHIFTRT ) { if ( ! CONST_INT_P ( XEXP ( op , 1 ) ) ) * shift_reg = XEXP ( op , 1 ) ; return XEXP ( op , 0 ) ; } return NULL ; } </s>

Helper function for arm_rtx_costs . If the operand is a valid shift operand , then return the operand that is being shifted . If the shift is not by a constant , then set SHIFT_REG to point to the operand . Return NULL if OP is not a shifter operand .


<s> bool aarch64_expand_sve_vec_cmp_float ( rtx target , rtx_code code , rtx op0 , rtx op1 , bool can_invert_p ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; rtx ptrue = aarch64_ptrue_reg ( pred_mode ) ; switch ( code ) { case UNORDERED : op1 = force_reg ( data_mode , op1 ) ; case LT : case LE : case GT : case GE : case EQ : case NE : { aarch64_emit_sve_fp_cond ( target , code , ptrue , true , op0 , op1 ) ; return false ; } case LTGT : aarch64_emit_sve_or_fp_conds ( target , LT , GT , ptrue , true , op0 , op1 ) ; return false ; case UNEQ : if ( ! flag_trapping_math ) { op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_sve_or_fp_conds ( target , UNORDERED , EQ , ptrue , true , op0 , op1 ) ; return false ; } case UNLT : case UNLE : case UNGT : case UNGE : if ( flag_trapping_math ) { rtx ordered = gen_reg_rtx ( pred_mode ) ; op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_sve_invert_fp_cond ( ordered , UNORDERED , ptrue , true , op0 , op1 ) ; if ( code == UNEQ ) code = NE ; else code = reverse_condition_maybe_unordered ( code ) ; if ( can_invert_p ) { aarch64_emit_sve_fp_cond ( target , code , ordered , false , op0 , op1 ) ; return true ; } aarch64_emit_sve_invert_fp_cond ( target , code , ordered , false , op0 , op1 ) ; return false ; } break ; case ORDERED : op1 = force_reg ( data_mode , op1 ) ; break ; default : gcc_unreachable ( ) ; } code = reverse_condition_maybe_unordered ( code ) ; if ( can_invert_p ) { aarch64_emit_sve_fp_cond ( target , code , ptrue , true , op0 , op1 ) ; return true ; } aarch64_emit_sve_invert_fp_cond ( target , code , ptrue , true , op0 , op1 ) ; return false ; } </s>

Expand an SVE floating-point comparison : TARGET = CODE ( OP0 , OP1 ) If CAN_INVERT_P is true , the caller can also handle inverted results ; return true if the result is in fact inverted .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( ! GV ) return X86II :: MO_NO_FLAG ; if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( isOSWindows ( ) ) return X86II :: MO_NO_FLAG ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } if ( TM . getRelocationModel ( ) == Reloc :: Static ) return X86II :: MO_NO_FLAG ; return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
isReg
(
)
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> void MipsSETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"reloc_pcrel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_pcrel_1byte"
,
0
,
1
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_pcrel_2byte"
,
0
,
2
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static void ix86_sched_init_global ( FILE * , int , int ) { switch ( ix86_tune ) { case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : if ( reload_completed ) { targetm . sched . dfa_post_advance_cycle = core2i7_dfa_post_advance_cycle ; targetm . sched . first_cycle_multipass_init = core2i7_first_cycle_multipass_init ; targetm . sched . first_cycle_multipass_begin = core2i7_first_cycle_multipass_begin ; targetm . sched . first_cycle_multipass_issue = core2i7_first_cycle_multipass_issue ; targetm . sched . first_cycle_multipass_backtrack = core2i7_first_cycle_multipass_backtrack ; targetm . sched . first_cycle_multipass_end = core2i7_first_cycle_multipass_end ; targetm . sched . first_cycle_multipass_fini = core2i7_first_cycle_multipass_fini ; core2i7_secondary_decoder_max_insn_size = 8 ; core2i7_ifetch_block_size = 16 ; core2i7_ifetch_block_max_insns = 6 ; break ; } default : targetm . sched . dfa_post_advance_cycle = NULL ; targetm . sched . first_cycle_multipass_init = NULL ; targetm . sched . first_cycle_multipass_begin = NULL ; targetm . sched . first_cycle_multipass_issue = NULL ; targetm . sched . first_cycle_multipass_backtrack = NULL ; targetm . sched . first_cycle_multipass_end = NULL ; targetm . sched . first_cycle_multipass_fini = NULL ; break ; } } </s>


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; EmitXRayTable ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> static int no_previous_def ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return 0 ; return 1 ; } </s>

NO_PREVIOUS_DEF checks in the link list whether the function name is already there or not .


<s> bool VEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static sbitmap rs6000_get_separate_components ( void ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( WORLD_SAVE_P ( info ) ) return NULL ; if ( TARGET_SPE_ABI ) return NULL ; sbitmap components = sbitmap_alloc ( 32 ) ; bitmap_clear ( components ) ; gcc_assert ( ! ( info -> savres_strategy & SAVE_MULTIPLE ) && ! ( info -> savres_strategy & REST_MULTIPLE ) ) ; if ( ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) ) { int reg_size = TARGET_32BIT ? 4 : 8 ; int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && rs6000_reg_live_or_pic_offset_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += reg_size ; } } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( ( TARGET_TOC && TARGET_MINIMAL_TOC ) || ( flag_pic == 1 && DEFAULT_ABI == ABI_V4 ) || ( flag_pic && DEFAULT_ABI == ABI_DARWIN ) ) bitmap_clear_bit ( components , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( info -> lr_save_p && ! ( flag_pic && ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) ) && ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) && ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) && ( info -> savres_strategy & SAVE_INLINE_VRS ) && ( info -> savres_strategy & REST_INLINE_VRS ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) ) bitmap_set_bit ( components , 0 ) ; } return components ; } </s>


<s> bool mep_use_post_modify_p ( rtx_insn * insn , rtx reg , rtx offset ) { bool result = mep_use_post_modify_p_1 ( insn , reg , offset ) ; extract_insn ( insn ) ; return result ; } </s>

A wrapper around mep_use_post_modify_p_1 that preserves recog_data .


<s>
void
SystemZInstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
Register
DstReg
,
ArrayRef
<
MachineOperand
>
Pred
,
Register
TrueReg
,
Register
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
unsigned
Opc
;
if
(
SystemZ
::
GRX32BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELRMux
;
else
if
(
STI
.
hasLoadStoreOnCond2
(
)
)
Opc
=
SystemZ
::
LOCRMux
;
else
{
Opc
=
SystemZ
::
LOCR
;
MRI
.
constrainRegClass
(
DstReg
,
&
SystemZ
::
GR32BitRegClass
)
;
Register
TReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
Register
FReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
TReg
)
.
addReg
(
TrueReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
FReg
)
.
addReg
(
FalseReg
)
;
TrueReg
=
TReg
;
FalseReg
=
FReg
;
}
}
else
if
(
SystemZ
::
GR64BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELGR
;
else
Opc
=
SystemZ
::
LOCGR
;
}
else
llvm_unreachable
(
"Invalid register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


"Tail call for extern symbol not yet supported."

Targets should implement this to emit instructions .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) ; const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( STI . getInstrInfo ( ) ) ; const TargetMachine & TM = F . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; LongBranchSeqSize = IsPIC ? ( ( ABI . IsN64 ( ) || STI . isTargetNaCl ( ) ) ? 10 : 9 ) : ( STI . hasMips32r6 ( ) ? 1 : 2 ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( IsPIC && static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( IsPIC ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>


<s> bool XNCMPassConfig :: addPreEmitPass ( ) { return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
uint32_t
AArch64MCCodeEmitter
::
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
unsigned
NumOperands
=
MI
.
getNumOperands
(
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected ADR target type!"
)
;
MCFixupKind
Kind
=
MI
.
getOpcode
(
)
==
AArch64
::
BL
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_call26
)
:
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_branch26
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
Kind
,
MI
.
getLoc
(
)
)
)
;
++
MCNumFixups
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
,
Fixup
,
Asm
.
getContext
(
)
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ARMAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb" ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arm" ) return parseDirectiveARM ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb_func" ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".code" ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".syntax" ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arch" ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".eabi_attribute" ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) , GISel ( ) { GISelAccessor * AArch64GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * AArch64GISel = new AArch64GISelActualAccessor ( ) ; AArch64GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; AArch64GISel -> Legalizer . reset ( new AArch64LegalizerInfo ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; AArch64GISel -> InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; AArch64GISel -> RegBankInfo . reset ( RBI ) ; setGISelAccessor ( * AArch64GISel ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool AArch64FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; static const LoadStoreMethod PossibleClasses [ ] = { { & AArch64 :: GPR64RegClass , AArch64 :: LSPair64_STR , AArch64 :: LS64_STR } , { & AArch64 :: FPR64RegClass , AArch64 :: LSFPPair64_STR , AArch64 :: LSFP64_STR } , } ; const unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( true , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool swap_top_of_ready_list ( rtx_insn * * ready , int n_ready ) { rtx_insn * top = ready [ n_ready - 1 ] ; rtx_insn * next = ready [ n_ready - 2 ] ; rtx set ; sd_iterator_def sd_it ; dep_t dep ; int clock1 = - 1 ; int clock2 = - 1 ; if ( ! TARGET_CPU_P ( SILVERMONT ) && ! TARGET_CPU_P ( INTEL ) ) return false ; if ( ! NONDEBUG_INSN_P ( top ) ) return false ; if ( ! NONJUMP_INSN_P ( top ) ) return false ; if ( ! NONDEBUG_INSN_P ( next ) ) return false ; if ( ! NONJUMP_INSN_P ( next ) ) return false ; set = single_set ( top ) ; if ( ! set ) return false ; set = single_set ( next ) ; if ( ! set ) return false ; if ( INSN_PRIORITY_KNOWN ( top ) && INSN_PRIORITY_KNOWN ( next ) ) { if ( INSN_PRIORITY ( top ) != INSN_PRIORITY ( next ) ) return false ; FOR_EACH_DEP ( top , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock1 ) clock1 = INSN_TICK ( pro ) ; } FOR_EACH_DEP ( next , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock2 ) clock2 = INSN_TICK ( pro ) ; } if ( clock1 == clock2 ) { enum attr_memory memory1 , memory2 ; memory1 = get_attr_memory ( top ) ; memory2 = get_attr_memory ( next ) ; if ( memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD ) return true ; } return ( bool ) ( clock2 < clock1 ) ; } return false ; } </s>

Try to find the best candidate on the top of ready list if two insns have the same priority - candidate is best if its dependees were scheduled earlier . Applied for Silvermont only . Return true if top 2 insns must be interchanged .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || N -> getOpcode ( ) == X86ISD :: TC_RETURN ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , DstVT , dl , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> int const_ok_for_dimode_op ( HOST_WIDE_INT i , enum rtx_code code ) { HOST_WIDE_INT hi_val = ( i >> 32 ) & 0xFFFFFFFF ; HOST_WIDE_INT lo_val = i & 0xFFFFFFFF ; rtx hi = GEN_INT ( hi_val ) ; rtx lo = GEN_INT ( lo_val ) ; if ( TARGET_THUMB1 ) return 0 ; switch ( code ) { case AND : case IOR : case XOR : return const_ok_for_op ( hi_val , code ) || hi_val == 0xFFFFFFFF || const_ok_for_op ( lo_val , code ) || lo_val == 0xFFFFFFFF ; case PLUS : return arm_not_operand ( hi , SImode ) && arm_add_operand ( lo , SImode ) ; default : return 0 ; } } </s>

Return true if I is a valid di mode constant for the operation CODE .


<s> unsigned ARMTTI :: getIntImmCost ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 32 ) return 4 ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } else if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } else { if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } return 2 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static void * mingw32_gt_pch_get_address ( size_t size , int ) { void * res ; size = ( size + va_granularity - 1 ) & ~ ( va_granularity - 1 ) ; if ( size > pch_VA_max_size ) return NULL ; res = VirtualAlloc ( NULL , pch_VA_max_size , MEM_RESERVE | MEM_TOP_DOWN , PAGE_NOACCESS ) ; if ( ! res ) w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "VirtualAlloc" ) ; else VirtualFree ( res , 0 , MEM_RELEASE ) ; return res ; } </s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSIWithSVE
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
std
::
vector
<
CalleeSavedInfo
>
CSI
;
for
(
unsigned
i
=
0
;
i
<
CSIWithSVE
.
size
(
)
;
++
i
)
{
if
(
MFI
->
getStackRegionToHandleCSR
(
CSIWithSVE
[
i
]
.
getReg
(
)
)
!=
nullptr
)
continue
;
CSI
.
push_back
(
CSIWithSVE
[
i
]
)
;
}
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
begin
(
)
,
RPIE
=
RegPairs
.
end
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
if
(
MFI
->
getStackRegionToHandleCSR
(
Reg1
)
)
continue
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
static
void
pa_output_function_prologue
(
FILE
*
file
)
{
ASM_OUTPUT_LABEL
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
)
;
fputs
(
"\t.PROC\n"
,
file
)
;
fprintf
(
file
,
"\t.CALLINFO FRAME="
HOST_WIDE_INT_PRINT_DEC
,
actual_fsize
)
;
if
(
crtl
->
is_leaf
)
fputs
(
",NO_CALLS"
,
file
)
;
else
fputs
(
",CALLS"
,
file
)
;
if
(
rp_saved
)
fputs
(
",SAVE_RP"
,
file
)
;
if
(
frame_pointer_needed
)
fputs
(
",SAVE_SP"
,
file
)
;
if
(
gr_saved
)
fprintf
(
file
,
",ENTRY_GR=%d"
,
gr_saved
+
2
)
;
if
(
fr_saved
)
fprintf
(
file
,
",ENTRY_FR=%d"
,
fr_saved
+
11
)
;
fputs
(
"\n\t.ENTRY\n"
,
file
)
;
remove_useless_addtr_insns
(
0
)
;
}
</s>

On HP-PA , move-double insns between fpu and cpu need an 8-byte block of memory . If any fpu reg is used in the function , we allocate such a block here , at the bottom of the frame , just in case it 's needed . If this function is a leaf procedure , then we may choose not to do a `` save '' insn . The decision about whether or not to do this is made in regclass.c .


<s> static int rs6000_hard_regno_mode_ok ( int regno , machine_mode mode ) { int last_regno = regno + rs6000_hard_regno_nregs [ mode ] [ regno ] - 1 ; if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & 1 ) == 0 ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || ( TARGET_VSX_TIMODE && mode == TImode ) || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) != 16 && ! reg_addr [ mode ] . scalar_in_vmx_p ) return 0 ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( FLOAT128_VECTOR_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % 2 ) == 0 ) && FP_REGNO_P ( last_regno ) ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return 1 ; if ( TARGET_VSX_SMALL_INTEGER ) { if ( mode == SImode ) return 1 ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return 1 ; } } if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return 1 ; return 0 ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return 1 ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s>
const
char
*
nds32_output_float_store
(
rtx
*
operands
)
{
char
buff
[
100
]
;
const
char
*
pattern
;
rtx
addr
,
addr_op0
,
addr_op1
;
int
dp
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
8
;
addr
=
XEXP
(
operands
[
0
]
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
pattern
=
"fs%ci\t%%1, %%0"
;
break
;
case
PLUS
:
addr_op0
=
XEXP
(
addr
,
0
)
;
addr_op1
=
XEXP
(
addr
,
1
)
;
if
(
REG_P
(
addr_op0
)
&&
REG_P
(
addr_op1
)
)
pattern
=
"fs%c\t%%1, %%0"
;
else
if
(
REG_P
(
addr_op0
)
&&
CONST_INT_P
(
addr_op1
)
)
pattern
=
"fs%ci\t%%1, %%0"
;
else
if
(
GET_CODE
(
addr_op0
)
==
MULT
&&
REG_P
(
addr_op1
)
&&
REG_P
(
XEXP
(
addr_op0
,
0
)
)
&&
CONST_INT_P
(
XEXP
(
addr_op0
,
1
)
)
)
pattern
=
"fs%c\t%%1, %%0"
;
else
gcc_unreachable
(
)
;
break
;
case
POST_MODIFY
:
addr_op0
=
XEXP
(
addr
,
0
)
;
addr_op1
=
XEXP
(
addr
,
1
)
;
if
(
REG_P
(
addr_op0
)
&&
GET_CODE
(
addr_op1
)
==
PLUS
&&
REG_P
(
XEXP
(
addr_op1
,
1
)
)
)
pattern
=
"fs%c.bi\t%%1, %%0"
;
else
if
(
REG_P
(
addr_op0
)
&&
GET_CODE
(
addr_op1
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
addr_op1
,
1
)
)
)
pattern
=
"fs%ci.bi\t%%1, %%0"
;
else
gcc_unreachable
(
)
;
break
;
case
POST_INC
:
if
(
REG_P
(
XEXP
(
addr
,
0
)
)
)
{
if
(
dp
)
pattern
=
"fs%ci.bi\t%%1, %%0, 8"
;
else
pattern
=
"fs%ci.bi\t%%1, %%0, 4"
;
}
else
gcc_unreachable
(
)
;
break
;
case
POST_DEC
:
if
(
REG_P
(
XEXP
(
addr
,
0
)
)
)
{
if
(
dp
)
pattern
=
"fs%ci.bi\t%%1, %%0, -8"
;
else
pattern
=
"fs%ci.bi\t%%1, %%0, -4"
;
}
else
gcc_unreachable
(
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
sprintf
(
buff
,
pattern
,
dp
'd'
:
's'
)
;
output_asm_insn
(
buff
,
operands
)
;
return
""
;
}
</s>


<s> bool hasFusion ( ) const { return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseCCSelect ( ) || hasFuseLiterals ( ) ; } </s>

Return true if the CPU supports any kind of instruction fusion .


"LowerFormalArguments Unhandled argument type: "

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static void fold_mergehl_helper ( gimple_stmt_iterator * gsi , gimple * stmt , int use_high ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree lhs_type = TREE_TYPE ( lhs ) ; tree lhs_type_type = TREE_TYPE ( lhs_type ) ; int n_elts = TYPE_VECTOR_SUBPARTS ( lhs_type ) ; int midpoint = n_elts / 2 ; int offset = 0 ; if ( use_high == 1 ) offset = midpoint ; tree_vector_builder elts ( lhs_type , VECTOR_CST_NELTS ( arg0 ) , 1 ) ; for ( int i = 0 ; i < midpoint ; i ++ ) { elts . safe_push ( build_int_cst ( lhs_type_type , offset + i ) ) ; elts . safe_push ( build_int_cst ( lhs_type_type , offset + n_elts + i ) ) ; } tree permute = elts . build ( ) ; gimple * g = gimple_build_assign ( lhs , VEC_PERM_EXPR , arg0 , arg1 , permute ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the vector merge [ hl ] built-ins . The implementation difference between h and l versions for this code are in the values used when building of the permute vector for high word versus low word merge . The variance is keyed off the use_high parameter .