<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_SaveList ; return CSR_SystemZ_SaveList ; } </s>


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


"  /* The fndecl for an overload is arbitrarily the first one\n"

"     for the overload.  We sort out the real types when\n"

"     processing the overload in the gcc front end.  */\n"

"  rs6000_builtin_decls[(int)RS6000_OVLD_%s] = t\n"

"                            NULL, NULL_TREE);\n"

"  rs6000_overload_info[RS6000_OVLD_%s - base]"

"    = &rs6000_instance_info[RS6000_INST_%s];\n\n"

Write code to initialize the overload table .

"                            NULL, NULL_TREE);\n"


<s> Optional < MCFixupKind > getFixupKind ( StringRef Name ) const override { unsigned Type ; Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_SPARC_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_SPARC_8 ) . Case ( "BFD_RELOC_16" , ELF :: R_SPARC_16 ) . Case ( "BFD_RELOC_32" , ELF :: R_SPARC_32 ) . Case ( "BFD_RELOC_64" , ELF :: R_SPARC_64 ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static bool ix86_function_ok_for_sibcall ( tree decl , tree exp ) { tree type , decl_or_type ; rtx a , b ; bool bind_global = decl && ! targetm . binds_local_p ( decl ) ; if ( cfun -> machine -> no_caller_saved_registers ) return false ; if ( ! TARGET_MACHO && ! TARGET_64BIT && flag_pic && flag_plt && bind_global ) return false ; if ( ix86_minimum_incoming_stack_boundary ( true ) < PREFERRED_STACK_BOUNDARY ) return false ; if ( decl ) { decl_or_type = decl ; type = TREE_TYPE ( decl ) ; } else { type = CALL_EXPR_FN ( exp ) ; type = TREE_TYPE ( type ) ; type = TREE_TYPE ( type ) ; decl_or_type = type ; } a = ix86_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT ) { if ( cfun -> machine -> call_abi == MS_ABI && ix86_function_type_abi ( type ) == SYSV_ABI ) return false ; } else { if ( ! decl || ( bind_global && flag_pic && ! flag_plt ) || ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P ( decl ) ) ) { if ( ix86_function_regparm ( type , NULL ) >= 3 && ! cfun -> machine -> arg_reg_available ) return false ; } } return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> bool aarch64_regno_ok_for_base_p ( int regno , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; } return ( GP_REGNUM_P ( regno ) || regno == SP_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return true if register REGNO is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s> static int arm_cortex_m_branch_cost ( bool speed_p , bool predictable_p ) { return ( TARGET_32BIT && speed_p ) ? 1 : arm_default_branch_cost ( speed_p , predictable_p ) ; } </s>

Thumb-2 branches are relatively cheap on Cortex-M processors ( `` 1 + P cycles '' on Cortex-M4 , where P varies from 1 to 3 according to some criteria ) , since sequences of non-executed instructions in IT blocks probably take the same amount of time as executed instructions ( and the IT instruction itself takes space in icache ) . This function was experimentally determined to give good results on a popular embedded benchmark .


<s> bool shouldBuildLookupTables ( ) const { return false ; } </s>

Return true if switches should be turned into lookup tables for the target .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
(
unsigned
)
Fixup
.
getKind
(
)
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
dyn_cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


<s>
bool
AArch64PostLegalizerLowering
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Legalized
)
&&
"Expected a legalized function?"
)
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
AArch64PostLegalizerLoweringInfo
PCInfo
(
F
.
hasOptSize
(
)
,
F
.
hasMinSize
(
)
)
;
Combiner
C
(
PCInfo
,
TPC
)
;
return
C
.
combineMachineInstrs
(
MF
,
nullptr
)
;
}
</s>

runOnMachineFunction - Emit the function body .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s>
void
SystemZHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCSchedClassDesc
*
SC
=
getSchedClass
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"++ HazardRecognizer emitting "
;
dumpSU
(
SU
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
DEBUG
(
dumpCurrGroup
(
"Decode group before emission"
)
;
)
;
if
(
!
fitsIntoCurrentGroup
(
SU
)
)
nextGroup
(
)
;
DEBUG
(
raw_string_ostream
cgd
(
CurGroupDbg
)
;
if
(
CurGroupDbg
.
length
(
)
)
cgd
<<
", "
;
dumpSU
(
SU
,
cgd
)
;
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
if
(
SU
->
isCall
)
{
DEBUG
(
dbgs
(
)
<<
"++ Clearing state after call.\n"
;
)
;
Reset
(
)
;
LastEmittedMI
=
SU
->
getInstr
(
)
;
return
;
}
for
(
TargetSchedModel
::
ProcResIter
PI
=
SchedModel
->
getWriteProcResBegin
(
SC
)
,
PE
=
SchedModel
->
getWriteProcResEnd
(
SC
)
;
PI
!=
PE
;
++
PI
)
{
if
(
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
BufferSize
==
1
)
continue
;
int
&
CurrCounter
=
ProcResourceCounters
[
PI
->
ProcResourceIdx
]
;
CurrCounter
+=
PI
->
Cycles
;
if
(
(
CurrCounter
>
ProcResCostLim
)
&&
(
CriticalResourceIdx
==
UINT_MAX
||
(
PI
->
ProcResourceIdx
!=
CriticalResourceIdx
&&
CurrCounter
>
ProcResourceCounters
[
CriticalResourceIdx
]
)
)
)
{
DEBUG
(
dbgs
(
)
<<
"++ New critical resource: "
<<
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
Name
<<
"\n"
;
)
;
CriticalResourceIdx
=
PI
->
ProcResourceIdx
;
}
}
if
(
SU
->
isUnbuffered
)
{
LastFPdOpCycleIdx
=
getCurrCycleIdx
(
SU
)
;
DEBUG
(
dbgs
(
)
<<
"++ Last FPd cycle index: "
<<
LastFPdOpCycleIdx
<<
"\n"
;
)
;
}
CurrGroupSize
+=
getNumDecoderSlots
(
SU
)
;
assert
(
CurrGroupSize
<=
3
)
;
if
(
CurrGroupSize
==
3
||
SC
->
EndGroup
)
nextGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

SystemZ
SystemZ
"++ HazardRecognizer emitting "
"\n"
"Decode group before emission"
", "
"++ Clearing state after call.\n"
1
"++ New critical resource: "
"\n"
"++ Last FPd cycle index: "
"\n"
3
3


<s> machreg_t semctl ( machreg_t semid , machreg_t semnum , machreg_t cmd , machreg_t arg ) { return _semctl ( semid , semnum , cmd , arg << SHIFT_BITS ) ; } </s>

< sys/sem.h > has int semctl ( int , int , int , ... ) ; where the variadic argument is union semun if used . union semun contains an int and two pointers , so the union is already 64 bits wide under the N64 ABI and alignment is not an issue .


<s> static void arm_emit_multi_reg_pop ( unsigned long saved_regs_mask ) { int num_regs = 0 ; int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( 1 << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? 1 : 0 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 16 ) ; emit_update = ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ? 0 : 1 ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , 0 , 0 ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , offset_adj ) = tmp ; } for ( j = 0 , i = 0 ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) { rtx dwarf_reg = reg = gen_rtx_REG ( SImode , i ) ; if ( arm_current_function_pac_enabled_p ( ) && i == IP_REGNUM ) dwarf_reg = gen_rtx_REG ( SImode , RA_AUTH_CODE ) ; if ( ( num_regs == 1 ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , dwarf_reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , dwarf_reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( ! return_in_pc ) arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD * num_regs , stack_pointer_rtx , stack_pointer_rtx ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi . SAVED_REGS_MASK shows which registers need to be restored . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( PPC :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> void rs6000_emit_eh_reg_restore ( rtx source , rtx scratch ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx operands [ 2 ] ; operands [ 0 ] = source ; operands [ 1 ] = scratch ; if ( info -> lr_save_p ) { rtx frame_rtx = stack_pointer_rtx ; HOST_WIDE_INT sp_offset = 0 ; rtx tmp ; if ( frame_pointer_needed || cfun -> calls_alloca || info -> total_size > 32767 ) { tmp = gen_frame_mem ( Pmode , frame_rtx ) ; emit_move_insn ( operands [ 1 ] , tmp ) ; frame_rtx = operands [ 1 ] ; } else if ( info -> push_p ) sp_offset = info -> total_size ; tmp = plus_constant ( Pmode , frame_rtx , info -> lr_save_offset + sp_offset ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_move_insn ( tmp , operands [ 0 ] ) ; } else emit_move_insn ( gen_rtx_REG ( Pmode , LR_REGNO ) , operands [ 0 ] ) ; cfun -> machine -> lr_save_state = info -> lr_save_p + 1 ; } </s>

Emit instructions to restore the link register after determining where its value has been stored .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) || TT . isOSWindows ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) , GISel ( ) { GISelAccessor * AArch64GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * AArch64GISel = new AArch64GISelActualAccessor ( ) ; AArch64GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; AArch64GISel -> Legalizer . reset ( new AArch64LegalizerInfo ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; AArch64GISel -> InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; AArch64GISel -> RegBankInfo . reset ( RBI ) ; setGISelAccessor ( * AArch64GISel ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s>
const
char
*
mips_output_order_conditional_branch
(
rtx_insn
*
insn
,
rtx
*
operands
,
bool
inverted_p
)
{
const
char
*
branch
[
2
]
;
if
(
operands
[
3
]
!=
const0_rtx
)
{
if
(
REGNO
(
operands
[
2
]
)
==
REGNO
(
operands
[
3
]
)
)
{
switch
(
GET_CODE
(
operands
[
1
]
)
)
{
case
LT
:
case
LTU
:
inverted_p
=
!
inverted_p
;
case
GE
:
case
GEU
:
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b"
,
"%0"
)
;
branch
[
inverted_p
]
=
"%*\t\t# branch never"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b%C1"
,
"%2,%3,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"b%N1"
,
"%2,%3,%0"
)
;
}
}
else
{
switch
(
GET_CODE
(
operands
[
1
]
)
)
{
case
LEU
:
inverted_p
=
!
inverted_p
;
case
GTU
:
if
(
TARGET_CB_MAYBE
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"bnez"
,
"%2,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"beqz"
,
"%2,%0"
)
;
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH
(
"bne"
,
"%2,%.,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH
(
"beq"
,
"%2,%.,%0"
)
;
}
break
;
case
LTU
:
inverted_p
=
!
inverted_p
;
case
GEU
:
if
(
TARGET_CB_MAYBE
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b"
,
"%0"
)
;
branch
[
inverted_p
]
=
"%*\t\t# branch never"
;
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH
(
"beq"
,
"%.,%.,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH
(
"bne"
,
"%.,%.,%0"
)
;
}
break
;
default
:
if
(
TARGET_CB_MAYBE
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b%C1z"
,
"%2,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"b%N1z"
,
"%2,%0"
)
;
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH
(
"b%C1z"
,
"%2,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH
(
"b%N1z"
,
"%2,%0"
)
;
}
break
;
}
}
return
mips_output_conditional_branch
(
insn
,
operands
,
branch
[
1
]
,
branch
[
0
]
)
;
}
</s>

Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some ordering condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; its second is always zero .


<s> const TOYRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static inline bool offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED , poly_int64 offset ) { HOST_WIDE_INT const_offset ; return ( offset . is_constant ( & const_offset ) && IN_RANGE ( const_offset , - 256 , 255 ) ) ; } </s>

Return true if OFFSET is a signed 9-bit value .


<s> bool isIncomingArgumentHandler ( ) const override { return false ; } </s>

Returns true if the handler is dealing with incoming arguments , i.e .


Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .

aarch64
"\t.arch %s\n"
"\t"
".tune %s\n"
"function"


<s> static const predefined_function_abi & aarch64_fntype_abi ( const_tree fntype ) { if ( lookup_attribute ( "aarch64_vector_pcs" , TYPE_ATTRIBUTES ( fntype ) ) ) return aarch64_simd_abi ( ) ; if ( aarch64_returns_value_in_sve_regs_p ( fntype ) || aarch64_takes_arguments_in_sve_regs_p ( fntype ) ) return aarch64_sve_abi ( ) ; return default_function_abi ; } </s>


<s> static void arm_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { if ( mode == SImode ) gcc_assert ( ! TARGET_IDIV ) ; machine_mode libval_mode = smallest_mode_for_size ( 2 * GET_MODE_BITSIZE ( mode ) , MODE_INT ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , 2 , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) ) ; rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , 0 ) ; rtx remainder = simplify_gen_subreg ( mode , libval , libval_mode , GET_MODE_SIZE ( mode ) ) ; gcc_assert ( quotient ) ; gcc_assert ( remainder ) ; * quot_p = quotient ; * rem_p = remainder ; } </s>

Generate call to __aeabi_ [ mode ] divmod ( op0 , op1 ) .


<s> static int rs6000_emit_p9_fp_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode result_mode = GET_MODE ( dest ) ; rtx compare_rtx ; rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return 0 ; switch ( code ) { case EQ : case GE : case GT : break ; case NE : case LT : case LE : code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : return 0 ; } compare_rtx = gen_rtx_fmt_ee ( code , CCFPmode , op0 , op1 ) ; cmove_rtx = gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , compare_rtx , true_cond , false_cond ) ) ; clobber_rtx = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( V2DImode ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , cmove_rtx , clobber_rtx ) ) ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) conditional move subcase to emit XSCMP { EQ , GE , GT , NE } DP and XXSEL instructions for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s> int getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


<s> bool ARMBaseInstrInfo :: PredicateInstruction ( MachineInstr & MI , ArrayRef < MachineOperand > Pred ) const { unsigned Opc = MI . getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI . setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ 0 ] . getImm ( ) ) . addReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI . getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI . getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> static void or1k_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int nreg = CEIL ( GET_MODE_SIZE ( arg . mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= 2 ) ; if ( arg . named ) * cum += nreg ; } </s>

Worker for TARGET_FUNCTION_ARG_ADVANCE . Update the cumulative args descriptor CUM_V to advance past the next function argument . Note , this is not called for arguments passed on the stack .


<s> bool X86TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return needsCmpXchgNb ( SI -> getValueOperand ( ) -> getType ( ) ) ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> static ARMOperand * CreateMem ( unsigned BaseRegNum , const MCConstantExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E ) { ARMOperand * Op = new ARMOperand ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; ( void ) SPAdj ; ( void ) RS ; bool LP64 = Subtarget . isPPC64 ( ) ; unsigned Reg = Subtarget . isDarwinABI ( ) ? ( LP64 ? PPC :: X2 : PPC :: R2 ) : ( LP64 ? PPC :: X0 : PPC :: R0 ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFCR8pseud : PPC :: MFCRpseud ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( getPPCRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( 1 ) . getImm ( ) ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static rtx address_offset ( rtx op ) { if ( GET_CODE ( op ) == PRE_INC || GET_CODE ( op ) == PRE_DEC ) op = XEXP ( op , 0 ) ; else if ( GET_CODE ( op ) == PRE_MODIFY || GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == PLUS ) op = XEXP ( op , 1 ) ; if ( CONST_INT_P ( op ) ) return op ; return NULL_RTX ; } </s>

Given an address , return a constant offset term if one exists .


<s> bool rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; machine_mode mode = GET_MODE ( dest ) ; enum rtx_code cond_code ; rtx ( * isel_func ) ( rtx , rtx , rtx , rtx , rtx ) ; bool signedp ; if ( mode != SImode && ( ! TARGET_POWERPC64 || mode != DImode ) ) return false ; if ( GET_MODE_CLASS ( GET_MODE ( XEXP ( op , 0 ) ) ) == MODE_CC ) return false ; condition_rtx = rs6000_generate_compare ( op , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; cr = XEXP ( condition_rtx , 0 ) ; signedp = GET_MODE ( cr ) == CCmode ; isel_func = ( mode == SImode ? ( signedp ? gen_isel_signed_si : gen_isel_unsigned_si ) : ( signedp ? gen_isel_signed_di : gen_isel_unsigned_di ) ) ; switch ( cond_code ) { case LT : case GT : case LTU : case GTU : case EQ : break ; default : { std :: swap ( false_cond , true_cond ) ; PUT_CODE ( condition_rtx , reverse_condition ( cond_code ) ) ; } break ; } false_cond = force_reg ( mode , false_cond ) ; if ( true_cond != const0_rtx ) true_cond = force_reg ( mode , true_cond ) ; emit_insn ( isel_func ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return true ; } </s>


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned AArch64AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { AArch64Operand & Op = static_cast < AArch64Operand & > ( AsmOp ) ; int64_t ExpectedVal ; switch ( Kind ) { default : return Match_InvalidOperand ; case MCK__HASH_0 : ExpectedVal = 0 ; break ; case MCK__HASH_1 : ExpectedVal = 1 ; break ; case MCK__HASH_12 : ExpectedVal = 12 ; break ; case MCK__HASH_16 : ExpectedVal = 16 ; break ; case MCK__HASH_2 : ExpectedVal = 2 ; break ; case MCK__HASH_24 : ExpectedVal = 24 ; break ; case MCK__HASH_3 : ExpectedVal = 3 ; break ; case MCK__HASH_32 : ExpectedVal = 32 ; break ; case MCK__HASH_4 : ExpectedVal = 4 ; break ; case MCK__HASH_48 : ExpectedVal = 48 ; break ; case MCK__HASH_6 : ExpectedVal = 6 ; break ; case MCK__HASH_64 : ExpectedVal = 64 ; break ; case MCK__HASH_8 : ExpectedVal = 8 ; break ; case MCK_MPR : if ( Op . isTokenEqual ( "za" ) ) return Match_Success ; break ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> SDValue PPCTargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget . isPPC64 ( ) || Subtarget . isAIXABI ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; default : return DAG . getNode ( PPCISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } } </s>

Returns relocation base for the given PIC jumptable .


<s> static char * aarch64_offload_options ( void ) { if ( TARGET_ILP32 ) return xstrdup ( "-foffload-abi=ilp32" ) ; else return xstrdup ( "-foffload-abi=lp64" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


<s> static void rs6000_init_dwarf_reg_sizes_extra ( tree address ) { if ( TARGET_SPE ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 4 , mode ) ; for ( i = FIRST_SPE_HIGH_REGNO ; i < LAST_SPE_HIGH_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } if ( TARGET_MACHO && ! TARGET_ALTIVEC ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 16 , mode ) ; for ( i = FIRST_ALTIVEC_REGNO ; i < LAST_ALTIVEC_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } } </s>

Fill in sizes of registers used by unwinder .


<s> void Cpu0InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const ARMMCExpr * ARMMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) ARMMCExpr ( Kind , Expr ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case E_V2HImode : case E_V4QImode : case E_V2HQmode : case E_V2UHQmode : case E_V2HAmode : case E_V2UHAmode : case E_V4QQmode : case E_V4UQQmode : return TARGET_DSP ; case E_V2SImode : case E_V4HImode : case E_V8QImode : return TARGET_LOONGSON_MMI ; default : return MSA_SUPPORTED_MODE_P ( mode ) ; } } </s>

Target hook for vector_mode_supported_p .


<s> bool MipsInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { switch ( MI . getOpcode ( ) ) { case Mips :: EXT : case Mips :: EXT_MM : case Mips :: INS : case Mips :: INS_MM : case Mips :: DINS : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 0 , 32 , 0 , 32 ) ; case Mips :: DINSM : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 1 , 64 , 32 , 64 ) ; case Mips :: DINSU : return verifyInsExtInstruction ( MI , ErrInfo , 32 , 64 , 0 , 32 , 32 , 64 ) ; case Mips :: DEXT : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 0 , 32 , 0 , 63 ) ; case Mips :: DEXTM : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 32 , 64 , 32 , 64 ) ; case Mips :: DEXTU : return verifyInsExtInstruction ( MI , ErrInfo , 32 , 64 , 0 , 32 , 32 , 64 ) ; default : return true ; } return true ; } </s>

Perform target-specific instruction verification .


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextVector CallSeqVector ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext Context ; collectCallInfo ( MF , * BB , I , Context ) ; CallSeqVector . push_back ( Context ) ; } if ( ! isProfitable ( MF , CallSeqVector ) ) return false ; for ( auto CC : CallSeqVector ) if ( CC . UsePush ) Changed |= adjustCallSequence ( MF , CC ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> const SystemZRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void or1k_expand_prologue ( void ) { HOST_WIDE_INT sp_offset = - cfun -> machine -> total_size ; HOST_WIDE_INT reg_offset , this_offset ; rtx insn ; if ( flag_stack_usage_info ) current_function_static_stack_size = - sp_offset ; if ( sp_offset == 0 ) goto fini ; reg_offset = ( sp_offset + cfun -> machine -> local_vars_size + cfun -> machine -> args_size ) ; this_offset = MAX ( sp_offset , - 32764 ) ; reg_offset -= this_offset ; sp_offset -= this_offset ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( this_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; for ( int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regno != HARD_FRAME_POINTER_REGNUM && regno != LR_REGNUM && callee_saved_regno_p ( regno ) ) { or1k_save_reg ( regno , reg_offset ) ; reg_offset += UNITS_PER_WORD ; } if ( callee_saved_regno_p ( HARD_FRAME_POINTER_REGNUM ) ) { or1k_save_reg ( HARD_FRAME_POINTER_REGNUM , reg_offset ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( - this_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } reg_offset += UNITS_PER_WORD ; } if ( callee_saved_regno_p ( LR_REGNUM ) ) { or1k_save_reg ( LR_REGNUM , reg_offset ) ; reg_offset += UNITS_PER_WORD ; } gcc_assert ( reg_offset + this_offset == 0 ) ; if ( sp_offset != 0 ) { if ( sp_offset < 2 * - 32768 ) { rtx tmp = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( tmp , GEN_INT ( sp_offset ) ) ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; if ( ! frame_pointer_needed ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ) ; } } else { do { this_offset = MAX ( sp_offset , - 32768 ) ; sp_offset -= this_offset ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( this_offset ) ) ) ; if ( ! frame_pointer_needed ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } while ( sp_offset != 0 ) ; } } fini : rtx_insn * set_got_insn = cfun -> machine -> set_got_insn ; if ( crtl -> uses_pic_offset_table ) { rtx reg = SET_DEST ( PATTERN ( set_got_insn ) ) ; rtx_insn * insn = emit_insn_before ( gen_set_got ( reg ) , set_got_insn ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_FLUSH_QUEUE , NULL_RTX ) ; } delete_insn ( set_got_insn ) ; } </s>


<s> bool CAHPMCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } </s>

Evaluates the fixup as a constant value .


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == MVT :: f32 ) return ARM :: getVFPf32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 ) return ARM :: getVFPf64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> StringRef getPassName ( ) const override { return "AArch64PostLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


"This resolveFrameIndex does not support Thumb1!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( machine_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) + 1 ) >= 0 && ( INTVAL ( mask ) & ( ( 1 << INTVAL ( shft_amnt ) ) - 1 ) ) == 0 ; } </s>

Return true if the mask and a shift amount from an RTX of the form ( x < < SHFT_AMNT ) & MASK are valid to combine into a UBFIZ instruction of mode MODE . See the * andim_ashift < mode > _bfiz pattern .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> int sh_dwarf_calling_convention ( const_tree func ) { if ( sh_attr_renesas_p ( func ) ) return DW_CC_GNU_renesas_sh ; return DW_CC_normal ; } </s>

Implements target hook dwarf_calling_convention . Return an enum of dwarf_calling_convention .


<s>
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsCheriPureCap
(
)
)
return
{
}
;
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


<s>
void
LanaiInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
Position
,
const
DebugLoc
&
DL
,
MCRegister
DestinationRegister
,
MCRegister
SourceRegister
,
bool
KillSource
)
const
{
if
(
!
Lanai
::
GPRRegClass
.
contains
(
DestinationRegister
,
SourceRegister
)
)
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
Position
,
DL
,
get
(
Lanai
::
OR_I_LO
)
,
DestinationRegister
)
.
addReg
(
SourceRegister
,
getKillRegState
(
KillSource
)
)
.
addImm
(
0
)
;
}
</s>

Lanai
Lanai
Lanai::GPRRegClass
"Impossible reg-to-reg copy"
Lanai::OR_I_LO
0


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new ARMHazardRecognizer ( II , DAG ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


"unknown architecture specific memory model"

"%<HLE_ACQUIRE%> not used with %<ACQUIRE%> or stronger "

"%<HLE_RELEASE%> not used with %<RELEASE%> or stronger "

Validate target specific memory model bits in VAL .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 && Subtarget . hasAVX ( ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


Return true if at least one possible value of type TYPE includes at least one object of Pure Scalable Type , in the sense of the AAPCS64 . This is a relatively expensive test for some types , so it should generally be made as late as possible .


" was Pass-through, is now Dirty-out.\n"


<s> bool ix86_vec_interleave_v2df_operator_ok ( rtx operands [ 3 ] , bool high ) { if ( MEM_P ( operands [ 0 ] ) ) return rtx_equal_p ( operands [ 0 ] , operands [ 1 + high ] ) ; if ( MEM_P ( operands [ 1 ] ) && MEM_P ( operands [ 2 ] ) ) return false ; return true ; } </s>

Return TRUE if the operands to a vec_interleave_ { high , low } v2df are ok , keeping in mind the possible movddup alternative .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( createX86MacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> static machine_mode ix86_get_mask_mode ( unsigned nunits , unsigned vector_size ) { unsigned elem_size = vector_size / nunits ; if ( ( TARGET_AVX512F && vector_size == 64 ) || ( TARGET_AVX512VL && ( vector_size == 32 || vector_size == 16 ) ) ) { if ( elem_size == 4 || elem_size == 8 || TARGET_AVX512BW ) return smallest_mode_for_size ( nunits , MODE_INT ) ; } machine_mode elem_mode = smallest_mode_for_size ( elem_size * BITS_PER_UNIT , MODE_INT ) ; gcc_assert ( elem_size * nunits == vector_size ) ; return mode_for_vector ( elem_mode , nunits ) ; } </s>

Implemenation of targetm.vectorize.get_mask_mode .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM::GPRRegClassID ARM::SPRRegClassID ARM::DPRRegClassID ARM::QPRRegClassID ARM::QQPRRegClassID ARM::QQQQPRRegClassID


<s>
static
void
xstormy16_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
switch
(
code
)
{
case
'B'
:
{
static
int
bits_set
[
8
]
=
{
0
,
1
,
1
,
2
,
1
,
2
,
2
,
3
}
;
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
if
(
bits_set
[
xx
&
7
]
<=
1
)
{
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
&=
0xff
;
else
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
&=
0xffff
;
l
=
exact_log2
(
xx
)
;
}
else
{
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xff
;
else
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xffff
;
l
=
exact_log2
(
~
xx
)
;
}
if
(
l
==
1
)
output_operand_lossage
(
"'B' operand has multiple bits set"
)
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
'C'
:
if
(
GET_CODE
(
x
)
==
SYMBOL_REF
)
assemble_name
(
file
,
XSTR
(
x
,
0
)
)
;
else
if
(
LABEL_P
(
x
)
)
output_asm_label
(
x
)
;
else
xstormy16_print_operand_address
(
file
,
VOIDmode
,
x
)
;
return
;
case
'o'
:
case
'O'
:
{
HOST_WIDE_INT
xx
=
0
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'o' operand is not constant"
)
;
if
(
code
==
'O'
)
xx
=
xx
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
xx
1
)
;
return
;
}
case
'b'
:
{
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
l
=
7
xx
;
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
0
:
break
;
default
:
output_operand_lossage
(
"xstormy16_print_operand: unknown code"
)
;
return
;
}
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
fputs
(
reg_names
[
REGNO
(
x
)
]
,
file
)
;
break
;
case
MEM
:
xstormy16_print_operand_address
(
file
,
GET_MODE
(
x
)
,
XEXP
(
x
,
0
)
)
;
break
;
default
:
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
output_addr_const
(
file
,
x
)
;
break
;
}
return
;
}
</s>

Print an operand to an assembler instruction .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
SADDSAT
:
case
ISD
::
SSUBSAT
:
case
ISD
::
UADDSAT
:
case
ISD
::
USUBSAT
:
Res
=
LowerADDSUBSAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
ABS
:
lowerABS
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
LOAD
:
LowerLOAD
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
TRUNCATE
:
Res
=
LowerTruncate
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
LowerVectorExtend
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
FP_TO_SINT_SAT
:
case
ISD
::
FP_TO_UINT_SAT
:
Res
=
LowerFP_TO_INT_SAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> unsigned ARMTargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return 4 ; if ( Subtarget -> hasMVEIntegerOps ( ) ) return MVEMaxSupportedInterleaveFactor ; return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s>
static
void
rs6000_parse_yes_no_option
(
const
char
*
name
,
const
char
*
value
,
int
*
flag
)
{
if
(
value
==
0
)
return
;
else
if
(
!
strcmp
(
value
,
"yes"
)
)
*
flag
=
1
;
else
if
(
!
strcmp
(
value
,
"no"
)
)
*
flag
=
0
;
else
error
(
"unknown -m%s= option specified: '%s'"
,
name
,
value
)
;
}
</s>

Handle generic options of the form -mfoo=yes/no . NAME is the option name . VALUE is the option value . FLAG is the pointer to the flag where to store a 1 or 0 , depending on whether the option value is 'yes ' or 'no ' respectively .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getDarwinDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: DIR_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: DIR_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR8 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR9 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> bool free_insn_info ( const rtx & t ATTRIBUTE_UNUSED , insn_info_list_t * v , void * arg ATTRIBUTE_UNUSED ) { while ( v -> length ( ) > 0 ) delete v -> pop ( ) ; return true ; } </s>

Callback to free all tag_insn_info objects .


<s> bool aarch64_sve_float_mul_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && GET_CODE ( elt ) == CONST_DOUBLE && real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconsthalf ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE FMUL instruction .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> static rtx_insn * get_next_active_insn ( rtx_insn * insn , rtx_insn * tail ) { if ( insn == NULL_RTX || insn == tail ) return NULL ; while ( 1 ) { insn = NEXT_INSN ( insn ) ; if ( insn == NULL_RTX || insn == tail ) return NULL ; if ( CALL_P ( insn ) || JUMP_P ( insn ) || JUMP_TABLE_DATA_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && INSN_CODE ( insn ) != CODE_FOR_stack_tie ) ) break ; } return insn ; } </s>

Return the next insn after INSN that is found before TAIL is reached , skipping any `` non-active '' insns - insns that will not actually occupy an issue slot . Return NULL_RTX if such an insn is not found .


"PPC hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> bool MipsSubtarget :: enablePostRAScheduler ( ) const { return true ; } </s>

True if the subtarget should run a scheduler after register allocation .


This function is called when the end of a window processing is reached .


<s> const VEMCExpr * VEMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) VEMCExpr ( Kind , Expr ) ; } </s>


<s> enum aarch64_symbol_type aarch64_classify_tls_symbol ( rtx x ) { enum tls_model tls_kind = tls_symbolic_operand_type ( x ) ; switch ( tls_kind ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : return TARGET_TLS_DESC ? SYMBOL_SMALL_TLSDESC : SYMBOL_SMALL_TLSGD ; case TLS_MODEL_INITIAL_EXEC : return SYMBOL_SMALL_GOTTPREL ; case TLS_MODEL_LOCAL_EXEC : return SYMBOL_SMALL_TPREL ; case TLS_MODEL_EMULATED : case TLS_MODEL_NONE : return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } </s>

Classify a TLS symbol into one of the TLS kinds .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> isPredicable ( ) ) return false ; ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . hasV8Ops ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> unsigned MipsInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( ( MI -> getOpcode ( ) == Mips :: LW ) || ( MI -> getOpcode ( ) == Mips :: LWC1 ) || ( MI -> getOpcode ( ) == Mips :: LDC1 ) ) { if ( ( MI -> getOperand ( 2 ) . isFI ( ) ) && ( MI -> getOperand ( 1 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 1 ) ) ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s>
static
void
adjust_splat
(
rtx_insn
*
insn
)
{
rtx
body
=
PATTERN
(
insn
)
;
rtx
unspec
=
XEXP
(
body
,
1
)
;
int
half_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
unspec
)
)
>>
1
;
int
lane
=
INTVAL
(
XVECEXP
(
unspec
,
0
,
1
)
)
;
lane
=
lane
>=
half_elts
lane
half_elts
:
lane
+
half_elts
;
XVECEXP
(
unspec
,
0
,
1
)
=
GEN_INT
(
lane
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lane for splat %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a vector direct-splat operation , adjust the index of the source lane to account for the doubleword swap .


<s> rtx sh_try_omit_signzero_extend ( rtx extended_op , rtx_insn * insn ) { if ( REG_P ( extended_op ) ) extended_op = extended_op ; else if ( GET_CODE ( extended_op ) == SUBREG && REG_P ( SUBREG_REG ( extended_op ) ) ) extended_op = SUBREG_REG ( extended_op ) ; else return NULL_RTX ; if ( GET_MODE ( extended_op ) != SImode ) return NULL_RTX ; set_of_reg s = sh_find_set_of_reg ( extended_op , insn , prev_nonnote_nondebug_insn_bb ) ; if ( s . set_src == NULL_RTX ) return NULL_RTX ; if ( t_reg_operand ( s . set_src , VOIDmode ) || negt_reg_operand ( s . set_src , VOIDmode ) ) return extended_op ; else if ( sh_is_logical_t_store_expr ( s . set_src , s . insn ) ) return extended_op ; return NULL_RTX ; } </s>

Given the operand that is extended in a sign/zero extend insn , and the insn , try to figure out whether the sign/zero extension can be replaced by a simple reg-reg copy . If so , the replacement reg rtx is returned , NULL_RTX otherwise .


"TODO implement argument passing on stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> int mmix_print_operand_punct_valid_p ( int code ATTRIBUTE_UNUSED ) { return code == '+' || code == '.' ; } </s>


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; case 'x' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) ) return true ; Register Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; if ( PPCInstrInfo :: isVRRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: V0 ) ; else if ( PPCInstrInfo :: isVFRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: VF0 ) ; const char * RegName ; RegName = PPCInstPrinter :: getRegisterName ( Reg ) ; RegName = PPCRegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool X86TTIImpl :: isLegalMaskedScatter ( Type * DataType ) { if ( ! ST -> hasAVX512 ( ) ) return false ; return isLegalMaskedGather ( DataType ) ; } </s>

Return true if the target supports masked scatter .


<s> void DCPU16InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc = DCPU16 :: MOV16rr ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> bool aarch64_regno_ok_for_index_p ( int regno , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; } return GP_REGNUM_P ( regno ) ; } </s>

Return true if register REGNO is a valid index register . STRICT_P is true if REG_OK_STRICT is in effect .


<s> unsigned X86TargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) == 64 && ! Subtarget . hasBWI ( ) ) || VT . getVectorNumElements ( ) > 64 ) ) { RegisterVT = MVT :: i8 ; IntermediateVT = MVT :: i1 ; NumIntermediates = VT . getVectorNumElements ( ) ; return NumIntermediates ; } if ( VT == MVT :: v64i1 && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && CC != CallingConv :: X86_RegCall ) { RegisterVT = MVT :: v32i8 ; IntermediateVT = MVT :: v32i1 ; NumIntermediates = 2 ; return 2 ; } return TargetLowering :: getVectorTypeBreakdownForCallingConv ( Context , CC , VT , IntermediateVT , NumIntermediates , RegisterVT ) ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void mips_expand_atomic_qihi ( union mips_gen_fn_ptrs generator , rtx result , rtx mem , rtx oldval , rtx newval ) { rtx orig_addr , memsi_addr , memsi , shift , shiftsi , unshifted_mask ; rtx unshifted_mask_reg , mask , inverted_mask , si_op ; rtx res = NULL ; machine_mode mode ; mode = GET_MODE ( mem ) ; orig_addr = force_reg ( Pmode , XEXP ( mem , 0 ) ) ; memsi_addr = mips_force_binary ( Pmode , AND , orig_addr , force_reg ( Pmode , GEN_INT ( - 4 ) ) ) ; memsi = gen_rtx_MEM ( SImode , memsi_addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = mips_force_binary ( Pmode , AND , orig_addr , GEN_INT ( 3 ) ) ; if ( TARGET_BIG_ENDIAN ) mips_emit_binary ( XOR , shift , shift , GEN_INT ( mode == QImode ? 3 : 2 ) ) ; mips_emit_binary ( ASHIFT , shift , shift , GEN_INT ( 3 ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = mips_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = mips_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = mips_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , newval ) ; else if ( result ) si_op = generator . fn_5 ( res , memsi , mask , inverted_mask , oldval ) ; else si_op = generator . fn_4 ( memsi , mask , inverted_mask , oldval ) ; emit_insn ( si_op ) ; if ( result ) { mips_emit_binary ( AND , res , res , mask ) ; mips_emit_binary ( LSHIFTRT , res , res , shiftsi ) ; mips_emit_move ( result , gen_lowpart ( GET_MODE ( result ) , res ) ) ; } } </s>

Expand a QI or HI mode atomic memory operation . GENERATOR contains a pointer to the gen_ * function that generates the SI mode underlying atomic operation using masks that we calculate . RESULT is the return register for the operation . Its value is NULL if unused . MEM is the location of the atomic access . OLDVAL is the first operand for the operation . NEWVAL is the optional second operand for the operation . Its value is NULL if unused .


<s> void LC3PassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void OutgoingValueHandler :: assignValueToAddress ( Register ValVReg , const CCValAssign & VA ) { MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI . getOpcode ( ) , Subtarget ) ) return 0 ; const MachineOperand & MO = MI . getOperand ( 0 ) ; Register Reg = MO . getReg ( ) ; if ( Reg . isVirtual ( ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return 0 ; } return PartialRegUpdateClearance ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> bool rx_can_use_simple_return ( void ) { unsigned int low ; unsigned int high ; unsigned int frame_size ; unsigned int stack_size ; unsigned int register_mask ; if ( is_naked_func ( NULL_TREE ) || is_fast_interrupt_func ( NULL_TREE ) || is_interrupt_func ( NULL_TREE ) ) return false ; rx_get_stack_layout ( & low , & high , & register_mask , & frame_size , & stack_size ) ; return ( register_mask == 0 && ( frame_size + stack_size ) == 0 && low == 0 ) ; } </s>

Returns true if a simple return insn can be used .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Op . size ( ) >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || Op . isAligned ( Align ( 16 ) ) ) ) { if ( Op . size ( ) >= 64 && Subtarget . hasAVX512 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 512 ) ) { return Subtarget . hasBWI ( ) ? MVT :: v64i8 : MVT :: v16i32 ; } if ( Op . size ( ) >= 32 && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 256 ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v4f32 ; } else if ( ( ( Op . isMemcpy ( ) && ! Op . isMemcpyStrSrc ( ) ) || Op . isZeroMemset ( ) ) && Op . size ( ) >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Op . size ( ) >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> static bool mips_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( GET_MODE_SIZE ( from ) == 8 && GET_MODE_SIZE ( to ) == 8 && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return true ; if ( MSA_SUPPORTED_MODE_P ( from ) && MSA_SUPPORTED_MODE_P ( to ) ) return true ; return ! reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


"missing value in %<target()%> pragma or attribute"

"invalid feature modifier %s of value (\"%s\") in "

Parse an architecture extensions target attribute string specified in STR . For example `` +fp+nosimd '' . Show any errors if needed . Return TRUE if successful . Update aarch64_isa_flags to reflect the ISA features modified . PRAGMA_OR_ATTR is used in potential error messages .


<s>
int
SparcSubtarget
::
getAdjustedFrameSize
(
int
frameSize
)
const
{
if
(
is64Bit
(
)
)
{
frameSize
+=
128
;
assert
(
frameSize
%
16
==
0
&&
"Stack size not 16-byte aligned"
)
;
}
else
{
frameSize
+=
92
;
frameSize
=
RoundUpToAlignment
(
frameSize
,
8
)
;
}
return
frameSize
;
}
</s>

Given a actual stack size as determined by FrameInfo , this function returns adjusted framesize which includes space for RSA , return address , and frame poitner .


<s>
unsigned
SystemZRegisterInfo
::
getRARegister
(
)
const
{
assert
(
0
&&
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> bool csky_symbolic_address_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case SYMBOL_REF : case LABEL_REF : return 1 ; case CONST : x = XEXP ( x , 0 ) ; return ( ( GET_CODE ( XEXP ( x , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( x , 0 ) ) == LABEL_REF ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) ; default : return 0 ; } } </s>

Return true if X is an address form involving a symbol or label ref .


<s> ATTRIBUTE_UNUSED static section * ia64_hpux_function_section ( tree decl ATTRIBUTE_UNUSED , enum node_frequency freq ATTRIBUTE_UNUSED , bool startup ATTRIBUTE_UNUSED , bool exit ATTRIBUTE_UNUSED ) { return NULL ; } </s>

Always default to .text section until HP-UX linker is fixed .


<s> void PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCPreEmitPeepholePass ( ) ) ; addPass ( createPPCExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) ) ; } </s>


<s> int mmix_constant_address_p ( rtx x ) { RTX_CODE code = GET_CODE ( x ) ; int addend = 0 ; int constant_ok = TARGET_BASE_ADDRESSES != 0 ; switch ( code ) { case LABEL_REF : case SYMBOL_REF : return 1 ; case HIGH : return constant_ok ; case CONST_INT : addend = INTVAL ( x ) ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) != VOIDmode ) return constant_ok ; addend = CONST_DOUBLE_LOW ( x ) ; break ; case CONST : if ( GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { rtx x0 = XEXP ( XEXP ( x , 0 ) , 0 ) ; rtx x1 = XEXP ( XEXP ( x , 0 ) , 1 ) ; if ( ( GET_CODE ( x0 ) == SYMBOL_REF || GET_CODE ( x0 ) == LABEL_REF ) && ( GET_CODE ( x1 ) == CONST_INT || ( GET_CODE ( x1 ) == CONST_DOUBLE && GET_MODE ( x1 ) == VOIDmode ) ) ) addend = mmix_intval ( x1 ) ; else return constant_ok ; } else return constant_ok ; break ; default : return 0 ; } return constant_ok || ( addend & 3 ) == 0 ; } </s>

We must exclude constant addresses that have an increment that is not a multiple of four bytes because of restrictions of the GETA instruction , unless TARGET_BASE_ADDRESSES .


<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = ( regno1 <= R30_REGNUM ) ? DImode : DFmode ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 2 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push registers numbered REGNO1 and REGNO2 to the stack , adjusting the stack pointer by ADJUSTMENT .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCInstFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

Mips
0
"RelaxInstruction() unimplemented"


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> void CAHPFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( CAHP :: X0 ) ; SavedRegs . set ( CAHP :: X2 ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static char * mips16e_add_register_range ( char * s , unsigned int min_reg , unsigned int max_reg ) { if ( min_reg != max_reg ) s += sprintf ( s , ",%s-%s" , reg_names [ min_reg ] , reg_names [ max_reg ] ) ; else s += sprintf ( s , ",%s" , reg_names [ min_reg ] ) ; return s ; } </s>

Add a MIPS16e SAVE or RESTORE register-range argument to string S for the register range [ MIN_REG , MAX_REG ] . Return a pointer to the null terminator .


<s> MCELFStreamer & MipsTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> const X86RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> StringRef PPCInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s> rtx ix86_find_base_term ( rtx x ) { rtx term ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , 0 ) ; if ( GET_CODE ( term ) == PLUS && CONST_INT_P ( XEXP ( term , 1 ) ) ) term = XEXP ( term , 0 ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , 1 ) != UNSPEC_GOTPCREL && XINT ( term , 1 ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , 0 , 0 ) ; } return ix86_delegitimize_address_1 ( x , true ) ; } </s>

If X is a machine specific address ( i.e . a symbol or label being referenced as a displacement from the GOT implemented using an UNSPEC ) , then return the base term . Otherwise return X .


<s> static bool rs6000_slow_unaligned_access ( machine_mode mode , unsigned int align ) { return ( STRICT_ALIGNMENT || ( ! TARGET_EFFICIENT_UNALIGNED_VSX && ( ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && align < 32 ) || ( ( VECTOR_MODE_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) ) && ( int ) align < VECTOR_ALIGN ( mode ) ) ) ) ) ; } </s>

Implement TARGET_SLOW_UNALIGNED_ACCESS . Altivec vector memory instructions simply ignore the low bits ; VSX memory instructions are aligned to 4 or 8 bytes .


<s> void Thumb2RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: t2LDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) ARMCC :: AL ) . addReg ( 0 ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s>
unsigned
AArch64FastISel
::
fastMaterializeConstant
(
const
Constant
*
C
)
{
EVT
CEVT
=
TLI
.
getValueType
(
DL
,
C
->
getType
(
)
,
true
)
;
if
(
!
CEVT
.
isSimple
(
)
)
return
0
;
MVT
VT
=
CEVT
.
getSimpleVT
(
)
;
if
(
isa
<
ConstantPointerNull
>
(
C
)
)
{
assert
(
VT
==
MVT
::
i64
&&
"Expected 64-bit pointers"
)
;
return
materializeInt
(
ConstantInt
::
get
(
Type
::
getInt64Ty
(
*
Context
)
,
0
)
,
VT
)
;
}
if
(
const
auto
*
CI
=
dyn_cast
<
ConstantInt
>
(
C
)
)
return
materializeInt
(
CI
,
VT
)
;
else
if
(
const
ConstantFP
*
CFP
=
dyn_cast
<
ConstantFP
>
(
C
)
)
return
materializeFP
(
CFP
,
VT
)
;
else
if
(
const
GlobalValue
*
GV
=
dyn_cast
<
GlobalValue
>
(
C
)
)
return
materializeGV
(
GV
)
;
return
0
;
}
</s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s>
unsigned
CJGInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
CJG
::
JMP
&&
I
->
getOpcode
(
)
!=
CJG
::
JCC
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

CJG
CJG
"code size not handled"
0
CJG::JMP
CJG::JCC


<s> static int num_insns_constant_gpr ( HOST_WIDE_INT value ) { if ( SIGNED_INTEGER_16BIT_P ( value ) ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P ( value ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 || low == high ) return num_insns_constant_gpr ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_gpr ( low ) + 1 ; else return ( num_insns_constant_gpr ( high ) + num_insns_constant_gpr ( low ) + 1 ) ; } else return 2 ; } </s>

Helper for num_insns_constant . Calculate number of instructions to load VALUE to a single gpr using combinations of addi , addis , ori , oris , sldi and rldimi instructions .


<s> static void replace_swapped_aligned_load ( swap_web_entry * insn_entry , rtx swap_insn ) { unsigned uid = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && ! insn_entry [ uid ] . is_load ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( swap_insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; gcc_assert ( def_link && ! def_link -> next ) ; gcc_assert ( def_link && def_link -> ref && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) && ! def_link -> next ) ; rtx_insn * def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT ) && ( GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) == MEM ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && ( GET_CODE ( SET_SRC ( new_body ) ) == MEM ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( def_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted ( ) ; mark_swaps_for_removal ( insn_entry , uid ) ; replace_swap_with_copy ( insn_entry , uid ) ; } </s>

Given that SWAP_INSN represents a swap of an aligned load-with-swap , replace the load with an aligned load ( without swap ) and replace the swap with a copy insn .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Fixup SetCC"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool MipsRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int Cost = 0 ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return ( Cost + 1 ) * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static void or1k_tls_call ( rtx dest , rtx arg ) { emit_library_call_value ( gen_tls_get_addr ( ) , dest , LCT_CONST , Pmode , arg , Pmode ) ; } </s>


<s> bool ARMTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! I -> getType ( ) -> isVectorTy ( ) ) return false ; if ( Subtarget -> hasNEON ( ) ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsFMSMul = [ & ] ( Instruction * I ) { if ( ! I -> hasOneUse ( ) ) return false ; auto * Sub = cast < Instruction > ( * I -> users ( ) . begin ( ) ) ; return Sub -> getOpcode ( ) == Instruction :: FSub && Sub -> getOperand ( 1 ) == I ; } ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: FAdd : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: FMul : return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == 1 ; default : return false ; } } ; int Op = 0 ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = 1 ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( Op ) ) ; return true ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> bool X86TargetLowering :: areJTsAllowed ( const Function * Fn ) const { if ( Subtarget . useRetpoline ( ) ) return false ; return TargetLowering :: areJTsAllowed ( Fn ) ; } </s>

Returns true if lowering to a jump table is allowed .


<s> static bool expand_vec_perm_vpshufb2_vpermq ( struct expand_vec_perm_d * d ) { rtx rperm [ 2 ] [ 32 ] , vperm , l , h , hp , op , m128 ; unsigned int i , nelt , eltsz ; if ( ! TARGET_AVX2 || ! d -> one_operand_p || ( d -> vmode != V32QImode && d -> vmode != V16HImode ) ) return false ; if ( d -> testing_p ) return true ; nelt = d -> nelt ; eltsz = GET_MODE_UNIT_SIZE ( d -> vmode ) ; m128 = GEN_INT ( - 128 ) ; for ( i = 0 ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] & ( nelt / 2 - 1 ) ; unsigned which = ( ( d -> perm [ i ] ^ i ) & ( nelt / 2 ) ) * eltsz ; for ( j = 0 ; j < eltsz ; ++ j ) { rperm [ ! ! which ] [ ( i * eltsz + j ) ^ which ] = GEN_INT ( e * eltsz + j ) ; rperm [ ! which ] [ ( i * eltsz + j ) ^ ( which ^ 16 ) ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( 32 , rperm [ 1 ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; h = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( h , op , vperm ) ) ; hp = gen_reg_rtx ( V4DImode ) ; op = gen_lowpart ( V4DImode , h ) ; emit_insn ( gen_avx2_permv4di_1 ( hp , op , const2_rtx , GEN_INT ( 3 ) , const0_rtx , const1_rtx ) ) ; vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( 32 , rperm [ 0 ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; l = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( l , op , vperm ) ) ; op = d -> target ; if ( d -> vmode != V32QImode ) op = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_iorv32qi3 ( op , l , gen_lowpart ( V32QImode , hp ) ) ) ; if ( op != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , op ) ) ; return true ; } </s>

Implement arbitrary permutation of one V32QImode and V16QImode operand with two vpshufb insns , vpermq and vpor . We should have already failed all two or three instruction sequences .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
bool
MipsAsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getString
(
)
;
if
(
IDVal
==
".cpload"
)
return
parseDirectiveCPLoad
(
DirectiveID
.
getLoc
(
)
)
;
if
(
IDVal
==
".dword"
)
{
parseDataDirective
(
8
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".ent"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".end"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".frame"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".set"
)
{
return
parseDirectiveSet
(
)
;
}
if
(
IDVal
==
".fmask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".mask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".nan"
)
return
parseDirectiveNaN
(
)
;
if
(
IDVal
==
".gpword"
)
{
parseDirectiveGpWord
(
)
;
return
false
;
}
if
(
IDVal
==
".gpdword"
)
{
parseDirectiveGpDWord
(
)
;
return
false
;
}
if
(
IDVal
==
".word"
)
{
parseDataDirective
(
4
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".option"
)
return
parseDirectiveOption
(
)
;
if
(
IDVal
==
".abicalls"
)
{
getTargetStreamer
(
)
.
emitDirectiveAbiCalls
(
)
;
if
(
Parser
.
getTok
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Error
(
Parser
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in directive"
)
;
Parser
.
eatToEndOfStatement
(
)
;
}
return
false
;
}
if
(
IDVal
==
".cpsetup"
)
return
parseDirectiveCPSetup
(
)
;
if
(
IDVal
==
".module"
)
return
parseDirectiveModule
(
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { while ( MBBI -> isDebugValue ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = 0 ; return llvm :: getITInstrPredicate ( MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> Align getABIAlignmentForCallingConv ( Type * ArgTy , const DataLayout & DL ) const override { const Align ABIAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ArgTy -> isVectorTy ( ) ) return std :: min ( ABIAlign , Align ( 8 ) ) ; return ABIAlign ; } </s>

Return the correct alignment for the current calling convention .


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\t.set\tpush\n" ; O << "\t.set\tmips32r2\n" ; } if ( ! printAliasInstr ( MI , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\n\t.set\tpop" ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> TargetPassConfig * SHUXITargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SHUXIPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool X86TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return Imm == ( int32_t ) Imm ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> static bool mips_interrupt_extra_call_saved_reg_p ( unsigned int regno ) { if ( ( ISA_HAS_HILO || TARGET_DSP ) && MD_REG_P ( regno ) ) return true ; if ( TARGET_DSP && DSP_ACC_REG_P ( regno ) ) return true ; if ( GP_REG_P ( regno ) && cfun -> machine -> use_shadow_register_set == SHADOW_SET_NO ) { if ( regno == GP_REG_FIRST ) return false ; if ( KERNEL_REG_P ( regno ) ) return false ; if ( regno == STACK_POINTER_REGNUM ) return false ; return call_really_used_regs [ regno ] ; } return false ; } </s>

Return true if REGNO is a register that is ordinarily call-clobbered but must nevertheless be preserved by an interrupt handler .


<s>
unsigned
assignCustomValue
(
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
,
std
::
function
<
void
(
)
>
*
Thunk
)
override
{
assert
(
Arg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
if
(
VA
.
getValVT
(
)
!=
MVT
::
f64
)
return
0
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
Register
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Regs
[
0
]
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , bool isVector , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . isVector = isVector ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static bool aarch64_pass_by_reference ( cumulative_args_t pcum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; machine_mode dummymode ; int nregs ; size = ( mode == BLKmode && type ) ? int_size_in_bytes ( type ) : ( int ) GET_MODE_SIZE ( mode ) ; if ( type && AGGREGATE_TYPE_P ( type ) ) { size = int_size_in_bytes ( type ) ; } if ( size < 0 ) return true ; if ( aarch64_vfp_is_call_or_return_candidate ( mode , type , & dummymode , & nregs , NULL ) ) return false ; return size > 2 * UNITS_PER_WORD ; } </s>


<s> bool shouldKeepZExtForFP16Conv ( ) const override { return true ; } </s>

Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function .


<s> void MipsOutgoingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static bool ix86_expand_vector_init_duplicate ( bool mmx_ok , enum machine_mode mode , rtx target , rtx val ) { enum machine_mode smode , wsmode , wvmode ; rtx x ; switch ( mode ) { case V2SImode : case V2SFmode : if ( ! mmx_ok && ! TARGET_SSE ) return false ; case V2DFmode : case V2DImode : case V4SFmode : case V4SImode : val = force_reg ( GET_MODE_INNER ( mode ) , val ) ; x = gen_rtx_VEC_DUPLICATE ( mode , val ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return true ; case V4HImode : if ( ! mmx_ok ) return false ; if ( TARGET_SSE || TARGET_3DNOW_A ) { val = gen_lowpart ( SImode , val ) ; x = gen_rtx_TRUNCATE ( HImode , val ) ; x = gen_rtx_VEC_DUPLICATE ( mode , x ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return true ; } else { smode = HImode ; wsmode = SImode ; wvmode = V2SImode ; goto widen ; } case V8QImode : if ( ! mmx_ok ) return false ; smode = QImode ; wsmode = HImode ; wvmode = V4HImode ; goto widen ; case V8HImode : smode = HImode ; wsmode = SImode ; wvmode = V4SImode ; goto widen ; case V16QImode : smode = QImode ; wsmode = HImode ; wvmode = V8HImode ; goto widen ; widen : val = convert_modes ( wsmode , smode , val , true ) ; x = expand_simple_binop ( wsmode , ASHIFT , val , GEN_INT ( GET_MODE_BITSIZE ( smode ) ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; val = expand_simple_binop ( wsmode , IOR , val , x , x , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wvmode ) ; if ( ! ix86_expand_vector_init_duplicate ( mmx_ok , wvmode , x , val ) ) gcc_unreachable ( ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector with all elements equal to VAR . Return true if successful .


<s> bool nds32_rtx_costs_impl ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code , int opno , int * total , bool speed ) { int code = GET_CODE ( x ) ; if ( speed ) return rtx_cost_model . speed_prefer ( x , code , outer_code , opno , total ) ; else return rtx_cost_model . size_prefer ( x , code , outer_code , opno , total ) ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s> bool KudeyarAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { KudeyarFI = MF . getInfo < KudeyarMachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void SystemZTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .