<s> bool ARMFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( ARM :: FPCXTNS ) ; CSI . back ( ) . setRestored ( false ) ; } const auto & AFI = * MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI . shouldSignReturnAddress ( ) ) { CSI . insert ( find_if ( CSI , [ = ] ( const auto & CS ) { unsigned Reg = CS . getReg ( ) ; return Reg == ARM :: R10 || Reg == ARM :: R11 || Reg == ARM :: R8 || Reg == ARM :: R9 || ARM :: DPRRegClass . contains ( Reg ) ; } ) , CalleeSavedInfo ( ARM :: R12 ) ) ; } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static void rs6000_finish_atomic_subword ( rtx narrow , rtx wide , rtx shift ) { wide = expand_simple_binop ( SImode , LSHIFTRT , wide , shift , wide , 1 , OPTAB_LIB_WIDEN ) ; emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow ) , wide ) ) ; } </s>

A subroutine of the various atomic expanders . For sub-word operands , extract WIDE to NARROW via SHIFT .


"instruction use requires an option to be enabled"

"immediate must be a multiple of 2 bytes in the range"

"operand must be a symbol with %hi modifier or an integer in "

"operand must be a symbol with %lo modifier or an integer in "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( ! PPCSubTarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; Register TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { MF -> getInfo < PPCFunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> rtx nds32_legitimize_tls_address ( rtx x ) { rtx tmp_reg ; rtx tp_reg = gen_rtx_REG ( Pmode , TP_REGNUM ) ; rtx pat , insns , reg0 ; int relax_group_id = nds32_alloc_relax_group_id ( ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) switch ( SYMBOL_REF_TLS_MODEL ( x ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : if ( SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_GLOBAL_DYNAMIC ) pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_TLSGD ) ; else pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_TLSLD ) ; pat = gen_rtx_CONST ( SImode , pat ) ; reg0 = gen_rtx_REG ( Pmode , 0 ) ; insns = emit_call_insn ( gen_tls_desc ( pat , GEN_INT ( relax_group_id ) ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insns ) , pic_offset_table_rtx ) ; RTL_CONST_CALL_P ( insns ) = 1 ; tmp_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp_reg , reg0 ) ; x = tmp_reg ; break ; case TLS_MODEL_INITIAL_EXEC : pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_TLSIE ) ; tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_ie ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; if ( flag_pic ) emit_use ( pic_offset_table_rtx ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , x ) , UNSPEC_TLSLE ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_le ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; break ; default : gcc_unreachable ( ) ; } else if ( GET_CODE ( x ) == CONST ) { rtx base , addend ; split_const ( x , & base , & addend ) ; if ( SYMBOL_REF_TLS_MODEL ( base ) == TLS_MODEL_LOCAL_EXEC ) { tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , base ) , UNSPEC_TLSLE ) ; pat = gen_rtx_PLUS ( SImode , pat , addend ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_le ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; } } return x ; } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> static void get_pc_thunk_name ( char name [ 32 ] , unsigned int regno ) { if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__i686.get_pc_thunk.%s" , reg_names [ regno ] ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LPR" , regno ) ; } </s>

Fills in the label name that should be used for a pc thunk for the given register .


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s>
uint64_t
SystemZMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
uint64_t
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unexpected operand type!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

SystemZ
SystemZ
"Unexpected operand type!"


<s> void Cpu0TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const Cpu0TargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> void loongarch_move_integer ( rtx temp , rtx dest , unsigned HOST_WIDE_INT value ) { struct loongarch_integer_op codes [ LARCH_MAX_INTEGER_OPS ] ; machine_mode mode ; unsigned int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = loongarch_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) { emit_insn ( gen_rtx_SET ( temp , x ) ) ; x = temp ; } else x = force_reg ( mode , x ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , GEN_INT ( codes [ i - 1 ] . curr_value ) ) ; switch ( codes [ i ] . method ) { case METHOD_NORMAL : x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; break ; case METHOD_LU32I : gcc_assert ( mode == DImode ) ; x = gen_rtx_IOR ( DImode , gen_rtx_ZERO_EXTEND ( DImode , gen_rtx_SUBREG ( SImode , x , 0 ) ) , GEN_INT ( codes [ i ] . value ) ) ; break ; case METHOD_LU52I : gcc_assert ( mode == DImode ) ; x = gen_rtx_IOR ( DImode , gen_rtx_AND ( DImode , x , GEN_INT ( 0xfffffffffffff ) ) , GEN_INT ( codes [ i ] . value ) ) ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>

Load VALUE into DEST . TEMP is as for loongarch_force_temporary .


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == MVT :: f16 && Subtarget -> hasFullFP16 ( ) ) return ARM_AM :: getFP16Imm ( Imm ) != - 1 ; if ( VT == MVT :: f32 ) return ARM_AM :: getFP32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 && ! Subtarget -> isFPOnlySP ( ) ) return ARM_AM :: getFP64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool shouldBuildLookupTablesForConstant ( Constant * C ) const { if ( ST -> isROPI ( ) || ST -> isRWPI ( ) ) return ! C -> needsDynamicRelocation ( ) ; return true ; } </s>

Return true if switches should be turned into lookup tables containing this constant value for the target .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
bool
AArch64InstrInfo
::
optimizeCondBranch
(
MachineInstr
*
MI
)
const
{
bool
IsNegativeBranch
=
false
;
bool
IsTestAndBranch
=
false
;
unsigned
TargetBBInMI
=
0
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown branch instruction?"
)
;
case
AArch64
::
Bcc
:
return
false
;
case
AArch64
::
CBZW
:
case
AArch64
::
CBZX
:
TargetBBInMI
=
1
;
break
;
case
AArch64
::
CBNZW
:
case
AArch64
::
CBNZX
:
TargetBBInMI
=
1
;
IsNegativeBranch
=
true
;
break
;
case
AArch64
::
TBZW
:
case
AArch64
::
TBZX
:
TargetBBInMI
=
2
;
IsTestAndBranch
=
true
;
break
;
case
AArch64
::
TBNZW
:
case
AArch64
::
TBNZX
:
TargetBBInMI
=
2
;
IsNegativeBranch
=
true
;
IsTestAndBranch
=
true
;
break
;
}
if
(
IsTestAndBranch
&&
MI
->
getOperand
(
1
)
.
getImm
(
)
)
return
false
;
assert
(
MI
->
getParent
(
)
&&
"Incomplete machine instruciton\n"
)
;
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
MachineRegisterInfo
*
MRI
=
&
MF
->
getRegInfo
(
)
;
unsigned
VReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
VReg
)
)
return
false
;
MachineInstr
*
DefMI
=
MRI
->
getVRegDef
(
VReg
)
;
if
(
!
(
DefMI
->
getOpcode
(
)
==
AArch64
::
CSINCWr
&&
DefMI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
&&
DefMI
->
getOperand
(
2
)
.
getReg
(
)
==
AArch64
::
WZR
)
&&
!
(
DefMI
->
getOpcode
(
)
==
AArch64
::
CSINCXr
&&
DefMI
->
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
&&
DefMI
->
getOperand
(
2
)
.
getReg
(
)
==
AArch64
::
XZR
)
)
return
false
;
if
(
DefMI
->
findRegisterDefOperandIdx
(
AArch64
::
NZCV
,
true
)
!=
1
)
return
false
;
AArch64CC
::
CondCode
CC
=
(
AArch64CC
::
CondCode
)
DefMI
->
getOperand
(
3
)
.
getImm
(
)
;
bool
CheckOnlyCCWrites
=
true
;
if
(
modifiesConditionCode
(
DefMI
,
MI
,
CheckOnlyCCWrites
,
&
getRegisterInfo
(
)
)
)
return
false
;
MachineBasicBlock
&
RefToMBB
=
*
MBB
;
MachineBasicBlock
*
TBB
=
MI
->
getOperand
(
TargetBBInMI
)
.
getMBB
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
if
(
IsNegativeBranch
)
CC
=
AArch64CC
::
getInvertedCondCode
(
CC
)
;
BuildMI
(
RefToMBB
,
MI
,
DL
,
get
(
AArch64
::
Bcc
)
)
.
addImm
(
CC
)
.
addMBB
(
TBB
)
;
MI
->
eraseFromParent
(
)
;
return
true
;
}
</s>

Replace csincr-branch sequence by simple conditional branch .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { MVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : case MVT :: i64 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( AM . Scale & 1 ) return false ; return isPowerOf2_32 ( AM . Scale ) ; } break ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool mips_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( cfun -> machine -> interrupt_handler_p && ! df_regs_ever_live_p ( new_reg ) ) return false ; return true ; } </s>

Return nonzero if register OLD_REG can be renamed to register NEW_REG .


"\ninit_cumulative_args, fntype = 0x%.8lx"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> static void push_minipool_barrier ( rtx insn , HOST_WIDE_INT address ) { Mfix * fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * fix ) ) ; fix -> insn = insn ; fix -> address = address ; fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail -> next = fix ; else minipool_fix_head = fix ; minipool_fix_tail = fix ; } </s>

Record that there is a natural barrier in the insn stream at ADDRESS .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

PowerPC PPC PPC PPC 0 PPC::VRSAVE PPC::CR2 PPC::CR4 PPC PPC PPC PPC::MFCR PPC::R12 PPC::STW PPC::R12


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool aarch64_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( mode1 ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> static const char * rs6000_xcoff_strip_name_encoding ( const char * name ) { size_t len ; if ( * name == '*' ) name ++ ; len = strlen ( name ) ; if ( name [ len - 1 ] == ']' ) return ggc_alloc_string ( name , len - 4 ) ; else return name ; } </s>

Remove any trailing [ DS ] or the like from the symbol name .


<s> const FISCRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool isKZeroMasked ( ) const { return ( Attributes & X86FMA3KZeroMasked ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds k-zero-masked opcodes .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
nullptr
,
IsLittleEndian
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool convertSelectOfConstantsToMath ( EVT VT ) const override { return true ; } </s>

Return true if a select of constants ( select Cond , C1 , C2 ) should be transformed into simple math ops with the condition value .


<s> EVT MipsTargetLowering :: getTypeForExtReturn ( LLVMContext & Context , EVT VT , ISD :: NodeType ) const { bool Cond = ! Subtarget . isABI_O32 ( ) && VT . getSizeInBits ( ) == 32 ; EVT MinVT = getRegisterType ( Context , Cond ? MVT :: i64 : MVT :: i32 ) ; return VT . bitsLT ( MinVT ) ? MinVT : VT ; } </s>

Return the type that should be used to zero or sign extend a zeroext/signext integer return value .


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TFL = STI -> getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextVector CallSeqVector ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext Context ; collectCallInfo ( MF , * BB , I , Context ) ; CallSeqVector . push_back ( Context ) ; } if ( ! isProfitable ( MF , CallSeqVector ) ) return false ; for ( auto CC : CallSeqVector ) if ( CC . UsePush ) Changed |= adjustCallSequence ( MF , CC ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> int aarch64_add_offset_temporaries ( rtx x ) { poly_int64 offset ; if ( ! poly_int_rtx_p ( x , & offset ) ) return - 1 ; return aarch64_offset_temporaries ( true , offset ) ; } </s>

If X can be represented as a poly_int64 , return the number of temporaries that are required to add it to a register . Return -1 otherwise .


<s> bool Thumb1InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>


<s> bool Thumb1FrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } return true ; } </s>


<s>
bool
SparcAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
if
(
parseBranchModifiers
(
Operands
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Sparc
Sparc
SparcOperand::CreateToken
0
"unexpected token"
"unexpected token"
"unexpected token"
"unexpected token"


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
X86
::
getCondFromBranch
(
*
I
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
LivePhysRegs
LiveRegs
(
getRegisterInfo
(
)
)
;
LiveRegs
.
addLiveOuts
(
MBB
)
;
SmallVector
<
std
::
pair
<
MCPhysReg
,
const
MachineOperand
*
>
,
8
>
Clobbers
;
LiveRegs
.
stepForward
(
*
MIB
,
Clobbers
)
;
for
(
const
auto
&
C
:
Clobbers
)
{
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
)
;
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
|
RegState
::
Define
)
;
}
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


<s> rtx loongarch_unspec_address ( rtx address , enum loongarch_symbol_type symbol_type ) { rtx base , offset ; split_const ( address , & base , & offset ) ; return loongarch_unspec_address_offset ( base , offset , symbol_type ) ; } </s>

Return an UNSPEC address with underlying address ADDRESS and symbol type SYMBOL_TYPE .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getArchName ( ) != "arm64e" && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> virtual const OR1KSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static unsigned int num_occurences_in_str ( char c , char * str ) { unsigned int res = 0 ; while ( * str != '\0' ) { if ( * str == c ) res ++ ; str ++ ; } return res ; } </s>

Count how many times the character C appears in NULL-terminated string STR .


<s> static void aarch64_print_operand_address ( FILE * f , machine_mode mode , rtx x ) { if ( ! aarch64_print_address_internal ( f , mode , x , ADDR_QUERY_ANY ) ) output_addr_const ( f , x ) ; } </s>

Print address ' x ' of a memory access with mode 'mode ' .


<s> bool equals ( const ARMConstantPoolMBB * A ) const { return MBB == A -> MBB && ARMConstantPoolValue :: equals ( A ) ; } </s>

equals - Check for string equality , this is more efficient than compare ( ) when the relative ordering of inequal strings is n't needed .


<s> void X86WinCOFFStreamer :: emitCVFPOData ( const MCSymbol * ProcSym , SMLoc Loc ) { X86TargetStreamer * XTS = static_cast < X86TargetStreamer * > ( getTargetStreamer ( ) ) ; XTS -> emitFPOData ( ProcSym , Loc ) ; } </s>

This implements the CodeView '.cv_fpo_data ' assembler directive .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy , Align Alignment ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && cast < FixedVectorType > ( DataTy ) -> getNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ScalarTy -> isHalfTy ( ) && ST -> hasBWI ( ) && ST -> hasFP16 ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s> bool arm_expand_vec_perm_const ( rtx target , rtx op0 , rtx op1 , rtx sel ) { struct expand_vec_perm_d d ; int i , nelt , which ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; for ( i = which = 0 ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , 0 , i ) ; int ei = INTVAL ( e ) & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; d . perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( ! rtx_equal_p ( op0 , op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = op0 ; d . one_vector_p = true ; break ; } return arm_expand_vec_perm_const_1 ( & d ) ; } </s>


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; if ( CC == CallingConv :: Mono && IsWin64 ) CC = CallingConv :: Win64 ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( PerformTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt16 ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , false , false , true ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) ) . addReg ( StackReg ) . addReg ( StackReg ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr & MI = * -- MBBI ; if ( CompleteCCUsers && ( MI . isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI . eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI . definesRegister ( SystemZ :: CC ) ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( MI . readsRegister ( SystemZ :: CC ) && CompleteCCUsers ) CCUsers . push_back ( & MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ 4 SystemZ::CC SystemZ::CC


<s>
Register
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
MatchRegisterName
(
RegName
)
;
if
(
AArch64
::
X1
<=
Reg
&&
Reg
<=
AArch64
::
X28
)
{
const
MCRegisterInfo
*
MRI
=
Subtarget
->
getRegisterInfo
(
)
;
unsigned
DwarfRegNum
=
MRI
->
getDwarfRegNum
(
Reg
,
false
)
;
if
(
!
Subtarget
->
isXRegisterReserved
(
DwarfRegNum
)
)
Reg
=
0
;
}
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> virtual const SystemZSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s>
MCFragment
*
AArch64MCExpr
::
findAssociatedFragment
(
)
const
{
llvm_unreachable
(
"FIXME: what goes here?"
)
;
}
</s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> const DLXTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Fixup SetCC"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool ix86_additional_allocno_class_p ( reg_class_t cl ) { return cl == MOD4_SSE_REGS ; } </s>

Return true if register class CL should be an additional allocno class .


<s>
static
void
pru_dump_frame_layout
(
FILE
*
file
)
{
fprintf
(
file
,
"\t%s Current Frame Info\n"
,
ASM_COMMENT_START
)
;
fprintf
(
file
,
"\t%s total_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
total_size
)
;
fprintf
(
file
,
"\t%s var_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
var_size
)
;
fprintf
(
file
,
"\t%s out_args_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
out_args_size
)
;
fprintf
(
file
,
"\t%s save_reg_size = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
save_reg_size
)
;
fprintf
(
file
,
"\t%s initialized = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
initialized
)
;
fprintf
(
file
,
"\t%s save_regs_offset = %d\n"
,
ASM_COMMENT_START
,
cfun
->
machine
->
save_regs_offset
)
;
fprintf
(
file
,
"\t%s is_leaf = %d\n"
,
ASM_COMMENT_START
,
crtl
->
is_leaf
)
;
fprintf
(
file
,
"\t%s frame_pointer_needed = %d\n"
,
ASM_COMMENT_START
,
frame_pointer_needed
)
;
fprintf
(
file
,
"\t%s pretend_args_size = %d\n"
,
ASM_COMMENT_START
,
crtl
->
args
.
pretend_args_size
)
;
}
</s>

pru
"\t%s Current Frame Info\n"
"\t%s total_size = %d\n"
"\t%s var_size = %d\n"
"\t%s out_args_size = %d\n"
"\t%s save_reg_size = %d\n"
"\t%s initialized = %d\n"
"\t%s save_regs_offset = %d\n"
"\t%s is_leaf = %d\n"
"\t%s frame_pointer_needed = %d\n"
"\t%s pretend_args_size = %d\n"


<s> static bool mmix_pass_by_reference ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > 8 && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ; return false ; } </s>

Returns nonzero for everything that goes by reference , 0 for everything that goes by value .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 CondBr Folding"
;
}
</s>


<s> static bool ix86_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) { if ( ( mode == P2QImode || mode == P2HImode ) ) return MASK_PAIR_REGNO_P ( regno ) ; return ( ( TARGET_AVX512F && VALID_MASK_REG_MODE ( mode ) ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; } if ( GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( VALID_AVX512F_REG_OR_XI_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( TARGET_AVX512FP16 && VALID_AVX512FP16_SCALAR_MODE ( mode ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && ( mode == V64SFmode || mode == V64SImode ) && MOD4_SSE_REGNO_P ( regno ) ) return true ; if ( TARGET_AVX512VL && ( VALID_AVX256_REG_OR_OI_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) || VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_src , permute_tmp ; gcc_assert ( ! reload_in_progress && ! lra_in_progress && ! reload_completed ) ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , 0 ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source ) : source ; permute_src = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_tmp = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_src ) ) ; emit_insn ( gen_rtx_SET ( dest , permute_tmp ) ) ; } </s>

Emit a little-endian store to vector memory location DEST from VSX register SOURCE in mode MODE . The store is done with two permuting insn 's that represent an xxpermdi and an stxvd2x .


<s> OperandMatchResultTy AArch64AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = getLoc ( ) ; auto Res = tryParseScalarRegister ( RegNo ) ; EndLoc = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - 1 ) ; return Res ; } </s>

tryParseRegister - parse one register if possible


<s>
int
scalar_chain
::
convert
(
)
{
bitmap_iterator
bi
;
unsigned
id
;
int
converted_insns
=
0
;
if
(
!
dbg_cnt
(
stv_conversion
)
)
return
0
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Converting chain #%d...\n"
,
chain_id
)
;
EXECUTE_IF_SET_IN_BITMAP
(
defs
,
0
,
id
,
bi
)
convert_reg
(
id
)
;
EXECUTE_IF_AND_COMPL_IN_BITMAP
(
defs_conv
,
defs
,
0
,
id
,
bi
)
make_vector_copies
(
id
)
;
EXECUTE_IF_SET_IN_BITMAP
(
insns
,
0
,
id
,
bi
)
{
convert_insn
(
DF_INSN_UID_GET
(
id
)
->
insn
)
;
converted_insns
++
;
}
return
converted_insns
;
}
</s>

Convert whole chain creating required register conversions and copies .


<s> void LEGInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LEG :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , PPC :: ZERO ) ; markSuperRegs ( Reserved , PPC :: FP ) ; markSuperRegs ( Reserved , PPC :: BP ) ; markSuperRegs ( Reserved , PPC :: CTR ) ; markSuperRegs ( Reserved , PPC :: CTR8 ) ; markSuperRegs ( Reserved , PPC :: R1 ) ; markSuperRegs ( Reserved , PPC :: LR ) ; markSuperRegs ( Reserved , PPC :: LR8 ) ; markSuperRegs ( Reserved , PPC :: RM ) ; markSuperRegs ( Reserved , PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( ! TM . isPPC64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; markSuperRegs ( Reserved , PPC :: R13 ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; if ( TM . isPPC64 ( ) ) markSuperRegs ( Reserved , PPC :: R13 ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R29 ) ; else markSuperRegs ( Reserved , PPC :: R30 ) ; } if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) markSuperRegs ( Reserved , * I ) ; if ( Subtarget . isAIXABI ( ) && Subtarget . hasAltivec ( ) && ! TM . getAIXExtendedAltivecABI ( ) ) { for ( auto Reg : CSR_Altivec_SaveList ) { if ( Reg == 0 ) break ; markSuperRegs ( Reserved , Reg ) ; for ( MCRegAliasIterator AS ( Reg , this , true ) ; AS . isValid ( ) ; ++ AS ) { Reserved . set ( * AS ) ; } } } assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC -> getID ( ) == X86 :: TILERegClassID ) { unsigned Opc = X86 :: TILELOADD ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & X86 :: GR64_NOSPRegClass ) ; MachineInstr * NewMI = BuildMI ( MBB , MI , DebugLoc ( ) , get ( X86 :: MOV64ri ) , VirtReg ) . addImm ( 64 ) ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; MachineOperand & MO = NewMI -> getOperand ( 3 ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || ( RI . canRealignStack ( MF ) && ! MFI . isFixedObjectIndex ( FrameIdx ) ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> const MCExpr * MipsTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> static bool ix86_in_large_data_p ( tree exp ) { if ( ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = TREE_STRING_POINTER ( DECL_SECTION_NAME ( exp ) ) ; if ( strcmp ( section , ".ldata" ) == 0 || strcmp ( section , ".lbss" ) == 0 ) return true ; return false ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( ! size || size > ix86_section_threshold ) return true ; } return false ; } </s>

Return true if this goes in small data/bss .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
&
STI
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
.
begin
(
)
,
MLI
.
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> unsigned AArch64TTI :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , OperandValueKind Opd1Info , OperandValueKind Opd2Info , OperandValueProperties Opd1PropInfo , OperandValueProperties Opd2PropInfo ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { unsigned Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1


<s> bool CSKYAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < CSKYSubtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> bool SystemZTargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return Subtarget . hasVectorEnhancements1 ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; ARMGISelActualAccessor * GISel = new ARMGISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new ARMCallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new ARMLegalizerInfo ( * I ) ) ; auto * RBI = new ARMRegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( new ARMInstructionSelector ( * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM ARM ARM ARM ARM ARM ARM


<s> static void loongarch_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned int argno ) { tree arg ; rtx value ; arg = CALL_EXPR_ARG ( exp , argno ) ; value = expand_normal ( arg ) ; create_input_operand ( op , value , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } </s>

Take argument ARGNO from EXP 's argument list and convert it into an expand operand . Store the operand in * OP .


<s> bool aarch64_sve_index_immediate_p ( rtx base_or_step ) { return ( CONST_INT_P ( base_or_step ) && IN_RANGE ( INTVAL ( base_or_step ) , - 16 , 15 ) ) ; } </s>

Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX instruction .


<s> void erasingInstr ( MachineInstr & MI ) override { } </s>


"ARM constant island placement and branch shortening pass"

getPassName - Return a nice clean name for a pass .


<s> bool invalid_e500_subreg ( rtx op , machine_mode mode ) { if ( TARGET_E500_DOUBLE ) { if ( GET_CODE ( op ) == SUBREG && ( mode == SImode || mode == DImode || mode == TImode || mode == DDmode || mode == TDmode || mode == PTImode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DFmode || GET_MODE ( SUBREG_REG ( op ) ) == TFmode || GET_MODE ( SUBREG_REG ( op ) ) == IFmode || GET_MODE ( SUBREG_REG ( op ) ) == KFmode ) ) return true ; if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode || mode == IFmode || mode == KFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE ( SUBREG_REG ( op ) ) == TDmode ) ) return true ; } if ( TARGET_SPE && GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && SPE_VECTOR_MODE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) return true ; return false ; } </s>

Return TRUE if OP is an invalid SUBREG operation on the e500 .


<s> bool aarch64_and_bitmask_imm ( unsigned HOST_WIDE_INT val_in , machine_mode mode ) { if ( aarch64_bitmask_imm ( val_in , mode ) ) return false ; if ( aarch64_move_imm ( val_in , mode ) ) return false ; unsigned HOST_WIDE_INT imm2 = aarch64_and_split_imm2 ( val_in ) ; return aarch64_bitmask_imm ( imm2 , mode ) ; } </s>

Return true if VAL_IN is a valid 'and ' bitmask immediate .


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; enum memmodel model ; rtx model_rtx ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; model_rtx = operands [ 5 ] ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ! is_weak && oldval == const0_rtx ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) { x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = aarch64_gen_compare_reg ( NE , rval , oldval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } emit_label ( label2 ) ; if ( strong_zero_p ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , rval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( is_mm_sync ( model ) ) aarch64_emit_post_barrier ( model ) ; } </s>


<s>
const
char
*
output_call_mem
(
rtx
*
operands
)
{
gcc_assert
(
!
arm_arch5
)
;
if
(
TARGET_INTERWORK
)
{
output_asm_insn
(
"ldr%?\t%|ip, %0"
,
operands
)
;
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
output_asm_insn
(
"bx%?\t%|ip"
,
operands
)
;
}
else
if
(
regno_use_in
(
LR_REGNUM
,
operands
[
0
]
)
)
{
output_asm_insn
(
"ldr%?\t%|ip, %0"
,
operands
)
;
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
if
(
arm_arch4t
)
output_asm_insn
(
"bx%?\t%|ip"
,
operands
)
;
else
output_asm_insn
(
"mov%?\t%|pc, %|ip"
,
operands
)
;
}
else
{
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
output_asm_insn
(
"ldr%?\t%|pc, %0"
,
operands
)
;
}
return
""
;
}
</s>

Output a 'call ' insn that is a reference in memory . This is disabled for ARMv5 and we prefer a blx instead because otherwise there 's a significant performance overhead .


"Switch should handle all register classes"


<s> bool X86CondBrFolding :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , int & CmpValue ) { unsigned SrcRegIndex = 0 ; unsigned ValueIndex = 0 ; switch ( MI . getOpcode ( ) ) { default : return false ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcRegIndex = 0 ; ValueIndex = 1 ; break ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcRegIndex = 1 ; ValueIndex = 2 ; break ; } SrcReg = MI . getOperand ( SrcRegIndex ) . getReg ( ) ; if ( ! MI . getOperand ( ValueIndex ) . isImm ( ) ) return false ; CmpValue = MI . getOperand ( ValueIndex ) . getImm ( ) ; return true ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
MachineOperand
Target
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
Target
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode , cmp_mode ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case E_DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_THUMB1 ) cmp_mode = E_SImode ; else cmp_mode = CC_Zmode ; bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CC_Zmode , CC_REGNUM ) ; emit_insn ( gen_atomic_compare_and_swap_1 ( cmp_mode , mode , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; if ( TARGET_THUMB1 ) emit_insn ( gen_cstoresi_eq0_thumb1 ( bval , bdst ) ) ; else { x = gen_rtx_EQ ( SImode , bdst , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } } </s>


<s> unsigned getNumFixupKinds ( ) const { return 5 ; } </s>

Get the number of target specific fixup kinds .


<s> void LanaiInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annotation , const MCSubtargetInfo & , raw_ostream & OS ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , Address , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned Cpu0MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> machine_mode loongarch_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , NULL ) ; else return mode ; } </s>


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . mayLoad ( ) ) return Sched :: Latency ; const InstrItineraryData & Itins = getTargetMachine ( ) . getInstrItineraryData ( ) ; if ( ! Itins . isEmpty ( ) && Itins . getStageLatency ( TID . getSchedClass ( ) ) > 2 ) return Sched :: Latency ; return Sched :: RegPressure ; } </s>


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != 128 || isOpSuitableForLDPSTP ( LI ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? TII . getFrameSize ( * I ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || F . needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . optForMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( ! I -> hasOneUse ( ) ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const Function * F = I -> getFunction ( ) ; const DataLayout & DL = F -> getParent ( ) -> getDataLayout ( ) ; Type * Ty = User -> getOperand ( 0 ) -> getType ( ) ; return ! ( isFMAFasterThanFMulAndFAdd ( * F , Ty ) && isOperationLegalOrCustom ( ISD :: FMA , getValueType ( DL , Ty ) ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( ( Sparc :: Fixups ) Fixup . getKind ( ) ) { default : return false ; case Sparc :: fixup_sparc_wplt30 : if ( Target . getSymA ( ) -> getSymbol ( ) . isTemporary ( ) ) return false ; LLVM_FALLTHROUGH ; case Sparc :: fixup_sparc_tls_gd_hi22 : case Sparc :: fixup_sparc_tls_gd_lo10 : case Sparc :: fixup_sparc_tls_gd_add : case Sparc :: fixup_sparc_tls_gd_call : case Sparc :: fixup_sparc_tls_ldm_hi22 : case Sparc :: fixup_sparc_tls_ldm_lo10 : case Sparc :: fixup_sparc_tls_ldm_add : case Sparc :: fixup_sparc_tls_ldm_call : case Sparc :: fixup_sparc_tls_ldo_hix22 : case Sparc :: fixup_sparc_tls_ldo_lox10 : case Sparc :: fixup_sparc_tls_ldo_add : case Sparc :: fixup_sparc_tls_ie_hi22 : case Sparc :: fixup_sparc_tls_ie_lo10 : case Sparc :: fixup_sparc_tls_ie_ld : case Sparc :: fixup_sparc_tls_ie_ldx : case Sparc :: fixup_sparc_tls_ie_add : case Sparc :: fixup_sparc_tls_le_hix22 : case Sparc :: fixup_sparc_tls_le_lox10 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static void ix86_avx256_split_vector_move_misalign ( rtx op0 , rtx op1 ) { rtx m ; rtx ( * extract ) ( rtx , rtx , rtx ) ; machine_mode mode ; if ( ( MEM_P ( op1 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_LOAD ) || ( MEM_P ( op0 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_STORE ) ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } rtx orig_op0 = NULL_RTX ; mode = GET_MODE ( op0 ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case E_V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case E_V16BFmode : extract = gen_avx_vextractf128v16bf ; mode = V8BFmode ; break ; case E_V16HFmode : extract = gen_avx_vextractf128v16hf ; mode = V8HFmode ; break ; case E_V8SFmode : extract = gen_avx_vextractf128v8sf ; mode = V4SFmode ; break ; case E_V4DFmode : extract = gen_avx_vextractf128v4df ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , 0 ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , 16 ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( MEM_P ( op0 ) ) { m = adjust_address ( op0 , mode , 0 ) ; emit_insn ( extract ( m , op1 , const0_rtx ) ) ; m = adjust_address ( op0 , mode , 16 ) ; emit_insn ( extract ( m , copy_rtx ( op1 ) , const1_rtx ) ) ; } else gcc_unreachable ( ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; } </s>

Split 32-byte AVX unaligned load and store if needed .


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: SExt : return X86SelectSExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: UIToFP : return X86SelectUIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; MVT SrcVT , DstVT ; if ( ! isTypeLegal ( I -> getOperand ( 0 ) -> getType ( ) , SrcVT ) || ! isTypeLegal ( I -> getType ( ) , DstVT ) ) return false ; if ( ! SrcVT . isVector ( ) || ! DstVT . isVector ( ) || SrcVT . getVectorElementType ( ) == MVT :: i1 || DstVT . getVectorElementType ( ) == MVT :: i1 ) return false ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: STXVD2X : case PPC :: QVSTFDX : case PPC :: QVSTFSXs : case PPC :: QVSTFDXb : case PPC :: SPILL_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> unsigned ARMFastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with one register operand and a result register in the given register class .


<s> bool isMem ( ) const override { return false ; } </s>


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


"Switch should handle all register classes"


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { auto * ReadFunc = IsLittleEndian ? support :: endian :: read32le : support :: endian :: read32be ; if ( STI . getFeatureBits ( ) [ PPC :: FeaturePrefixInstrs ] && Bytes . size ( ) >= 8 ) { uint32_t Prefix = ReadFunc ( Bytes . data ( ) ) ; uint32_t BaseInst = ReadFunc ( Bytes . data ( ) + 4 ) ; uint64_t Inst = BaseInst | ( uint64_t ) Prefix << 32 ; DecodeStatus result = decodeInstruction ( DecoderTable64 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = 8 ; return result ; } } Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint64_t Inst = ReadFunc ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureSPE ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> int ARMTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static void emit_unlikely_jump ( rtx insn ) { rtx_insn * jump = emit_jump_insn ( insn ) ; add_reg_br_prob_note ( jump , profile_probability :: very_unlikely ( ) ) ; } </s>

Mark the previous jump instruction as unlikely .


This routine handles output of long unconditional branches that exceed the maximum range of a simple branch instruction . Since we do n't have a register available for the branch , we save register % r1 in the frame marker , load the branch destination DEST into % r1 , execute the branch , and restore % r1 in the delay slot of the branch . Since long branches may have an insn in the delay slot and the delay slot is used to restore % r1 , we in general need to extract this insn and execute it before the branch . However , to facilitate use of this function by conditional branches , we also provide an option to not extract the delay insn so that it will be emitted after the long branch . So , if there is an insn in the delay slot , it is extracted if XDELAY is nonzero . The lengths of the various long-branch sequences are 20 , 16 and 24 bytes for the portable runtime , non-PIC and PIC cases , respectively .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const char * Func ) { PreAnalyzeCallOperands ( Outs , FuncArgs , Func ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasFloatVector . clear ( ) ; CallOperandIsFixed . clear ( ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> int nds32_expand_movmemqi ( rtx dstmem , rtx srcmem , rtx total_bytes , rtx alignment ) { HOST_WIDE_INT in_words , out_words ; rtx dst_base_reg , src_base_reg ; int maximum_bytes ; if ( TARGET_REDUCED_REGS ) maximum_bytes = 16 ; else maximum_bytes = 32 ; if ( GET_CODE ( total_bytes ) != CONST_INT || GET_CODE ( alignment ) != CONST_INT || INTVAL ( total_bytes ) > maximum_bytes || INTVAL ( total_bytes ) & 3 || INTVAL ( alignment ) & 3 ) return 0 ; dst_base_reg = copy_to_mode_reg ( SImode , XEXP ( dstmem , 0 ) ) ; src_base_reg = copy_to_mode_reg ( SImode , XEXP ( srcmem , 0 ) ) ; out_words = in_words = INTVAL ( total_bytes ) / UNITS_PER_WORD ; emit_insn ( nds32_expand_load_multiple ( 0 , in_words , src_base_reg , srcmem ) ) ; emit_insn ( nds32_expand_store_multiple ( 0 , out_words , dst_base_reg , dstmem ) ) ; return 1 ; } </s>

Function to move block memory content by using load_multiple and store_multiple . This is auxiliary extern function to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> static int ix86_fp_comparison_fcomi_cost ( enum rtx_code code ) { enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_CMOVE ) return 1024 ; ix86_fp_comparison_codes ( code , & bypass_code , & first_code , & second_code ) ; return ( bypass_code != UNKNOWN || second_code != UNKNOWN ) + 2 ; } </s>

Return cost of comparison done using fcomi operation . See ix86_fp_comparison_arithmetics_cost for the metrics .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
TM
=
&
Func
.
getTarget
(
)
;
const
X86Subtarget
&
ST
=
TM
->
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
static_cast
<
const
X86InstrInfo
*
>
(
TM
->
getInstrInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> inline void assign_registers ( const_tree field , int bitpos , bool fp , assign_data_t * data ) { if ( fp ) { assign_int_registers ( bitpos , data ) ; assign_fp_registers ( field , bitpos , data ) ; } else { if ( data -> intoffset < 0 ) data -> intoffset = bitpos ; } } </s>

A subroutine of function_arg_record_value . Assign FIELD and the bits of the structure between PARMS- > intoffset and BITPOS to registers .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dest , SDValue Src , MachinePointerInfo DestPtrInfo , MachinePointerInfo SrcPtrInfo , bool isStpcpy ) const { SDVTList VTs = DAG . getVTList ( Dest . getValueType ( ) , MVT :: Other ) ; SDValue EndDest = DAG . getNode ( SystemZISD :: STPCPY , DL , VTs , Chain , Dest , Src , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; return std :: make_pair ( isStpcpy ? EndDest : Dest , EndDest . getValue ( 1 ) ) ; } </s>

Emit target-specific code that performs a strcpy or stpcpy , in cases where that is faster than a libcall .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> static bool branch_to_delay_slot_p ( rtx_insn * insn ) { rtx_insn * jump_insn ; if ( dbr_sequence_length ( ) ) return FALSE ; jump_insn = next_active_insn ( JUMP_LABEL ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( jump_insn == insn ) return TRUE ; if ( ! insn || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || extract_asm_operands ( PATTERN ( insn ) ) != NULL_RTX || get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a jump insn , has an unfilled delay slot and it branches into the delay slot . Otherwise , return FALSE .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( isOSWindows ( ) ) return X86II :: MO_NO_FLAG ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } if ( TM . getRelocationModel ( ) == Reloc :: Static ) return X86II :: MO_NO_FLAG ; return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool isEqualTo ( const MCExpr * X ) const override { if ( auto * E = dyn_cast < X86MCExpr > ( X ) ) return getRegNo ( ) == E -> getRegNo ( ) ; return false ; } </s>

Test whether two SDValues are known to compare equal .


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DF : IX86_BUILTIN_SCATTERDIV4DF ; else return NULL_TREE ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DI : IX86_BUILTIN_SCATTERDIV4DI ; else return NULL_TREE ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SF : IX86_BUILTIN_SCATTERALTDIV8SF ; else return NULL_TREE ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SI : IX86_BUILTIN_SCATTERALTDIV8SI ; else return NULL_TREE ; break ; case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DF : IX86_BUILTIN_SCATTERDIV2DF ; else return NULL_TREE ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DI : IX86_BUILTIN_SCATTERDIV2DI ; else return NULL_TREE ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SF : IX86_BUILTIN_SCATTERALTDIV4SF ; else return NULL_TREE ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SI : IX86_BUILTIN_SCATTERALTDIV4SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return get_ix86_builtin ( code ) ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s> void printPCRelImm ( const MCInst * MI , uint64_t , unsigned OpNo , raw_ostream & O ) { printPCRelImm ( MI , OpNo , O ) ; } </s>


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> static arm_stack_offsets * arm_get_frame_offsets ( void ) { struct arm_stack_offsets * offsets ; offsets = & cfun -> machine -> stack_offsets ; return offsets ; } </s>

Calculate stack offsets . These are used to calculate register elimination offsets and in prologue/epilogue code . Also calculates which registers should be saved .


<s> bool hasFusion ( ) const { return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseArithmeticLogic ( ) || hasFuseCCSelect ( ) || hasFuseLiterals ( ) ; } </s>

Return true if the CPU supports any kind of instruction fusion .


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI -> hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 ) ; } </s>

Can this function use the red zone for local allocations .


<s> virtual void print ( raw_ostream & OS ) const { llvm_unreachable ( "unimplemented!" ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> void ia64_function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ) { int words = ia64_function_arg_words ( type , mode ) ; int offset = ia64_function_arg_offset ( cum , type , words ) ; enum machine_mode hfa_mode = VOIDmode ; if ( cum -> words >= MAX_ARGUMENT_SLOTS ) return ; cum -> words += words + offset ; if ( type ) hfa_mode = hfa_element_mode ( type , 0 ) ; if ( hfa_mode != VOIDmode && ( ! cum -> prototype || named ) ) { int fp_regs = cum -> fp_regs ; int int_regs = cum -> words - words ; int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; int byte_size ; int args_byte_size ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; args_byte_size = int_regs * UNITS_PER_WORD ; offset = 0 ; for ( ; ( offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS && args_byte_size < ( MAX_ARGUMENT_SLOTS * UNITS_PER_WORD ) ) ; ) { offset += hfa_size ; args_byte_size += hfa_size ; fp_regs ++ ; } cum -> fp_regs = fp_regs ; } else if ( mode == TFmode || mode == TCmode || ( ! FLOAT_MODE_P ( mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) ) cum -> int_regs = cum -> words ; else if ( cum -> prototype ) { if ( ! named ) cum -> int_regs = cum -> words ; else cum -> fp_regs += ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ? 2 : 1 ) ; } else { cum -> fp_regs += ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ? 2 : 1 ) ; cum -> int_regs = cum -> words ; } } </s>

Update CUM to point after this argument . This is patterned after ia64_function_arg .


<s>
void
assignValueToReg
(
unsigned
ValVReg
,
unsigned
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
assert
(
VA
.
getValVT
(
)
.
getSizeInBits
(
)
<=
32
&&
"Unsupported value size"
)
;
assert
(
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
==
32
&&
"Unsupported location size"
)
;
MIRBuilder
.
getMBB
(
)
.
addLiveIn
(
PhysReg
)
;
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
32
"Unsupported value size"
32
"Unsupported location size"


<s> static bool mips_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { if ( TARGET_FLOATXX && hard_regno_nregs ( regno , mode ) == 1 && FP_REG_P ( regno ) && ( regno & 1 ) != 0 ) return true ; if ( ISA_HAS_MSA && FP_REG_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 ) return true ; return false ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . Odd-numbered single-precision registers are not considered callee-saved for o32 FPXX as they will be clobbered when run on an FR=1 FPU . MSA vector registers with MODE > 64 bits are part clobbered too .


<s>
static
void
recombine_stvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_DEST
(
body
)
)
==
MEM
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
)
;
rtx
mem
=
SET_DEST
(
body
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
)
;
if
(
and_operation
!=
0
)
{
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
df_ref
src_use
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_USE
(
src_use
,
insn_info
)
{
if
(
!
rtx_equal_p
(
DF_REF_REG
(
src_use
)
,
src_reg
)
)
continue
;
struct
df_link
*
link
=
DF_REF_CHAIN
(
src_use
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
XEXP
(
mem
,
0
)
=
and_operation
;
SET_SRC
(
body
)
=
src_reg
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"stvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the store for an stvx pattern , put it in canonical form .


<s> bool X86TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? 64 : 32 ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } if ( MemVT . getSizeInBits ( ) > Subtarget . getPreferVectorWidth ( ) ) return false ; return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> bool ARMGlobalMerge :: runOnFunction ( Function & F ) { return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> HOST_WIDE_INT arm_compute_initial_elimination_offset ( unsigned int from , unsigned int to ) { arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; switch ( from ) { case ARG_POINTER_REGNUM : switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return 0 ; case FRAME_POINTER_REGNUM : return offsets -> soft_frame - offsets -> saved_args ; case ARM_HARD_FRAME_POINTER_REGNUM : if ( offsets -> frame == offsets -> saved_regs ) return 0 ; return ( frame_pointer_needed && cfun -> static_chain_decl != NULL && ! cfun -> machine -> uses_anonymous_args ) ? 4 : 0 ; case STACK_POINTER_REGNUM : return offsets -> outgoing_args - ( offsets -> saved_args + 4 ) ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; case FRAME_POINTER_REGNUM : switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return 0 ; case ARM_HARD_FRAME_POINTER_REGNUM : return offsets -> frame - offsets -> soft_frame ; case STACK_POINTER_REGNUM : return offsets -> outgoing_args - offsets -> soft_frame ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; default : gcc_unreachable ( ) ; } } </s>

Compute the distance from register FROM to register TO . These can be the arg pointer ( 26 ) , the soft frame pointer ( 25 ) , the stack pointer ( 13 ) or the hard frame pointer ( 11 ) . Typical stack layout looks like this : old stack pointer - > | | -- -- | | \ | | saved arguments for | | vararg functions | | / -- hard FP & arg pointer - > | | \ | | stack | | frame | | / -- | | \ | | call saved | | registers soft frame pointer - > | | / -- | | \ | | local | | variables | | / -- | | \ | | outgoing | | arguments current stack pointer - > | | / -- For a given funciton some or all of these stack compomnents may not be needed , giving rise to the possibility of eliminating some of the registers . The values returned by this function must reflect the behaviour of arm_expand_prologue ( ) and arm_compute_save_reg_mask ( ) . The sign of the number returned reflects the direction of stack growth , so the values are positive for all eliminations except from the soft frame pointer to the hard frame pointer .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . ) Return a number of integer regsiters advanced over .