<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
Modified
|=
runOnInstruction
(
&
MI
)
;
}
}
for
(
MachineInstr
*
MI
:
DeadInstr
)
{
MI
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool sh_dynamicalize_shift_p ( rtx count ) { gcc_assert ( CONST_INT_P ( count ) ) ; const int shift_amount_i = INTVAL ( count ) & 31 ; int insn_count ; if ( shift_amount_i == 31 ) insn_count = 2 ; else insn_count = ashl_lshr_seq [ shift_amount_i ] . insn_count ; return TARGET_DYNSHIFT && ( insn_count > 1 + SH_DYNAMIC_SHIFT_COST ) ; } </s>

Return true if it is potentially beneficial to use a dynamic shift instruction ( shad / shar ) instead of a combination of 1/2/8/16 shift instructions for the specified shift count . If dynamic shifts are not available , always return false .


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static rtx moxie_function_value ( const_tree valtype , const_tree fntype_or_decl ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , MOXIE_R0 ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . We always return values in register $ r0 for moxie .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
"0x"
;
O
.
write_hex
(
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> void F2003fInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( F2003f :: KRZmr ) ) . addFrameIndex ( FrameIdx ) . addReg ( 0 ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx alignment_with_canonical_addr ( rtx align ) { rtx canon ; rtx addr = XEXP ( align , 0 ) ; if ( REG_P ( addr ) ) canon = addr ; else if ( GET_CODE ( addr ) == PLUS ) { rtx addrop0 = XEXP ( addr , 0 ) ; rtx addrop1 = XEXP ( addr , 1 ) ; if ( ! REG_P ( addrop0 ) ) addrop0 = force_reg ( GET_MODE ( addrop0 ) , addrop0 ) ; if ( ! REG_P ( addrop1 ) ) addrop1 = force_reg ( GET_MODE ( addrop1 ) , addrop1 ) ; canon = gen_rtx_PLUS ( GET_MODE ( addr ) , addrop0 , addrop1 ) ; } else canon = force_reg ( GET_MODE ( addr ) , addr ) ; return gen_rtx_AND ( GET_MODE ( align ) , canon , GEN_INT ( - 16 ) ) ; } </s>

Return RTX with its address canonicalized to ( reg ) or ( + reg reg ) . Here RTX is an ( & addr ( const_int -16 ) ) . Always return a new copy to avoid problems with combine .


<s> void mips_declare_object_name ( FILE * stream , const char * name , tree decl ATTRIBUTE_UNUSED ) { if ( USE_GNU_UNIQUE_OBJECT && DECL_ONE_ONLY ( decl ) && ( ! DECL_ARTIFICIAL ( decl ) || ! TREE_READONLY ( decl ) ) ) ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , "gnu_unique_object" ) ; else ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , "object" ) ; size_directive_output = 0 ; if ( ! flag_inhibit_size_directive && DECL_SIZE ( decl ) ) { HOST_WIDE_INT size ; size_directive_output = 1 ; size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; } mips_declare_object ( stream , name , "" , ":\n" ) ; } </s>

Implement ASM_DECLARE_OBJECT_NAME . This is like most of the standard ELF definitions except that it uses mips_declare_object ( ) to emit the label .


<s> void loongarch_expand_prologue ( void ) { struct loongarch_frame_info * frame = & cfun -> machine -> frame ; HOST_WIDE_INT size = frame -> total_size ; rtx insn ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( ( frame -> mask | frame -> fmask ) != 0 ) { HOST_WIDE_INT step1 = MIN ( size , loongarch_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; size -= step1 ; loongarch_for_each_saved_reg ( size , loongarch_save_reg ) ; } if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; loongarch_emit_stack_tie ( ) ; } if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { HOST_WIDE_INT first = get_stack_check_protect ( ) ; if ( frame -> total_size == 0 ) { dump_stack_clash_frame_info ( NO_PROBE_NO_FRAME , false ) ; return ; } if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { HOST_WIDE_INT interval ; if ( flag_stack_clash_protection ) interval = STACK_CLASH_PROTECTION_GUARD_SIZE ; else interval = PROBE_INTERVAL ; if ( size > interval && size > first ) loongarch_emit_probe_stack_range ( first , size - first ) ; else loongarch_emit_probe_stack_range ( first , size ) ; } else loongarch_emit_probe_stack_range ( first , size ) ; if ( size > 0 ) { insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; loongarch_set_frame_expr ( insn ) ; } return ; } if ( size > 0 ) { if ( IMM12_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; } else { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , LARCH_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; loongarch_set_frame_expr ( insn ) ; } } } </s>


"code model %s does not support PIC mode"

Adjust target options after streaming them in . This is mainly about reconciling them with global options .


"attribute %<target%> argument not a string"

"malformed %<target()%> pragma or attribute"

"pragma or attribute %<target(\"%s\")%> is not valid"

"malformed %<target(\"%s\")%> pragma or attribute"

Parse the tree in ARGS that contains the target attribute information and update the global target options space . PRAGMA_OR_ATTR is a string to be used in error messages , specifying whether this is processing a target attribute or a target pragma .


<s> static bool mem_ok_for_ldrd_strd ( rtx mem , rtx * base , rtx * offset , HOST_WIDE_INT * align ) { rtx addr ; gcc_assert ( base != NULL && offset != NULL ) ; if ( side_effects_p ( mem ) ) return false ; if ( SUBREG_P ( mem ) ) return false ; gcc_assert ( MEM_P ( mem ) ) ; * offset = const0_rtx ; * align = MEM_ALIGN ( mem ) ; addr = XEXP ( mem , 0 ) ; if ( ! arm_legitimate_address_p ( DImode , addr , reload_in_progress || reload_completed ) ) return false ; if ( REG_P ( addr ) ) { * base = addr ; return true ; } else if ( GET_CODE ( addr ) == PLUS ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return ( REG_P ( * base ) && CONST_INT_P ( * offset ) ) ; } return false ; } </s>

Helper for gen_operands_ldrd_strd . Returns true iff the memory operand MEM 's address contains an immediate offset from the base register and has no side effects , in which case it sets BASE and OFFSET accordingly .


"extern const void *const __offload_funcs_end[];\n"

"extern const void *const __offload_vars_end[];\n\n"

"const void *const __offload_func_table[0]\n"

"__attribute__ ((__used__, visibility (\"hidden\"),\n"

"section (\".gnu.offload_funcs\"))) = { };\n\n"

"const void *const __offload_var_table[0]\n"

"section (\".gnu.offload_vars\"))) = { };\n\n"

"const void *const __OFFLOAD_TARGET_TABLE__[]\n"

"__attribute__ ((__used__, visibility (\"hidden\"))) = {\n"

"  &__offload_func_table, &__offload_funcs_end,\n"

"  &__offload_var_table, &__offload_vars_end\n"

"void target_register_lib (const void *);\n\n"

"  target_register_lib (__OFFLOAD_TARGET_TABLE__);\n"

Generates object file with the descriptor for the target library .


<s>
unsigned
MMIXMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool LoongArchAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> int mips_load_store_insns ( rtx mem , rtx_insn * insn ) { machine_mode mode ; bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ; if ( might_split_p ) { set = single_set ( insn ) ; if ( set && ! mips_split_move_insn_p ( SET_DEST ( set ) , SET_SRC ( set ) , insn ) ) might_split_p = false ; } return mips_address_insns ( XEXP ( mem , 0 ) , mode , might_split_p ) ; } </s>

Return the number of instructions needed to implement INSN , given that it loads from or stores to MEM . Assume that BASE_INSN_LENGTH is the length of one instruction .


<s> LoongArchSubtarget & LoongArchSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; if ( CPU . empty ( ) ) CPU = Is64Bit ? "generic-la64" : "generic-la32" ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ; if ( Is64Bit ) { GRLenVT = MVT :: i64 ; GRLen = 64 ; } TargetABI = Is64Bit ? LoongArchABI :: ABI_LP64D : LoongArchABI :: ABI_ILP32D ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return true ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> bool X86TargetLowering :: isCtlzFast ( ) const { return Subtarget . hasFastLZCNT ( ) ; } </s>

Return true if ctlz instruction is fast .


"argument to %qs must be a 2-bit unsigned literal"


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; char * NewOpcode = new char [ Name . size ( ) + 1 ] ; memcpy ( NewOpcode , Name . data ( ) , Name . size ( ) ) ; NewOpcode [ Name . size ( ) ] = '+' ; Name = StringRef ( NewOpcode , Name . size ( ) + 1 ) ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; char * NewOpcode = new char [ Name . size ( ) + 1 ] ; memcpy ( NewOpcode , Name . data ( ) , Name . size ( ) ) ; NewOpcode [ Name . size ( ) ] = '-' ; Name = StringRef ( NewOpcode , Name . size ( ) + 1 ) ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || isTargetAndroid ( ) ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMemImm ( DAG , DL , SystemZISD :: MVC , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return emitMemMemReg ( DAG , DL , SystemZISD :: MVC , Chain , Dst , Src , Size ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC


<s> FastISel * PPC :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const PPCSubtarget & Subtarget = FuncInfo . MF -> getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . is64BitELFABI ( ) ) return new PPCFastISel ( FuncInfo , LibInfo ) ; return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> unsigned getMaxInlineSizeThreshold ( ) const { return MaxInlineSizeThreshold ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s>
SDValue
SystemZTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
lowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
lowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
cast
<
GlobalAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
cast
<
GlobalAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
cast
<
BlockAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
cast
<
JumpTableSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
cast
<
ConstantPoolSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
BITCAST
:
return
lowerBITCAST
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
lowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
lowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
lowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
lowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
lowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
OR
:
return
lowerOR
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_SWAPW
)
;
case
ISD
::
ATOMIC_LOAD_ADD
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_ADD
)
;
case
ISD
::
ATOMIC_LOAD_SUB
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_SUB
)
;
case
ISD
::
ATOMIC_LOAD_AND
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_AND
)
;
case
ISD
::
ATOMIC_LOAD_OR
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_OR
)
;
case
ISD
::
ATOMIC_LOAD_XOR
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_XOR
)
;
case
ISD
::
ATOMIC_LOAD_NAND
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_NAND
)
;
case
ISD
::
ATOMIC_LOAD_MIN
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_MIN
)
;
case
ISD
::
ATOMIC_LOAD_MAX
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_MAX
)
;
case
ISD
::
ATOMIC_LOAD_UMIN
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_UMIN
)
;
case
ISD
::
ATOMIC_LOAD_UMAX
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_UMAX
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
return
lowerATOMIC_CMP_SWAP
(
Op
,
DAG
)
;
case
ISD
::
STACKSAVE
:
return
lowerSTACKSAVE
(
Op
,
DAG
)
;
case
ISD
::
STACKRESTORE
:
return
lowerSTACKRESTORE
(
Op
,
DAG
)
;
case
ISD
::
PREFETCH
:
return
lowerPREFETCH
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void computeKnownBits ( SelectionDAG & DAG , SDValue Op , APInt & KnownZero , APInt & KnownOne ) { if ( Op . getOpcode ( ) == ARMISD :: BFI ) { computeKnownBits ( DAG , Op . getOperand ( 0 ) , KnownZero , KnownOne ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; KnownZero &= Mask ; KnownOne &= Mask ; return ; } if ( Op . getOpcode ( ) == ARMISD :: CMOV ) { APInt KZ2 ( KnownZero . getBitWidth ( ) , 0 ) ; APInt KO2 ( KnownOne . getBitWidth ( ) , 0 ) ; computeKnownBits ( DAG , Op . getOperand ( 0 ) , KnownZero , KnownOne ) ; computeKnownBits ( DAG , Op . getOperand ( 1 ) , KZ2 , KO2 ) ; KnownZero &= KZ2 ; KnownOne &= KO2 ; return ; } return DAG . computeKnownBits ( Op , KnownZero , KnownOne ) ; } </s>

Determine which bits of Op are known to be either zero or one and return them in Known .


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void LC2200InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , MI , DL , get ( LC2200 :: ADD ) ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( LC2200 :: zero ) ; } </s>


<s>
const
char
*
output_move_vfp
(
rtx
*
operands
)
{
rtx
reg
,
mem
,
addr
,
ops
[
2
]
;
int
load
=
REG_P
(
operands
[
0
]
)
;
int
dp
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
8
;
int
sp
=
(
!
TARGET_VFP_FP16INST
||
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
4
)
;
int
integer_p
=
GET_MODE_CLASS
(
GET_MODE
(
operands
[
0
]
)
)
==
MODE_INT
;
const
char
*
templ
;
char
buff
[
50
]
;
machine_mode
mode
;
reg
=
operands
[
!
load
]
;
mem
=
operands
[
load
]
;
mode
=
GET_MODE
(
reg
)
;
gcc_assert
(
REG_P
(
reg
)
)
;
gcc_assert
(
IS_VFP_REGNUM
(
REGNO
(
reg
)
)
)
;
gcc_assert
(
(
mode
==
HFmode
&&
TARGET_HARD_FLOAT
)
||
mode
==
SFmode
||
mode
==
DFmode
||
mode
==
HImode
||
mode
==
SImode
||
mode
==
DImode
||
(
TARGET_NEON
&&
VALID_NEON_DREG_MODE
(
mode
)
)
)
;
gcc_assert
(
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
PRE_DEC
:
templ
=
"v%smdb%%?.%s\t%%0!, {%%%s1}%s"
;
ops
[
0
]
=
XEXP
(
addr
,
0
)
;
ops
[
1
]
=
reg
;
break
;
case
POST_INC
:
templ
=
"v%smia%%?.%s\t%%0!, {%%%s1}%s"
;
ops
[
0
]
=
XEXP
(
addr
,
0
)
;
ops
[
1
]
=
reg
;
break
;
default
:
templ
=
"v%sr%%?.%s\t%%%s0, %%1%s"
;
ops
[
0
]
=
reg
;
ops
[
1
]
=
mem
;
break
;
}
sprintf
(
buff
,
templ
,
load
"ld"
:
"st"
,
dp
"64"
:
sp
"32"
:
"16"
,
dp
"P"
:
""
,
integer_p
"\t%@ int"
:
""
)
;
output_asm_insn
(
buff
,
ops
)
;
return
""
;
}
</s>

Output a VFP load or store instruction .


<s> static bool pa_scalar_mode_supported_p ( scalar_mode mode ) { int precision = GET_MODE_PRECISION ( mode ) ; if ( TARGET_64BIT && mode == TImode ) return true ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_PARTIAL_INT : case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE ) return true ; if ( precision == LONG_TYPE_SIZE ) return true ; if ( precision == LONG_LONG_TYPE_SIZE ) return true ; return false ; case MODE_FLOAT : if ( precision == FLOAT_TYPE_SIZE ) return true ; if ( precision == DOUBLE_TYPE_SIZE ) return true ; if ( precision == LONG_DOUBLE_TYPE_SIZE ) return true ; return false ; case MODE_DECIMAL_FLOAT : return false ; default : gcc_unreachable ( ) ; } } </s>

True if MODE is valid for the target . By `` valid '' , we mean able to be manipulated in non-trivial ways . In particular , this means all the arithmetic is supported .


"fixup kind VK_Mips_GOT_DISP not supported for direct object!"


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { switch ( Constraint . size ( ) ) { case 1 : switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 || VT == MVT :: i32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_VFP2RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_VFP2RegClass ) ; break ; } break ; case 2 : if ( Constraint [ 0 ] == 'T' ) { switch ( Constraint [ 1 ] ) { default : break ; case 'e' : return RCPair ( 0U , & ARM :: tGPREvenRegClass ) ; case 'o' : return RCPair ( 0U , & ARM :: tGPROddRegClass ) ; } } break ; default : break ; } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"%<-g%> with %<-mno-apcs-frame%> may not give sensible "

"cannot use %<-mtp=cp15%> with 16-bit Thumb"

"%s only supports non-pic code on M-profile targets with the "

"%s incompatible with %<-mword-relocations%>"

Check any incompatible options that the user has specified .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; if ( STI . hasMOPS ( ) ) { return EmitMOPS ( AArch64ISD :: MOPS_MEMSET , DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , MachinePointerInfo { } ) ; } ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroName = ( V && V -> isZero ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> bool AArch64TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode * Node : Copy -> uses ( ) ) { if ( Node -> getOpcode ( ) != AArch64ISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> static tree associated_type ( tree decl ) { return ( DECL_CONTEXT ( decl ) && TYPE_P ( DECL_CONTEXT ( decl ) ) ? DECL_CONTEXT ( decl ) : NULL_TREE ) ; } </s>

Return the type that we should use to determine if DECL is imported or exported .


<s> int mems_ok_for_ldd_peep ( rtx mem1 , rtx mem2 , rtx dependent_reg_rtx ) { rtx addr1 , addr2 ; unsigned int reg1 ; HOST_WIDE_INT offset1 ; if ( MEM_VOLATILE_P ( mem1 ) || MEM_VOLATILE_P ( mem2 ) ) return 0 ; if ( MEM_ALIGN ( mem1 ) < 64 ) return 0 ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( GET_CODE ( XEXP ( addr1 , 0 ) ) != REG ) return 0 ; else { reg1 = REGNO ( XEXP ( addr1 , 0 ) ) ; if ( GET_CODE ( XEXP ( addr1 , 1 ) ) != CONST_INT ) return 0 ; offset1 = INTVAL ( XEXP ( addr1 , 1 ) ) ; } } else if ( GET_CODE ( addr1 ) != REG ) return 0 ; else { reg1 = REGNO ( addr1 ) ; offset1 = 0 ; } if ( GET_CODE ( addr2 ) != PLUS ) return 0 ; if ( GET_CODE ( XEXP ( addr2 , 0 ) ) != REG || GET_CODE ( XEXP ( addr2 , 1 ) ) != CONST_INT ) return 0 ; if ( reg1 != REGNO ( XEXP ( addr2 , 0 ) ) ) return 0 ; if ( dependent_reg_rtx != NULL_RTX && reg1 == REGNO ( dependent_reg_rtx ) ) return 0 ; if ( offset1 % 8 != 0 ) return 0 ; if ( INTVAL ( XEXP ( addr2 , 1 ) ) != offset1 + 4 ) return 0 ; return 1 ; } </s>

Return 1 if the addresses in mem1 and mem2 are suitable for use in an ldd or std insn . This can only happen when addr1 and addr2 , the addresses in mem1 and mem2 , are consecutive memory locations ( addr1 + 4 == addr2 ) . addr1 must also be aligned on a 64-bit boundary . Also iff dependent_reg_rtx is not null it should not be used to compute the address for mem1 , i.e . we can not optimize a sequence like : ld [ % o0 ] , % o0 ld [ % o0 + 4 ] , % o1 to ldd [ % o0 ] , % o0 nor : ld [ % g3 + 4 ] , % g3 ld [ % g3 ] , % g2 to ldd [ % g3 ] , % g2 But , note that the transformation from : ld [ % g2 + 4 ] , % g3 ld [ % g2 ] , % g2 to ldd [ % g2 ] , % g2 is perfectly fine . Thus , the peephole2 patterns always pass us the destination register of the first load , never the second one . For stores we do n't have a similar problem , so dependent_reg_rtx is NULL_RTX .


<s> bool moxie_offset_address_p ( rtx x ) { x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { x = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) == CONST_INT ) { unsigned int v = INTVAL ( x ) & 0xFFFF8000 ; return ( v == 0xFFFF8000 || v == 0x00000000 ) ; } } return 0 ; } </s>

Return true for memory offset addresses between -32768 and 32767 .


<s> static void rs6000_emit_vector_select ( rtx dest , rtx op1 , rtx op2 , rtx mask ) { rtx t , temp ; enum machine_mode dest_mode = GET_MODE ( dest ) ; int vsel_insn_index = get_vsel_insn ( GET_MODE ( dest ) ) ; temp = gen_reg_rtx ( dest_mode ) ; t = gen_rtx_SET ( VOIDmode , temp , gen_rtx_UNSPEC ( dest_mode , gen_rtvec ( 3 , op2 , op1 , mask ) , vsel_insn_index ) ) ; emit_insn ( t ) ; emit_move_insn ( dest , temp ) ; return ; } </s>

Emit vector select insn where DEST is destination using operands OP1 , OP2 and MASK .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: ILP ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( MCID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( MCID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: ILP ; return Sched :: RegPressure ; } </s>


<s> void SystemZMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { unsigned Opcode = MI -> getOpcode ( ) ; if ( ! AsmPrinter . OutStreamer . hasRawTextSupport ( ) ) Opcode = getShortenedInstr ( Opcode ) ; OutMI . setOpcode ( Opcode ) ; for ( unsigned I = 0 , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; MCOperand MCOp = lowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ; } } </s>


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
case
InlineAsm
::
Constraint_p
:
if
(
!
selectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
static
void
pa_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
ASM_OUTPUT_LABEL
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
)
;
fputs
(
"\t.PROC\n"
,
file
)
;
fprintf
(
file
,
"\t.CALLINFO FRAME="
HOST_WIDE_INT_PRINT_DEC
,
actual_fsize
)
;
if
(
regs_ever_live
[
2
]
)
fputs
(
",CALLS,SAVE_RP"
,
file
)
;
else
fputs
(
",NO_CALLS"
,
file
)
;
if
(
frame_pointer_needed
)
fputs
(
",SAVE_SP"
,
file
)
;
if
(
gr_saved
)
fprintf
(
file
,
",ENTRY_GR=%d"
,
gr_saved
+
2
)
;
if
(
fr_saved
)
fprintf
(
file
,
",ENTRY_FR=%d"
,
fr_saved
+
11
)
;
fputs
(
"\n\t.ENTRY\n"
,
file
)
;
remove_useless_addtr_insns
(
0
)
;
}
</s>

On HP-PA , move-double insns between fpu and cpu need an 8-byte block of memory . If any fpu reg is used in the function , we allocate such a block here , at the bottom of the frame , just in case it 's needed . If this function is a leaf procedure , then we may choose not to do a `` save '' insn . The decision about whether or not to do this is made in regclass.c .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Stack Tagging PreRA"
;
}
</s>

getPassName - Return a nice clean name for a pass .


Return an array that contains the direct target flag values and their names .


<s> static bool arm_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; int i , nelt , which ; if ( ! VALID_NEON_DREG_MODE ( vmode ) && ! VALID_NEON_QREG_MODE ( vmode ) ) return false ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . testing_p = ! target ; nelt = GET_MODE_NUNITS ( d . vmode ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { int ei = sel [ i ] & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; } switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( d . testing_p || ! rtx_equal_p ( op0 , op1 ) ) break ; case 2 : d . op0 = op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = op0 ; d . one_vector_p = true ; break ; } d . perm . new_vector ( sel . encoding ( ) , d . one_vector_p ? 1 : 2 , nelt ) ; if ( ! d . testing_p ) return arm_expand_vec_perm_const_1 ( & d ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; bool ret = arm_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> int regs_used ( rtx x , int is_dest ) { enum rtx_code code ; const char * fmt ; int i , used = 0 ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( x ) + is_dest ) ) ; return 0 ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < 16 ) return ( ( ( 1 << HARD_REGNO_NREGS ( 0 , GET_MODE ( x ) ) ) - 1 ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return 0 ; } case SET : return regs_used ( SET_SRC ( x ) , 0 ) | regs_used ( SET_DEST ( x ) , 16 ) ; case RETURN : return 0x00ffff00 ; case CLOBBER : is_dest = 1 ; break ; case MEM : is_dest = 0 ; break ; case CALL : used |= 0x00ff00f0 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) used |= regs_used ( XVECEXP ( x , i , j ) , is_dest ) ; } else if ( fmt [ i ] == 'e' ) used |= regs_used ( XEXP ( x , i ) , is_dest ) ; } return used ; } </s>

Given a X , a pattern of an insn or a part of it , return a mask of used general registers . Bits 0 .. 15 mean that the respective registers are used as inputs in the instruction . Bits 16 .. 31 mean that the registers 0 .. 15 , respectively , are used as outputs , or are clobbered . IS_DEST should be set to 16 if X is the destination of a SET , else to 0 .


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named , bool incoming ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regbase = ( incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; slotno = function_arg_slotno ( cum , mode , type , named , incoming , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 16 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST + 2 * slotno ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) return reg ; else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


<s> SDValue TeeRISCTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_TeeRISC ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool ia64_expand_load_address ( rtx dest , rtx src ) { gcc_assert ( GET_CODE ( dest ) == REG ) ; if ( GET_MODE ( dest ) != Pmode ) dest = gen_rtx_REG_offset ( dest , Pmode , REGNO ( dest ) , 0 ) ; if ( TARGET_NO_PIC ) return false ; if ( small_addr_symbolic_operand ( src , VOIDmode ) ) return false ; if ( TARGET_AUTO_PIC ) emit_insn ( gen_load_gprel64 ( dest , src ) ) ; else if ( GET_CODE ( src ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( src ) ) emit_insn ( gen_load_fptr ( dest , src ) ) ; else if ( sdata_symbolic_operand ( src , VOIDmode ) ) emit_insn ( gen_load_gprel ( dest , src ) ) ; else { HOST_WIDE_INT addend = 0 ; rtx tmp ; if ( GET_CODE ( src ) == CONST ) { HOST_WIDE_INT hi , lo ; hi = INTVAL ( XEXP ( XEXP ( src , 0 ) , 1 ) ) ; lo = ( ( hi & 0x3fff ) ^ 0x2000 ) - 0x2000 ; hi = hi - lo ; if ( lo != 0 ) { addend = lo ; src = plus_constant ( XEXP ( XEXP ( src , 0 ) , 0 ) , hi ) ; } } tmp = gen_rtx_HIGH ( Pmode , src ) ; tmp = gen_rtx_PLUS ( Pmode , tmp , pic_offset_table_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; tmp = gen_rtx_LO_SUM ( Pmode , dest , src ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; if ( addend ) { tmp = gen_rtx_PLUS ( Pmode , dest , GEN_INT ( addend ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; } } return true ; } </s>


<s> void ix86_expand_vector_move_misalign ( enum machine_mode mode , rtx operands [ ] ) { rtx op0 , op1 , m ; op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; if ( MEM_P ( op1 ) ) { if ( optimize_size ) { op0 = gen_lowpart ( V4SFmode , op0 ) ; op1 = gen_lowpart ( V4SFmode , op1 ) ; emit_insn ( gen_sse_movups ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { op0 = gen_lowpart ( V16QImode , op0 ) ; op1 = gen_lowpart ( V16QImode , op1 ) ; emit_insn ( gen_sse2_movdqu ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && mode == V2DFmode ) { rtx zero ; if ( TARGET_SSE_SPLIT_REGS ) { emit_insn ( gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; zero = op0 ; } else { zero = CONST0_RTX ( V2DFmode ) ; } m = adjust_address ( op1 , DFmode , 0 ) ; emit_insn ( gen_sse2_loadlpd ( op0 , zero , m ) ) ; m = adjust_address ( op1 , DFmode , 8 ) ; emit_insn ( gen_sse2_loadhpd ( op0 , op0 , m ) ) ; } else { if ( TARGET_SSE_PARTIAL_REG_DEPENDENCY ) emit_move_insn ( op0 , CONST0_RTX ( mode ) ) ; else emit_insn ( gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; if ( mode != V4SFmode ) op0 = gen_lowpart ( V4SFmode , op0 ) ; m = adjust_address ( op1 , V2SFmode , 0 ) ; emit_insn ( gen_sse_loadlps ( op0 , op0 , m ) ) ; m = adjust_address ( op1 , V2SFmode , 8 ) ; emit_insn ( gen_sse_loadhps ( op0 , op0 , m ) ) ; } } else if ( MEM_P ( op0 ) ) { if ( optimize_size ) { op0 = gen_lowpart ( V4SFmode , op0 ) ; op1 = gen_lowpart ( V4SFmode , op1 ) ; emit_insn ( gen_sse_movups ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && ! TARGET_SSE_TYPELESS_STORES && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { op0 = gen_lowpart ( V16QImode , op0 ) ; op1 = gen_lowpart ( V16QImode , op1 ) ; emit_insn ( gen_sse2_movdqu ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && mode == V2DFmode ) { m = adjust_address ( op0 , DFmode , 0 ) ; emit_insn ( gen_sse2_storelpd ( m , op1 ) ) ; m = adjust_address ( op0 , DFmode , 8 ) ; emit_insn ( gen_sse2_storehpd ( m , op1 ) ) ; } else { if ( mode != V4SFmode ) op1 = gen_lowpart ( V4SFmode , op1 ) ; m = adjust_address ( op0 , V2SFmode , 0 ) ; emit_insn ( gen_sse_storelps ( m , op1 ) ) ; m = adjust_address ( op0 , V2SFmode , 8 ) ; emit_insn ( gen_sse_storehps ( m , op1 ) ) ; } } else gcc_unreachable ( ) ; } </s>

Implement the movmisalign patterns for SSE . Non-SSE modes go straight to ix86_expand_vector_move .


<s> static bool classof ( const SparcMCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static const char * aarch64_mangle_type ( const_tree type ) { if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type ) , va_list_type ) ) return "St9__va_list" ; if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == 16 ) return "Dh" ; if ( TYPE_NAME ( type ) != NULL ) return aarch64_mangle_builtin_type ( type ) ; return NULL ; } </s>


<s>
void
assignValueToAddress
(
unsigned
ValVReg
,
unsigned
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
Size
=
4
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
auto
LoadVReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
;
buildLoad
(
LoadVReg
,
Addr
,
Size
,
1
,
MPO
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
LoadVReg
)
;
}
else
{
buildLoad
(
ValVReg
,
Addr
,
Size
,
1
,
MPO
)
;
}
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool PPCSubtarget :: enableMachinePipeliner ( ) const { return ( CPUDirective == PPC :: DIR_PWR9 ) && EnableMachinePipeliner ; } </s>

True if the subtarget should run MachinePipeliner .


Relax the instruction in the given fragment to the next wider instruction .


"MF used frame lowering for wrong subtarget"

Return true if the function has a redzone ( accessible bytes past the frame of the top of stack function ) as part of it 's ABI .


<s> void expand_fusion_p9_load ( rtx * operands ) { rtx tmp_reg = operands [ 0 ] ; rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset , set , clobber , insn ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == FLOAT_EXTEND || GET_CODE ( orig_mem ) == ZERO_EXTEND ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( extend , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_P9 ) ; set = gen_rtx_SET ( target , new_mem ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , tmp_reg ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ; emit_insn ( insn ) ; return ; } </s>

During the peephole2 pass , adjust and expand the insns for an extended fusion load sequence . The operands are : operands [ 0 ] register set with addis operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] . This is similar to the fusion introduced with power8 , except it scales to both loads/stores and does not require the result register to be the same as the base register . At the moment , we only do this if register set with addis is dead .


<s> static void emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; insn = emit_jump_insn ( insn ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> static bool ix86_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; const unsigned HOST_WIDE_INT always_inline_safe_mask = ( MASK_USE_8BIT_IDIV | MASK_ACCUMULATE_OUTGOING_ARGS | MASK_NO_ALIGN_STRINGOPS | MASK_AVX256_SPLIT_UNALIGNED_LOAD | MASK_AVX256_SPLIT_UNALIGNED_STORE | MASK_CLD | MASK_NO_FANCY_MATH_387 | MASK_IEEE_FP | MASK_INLINE_ALL_STRINGOPS | MASK_INLINE_STRINGOPS_DYNAMICALLY | MASK_RECIP | MASK_STACK_PROBE | MASK_STV | MASK_TLS_DIRECT_SEG_REFS | MASK_VZEROUPPER | MASK_NO_PUSH_ARGS | MASK_OMIT_LEAF_FRAME_POINTER ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; if ( ! caller_tree ) caller_tree = target_option_default_node ; if ( callee_tree == caller_tree ) return true ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; bool ret = false ; bool always_inline = ( DECL_DISREGARD_INLINE_LIMITS ( callee ) && lookup_attribute ( "always_inline" , DECL_ATTRIBUTES ( callee ) ) ) ; if ( ( ( caller_opts -> x_ix86_isa_flags & callee_opts -> x_ix86_isa_flags ) != callee_opts -> x_ix86_isa_flags ) || ( ( caller_opts -> x_ix86_isa_flags2 & callee_opts -> x_ix86_isa_flags2 ) != callee_opts -> x_ix86_isa_flags2 ) ) ret = false ; else if ( ( ! always_inline && caller_opts -> x_target_flags != callee_opts -> x_target_flags ) || ( caller_opts -> x_target_flags & ~ always_inline_safe_mask ) != ( callee_opts -> x_target_flags & ~ always_inline_safe_mask ) ) ret = false ; else if ( caller_opts -> arch != callee_opts -> arch ) ret = false ; else if ( ! always_inline && caller_opts -> tune != callee_opts -> tune ) ret = false ; else if ( caller_opts -> x_ix86_fpmath != callee_opts -> x_ix86_fpmath && ( ! ipa_fn_summaries || ipa_fn_summaries -> get ( cgraph_node :: get ( callee ) ) -> fp_expressions ) ) ret = false ; else if ( ! always_inline && caller_opts -> branch_cost != callee_opts -> branch_cost ) ret = false ; else ret = true ; return ret ; } </s>

Hook to determine if one function can safely inline another .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> virtual unsigned int execute ( function * ) { func_fma_steering * fma_steering = new func_fma_steering ; fma_steering -> execute_fma_steering ( ) ; delete fma_steering ; return 0 ; } </s>


<s>
static
tree
ix86_handle_fentry_name
(
tree
*
node
,
tree
name
,
tree
args
,
int
,
bool
*
no_add_attrs
)
{
if
(
TREE_CODE
(
*
node
)
==
FUNCTION_DECL
&&
TREE_CODE
(
TREE_VALUE
(
args
)
)
==
STRING_CST
)
;
else
{
warning
(
OPT_Wattributes
,
"%qE attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle fentry_name / fentry_section attribute .


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectT2ShifterOperandReg ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static int first_altivec_reg_to_save ( void ) { int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + 1 ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + 20 ; for ( i = FIRST_ALTIVEC_REGNO + 20 ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( save_reg_p ( i ) ) break ; return i ; } </s>


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg 32 32 ISD::InputArg 32 PPC PPC PPC


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
CallingConv
::
ID
CC
=
MF
->
getFunction
(
)
->
getCallingConv
(
)
;
if
(
MF
->
getFunction
(
)
->
hasFnAttribute
(
"no_caller_saved_registers"
)
)
CC
=
CallingConv
::
X86_INTR
;
switch
(
CC
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_64_AllRegs_SaveList
;
return
CSR_64_AllRegs_NoSSE_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
if
(
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_64_SwiftError_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_LR_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
SwiftTail
)
return
CSR_AArch64_AAPCS_SwiftTail_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
)
return
CSR_AArch64_AAPCS_X18_SaveList
;
if
(
hasSVEArgsOrReturn
(
MF
)
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> OperandMatchResultTy MipsAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { SmallVector < std :: unique_ptr < MCParsedAsmOperand > , 1 > Operands ; OperandMatchResultTy ResTy = parseAnyRegister ( Operands ) ; if ( ResTy == MatchOperand_Success ) { assert ( Operands . size ( ) == 1 ) ; MipsOperand & Operand = static_cast < MipsOperand & > ( * Operands . front ( ) ) ; StartLoc = Operand . getStartLoc ( ) ; EndLoc = Operand . getEndLoc ( ) ; if ( Operand . isGPRAsmReg ( ) ) { RegNo = isGP64bit ( ) ? Operand . getGPR64Reg ( ) : Operand . getGPR32Reg ( ) ; } return ( RegNo == ( unsigned ) - 1 ) ? MatchOperand_NoMatch : MatchOperand_Success ; } assert ( Operands . size ( ) == 0 ) ; return ( RegNo == ( unsigned ) - 1 ) ? MatchOperand_NoMatch : MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> bool X86TTIImpl :: isLegalMaskedStore ( Type * DataType ) { return isLegalMaskedLoad ( DataType ) ; } </s>

Return true if the target supports masked store .


<s>
SDValue
SparcTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Sparc32
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; if ( bitmap_bit_p ( in , LR_REGNO ) || bitmap_bit_p ( gen , LR_REGNO ) || bitmap_bit_p ( kill , LR_REGNO ) ) bitmap_set_bit ( components , 0 ) ; if ( bitmap_bit_p ( in , TOC_REGNUM ) || bitmap_bit_p ( gen , TOC_REGNUM ) || bitmap_bit_p ( kill , TOC_REGNUM ) ) bitmap_set_bit ( components , 2 ) ; return components ; } </s>


<s> static bool arm_block_set_unaligned_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { unsigned int i , j , nelt_v16 , nelt_v8 , nelt_mode ; rtx dst , mem ; rtx val_elt , val_vec , reg ; rtx rval [ MAX_VECT_LEN ] ; rtx ( * gen_func ) ( rtx , rtx ) ; machine_mode mode ; unsigned HOST_WIDE_INT v = value ; gcc_assert ( ( align & 0x3 ) != 0 ) ; nelt_v8 = GET_MODE_NUNITS ( V8QImode ) ; nelt_v16 = GET_MODE_NUNITS ( V16QImode ) ; if ( length >= nelt_v16 ) { mode = V16QImode ; gen_func = gen_movmisalignv16qi ; } else { mode = V8QImode ; gen_func = gen_movmisalignv8qi ; } nelt_mode = GET_MODE_NUNITS ( mode ) ; gcc_assert ( length >= nelt_mode ) ; if ( ! arm_block_set_vect_profit_p ( length , align , mode ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , 0 ) ) ; mem = adjust_automodify_address ( dstbase , mode , dst , 0 ) ; v = sext_hwi ( v , BITS_PER_WORD ) ; val_elt = GEN_INT ( v ) ; for ( j = 0 ; j < nelt_mode ; j ++ ) rval [ j ] = val_elt ; reg = gen_reg_rtx ( mode ) ; val_vec = gen_rtx_CONST_VECTOR ( mode , gen_rtvec_v ( nelt_mode , rval ) ) ; emit_move_insn ( reg , val_vec ) ; for ( i = 0 ; ( i + nelt_mode <= length ) ; i += nelt_mode ) { emit_insn ( ( * gen_func ) ( mem , reg ) ) ; if ( i + 2 * nelt_mode <= length ) emit_insn ( gen_add2_insn ( dst , GEN_INT ( nelt_mode ) ) ) ; } gcc_assert ( ( i + nelt_v8 ) > length || mode == V16QImode ) ; if ( i + nelt_v8 < length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - i ) ) ) ; if ( ( length & 1 ) != 0 && align >= 2 ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; } else if ( i < length && i + nelt_v8 >= length ) { if ( mode == V16QImode ) { reg = gen_lowpart ( V8QImode , reg ) ; mem = adjust_automodify_address ( dstbase , V8QImode , dst , 0 ) ; } emit_insn ( gen_add2_insn ( dst , GEN_INT ( ( length - i ) + ( nelt_mode - nelt_v8 ) ) ) ) ; if ( ( length & 1 ) != 0 && align >= 2 ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_movmisalignv8qi ( mem , reg ) ) ; } return true ; } </s>

Set a block of memory using vectorization instructions for the unaligned case . We fill the first LENGTH bytes of the memory area starting from DSTBASE with byte constant VALUE . ALIGN is the alignment requirement of memory . Return TRUE if succeeded .


<s> static bool moxie_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REG ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


<s>
static
unsigned
getInstSizeInBytes
(
const
MachineInstr
&
MI
,
const
SystemZInstrInfo
*
TII
)
{
unsigned
Size
=
TII
->
getInstSizeInBytes
(
MI
)
;
assert
(
(
Size
||
MI
.
isDebugOrPseudoInstr
(
)
||
MI
.
isPosition
(
)
||
MI
.
isKill
(
)
||
MI
.
isImplicitDef
(
)
||
MI
.
getOpcode
(
)
==
SystemZ
::
MemBarrier
||
MI
.
isInlineAsm
(
)
||
MI
.
getOpcode
(
)
==
SystemZ
::
STACKMAP
||
MI
.
getOpcode
(
)
==
SystemZ
::
PATCHPOINT
)
&&
"Missing size value for instruction."
)
;
return
Size
;
}
</s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .

SystemZ
SystemZ
SystemZ::MemBarrier
SystemZ::STACKMAP
SystemZ::PATCHPOINT
"Missing size value for instruction."


<s> bool ARMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Restores ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST_IMM ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register , NumAlignedDPRCS2Regs ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register , 0 ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register , 0 ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void X86AsmPrinter :: emitEndOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; emitAsanMemaccessSymbols ( M ) ; if ( TT . isOSBinFormatMachO ( ) ) { emitNonLazyStubs ( MMI , * OutStreamer ) ; emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } else if ( TT . isOSBinFormatCOFF ( ) ) { if ( MMI -> usesMSVCFloatingPoint ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86 ) ? "__fltused" : "_fltused" ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; return ; } emitStackMaps ( SM ) ; } else if ( TT . isOSBinFormatELF ( ) ) { emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool AArch64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f128 ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> unsigned PPCTTIImpl :: getPrefetchDistance ( ) { return PrefDist ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> void ARMInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; if ( Orig -> getOpcode ( ) == ARM :: MOVi2pieces ) { RI . emitLoadConstPool ( MBB , I , dl , DestReg , SubIdx , Orig -> getOperand ( 1 ) . getImm ( ) , ( ARMCC :: CondCodes ) Orig -> getOperand ( 2 ) . getImm ( ) , Orig -> getOperand ( 3 ) . getReg ( ) ) ; return ; } MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
tree
target_parts
=
DECL_FUNCTION_SPECIFIC_TARGET
(
decl
)
;
struct
cl_target_option
*
targ_options
;
if
(
target_parts
)
targ_options
=
TREE_TARGET_OPTION
(
target_parts
)
;
else
targ_options
=
TREE_TARGET_OPTION
(
target_option_current_node
)
;
gcc_assert
(
targ_options
)
;
std
::
string
arch_to_print
;
if
(
targ_options
->
x_arm_arch_string
)
arch_to_print
=
targ_options
->
x_arm_arch_string
;
if
(
arch_to_print
!=
arm_last_printed_arch_string
)
{
std
::
string
arch_name
=
arch_to_print
.
substr
(
0
,
arch_to_print
.
find
(
"+"
)
)
;
asm_fprintf
(
asm_out_file
,
"\t.arch %s\n"
,
arch_name
.
c_str
(
)
)
;
const
arch_option
*
arch
=
arm_parse_arch_option_name
(
all_architectures
,
"-march"
,
targ_options
->
x_arm_arch_string
)
;
auto_sbitmap
opt_bits
(
isa_num_bits
)
;
gcc_assert
(
arch
)
;
if
(
arch
->
common
.
extensions
)
{
for
(
const
struct
cpu_arch_extension
*
opt
=
arch
->
common
.
extensions
;
opt
->
name
!=
;
opt
++
)
{
if
(
!
opt
->
remove
)
{
arm_initialize_isa
(
opt_bits
,
opt
->
isa_bits
)
;
if
(
bitmap_subset_p
(
opt_bits
,
arm_active_target
.
isa
)
&&
!
bitmap_subset_p
(
opt_bits
,
isa_all_fpubits
)
)
asm_fprintf
(
asm_out_file
,
"\t.arch_extension %s\n"
,
opt
->
name
)
;
}
}
}
arm_last_printed_arch_string
=
arch_to_print
;
}
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
std
::
string
fpu_to_print
=
TARGET_SOFT_FLOAT
"softvfp"
:
arm_identify_fpu_from_isa
(
arm_active_target
.
isa
)
;
if
(
fpu_to_print
!=
arm_last_printed_arch_string
)
{
asm_fprintf
(
asm_out_file
,
"\t.fpu %s\n"
,
fpu_to_print
.
c_str
(
)
)
;
arm_last_printed_fpu_string
=
fpu_to_print
;
}
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .

arm
0
"+"
"\t.arch %s\n"
"-march"
"\t.arch_extension %s\n"
"\t.syntax unified\n"
"\t.code 32\n"
"\t.code\t16\n\t.thumb_func\n"
"\t.thumb\n\t.thumb_func\n"
"\t.arm\n"
"softvfp"
"\t.fpu %s\n"


<s> static void sparc_asm_function_epilogue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { rtx_insn * insn = get_last_insn ( ) ; rtx last_real_insn = prev_real_insn ( insn ) ; if ( last_real_insn && NONJUMP_INSN_P ( last_real_insn ) && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE ) last_real_insn = XVECEXP ( PATTERN ( last_real_insn ) , 0 , 0 ) ; if ( last_real_insn && CALL_P ( last_real_insn ) && ! SIBLING_CALL_P ( last_real_insn ) ) fputs ( "\tnop\n" , file ) ; sparc_output_deferred_case_vectors ( ) ; } </s>

This function generates the assembly code for function exit .


<s> TargetPassConfig * LoongArchTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LoongArchPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

"incompatible options %<-mstack-protector-guard=global%> and "

"This architecture does not support branch protection "

"Return address signing is not supported with %<-mtpcs-frame%>."

Reset options between modes that the user has specified .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const char * OpenRISCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case OpenRISCISD :: RET_FLAG : return "OpenRISCISD::RET_FLAG" ; case OpenRISCISD :: CALL : return "OpenRISCISD::CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

OpenRISC OpenRISC OpenRISCISD::RET_FLAG "OpenRISCISD::RET_FLAG" OpenRISCISD::CALL "OpenRISCISD::CALL"


<s>
TargetTransformInfo
::
PopcntSupportKind
PPCTTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
if
(
ST
->
hasPOPCNTD
(
)
&&
TyWidth
<=
64
)
return
TTI
::
PSK_FastHardware
;
return
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .

PowerPC
PPC
"Ty width must be power of 2"
64


Return true if the vector misalignment factor is supported by the target .


<s> int thumb_legitimate_offset_p ( enum machine_mode mode , HOST_WIDE_INT val ) { switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return val >= 0 && val < 32 ; case 2 : return val >= 0 && val < 64 && ( val & 1 ) == 0 ; default : return ( val >= 0 && ( val + GET_MODE_SIZE ( mode ) ) <= 128 && ( val & 3 ) == 0 ) ; } } </s>

Return nonzero if VAL can be used as an offset in a Thumb-state address instruction of mode MODE .


";; %smode fixup for i%d; addr %lu, range (%ld,%ld): "

Record INSN , which will need fixing up to load a value from the minipool . ADDRESS is the offset of the insn since the start of the function ; LOC is a pointer to the part of the insn which requires fixing ; VALUE is the constant that must be loaded , which is of type MODE .


"passing %qT to argument %d of %qE, which expects"

Require argument ARGNO to be a 32-bit or 64-bit scalar integer type . Return the associated type suffix on success , otherwise report an error and return NUM_TYPE_SUFFIXES .


<s> MVT getVectorIdxTy ( ) const override { return MVT :: i32 ; } </s>

Returns the type to be used for the index operand of : ISD : :INSERT_VECTOR_ELT , ISD : :EXTRACT_VECTOR_ELT , ISD : :INSERT_SUBVECTOR , and ISD : :EXTRACT_SUBVECTOR .


<s> static machine_mode pa_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ) { if ( for_return == 0 ) return mode ; return promote_mode ( type , mode , punsignedp ) ; } </s>

Promote the return value , but not the arguments .


<s> static inline bool mode_supports_vmx_dform ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_OFFSET ) != 0 ) ; } </s>

Return true if we have D-form addressing in altivec registers .


<s> unsigned int rs6000_cost_data :: determine_suggested_unroll_factor ( loop_vec_info loop_vinfo ) { class loop * loop = LOOP_VINFO_LOOP ( loop_vinfo ) ; if ( loop -> unroll == 1 || ( OPTION_SET_P ( flag_unroll_loops ) && ! flag_unroll_loops ) || ( OPTION_SET_P ( flag_unroll_all_loops ) && ! flag_unroll_all_loops ) ) return 1 ; unsigned int nstmts_nonldst = m_nstmts - m_nloads - m_nstores ; if ( nstmts_nonldst == 0 ) return 1 ; unsigned int reduc_factor = m_reduc_factor > 1 ? m_reduc_factor : 1 ; unsigned int issue_width = rs6000_vect_unroll_issue ; unsigned int uf = CEIL ( reduc_factor * issue_width , nstmts_nonldst ) ; uf = MIN ( ( unsigned int ) rs6000_vect_unroll_limit , uf ) ; uf = 1 << ceil_log2 ( uf ) ; if ( LOOP_VINFO_NITERS_KNOWN_P ( loop_vinfo ) ) return uf ; if ( reduc_factor > ( unsigned int ) rs6000_vect_unroll_reduc_threshold || m_gather_load ) return uf ; HOST_WIDE_INT est_niter = get_estimated_loop_iterations_int ( loop ) ; unsigned int vf = vect_vf_for_cost ( loop_vinfo ) ; unsigned int unrolled_vf = vf * uf ; if ( est_niter == - 1 || est_niter < unrolled_vf ) return 1 ; else { unsigned int epil_niter_unr = est_niter % unrolled_vf ; unsigned int epil_niter = est_niter % vf ; if ( LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P ( loop_vinfo ) && epil_niter_unr <= vf ) return uf ; else if ( ! LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P ( loop_vinfo ) && epil_niter_unr <= epil_niter ) return uf ; } return 1 ; } </s>

Determine suggested unroll factor by considering some below factors : - unroll option/pragma which can disable unrolling for this loop ; - simple hardware resource model for non memory vector insns ; - aggressive heuristics when iteration count is unknown : - reduction case to break cross iteration dependency ; - emulated gather load ; - estimated iteration count when iteration count is unknown ;


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s>
void
SystemZInstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Pred
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
unsigned
Opc
;
if
(
SystemZ
::
GRX32BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELRMux
;
else
if
(
STI
.
hasLoadStoreOnCond2
(
)
)
Opc
=
SystemZ
::
LOCRMux
;
else
{
Opc
=
SystemZ
::
LOCR
;
MRI
.
constrainRegClass
(
DstReg
,
&
SystemZ
::
GR32BitRegClass
)
;
Register
TReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
Register
FReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
TReg
)
.
addReg
(
TrueReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
FReg
)
.
addReg
(
FalseReg
)
;
TrueReg
=
TReg
;
FalseReg
=
FReg
;
}
}
else
if
(
SystemZ
::
GR64BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELGR
;
else
Opc
=
SystemZ
::
LOCGR
;
}
else
llvm_unreachable
(
"Invalid register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> void ARMBaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? 2 : 0 ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? ARM :: tTAILJMPr : ARM :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) ; Call -> eraseFromParent ( ) ; } } </s>

Insert a custom frame for outlined functions .

ARM ARM 2 0 ARM::tTAILJMPr ARM::TAILJMPr ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL


<s> static machine_mode mips_get_reg_raw_mode ( int regno ) { if ( TARGET_FLOATXX && FP_REG_P ( regno ) ) return DFmode ; return default_get_reg_raw_mode ( regno ) ; } </s>


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return & ARM :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
static
const
char
*
ia64_invalid_conversion
(
const_tree
fromtype
,
const_tree
totype
)
{
if
(
TYPE_MODE
(
fromtype
)
==
RFmode
&&
TYPE_MODE
(
totype
)
!=
RFmode
&&
TYPE_MODE
(
totype
)
!=
VOIDmode
)
return
N_
(
"invalid conversion from %<__fpreg%>"
)
;
if
(
TYPE_MODE
(
totype
)
==
RFmode
&&
TYPE_MODE
(
fromtype
)
!=
RFmode
)
return
N_
(
"invalid conversion to %<__fpreg%>"
)
;
return
;
}
</s>

Return the diagnostic message string if conversion from FROMTYPE to TOTYPE is not allowed , NULL otherwise .

ia64
"invalid conversion from %<__fpreg%>"
"invalid conversion to %<__fpreg%>"


<s> static tree altivec_build_resolved_builtin ( tree * args , int n , const struct altivec_builtin_types * desc ) { tree impl_fndecl = rs6000_builtin_decls [ desc -> overloaded_code ] ; tree ret_type = rs6000_builtin_type ( desc -> ret_type ) ; tree argtypes = TYPE_ARG_TYPES ( TREE_TYPE ( impl_fndecl ) ) ; tree arg_type [ 4 ] ; tree call ; int i ; for ( i = 0 ; i < n ; i ++ ) arg_type [ i ] = TREE_VALUE ( argtypes ) , argtypes = TREE_CHAIN ( argtypes ) ; if ( n == 3 && desc -> code == ALTIVEC_BUILTIN_VEC_VCMPGE_P && desc -> overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P && desc -> overloaded_code != VSX_BUILTIN_XVCMPGEDP_P ) { std :: swap ( args [ 1 ] , args [ 2 ] ) ; std :: swap ( arg_type [ 1 ] , arg_type [ 2 ] ) ; args [ 0 ] = fold_build2 ( BIT_XOR_EXPR , TREE_TYPE ( args [ 0 ] ) , args [ 0 ] , build_int_cst ( NULL_TREE , 2 ) ) ; } switch ( n ) { case 0 : call = build_call_expr ( impl_fndecl , 0 ) ; break ; case 1 : call = build_call_expr ( impl_fndecl , 1 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) ) ; break ; case 2 : call = build_call_expr ( impl_fndecl , 2 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) , fully_fold_convert ( arg_type [ 1 ] , args [ 1 ] ) ) ; break ; case 3 : call = build_call_expr ( impl_fndecl , 3 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) , fully_fold_convert ( arg_type [ 1 ] , args [ 1 ] ) , fully_fold_convert ( arg_type [ 2 ] , args [ 2 ] ) ) ; break ; case 4 : call = build_call_expr ( impl_fndecl , 4 , fully_fold_convert ( arg_type [ 0 ] , args [ 0 ] ) , fully_fold_convert ( arg_type [ 1 ] , args [ 1 ] ) , fully_fold_convert ( arg_type [ 2 ] , args [ 2 ] ) , fully_fold_convert ( arg_type [ 3 ] , args [ 3 ] ) ) ; break ; default : gcc_unreachable ( ) ; } return fold_convert ( ret_type , call ) ; } </s>

Build a tree for a function call to an Altivec non-overloaded builtin . The overloaded builtin that matched the types and args is described by DESC . The N arguments are given in ARGS , respectively . Actually the only thing it does is calling fold_convert on ARGS , with a small exception for vec_ { all , any } _ { ge , le } predicates .


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( ARM :: tGPRRegClass . hasSubClassEq ( RC ) ) return ARM :: tGPRRegisterClass ; return ARMBaseRegisterInfo :: getLargestLegalSuperClass ( RC ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM::tGPRRegClass ARM::tGPRRegisterClass ARM


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> MCELFStreamer & getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED ) { static CUMULATIVE_ARGS zero_cum ; tree param , next_param ; * cum = zero_cum ; cum -> prototype = ( fntype && TYPE_ARG_TYPES ( fntype ) ) ; for ( param = fntype ? TYPE_ARG_TYPES ( fntype ) : 0 ; param != 0 ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( next_param == 0 && TREE_VALUE ( param ) != void_type_node ) cum -> gp_reg_found = 1 ; } } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; } </s>


<s> bool ix86_use_pseudo_pic_reg ( void ) { if ( ( TARGET_64BIT && ( ix86_cmodel == CM_SMALL_PIC || TARGET_PECOFF ) ) || ! flag_pic ) return false ; return true ; } </s>

Return 1 if pseudo register should be created and used to hold GOT address for PIC code .


<s> void ARMAsmPrinter :: emitEndOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; emitAlignment ( Align ( 4 ) ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetThreadLocalGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getThreadLocalPointerSection ( ) ) ; emitAlignment ( Align ( 4 ) ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ; ARMTargetStreamer & ATS = static_cast < ARMTargetStreamer & > ( TS ) ; if ( OptimizationGoals > 0 && ( Subtarget -> isTargetAEABI ( ) || Subtarget -> isTargetGNUAEABI ( ) || Subtarget -> isTargetMuslAEABI ( ) ) ) ATS . emitAttribute ( ARMBuildAttrs :: ABI_optimization_goals , OptimizationGoals ) ; OptimizationGoals = - 1 ; ATS . finishAttributeSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool X86CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { if ( Val ) return false ; MIRBuilder . buildInstr ( X86 :: RET ) . addImm ( 0 ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> int rs6000_darwin64_struct_check_p ( machine_mode mode , const_tree type ) { return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > 0 ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) == 8 ) ) ? 1 : 0 ; } </s>

Check for an item that needs to be considered specially under the darwin 64 bit ABI . These are record types where the mode is BLK or the structure is 8 bytes in size .


<s> int nds32_can_use_btgl_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) ) ; return ( TARGET_PERF_EXT && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'btgl ' instruction can be used with IVAL .


<s>
DEBUG_FUNCTION
char
*
rs6000_debug_addr_mask
(
addr_mask_type
mask
,
bool
keep_spaces
)
{
static
char
ret
[
8
]
;
char
*
p
=
ret
;
if
(
(
mask
&
RELOAD_REG_VALID
)
!=
0
)
*
p
++
=
'v'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_MULTIPLE
)
!=
0
)
*
p
++
=
'm'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_INDEXED
)
!=
0
)
*
p
++
=
'i'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_OFFSET
)
!=
0
)
*
p
++
=
'o'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_INCDEC
)
!=
0
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_MODIFY
)
!=
0
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_AND_M16
)
!=
0
)
*
p
++
=
'&'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
*
p
=
'\0'
;
return
ret
;
}
</s>

Inner function printing just the address mask for a particular reload register class .


<s>
void
mmix_asm_output_addr_vec_elt
(
FILE
*
stream
,
int
value
)
{
fprintf
(
stream
,
"\tOCTA L:%d\n"
,
value
)
;
}
</s>


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; if ( CommentStream ) { printAnnotation ( OS , Annot ) ; EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . hasMips64 ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < MipsFunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < 16 > ( MaxSPOffset ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , unsigned RegIndex , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { unsigned MaxSize = MemTy . getSizeInBytes ( ) * 8 ; if ( ! Arg . IsFixed ) MaxSize = 0 ; Register ValVReg = Arg . Regs [ RegIndex ] ; if ( VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ) { MVT LocVT = VA . getLocVT ( ) ; MVT ValVT = VA . getValVT ( ) ; if ( VA . getValVT ( ) == MVT :: i8 || VA . getValVT ( ) == MVT :: i16 ) { std :: swap ( ValVT , LocVT ) ; MemTy = LLT ( VA . getValVT ( ) ) ; } ValVReg = extendRegister ( ValVReg , VA , MaxSize ) ; } else { MemTy = LLT ( VA . getValVT ( ) ) ; } assignValueToAddress ( ValVReg , Addr , MemTy , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .