<s> int SystemZHazardRecognizer :: resourcesCost ( SUnit * SU ) { int Cost = 0 ; const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return 0 ; if ( SU -> isUnbuffered ) Cost = ( isFPdOpPreferred_distance ( SU ) ? INT_MIN : INT_MAX ) ; else if ( CriticalResourceIdx != UINT_MAX ) { for ( TargetSchedModel :: ProcResIter PI = SchedModel -> getWriteProcResBegin ( SC ) , PE = SchedModel -> getWriteProcResEnd ( SC ) ; PI != PE ; ++ PI ) if ( PI -> ProcResourceIdx == CriticalResourceIdx ) Cost = PI -> Cycles ; } return Cost ; } </s>

Return the cost of SU in regards to processor resources usage .


<s> static tree parse_type ( const function_instance & instance , const char * & format ) { int ch = * format ++ ; if ( ch == '_' ) return void_type_node ; if ( ch == 'a' ) { ch = * format ++ ; if ( ch == 'l' ) return build_const_pointer ( instance . memory_scalar_type ( ) ) ; if ( ch == 'p' ) return const_ptr_type_node ; if ( ch == 's' ) return build_pointer_type ( instance . memory_scalar_type ( ) ) ; gcc_unreachable ( ) ; } if ( ch == 'b' ) return instance . base_vector_type ( ) ; if ( ch == 'd' ) return instance . displacement_vector_type ( ) ; if ( ch == 'e' ) { if ( strncmp ( format , "pattern" , 7 ) == 0 ) { format += 7 ; return acle_svpattern ; } if ( strncmp ( format , "prfop" , 5 ) == 0 ) { format += 5 ; return acle_svprfop ; } gcc_unreachable ( ) ; } if ( ch == 's' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return scalar_types [ type_suffixes [ suffix ] . vector_type ] ; } if ( ch == 't' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; vector_type_index vector_type = type_suffixes [ suffix ] . vector_type ; unsigned int num_vectors = instance . vectors_per_tuple ( ) ; return acle_vector_types [ num_vectors - 1 ] [ vector_type ] ; } if ( ch == 'v' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return acle_vector_types [ 0 ] [ type_suffixes [ suffix ] . vector_type ] ; } gcc_unreachable ( ) ; } </s>

Read and return a type from FORMAT for function INSTANCE . Advance FORMAT beyond the type string . The format is : _ - void al - array pointer for loads ap - array pointer for prefetches as - array pointer for stores b - base vector type ( from a _ < m0 > base suffix ) d - displacement vector type ( from a _ < m1 > index or _ < m1 > offset suffix ) e < name > - an enum with the given name s < elt > - a scalar type with the given element suffix t < elt > - a vector or tuple type with given element suffix [ * 1 ] v < elt > - a vector with the given element suffix where < elt > has the format described above parse_element_type [ * 1 ] the vectors_per_tuple function indicates whether the type should be a tuple , and if so , how many vectors it should contain .


<s> static rtx gen_safe_HIGH64 ( rtx dest , HOST_WIDE_INT val ) { return gen_rtx_SET ( VOIDmode , dest , GEN_INT ( val & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ; } </s>

The optimizer is not to assume anything about exactly which bits are set for a HIGH , they are unspecified . Unfortunately this leads to many missed optimizations during CSE . We mask out the non-HIGH bits , and matches a plain movdi , to alleviate this problem .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; unsigned SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , II , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; unsigned DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , II , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> SDNode * MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallSDNode * TheCall , unsigned CallingConv , SelectionDAG & DAG ) { bool isVarArg = TheCall -> isVarArg ( ) ; DebugLoc dl = TheCall -> getDebugLoc ( ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallingConv , isVarArg , getTargetMachine ( ) , RVLocs ) ; CCInfo . AnalyzeCallResult ( TheCall , RetCC_Mips ) ; SmallVector < SDValue , 8 > ResultVals ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; ResultVals . push_back ( Chain . getValue ( 0 ) ) ; } ResultVals . push_back ( Chain ) ; return DAG . getNode ( ISD :: MERGE_VALUES , dl , TheCall -> getVTList ( ) , & ResultVals [ 0 ] , ResultVals . size ( ) ) . getNode ( ) ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> InstructionCost ARMTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , bool IsPairwiseForm , TTI :: TargetCostKind CostKind ) { EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ValVT . isSimple ( ) || ISD != ISD :: ADD ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { ISD :: ADD , MVT :: v16i8 , 1 } , { ISD :: ADD , MVT :: v8i16 , 1 } , { ISD :: ADD , MVT :: v4i32 , 1 } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( CostKind ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s> static void rs6000_frame_related ( rtx insn , rtx reg , HOST_WIDE_INT val , rtx reg2 , rtx rreg ) { rtx real , temp ; if ( reg == reg2 ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; if ( reg == rreg ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; real = copy_rtx ( PATTERN ( insn ) ) ; if ( reg2 != NULL_RTX ) real = replace_rtx ( real , reg2 , rreg ) ; real = replace_rtx ( real , reg , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ) ; if ( GET_CODE ( real ) == SET ) { rtx set = real ; temp = simplify_rtx ( SET_SRC ( set ) ) ; if ( temp ) SET_SRC ( set ) = temp ; temp = simplify_rtx ( SET_DEST ( set ) ) ; if ( temp ) SET_DEST ( set ) = temp ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { temp = simplify_rtx ( XEXP ( SET_DEST ( set ) , 0 ) ) ; if ( temp ) XEXP ( SET_DEST ( set ) , 0 ) = temp ; } } else { int i ; gcc_assert ( GET_CODE ( real ) == PARALLEL ) ; for ( i = 0 ; i < XVECLEN ( real , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( real , 0 , i ) ) == SET ) { rtx set = XVECEXP ( real , 0 , i ) ; temp = simplify_rtx ( SET_SRC ( set ) ) ; if ( temp ) SET_SRC ( set ) = temp ; temp = simplify_rtx ( SET_DEST ( set ) ) ; if ( temp ) SET_DEST ( set ) = temp ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { temp = simplify_rtx ( XEXP ( SET_DEST ( set ) , 0 ) ) ; if ( temp ) XEXP ( SET_DEST ( set ) , 0 ) = temp ; } RTX_FRAME_RELATED_P ( set ) = 1 ; } } if ( TARGET_SPE ) real = spe_synthesize_frame_save ( real ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , real , REG_NOTES ( insn ) ) ; } </s>

Add to 'insn ' a note which is PATTERN ( INSN ) but with REG replaced with ( plus : P ( reg 1 ) VAL ) , and with REG2 replaced with RREG if REG2 is not NULL . It would be nice if dwarf2out_frame_debug_expr could deduce these equivalences by itself so it was n't necessary to hold its hand so much . Do n't be tempted to always supply d2_f_d_e with the actual cfa register , ie . r31 when we are using a hard frame pointer . That fails when saving regs off r1 , and sched moves the r31 setup past the reg saves .


<s> bool sh_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_FPU_ANY && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode == V2SImode ) ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> void PPCInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , 4 > NewMIs ; PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = 0 , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case E_DImode : case E_SCmode : case E_DCmode : case E_TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ! FLOAT128_VECTOR_P ( mode ) && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || FLOAT128_VECTOR_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> const MipsTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool insertEdge ( unsigned Reg ) { return Edges . insert ( Reg ) . second ; } </s>

Update the call graph after inserting a new edge .


<s> bool SystemZFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
mmix_asm_output_reg_pop
(
FILE
*
stream
,
int
regno
)
{
fprintf
(
stream
,
"\tLDOU %s,%s,0\n\tINCL %s,8\n"
,
reg_names
[
MMIX_OUTPUT_REGNO
(
regno
)
]
,
reg_names
[
MMIX_STACK_POINTER_REGNUM
]
,
reg_names
[
MMIX_STACK_POINTER_REGNUM
]
)
;
}
</s>


<s> Optional < MCFixupKind > ARMAsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) && Name == "R_ARM_NONE" ) return FK_NONE ; return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Domain Reassignment Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( & getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16Pass ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloatPass ( getMipsTargetMachine ( ) ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> bool ARMAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printAddrMode2Operand ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> int ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 32 ) return 4 ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .


"insertNop does not support MIPS16e mode at this time"


<s> bool isThumb ( ) const { return InThumbMode ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s>
static
void
mmix_option_override
(
void
)
{
if
(
flag_pic
)
{
warning
(
0
,
"%<-f%s%> not supported: ignored"
,
(
flag_pic
>
1
)
"PIC"
:
"pic"
)
;
flag_pic
=
0
;
}
if
(
flag_verbose_asm
||
flag_debug_asm
||
flag_dump_rtl_in_asm
)
{
targetm
.
asm_out
.
byte_op
=
"\t.byte\t"
;
targetm
.
asm_out
.
aligned_op
.
hi
=
"\t.short\t"
;
targetm
.
asm_out
.
aligned_op
.
si
=
"\t.long\t"
;
targetm
.
asm_out
.
aligned_op
.
di
=
"\t.dc.a\t"
;
}
}
</s>


<s> void aarch64_emit_sve_pred_move ( rtx dest , rtx pred , rtx src ) { expand_operand ops [ 3 ] ; machine_mode mode = GET_MODE ( dest ) ; create_output_operand ( & ops [ 0 ] , dest , mode ) ; create_input_operand ( & ops [ 1 ] , pred , GET_MODE ( pred ) ) ; create_input_operand ( & ops [ 2 ] , src , mode ) ; temporary_volatile_ok v ( true ) ; expand_insn ( code_for_aarch64_pred_mov ( mode ) , 3 , ops ) ; } </s>

Emit an SVE predicated move from SRC to DEST . PRED is a predicate that is known to contain PTRUE .


<s> bool MipsInstrInfo :: SafeInForbiddenSlot ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) return false ; return ( MI . getDesc ( ) . TSFlags & MipsII :: IsCTI ) == 0 ; } </s>

Predicate to determine if an instruction can go in a forbidden slot .


<s> static int function_arg_slotno ( const struct sparc_args * cum , machine_mode mode , const_tree type , bool named , bool incoming_p , int * pregno , int * ppadding ) { int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = 0 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != 0 ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) slotno ++ , * ppadding = 1 ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) != VECTOR_TYPE && TREE_CODE ( type ) != RECORD_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } else { int intregs_p = 0 , fpregs_p = 0 , packed_p = 0 ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) fpregs_p = 1 ; else scan_record_type ( type , & intregs_p , & fpregs_p , & packed_p ) ; if ( packed_p || ! named ) fpregs_p = 0 , intregs_p = 1 ; if ( fpregs_p && slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( ! fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX ) return - 1 ; return slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s> void output_profile_hook ( int labelno ATTRIBUTE_UNUSED ) { if ( TARGET_PROFILE_KERNEL ) return ; if ( DEFAULT_ABI == ABI_AIX ) { if ( NO_PROFILE_COUNTERS ) emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , 0 , VOIDmode , 0 ) ; else { char buf [ 30 ] ; const char * label_name ; rtx fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; label_name = ( * targetm . strip_name_encoding ) ( ggc_strdup ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , 0 , VOIDmode , 1 , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LINK_REGISTER_REGNUM ; current_function_uses_pic_offset_table = 1 ; if ( MACHOPIC_INDIRECT && current_function_uses_pic_offset_table ) caller_addr_regno = 0 ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , 0 , VOIDmode , 1 , gen_rtx_REG ( Pmode , caller_addr_regno ) , Pmode ) ; } } </s>


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( TRI -> hasBasePointer ( MF ) ) SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static bool mep_get_intrinsic_insn ( int intrinsic ATTRIBUTE_UNUSED , const struct cgen_insn * * insn_ptr ATTRIBUTE_UNUSED ) { int i ; i = mep_intrinsic_insn [ intrinsic ] ; while ( i >= 0 && ! CGEN_ENABLE_INSN_P ( i ) ) i = mep_intrinsic_chain [ i ] ; if ( i >= 0 ) { * insn_ptr = & cgen_insns [ i ] ; return true ; } return false ; } </s>

See if any implementation of INTRINSIC is available to the current function . If so , store the most general implementation in * INSN_PTR and return true . Return false otherwise .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != NULL ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
static
int
rs6000_arg_partial_bytes
(
CUMULATIVE_ARGS
*
cum
,
enum
machine_mode
mode
,
tree
type
,
bool
named
)
{
int
ret
=
0
;
int
align_words
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
mode
,
type
,
named
)
&&
cum
->
nargs_prototype
>=
0
)
return
0
;
if
(
rs6000_darwin64_abi
&&
mode
==
BLKmode
&&
TREE_CODE
(
type
)
==
RECORD_TYPE
&&
int_size_in_bytes
(
type
)
>
0
)
return
0
;
align_words
=
rs6000_parm_start
(
mode
,
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
mode
,
type
)
&&
!
(
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
DEFAULT_ABI
==
ABI_AIX
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
)
{
if
(
cum
->
fregno
+
(
(
GET_MODE_SIZE
(
mode
)
+
7
)
>>
3
)
>
FP_ARG_MAX_REG
+
1
)
ret
=
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
8
;
else
if
(
cum
->
nargs_prototype
>=
0
)
return
0
;
}
if
(
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
mode
,
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


<s> const MCExpr * AArch64TargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr ) { return ConstantPools -> addEntry ( Streamer , Expr ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s> void DLXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( I -> isCall ( ) ) { emitCallInstruction ( & * I ) ; continue ; } customEmitInstruction ( & * I ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool MINA32AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { isa &= ~ OPTION_MASK_ISA_64BIT ; if ( ( isa & deferred_isa_values ) == 0 && ( isa2 & deferred_isa_values2 ) == 0 && ( ( deferred_isa_values & OPTION_MASK_ISA_MMX ) == 0 || ! ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) ) ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; if ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) deferred_isa_values &= ~ OPTION_MASK_ISA_MMX ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != 0 || ( ( ix86_builtins_isa [ i ] . isa & OPTION_MASK_ISA_MMX ) != 0 && TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != 0 ) ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; if ( ix86_builtins_isa [ i ] . pure_p ) DECL_PURE_P ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


<s> const Cpu0InstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; if ( Created ) Created -> push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < AArch64FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; AArch64IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Assigner . StackOffset , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> BitVector OpenRISCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( OpenRISC :: SP ) ; Reserved . set ( OpenRISC :: PC ) ; Reserved . set ( OpenRISC :: ZERO ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( OpenRISC :: FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

OpenRISC OpenRISC OpenRISC::SP OpenRISC::PC OpenRISC::ZERO OpenRISC::FP


"ARM64 Collect Linker Optimization Hint (LOH)"

getPassName - Return a nice clean name for a pass .


<s> bool AArch64O0PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; AArch64O0PreLegalizerCombinerInfo PCInfo ( false , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , nullptr ) ; Combiner C ( PCInfo , & TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> StackOffset CSKYFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const CSKYMachineFunctionInfo * CFI = MF . getInfo < CSKYMachineFunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = CSKY :: R14 ; Offset += CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; } else if ( RI -> hasStackRealignment ( MF ) ) { assert ( hasFP ( MF ) ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) { FrameReg = hasBP ( MF ) ? getBPReg ( STI ) : CSKY :: R14 ; Offset += MFI . getStackSize ( ) ; } else { FrameReg = getFPReg ( STI ) ; Offset += CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; } } else { if ( MFI . isFixedObjectIndex ( FI ) && hasFP ( MF ) ) { FrameReg = getFPReg ( STI ) ; Offset += CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; } else { FrameReg = hasBP ( MF ) ? getBPReg ( STI ) : CSKY :: R14 ; Offset += MFI . getStackSize ( ) ; } } return StackOffset :: getFixed ( Offset ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( getARMSubtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> int ix86_data_alignment ( tree type , unsigned int align , bool opt ) { unsigned int max_align_compat = MIN ( 256 , MAX_OFILE_ALIGNMENT ) ; unsigned int max_align = MIN ( ( unsigned ) ix86_tune_cost -> prefetch_block * 8 , MAX_OFILE_ALIGNMENT ) ; if ( max_align < BITS_PER_WORD ) max_align = BITS_PER_WORD ; switch ( ix86_align_data_type ) { case ix86_align_data_type_abi : opt = false ; break ; case ix86_align_data_type_compat : max_align = BITS_PER_WORD ; break ; case ix86_align_data_type_cacheline : break ; } if ( TARGET_IAMCU ) align = iamcu_alignment ( type , align ) ; if ( opt && AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) { if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align_compat ) && align < max_align_compat ) align = max_align_compat ; if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , 128 ) && align < 128 ) return 128 ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a static variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


"PRINT_OPERAND, invalid operand for relocation"

Print symbolic operand OP , which is part of a HIGH or LO_SUM . RELOCS is the array of relocations to use .


<s>
const
MipsMCExpr
*
MipsMCExpr
::
Create
(
MCSymbolRefExpr
::
VariantKind
VK
,
const
MCExpr
*
Expr
,
MCContext
&
Ctx
)
{
VariantKind
Kind
;
switch
(
VK
)
{
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
Kind
=
VK_Mips_LO
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
Kind
=
VK_Mips_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHER
:
Kind
=
VK_Mips_HIGHER
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHEST
:
Kind
=
VK_Mips_HIGHEST
;
break
;
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
return
new
(
Ctx
)
MipsMCExpr
(
Kind
,
Expr
)
;
}
</s>

Construct a unary instruction , given the opcode and an operand .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid kind!"
Mips


<s> rtx aarch64_reverse_mask ( machine_mode mode , unsigned int nunits ) { rtx mask ; rtvec v = rtvec_alloc ( 16 ) ; unsigned int i , j ; unsigned int usize = GET_MODE_UNIT_SIZE ( mode ) ; gcc_assert ( BYTES_BIG_ENDIAN ) ; gcc_assert ( AARCH64_VALID_SIMD_QREG_MODE ( mode ) ) ; for ( i = 0 ; i < nunits ; i ++ ) for ( j = 0 ; j < usize ; j ++ ) RTVEC_ELT ( v , i * usize + j ) = GEN_INT ( ( i + 1 ) * usize - 1 - j ) ; mask = gen_rtx_CONST_VECTOR ( V16QImode , v ) ; return force_reg ( V16QImode , mask ) ; } </s>

Generate a byte permute mask for a register of mode MODE , which has NUNITS units .


<s> Function * AArch64TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getFunction ( "__security_check_cookie" ) ; return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const SDNode * CallNode ) { PreAnalyzeCallOperands ( Outs , FuncArgs , CallNode ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloat . clear ( ) ; CallOperandIsFixed . clear ( ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> void emitBytes ( StringRef Data ) override { EmitMappingSymbol ( "$d" ) ; MCELFStreamer :: emitBytes ( Data ) ; } </s>

Emit the bytes in Data into the output .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "-hard-float" : ",-hard-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "true" "-hard-float" ",-hard-float" PPC


<s> void aarch64_general_init_builtins ( void ) { aarch64_init_fpsr_fpcr_builtins ( ) ; aarch64_init_fp16_types ( ) ; aarch64_init_bf16_types ( ) ; { aarch64_simd_switcher simd ; aarch64_init_simd_builtins ( ) ; } aarch64_init_crc32_builtins ( ) ; aarch64_init_builtin_rsqrt ( ) ; aarch64_init_rng_builtins ( ) ; aarch64_init_data_intrinsics ( ) ; tree ftype_jcvt = build_function_type_list ( intSI_type_node , double_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_JSCVT ] = aarch64_general_add_builtin ( "__builtin_aarch64_jcvtzs" , ftype_jcvt , AARCH64_JSCVT ) ; if ( ! TARGET_ILP32 ) aarch64_init_pauth_hint_builtins ( ) ; if ( TARGET_TME ) aarch64_init_tme_builtins ( ) ; if ( TARGET_MEMTAG ) aarch64_init_memtag_builtins ( ) ; } </s>

Initialize all builtins in the AARCH64_BUILTIN_GENERAL group .


Check whether or not the given MBB can be used as a epilogue for the target .


<s> int aarch64_fpconst_pow2_recip ( rtx x ) { REAL_VALUE_TYPE r0 ; if ( ! CONST_DOUBLE_P ( x ) ) return - 1 ; r0 = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( exact_real_inverse ( DFmode , & r0 ) && ! REAL_VALUE_NEGATIVE ( r0 ) ) { int ret = exact_log2 ( real_to_integer ( & r0 ) ) ; if ( ret >= 1 && ret <= 32 ) return ret ; } return - 1 ; } </s>

If X is a positive CONST_DOUBLE with a value that is the reciprocal of a power of 2 ( i.e 1/2^n ) return the number of float bits . e.g . for x== ( 1/2^n ) return n. Otherwise return -1 .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void ix86_expand_rounddf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , dxa , TWO52 , tmp , half , mhalf , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , 0 , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , 0 , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , 0 , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , res , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing round from OPERAND1 storing into OPERAND0 . Sequence that works without relying on DImode truncation via cvttsd2siq that is only available on 64bit targets .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
,
MipsTargetMachine
*
_TM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMips16HardFloat
(
Mips16HardFloat
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
AllowMixed16_32
(
Mixed16_32
|
Mips_Os16
)
,
Os16
(
Mips_Os16
)
,
RM
(
_RM
)
,
OverrideMode
(
NoOverride
)
,
TM
(
_TM
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
PreviousInMips16Mode
=
InMips16Mode
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> unsigned X86RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool use_rsqrt_p ( machine_mode mode ) { return ( ! flag_trapping_math && flag_unsafe_math_optimizations && ( ( aarch64_tune_params . approx_modes -> recip_sqrt & AARCH64_APPROX_MODE ( mode ) ) || flag_mrecip_low_precision_sqrt ) ) ; } </s>

Return true if it is safe to use the rsqrt optabs to optimize 1.0/sqrt .


<s> static void pop ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_pop_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_pop_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) , 0 ) ; } </s>

Output RTL to pop register RN from the stack .


<s> bool ARM64RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


"-fstack-check=specific not implemented for MIPS16"

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static bool rs6000_expand_vec_perm_const_1 ( rtx target , rtx op0 , rtx op1 , unsigned char perm0 , unsigned char perm1 ) { rtx x ; if ( ( perm0 & 2 ) == ( perm1 & 2 ) ) { if ( perm0 & 2 ) op0 = op1 ; else op1 = op0 ; } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & 1 ; perm1 = ( perm1 & 1 ) + 2 ; } else if ( perm0 & 2 ) { if ( perm1 & 2 ) return false ; perm0 -= 2 ; perm1 += 2 ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & 2 ) == 0 ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == 2 ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , 4 ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( 2 , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } return true ; } </s>

Expand a Paired Single or VSX Permute Doubleword constant permutation . Return true if we match an efficient implementation .


<s> void SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) , false ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( MISchedPostRA ) addPass ( & PostMachineSchedulerID ) ; else addPass ( & PostRASchedulerID ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool MipsSEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return isInt < 16 > ( MFI . getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> const MipsInstrInfo * MipsInstrInfo :: create ( MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return createMips16InstrInfo ( STI ) ; return createMipsSEInstrInfo ( STI ) ; } </s>


<s> static bool ix86_scalar_mode_supported_p ( machine_mode mode ) { if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( mode == TFmode ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> static void or1k_init_pic_reg ( void ) { if ( crtl -> profile ) cfun -> machine -> set_got_insn = emit_insn_after ( gen_set_got_tmp ( pic_offset_table_rtx ) , cfun -> machine -> set_mcount_arg_insn ) ; else { start_sequence ( ) ; cfun -> machine -> set_got_insn = emit_insn ( gen_set_got_tmp ( pic_offset_table_rtx ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; edge entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } } </s>

Worker for TARGET_INIT_PIC_REG . Initialize the cfun- > machine- > set_got_insn rtx and insert it at the entry of the current function . The rtx is just a temporary placeholder for the GOT and will be replaced or removed during or1k_expand_prologue .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> static bool ix86_vectorize_vec_perm_const_ok ( machine_mode vmode , const unsigned char * sel ) { struct expand_vec_perm_d d ; unsigned int i , nelt , which ; bool ret ; d . vmode = vmode ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = true ; switch ( d . vmode ) { case V16SFmode : case V16SImode : case V8DImode : case V8DFmode : if ( TARGET_AVX512F ) return true ; break ; case V32HImode : if ( TARGET_AVX512BW ) return true ; break ; case V64QImode : if ( TARGET_AVX512BW ) return true ; break ; case V8SImode : case V8SFmode : case V4DFmode : case V4DImode : if ( TARGET_AVX512VL ) return true ; break ; case V16HImode : if ( TARGET_AVX2 ) return true ; break ; case V32QImode : if ( TARGET_AVX2 ) return true ; break ; case V4SImode : case V4SFmode : case V8HImode : case V16QImode : if ( TARGET_XOP ) return true ; if ( TARGET_SSSE3 ) return true ; break ; case V2DImode : case V2DFmode : return true ; default : return false ; } memcpy ( d . perm , sel , nelt ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { unsigned char e = d . perm [ i ] ; gcc_assert ( e < 2 * nelt ) ; which |= ( e < nelt ? 1 : 2 ) ; } if ( which == 2 ) for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_operand_p = ( which != 3 ) ; if ( d . one_operand_p && ( d . vmode == V4SFmode || d . vmode == V4SImode ) ) return true ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_operand_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ret = ix86_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> bool ARMBaseInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { bool Found = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: CPSR ) ; bool IsCPSR = MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == ARM :: CPSR ; if ( ClobbersCPSR || IsCPSR ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . TSFlags & ARMII :: ThumbArithFlagSetting && MO . isDead ( ) && SkipDead ) continue ; Pred . push_back ( MO ) ; Found = true ; } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .

ARM ARM ARM::CPSR ARM::CPSR ARMII::ThumbArithFlagSetting


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64FI = MF . getInfo < AArch64FunctionInfo > ( ) ; STI = static_cast < const AArch64Subtarget * > ( & MF . getSubtarget ( ) ) ; SetupMachineFunction ( MF ) ; if ( STI -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; return false ; } </s>


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP && CS != X86 :: RSP && CS != X86 :: ESP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> bool AArch64InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; switch ( MI . getOpcode ( ) ) { case AArch64 :: HINT : if ( MI . getOperand ( 0 ) . getImm ( ) == 0x14 ) return true ; break ; case AArch64 :: DSB : case AArch64 :: ISB : return true ; default : ; } if ( isSEHInstruction ( MI ) ) return true ; auto Next = std :: next ( MI . getIterator ( ) ) ; return Next != MBB -> end ( ) && Next -> isCFIInstruction ( ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> void Mips16FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; TII . adjustStackPtr ( Mips :: SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips Mips Mips::SP


"Maximum call-frame size not sufficiently aligned"

lowerDynamicAlloc - Generate the code for allocating an object in the current frame .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> unsigned ARMBaseInstrInfo :: extraSizeToPredicateInstructions ( const MachineFunction & MF , unsigned NumInsts ) const { if ( ! Subtarget . isThumb2 ( ) ) return 0 ; unsigned MaxInsts = Subtarget . restrictIT ( ) ? 1 : 4 ; return divideCeil ( NumInsts , MaxInsts ) * 2 ; } </s>

Return the increase in code size needed to predicate a contiguous run of NumInsts instructions .


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( X86 :: RSP ) ; Reserved . set ( X86 :: ESP ) ; Reserved . set ( X86 :: SP ) ; Reserved . set ( X86 :: SPL ) ; Reserved . set ( X86 :: RIP ) ; Reserved . set ( X86 :: EIP ) ; Reserved . set ( X86 :: IP ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; Reserved . set ( X86 :: EBP ) ; Reserved . set ( X86 :: BP ) ; Reserved . set ( X86 :: BPL ) ; } Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool aarch64_sve_sqadd_sqsub_immediate_p ( machine_mode mode , rtx x , bool negate_p ) { if ( ! aarch64_sve_arith_immediate_p ( mode , x , negate_p ) ) return false ; rtx elt = unwrap_const_vec_duplicate ( x ) ; return negate_p == ( INTVAL ( elt ) < 0 ) ; } </s>

Return true if X is a valid immediate for the SVE SQADD and SQSUB instructions when applied to mode MODE . Negate X first if NEGATE_P is true .


<s> static bool ix86_pass_by_reference ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) { HOST_WIDE_INT msize = GET_MODE_SIZE ( mode ) ; if ( type ) { if ( TREE_CODE ( type ) == ARRAY_TYPE ) return true ; if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != 1 && msize != 2 && msize != 4 && msize != 8 ; } else if ( type && int_size_in_bytes ( type ) == - 1 ) return true ; } return false ; } </s>

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
LLT
p0
=
LLT
::
pointer
(
0
,
32
)
;
LLT
s32
=
LLT
::
scalar
(
32
)
;
Register
SPReg
=
MRI
.
createGenericVirtualRegister
(
p0
)
;
MIRBuilder
.
buildCopy
(
SPReg
,
Register
(
ARM
::
SP
)
)
;
Register
OffsetReg
=
MRI
.
createGenericVirtualRegister
(
s32
)
;
MIRBuilder
.
buildConstant
(
OffsetReg
,
Offset
)
;
Register
AddrReg
=
MRI
.
createGenericVirtualRegister
(
p0
)
;
MIRBuilder
.
buildPtrAdd
(
AddrReg
,
SPReg
,
OffsetReg
)
;
MPO
=
MachinePointerInfo
::
getStack
(
MIRBuilder
.
getMF
(
)
,
Offset
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
static
void
mmix_output_octa
(
FILE
*
stream
,
int64_t
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\tOCTA "
)
;
if
(
(
value
<
(
int64_t
)
0
&&
value
>
(
int64_t
)
10000
)
||
(
value
>=
(
int64_t
)
0
&&
value
<=
(
int64_t
)
16384
)
)
fprintf
(
stream
,
"%d"
,
(
int
)
value
)
;
else
if
(
value
>
(
int64_t
)
0
&&
value
<
(
(
int64_t
)
1
<<
31
)
*
2
)
fprintf
(
stream
,
"#%x"
,
(
unsigned
int
)
value
)
;
else
if
(
sizeof
(
HOST_WIDE_INT
)
==
sizeof
(
int64_t
)
)
fprintf
(
stream
,
"#"
HOST_WIDE_INT_PRINT_HEX_PURE
,
(
HOST_WIDE_INT
)
value
)
;
else
fprintf
(
stream
,
"%"
PRIu64
,
value
)
;
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Print a 64-bit value , optionally prefixed by assembly pseudo .


"Asked to disassemble an ARM instruction but Subtarget is in Thumb "

Returns the disassembly of a single instruction .


<s> CCAssignFn * CSKYTargetLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool IsVarArg ) const { if ( IsVarArg || ! Subtarget . useHardFloatABI ( ) ) return CC_CSKY_ABIV2_SOFT ; else return CC_CSKY_ABIV2_FP ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
getARMRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isFPImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getFPImm
(
)
->
getValueAPF
(
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
MCID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> unsigned ARMFastISel :: constrainOperandRegClass ( const MCInstrDesc & II , unsigned Op , unsigned OpNum ) { if ( TargetRegisterInfo :: isVirtualRegister ( Op ) ) { const TargetRegisterClass * RegClass = TII . getRegClass ( II , OpNum , & TRI , * FuncInfo . MF ) ; if ( ! MRI . constrainRegClass ( Op , RegClass ) ) { unsigned NewOp = createResultReg ( RegClass ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , NewOp ) . addReg ( Op ) ) ; return NewOp ; } } return Op ; } </s>

Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc .


<s>
const
ARMGOT
&
ARMGNULDBackend
::
getGOT
(
)
const
{
assert
(
m_pGOT
!=
&&
"GOT section not exist"
)
;
return
*
m_pGOT
;
}
</s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass || RC == ARM :: GPRnopcRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass ARM::GPRnopcRegisterClass ARM::t2LDRi12 0 ARM


<s> static void add_dependee_for_func_arg ( rtx_insn * arg , basic_block bb ) { rtx_insn * insn = BB_END ( bb ) ; while ( insn ) { if ( NONDEBUG_INSN_P ( insn ) && NONJUMP_INSN_P ( insn ) ) { rtx set = single_set ( insn ) ; if ( set ) { avoid_func_arg_motion ( arg , insn ) ; return ; } } if ( insn == BB_HEAD ( bb ) ) return ; insn = PREV_INSN ( insn ) ; } } </s>

Avoid cross block motion of function argument through adding dependency from the first non-jump instruction in bb .


<s> enum rtx_code ix86_reverse_condition ( enum rtx_code code , machine_mode mode ) { return ( mode != CCFPmode && mode != CCFPUmode ? reverse_condition ( code ) : reverse_condition_maybe_unordered ( code ) ) ; } </s>


<s> TargetTransformInfo FPGATargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( FPGATTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> void nds32_expand_epilogue_v3pop ( bool sibcall_p ) { int sp_adjust ; unsigned Rb , Re ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_position = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_v3pop_fpr_callee_saved ( fpr_position ) ; } nds32_emit_stack_v3pop ( Rb , Re , sp_adjust ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - 1 * sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( 0 ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - 1 * sp_adjust ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - cfun -> machine -> callee_saved_area_gpr_padding_bytes - cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( 0 ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_stack_v3pop ( Rb , Re , fpr_space ) ; } else { nds32_emit_stack_v3pop ( Rb , Re , 0 ) ; } } emit_jump_insn ( gen_pop25return ( ) ) ; } </s>


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".tc" ) return ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static bool rx_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_JSR ) return false ; if ( decl == NULL ) return false ; if ( is_fast_interrupt_func ( NULL_TREE ) || is_interrupt_func ( NULL_TREE ) || is_naked_func ( NULL_TREE ) ) return false ; return true ; } </s>

Return nonzero if it is ok to make a tail-call to DECL , a function_decl or NULL if this is an indirect call , using EXP


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) if ( isFrameOperand ( MI , 0 , FrameIndex ) ) return MI -> getOperand ( X86AddrNumOperands ) . getReg ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isLikeA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA15 ( ) && getARMSubtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( ) ) ; } return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool originalTypeIsF128 ( const Type * Ty , const SDNode * CallNode ) { if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == 1 && Ty -> getStructElementType ( 0 ) -> isFP128Ty ( ) ) return true ; const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( CallNode ) ; return ( ES && Ty -> isIntegerTy ( 128 ) && isF128SoftLibCall ( ES -> getSymbol ( ) ) ) ; } </s>

This function returns true if Ty is fp128 , { f128 } or i128 which was originally a fp128 .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( MachineBasicBlock * MBB : RPOT ) Modified |= ReduceMBB ( * MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> BitVector KudeyarRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( Kudeyar :: SP ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( Kudeyar :: FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool mayNeedRelaxation ( const MCInst & , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static machine_mode ix86_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree fntype , int for_return ) { if ( type != NULL_TREE && POINTER_TYPE_P ( type ) ) { * punsignedp = POINTERS_EXTEND_UNSIGNED ; return word_mode ; } return default_promote_function_mode ( type , mode , punsignedp , fntype , for_return ) ; } </s>

Pointer function arguments and return values are promoted to word_mode .


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( createAArch64ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s>
void
rs6000_output_tlsargs
(
rtx
*
operands
)
{
rtx
op
[
3
]
;
op
[
0
]
=
operands
[
0
]
;
op
[
1
]
=
XVECEXP
(
operands
[
2
]
,
0
,
0
)
;
if
(
XINT
(
operands
[
2
]
,
1
)
==
UNSPEC_TLSGD
)
{
op
[
2
]
=
XVECEXP
(
operands
[
2
]
,
0
,
1
)
;
if
(
TARGET_CMODEL
!=
CMODEL_SMALL
)
output_asm_insn
(
"addis %0,%2,%1@got@tlsgd@ha\n\t"
"addi %0,%0,%1@got@tlsgd@l"
,
op
)
;
else
output_asm_insn
(
"addi %0,%2,%1@got@tlsgd"
,
op
)
;
}
else
if
(
XINT
(
operands
[
2
]
,
1
)
==
UNSPEC_TLSLD
)
{
if
(
TARGET_CMODEL
!=
CMODEL_SMALL
)
output_asm_insn
(
"addis %0,%1,%&@got@tlsld@ha\n\t"
"addi %0,%0,%&@got@tlsld@l"
,
op
)
;
else
output_asm_insn
(
"addi %0,%1,%&@got@tlsld"
,
op
)
;
}
else
gcc_unreachable
(
)
;
}
</s>

Output arg setup instructions for a ! TARGET_TLS_MARKERS __tls_get_addr call .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == 0 && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ; Register Reg = I . getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> void nds32_expand_prologue_v3push ( void ) { int fp_adjust ; int sp_adjust ; int fpr_space = 0 ; unsigned Rb , Re ; nds32_compute_stack_frame ( ) ; if ( cfun -> machine -> callee_saved_gpr_regs_size > 0 ) df_set_regs_ever_live ( FP_REGNUM , 1 ) ; if ( frame_pointer_needed ) cfun -> machine -> fp_as_gp_p = false ; if ( cfun -> machine -> naked_p && ! flag_pic ) return ; Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) ) { nds32_emit_stack_v3push ( Rb , Re , sp_adjust ) ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_position = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_push_fpr_callee_saved ( fpr_position ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + sp_adjust ; nds32_emit_adjust_frame ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_adjust ) ; } } else { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_stack_v3push ( Rb , Re , fpr_space ) ; nds32_emit_push_fpr_callee_saved ( 0 ) ; } else { nds32_emit_stack_v3push ( Rb , Re , 0 ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { fp_adjust = fp_adjust + fpr_space ; } nds32_emit_adjust_frame ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_adjust ) ; } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - fpr_space ; } nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - 1 * sp_adjust ) ; } if ( flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) nds32_emit_load_gp ( ) ; emit_insn ( gen_blockage ( ) ) ; } </s>


<s> unsigned OR1KRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? OR1K :: R2 : OR1K :: R1 ; } </s>


<s> const char * MINA32TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case MINA32ISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge && ! getARMSubtarget ( ) . isTargetNaCl ( ) ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> void neon_lane_bounds ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high , const_tree exp ) { bounds_check ( operand , low , high , exp , "lane" ) ; } </s>


<s> static void ix86_emit_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src ) { rtx op , clob ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , mode , dst , src ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } </s>

Emit x86 binary operand CODE in mode MODE , where the first operand matches destination . RTX includes clobber of FLAGS_REG .


<s> static bool have_compare_and_set_mask ( machine_mode mode ) { switch ( mode ) { case E_SFmode : case E_DFmode : return TARGET_P9_MINMAX ; case E_KFmode : case E_TFmode : return TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P ( mode ) ; default : break ; } return false ; } </s>

Helper function to return true if the target has instructions to do a compare and set mask instruction that can be used with XXSEL to implement a conditional move . It is also assumed that such a target also supports the `` C '' minimum and maximum instructions .


<s> static unsigned getBasePointerSaveOffset ( bool isPPC64 , bool isDarwinABI , bool isPIC ) { if ( isDarwinABI ) return isPPC64 ? - 16U : - 8U ; return isPPC64 ? - 16U : isPIC ? - 12U : - 8U ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s>
SUnit
*
SystemZPostRASchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
IsTopNode
=
true
;
if
(
Available
.
empty
(
)
)
return
nullptr
;
if
(
Available
.
size
(
)
==
1
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Only one: "
;
HazardRec
->
dumpSU
(
*
Available
.
begin
(
)
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
return
*
Available
.
begin
(
)
;
}
DEBUG
(
dbgs
(
)
<<
"+++ Available: "
;
Available
.
dump
(
*
HazardRec
)
;
)
;
Candidate
Best
;
for
(
auto
*
SU
:
Available
)
{
Candidate
c
(
SU
,
*
HazardRec
)
;
if
(
Best
.
SU
==
nullptr
||
c
<
Best
)
{
Best
=
c
;
DEBUG
(
dbgs
(
)
<<
"+++ Best sofar: "
;
HazardRec
->
dumpSU
(
Best
.
SU
,
dbgs
(
)
)
;
if
(
Best
.
GroupingCost
!=
0
)
dbgs
(
)
<<
"\tGrouping cost:"
<<
Best
.
GroupingCost
;
if
(
Best
.
ResourcesCost
!=
0
)
dbgs
(
)
<<
" Resource cost:"
<<
Best
.
ResourcesCost
;
dbgs
(
)
<<
" Height:"
<<
Best
.
SU
->
getHeight
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
}
if
(
!
SU
->
isScheduleHigh
&&
Best
.
noCost
(
)
)
break
;
}
assert
(
Best
.
SU
!=
nullptr
)
;
return
Best
.
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

SystemZ
SystemZ
1
"+++ Only one: "
"\n"
"+++ Available: "
"+++ Best sofar: "
0
"\tGrouping cost:"
0
" Resource cost:"
" Height:"
"\n"


<s> TargetPassConfig * MandarinTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MandarinPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
TargetTransformInfo
::
PopcntSupportKind
X86TTIImpl
::
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
ST
->
hasPOPCNT
(
)
TTI
::
PSK_FastHardware
:
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> static bool mips_strict_argument_naming ( cumulative_args_t ca ATTRIBUTE_UNUSED ) { return ! TARGET_OLDABI ; } </s>


<s>
bool
MipsAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
int
Offset
=
0
;
if
(
ExtraCode
)
{
if
(
ExtraCode
[
0
]
==
'D'
)
Offset
=
4
;
else
return
true
;
}
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
Offset
<<
"($"
<<
MipsInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

Mips
Mips
0
0
4
"unexpected inline asm memory operand"
"($"
Mips
")"


Return an array that contains the direct target flag values and their names .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


"mnop-mcount only supported with fentry-call"

"mrecord-mcount only supported with fentry-call"

runOnMachineFunction - Emit the function body .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void PPCPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool pru_regno_ok_for_base_p ( int regno , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) && ! strict_p ) return true ; return ( GP_REG_P ( regno ) || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return true if register REGNO is a valid base register . STRICT_P is true if REG_OK_STRICT is in effect .


<s> bool aarch64_pad_reg_upward ( machine_mode mode , const_tree type , bool first ATTRIBUTE_UNUSED ) { if ( BYTES_BIG_ENDIAN && aarch64_composite_type_p ( type , mode ) ) { HOST_WIDE_INT size = ( type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; if ( size < 2 * UNITS_PER_WORD ) return true ; } return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . It specifies padding for the last ( may also be the only ) element of a block move between registers and memory . If assuming the block is in the memory , padding upward means that the last element is padded after its highest significant byte , while in downward padding , the last element is padded at the its least significant byte side . Small aggregates and small complex types are always padded upwards . We do n't need to worry about homogeneous floating-point or short-vector aggregates ; their move is not affected by the padding direction determined here . Regardless of endianness , each element of such an aggregate is put in the least significant bits of a fp/simd register . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does .


<s> bool use_simple_return_p ( void ) { arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; return offsets -> outgoing_args != 0 ; } </s>

Return TRUE if we should try to use a simple_return insn , i.e . perform shrink-wrapping if possible . This is the case if we need to emit a prologue , which we can test by looking at the offsets .


<s> bool ARMExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const ARMBaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified ; } </s>


<s> void X86PassConfig :: addPreEmitPass2 ( ) { const Triple & TT = TM -> getTargetTriple ( ) ; const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( createX86RetpolineThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( createX86AvoidTrailingCallPass ( ) ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; if ( TT . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> static tree make_resolver_func ( const tree default_decl , const tree ifunc_alias_decl , basic_block * empty_bb ) { char * resolver_name ; tree decl , type , decl_name , t ; if ( TREE_PUBLIC ( default_decl ) == 0 ) { char * ifunc_name = make_unique_name ( default_decl , "ifunc" , true ) ; symtab -> change_decl_assembler_name ( ifunc_alias_decl , get_identifier ( ifunc_name ) ) ; XDELETEVEC ( ifunc_name ) ; } resolver_name = make_unique_name ( default_decl , "resolver" , false ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; decl_name = get_identifier ( resolver_name ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( ifunc_alias_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl ) ) ; cgraph_node :: create_same_body_alias ( ifunc_alias_decl , decl ) ; XDELETEVEC ( resolver_name ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s> bool AArch64InstrInfo :: isSEHInstruction ( const MachineInstr & MI ) { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return false ; case AArch64 :: SEH_StackAlloc : case AArch64 :: SEH_SaveFPLR : case AArch64 :: SEH_SaveFPLR_X : case AArch64 :: SEH_SaveReg : case AArch64 :: SEH_SaveReg_X : case AArch64 :: SEH_SaveRegP : case AArch64 :: SEH_SaveRegP_X : case AArch64 :: SEH_SaveFReg : case AArch64 :: SEH_SaveFReg_X : case AArch64 :: SEH_SaveFRegP : case AArch64 :: SEH_SaveFRegP_X : case AArch64 :: SEH_SetFP : case AArch64 :: SEH_AddFP : case AArch64 :: SEH_Nop : case AArch64 :: SEH_PrologEnd : case AArch64 :: SEH_EpilogStart : case AArch64 :: SEH_EpilogEnd : return true ; } } </s>

Return true if the instructions is a SEH instruciton used for unwinding on Windows .


<s> void MINA32FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> void MipsRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjustMipsStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> hasCalls ( ) ) return ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOREORDER ) ) ; if ( isPIC && Subtarget . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPLOAD ) ) . addReg ( getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOMACRO ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( - StackSize ) ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: FP ) . addReg ( Mips :: SP ) . addReg ( Mips :: ZERO ) ; } if ( ( isPIC ) && ( MFI -> hasCalls ( ) ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPRESTORE ) ) . addImm ( MipsFI -> getGPStackOffset ( ) ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips Mips Mips 0 Mips Mips Mips::NOREORDER Mips::CPLOAD Mips::NOMACRO Mips::ADDiu Mips::SP Mips::SP Mips::SW Mips::RA Mips::SP Mips::SW Mips::FP Mips::SP Mips::ADDu Mips::FP Mips::SP Mips::ZERO Mips::CPRESTORE Mips


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
->
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> bool Mips16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static const uint16_t * lookup ( unsigned opcode , unsigned domain ) { for ( unsigned i = 0 , e = array_lengthof ( ReplaceableInstrs ) ; i != e ; ++ i ) if ( ReplaceableInstrs [ i ] [ domain - 1 ] == opcode ) return ReplaceableInstrs [ i ] ; return 0 ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI . getOpcode ( ) ) ) if ( MI . getOperand ( X86 :: AddrNumOperands ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 0 , FrameIndex ) ) return MI . getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
Opc
=
IsN64
Mips
::
LW_P8
:
Mips
::
LW
;
else
if
(
RC
==
Mips
::
CPU64RegsRegisterClass
)
Opc
=
IsN64
Mips
::
LD_P8
:
Mips
::
LD
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
Opc
=
IsN64
Mips
::
LWC1_P8
:
Mips
::
LWC1
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
Opc
=
Mips
::
LDC1
;
else
if
(
RC
==
Mips
::
FGR64RegisterClass
)
Opc
=
IsN64
Mips
::
LDC164_P8
:
Mips
::
LDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .