<s>
void
DLXDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
if
(
VT
==
MVT
::
i32
)
{
ConstantSDNode
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
DLX
::
R0
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
if
(
ConstNode
->
isAllOnesValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
DLX
::
R1
,
MVT
::
i32
)
;
return
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
}
}
break
;
case
ISD
::
FrameIndex
:
selectFrameIndex
(
Node
)
;
return
;
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s>
const
char
*
aarch64_output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
HOST_WIDE_INT
stack_clash_probe_interval
=
1
<<
PARAM_VALUE
(
PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE
)
;
xops
[
0
]
=
reg1
;
HOST_WIDE_INT
interval
;
if
(
flag_stack_clash_protection
)
interval
=
stack_clash_probe_interval
;
else
interval
=
PROBE_INTERVAL
;
gcc_assert
(
aarch64_uimm12_shift
(
interval
)
)
;
xops
[
1
]
=
GEN_INT
(
interval
)
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
if
(
flag_stack_clash_protection
)
xops
[
1
]
=
GEN_INT
(
STACK_CLASH_CALLER_GUARD
)
;
else
xops
[
1
]
=
CONST0_RTX
(
GET_MODE
(
xops
[
1
]
)
)
;
output_asm_insn
(
"str\txzr, [%0, %1]"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tb.ne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> static tree aarch64_simd_builtin_type ( machine_mode mode , bool unsigned_p , bool poly_p ) { if ( poly_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_poly ) ; else if ( unsigned_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ; else return aarch64_lookup_simd_builtin_type ( mode , qualifier_none ) ; } </s>

Return a type for an operand with specified mode and qualifiers .


This is used as a target hook to modify the DECL_ASSEMBLER_NAME in the language-independent default hook langhooks , c : lhd_set_decl_assembler_name ( ) and in cp/mangle , c : mangle_decl ( ) .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

"Incorrect array index for MVE_VMOV_q_rr"

Perform target-specific instruction verification .


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx , tree ) { cum -> words = 0 ; cum -> prototype_p = fntype && prototype_p ( fntype ) ; cum -> libcall_p = ! fntype ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s>
void
AArch64InstrInfo
::
suppressLdStPair
(
MachineInstr
&
MI
)
const
{
if
(
MI
.
memoperands_empty
(
)
)
return
;
static_assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
,
"Too many target MO flags"
)
;
(
*
MI
.
memoperands_begin
(
)
)
->
setFlags
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
;
}
</s>

Hint that pairing the given load or store is unprofitable .


<s> static int vfp_emit_fstmd ( int base_reg , int count ) { rtx par ; rtx dwarf ; rtx tmp , reg ; int i ; if ( count == 2 && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - 3 ) base_reg -= 2 ; count ++ ; } if ( count > 16 ) { int saved ; saved = vfp_emit_fstmd ( base_reg + 32 , count - 16 ) ; saved += vfp_emit_fstmd ( base_reg , 16 ) ; return saved ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 1 ) = tmp ; for ( i = 1 ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , plus_constant ( Pmode , stack_pointer_rtx , i * 8 ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , i + 1 ) = tmp ; } par = emit_insn ( par ) ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( par ) = 1 ; return count * 8 ; } </s>

Emit RTL to save block of VFP register pairs to the stack . Returns the number of bytes pushed .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { const Function * F = MF . getFunction ( ) ; if ( Subtarget . hasQPX ( ) && Size >= 32 && ( ! IsMemset || Size >= 64 ) && ( ! SrcAlign || SrcAlign >= 32 ) && ( ! DstAlign || DstAlign >= 32 ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return MVT :: v4f64 ; } if ( Subtarget . hasAltivec ( ) && Size >= 16 && ( ( ( ! SrcAlign || SrcAlign >= 16 ) && ( ! DstAlign || DstAlign >= 16 ) ) || ( ( IsMemset && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return MVT :: v4i32 ; } if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> Expected < const MCExpr * > createExprForCAPIVariantKind ( const MCExpr * SubExpr , unsigned VariantKind ) override { switch ( VariantKind ) { case LLVMDisassembler_VariantKind_ARM_HI16 : return ARMMCExpr :: createUpper16 ( SubExpr , Ctx ) ; case LLVMDisassembler_VariantKind_ARM_LO16 : return ARMMCExpr :: createLower16 ( SubExpr , Ctx ) ; default : return MCRelocationInfo :: createExprForCAPIVariantKind ( SubExpr , VariantKind ) ; } } </s>

Create an MCExpr for the target-specific VariantKind .


<s> static int no_previous_def ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return 0 ; return 1 ; } </s>

NO_PREVIOUS_DEF checks in the link list whether the function name is already there or not .


<s> static rtx gen_rx_popm_vector ( unsigned int low , unsigned int high ) { unsigned int i ; unsigned int count = ( high - low ) + 2 ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , ( count - 1 ) * UNITS_PER_WORD ) ) ; for ( i = 0 ; i < count - 1 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == 0 ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; return vector ; } </s>

Generate a PARALLEL which will satisfy the rx_load_multiple_vector predicate .


<s> bool X86TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == 8 ) return false ; if ( Subtarget . hasXOP ( ) && Ty -> getPrimitiveSizeInBits ( ) == 128 && ( Bits == 8 || Bits == 16 || Bits == 32 || Bits == 64 ) ) return false ; if ( Subtarget . hasAVX2 ( ) && ( Bits == 32 || Bits == 64 ) ) return false ; if ( Subtarget . hasBWI ( ) && Bits == 16 ) return false ; return true ; } </s>

This is used to enable splatted operand transforms for vector shifts and vector funnel shifts .


<s> virtual unsigned int execute ( function * ) { timevar_push ( TV_MACH_DEP ) ; rest_of_insert_endbr_and_patchable_area ( need_endbr , patchable_area_size ) ; timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>


<s> HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function ) { HOST_WIDE_INT frame_size , apparent_frame_size ; int args_size , n_global_fp_regs = 0 ; bool save_local_in_regs_p = false ; unsigned int i ; if ( leaf_function && ! cfun -> calls_alloca ) args_size = 0 ; else args_size = crtl -> outgoing_args_size + REG_PARM_STACK_SPACE ( cfun -> decl ) ; if ( TARGET_ARCH64 ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_global_or_fp_reg_p ( i , 0 ) ) n_global_fp_regs += 2 ; } else { for ( i = 0 ; i < 8 ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; } if ( TARGET_FLAT ) for ( i = 16 ; i < 32 ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( size == 0 && n_global_fp_regs == 0 && args_size == 0 && ! save_local_in_regs_p ) frame_size = apparent_frame_size = 0 ; else { apparent_frame_size = ROUND_UP ( size , 8 ) + n_global_fp_regs * 4 ; frame_size = apparent_frame_size + ROUND_UP ( args_size , 8 ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size ; sparc_apparent_frame_size = apparent_frame_size ; sparc_n_global_fp_regs = n_global_fp_regs ; sparc_save_local_in_regs_p = save_local_in_regs_p ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s> FastISel * X86TargetLowering :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmo , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , 8 > & cil ) { return X86 :: createFastISel ( mf , mmo , dw , vm , bm , am , cil ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> const MipsMCSymbolRefExpr * MipsMCSymbolRefExpr :: Create ( VariantKind Kind , const MCSymbol * Symbol , int Offset , MCContext & Ctx ) { return new ( Ctx ) MipsMCSymbolRefExpr ( Kind , Symbol , Offset ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> static void mips_sim_reset ( struct mips_sim * state ) { state -> time = 0 ; state -> insns_left = state -> issue_rate ; memset ( & state -> last_set , 0 , sizeof ( state -> last_set ) ) ; state_reset ( state -> dfa_state ) ; } </s>

Reset STATE to the initial simulation state .


<s> static void rs6000_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.long\t" , file ) ; break ; case 8 : fputs ( DOUBLE_INT_ASM_OP , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; if ( TARGET_ELF ) fputs ( "@dtprel+0x8000" , file ) ; else if ( TARGET_XCOFF && GET_CODE ( x ) == SYMBOL_REF ) { switch ( SYMBOL_REF_TLS_MODEL ( x ) ) { case 0 : break ; case TLS_MODEL_LOCAL_EXEC : fputs ( "@le" , file ) ; break ; case TLS_MODEL_INITIAL_EXEC : fputs ( "@ie" , file ) ; break ; case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : fputs ( "@m" , file ) ; break ; default : gcc_unreachable ( ) ; } } } </s>

This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> int arm_return_in_memory ( tree type ) { HOST_WIDE_INT size ; if ( ! AGGREGATE_TYPE_P ( type ) && ( TREE_CODE ( type ) != VECTOR_TYPE ) && ! ( TARGET_AAPCS_BASED && TREE_CODE ( type ) == COMPLEX_TYPE ) ) return 0 ; size = int_size_in_bytes ( type ) ; if ( arm_abi != ARM_ABI_APCS ) { return ( size < 0 || size > UNITS_PER_WORD ) ; } if ( TREE_CODE ( type ) == VECTOR_TYPE ) return ( size < 0 || size > ( 4 * UNITS_PER_WORD ) ) ; if ( size < 0 || size > UNITS_PER_WORD ) return 1 ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field && TREE_CODE ( field ) != FIELD_DECL ; field = TREE_CHAIN ( field ) ) continue ; if ( field == NULL ) return 0 ; if ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return 1 ; if ( RETURN_IN_MEMORY ( TREE_TYPE ( field ) ) ) return 1 ; for ( field = TREE_CHAIN ( field ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_BIT_FIELD_TYPE ( field ) ) return 1 ; } return 0 ; } if ( TREE_CODE ( type ) == UNION_TYPE ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return 1 ; if ( RETURN_IN_MEMORY ( TREE_TYPE ( field ) ) ) return 1 ; } return 0 ; } return 1 ; } </s>

Decide whether a type should be returned in memory ( true ) or in a register ( false ) . This is called by the macro RETURN_IN_MEMORY .


<s> bool X86TargetLowering :: shouldFormOverflowOp ( unsigned Opcode , EVT VT ) const { if ( VT . isVector ( ) ) return false ; return VT . isSimple ( ) || ! isOperationExpand ( Opcode , VT ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void CJGInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; BuildMI ( MBB , MI , DL , get ( CJG :: PUSH ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { return isShuffleMaskLegal ( Mask , VT ) ; } </s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
auto
PrintImmValue
=
[
&
]
(
const
MCExpr
*
Val
,
const
char
*
VName
)
{
if
(
Val
->
getKind
(
)
==
MCExpr
::
Constant
)
{
if
(
auto
Imm
=
cast
<
MCConstantExpr
>
(
Val
)
->
getValue
(
)
)
OS
<<
VName
<<
Imm
;
}
else
if
(
Val
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
{
if
(
auto
*
SRE
=
dyn_cast
<
MCSymbolRefExpr
>
(
Val
)
)
{
const
MCSymbol
&
Sym
=
SRE
->
getSymbol
(
)
;
if
(
auto
SymName
=
Sym
.
getName
(
)
.
data
(
)
)
OS
<<
VName
<<
SymName
;
}
}
}
;
switch
(
Kind
)
{
case
Token
:
OS
<<
Tok
.
Data
;
break
;
case
Register
:
OS
<<
"Reg:"
<<
X86IntelInstPrinter
::
getRegisterName
(
Reg
.
RegNo
)
;
break
;
case
DXRegister
:
OS
<<
"DXReg"
;
break
;
case
Immediate
:
PrintImmValue
(
Imm
.
Val
,
"Imm:"
)
;
break
;
case
Prefix
:
OS
<<
"Prefix:"
<<
Pref
.
Prefixes
;
break
;
case
Memory
:
OS
<<
"Memory: ModeSize="
<<
Mem
.
ModeSize
;
if
(
Mem
.
Size
)
OS
<<
",Size="
<<
Mem
.
Size
;
if
(
Mem
.
BaseReg
)
OS
<<
",BaseReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
BaseReg
)
;
if
(
Mem
.
IndexReg
)
OS
<<
",IndexReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
IndexReg
)
;
if
(
Mem
.
Scale
)
OS
<<
",Scale="
<<
Mem
.
Scale
;
if
(
Mem
.
Disp
)
PrintImmValue
(
Mem
.
Disp
,
",Disp="
)
;
if
(
Mem
.
SegReg
)
OS
<<
",SegReg="
<<
X86IntelInstPrinter
::
getRegisterName
(
Mem
.
SegReg
)
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

X86
"Reg:"
X86
"DXReg"
"Imm:"
"Prefix:"
"Memory: ModeSize="
",Size="
",BaseReg="
X86
",IndexReg="
X86
",Scale="
",Disp="
",SegReg="
X86


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; } </s>

Return true if the function can safely be outlined from .


"getMemOperandWithOffset only supports base "

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TM . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s> bool ARM64AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> std :: unique_ptr < MCObjectWriter > SHUXIAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createSHUXIELFObjectWriter ( OS , false , true , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 load / store optimization pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int rs6000_use_sched_lookahead_guard ( rtx_insn * insn , int ready_index ) { if ( ready_index == 0 ) return 0 ; if ( rs6000_tune != PROCESSOR_CELL ) return 0 ; gcc_assert ( insn != NULL_RTX && INSN_P ( insn ) ) ; if ( ! reload_completed || is_nonpipeline_insn ( insn ) || is_microcoded_insn ( insn ) ) return 1 ; return 0 ; } </s>

We are choosing insn from the ready queue . Return zero if INSN can be chosen .


"This eliminateCallFramePseudoInstr does not suppor Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
begin
(
)
,
RPIE
=
RegPairs
.
end
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
bool
BumpSP
=
RPII
==
std
::
prev
(
RegPairs
.
end
(
)
)
;
if
(
RPI
.
IsGPR
)
{
if
(
BumpSP
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXpost
:
AArch64
::
LDRXpost
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
}
else
{
if
(
BumpSP
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDpost
:
AArch64
::
LDRDpost
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
}
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
const
int
Offset
=
RPI
.
Offset
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
BumpSP
)
MIB
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
;
if
(
RPI
.
isPaired
(
)
)
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
else
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
BumpSP
Offset
*
8
:
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool aarch64_could_trap_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY | FLAG_WRITE_MEMORY ) ) return true ; return false ; } </s>

Return true if calls to the function could raise a signal .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>


<s> ARMProcFamilyEnum getProcFamily ( ) const { return ARMProcFamily ; } </s>


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt , PPCSubTarget -> hasSPE ( ) ? PPC :: EVLDD : PPC :: LFD ) ) return false ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> unsigned ARMFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ARMMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return ARMMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return ARMMaterializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


"\nRelevant insns with their flag settings\n\n"


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Hazard Schedule"
;
}
</s>


<s> static void arm_set_current_function ( tree fndecl ) { if ( ! fndecl || fndecl == arm_previous_fndecl ) return ; tree old_tree = ( arm_previous_fndecl ? DECL_FUNCTION_SPECIFIC_TARGET ( arm_previous_fndecl ) : NULL_TREE ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! new_tree && old_tree ) new_tree = target_option_default_node ; if ( old_tree == new_tree ) return ; arm_previous_fndecl = fndecl ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; save_restore_target_globals ( new_tree ) ; arm_override_options_after_change_1 ( & global_options , & global_options_set ) ; } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> HOST_WIDE_INT pa_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; if ( ( from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM ) && to == STACK_POINTER_REGNUM ) offset = - pa_compute_frame_size ( get_frame_size ( ) , 0 ) ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = 0 ; else gcc_unreachable ( ) ; return offset ; } </s>

Define the offset between two registers , FROM to be eliminated and its replacement TO , at the start of a routine .


<s> static bool ix86_can_inline_p ( tree caller , tree callee ) { bool ret = false ; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) ret = true ; else if ( ! caller_tree ) ret = false ; else { struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; if ( ( caller_opts -> x_ix86_isa_flags & callee_opts -> x_ix86_isa_flags ) != callee_opts -> x_ix86_isa_flags ) ret = false ; else if ( caller_opts -> x_target_flags != callee_opts -> x_target_flags ) ret = false ; else if ( caller_opts -> arch != callee_opts -> arch ) ret = false ; else if ( caller_opts -> tune != callee_opts -> tune ) ret = false ; else if ( caller_opts -> x_ix86_fpmath != callee_opts -> x_ix86_fpmath ) ret = false ; else if ( caller_opts -> branch_cost != callee_opts -> branch_cost ) ret = false ; else ret = true ; } return ret ; } </s>

Hook to determine if one function can safely inline another .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


runOnMachineFunction - Emit the function body .


<s> void PPCTTI :: getUnrollingPreferences ( const Function * F , Loop * L , UnrollingPreferences & UP ) const { if ( TM -> getSubtarget < PPCSubtarget > ( F ) . getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; } TargetTransformInfo :: getUnrollingPreferences ( F , L , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> X86GenInstrInfo :: MachineOutlinerInstrType X86InstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MIT , unsigned Flags ) const { MachineInstr & MI = * MIT ; if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


"eliminateCallFramePseudoInstr not implemented yet"


<s> const uint16_t * XNCMRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { XNCM :: LR , 0 } ; return CalleeSavedRegs ; } </s>


<s>
unsigned
LanaiInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
Instruction
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
Instruction
!=
MBB
.
begin
(
)
)
{
Instruction
;
if
(
Instruction
->
isDebugInstr
(
)
)
continue
;
if
(
Instruction
->
getOpcode
(
)
!=
Lanai
::
BT
&&
Instruction
->
getOpcode
(
)
!=
Lanai
::
BRCC
)
{
break
;
}
Instruction
->
eraseFromParent
(
)
;
Instruction
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

Lanai
Lanai
"code size not handled"
0
Lanai::BT
Lanai::BRCC


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> void rbt_inorder_callback ( struct rbt_strings * t , struct rbt_string_node * subtree , void ( * fn ) ( char * ) ) { if ( subtree != t -> rbt_nil ) { rbt_inorder_callback ( t , subtree -> left , fn ) ; ( * fn ) ( subtree -> str ) ; rbt_inorder_callback ( t , subtree -> right , fn ) ; } } </s>

Inorder call-back for iteration over the tree .


<s> static bool moxie_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( arg . aggregate_type_p ( ) ) return true ; unsigned HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return size > 4 * 6 ; } </s>

Return non-zero if the function argument described by TYPE is to be passed by reference .


<s> void Cpu0AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
bool
VEAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
VEOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

VE
VE
VEOperand::CreateToken
"unexpected token"
"unexpected token"
"unexpected token"


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
return
Error
(
NameLoc
,
"unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

Mips
Mips
"ParseInstruction\n"
0
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> bool AArch64IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return runTIs ( MMI , MF , TIs ) ; } </s>


<s> static void ia64_file_start ( void ) { default_file_start ( ) ; emit_safe_across_calls ( ) ; } </s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createARM64ELFObjectWriter ( OS , OSABI , IsLittleEndian ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool loongarch_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { return true ; } </s>


<s>
static
void
rs6000_debug_target_options
(
tree
args
,
const
char
*
prefix
)
{
if
(
args
==
NULL_TREE
)
fprintf
(
stderr
,
"%s<NULL>"
,
prefix
)
;
else
if
(
TREE_CODE
(
args
)
==
STRING_CST
)
{
char
*
p
=
ASTRDUP
(
TREE_STRING_POINTER
(
args
)
)
;
char
*
q
;
while
(
(
q
=
strtok
(
p
,
","
)
)
!=
)
{
p
=
;
fprintf
(
stderr
,
"%s\"%s\""
,
prefix
,
q
)
;
prefix
=
", "
;
}
}
else
if
(
TREE_CODE
(
args
)
==
TREE_LIST
)
{
do
{
tree
value
=
TREE_VALUE
(
args
)
;
if
(
value
)
{
rs6000_debug_target_options
(
value
,
prefix
)
;
prefix
=
", "
;
}
args
=
TREE_CHAIN
(
args
)
;
}
while
(
args
!=
NULL_TREE
)
;
}
else
gcc_unreachable
(
)
;
return
;
}
</s>

Print out the target options as a list for -mdebug=target .


<s>
bool
ARMCallLowering
::
lowerFormalArguments
(
MachineIRBuilder
&
MIRBuilder
,
const
Function
&
F
,
ArrayRef
<
ArrayRef
<
Register
>>
VRegs
)
const
{
auto
&
TLI
=
*
getTLI
<
ARMTargetLowering
>
(
)
;
auto
Subtarget
=
TLI
.
getSubtarget
(
)
;
if
(
Subtarget
->
isThumb1Only
(
)
)
return
false
;
if
(
F
.
arg_empty
(
)
)
return
true
;
if
(
F
.
isVarArg
(
)
)
return
false
;
auto
&
MF
=
MIRBuilder
.
getMF
(
)
;
auto
&
MBB
=
MIRBuilder
.
getMBB
(
)
;
auto
DL
=
MF
.
getDataLayout
(
)
;
for
(
auto
&
Arg
:
F
.
args
(
)
)
{
if
(
!
isSupportedType
(
DL
,
TLI
,
Arg
.
getType
(
)
)
)
return
false
;
if
(
Arg
.
hasByValOrInAllocaAttr
(
)
)
return
false
;
}
CCAssignFn
*
AssignFn
=
TLI
.
CCAssignFnForCall
(
F
.
getCallingConv
(
)
,
F
.
isVarArg
(
)
)
;
FormalArgHandler
ArgHandler
(
MIRBuilder
,
MIRBuilder
.
getMF
(
)
.
getRegInfo
(
)
,
AssignFn
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgInfos
;
unsigned
Idx
=
0
;
for
(
auto
&
Arg
:
F
.
args
(
)
)
{
ArgInfo
OrigArgInfo
(
VRegs
[
Idx
]
,
Arg
.
getType
(
)
)
;
setArgFlags
(
OrigArgInfo
,
Idx
+
AttributeList
::
FirstArgIndex
,
DL
,
F
)
;
splitToValueTypes
(
OrigArgInfo
,
SplitArgInfos
,
MF
,
[
&
]
(
Register
Reg
)
{
llvm_unreachable
(
"Args should already be split"
)
;
}
)
;
Idx
++
;
}
if
(
!
MBB
.
empty
(
)
)
MIRBuilder
.
setInstr
(
*
MBB
.
begin
(
)
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgInfos
,
ArgHandler
)
)
return
false
;
MIRBuilder
.
setMBB
(
MBB
)
;
return
true
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .

ARM
ARM
ARM
8
0
"Args should already be split"


<s> virtual const PPCSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool aarch_rev16_p ( rtx x ) { rtx left_sub_rtx , right_sub_rtx ; bool is_rev = false ; if ( GET_CODE ( x ) != IOR ) return false ; left_sub_rtx = XEXP ( x , 0 ) ; right_sub_rtx = XEXP ( x , 1 ) ; is_rev = aarch_rev16_p_1 ( left_sub_rtx , right_sub_rtx , GET_MODE ( x ) ) ; if ( ! is_rev ) is_rev = aarch_rev16_p_1 ( right_sub_rtx , left_sub_rtx , GET_MODE ( x ) ) ; return is_rev ; } </s>

Recognise a sequence of bitwise operations corresponding to a rev16 operation . These will be of the form : ( ( x > > 8 ) & 0x00ff00ff ) | ( ( x < < 8 ) & 0xff00ff00 ) for SImode and with similar but wider bitmasks for DImode . The two sub-expressions of the IOR can appear on either side so check both permutations with the help of aarch_rev16_p_1 above .


<s> SDValue AArch64TargetLowering :: getGOT ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { DEBUG ( dbgs ( ) << "AArch64TargetLowering::getGOT\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty , DAG , AArch64II :: MO_GOT | Flags ) ; return DAG . getNode ( AArch64ISD :: LOADgot , DL , Ty , GotAddr ) ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> static const char * rs6000_xcoff_strip_name_encoding ( const char * name ) { size_t len ; if ( * name == '*' ) name ++ ; len = strlen ( name ) ; if ( name [ len - 1 ] == ']' ) return ggc_alloc_string ( name , len - 4 ) ; else return name ; } </s>

Remove any trailing [ DS ] or the like from the symbol name .


<s> virtual const TOYRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
ATOMIC_LOAD_ADD
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMADD64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_AND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_NAND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMNAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_OR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_SUB
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSUB64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_XOR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMXOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSWAP64_DAG
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMCMPXCHG64_DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> int adjacent_mem_locations ( rtx a , rtx b ) { if ( volatile_refs_p ( a ) || volatile_refs_p ( b ) ) return 0 ; if ( ( REG_P ( XEXP ( a , 0 ) ) || ( GET_CODE ( XEXP ( a , 0 ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( a , 0 ) , 1 ) ) ) ) && ( REG_P ( XEXP ( b , 0 ) ) || ( GET_CODE ( XEXP ( b , 0 ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( b , 0 ) , 1 ) ) ) ) ) { HOST_WIDE_INT val0 = 0 , val1 = 0 ; rtx reg0 , reg1 ; int val_diff ; if ( GET_CODE ( XEXP ( a , 0 ) ) == PLUS ) { reg0 = XEXP ( XEXP ( a , 0 ) , 0 ) ; val0 = INTVAL ( XEXP ( XEXP ( a , 0 ) , 1 ) ) ; } else reg0 = XEXP ( a , 0 ) ; if ( GET_CODE ( XEXP ( b , 0 ) ) == PLUS ) { reg1 = XEXP ( XEXP ( b , 0 ) , 0 ) ; val1 = INTVAL ( XEXP ( XEXP ( b , 0 ) , 1 ) ) ; } else reg1 = XEXP ( b , 0 ) ; if ( ! const_ok_for_op ( val0 , PLUS ) || ! const_ok_for_op ( val1 , PLUS ) ) return 0 ; if ( arm_eliminable_register ( reg0 ) ) return 0 ; val_diff = val1 - val0 ; if ( arm_ld_sched ) { return ( optimize_size && ( REGNO ( reg0 ) == REGNO ( reg1 ) ) && ( val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4 ) && ( val_diff == 4 || val_diff == - 4 ) ) ; } return ( ( REGNO ( reg0 ) == REGNO ( reg1 ) ) && ( val_diff == 4 || val_diff == - 4 ) ) ; } return 0 ; } </s>

If the target storage locations of arguments MEM1 and MEM2 are adjacent , then return the argument that has the lower address . Otherwise , return NULL_RTX .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; bool HasDwarfEHHandlers = ! MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return ; Amount -= InternalAmt ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( MF . getFunction ( ) -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static rtx gen_rx_store_vector ( unsigned int low , unsigned int high ) { unsigned int i ; unsigned int count = ( high - low ) + 2 ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( ( count - 1 ) * UNITS_PER_WORD ) ) ) ; for ( i = 0 ; i < count - 1 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( gen_rtx_MEM ( SImode , gen_rtx_MINUS ( SImode , stack_pointer_rtx , GEN_INT ( ( i + 1 ) * UNITS_PER_WORD ) ) ) , gen_rtx_REG ( SImode , high - i ) ) ; return vector ; } </s>

Generate a PARALLEL that will pass the rx_store_multiple_vector predicate .


<s> bool VEInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { VECC :: CondCode CC = static_cast < VECC :: CondCode > ( Cond [ 0 ] . getImm ( ) ) ; Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( CC ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MVE lane interleaving"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; if ( ! ISA_HAS_LWL_LWR ) bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; else { if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; } mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , 0 , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , RETURN_BEGIN ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> SDValue F2003fTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_F2003f ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool aarch64_rtx_arith_op_extract_p ( rtx x ) { if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) return REG_P ( XEXP ( x , 0 ) ) ; return false ; } </s>

Return true if X is a zero or sign extract usable in an ADD or SUB ( extended register ) instruction .


<s> static HOST_WIDE_INT aarch64_simd_vector_alignment ( const_tree type ) { if ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_VECTOR_BOOL ? 16 : 128 ; return wi :: umin ( wi :: to_wide ( TYPE_SIZE ( type ) ) , 128 ) . to_uhwi ( ) ; } </s>

Implement target hook TARGET_VECTOR_ALIGNMENT . The AAPCS64 sets the maximum alignment of a vector to 128 bits .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addi %0,%0,%1"
,
xops
)
;
xops
[
1
]
=
gen_rtx_REG
(
Pmode
,
0
)
;
output_asm_insn
(
"stw %1,0(%0)"
,
xops
)
;
xops
[
1
]
=
reg2
;
if
(
TARGET_64BIT
)
output_asm_insn
(
"cmpd 0,%0,%1"
,
xops
)
;
else
output_asm_insn
(
"cmpw 0,%0,%1"
,
xops
)
;
fputs
(
"\tbne 0,"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> bool direct_move_p ( rtx op0 , rtx op1 ) { int regno0 , regno1 ; if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE && ! TARGET_MFPGPR ) return false ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; if ( regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 ) ) return true ; else if ( TARGET_DIRECT_MOVE && VSX_REGNO_P ( regno0 ) ) return true ; } return false ; } </s>

Return true if this is a move direct operation between GPR registers and floating point/VSX registers .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: SUB64ri8 : X86 :: SUB32ri8 ) : ( Is64Bit ? X86 :: SUB64ri32 : X86 :: SUB32ri ) ) : ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: ADD64ri8 : X86 :: ADD32ri8 ) : ( Is64Bit ? X86 :: ADD64ri32 : X86 :: ADD32ri ) ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> std :: pair < unsigned , const TargetRegisterClass * > OR1KTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & OR1K :: GPRRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
static
bool
darwin_local_data_pic
(
rtx
disp
)
{
if
(
GET_CODE
(
disp
)
==
MINUS
)
{
if
(
GET_CODE
(
XEXP
(
disp
,
0
)
)
==
LABEL_REF
||
GET_CODE
(
XEXP
(
disp
,
0
)
)
==
SYMBOL_REF
)
if
(
GET_CODE
(
XEXP
(
disp
,
1
)
)
==
SYMBOL_REF
)
{
const
char
*
sym_name
=
XSTR
(
XEXP
(
disp
,
1
)
,
0
)
;
if
(
!
strcmp
(
sym_name
,
"<pic base>"
)
)
return
true
;
}
}
return
false
;
}
</s>

Allow { LABEL | SYMBOL } _REF - SYMBOL_REF-FOR-PICBASE for Mach-O as this is used for to form addresses to local data when -fPIC is in use .


<s> void ix86_expand_unary_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { bool matching_memory = false ; rtx src , dst , op , clob ; dst = operands [ 0 ] ; src = operands [ 1 ] ; if ( MEM_P ( dst ) ) { if ( rtx_equal_p ( dst , src ) ) matching_memory = true ; else dst = gen_reg_rtx ( mode ) ; } if ( MEM_P ( src ) && ! matching_memory ) src = force_reg ( mode , src ) ; op = gen_rtx_SET ( dst , gen_rtx_fmt_e ( code , mode , src ) ) ; if ( code == NOT ) emit_insn ( op ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a unary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 2 separate memory references ( one output , one input ) in a single insn .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other , MVT :: Glue ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( 1 ) ; SDValue Glue = End . getValue ( 2 ) ; SDValue Ops [ ] = { End , DAG . getConstant ( 0 , PtrVT ) , DAG . getConstant ( SystemZ :: CCMASK_SRST , MVT :: i32 ) , DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , MVT :: i32 ) , Glue } ; VTs = DAG . getVTList ( PtrVT , MVT :: Glue ) ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , VTs , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s>
const
char
*
pa_output_parallel_movb
(
rtx
*
operands
,
rtx_insn
*
insn
)
{
int
length
=
get_attr_length
(
insn
)
;
if
(
length
==
4
)
return
"mov%I1b,tr %1,%0,%2"
;
if
(
length
==
8
)
{
if
(
dbr_sequence_length
(
)
==
0
)
{
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
return
"b %2\n\tldi %1,%0"
;
else
return
"b %2\n\tcopy %1,%0"
;
}
else
{
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
return
"ldi %1,%0\n\tb %2"
;
else
return
"copy %1,%0\n\tb %2"
;
}
}
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
output_asm_insn
(
"ldi %1,%0"
,
operands
)
;
else
output_asm_insn
(
"copy %1,%0"
,
operands
)
;
return
pa_output_lbranch
(
operands
[
2
]
,
insn
,
1
)
;
}
</s>

Output an unconditional move and branch insn .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { DebugLoc DL = Orig -> getDebugLoc ( ) ; bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case X86 :: MOV8r0 : case X86 :: MOV16r0 : case X86 :: MOV32r0 : case X86 :: MOV64r0 : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOV8r0 : Opc = X86 :: MOV8ri ; break ; case X86 :: MOV16r0 : Opc = X86 :: MOV16ri ; break ; case X86 :: MOV32r0 : Opc = X86 :: MOV32ri ; break ; case X86 :: MOV64r0 : Opc = X86 :: MOV64ri64i32 ; break ; } Clone = false ; } break ; } } if ( Clone ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } else { BuildMI ( MBB , I , DL , get ( Opc ) ) . addOperand ( Orig -> getOperand ( 0 ) ) . addImm ( 0 ) ; } MachineInstr * NewMI = prior ( I ) ; NewMI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_condbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_blx"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static void release_scratch_register_on_entry ( struct scratch_reg * sr ) { if ( sr -> saved ) { rtx addr = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; rtx insn = emit_set_insn ( sr -> reg , gen_frame_mem ( SImode , addr ) ) ; rtx x = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ; } } </s>

Release a scratch register obtained from the preceding function . If RELEASE_VIA_POP is true , we just pop the register off the stack to release it . This is what non-Linux systems use with -fstack-check . Otherwise we use OFFSET to locate the saved register and the allocated stack space becomes part of the local frame and is deallocated by the epilogue .


<s> int gen_v9_scc ( enum rtx_code compare_code , register rtx * operands ) { rtx temp , op0 , op1 ; if ( ! TARGET_ARCH64 && ( GET_MODE ( sparc_compare_op0 ) == DImode || GET_MODE ( operands [ 0 ] ) == DImode ) ) return 0 ; op0 = sparc_compare_op0 ; op1 = sparc_compare_op1 ; if ( TARGET_ARCH64 && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT && op1 == const0_rtx && v9_regcmp_p ( compare_code ) ) { if ( compare_code == NE && GET_MODE ( operands [ 0 ] ) == DImode && rtx_equal_p ( op0 , operands [ 0 ] ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_fmt_ee ( compare_code , DImode , op0 , const0_rtx ) , const1_rtx , operands [ 0 ] ) ) ) ; return 1 ; } if ( reg_overlap_mentioned_p ( operands [ 0 ] , op0 ) ) { op0 = gen_reg_rtx ( GET_MODE ( sparc_compare_op0 ) ) ; emit_move_insn ( op0 , sparc_compare_op0 ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , 0 ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , operands [ 0 ] ) ) ) ; return 1 ; } else { operands [ 1 ] = gen_compare_reg ( compare_code , op0 , op1 ) ; switch ( GET_MODE ( operands [ 1 ] ) ) { case CCmode : case CCXmode : case CCFPEmode : case CCFPmode : break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , gen_rtx_fmt_ee ( compare_code , GET_MODE ( operands [ 1 ] ) , operands [ 1 ] , const0_rtx ) , const1_rtx , operands [ 0 ] ) ) ) ; return 1 ; } } </s>

This function is used for v9 only . CODE is the code for an Scc 's comparison . OPERANDS [ 0 ] is the target of the Scc insn . OPERANDS [ 1 ] is the value we compare against const0_rtx ( which has n't been generated yet ) . This function is needed to turn ( set ( reg : SI 110 ) ( gt ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) into ( set ( reg : SI 110 ) ( gt : DI ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) IE : The instruction recognizer needs to see the mode of the comparison to find the right instruction . We could use `` gt : DI '' right in the define_expand , but leaving it out allows us to handle DI , SI , etc . We refer to the global sparc compare operands sparc_compare_op0 and sparc_compare_op1 .


<s>
void
loongarch_output_external
(
FILE
*
file
,
tree
decl
,
const
char
*
name
)
{
default_elf_asm_output_external
(
file
,
decl
,
name
)
;
if
(
TREE_SYMBOL_REFERENCED
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
{
if
(
loongarch_in_small_data_p
(
decl
)
)
{
fputs
(
"\t.extern\t"
,
file
)
;
assemble_name
(
file
,
name
)
;
fprintf
(
file
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
int_size_in_bytes
(
TREE_TYPE
(
decl
)
)
)
;
}
}
}
</s>


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> void LanaiInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annotation , const MCSubtargetInfo & STI ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> MipsSubtarget & MipsSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = selectMipsCPU ( TargetTriple , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( InMips16Mode && ! TM . Options . UseSoftFloat ) InMips16HardFloat = true ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"%qE attribute only applies to functions"

"%qE attribute argument not a string constant"

Handle an `` sp_switch '' attribute ; arguments as in struct attribute_spec.handler .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
.
getName
(
)
<<
" ------------- \n"
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
MF
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; addPass ( createSandBoxingPreRegallocPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> StackOffset MipsSEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; if ( MFI . isFixedObjectIndex ( FI ) ) FrameReg = hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ; else FrameReg = hasBP ( MF ) ? ABI . GetBasePtr ( ) : ABI . GetStackPtr ( ) ; return StackOffset :: getFixed ( MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> void ARMInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool AArch64AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OS . write ( "\x1f\x20\x03\xd5" , 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
void
ATTRIBUTE_UNUSED
ix86_debug_options
(
void
)
{
char
*
opts
=
ix86_target_string
(
ix86_isa_flags
,
ix86_isa_flags2
,
target_flags
,
ix86_target_flags
,
ix86_arch_string
,
ix86_tune_string
,
ix86_fpmath
,
true
,
true
)
;
if
(
opts
)
{
fprintf
(
stderr
,
"%s\n\n"
,
opts
)
;
free
(
opts
)
;
}
else
fputs
(
"<no options>\n\n"
,
stderr
)
;
return
;
}
</s>

Function that is callable from the debugger to print the current options .


<s> void sparc_expand_epilogue ( void ) { if ( num_gfregs ) emit_save_or_restore_regs ( SORR_RESTORE ) ; if ( actual_fsize == 0 ) ; else if ( sparc_leaf_function_p ) { if ( actual_fsize <= 4096 ) emit_insn ( gen_stack_pointer_dec ( GEN_INT ( - actual_fsize ) ) ) ; else if ( actual_fsize <= 8192 ) { emit_insn ( gen_stack_pointer_dec ( GEN_INT ( - 4096 ) ) ) ; emit_insn ( gen_stack_pointer_dec ( GEN_INT ( 4096 - actual_fsize ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( - actual_fsize ) ) ; emit_insn ( gen_stack_pointer_dec ( reg ) ) ; } } } </s>

Expand the function epilogue , either normal or part of a sibcall . We emit all the instructions except the return or the call .


<s>
static
void
AnalyzeArguments
(
CCState
&
State
,
SmallVectorImpl
<
CCValAssign
>
&
ArgLocs
,
const
SmallVectorImpl
<
ArgT
>
&
Args
)
{
static
const
MCPhysReg
RegList
[
]
=
{
SHUXI
::
R24
,
SHUXI
::
R25
,
SHUXI
::
R26
,
SHUXI
::
R27
,
SHUXI
::
R28
,
SHUXI
::
R29
,
SHUXI
::
R30
,
SHUXI
::
R31
}
;
static
const
MCPhysReg
RegList
[
]
=
{
SHUXI
::
R4
,
SHUXI
::
R5
,
SHUXI
::
R6
,
SHUXI
::
R7
,
SHUXI
::
R8
}
;
static
const
unsigned
NbRegs
=
array_lengthof
(
RegList
)
;
if
(
State
.
isVarArg
(
)
)
{
llvm_unreachable
(
"Cannot support var args"
)
;
}
SmallVector
<
unsigned
,
4
>
ArgsParts
;
ParseFunctionArgs
(
Args
,
ArgsParts
)
;
unsigned
RegsLeft
=
NbRegs
;
bool
UseStack
=
false
;
unsigned
ValNo
=
0
;
for
(
unsigned
i
=
0
,
e
=
ArgsParts
.
size
(
)
;
i
!=
e
;
i
++
)
{
MVT
ArgVT
=
Args
[
ValNo
]
.
VT
;
ISD
::
ArgFlagsTy
ArgFlags
=
Args
[
ValNo
]
.
Flags
;
MVT
LocVT
=
ArgVT
;
CCValAssign
::
LocInfo
LocInfo
=
CCValAssign
::
Full
;
if
(
ArgFlags
.
isByVal
(
)
)
{
State
.
HandleByVal
(
ValNo
++
,
ArgVT
,
LocVT
,
LocInfo
,
4
,
4
,
ArgFlags
)
;
continue
;
}
unsigned
Parts
=
ArgsParts
[
i
]
;
if
(
!
UseStack
&&
Parts
<=
RegsLeft
)
{
unsigned
FirstVal
=
ValNo
;
for
(
unsigned
j
=
0
;
j
<
Parts
;
j
++
)
{
unsigned
Reg
=
State
.
AllocateReg
(
RegList
)
;
State
.
addLoc
(
CCValAssign
::
getReg
(
ValNo
++
,
ArgVT
,
Reg
,
LocVT
,
LocInfo
)
)
;
RegsLeft
;
}
SmallVectorImpl
<
CCValAssign
>
::
iterator
B
=
ArgLocs
.
begin
(
)
+
FirstVal
;
std
::
reverse
(
B
,
B
+
Parts
)
;
}
else
{
UseStack
=
true
;
for
(
unsigned
j
=
0
;
j
<
Parts
;
j
++
)
CC_SHUXI
(
ValNo
++
,
ArgVT
,
LocVT
,
LocInfo
,
ArgFlags
,
State
)
;
}
}
}
</s>

The function will invoke AnalyzeCallOperands .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin_Or_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static void * mingw32_gt_pch_get_address ( size_t size , int fd ATTRIBUTE_UNUSED ) { void * res ; size = ( size + va_granularity - 1 ) & ~ ( va_granularity - 1 ) ; if ( size > pch_VA_max_size ) return NULL ; res = VirtualAlloc ( NULL , pch_VA_max_size , MEM_RESERVE | MEM_TOP_DOWN , PAGE_NOACCESS ) ; if ( ! res ) w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "VirtualAlloc" ) ; else VirtualFree ( res , 0 , MEM_RELEASE ) ; return res ; } </s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s> static void vr4130_avoid_branch_rt_conflict ( rtx_insn * insn ) { rtx_insn * first , * second ; first = SEQ_BEGIN ( insn ) ; second = SEQ_END ( insn ) ; if ( JUMP_P ( first ) && NONJUMP_INSN_P ( second ) && GET_CODE ( PATTERN ( first ) ) == SET && GET_CODE ( SET_DEST ( PATTERN ( first ) ) ) == PC && GET_CODE ( SET_SRC ( PATTERN ( first ) ) ) == IF_THEN_ELSE ) { rtx cond = XEXP ( SET_SRC ( PATTERN ( first ) ) , 0 ) ; if ( ( GET_CODE ( cond ) == EQ || GET_CODE ( cond ) == NE ) && REG_P ( XEXP ( cond , 0 ) ) && REG_P ( XEXP ( cond , 1 ) ) && reg_referenced_p ( XEXP ( cond , 1 ) , PATTERN ( second ) ) && ! reg_referenced_p ( XEXP ( cond , 0 ) , PATTERN ( second ) ) ) { rtx tmp = XEXP ( cond , 0 ) ; XEXP ( cond , 0 ) = XEXP ( cond , 1 ) ; XEXP ( cond , 1 ) = tmp ; } } } </s>

The VR4130 pipeline issues aligned pairs of instructions together , but it stalls the second instruction if it depends on the first . In order to cut down the amount of logic required , this dependence check is not based on a full instruction decode . Instead , any non-SPECIAL instruction is assumed to modify the register specified by bits 20-16 ( which is usually the `` rt '' field ) . In beq , beql , bne and bnel instructions , the rt field is actually an input , so we can end up with a false dependence between the branch and its delay slot . If this situation occurs in instruction INSN , try to avoid it by swapping rs and rt .


"stack re-alignment, but LLVM couldn't handle it "

"(probably because it has a dynamic alloca)."

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STR : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: t2STRi12 : case ARM :: tSpill : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: FSTD : case ARM :: FSTS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 16 ; return 0 ; } if ( ST -> isThumb1Only ( ) ) return 8 ; return 13 ; } </s>


<s> bool PPCFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Load : return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , ISD :: ADD ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , ISD :: OR ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , ISD :: SUB ) ; case Instruction :: Call : if ( dyn_cast < IntrinsicInst > ( I ) ) return false ; return SelectCall ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I ) ; default : break ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> MCSymbol * ARM64MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; this -> TM = & static_cast < const MipsTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s>
const
char
*
mt_asm_output_opcode
(
FILE
*
f
ATTRIBUTE_UNUSED
,
const
char
*
ptr
)
{
if
(
mt_nops_required
)
fprintf
(
f
,
";# need %d nops because of %s\n\t"
,
mt_nops_required
,
mt_nop_reasons
)
;
while
(
mt_nops_required
)
{
fprintf
(
f
,
"nop\n\t"
)
;
mt_nops_required
;
}
return
ptr
;
}
</s>

mt
";# need %d nops because of %s\n\t"
"nop\n\t"


<s> virtual unsigned int execute ( function * ) { execute_tag_collision_avoidance ( ) ; return 0 ; } </s>


<s> bool isCollapsed ( ) const { return Instrs . empty ( ) ; } </s>

A collapsed DomainValue has no instructions to twiddle - it simply keeps track of the domains where the registers are already available .


"%qE redeclared with conflicting %qs attributes"


<s> static void arm_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == 4 ) ; fputs ( "\t.word\t" , file ) ; output_addr_const ( file , x ) ; fputs ( "(tlsldo)" , file ) ; } </s>

ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL .


<s> gimple * fold ( gimple_folder & f ) const override { if ( tree amount = uniform_integer_cst_p ( gimple_call_arg ( f . call , 2 ) ) ) { if ( wi :: to_widest ( amount ) >= 0 ) { function_instance instance ( "svlsl" , functions :: svlsl , shapes :: binary_uint_opt_n , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , 2 , amount ) ; return call ; } int element_bits = f . type_suffix ( 0 ) . element_bits ; if ( wi :: to_widest ( amount ) >= - element_bits ) { amount = wide_int_to_tree ( TREE_TYPE ( amount ) , - wi :: to_wide ( amount ) ) ; function_instance instance ( "svrshr" , functions :: svrshr , shapes :: shift_right_imm , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , 2 , amount ) ; return call ; } } return NULL ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


<s>
void
DarwinARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> int find_post_update_rtx ( rtx_insn * insn ) { rtx mem_rtx ; int i , len ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : len = parallel_elements ( insn ) ; for ( i = 0 ; i < len ; ++ i ) { rtx curr_insn = parallel_element ( insn , i ) ; if ( GET_CODE ( curr_insn ) == SET && REG_P ( SET_DEST ( curr_insn ) ) && GET_CODE ( SET_SRC ( curr_insn ) ) == PLUS ) return i ; } return - 1 ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case TYPE_FSTORE : mem_rtx = extract_mem_rtx ( insn ) ; switch ( GET_CODE ( XEXP ( mem_rtx , 0 ) ) ) { case POST_INC : case POST_DEC : case POST_MODIFY : return 0 ; default : return - 1 ; } default : gcc_unreachable ( ) ; } } </s>

Find the post update rtx in INSN . If INSN is a load/store multiple insn , the function returns the vector index of its parallel part . If INSN is a single load/store insn , the function returns 0 . If INSN is not a post- update insn , the function returns -1 .


<s> static bool rs6000_builtin_valid_without_lhs ( enum rs6000_builtins fn_code ) { switch ( fn_code ) { case ALTIVEC_BUILTIN_STVX_V16QI : case ALTIVEC_BUILTIN_STVX_V8HI : case ALTIVEC_BUILTIN_STVX_V4SI : case ALTIVEC_BUILTIN_STVX_V4SF : case ALTIVEC_BUILTIN_STVX_V2DI : case ALTIVEC_BUILTIN_STVX_V2DF : case VSX_BUILTIN_STXVW4X_V16QI : case VSX_BUILTIN_STXVW4X_V8HI : case VSX_BUILTIN_STXVW4X_V4SF : case VSX_BUILTIN_STXVW4X_V4SI : case VSX_BUILTIN_STXVD2X_V2DF : case VSX_BUILTIN_STXVD2X_V2DI : return true ; default : return false ; } } </s>

Helper function to sort out which built-ins may be valid without having a LHS .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool EvexToVexInstPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; if ( ! ST . hasAVX512 ( ) ) return false ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) Changed |= CompressEvexToVexImpl ( MI ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s> static rtx ix86_expand_vec_ext_builtin ( tree exp , rtx target ) { machine_mode tmode , mode0 ; tree arg0 , arg1 ; int elt ; rtx op0 ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_extract ( true , target , op0 , elt ) ; return target ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_extract . They would be redundant ( for non-MMX ) if we had a language-level syntax for referencing vector elements .


<s> bool isLittleEndian ( ) const { return isLittle ; } </s>

Tests whether the target triple is little endian .


<s>
StringRef
ARM64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


"Could not generate addis value for fusion"

Emit the addis instruction that will be part of a fused instruction sequence .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"OR1K Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static unsigned int mips_seq_time ( struct mips_sim * state , rtx_insn * seq ) { mips_sim_reset ( state ) ; for ( rtx_insn * insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) { mips_sim_wait_insn ( state , insn ) ; mips_sim_issue_insn ( state , insn ) ; } return state -> time ; } </s>

Use simulator state STATE to calculate the execution time of instruction sequence SEQ .


<s>
InstructionCost
AArch64TTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
ValTy
,
bool
IsPairwiseForm
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
isa
<
ScalableVectorType
>
(
ValTy
)
)
return
getArithmeticReductionCostSVE
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
if
(
IsPairwiseForm
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
ValTy
)
;
MVT
MTy
=
LT
.
second
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
CostTblEntry
CostTblNoPairwise
[
]
{
{
ISD
::
ADD
,
MVT
::
v8i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v16i8
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v8i16
,
1
}
,
{
ISD
::
ADD
,
MVT
::
v4i32
,
1
}
,
}
;
if
(
const
auto
*
Entry
=
CostTableLookup
(
CostTblNoPairwise
,
ISD
,
MTy
)
)
return
LT
.
first
*
Entry
->
Cost
;
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
ValTy
,
IsPairwiseForm
,
CostKind
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .


<s> static inline int rs6000_secondary_reload_toc_costs ( addr_mask_type addr_mask ) { int ret ; if ( TARGET_CMODEL != CMODEL_SMALL ) ret = ( ( addr_mask & RELOAD_REG_OFFSET ) == 0 ) ? 1 : 2 ; else ret = ( TARGET_MINIMAL_TOC ) ? 6 : 3 ; return ret ; } </s>

Helper function to return the cost of adding a TOC entry address .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> rtx extract_base_reg ( rtx_insn * insn ) { int post_update_rtx_index ; rtx mem_rtx ; rtx plus_rtx ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_SRC ( parallel_element ( insn , 0 ) ) ; break ; case TYPE_STORE_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_DEST ( parallel_element ( insn , 0 ) ) ; break ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case TYPE_FSTORE : mem_rtx = extract_mem_rtx ( insn ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( MEM_P ( mem_rtx ) ) ; if ( REG_P ( XEXP ( mem_rtx , 0 ) ) ) return XEXP ( mem_rtx , 0 ) ; if ( GET_CODE ( XEXP ( mem_rtx , 0 ) ) == LO_SUM ) return XEXP ( XEXP ( mem_rtx , 0 ) , 0 ) ; plus_rtx = XEXP ( mem_rtx , 0 ) ; if ( GET_CODE ( plus_rtx ) == SYMBOL_REF || GET_CODE ( plus_rtx ) == CONST ) return NULL_RTX ; gcc_assert ( GET_CODE ( plus_rtx ) == PLUS || GET_CODE ( plus_rtx ) == POST_INC || GET_CODE ( plus_rtx ) == POST_DEC || GET_CODE ( plus_rtx ) == POST_MODIFY ) ; if ( REG_P ( XEXP ( plus_rtx , 0 ) ) ) return XEXP ( plus_rtx , 0 ) ; gcc_assert ( REG_P ( XEXP ( plus_rtx , 1 ) ) ) ; return XEXP ( plus_rtx , 1 ) ; } </s>

Extract the base register from load/store insns . The function returns NULL_RTX if the address is not consist of any registers .


<s> bool isBlockAddress ( ) const { return Kind == CSKYCP :: CPBlockAddress ; } </s>

isBlockAddress - Tests if this is a MO_BlockAddress operand .


<s> rtx ia64_return_addr_rtx ( HOST_WIDE_INT count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return NULL ; return gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_RET_ADDR ) ; } </s>

Return the magic cookie that we use to hold the return address during early compilation .


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr * MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI -> getOpcode ( ) ) ) return 0 ; const MachineOperand & MO = MI -> getOperand ( 0 ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI -> readsRegister ( Reg , TRI ) ) return 0 ; } return 16 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> RegisterBankInfo :: InstructionMapping AArch64RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { RegisterBankInfo :: InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; LLT Ty = MI . getType ( ) ; unsigned BankID ; if ( Ty . isVector ( ) ) BankID = AArch64 :: FPRRegBankID ; else BankID = AArch64 :: GPRRegBankID ; Mapping = InstructionMapping { 1 , 1 , MI . getNumOperands ( ) } ; int Size = Ty . isSized ( ) ? Ty . getSizeInBits ( ) : 0 ; for ( unsigned Idx = 0 ; Idx < MI . getNumOperands ( ) ; ++ Idx ) Mapping . setOperandMapping ( Idx , Size , getRegBank ( BankID ) ) ; return Mapping ; } </s>

Get the mapping of the different operands of MI on the register bank .