<s>
SDValue
OpenRISCTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

OpenRISC
OpenRISC
"unimplemented operand"


<s> bool nonpic_symbol_mentioned_p ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == PC ) return true ; if ( GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC || XINT ( x , 1 ) == UNSPEC_GOT || XINT ( x , 1 ) == UNSPEC_GOTOFF || XINT ( x , 1 ) == UNSPEC_GOTPLT || XINT ( x , 1 ) == UNSPEC_GOTTPOFF || XINT ( x , 1 ) == UNSPEC_DTPOFF || XINT ( x , 1 ) == UNSPEC_TPOFF || XINT ( x , 1 ) == UNSPEC_PLT || XINT ( x , 1 ) == UNSPEC_PCREL || XINT ( x , 1 ) == UNSPEC_SYMOFF || XINT ( x , 1 ) == UNSPEC_PCREL_SYMOFF || XINT ( x , 1 ) == UNSPEC_GOTFUNCDESC || XINT ( x , 1 ) == UNSPEC_GOTOFFFUNCDESC ) ) return false ; const char * fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( int i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { for ( int j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( nonpic_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && nonpic_symbol_mentioned_p ( XEXP ( x , i ) ) ) return true ; } return false ; } </s>

Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol is n't protected by a PIC unspec .


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> rtx gen_datalabel_ref ( rtx sym ) { const char * str ; if ( GET_CODE ( sym ) == LABEL_REF ) return gen_rtx_CONST ( GET_MODE ( sym ) , gen_rtx_UNSPEC ( GET_MODE ( sym ) , gen_rtvec ( 1 , sym ) , UNSPEC_DATALABEL ) ) ; gcc_assert ( GET_CODE ( sym ) == SYMBOL_REF ) ; str = XSTR ( sym , 0 ) ; str = IDENTIFIER_POINTER ( get_identifier ( str ) ) ; XSTR ( sym , 0 ) = str ; return sym ; } </s>

Prefix a symbol_ref name with `` datalabel '' .


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getCPUDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> static bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ) { tree fntype ; if ( decl ) fntype = TREE_TYPE ( decl ) ; else fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE && ! ( decl && decl == current_function_decl ) ) { function_args_iterator args_iter ; tree type ; int nvreg = 0 ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > 0 ) return false ; } if ( DEFAULT_ABI == ABI_DARWIN || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && decl && ! DECL_EXTERNAL ( decl ) && ! DECL_WEAK ( decl ) && ( * targetm . binds_local_p ) ( decl ) ) || ( DEFAULT_ABI == ABI_V4 && ( ! TARGET_SECURE_PLT || ! flag_pic || ( decl && ( * targetm . binds_local_p ) ( decl ) ) ) ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> bool FISCTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void PPCPostRASchedStrategy :: initialize ( ScheduleDAGMI * Dag ) { PostGenericScheduler :: initialize ( Dag ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> void AArch64ConditionalCompares :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void sparc_expand_vcond ( machine_mode mode , rtx * operands , int ccode , int fcode ) { enum rtx_code code = signed_condition ( GET_CODE ( operands [ 3 ] ) ) ; rtx mask , cop0 , cop1 , fcmp , cmask , bshuf , gsr ; mask = gen_reg_rtx ( Pmode ) ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; if ( code == LT || code == GE ) { code = swap_condition ( code ) ; std :: swap ( cop0 , cop1 ) ; } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 2 , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , operands [ 1 ] , operands [ 2 ] , gsr ) , UNSPEC_BSHUFFLE ) ; emit_insn ( gen_rtx_SET ( mask , fcmp ) ) ; emit_insn ( gen_rtx_SET ( gsr , cmask ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , bshuf ) ) ; } </s>

Emit code to conditionally move a combination of OPERANDS [ 1 ] and OPERANDS [ 2 ] into OPERANDS [ 0 ] in MODE , depending on the outcome of the comparison of OPERANDS [ 4 ] and OPERANDS [ 5 ] . OPERANDS [ 3 ] is the operator of the condition . FCODE is the machine code to be used for OPERANDS [ 3 ] and CCODE the machine code to be used for the condition mask .


<s>
bool
Mips16HardFloat
::
runOnModule
(
Module
&
M
)
{
auto
&
TM
=
static_cast
<
const
MipsTargetMachine
&
>
(
getAnalysis
<
TargetPassConfig
>
(
)
.
getTM
<
TargetMachine
>
(
)
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Run on Module Mips16HardFloat\n"
)
;
bool
Modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
hasFnAttribute
(
"nomips16"
)
&&
F
->
hasFnAttribute
(
"use-soft-float"
)
)
{
removeUseSoftFloat
(
*
F
)
;
continue
;
}
if
(
F
->
isDeclaration
(
)
||
F
->
hasFnAttribute
(
"mips16_fp_stub"
)
||
F
->
hasFnAttribute
(
"nomips16"
)
)
continue
;
Modified
|=
fixupFPReturnAndCall
(
*
F
,
&
M
,
TM
)
;
FPParamVariant
V
=
whichFPParamVariantNeeded
(
*
F
)
;
if
(
V
!=
NoSig
)
{
Modified
=
true
;
createFPFnStub
(
&
*
F
,
&
M
,
V
,
TM
)
;
}
}
return
Modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , DCI ) ; case ISD :: VSELECT : case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: ADD : return PerformAddCombine ( N , DAG , Subtarget ) ; case ISD :: SUB : return PerformSubCombine ( N , DAG , Subtarget ) ; case X86ISD :: ADC : return PerformADCCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: XOR : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: LOAD : return PerformLOADCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case ISD :: SINT_TO_FP : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case ISD :: FADD : return PerformFADDCombine ( N , DAG , Subtarget ) ; case ISD :: FSUB : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: TRUNCATE : return PerformTruncateCombine ( N , DAG , DCI ) ; case X86ISD :: SETCC : return PerformSETCCCombine ( N , DAG ) ; case X86ISD :: SHUFP : case X86ISD :: PALIGN : case X86ISD :: UNPCKH : case X86ISD :: UNPCKL : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case X86ISD :: VPERMILP : case X86ISD :: VPERM2X128 : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool AArch64TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 1 , FrameIndex ) ) return MI -> getOperand ( 0 ) . getReg ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void LC3bInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool targetHandlesStackFrameRounding ( ) const { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
char
Letter
,
bool
hasMemory
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
unsigned
Value
=
CST
->
getZExtValue
(
)
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'J'
:
case
'L'
:
if
(
(
short
)
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'K'
:
if
(
(
Value
>>
16
)
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'N'
:
if
(
(
int
)
Value
>
0
&&
isPowerOf2_32
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'P'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Letter
,
hasMemory
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> bool PPCSubtarget :: enablePostRAScheduler ( ) const { return true ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> int registers_ok_for_ldd_peep ( rtx reg1 , rtx reg2 ) { if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return 0 ; if ( REGNO ( reg1 ) % 2 != 0 ) return 0 ; if ( TARGET_V9 && SPARC_INT_REG_P ( REGNO ( reg1 ) ) ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) is even and REGNO ( reg1 ) == REGNO ( reg2 ) - 1 . This makes them candidates for using ldd and std insns . Note reg1 and reg2 * must * be hard registers .


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! Subtarget . allowsUnalignedFPAccess ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
if
(
Factor
>
4
)
return
false
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeSizeInBits
(
SubVecTy
)
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! DisableLdStOpti && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None && ! DisableIfConversion && ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; if ( Subtarget . isThumb2 ( ) ) { PM . add ( createThumb2ITBlockPass ( ) ) ; PM . add ( createThumb2SizeReductionPass ( ) ) ; } PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
CAHPDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
Node
->
getOpcode
(
)
==
ISD
::
FrameIndex
)
{
SDLoc
DL
(
Node
)
;
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
MVT
::
i16
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
CAHP
::
ADDI
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> int compute_convert_gain ( ) { return 1 ; } </s>


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) ; const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( STI . getInstrInfo ( ) ) ; LongBranchSeqSize = ! IsPIC ? 2 : ( ABI . IsN64 ( ) ? 10 : ( ! STI . isTargetNaCl ( ) ? 9 : 10 ) ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool isPredicated ( ) const { return Predicated ; } </s>

Returns true if the instruction is already predicated .


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , unsigned nelt , rtx perm [ ] ) { machine_mode imode ; rtx x ; imode = vmode ; if ( GET_MODE_CLASS ( vmode ) != MODE_VECTOR_INT ) { imode = mode_for_size ( GET_MODE_UNIT_BITSIZE ( vmode ) , MODE_INT , 0 ) ; imode = mode_for_vector ( imode , nelt ) ; } x = gen_rtx_CONST_VECTOR ( imode , gen_rtvec_v ( nelt , perm ) ) ; x = expand_vec_perm ( vmode , op0 , op1 , x , target ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave .


<s> void function_expander :: prepare_gather_address_operands ( unsigned int argno , bool scaled_p ) { machine_mode mem_mode = memory_vector_mode ( ) ; tree vector_type = base_vector_type ( ) ; units_index units = displacement_units ( ) ; int shift_idx = - 1 ; if ( units == UNITS_none ) { args . quick_insert ( argno , const0_rtx ) ; units = UNITS_bytes ; } else if ( vector_type ) { std :: swap ( args [ argno ] , args [ argno + 1 ] ) ; if ( units == UNITS_elements ) shift_idx = argno ; } else { args [ argno ] = convert_to_pmode ( args [ argno ] ) ; vector_type = displacement_vector_type ( ) ; if ( units == UNITS_elements && ! scaled_p ) shift_idx = argno + 1 ; } tree scalar_displacement_type = TREE_TYPE ( vector_type ) ; if ( shift_idx >= 0 ) { machine_mode arg_mode = GET_MODE ( args [ shift_idx ] ) ; if ( arg_mode == VOIDmode ) arg_mode = DImode ; unsigned int elt_bytes = GET_MODE_UNIT_SIZE ( mem_mode ) ; rtx shift = gen_int_mode ( exact_log2 ( elt_bytes ) , DImode ) ; args [ shift_idx ] = simplify_gen_binary ( ASHIFT , arg_mode , args [ shift_idx ] , shift ) ; units = UNITS_bytes ; } bool uxtw_p = ( TYPE_PRECISION ( scalar_displacement_type ) == 64 || TYPE_UNSIGNED ( scalar_displacement_type ) ) ; unsigned int scale = ( units == UNITS_bytes ? 1 : GET_MODE_UNIT_SIZE ( mem_mode ) ) ; if ( scaled_p ) { args . quick_insert ( argno + 2 , GEN_INT ( uxtw_p ) ) ; args . quick_insert ( argno + 3 , GEN_INT ( scale ) ) ; } else gcc_assert ( uxtw_p && scale == 1 ) ; } </s>

Convert the arguments to a gather/scatter function into the associated md operands . Argument ARGNO is the scalar or vector base and argument ARGNO + 1 is the scalar or vector displacement ( if applicable ) . The md pattern expects : - a scalar base - a vector displacement If SCALED_P is true , it also expects : - a const_int that is 1 if the displacement is zero-extended from 32 bits - a scaling multiplier ( 1 for bytes , 2 for .h indices , etc. ) . If SCALED_P is false , the displacement is implicitly zero-extended and the scaling multiplier is implicitly 1 .


<s> bool AArch64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> Write32 ( 0xd503201f ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
.
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
Subtarget
.
isGP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
if
(
VT
==
MVT
::
i64
&&
Subtarget
.
isGP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR64RegClass
)
;
return
std
::
make_pair
(
0U
,
nullptr
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
else
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
.
isSingleFloat
(
)
)
)
{
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
GPR32RegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
GPR64RegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO0
,
&
Mips
::
LO32RegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO0_64
,
&
Mips
::
LO64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0U
,
nullptr
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
parseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> bool aarch64_high_bits_all_ones_p ( HOST_WIDE_INT i ) { return exact_log2 ( - i ) != HOST_WIDE_INT_M1 ; } </s>

Return true if I 's bits are consecutive ones from the MSB .


<s> unsigned TOYRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return TOY :: SP ; } </s>


<s> int ia64_eh_uses ( int regno ) { unsigned int r ; if ( ! reload_completed ) return 0 ; if ( regno == 0 ) return 0 ; for ( r = reg_save_b0 ; r <= reg_save_ar_lc ; r ++ ) if ( regno == current_frame_info . r [ r ] || regno == emitted_frame_related_regs [ r ] ) return 1 ; return 0 ; } </s>

Return true if REGNO is used by the frame unwinder .


<s> static void push_regs ( HARD_REG_SET * mask , int interrupt_handler ) { int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0 ; int skip_fpscr = 0 ; for ( ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_reg_set_intersect_p ( * mask , reg_class_contents [ DF_REGS ] ) ) { HARD_REG_SET unsaved ; push ( FPSCR_REG ) ; COMPL_HARD_REG_SET ( unsaved , * mask ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , unsaved ) ; skip_fpscr = 1 ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = 0 ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + 1 ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = frame_insn ( x ) ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * 4 ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( SImode , mem , reg ) ) ; } set = gen_rtx_SET ( SImode , sp_reg , plus_constant ( Pmode , sp_reg , - 32 ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; } else for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) && ! sh_cfun_resbank_handler_p ( ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


"Not adding R_MIPS_JALR against data symbol "

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool isReg ( ) const { return false ; } </s>


<s> bool X86AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { unsigned Kind ; unsigned Opcode ; unsigned ErrorInfo ; SmallVector < std :: pair < unsigned , std :: string > , 4 > MapAndConstraints ; bool Error = MatchInstruction ( IDLoc , Operands , Out , Kind , Opcode , MapAndConstraints , ErrorInfo ) ; return Error ; } </s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> machine_mode select_cc_mode ( enum rtx_code op , rtx x , rtx y ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return CCFPmode ; case LT : case LE : case GT : case GE : case LTGT : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) && y == const0_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXNZmode ; else return CCNZmode ; } else { if ( GET_CODE ( x ) == NOT && y == constm1_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXCmode ; else return CCCmode ; } if ( ! TARGET_ARCH64 && GET_MODE ( x ) == DImode ) { if ( GET_CODE ( y ) == UNSPEC && ( XINT ( y , 1 ) == UNSPEC_ADDV || XINT ( y , 1 ) == UNSPEC_SUBV || XINT ( y , 1 ) == UNSPEC_NEGV ) ) return CCVmode ; else return CCCmode ; } if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXmode ; else return CCmode ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison . For floating-point , CCFP [ E ] mode is used . CC_NOOVmode should be used when the first operand is a PLUS , MINUS , NEG , or ASHIFT . CCmode should be used when no special processing is needed .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: LVX : case PPC :: RESTORE_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : case V2HQmode : case V2UHQmode : case V2HAmode : case V2UHAmode : case V4QQmode : case V4UQQmode : return TARGET_DSP ; case V2SImode : case V4HImode : case V8QImode : return TARGET_LOONGSON_VECTORS ; default : return false ; } } </s>

Target hook for vector_mode_supported_p .


<s> void sparc_flat_expand_epilogue ( bool for_eh ) { HOST_WIDE_INT size = sparc_frame_size ; if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_RESTORE ) ; if ( frame_pointer_needed && ! for_eh ) emit_move_insn ( gen_rtx_REG ( Pmode , 1 ) , hard_frame_pointer_rtx ) ; if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) emit_move_insn ( gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ; if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( sparc_frame_base_reg , sparc_frame_base_offset , SORR_RESTORE ) ; if ( size == 0 || for_eh ) ; else if ( frame_pointer_needed ) { emit_insn ( gen_frame_blockage ( ) ) ; emit_move_insn ( stack_pointer_rtx , gen_rtx_REG ( Pmode , 1 ) ) ; } else { emit_insn ( gen_frame_blockage ( ) ) ; if ( size <= 4096 ) emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; else if ( size <= 8192 ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - 4096 ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( size ) ) ; emit_insn ( gen_stack_pointer_inc ( reg ) ) ; } } } </s>

Expand the function epilogue , either normal or part of a sibcall . We emit all the instructions except the return or the call .


<s> int arm_float_words_big_endian ( void ) { if ( TARGET_MAVERICK ) return 0 ; if ( TARGET_FPA ) { return 1 ; } if ( TARGET_VFP ) return ( TARGET_BIG_END ? 1 : 0 ) ; return 1 ; } </s>

Indicate whether or not words of a double are in big-endian order .


<s> void csky_init_builtins ( void ) { static tree csky_floatHF_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( csky_floatHF_type_node ) = GET_MODE_PRECISION ( HFmode ) ; layout_type ( csky_floatHF_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( csky_floatHF_type_node , "__fp16" ) ; } </s>

Implement the TARGET_INIT_BUILTINS target macro .


<s> void nds32_cpu_cpp_builtins ( struct cpp_reader * pfile ) { builtin_define ( "__nds32__" ) ; builtin_define ( "__NDS32__" ) ; if ( ! TARGET_LINUX_ABI ) { if ( TARGET_ISR_VECTOR_SIZE_4_BYTE ) builtin_define ( "__NDS32_ISR_VECTOR_SIZE_4__" ) ; else builtin_define ( "__NDS32_ISR_VECTOR_SIZE_16__" ) ; } if ( TARGET_HARD_FLOAT ) builtin_define ( "__NDS32_ABI_2FP_PLUS__" ) ; else builtin_define ( "__NDS32_ABI_2__" ) ; if ( TARGET_ISA_V2 ) builtin_define ( "__NDS32_ISA_V2__" ) ; if ( TARGET_ISA_V3 ) builtin_define ( "__NDS32_ISA_V3__" ) ; if ( TARGET_ISA_V3M ) builtin_define ( "__NDS32_ISA_V3M__" ) ; if ( TARGET_FPU_SINGLE ) builtin_define ( "__NDS32_EXT_FPU_SP__" ) ; if ( TARGET_FPU_DOUBLE ) builtin_define ( "__NDS32_EXT_FPU_DP__" ) ; if ( TARGET_EXT_FPU_FMA ) builtin_define ( "__NDS32_EXT_FPU_FMA__" ) ; if ( NDS32_EXT_FPU_DOT_E ) builtin_define ( "__NDS32_EXT_FPU_DOT_E__" ) ; if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { switch ( nds32_fp_regnum ) { case 0 : case 4 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_0__" ) ; break ; case 1 : case 5 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_1__" ) ; break ; case 2 : case 6 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_2__" ) ; break ; case 3 : case 7 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_3__" ) ; break ; default : abort ( ) ; } } if ( TARGET_BIG_ENDIAN ) builtin_define ( "__NDS32_EB__" ) ; else builtin_define ( "__NDS32_EL__" ) ; if ( TARGET_REDUCED_REGS ) builtin_define ( "__NDS32_REDUCED_REGS__" ) ; if ( TARGET_CMOV ) builtin_define ( "__NDS32_CMOV__" ) ; if ( TARGET_EXT_PERF ) builtin_define ( "__NDS32_EXT_PERF__" ) ; if ( TARGET_EXT_PERF2 ) builtin_define ( "__NDS32_EXT_PERF2__" ) ; if ( TARGET_EXT_STRING ) builtin_define ( "__NDS32_EXT_STRING__" ) ; if ( TARGET_16_BIT ) builtin_define ( "__NDS32_16_BIT__" ) ; if ( TARGET_GP_DIRECT ) builtin_define ( "__NDS32_GP_DIRECT__" ) ; if ( TARGET_VH ) builtin_define ( "__NDS32_VH__" ) ; if ( NDS32_EXT_DSP_P ( ) ) builtin_define ( "__NDS32_EXT_DSP__" ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( "__big_endian__" ) ; builtin_assert ( "cpu=nds32" ) ; builtin_assert ( "machine=nds32" ) ; if ( TARGET_HARD_FLOAT ) builtin_define ( "__NDS32_ABI_2FP_PLUS" ) ; else builtin_define ( "__NDS32_ABI_2" ) ; } </s>


<s> unsigned int UPTInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( MBB . empty ( ) ) return 0 ; unsigned NumRemoved = 0 ; auto I = MBB . end ( ) ; do { -- I ; unsigned Opc = I -> getOpcode ( ) ; if ( ( Opc == UPT :: JMP ) || ( Opc == UPT :: Bcc ) ) { auto ToDelete = I ; ++ I ; MBB . erase ( ToDelete ) ; NumRemoved ++ ; } } while ( I != MBB . begin ( ) ) ; return NumRemoved ; } </s>

Remove the branching code at the end of the specific MBB .


<s> rtx expand ( function_expander & e ) const override { int unspec = ( e . type_suffix ( 1 ) . unsigned_p ? m_unspec_for_uint : m_unspec_for_sint ) ; machine_mode pred_mode = e . vector_mode ( 0 ) ; scalar_mode reg_mode = GET_MODE_INNER ( e . vector_mode ( 1 ) ) ; return e . use_exact_insn ( code_for_while ( unspec , reg_mode , pred_mode ) ) ; } </s>


<s> static bool insn_is_function_arg ( rtx insn , bool * is_spilled ) { rtx dst ; if ( ! NONDEBUG_INSN_P ( insn ) ) return false ; if ( CALL_P ( insn ) ) return false ; insn = PATTERN ( insn ) ; if ( GET_CODE ( insn ) == PARALLEL ) insn = XVECEXP ( insn , 0 , 0 ) ; if ( GET_CODE ( insn ) != SET ) return false ; dst = SET_DEST ( insn ) ; if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ix86_function_arg_regno_p ( REGNO ( dst ) ) ) { if ( ! TEST_HARD_REG_BIT ( fixed_reg_set , REGNO ( dst ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) ) * is_spilled = true ; return true ; } return false ; } </s>

Returns true if lhs of insn is HW function argument register and set up is_spilled to true if it is likely spilled HW register .


"unknown parameter to option %<-mtune-ctrl%>: %s"

parse -mtune-ctrl= option . When DUMP is true , print the features that are explicitly set .


<s> static void arm_add_cfa_adjust_cfa_note ( rtx insn , int size , rtx dest , rtx src ) { rtx dwarf ; RTX_FRAME_RELATED_P ( insn ) = 1 ; dwarf = gen_rtx_SET ( dest , plus_constant ( Pmode , src , size ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , dwarf ) ; } </s>

Add a REG_CFA_ADJUST_CFA REG note to INSN . SIZE is the offset to be adjusted . DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx .


Expand movmem , as if from a __builtin_memcpy . Return true if we succeed , otherwise return false .


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) { if ( ! VECTOR_MODE_P ( mode ) ) return cost ; if ( GET_MODE_BITSIZE ( mode ) == 128 && TARGET_SSE_SPLIT_REGS ) return cost * 2 ; if ( GET_MODE_BITSIZE ( mode ) > 128 && TARGET_AVX256_SPLIT_REGS ) return cost * GET_MODE_BITSIZE ( mode ) / 128 ; return cost ; } </s>

Return cost of vector operation in MODE given that scalar version has COST . If PARALLEL is true assume that CPU has more than one unit performing the operation .


<s> static unsigned getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) { return ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / 128 ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


Initialize the table of extra 80387 mathematical constants .


<s> bool aarch64_bitmask_imm ( HOST_WIDE_INT val_in , machine_mode mode ) { unsigned HOST_WIDE_INT val , tmp , mask , first_one , next_one ; int bits ; val = ( unsigned HOST_WIDE_INT ) val_in ; tmp = val + ( val & - val ) ; if ( tmp == ( tmp & - tmp ) ) return ( val + 1 ) > 1 ; if ( mode == SImode ) val = ( val << 32 ) | ( val & 0xffffffff ) ; if ( val & 1 ) val = ~ val ; first_one = val & - val ; tmp = val & ( val + first_one ) ; if ( tmp == 0 ) return true ; next_one = tmp & - tmp ; bits = clz_hwi ( first_one ) - clz_hwi ( next_one ) ; mask = val ^ tmp ; if ( ( mask >> bits ) != 0 || bits != ( bits & - bits ) ) return false ; return val == mask * bitmask_imm_mul [ __builtin_clz ( bits ) - 26 ] ; } </s>

Return true if val is a valid bitmask immediate .


<s>
void
ARMBaseInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
unsigned
Align
=
MFI
.
getObjectAlignment
(
FI
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
0
,
MFI
.
getObjectSize
(
FI
)
,
Align
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
RC
=
ARM
::
GPRRegisterClass
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
STR
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
||
RC
==
ARM
::
DPR_VFP2RegisterClass
||
RC
==
ARM
::
DPR_8RegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VSTRD
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
SPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VSTRS
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
{
assert
(
(
RC
==
ARM
::
QPRRegisterClass
||
RC
==
ARM
::
QPR_VFP2RegisterClass
)
&&
"Unknown regclass!"
)
;
if
(
Align
>=
16
&&
(
getRegisterInfo
(
)
.
canRealignStack
(
MF
)
)
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VST1q
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
128
)
.
addMemOperand
(
MMO
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
)
;
}
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VSTMQ
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
ARM_AM
::
getAM5Opc
(
ARM_AM
::
ia
,
4
)
)
.
addMemOperand
(
MMO
)
)
;
}
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


"Tail call for extern symbol not yet supported."

Targets should implement this to emit instructions .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , const DebugLoc & DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = Subtarget ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; Register Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s>
StackOffset
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
IgnoreSPUpdates
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
StackOffset
::
getFixed
(
MFI
.
getObjectOffset
(
FI
)
)
;
}
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool AArch64TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


"getBranchTargetOpValueMM expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand .


<s> static void csky_setup_incoming_varargs ( cumulative_args_t pcum_v , machine_mode mode , tree type , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; CUMULATIVE_ARGS local_cum ; cumulative_args_t local_cum_v = pack_cumulative_args ( & local_cum ) ; int regs_to_push ; cfun -> machine -> uses_anonymous_args = 1 ; local_cum = * pcum ; csky_function_arg_advance ( local_cum_v , mode , type , true ) ; regs_to_push = CSKY_NPARM_REGS - local_cum ; if ( regs_to_push ) * pretend_size = regs_to_push * UNITS_PER_WORD ; } </s>

Implement TARGET_SETUP_INCOMING_VARARGS . On C-Sky the copy from the argument registers to the stack is emitted by the prologue hooks , so here we just have to note how much stack space to save .


<s> StringRef ARMALFWriter :: getPassName ( ) const { return "ARMALFWriter" ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
output_add_immediate
(
rtx
*
operands
)
{
HOST_WIDE_INT
n
=
INTVAL
(
operands
[
2
]
)
;
if
(
n
!=
0
||
REGNO
(
operands
[
0
]
)
!=
REGNO
(
operands
[
1
]
)
)
{
if
(
n
<
0
)
output_multi_immediate
(
operands
,
"sub%?\t%0, %1, %2"
,
"sub%?\t%0, %0, %2"
,
2
,
n
)
;
else
output_multi_immediate
(
operands
,
"add%?\t%0, %1, %2"
,
"add%?\t%0, %0, %2"
,
2
,
n
)
;
}
return
""
;
}
</s>

Output an ADD r , s , # n where n may be too big for one instruction . If adding zero to one register , output nothing .


<s> void AArch64ConditionOptimizer :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles ( nullptr ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , bool IsTailCall ) const { if ( IsTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const override { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


Return the type to use as __builtin_va_list .


"LC3b DAG->DAG Pattern Instruction Selection"


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , uint64_t Size , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Alignment = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , Alignment ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : case ISD :: ROTL : return combineSHIFTROT ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool AArch64ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AArch64InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
char
*
output_jump_label_table
(
void
)
{
int
i
;
if
(
pool_size
)
{
fprintf
(
asm_out_file
,
"\t.align 2\n"
)
;
for
(
i
=
0
;
i
<
pool_size
;
i
++
)
{
pool_node
*
p
=
&
pool_vector
[
i
]
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
p
->
label
)
)
;
output_asm_insn
(
".long	%O0"
,
&
p
->
value
)
;
}
pool_size
=
0
;
}
return
""
;
}
</s>

Dump out any constants accumulated in the final pass . These will only be labels .


<s>
void
GeneralShuffle
::
add
(
SDValue
Op
,
unsigned
Elem
)
{
unsigned
BytesPerElement
=
VT
.
getVectorElementType
(
)
.
getStoreSize
(
)
;
EVT
FromVT
=
Op
.
getNode
(
)
Op
.
getValueType
(
)
:
VT
;
unsigned
FromBytesPerElement
=
FromVT
.
getVectorElementType
(
)
.
getStoreSize
(
)
;
assert
(
FromBytesPerElement
>=
BytesPerElement
&&
"Invalid EXTRACT_VECTOR_ELT"
)
;
unsigned
Byte
=
(
(
Elem
*
FromBytesPerElement
)
%
SystemZ
::
VectorBytes
+
(
FromBytesPerElement
BytesPerElement
)
)
;
while
(
Op
.
getNode
(
)
)
{
if
(
Op
.
getOpcode
(
)
==
ISD
::
BITCAST
)
Op
=
Op
.
getOperand
(
0
)
;
else
if
(
Op
.
getOpcode
(
)
==
ISD
::
VECTOR_SHUFFLE
&&
Op
.
hasOneUse
(
)
)
{
SmallVector
<
int
,
SystemZ
::
VectorBytes
>
OpBytes
;
getVPermMask
(
cast
<
ShuffleVectorSDNode
>
(
Op
)
,
OpBytes
)
;
int
NewByte
;
if
(
!
getShuffleInput
(
OpBytes
,
Byte
,
BytesPerElement
,
NewByte
)
)
break
;
if
(
NewByte
<
0
)
{
addUndef
(
)
;
return
;
}
Op
=
Op
.
getOperand
(
unsigned
(
NewByte
)
/
SystemZ
::
VectorBytes
)
;
Byte
=
unsigned
(
NewByte
)
%
SystemZ
::
VectorBytes
;
}
else
if
(
Op
.
getOpcode
(
)
==
ISD
::
UNDEF
)
{
addUndef
(
)
;
return
;
}
else
break
;
}
unsigned
OpNo
=
0
;
for
(
;
OpNo
<
Ops
.
size
(
)
;
++
OpNo
)
if
(
Ops
[
OpNo
]
==
Op
)
break
;
if
(
OpNo
==
Ops
.
size
(
)
)
Ops
.
push_back
(
Op
)
;
unsigned
Base
=
OpNo
*
SystemZ
::
VectorBytes
+
Byte
;
for
(
unsigned
I
=
0
;
I
<
BytesPerElement
;
++
I
)
Bytes
.
push_back
(
Base
+
I
)
;
}
</s>


<s> static void aarch64_pushwb_single_reg ( machine_mode mode , unsigned regno , HOST_WIDE_INT adjustment ) { rtx base_rtx = stack_pointer_rtx ; rtx insn , reg , mem ; reg = gen_rtx_REG ( mode , regno ) ; mem = gen_rtx_PRE_MODIFY ( Pmode , base_rtx , plus_constant ( Pmode , base_rtx , - adjustment ) ) ; mem = gen_frame_mem ( mode , mem ) ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push the register number REGNO of mode MODE to the stack with write-back adjusting the stack by ADJUSTMENT .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None , bool MatchingInlineAsm = false ) { MCAsmParser & Parser = getParser ( ) ; if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MF . setHasWinCFI ( false ) ; if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) MF . getFrameInfo ( ) . ensureMaxAlignment ( Align ( SlotSize ) ) ; if ( STI . is64Bit ( ) && MF . hasEHFunclets ( ) && classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) == EHPersonality :: MSVC_CXX ) { adjustFrameForMsvcCxxEh ( MF ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void F2003fInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s>
SDValue
OR1KTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> void output_profile_hook ( int labelno ATTRIBUTE_UNUSED ) { if ( TARGET_PROFILE_KERNEL ) return ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( NO_PROFILE_COUNTERS ) emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode , 0 ) ; else { char buf [ 30 ] ; const char * label_name ; rtx fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode , 1 , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LR_REGNO ; crtl -> uses_pic_offset_table = 1 ; if ( MACHOPIC_INDIRECT && crtl -> uses_pic_offset_table ) caller_addr_regno = 0 ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , LCT_NORMAL , VOIDmode , 1 , gen_rtx_REG ( Pmode , caller_addr_regno ) , Pmode ) ; } } </s>


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) { addPass ( createAArch64AdvSIMDScalar ( ) ) ; addPass ( & PeepholeOptimizerID ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool AArch64PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64PostSelectOptimize ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; if ( CRSpilled && IsCRField ) continue ; MBB . addLiveIn ( Reg ) ; if ( IsCRField ) { CRSpilled = true ; if ( Subtarget . isPPC64 ( ) ) { MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: X12 ) ) ; MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: X12 , getKillRegState ( true ) ) . addImm ( 8 ) . addReg ( PPC :: X1 ) ) ; } else { MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>


<s> TargetPassConfig * TeeRISCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TeeRISCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool PPCPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override { if ( VT . isScalableVector ( ) || VT . getVectorNumElements ( ) == 1 ) return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; if ( VT . getScalarSizeInBits ( ) == 1 && VT . getSizeInBits ( ) > 16 ) return TypeSplitVector ; if ( VT . getScalarSizeInBits ( ) == 1 ) return TypePromoteInteger ; if ( VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s>
static
void
rs6000_debug_reg_print
(
int
first_regno
,
int
last_regno
,
const
char
*
reg_name
)
{
int
r
,
m
;
for
(
r
=
first_regno
;
r
<=
last_regno
;
++
r
)
{
const
char
*
comma
=
""
;
int
len
;
if
(
first_regno
==
last_regno
)
fprintf
(
stderr
,
"%s:\t"
,
reg_name
)
;
else
fprintf
(
stderr
,
"%s%d:\t"
,
reg_name
,
r
first_regno
)
;
len
=
8
;
for
(
m
=
0
;
m
<
NUM_MACHINE_MODES
;
++
m
)
if
(
rs6000_hard_regno_mode_ok_p
[
m
]
[
r
]
&&
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
if
(
rs6000_hard_regno_nregs
[
m
]
[
r
]
>
1
)
len
+=
fprintf
(
stderr
,
"%s%s/%d"
,
comma
,
GET_MODE_NAME
(
m
)
,
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
;
else
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
GET_MODE_NAME
(
m
)
)
;
comma
=
", "
;
}
if
(
call_used_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"call-used"
)
;
comma
=
", "
;
}
if
(
fixed_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"fixed"
)
;
comma
=
", "
;
}
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%sreg-class = %s"
,
comma
,
reg_class_names
[
(
int
)
rs6000_regno_regclass
[
r
]
]
)
;
comma
=
", "
;
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
fprintf
(
stderr
,
"%sregno = %d\n"
,
comma
,
r
)
;
}
}
</s>

Print interesting facts about registers .


<s> unsigned MipsTargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context , VT ) ; IntermediateVT = RegisterVT ; NumIntermediates = VT . getSizeInBits ( ) < RegisterVT . getSizeInBits ( ) ? VT . getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ; return NumIntermediates ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> static struct machine_function * mips_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> bool MipsFastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> void neon_const_bounds ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high ) { bounds_check ( operand , low , high , NULL_TREE , "constant" ) ; } </s>


<s> static unsigned long arm_compute_save_reg0_reg12_mask ( ) { unsigned long func_type = arm_current_func_type ( ) ; unsigned int save_reg_mask = 0 ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = 7 ; else max_reg = 12 ; for ( reg = 0 ; reg <= max_reg ; reg ++ ) if ( regs_ever_live [ reg ] || ( ! current_function_is_leaf && call_used_regs [ reg ] ) ) save_reg_mask |= ( 1 << reg ) ; } else { for ( reg = 0 ; reg <= 10 ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; if ( ! TARGET_APCS_FRAME && ! frame_pointer_needed && regs_ever_live [ HARD_FRAME_POINTER_REGNUM ] && ! call_used_regs [ HARD_FRAME_POINTER_REGNUM ] ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } return save_reg_mask ; } </s>

Compute the register save mask for registers 0 through 12 inclusive . This code is used by arm_compute_save_reg_mask .


<s> inline static bool isMem ( const MachineInstr * MI , unsigned Op ) { if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + 5 <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + 4 ) . isReg ( ) && isLeaMem ( MI , Op ) ; } </s>


<s> void TOYInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( TOY :: LOADrr ) , DestReg ) . addFrameIndex ( FI ) . addReg ( TOY :: ZERO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool AArch64TargetLowering :: isMulAddWithConstProfitable ( SDValue AddNode , SDValue ConstNode ) const { const EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) || VT . getScalarSizeInBits ( ) > 64 ) return true ; const ConstantSDNode * C1Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; const ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C1 = C1Node -> getSExtValue ( ) ; const APInt C1C2 = C1Node -> getAPIntValue ( ) * C2Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C1 ) || isLegalAddImmediate ( C1C2 . getSExtValue ( ) ) ) return true ; SmallVector < AArch64_IMM :: ImmInsnModel , 4 > Insn ; AArch64_IMM :: expandMOVImm ( C1C2 . getZExtValue ( ) , VT . getSizeInBits ( ) , Insn ) ; if ( Insn . size ( ) > 1 ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


<s> static bool ia64_expand_vec_perm_const_1 ( struct expand_vec_perm_d * d ) { if ( expand_vec_perm_1 ( d ) ) return true ; if ( expand_vec_perm_broadcast ( d ) ) return true ; if ( expand_vec_perm_interleave_2 ( d ) ) return true ; if ( expand_vec_perm_v4hi_5 ( d ) ) return true ; return false ; } </s>

The guts of ia64_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s> bool ARMPassConfig :: addInstSelector ( ) { addPass ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; const ARMSubtarget * Subtarget = & getARMSubtarget ( ) ; if ( Subtarget -> isTargetELF ( ) && ! Subtarget -> isThumb1Only ( ) && TM -> Options . EnableFastISel ) addPass ( createARMGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> inline bool wrapped_symbol_hasher :: equal ( const value_type * x , const compare_type * y ) { return ! strcmp ( x , y ) ; } </s>


<s> bool check_use_sfunc_addr ( rtx_insn * insn , rtx reg ) { while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( LABEL_P ( insn ) || JUMP_P ( insn ) ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( rtx_sequence * seq = dyn_cast < rtx_sequence * > ( PATTERN ( insn ) ) ) insn = seq -> insn ( 0 ) ; if ( GET_CODE ( PATTERN ( insn ) ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) continue ; return rtx_equal_p ( extract_sfunc_addr ( insn ) , reg ) ; } gcc_unreachable ( ) ; } </s>

Verify that the register in use_sfunc_addr still agrees with the address used in the sfunc . This prevents fill_slots_from_thread from changing use_sfunc_addr . INSN is the use_sfunc_addr instruction , and REG is the register it guards .


<s> static void init_float128_ibm ( machine_mode mode ) { if ( ! TARGET_XL_COMPAT ) { set_optab_libfunc ( add_optab , mode , "__gcc_qadd" ) ; set_optab_libfunc ( sub_optab , mode , "__gcc_qsub" ) ; set_optab_libfunc ( smul_optab , mode , "__gcc_qmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "__gcc_qdiv" ) ; if ( ! TARGET_HARD_FLOAT ) { set_optab_libfunc ( neg_optab , mode , "__gcc_qneg" ) ; set_optab_libfunc ( eq_optab , mode , "__gcc_qeq" ) ; set_optab_libfunc ( ne_optab , mode , "__gcc_qne" ) ; set_optab_libfunc ( gt_optab , mode , "__gcc_qgt" ) ; set_optab_libfunc ( ge_optab , mode , "__gcc_qge" ) ; set_optab_libfunc ( lt_optab , mode , "__gcc_qlt" ) ; set_optab_libfunc ( le_optab , mode , "__gcc_qle" ) ; set_optab_libfunc ( unord_optab , mode , "__gcc_qunord" ) ; set_conv_libfunc ( sext_optab , mode , SFmode , "__gcc_stoq" ) ; set_conv_libfunc ( sext_optab , mode , DFmode , "__gcc_dtoq" ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , "__gcc_qtos" ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , "__gcc_qtod" ) ; set_conv_libfunc ( sfix_optab , SImode , mode , "__gcc_qtoi" ) ; set_conv_libfunc ( ufix_optab , SImode , mode , "__gcc_qtou" ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , "__gcc_itoq" ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , "__gcc_utoq" ) ; } } else { set_optab_libfunc ( add_optab , mode , "_xlqadd" ) ; set_optab_libfunc ( sub_optab , mode , "_xlqsub" ) ; set_optab_libfunc ( smul_optab , mode , "_xlqmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "_xlqdiv" ) ; } if ( mode == IFmode ) { set_conv_libfunc ( sext_optab , mode , SDmode , "__dpd_extendsdtf2" ) ; set_conv_libfunc ( sext_optab , mode , DDmode , "__dpd_extendddtf2" ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , "__dpd_trunctftd2" ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , "__dpd_trunctfsd2" ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , "__dpd_trunctfdd2" ) ; set_conv_libfunc ( sext_optab , TDmode , mode , "__dpd_extendtdtf2" ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , "__fixtfti" ) ; set_conv_libfunc ( ufix_optab , TImode , mode , "__fixunstfti" ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , "__floattitf" ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , "__floatuntitf" ) ; } } } </s>

Set up AIX/Darwin/64-bit Linux quad floating point routines .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC -> getID ( ) == X86 :: TILERegClassID ) { unsigned Opc = X86 :: TILELOADD ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & X86 :: GR64_NOSPRegClass ) ; MachineInstr * NewMI = BuildMI ( MBB , MI , DebugLoc ( ) , get ( X86 :: MOV64ri ) , VirtReg ) . addImm ( 64 ) ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; MachineOperand & MO = NewMI -> getOperand ( 3 ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else if ( RC -> getID ( ) == X86 :: TILECFGRegClassID ) { unsigned Opc = X86 :: PLDTILECFG ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } } </s>


<s> int neon_immediate_valid_for_shift ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth , bool isleftshift ) { unsigned int innersize = GET_MODE_UNIT_SIZE ( mode ) ; unsigned int n_elts = CONST_VECTOR_NUNITS ( op ) , i ; unsigned HOST_WIDE_INT last_elt = 0 ; unsigned HOST_WIDE_INT maxshift ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( op , i ) ; unsigned HOST_WIDE_INT elpart ; if ( CONST_INT_P ( el ) ) elpart = INTVAL ( el ) ; else if ( CONST_DOUBLE_P ( el ) ) return 0 ; else gcc_unreachable ( ) ; if ( i != 0 && elpart != last_elt ) return 0 ; last_elt = elpart ; } maxshift = innersize * 8 ; if ( isleftshift ) { if ( last_elt >= maxshift ) return 0 ; } else { if ( last_elt == 0 || last_elt > maxshift ) return 0 ; } if ( elementwidth ) * elementwidth = innersize * 8 ; if ( modconst ) * modconst = CONST_VECTOR_ELT ( op , 0 ) ; return 1 ; } </s>

Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction . If the immediate is valid , write a constant suitable for using as an operand to VSHR/VSHL to * MODCONST and the corresponding element width to * ELEMENTWIDTH . ISLEFTSHIFT is for determine left or right shift , because they have different limitations .


<s> static rtx mmix_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , MMIX_STRUCT_VALUE_REGNUM ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> const ARM64Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool SystemZInstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * AA ) const { if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) return false ; MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; unsigned LA = std :: max ( unsigned ( PostAlign ) , LogAlign ) ; if ( ! LA ) return PO ; return WorstCaseAlign ( PO , LA , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s> bool isIncomingArgumentHandler ( ) const override { return true ; } </s>

Returns true if the handler is dealing with incoming arguments , i.e .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARM64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & ARM64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & ARM64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & ARM64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & ARM64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & ARM64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & ARM64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM64 :: NZCV ) , & ARM64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ 2 ] , & Constraint [ Size - 1 ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= 0 && RegNo <= 31 ) { Res . first = ARM64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & ARM64 :: FPR128RegClass ; } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; unsigned NumCopies = 0 ; SDNode * Copies [ 2 ] = { 0 , 0 } ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == ISD :: CopyToReg ) { Copies [ NumCopies ++ ] = Use ; } else if ( Use -> getOpcode ( ) == ARMISD :: VMOVRRD ) { for ( SDNode :: use_iterator UI = Use -> use_begin ( ) , UE = Use -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies [ UI . getUse ( ) . getResNo ( ) ] = * UI ; ++ NumCopies ; } } else if ( Use -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Use -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Use = * Use -> use_begin ( ) ; if ( Use -> getOpcode ( ) != ISD :: CopyToReg || ! Use -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Copies [ NumCopies ++ ] = Use ; } else { return false ; } if ( NumCopies != 1 && NumCopies != 2 ) return false ; bool HasRet = false ; for ( unsigned i = 0 ; i < NumCopies ; ++ i ) { SDNode * Copy = Copies [ i ] ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == ISD :: CopyToReg ) { SDNode * Use = * UI ; if ( Use == Copies [ 0 ] || ( ( NumCopies == 2 ) && ( Use == Copies [ 1 ] ) ) ) continue ; return false ; } if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG ) return false ; HasRet = true ; } } return HasRet ; } </s>

Return true if result of the specified node is used by a return node only .


<s> static bool xstormy16_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total ) { switch ( code ) { case CONST_INT : if ( INTVAL ( x ) < 16 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) / 2 ; else if ( INTVAL ( x ) < 256 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( 2 ) ; return true ; case MULT : * total = COSTS_N_INSNS ( 35 + 6 ) ; return true ; case DIV : * total = COSTS_N_INSNS ( 51 - 6 ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_cpu_index
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_tune_index
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
if
(
!
(
rs6000_default_cpu
&&
rs6000_default_cpu
[
0
]
)
&&
!
global_options_set
.
x_rs6000_cpu_index
)
{
fputs
(
"\t.machine "
,
asm_out_file
)
;
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MODULO
)
!=
0
)
fputs
(
"power9\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
fputs
(
"power8\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
fputs
(
"power7\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_CMPB
)
!=
0
)
fputs
(
"power6\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
fputs
(
"power5\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MFCRF
)
!=
0
)
fputs
(
"power4\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
fputs
(
"ppc64\n"
,
asm_out_file
)
;
else
fputs
(
"ppc\n"
,
asm_out_file
)
;
}
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
}
</s>

Do anything needed at the start of the asm file .


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . isX32 ( ) || TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


Generate compact unwind encoding for the function based on the CFI instructions .


<s> MipsCCState :: SpecialCallingConvType MipsCCState :: getSpecialCallingConvForCallee ( const SDNode * Callee , const MipsSubtarget & Subtarget ) { MipsCCState :: SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv ; if ( Subtarget . inMips16HardFloat ( ) ) { if ( const GlobalAddressSDNode * G = dyn_cast < const GlobalAddressSDNode > ( Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) -> getParent ( ) -> getFunction ( Sym ) ; if ( F && F -> hasFnAttribute ( "__Mips16RetHelper" ) ) { SpecialCallingConv = Mips16RetHelperConv ; } } } return SpecialCallingConv ; } </s>

Determine the SpecialCallingConvType for the given callee .

Mips Mips Mips Mips Mips Mips "__Mips16RetHelper" Mips


<s> enum reg_class vfp_secondary_reload_class ( enum machine_mode mode , rtx x ) { if ( arm_coproc_mem_operand ( x , FALSE ) || s_register_operand ( x , mode ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return GENERAL_REGS if a scratch register required to reload x to/from VFP registers . Otherwise return NO_REGS .


<s> static inline int addsubcosts ( rtx x ) { if ( GET_MODE ( x ) == SImode ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( op0 ) == AND && XEXP ( op0 , 1 ) == const1_rtx && ( GET_CODE ( op1 ) == PLUS || ( GET_CODE ( op1 ) == MULT && XEXP ( op1 , 1 ) == const2_rtx ) ) ) return 1 ; if ( GET_CODE ( op0 ) == MULT && XEXP ( op0 , 1 ) == const2_rtx && GET_CODE ( op1 ) == LSHIFTRT && CONST_INT_P ( XEXP ( op1 , 1 ) ) && INTVAL ( XEXP ( op1 , 1 ) ) == 31 ) return 1 ; } if ( treg_set_expr ( op1 , SImode ) ) return 1 ; if ( treg_set_expr ( op0 , SImode ) ) return 1 ; } const int cost_scale = ! TARGET_SHMEDIA && GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( REG_P ( XEXP ( x , 1 ) ) || GET_CODE ( XEXP ( x , 1 ) ) == SUBREG ) return 1 * cost_scale ; if ( CONST_INT_P ( XEXP ( x , 1 ) ) && CONST_OK_FOR_ADD ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 1 * cost_scale ; if ( TARGET_SHMEDIA ) switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST : case LABEL_REF : case SYMBOL_REF : return TARGET_SHMEDIA64 ? 5 : 3 ; case CONST_INT : if ( CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) ) ) return 2 ; else if ( CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , 1 ) ) >> 16 ) ) return 3 ; else if ( CONST_OK_FOR_I16 ( ( INTVAL ( XEXP ( x , 1 ) ) >> 16 ) >> 16 ) ) return 4 ; default : return 5 ; } return 3 * cost_scale ; } </s>

Return the cost of an addition or a subtraction .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( i * 2 + odd ) & mask ; if ( d -> perm [ i ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) x = out0 , out0 = out1 , out1 = x ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> static bool ix86_lea_outperforms ( rtx_insn * insn , unsigned int regno0 , unsigned int regno1 , unsigned int regno2 , int split_cost , bool has_scale ) { int dist_define , dist_use ; if ( TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS || TARGET_TREMONT || TARGET_INTEL ) { if ( has_scale ) return true ; if ( split_cost < 1 ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ; dist_use = distance_agu_use ( regno0 , insn ) ; if ( dist_define < 0 || dist_define >= LEA_MAX_STALL ) { if ( dist_use < 0 && split_cost == 0 ) return TARGET_64BIT || IX86_LEA_PRIORITY ; else return true ; } dist_define += split_cost + IX86_LEA_PRIORITY ; if ( dist_use < 0 ) return dist_define > LEA_MAX_STALL ; return dist_define >= dist_use ; } </s>

Return true if usage of lea INSN has performance advantage over a sequence of instructions . Instructions sequence has SPLIT_COST cycles higher latency than lea latency .


<s>
static
void
ia64_sched_finish
(
FILE
*
dump
,
int
sched_verbose
)
{
if
(
sched_verbose
)
fprintf
(
dump
,
"// Finishing schedule.\n"
)
;
if
(
!
reload_completed
)
return
;
if
(
reload_completed
)
{
final_emit_insn_group_barriers
(
dump
)
;
bundling
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
if
(
sched_verbose
&&
dump
)
fprintf
(
dump
,
"//    finishing %d-%d\n"
,
INSN_UID
(
NEXT_INSN
(
current_sched_info
->
prev_head
)
)
,
INSN_UID
(
PREV_INSN
(
current_sched_info
->
next_tail
)
)
)
;
return
;
}
}
</s>

Free data allocated by ia64_sched_init .

ia64
"// Finishing schedule.\n"
"//    finishing %d-%d\n"


<s> unsigned LanaiInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == Lanai :: LDW_RI ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> Register CSKYTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return CSKY :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) { initAsmInfo ( ) ; } </s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> MipsSubtarget & MipsSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine * TM ) { std :: string CPUName = selectMipsCPU ( TargetTriple , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( InMips16Mode && ! TM -> Options . UseSoftFloat ) { TM -> Options . UseSoftFloat = true ; TM -> Options . FloatABIType = FloatABI :: Soft ; InMips16HardFloat = true ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Lower AMX intrinsics"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool expand_vec_perm_vperm2f128_vblend ( struct expand_vec_perm_d * d ) { struct expand_vec_perm_d dfirst , dsecond ; unsigned i , j , msk , nelt = d -> nelt , nelt2 = nelt / 2 ; rtx_insn * seq ; bool ok ; rtx ( * blend ) ( rtx , rtx , rtx , rtx ) = NULL ; if ( ! TARGET_AVX || TARGET_AVX2 || ( d -> vmode != V8SFmode && d -> vmode != V4DFmode ) || ! d -> one_operand_p ) return false ; dfirst = * d ; for ( i = 0 ; i < nelt ; i ++ ) dfirst . perm [ i ] = 0xff ; for ( i = 0 , msk = 0 ; i < nelt ; i ++ ) { j = ( d -> perm [ i ] & nelt2 ) ? i | nelt2 : i & ~ nelt2 ; if ( dfirst . perm [ j ] != 0xff && dfirst . perm [ j ] != d -> perm [ i ] ) return false ; dfirst . perm [ j ] = d -> perm [ i ] ; if ( j != i ) msk |= ( 1 << i ) ; } for ( i = 0 ; i < nelt ; i ++ ) if ( dfirst . perm [ i ] == 0xff ) dfirst . perm [ i ] = i ; if ( ! d -> testing_p ) dfirst . target = gen_reg_rtx ( dfirst . vmode ) ; start_sequence ( ) ; ok = expand_vec_perm_1 ( & dfirst ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; if ( d -> testing_p ) return true ; emit_insn ( seq ) ; dsecond = * d ; dsecond . op0 = dfirst . target ; dsecond . op1 = dfirst . target ; dsecond . one_operand_p = true ; dsecond . target = gen_reg_rtx ( dsecond . vmode ) ; for ( i = 0 ; i < nelt ; i ++ ) dsecond . perm [ i ] = i ^ nelt2 ; ok = expand_vec_perm_1 ( & dsecond ) ; gcc_assert ( ok ) ; blend = d -> vmode == V8SFmode ? gen_avx_blendps256 : gen_avx_blendpd256 ; emit_insn ( blend ( d -> target , dfirst . target , dsecond . target , GEN_INT ( msk ) ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement a single vector permutation using a single intra-lane vector permutation , vperm2f128 swapping the lanes and vblend * insn blending the non-swapped and swapped vectors together .