<s> bool LEGInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case LEG :: MOVi32 : { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; const unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; const bool DstIsDead = MI -> getOperand ( 0 ) . isDead ( ) ; const MachineOperand & MO = MI -> getOperand ( 1 ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( LEG :: MOVLOi16 ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( LEG :: MOVHIi16 ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm & 0xffff ; const unsigned Hi16 = ( Imm >> 16 ) & 0xffff ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | LEGII :: MO_LO16 ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | LEGII :: MO_HI16 ) ; } MBB . erase ( MI ) ; return true ; } } } </s>


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : case ARM :: VSTR_P0_off : case ARM :: MVE_VSTRWU32 : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64 : case ARM :: VST1d64TPseudo : case ARM :: VST1d64QPseudo : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static const char * elf_platform ( void ) { int fd ; fd = open ( "/proc/self/auxv" , O_RDONLY ) ; if ( fd != - 1 ) { char buf [ 1024 ] ; ElfW ( auxv_t ) * av ; ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd ) ; if ( n > 0 ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_PLATFORM : return ( const char * ) av -> a_un . a_val ; default : break ; } } } </s>

Returns the canonical AT_PLATFORM if present , otherwise NULL .


<s> static bool aarch64_function_value_regno_p ( const unsigned int regno ) { if ( regno == R0_REGNUM || regno == R1_REGNUM ) return true ; if ( regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS ) return ! TARGET_GENERAL_REGS_ONLY ; return false ; } </s>

Implements TARGET_FUNCTION_VALUE_REGNO_P . Return true if REGNO is the number of a hard register in which the values of called function may come back .


<s>
MCOperand
SystemZMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
MCOperand
(
)
;
return
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
case
MachineOperand
::
MO_Immediate
:
return
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
case
MachineOperand
::
MO_MachineBasicBlock
:
return
lowerSymbolOperand
(
MO
,
MO
.
getMBB
(
)
->
getSymbol
(
)
,
0
)
;
case
MachineOperand
::
MO_GlobalAddress
:
return
lowerSymbolOperand
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
MO
.
getOffset
(
)
)
;
case
MachineOperand
::
MO_ExternalSymbol
:
{
StringRef
Name
=
MO
.
getSymbolName
(
)
;
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetExternalSymbolSymbol
(
Name
)
,
MO
.
getOffset
(
)
)
;
}
case
MachineOperand
::
MO_JumpTableIndex
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
,
0
)
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
,
MO
.
getOffset
(
)
)
;
case
MachineOperand
::
MO_BlockAddress
:
{
const
BlockAddress
*
BA
=
MO
.
getBlockAddress
(
)
;
return
lowerSymbolOperand
(
MO
,
AsmPrinter
.
GetBlockAddressSymbol
(
BA
)
,
MO
.
getOffset
(
)
)
;
}
}
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> int64_t getOffset ( ) const { return Offset ; } </s>

Get the offest of a string in the string table .


<s> SDValue PPCTargetLowering :: getSqrtInputTest ( SDValue Op , SelectionDAG & DAG , const DenormalMode & Mode ) const { EVT VT = Op . getValueType ( ) ; if ( ! isTypeLegal ( MVT :: i1 ) || ( VT != MVT :: f64 && ( ( VT != MVT :: v2f64 && VT != MVT :: v4f32 ) || ! Subtarget . hasVSX ( ) ) ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue FTSQRT = DAG . getNode ( PPCISD :: FTSQRT , DL , MVT :: i32 , Op ) ; SDValue SRIdxVal = DAG . getTargetConstant ( PPC :: sub_eq , DL , MVT :: i32 ) ; return SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , MVT :: i1 , FTSQRT , SRIdxVal ) , 0 ) ; } </s>

Return a target-dependent comparison result if the input operand is suitable for use with a square root estimate calculation .


<s> const ARMSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool is_load_insn1 ( rtx pat , rtx * load_mem ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) return find_mem_ref ( SET_SRC ( pat ) , load_mem ) ; if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_load_insn1 ( XVECEXP ( pat , 0 , i ) , load_mem ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a load insn .


<s> bool sh_cfun_interrupt_handler_p ( void ) { return ( lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) ; } </s>

Returns true if the current function has the `` interrupt_handler '' attribute set .


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > 4 ) mem_count += 2 ; else mem_count += 1 ; } free ( bbs ) ; if ( mem_count && mem_count <= 32 ) return MIN ( nunroll , 32 / mem_count ) ; return nunroll ; } </s>

This function adjusts the unroll factor based on the hardware capabilities . For ex , bdver3 has a loop buffer which makes unrolling of smaller loops less important . This function decides the unroll factor using number of memory references ( value 32 is used ) as a heuristic .


<s> bool useMachineCombiner ( ) const override { return true ; } </s>

Return true when a target supports MachineCombiner .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static tree arm_d_handle_target_float_abi ( void ) { const char * abi ; switch ( arm_float_abi ) { case ARM_FLOAT_ABI_HARD : abi = "hard" ; break ; case ARM_FLOAT_ABI_SOFT : abi = "soft" ; break ; case ARM_FLOAT_ABI_SOFTFP : abi = "softfp" ; break ; default : abi = "" ; break ; } return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; Register SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; Register SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; Register DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * LdMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , * LdMI , * LdMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int ia64_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = ia64_function_arg_words ( type , mode ) ; int offset = ia64_function_arg_offset ( cum , type , words ) ; if ( cum -> words + offset >= MAX_ARGUMENT_SLOTS ) return 0 ; if ( words + cum -> words + offset <= MAX_ARGUMENT_SLOTS ) return 0 ; return ( MAX_ARGUMENT_SLOTS - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

Return number of bytes , at the beginning of the argument , that must be put in registers . 0 is the argument is entirely in registers or entirely in memory .


<s> const TargetRegisterClass * X86InstructionSelector :: getRegClass ( LLT Ty , unsigned Reg , MachineRegisterInfo & MRI ) const { const RegisterBank & RegBank = * RBI . getRegBank ( Reg , MRI , TRI ) ; return getRegClass ( Ty , RegBank ) ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> unsigned AArch64InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: LDRWui : case AArch64 :: LDRXui : case AArch64 :: LDRBui : case AArch64 :: LDRHui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static unsigned int insn_is_swap_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET ) return 0 ; rtx rhs = SET_SRC ( body ) ; if ( pattern_is_rotate64 ( body ) ) return 1 ; if ( GET_CODE ( rhs ) != VEC_SELECT ) return 0 ; rtx parallel = XEXP ( rhs , 1 ) ; if ( GET_CODE ( parallel ) != PARALLEL ) return 0 ; unsigned int len = XVECLEN ( parallel , 0 ) ; if ( len != 2 && len != 4 && len != 8 && len != 16 ) return 0 ; for ( unsigned int i = 0 ; i < len / 2 ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( ! CONST_INT_P ( op ) || INTVAL ( op ) != len / 2 + i ) return 0 ; } for ( unsigned int i = len / 2 ; i < len ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( ! CONST_INT_P ( op ) || INTVAL ( op ) != i - len / 2 ) return 0 ; } return 1 ; } </s>

Return 1 iff INSN swaps doublewords . This may be a reg-reg swap , a permuting load , or a permuting store .


<s> static bool rs6000_reg_live_or_pic_offset_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ; } return ( ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) ) && ! call_used_regs [ reg ] ) ; } </s>

Determine whether the gp REG is really used .


<s> int arm_apply_result_size ( void ) { int size = 16 ; if ( TARGET_ARM ) { if ( TARGET_HARD_FLOAT_ABI ) { if ( TARGET_FPA ) size += 12 ; if ( TARGET_MAVERICK ) size += 8 ; } if ( TARGET_IWMMXT_ABI ) size += 8 ; } return size ; } </s>

Determine the amount of memory needed to store the possible return registers of an untyped call .


<s> bool SparcAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static enum aarch64_parse_opt_result aarch64_parse_arch ( const char * to_parse , const struct processor * * res , unsigned long * isa_flags ) { char * ext ; const struct processor * arch ; char * str = ( char * ) alloca ( strlen ( to_parse ) + 1 ) ; size_t len ; strcpy ( str , to_parse ) ; ext = strchr ( str , '+' ) ; if ( ext != NULL ) len = ext - str ; else len = strlen ( str ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( arch = all_architectures ; arch -> name != NULL ; arch ++ ) { if ( strlen ( arch -> name ) == len && strncmp ( arch -> name , str , len ) == 0 ) { unsigned long isa_temp = arch -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = arch ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the architecture struct that it selects into RES and the architectural features into ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> unsigned DCPU16InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == DCPU16 :: MOV16mr ) { if ( MI -> getOperand ( 0 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void mips_declare_object ( FILE * stream , const char * name , const char * init_string , const char * final_string , ... ) { va_list ap ; fputs ( init_string , stream ) ; assemble_name ( stream , name ) ; va_start ( ap , final_string ) ; vfprintf ( stream , final_string , ap ) ; va_end ( ap ) ; if ( ! TARGET_EXPLICIT_RELOCS ) { tree name_tree = get_identifier ( name ) ; TREE_ASM_WRITTEN ( name_tree ) = 1 ; } } </s>

Emit either a label , .comm , or .lcomm directive . When using assembler macros , mark the symbol as written so that mips_file_end wo n't emit an .extern for it . STREAM is the output file , NAME is the name of the symbol , INIT_STRING is the string that should be written before the symbol and FINAL_STRING is the string that should be written after it . FINAL_STRING is a printf ( ) format that consumes the remaining arguments .


<s> static bool note_csky_invalid_constants ( rtx_insn * insn , HOST_WIDE_INT address , int do_pushes ) { bool result = false ; int opno ; extract_constrain_insn ( insn ) ; if ( recog_data . n_alternatives == 0 ) return false ; preprocess_constraints ( insn ) ; const operand_alternative * op_alt = which_op_alt ( ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] != OP_IN ) continue ; if ( op_alt [ opno ] . memory_ok ) { rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_csky_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , op ) ; result = true ; } } } return result ; } </s>

Scan INSN and note any of its operands that need fixing . If DO_PUSHES is false we do not actually push any of the fixups needed . The function returns TRUE if any fixups were needed/pushed .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == 64 ) { cmp_mode = mode_for_size ( GET_MODE_NUNITS ( cmp_ops_mode ) , MODE_INT , 0 ) ; gcc_assert ( cmp_mode != BLKmode ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


<s> unsigned AArch64InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return 2 ; case AArch64 :: LDPXi : case AArch64 :: LDPDi : case AArch64 :: STPXi : case AArch64 :: STPDi : case AArch64 :: LDNPXi : case AArch64 :: LDNPDi : case AArch64 :: STNPXi : case AArch64 :: STNPDi : case AArch64 :: LDPQi : case AArch64 :: STPQi : case AArch64 :: LDNPQi : case AArch64 :: STNPQi : case AArch64 :: LDPWi : case AArch64 :: LDPSi : case AArch64 :: STPWi : case AArch64 :: STPSi : case AArch64 :: LDNPWi : case AArch64 :: LDNPSi : case AArch64 :: STNPWi : case AArch64 :: STNPSi : case AArch64 :: LDG : case AArch64 :: STGPi : return 3 ; case AArch64 :: ADDG : case AArch64 :: STGOffset : return 2 ; } } </s>

Returns the index for the immediate for a given instruction .


<s> void function_expander :: add_mem_operand ( machine_mode mode , rtx addr ) { gcc_assert ( VECTOR_MODE_P ( mode ) || mode == OImode ) ; rtx mem = gen_rtx_MEM ( mode , memory_address ( mode , addr ) ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( GET_MODE_INNER ( mode ) ) ) ; add_fixed_operand ( mem ) ; } </s>

Add a memory operand with mode MODE and address ADDR .


More limited version of SimplifyDemandedBits that can be used to `` look through '' ops that do n't contribute to the DemandedBits/DemandedElts - bitwise ops etc .


<s> bool X86TargetLowering :: isGAPlusOffset ( SDNode * N , const GlobalValue * & GA , int64_t & Offset ) const { if ( N -> getOpcode ( ) == X86ISD :: Wrapper ) { if ( isa < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) ) { GA = cast < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) -> getGlobal ( ) ; Offset = cast < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) -> getOffset ( ) ; return true ; } } return TargetLowering :: isGAPlusOffset ( N , GA , Offset ) ; } </s>

Returns true ( and the GlobalValue and the offset ) if the node is a GlobalAddress + offset .


<s> static bool ix86_in_large_data_p ( tree exp ) { if ( ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC ) return false ; if ( exp == NULL_TREE ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( VAR_P ( exp ) && ! is_global_var ( exp ) ) return false ; if ( VAR_P ( exp ) && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , ".ldata" ) == 0 || strcmp ( section , ".lbss" ) == 0 ) return true ; return false ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( size <= 0 || size > ix86_section_threshold ) return true ; } return false ; } </s>

Return true if this goes in small data/bss .


<s> SDValue MergeValues ( ArrayRef < SDValue > Values ) { return DAG -> getMergeValues ( Values , dl ) ; } </s>

MergeValues - Compute and return the merge of the two specified lattice values .


<s> MCContext & getContext ( ) const { return Streamer . getContext ( ) ; } </s>

Return the LLVMContext used by the analysis .


<s> bool SystemZXPLINKFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; unsigned LowGPR = 0 ; int LowOffset = INT32_MAX ; unsigned HighGPR = LowGPR ; int HighOffset = - 1 ; unsigned RegSP = Regs . getStackPointerRegister ( ) ; auto & GRRegClass = SystemZ :: GR64BitRegClass ; const unsigned RegSize = 8 ; auto ProcessCSI = [ & ] ( std :: vector < CalleeSavedInfo > & CSIList ) { for ( auto & CS : CSIList ) { Register Reg = CS . getReg ( ) ; int Offset = RegSpillOffsets [ Reg ] ; if ( Offset >= 0 ) { if ( GRRegClass . contains ( Reg ) ) { if ( LowOffset > Offset ) { LowOffset = Offset ; LowGPR = Reg ; } if ( Offset > HighOffset ) { HighOffset = Offset ; HighGPR = Reg ; } } int FrameIdx = MFFrame . CreateFixedSpillStackObject ( RegSize , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } } ; std :: vector < CalleeSavedInfo > Spills ; Spills . push_back ( CalleeSavedInfo ( Regs . getAddressOfCalleeRegister ( ) ) ) ; if ( hasFP ( MF ) || MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ) Spills . push_back ( CalleeSavedInfo ( RegSP ) ) ; ProcessCSI ( CSI ) ; MFI -> setRestoreGPRRegs ( LowGPR , HighGPR , LowOffset ) ; ProcessCSI ( Spills ) ; MFI -> setSpillGPRRegs ( LowGPR , HighGPR , LowOffset ) ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ; int FrameIdx = MFFrame . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; auto mi = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; addFrameReference ( mi , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool ix86_hardreg_mov_ok ( rtx dst , rtx src ) { if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ! REG_P ( src ) && ! MEM_P ( src ) && ! ( VECTOR_MODE_P ( GET_MODE ( dst ) ) ? standard_sse_constant_p ( src , GET_MODE ( dst ) ) : x86_64_immediate_operand ( src , GET_MODE ( dst ) ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) && ! reload_completed ) return false ; return true ; } </s>

Return true if a set of DST by the expression SRC should be allowed . This prevents complex sets of likely_spilled hard regs before reload .


<s> const char * pa_output_mul_insn ( int unsignedp ATTRIBUTE_UNUSED , rtx_insn * insn ) { import_milli ( mulI ) ; return pa_output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( Pmode , "$$mulI" ) ) ; } </s>

The register constraints have put the operands and return value in the proper registers .


<s> static void mips_emit_loadgp ( void ) { rtx addr , offset , incoming_address , base , index , pic_reg ; pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx ; switch ( mips_current_loadgp_style ( ) ) { case LOADGP_ABSOLUTE : if ( mips_gnu_local_gp == NULL ) { mips_gnu_local_gp = gen_rtx_SYMBOL_REF ( Pmode , "__gnu_local_gp" ) ; SYMBOL_REF_FLAGS ( mips_gnu_local_gp ) |= SYMBOL_FLAG_LOCAL ; } emit_insn ( PMODE_INSN ( gen_loadgp_absolute , ( pic_reg , mips_gnu_local_gp ) ) ) ; break ; case LOADGP_OLDABI : break ; case LOADGP_NEWABI : addr = XEXP ( DECL_RTL ( current_function_decl ) , 0 ) ; offset = mips_unspec_address ( addr , SYMBOL_GOTOFF_LOADGP ) ; incoming_address = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; emit_insn ( PMODE_INSN ( gen_loadgp_newabi , ( pic_reg , offset , incoming_address ) ) ) ; break ; case LOADGP_RTP : base = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( VXWORKS_GOTT_BASE ) ) ; index = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( VXWORKS_GOTT_INDEX ) ) ; emit_insn ( PMODE_INSN ( gen_loadgp_rtp , ( pic_reg , base , index ) ) ) ; break ; default : return ; } if ( TARGET_MIPS16 ) emit_insn ( PMODE_INSN ( gen_copygp_mips16 , ( pic_offset_table_rtx , pic_reg ) ) ) ; if ( ! TARGET_EXPLICIT_RELOCS || crtl -> profile ) emit_insn ( gen_loadgp_blockage ( ) ) ; } </s>

If we 're generating n32 or n64 abicalls , emit instructions to set up the global pointer .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
MBBI
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Cannot deal with nonzero SPAdj yet"
)
;
MachineInstr
&
MI
=
*
MBBI
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
static_cast
<
const
AArch64FrameLowering
*
>
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
int
MinCSFI
=
0
;
int
MaxCSFI
=
1
;
if
(
CSI
.
size
(
)
)
{
MinCSFI
=
CSI
[
0
]
.
getFrameIdx
(
)
;
MaxCSFI
=
CSI
[
CSI
.
size
(
)
1
]
.
getFrameIdx
(
)
;
}
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
bool
IsCalleeSaveOp
=
FrameIndex
>=
MinCSFI
&&
FrameIndex
<=
MaxCSFI
;
unsigned
FrameReg
;
int64_t
Offset
;
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
SPAdj
,
IsCalleeSaveOp
)
;
bool
HasOffsetOp
=
hasFrameOffset
(
MI
.
getOpcode
(
)
)
;
if
(
HasOffsetOp
)
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
if
(
MI
.
isDebugValue
(
)
)
{
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
const
AArch64InstrInfo
&
TII
=
*
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
int
MinOffset
,
MaxOffset
,
OffsetScale
;
if
(
MI
.
getOpcode
(
)
==
AArch64
::
ADDxxi_lsl0_s
||
!
HasOffsetOp
)
{
MinOffset
=
0
;
MaxOffset
=
0xfff
;
OffsetScale
=
1
;
}
else
{
TII
.
getAddressConstraints
(
MI
,
OffsetScale
,
MinOffset
,
MaxOffset
)
;
}
if
(
(
Offset
%
OffsetScale
!=
0
||
Offset
<
MinOffset
||
Offset
>
MaxOffset
)
||
(
!
HasOffsetOp
&&
Offset
!=
0
)
)
{
unsigned
BaseReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitRegUpdate
(
MBB
,
MBBI
,
MBBI
->
getDebugLoc
(
)
,
TII
,
BaseReg
,
FrameReg
,
BaseReg
,
Offset
)
;
FrameReg
=
BaseReg
;
Offset
=
0
;
}
assert
(
Offset
>=
0
&&
"Unexpected negative offset from SP"
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
,
false
,
true
)
;
if
(
HasOffsetOp
)
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
/
OffsetScale
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int rs6000_hard_regno_mode_ok_uncached ( int regno , machine_mode mode ) { int last_regno = regno + rs6000_hard_regno_nregs [ mode ] [ regno ] - 1 ; if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == OOmode ) return ( TARGET_MMA && VSX_REGNO_P ( regno ) && ( regno & 1 ) == 0 ) ; if ( mode == XOmode ) return ( TARGET_MMA && FP_REGNO_P ( regno ) && ( regno & 3 ) == 0 ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & 1 ) == 0 ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || mode == TImode || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) < 16 && ! reg_addr [ mode ] . scalar_in_vmx_p ) return 0 ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( VECTOR_ALIGNMENT_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % 2 ) == 0 ) && FP_REGNO_P ( last_regno ) ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return 1 ; if ( TARGET_P8_VECTOR && ( mode == SImode ) ) return 1 ; if ( TARGET_P9_VECTOR && ( mode == QImode || mode == HImode ) ) return 1 ; } return 0 ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != MVT :: v4f64 && VT != MVT :: v4f32 ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , false ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , true ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


"  group = %s, path = %d, byte_len = %d\n"

"  num_imm = %d, num_imm_32 = %d, num_imm_64 = %d, imm_size = %d\n"

Print INSN dispatch information to FILE .


<s> void ix86_expand_convert_uns_sisf_sse ( rtx target , rtx input ) { REAL_VALUE_TYPE ONE16r ; rtx fp_hi , fp_lo , int_hi , int_lo , x ; real_ldexp ( & ONE16r , & dconst1 , 16 ) ; x = const_double_from_real_value ( ONE16r , SFmode ) ; int_lo = expand_simple_binop ( SImode , AND , input , GEN_INT ( 0xffff ) , NULL , 0 , OPTAB_DIRECT ) ; int_hi = expand_simple_binop ( SImode , LSHIFTRT , input , GEN_INT ( 16 ) , NULL , 0 , OPTAB_DIRECT ) ; fp_hi = gen_reg_rtx ( SFmode ) ; fp_lo = gen_reg_rtx ( SFmode ) ; emit_insn ( gen_floatsisf2 ( fp_hi , int_hi ) ) ; emit_insn ( gen_floatsisf2 ( fp_lo , int_lo ) ) ; if ( TARGET_FMA ) { x = validize_mem ( force_const_mem ( SFmode , x ) ) ; fp_hi = gen_rtx_FMA ( SFmode , fp_hi , x , fp_lo ) ; emit_move_insn ( target , fp_hi ) ; } else { fp_hi = expand_simple_binop ( SFmode , MULT , fp_hi , x , fp_hi , 0 , OPTAB_DIRECT ) ; fp_hi = expand_simple_binop ( SFmode , PLUS , fp_hi , fp_lo , target , 0 , OPTAB_DIRECT ) ; if ( ! rtx_equal_p ( target , fp_hi ) ) emit_move_insn ( target , fp_hi ) ; } } </s>

Convert an unsigned SImode value into a SFmode , using only SSE . For x86_32 , -mfpmath=sse , ! optimize_size only .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


"extended registers have no high halves"

"unsupported operand size for extended register"


<s> static bool expand_vec_perm_interleave3 ( struct expand_vec_perm_d * d ) { unsigned i , nelt ; rtx ( * gen ) ( rtx , rtx , rtx ) ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( d -> vmode ) == 32 ) ; else if ( TARGET_AVX && ( d -> vmode == V8SFmode || d -> vmode == V4DFmode ) ) ; else return false ; nelt = d -> nelt ; if ( d -> perm [ 0 ] != 0 && d -> perm [ 0 ] != nelt / 2 ) return false ; for ( i = 0 ; i < nelt ; i += 2 ) if ( d -> perm [ i ] != d -> perm [ 0 ] + i / 2 || d -> perm [ i + 1 ] != d -> perm [ 0 ] + i / 2 + nelt ) return false ; if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V32QImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv32qi ; else gen = gen_vec_interleave_lowv32qi ; break ; case E_V16HImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv16hi ; else gen = gen_vec_interleave_lowv16hi ; break ; case E_V8SImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv8si ; else gen = gen_vec_interleave_lowv8si ; break ; case E_V4DImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv4di ; else gen = gen_vec_interleave_lowv4di ; break ; case E_V8SFmode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv8sf ; else gen = gen_vec_interleave_lowv8sf ; break ; case E_V4DFmode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv4df ; else gen = gen_vec_interleave_lowv4df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( d -> target , d -> op0 , d -> op1 ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to simplify a two vector permutation using 2 intra-lane interleave insns and cross-lane shuffle for 32-byte vectors .


<s> bool n7_consumed_by_ii_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_STORE : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at II .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
PrintOperand
(
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
case
'V'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'x'
:
case
't'
:
case
'g'
:
if
(
MO
.
isReg
(
)
)
return
printAsmVRegister
(
MO
,
ExtraCode
[
0
]
,
O
)
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
PrintPCRelImm
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const CJGInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static bool pa_callee_copies ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { return ! TARGET_CALLER_COPIES ; } </s>

Implement TARGET_CALLEE_COPIES . The callee is responsible for copying arguments passed by hidden reference in the 32-bit HP runtime . Users can override this behavior for better compatibility with openmp at the risk of library incompatibilities . Arguments are always passed by value in the 64-bit HP runtime .


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> static bool ia64_expand_vecint_compare ( enum rtx_code code , machine_mode mode , rtx dest , rtx op0 , rtx op1 ) { bool negate = false ; rtx x ; switch ( code ) { case EQ : case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = op0 , op0 = op1 , op1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V2SImode : { rtx t1 , t2 , mask ; mask = GEN_INT ( 0x80000000 ) ; mask = gen_rtx_CONST_VECTOR ( V2SImode , gen_rtvec ( 2 , mask , mask ) ) ; mask = force_reg ( mode , mask ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t1 , op0 , mask ) ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t2 , op1 , mask ) ) ; op0 = t1 ; op1 = t2 ; code = GT ; } break ; case V8QImode : case V4HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_US_MINUS ( mode , op0 , op1 ) ) ) ; code = EQ ; op0 = x ; op1 = CONST0_RTX ( mode ) ; negate = ! negate ; break ; default : gcc_unreachable ( ) ; } } x = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; return negate ; } </s>

Generate an integral vector comparison . Return true if the condition has been reversed , and so the sense of the comparison should be inverted .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> unsigned Cpu0SEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , const DebugLoc & DL , unsigned * NewImm ) const { Cpu0AnalyzeImmediate AnalyzeImm ; unsigned Size = 32 ; unsigned LUi = Cpu0 :: LUi ; unsigned ZEROReg = Cpu0 :: ZERO ; unsigned ATReg = Cpu0 :: AT ; bool LastInstrIsADDiu = NewImm ; const Cpu0AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; Cpu0AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , ATReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return ATReg ; } </s>

Emit a series of instructions to load an immediate .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } if ( STI . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s> bool ARM64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createARM64DeadRegisterDefinitions ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> const uint16_t * OR1KRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ; } </s>


<s> static void csky_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem , a_tramp ; int pool = TRAMPOLINE_SIZE - 8 ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , pool ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , pool + 4 ) ; emit_move_insn ( mem , fnaddr ) ; a_tramp = XEXP ( m_tramp , 0 ) ; maybe_emit_call_builtin___clear_cache ( a_tramp , plus_constant ( Pmode , a_tramp , TRAMPOLINE_SIZE ) ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SystemZ Instruction Shortening"
;
}
</s>

getPassName - Return a nice clean name for a pass .

SystemZ
"SystemZ Instruction Shortening"


"call to %qE is ambiguous; argument %d has type"

Argument FIRST_ARGNO is a scalar with type EXPECTED_TYPE , and argument ARGNO should be consistent with it . Return true if it is , otherwise report an appropriate error .


<s> const LegalizerInfo * X86Subtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> static int vax_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return COSTS_N_INSNS ( 1 + ( REG_P ( x ) ? 0 : vax_address_cost_1 ( x ) ) ) ; } </s>

Return the cost in cycles of a memory address , relative to register indirect . Each of the following adds the indicated number of cycles : 1 - symbolic address 1 - pre-decrement 1 - indexing and/or offset ( register ) 2 - indirect


<s> static void mips_expand_vi_broadcast ( machine_mode vmode , rtx target , rtx elt ) { struct expand_vec_perm_d d ; rtx t1 ; bool ok ; if ( elt != const0_rtx ) elt = force_reg ( GET_MODE_INNER ( vmode ) , elt ) ; if ( REG_P ( elt ) ) elt = gen_lowpart ( DImode , elt ) ; t1 = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case V8QImode : emit_insn ( gen_loongson_vec_init1_v8qi ( t1 , elt ) ) ; break ; case V4HImode : emit_insn ( gen_loongson_vec_init1_v4hi ( t1 , elt ) ) ; break ; default : gcc_unreachable ( ) ; } memset ( & d , 0 , sizeof ( d ) ) ; d . target = target ; d . op0 = t1 ; d . op1 = t1 ; d . vmode = vmode ; d . nelt = GET_MODE_NUNITS ( vmode ) ; d . one_vector_p = true ; ok = mips_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( ok ) ; } </s>

A subroutine of mips_expand_vec_init , expand via broadcast .


<s>
bool
MipsDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_R
:
case
InlineAsm
::
Constraint_ZC
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

Mips
Mips
"Unexpected asm memory constraint"


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilderBase & IRB ) const { if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( Subtarget . isTargetAndroid ( ) ) { int Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x18 , getAddressSpace ( ) ) ; } return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; unsigned opcode = MI . getOpcode ( ) ; uint16_t validDomains = 0 ; if ( domain ) { validDomains = getExecutionDomainCustom ( MI ) ; if ( validDomains ) return std :: make_pair ( domain , validDomains ) ; if ( lookup ( opcode , domain , ReplaceableInstrs ) ) { validDomains = 0xe ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; } else if ( lookup ( opcode , domain , ReplaceableInstrsFP ) ) { validDomains = 0x6 ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2InsertExtract ) ) { if ( ! Subtarget . hasAVX2 ( ) ) return std :: make_pair ( 0 , 0 ) ; validDomains = 0xe ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) && lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) ) { if ( const uint16_t * table = lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQMasked ) ) { if ( domain == 1 || ( domain == 3 && table [ 3 ] == opcode ) ) validDomains = 0xa ; else validDomains = 0xc ; } } } return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> bool n13_alu_e1_insn_dep_reg_p ( rtx_insn * alu_e1_insn , rtx def_reg ) { rtx unspec_rtx , operand_ra , operand_rb ; rtx src_rtx , dst_rtx ; switch ( INSN_CODE ( alu_e1_insn ) ) { case CODE_FOR_unspec_bsp : case CODE_FOR_unspec_bse : unspec_rtx = SET_SRC ( parallel_element ( alu_e1_insn , 0 ) ) ; gcc_assert ( GET_CODE ( unspec_rtx ) == UNSPEC ) ; operand_ra = XVECEXP ( unspec_rtx , 0 , 0 ) ; operand_rb = XVECEXP ( unspec_rtx , 0 , 1 ) ; if ( rtx_equal_p ( def_reg , operand_ra ) || rtx_equal_p ( def_reg , operand_rb ) ) return true ; return false ; case CODE_FOR_move_di : case CODE_FOR_move_df : src_rtx = SET_SRC ( PATTERN ( alu_e1_insn ) ) ; dst_rtx = SET_DEST ( PATTERN ( alu_e1_insn ) ) ; if ( REG_P ( dst_rtx ) && REG_P ( src_rtx ) && rtx_equal_p ( src_rtx , def_reg ) ) return true ; return false ; default : return false ; } } </s>

Check dependencies from any stages to ALU_E1 ( E1 ) . This is a helper function of n13_consumed_by_e1_dep_p ( ) .


<s> static tree make_resolver_func ( const tree default_decl , const tree dispatch_decl , basic_block * empty_bb ) { tree decl_name = clone_function_name ( default_decl , "resolver" ) ; const char * resolver_name = IDENTIFIER_POINTER ( decl_name ) ; tree type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; tree decl = build_fn_decl ( resolver_name , type ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 0 ; TREE_PUBLIC ( decl ) = 0 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( dispatch_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; tree t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; DECL_ATTRIBUTES ( dispatch_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( dispatch_decl ) ) ; cgraph_node :: create_same_body_alias ( dispatch_decl , decl ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


"Altivec is not implemented on AIX yet."

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> Optional < RegImmPair > ARMBaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , Register Reg ) const { int Sign = 1 ; unsigned Opcode = MI . getOpcode ( ) ; int64_t Offset = 0 ; const MachineOperand & Op0 = MI . getOperand ( 0 ) ; if ( ! Op0 . isReg ( ) || Reg != Op0 . getReg ( ) ) return None ; if ( Opcode == ARM :: SUBri ) Sign = - 1 ; else if ( Opcode != ARM :: ADDri ) return None ; if ( ! MI . getOperand ( 1 ) . isReg ( ) || ! MI . getOperand ( 2 ) . isImm ( ) ) return None ; Offset = MI . getOperand ( 2 ) . getImm ( ) * Sign ; return RegImmPair { MI . getOperand ( 1 ) . getReg ( ) , Offset } ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> static int try_issue_nops ( struct bundle_state * curr_state , int nops_num ) { int i ; for ( i = 0 ; i < nops_num ; i ++ ) if ( state_transition ( curr_state -> dfa_state , ia64_nop ) >= 0 ) { free_bundle_state ( curr_state ) ; return FALSE ; } return TRUE ; } </s>

The following function tries to issue NOPS_NUM nops for the current state without advancing processor cycle . If it failed , the function returns FALSE and frees the current state .


<s> static bool aarch64_macro_fusion_p ( void ) { return aarch64_tune_params -> fuseable_ops != AARCH64_FUSE_NOTHING ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_P . Return true if target supports instruction fusion of some sort .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool rs6000_vector_alignment_reachable ( const_tree type ATTRIBUTE_UNUSED , bool is_packed ) { if ( is_packed ) return false ; if ( TARGET_32BIT ) { if ( rs6000_alignment_flags == MASK_ALIGN_NATURAL ) return true ; if ( rs6000_alignment_flags == MASK_ALIGN_POWER ) return true ; return false ; } else { if ( TARGET_MACHO ) return false ; return true ; } } </s>

Return true iff , data reference of TYPE can reach vector alignment ( 16 ) after applying N number of iterations . This routine does not determine how may iterations are required to reach desired alignment .


<s> void FISCInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( CC == CallingConv :: CFGuard_Check ) return CSR_Win_AAPCS_CFGuard_Check_RegMask ; if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>


<s> bool SystemZInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const { if ( MBB . succ_empty ( ) && Probability < BranchProbability ( 1 , 8 ) ) return false ; return NumCycles == 1 ; } </s>


<s> static bool find_mem_ref ( rtx pat , rtx * mem_ref ) { const char * fmt ; int i , j ; if ( tie_operand ( pat , VOIDmode ) ) return false ; if ( GET_CODE ( pat ) == MEM ) { * mem_ref = pat ; return true ; } fmt = GET_RTX_FORMAT ( GET_CODE ( pat ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( pat ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( find_mem_ref ( XEXP ( pat , i ) , mem_ref ) ) return true ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( pat , i ) - 1 ; j >= 0 ; j -- ) { if ( find_mem_ref ( XVECEXP ( pat , i , j ) , mem_ref ) ) return true ; } } return false ; } </s>

Determine if PAT refers to memory . If so , set MEM_REF to the MEM rtx and return true .


<s>
static
void
pa_asm_trampoline_template
(
FILE
*
f
)
{
if
(
!
TARGET_64BIT
)
{
fputs
(
"\tldw	36(%r22),%r21\n"
,
f
)
;
fputs
(
"\tbb,>=,n	%r21,30,.+16\n"
,
f
)
;
if
(
ASSEMBLER_DIALECT
==
0
)
fputs
(
"\tdepi	0,31,2,%r21\n"
,
f
)
;
else
fputs
(
"\tdepwi	0,31,2,%r21\n"
,
f
)
;
fputs
(
"\tldw	4(%r21),%r19\n"
,
f
)
;
fputs
(
"\tldw	0(%r21),%r21\n"
,
f
)
;
if
(
TARGET_PA_20
)
{
fputs
(
"\tbve	(%r21)\n"
,
f
)
;
fputs
(
"\tldw	40(%r22),%r29\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
}
else
{
fputs
(
"\tldsid	(%r21),%r1\n"
,
f
)
;
fputs
(
"\tmtsp	%r1,%sr0\n"
,
f
)
;
fputs
(
"\tbe	0(%sr0,%r21)\n"
,
f
)
;
fputs
(
"\tldw	40(%r22),%r29\n"
,
f
)
;
}
fputs
(
"\t.word	0\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
fputs
(
"\t.word	0\n"
,
f
)
;
}
else
{
fputs
(
"\t.dword 0\n"
,
f
)
;
fputs
(
"\t.dword 0\n"
,
f
)
;
fputs
(
"\t.dword 0\n"
,
f
)
;
fputs
(
"\t.dword 0\n"
,
f
)
;
fputs
(
"\tmfia	%r31\n"
,
f
)
;
fputs
(
"\tldd	24(%r31),%r1\n"
,
f
)
;
fputs
(
"\tldd	24(%r1),%r27\n"
,
f
)
;
fputs
(
"\tldd	16(%r1),%r1\n"
,
f
)
;
fputs
(
"\tbve	(%r1)\n"
,
f
)
;
fputs
(
"\tldd	32(%r31),%r31\n"
,
f
)
;
fputs
(
"\t.dword 0  ; fptr\n"
,
f
)
;
fputs
(
"\t.dword 0  ; static link\n"
,
f
)
;
}
}
</s>

Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts.\ The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM and then branches to the specified routine . This code template is copied from text segment to stack location and then patched with pa_trampoline_init to contain valid values , and then entered as a subroutine . It is best to keep this as small as possible to avoid having to flush multiple lines in the cache .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
.
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
||
ST
.
slow3OpsLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TSM
.
init
(
&
Func
.
getSubtarget
(
)
)
;
TII
=
ST
.
getInstrInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> llvm :: FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { if ( EnableARMFastISel ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const unsigned CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX } ; static const unsigned CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETI : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < unsigned , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( const unsigned * AsI = TRI . getOverlaps ( Reg ) ; * AsI ; ++ AsI ) Uses . insert ( * AsI ) ; } const unsigned * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> bool isMem ( RegisterKind RegKind , MemoryKind MemKind ) const { return ( Kind == KindMem && Mem . RegKind == RegKind && ( MemKind == BDXMem || ! Mem . Index ) && ( MemKind == BDLMem ) == ( Mem . Length != nullptr ) ) ; } </s>


<s> static bool is_cracked_insn ( rtx insn ) { if ( ! insn || ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_LOAD_U || type == TYPE_STORE_U || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE || type == TYPE_IDIV || type == TYPE_LDIV || type == TYPE_INSERT_WORD ) return true ; } return false ; } </s>

The function returns true if INSN is cracked into 2 instructions by the processor ( and therefore occupies 2 issue slots ) .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; if ( Subtarget . hasSPE ( ) ) return CSR_SVR432_SPE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_SaveList : CSR_SVR32_ColdCC_SaveList ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC PPC


"%qE attribute ignored without -mcmse option."

"%qE attribute only applies to functions"

"%qE attribute has no effect on functions "

Called upon detection of the use of the cmse_nonsecure_entry attribute , this function will check whether the attribute is allowed here and will add the attribute to the function declaration tree or otherwise issue a warning .


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ; } </s>

getLocRange - Get the range between the first and last token of this operand .


<s> static enum ivms_arg_type ia64_arg_type ( machine_mode mode ) { switch ( mode ) { case SFmode : return FS ; case DFmode : return FT ; default : return I64 ; } } </s>

Return ivms_arg_type based on machine_mode .


<s> const TargetRegisterClass * ARMRegisterInfo :: getPointerRegClass ( ) const { return & ARM :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static enum aarch64_parse_opt_result aarch64_parse_cpu ( const char * to_parse , const struct processor * * res , uint64_t * isa_flags , std :: string * invalid_extension ) { const char * ext ; const struct processor * cpu ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , to_parse , len ) == 0 ) { uint64_t isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the result tuning in RES and the architecture flags in ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG && REGNO ( XEXP ( addr , 0 ) ) != 0 ) addr = XEXP ( addr , 0 ) ; else if ( GET_CODE ( XEXP ( addr , 1 ) ) == REG && REGNO ( XEXP ( addr , 1 ) ) != 0 ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 0 ) ) ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; else gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( addr ) == REG && REGNO ( addr ) != 0 ) ; return addr ; } </s>

Return a REG that occurs in ADDR with coefficient 1 . ADDR can be effectively incremented by incrementing REG . r0 is special and we must not select it as an address register by this routine since our caller will try to increment the returned register via an `` la '' instruction .


<s> rtx extract_nth_access_rtx ( rtx_insn * insn , int n ) { int n_elems = parallel_elements ( insn ) ; int post_update_rtx_index = find_post_update_rtx ( insn ) ; memory_access_direction direction = determine_access_direction ( insn ) ; gcc_assert ( direction != MEM_ACCESS_DIR_UNKNOWN ) ; if ( direction == MEM_ACCESS_DIR_NEG ) n = - 1 * n - 1 ; if ( post_update_rtx_index != - 1 ) { if ( n >= 0 && post_update_rtx_index <= n ) ++ n ; else if ( n < 0 && post_update_rtx_index >= n + n_elems ) -- n ; } return parallel_element ( insn , n ) ; } </s>

Return the nth load/store operation in the real micro-operation accessing order .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>


<s> static void aarch64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = R0_REGNUM ; rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; if ( vcall_offset == 0 ) aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - 1 ) ) == 0 ) ; addr = this_rtx ; if ( delta != 0 ) { if ( delta >= - 256 && delta < 256 ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - 256 && vcall_offset < 4096 * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return NumRegisters ; } return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> bool ARMTargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget -> hasV6T2Ops ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> inline machine_mode function_instance :: memory_vector_mode ( ) const { return base -> memory_vector_mode ( * this ) ; } </s>

If the function addresses memory , return a vector mode whose GET_MODE_NUNITS is the number of elements addressed and whose GET_MODE_INNER is the mode of a single scalar memory element .


<s> void rx_split_cbranch ( machine_mode cc_mode , enum rtx_code cmp1 , rtx c1 , rtx c2 , rtx label ) { rtx flags , x ; flags = gen_rtx_REG ( cc_mode , CC_REG ) ; x = gen_rtx_COMPARE ( cc_mode , c1 , c2 ) ; x = gen_rtx_SET ( VOIDmode , flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( cmp1 , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label , pc_rtx ) ; x = gen_rtx_SET ( VOIDmode , pc_rtx , x ) ; emit_jump_insn ( x ) ; } </s>

Split the conditional branch . Emit ( COMPARE C1 C2 ) into CC_REG with CC_MODE , and use that in branches based on that compare .


<s>
int
AArch64LoadStoreOpt
::
getMemSize
(
MachineInstr
*
MemMI
)
{
switch
(
MemMI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has has unknown size!"
)
;
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
return
4
;
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
return
8
;
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
return
16
;
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
return
4
;
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
return
8
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
return
16
;
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
return
4
;
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
return
8
;
}
}
</s>

Returns the size in bytes of the memory access .


<s> SDValue AArch64TargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> void MipsTargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { switch ( MI . getOpcode ( ) ) { default : return ; case Mips :: JALR : case Mips :: JALRPseudo : case Mips :: JALR64 : case Mips :: JALR64Pseudo : case Mips :: JALR16_MM : case Mips :: JALRC16_MMR6 : case Mips :: TAILCALLREG : case Mips :: TAILCALLREG64 : case Mips :: TAILCALLR6REG : case Mips :: TAILCALL64R6REG : case Mips :: TAILCALLREG_MM : case Mips :: TAILCALLREG_MMR6 : { if ( ! EmitJalrReloc || Subtarget . inMips16Mode ( ) || ! isPositionIndependent ( ) || Node -> getNumOperands ( ) < 1 || Node -> getOperand ( 0 ) . getNumOperands ( ) < 2 ) { return ; } const SDValue TargetAddr = Node -> getOperand ( 0 ) . getOperand ( 1 ) ; StringRef Sym ; if ( const GlobalAddressSDNode * G = dyn_cast_or_null < const GlobalAddressSDNode > ( TargetAddr ) ) { Sym = G -> getGlobal ( ) -> getName ( ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( TargetAddr ) ) { Sym = ES -> getSymbol ( ) ; } if ( Sym . empty ( ) ) return ; MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; MCSymbol * S = MF -> getContext ( ) . getOrCreateSymbol ( Sym ) ; MI . addOperand ( MachineOperand :: CreateMCSymbol ( S , MipsII :: MO_JALR ) ) ; } } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> unsigned Mips16InstrInfo :: loadImmediate ( unsigned FrameReg , int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned & NewImm ) const { RegScavenger rs ; int32_t lo = Imm & 0xFFFF ; int32_t hi = ( ( Imm >> 16 ) + ( lo >> 15 ) ) & 0xFFFF ; NewImm = lo ; unsigned Reg = 0 ; unsigned SpReg = 0 ; rs . enterBasicBlock ( & MBB ) ; rs . forward ( II ) ; unsigned FirstRegSaved = 0 , SecondRegSaved = 0 ; unsigned FirstRegSavedTo = 0 , SecondRegSavedTo = 0 ; Reg = rs . FindUnusedReg ( & Mips :: CPU16RegsRegClass ) ; if ( Reg == 0 ) { FirstRegSaved = Reg = Mips :: V0 ; FirstRegSavedTo = Mips :: T0 ; copyPhysReg ( MBB , II , DL , FirstRegSavedTo , FirstRegSaved , true ) ; } else rs . setUsed ( Reg ) ; BuildMI ( MBB , II , DL , get ( Mips :: LiRxImmX16 ) , Reg ) . addImm ( hi ) ; BuildMI ( MBB , II , DL , get ( Mips :: SllX16 ) , Reg ) . addReg ( Reg ) . addImm ( 16 ) ; if ( FrameReg == Mips :: SP ) { SpReg = rs . FindUnusedReg ( & Mips :: CPU16RegsRegClass ) ; if ( SpReg == 0 ) { if ( Reg != Mips :: V1 ) { SecondRegSaved = SpReg = Mips :: V1 ; SecondRegSavedTo = Mips :: T1 ; } else { SecondRegSaved = SpReg = Mips :: V0 ; SecondRegSavedTo = Mips :: T0 ; } copyPhysReg ( MBB , II , DL , SecondRegSavedTo , SecondRegSaved , true ) ; } else rs . setUsed ( SpReg ) ; copyPhysReg ( MBB , II , DL , SpReg , Mips :: SP , false ) ; BuildMI ( MBB , II , DL , get ( Mips :: AdduRxRyRz16 ) , Reg ) . addReg ( SpReg ) . addReg ( Reg ) ; } else BuildMI ( MBB , II , DL , get ( Mips :: AdduRxRyRz16 ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; if ( FirstRegSaved || SecondRegSaved ) { II = llvm :: next ( II ) ; if ( FirstRegSaved ) copyPhysReg ( MBB , II , DL , FirstRegSaved , FirstRegSavedTo , true ) ; if ( SecondRegSaved ) copyPhysReg ( MBB , II , DL , SecondRegSaved , SecondRegSavedTo , true ) ; } return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s> static void compute_save_world_info ( rs6000_stack_t * info_ptr ) { info_ptr -> world_save_p = 1 ; info_ptr -> world_save_p = ( WORLD_SAVE_P ( info_ptr ) && DEFAULT_ABI == ABI_DARWIN && ! ( current_function_calls_setjmp && flag_exceptions ) && info_ptr -> first_fp_reg_save == FIRST_SAVED_FP_REGNO && info_ptr -> first_gp_reg_save == FIRST_SAVED_GP_REGNO && info_ptr -> first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info_ptr -> cr_save_p ) ; if ( WORLD_SAVE_P ( info_ptr ) ) { rtx insn ; for ( insn = get_last_insn_anywhere ( ) ; insn ; insn = PREV_INSN ( insn ) ) if ( GET_CODE ( insn ) == CALL_INSN && SIBLING_CALL_P ( insn ) ) { info_ptr -> world_save_p = 0 ; break ; } } if ( WORLD_SAVE_P ( info_ptr ) ) { info_ptr -> vrsave_size = 4 ; if ( info_ptr -> vrsave_mask == 0 ) info_ptr -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info_ptr -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info_ptr -> first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ; } return ; } </s>

For a very restricted set of circumstances , we can cut down the size of prologues/epilogues by calling our own save/restore-the-world routines .


<s>
unsigned
int
sh_cbranch_distance
(
rtx_insn
*
_cbranch_insn
,
unsigned
int
max_dist
)
{
rtx_jump_insn
*
cbranch_insn
=
safe_as_a
<
rtx_jump_insn
*
>
(
_cbranch_insn
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"sh_cbranch_distance insn = \n"
)
;
print_rtl_single
(
dump_file
,
cbranch_insn
)
;
}
unsigned
int
dist
=
0
;
for
(
rtx_insn
*
i
=
next_nonnote_insn
(
cbranch_insn
)
;
i
!=
&&
dist
<
max_dist
;
i
=
next_nonnote_insn
(
i
)
)
{
const
unsigned
int
i_len
=
get_attr_length
(
i
)
;
dist
+=
i_len
;
if
(
dump_file
)
fprintf
(
dump_file
,
"  insn %d  length = %u  dist = %u\n"
,
INSN_UID
(
i
)
,
i_len
,
dist
)
;
if
(
rtx_code_label
*
l
=
dyn_cast
<
rtx_code_label
*
>
(
i
)
)
{
if
(
l
==
cbranch_insn
->
jump_target
(
)
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"  cbranch dist = %u\n"
,
dist
)
;
return
dist
;
}
break
;
}
}
if
(
dump_file
)
fprintf
(
dump_file
,
"  cbranch dist = unknown\n"
)
;
return
unknown_cbranch_distance
;
}
</s>

Try to calculate the branch distance of a conditional branch in bytes . FIXME : Because of PR 59189 we ca n't use the CFG here . Instead just walk from this insn into the next ( fall-through ) basic block and see if we hit the label .

sh
"sh_cbranch_distance insn = \n"
0
"  insn %d  length = %u  dist = %u\n"
"  cbranch dist = %u\n"
"  cbranch dist = unknown\n"


<s> bool ix86_expand_fp_vcond ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; rtx cmp ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & operands [ 4 ] , & operands [ 5 ] ) ; if ( code == UNKNOWN ) { rtx temp ; switch ( GET_CODE ( operands [ 3 ] ) ) { case LTGT : temp = ix86_expand_sse_cmp ( operands [ 0 ] , ORDERED , operands [ 4 ] , operands [ 5 ] , operands [ 0 ] , operands [ 0 ] ) ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , NE , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ; code = AND ; break ; case UNEQ : temp = ix86_expand_sse_cmp ( operands [ 0 ] , UNORDERED , operands [ 4 ] , operands [ 5 ] , operands [ 0 ] , operands [ 0 ] ) ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , EQ , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ; code = IOR ; break ; default : gcc_unreachable ( ) ; } cmp = expand_simple_binop ( GET_MODE ( cmp ) , code , temp , cmp , cmp , 1 , OPTAB_DIRECT ) ; ix86_expand_sse_movcc ( operands [ 0 ] , cmp , operands [ 1 ] , operands [ 2 ] ) ; return true ; } if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ) return true ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , cmp , operands [ 1 ] , operands [ 2 ] ) ; return true ; } </s>

Expand a floating-point vector conditional move ; a vcond operation rather than a movcc operation .


<s>
const
char
*
pru_output_signed_cbranch_zeroop2
(
rtx
*
operands
,
bool
is_near
)
{
static
char
buf
[
1024
]
;
enum
rtx_code
code
=
GET_CODE
(
operands
[
0
]
)
;
int
regop_sign_bit_pos
=
sign_bit_position
(
operands
[
1
]
)
;
if
(
code
==
LT
)
{
if
(
is_near
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t%%l3, %%1, %d\n\t"
,
regop_sign_bit_pos
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbc\t.+8, %%1, %d\n\t"
"jmp\t%%%%label(%%l3)"
,
regop_sign_bit_pos
)
;
}
else
if
(
code
==
GE
)
{
if
(
is_near
)
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbc\t%%l3, %%1, %d\n\t"
,
regop_sign_bit_pos
)
;
else
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+8, %%1, %d\n\t"
"jmp\t%%%%label(%%l3)"
,
regop_sign_bit_pos
)
;
}
else
gcc_unreachable
(
)
;
return
buf
;
}
</s>

Optimized version of pru_output_signed_cbranch_ubyteop2 for constant zero second operand .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
>
I
=
df_ext_begin
(
Entry
,
Processed
)
,
E
=
df_ext_end
(
Entry
,
Processed
)
;
I
!=
E
;
++
I
)
Changed
|=
processBasicBlock
(
MF
,
*
*
I
)
;
if
(
MF
.
size
(
)
==
Processed
.
size
(
)
)
return
Changed
;
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void aarch64_emit_sve_ptrue_op_cc ( rtx target , rtx ptrue , rtx op ) { rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( target ) , gen_rtvec ( 2 , ptrue , op ) , UNSPEC_MERGE_PTRUE ) ; rtx_insn * insn = emit_insn ( gen_set_clobber_cc ( target , unspec ) ) ; set_unique_reg_note ( insn , REG_EQUAL , copy_rtx ( op ) ) ; } </s>

Likewise , but also clobber the condition codes .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT , Subtarget -> hasAVX ( ) ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isPSHUFLWMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isPALIGNRMask ( M , VT , Subtarget ) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKH_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool AArch64PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> void sparc_emit_membar_for_model ( enum memmodel model , int load_store , int before_after ) { const int LoadLoad = 1 ; const int StoreLoad = 2 ; const int LoadStore = 4 ; const int StoreStore = 8 ; int mm = 0 , implied = 0 ; switch ( sparc_memory_model ) { case SMM_SC : implied = LoadLoad | StoreLoad | LoadStore | StoreStore ; break ; case SMM_TSO : implied |= StoreStore ; if ( load_store == 3 && before_after == 1 ) implied |= StoreLoad ; case SMM_PSO : implied |= LoadLoad | LoadStore ; if ( load_store == 3 && before_after == 2 ) implied |= StoreLoad | StoreStore ; case SMM_RMO : break ; default : gcc_unreachable ( ) ; } if ( before_after & 1 ) { if ( is_mm_release ( model ) || is_mm_acq_rel ( model ) || is_mm_seq_cst ( model ) ) { if ( load_store & 1 ) mm |= LoadLoad | StoreLoad ; if ( load_store & 2 ) mm |= LoadStore | StoreStore ; } } if ( before_after & 2 ) { if ( is_mm_acquire ( model ) || is_mm_acq_rel ( model ) || is_mm_seq_cst ( model ) ) { if ( load_store & 1 ) mm |= LoadLoad | LoadStore ; if ( load_store & 2 ) mm |= StoreLoad | StoreStore ; } } mm &= ~ implied ; if ( mm || before_after == 3 ) emit_insn ( gen_membar ( GEN_INT ( mm ) ) ) ; } </s>

Expand a membar instruction for various use cases . Both the LOAD_STORE and BEFORE_AFTER arguments of the form X_Y . They are two-bit masks where bit 0 indicates that X is true , and bit 1 indicates Y is true .


<s> void UPTAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"SVE type %qT does not have a fixed size"

"SVE type %qT does not have a defined alignment"

"variables of type %qT cannot have thread-local"

"member variables cannot have SVE type %qT"

"array elements cannot have SVE type %qT"

"cannot allocate objects with SVE type %qT"

"cannot delete objects with SVE type %qT"

Implement TARGET_VERIFY_TYPE_CONTEXT for RVV types .


<s> bool rs6000_is_valid_shift_mask ( rtx mask , rtx shift , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = - 1 ; if ( CONST_INT_P ( XEXP ( shift , 1 ) ) ) { sh = INTVAL ( XEXP ( shift , 1 ) ) ; if ( sh < 0 || sh >= n ) return false ; } rtx_code code = GET_CODE ( shift ) ; if ( sh == 0 ) code = ROTATE ; if ( code == ROTATE && sh >= 0 && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= 0 && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( nb == 63 || ne == 0 || ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < 32 && ne < 32 && sh < 32 ) ; if ( ne > nb ) return false ; if ( sh < 0 ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < 32 && ne < 32 && sh < 32 && ! ( code == LSHIFTRT && nb >= 32 - sh ) ) return true ; if ( code == LSHIFTRT ) sh = 64 - sh ; if ( nb == 63 || ne == 0 || ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlw [ i ] nm , rld [ i ] cl , rld [ i ] cr , or rld [ i ] c instruction , to implement an AND with shift SHIFT ( a ROTATE , ASHIFT , or LSHIFTRT ) in mode MODE .


<s> static int mips_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { reg_class_t dregs ; int cost1 , cost2 ; from = mips_canonicalize_move_class ( from ) ; to = mips_canonicalize_move_class ( to ) ; if ( from == FP_REGS ) { if ( to == FP_REGS && mips_mode_ok_for_mov_fmt_p ( mode ) ) return 4 ; } dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS ; if ( from == dregs ) return mips_move_from_gpr_cost ( to ) ; if ( to == dregs ) return mips_move_to_gpr_cost ( from ) ; cost1 = mips_move_to_gpr_cost ( from ) ; if ( cost1 != 0 ) { cost2 = mips_move_from_gpr_cost ( to ) ; if ( cost2 != 0 ) return cost1 + cost2 ; } return 0 ; } </s>

Implement TARGET_REGISTER_MOVE_COST . Return 0 for classes that are the maximum of the move costs for subclasses ; regclass will work out the maximum for us .


<s> static int ix86_register_priority ( int hard_regno ) { if ( hard_regno == R12_REG || hard_regno == R13_REG ) return 0 ; if ( hard_regno == BP_REG ) return 1 ; if ( REX_INT_REGNO_P ( hard_regno ) ) return 2 ; if ( REX_SSE_REGNO_P ( hard_regno ) ) return 2 ; if ( EXT_REX_SSE_REGNO_P ( hard_regno ) ) return 1 ; if ( hard_regno == AX_REG ) return 4 ; return 3 ; } </s>

Return a register priority for hard reg REGNO .


<s> static bool aarch64_vfp_is_call_or_return_candidate ( machine_mode mode , const_tree type , machine_mode * base_mode , int * count , bool * is_ha ) { machine_mode new_mode = VOIDmode ; bool composite_p = aarch64_composite_type_p ( type , mode ) ; if ( is_ha != NULL ) * is_ha = false ; if ( ( ! composite_p && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) || aarch64_short_vector_p ( type , mode ) ) { * count = 1 ; new_mode = mode ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( is_ha != NULL ) * is_ha = true ; * count = 2 ; new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS ) { if ( is_ha != NULL ) * is_ha = true ; * count = ag_count ; } else return false ; } else return false ; * base_mode = new_mode ; return true ; } </s>

Return TRUE if an argument , whose type is described by TYPE and MODE , shall be passed or returned in simd/fp register ( s ) ( providing these parameter passing registers are available ) . Upon successful return , * COUNT returns the number of needed registers , * BASE_MODE returns the mode of the individual register and when IS_HAF is not NULL , * IS_HA indicates whether or not the argument is a homogeneous floating-point aggregate or a homogeneous short-vector aggregate .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS ( ) ) { addPass ( new ReplaceFMULS ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> detectRoundChange ( ) ) { addPass ( new DetectRoundChange ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc


<s> static bool ix86_legitimate_constant_p ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; if ( ix86_force_load_from_GOT_p ( x ) ) return false ; break ; CASE_CONST_SCALAR_INT : if ( ix86_endbr_immediate_operand ( x , VOIDmode ) ) return false ; switch ( mode ) { case E_TImode : if ( TARGET_64BIT ) return true ; case E_OImode : case E_XImode : if ( ! standard_sse_constant_p ( x , mode ) && GET_MODE_SIZE ( TARGET_AVX512F ? XImode : ( TARGET_AVX ? OImode : ( TARGET_SSE2 ? TImode : DImode ) ) ) < GET_MODE_SIZE ( mode ) ) return false ; default : break ; } break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; break ; case CONST_DOUBLE : if ( mode == E_BFmode ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> static void rs6000_adjust_vect_cost_per_loop ( rs6000_cost_data * data ) { struct loop * loop = data -> loop_info ; gcc_assert ( loop ) ; loop_vec_info loop_vinfo = loop_vec_info_for_loop ( loop ) ; if ( LOOP_VINFO_FULLY_WITH_LENGTH_P ( loop_vinfo ) ) { rgroup_controls * rgc ; unsigned int num_vectors_m1 ; unsigned int shift_cnt = 0 ; FOR_EACH_VEC_ELT ( LOOP_VINFO_LENS ( loop_vinfo ) , num_vectors_m1 , rgc ) if ( rgc -> type ) shift_cnt += num_vectors_m1 + 1 ; rs6000_add_stmt_cost ( loop_vinfo , ( void * ) data , shift_cnt , scalar_stmt , NULL , NULL_TREE , 0 , vect_body ) ; } } </s>

For some target specific vectorization cost which ca n't be handled per stmt , we check the requisite conditions and adjust the vectorization cost accordingly if satisfied . One typical example is to model shift cost for vector with length by counting number of required lengths under condition LOOP_VINFO_FULLY_WITH_LENGTH_P .