<s> static void ix86_output_indirect_branch_via_push ( rtx call_op , const char * xasm , bool sibcall_p ) { char thunk_name_buf [ 32 ] ; char * thunk_name ; char push_buf [ 64 ] ; enum indirect_thunk_prefix need_prefix = indirect_thunk_need_prefix ( current_output_insn ) ; int regno = - 1 ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_inline ) { if ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) indirect_thunk_needed = true ; indirect_thunk_name ( thunk_name_buf , regno , need_prefix , false ) ; thunk_name = thunk_name_buf ; } else thunk_name = NULL ; snprintf ( push_buf , sizeof ( push_buf ) , "push{%c}\t%s" , TARGET_64BIT ? 'q' : 'l' , xasm ) ; if ( sibcall_p ) { output_asm_insn ( push_buf , & call_op ) ; ix86_output_jmp_thunk_or_indirect ( thunk_name , regno ) ; } else { char indirectlabel1 [ 32 ] ; char indirectlabel2 [ 32 ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; fputs ( "\tjmp\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( MEM_P ( call_op ) ) { struct ix86_address parts ; rtx addr = XEXP ( call_op , 0 ) ; if ( ix86_decompose_address ( addr , & parts ) && parts . base == stack_pointer_rtx ) { if ( parts . index ) { addr = gen_rtx_MULT ( Pmode , parts . index , GEN_INT ( parts . scale ) ) ; addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , addr ) ; } else addr = stack_pointer_rtx ; rtx disp ; if ( parts . disp != NULL_RTX ) disp = plus_constant ( Pmode , parts . disp , UNITS_PER_WORD ) ; else disp = GEN_INT ( UNITS_PER_WORD ) ; addr = gen_rtx_PLUS ( Pmode , addr , disp ) ; call_op = gen_rtx_MEM ( GET_MODE ( call_op ) , addr ) ; } } output_asm_insn ( push_buf , & call_op ) ; ix86_output_jmp_thunk_or_indirect ( thunk_name , regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; fputs ( "\tcall\t" , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel1 ) ; fputc ( '\n' , asm_out_file ) ; } } </s>

Output indirect branch via a call and return thunk . CALL_OP is the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : jmp L2 L1 : push CALL_OP jmp __x86_indirect_thunk L2 : call L1 and a tail call is converted to : push CALL_OP jmp __x86_indirect_thunk


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntValTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( Val -> getType ( ) ) ) ; Val = Builder . CreateBitCast ( Val , IntValTy ) ; return Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) ) ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


<s> static const char * svpattern_token ( enum aarch64_svpattern pattern ) { switch ( pattern ) { AARCH64_FOR_SVPATTERN ( CASE ) case AARCH64_NUM_SVPATTERNS : break ; } gcc_unreachable ( ) ; } </s>

Return the assembly token for svpattern value VALUE .


<s> TargetPassConfig * PPCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new PPCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> MCSymbol * X86TargetLowering :: getPICBaseSymbol ( const MachineFunction * MF , MCContext & Ctx ) const { const MCAsmInfo & MAI = * getTargetMachine ( ) . getMCAsmInfo ( ) ; return Ctx . GetOrCreateSymbol ( Twine ( MAI . getPrivateGlobalPrefix ( ) ) + Twine ( MF -> getFunctionNumber ( ) ) + "$pb" ) ; } </s>

getPICBaseSymbol - Return a function-local symbol to represent the PIC base .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( ConstantSDNode * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; if ( Bytes >= 1 && Bytes <= 0x100 ) { return DAG . getNode ( SystemZISD :: MVC , DL , MVT :: Other , Chain , Dst , Src , Size ) ; } } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ 1 0x100 SystemZISD::MVC MVT::Other


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s>
bool
ARMBlockPlacement
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
DEBUG_PREFIX
<<
"Running on "
<<
MF
.
getName
(
)
<<
"\n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
MF
.
RenumberBlocks
(
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
*
ML
:
*
MLI
)
Changed
|=
processPostOrderLoops
(
ML
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"Running on "
"\n"
ARM
ARM
ARM


<s>
unsigned
SparcRegisterInfo
::
getRARegister
(
)
const
{
llvm_unreachable
(
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .

Sparc
Sparc
"What is the return address register"
0


<s> void AArch64TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , SE , UP ) ; if ( L -> getLoopDepth ( ) > 1 ) UP . PartialThreshold *= 2 ; UP . PartialOptSizeThreshold = 0 ; if ( ST -> getProcFamily ( ) == AArch64Subtarget :: Falkor && EnableFalkorHWPFUnrollFix ) getFalkorUnrollingPreferences ( L , SE , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool valid_sf_si_move ( rtx dest , rtx src , machine_mode mode ) { if ( TARGET_ALLOW_SF_SUBREG ) return true ; if ( mode != SFmode && GET_MODE_CLASS ( mode ) != MODE_INT ) return true ; if ( ! SUBREG_P ( src ) || ! sf_subreg_operand ( src , mode ) ) return true ; if ( SUBREG_P ( dest ) ) { rtx dest_subreg = SUBREG_REG ( dest ) ; rtx src_subreg = SUBREG_REG ( src ) ; return GET_MODE ( dest_subreg ) == GET_MODE ( src_subreg ) ; } return false ; } </s>

Return whether a SFmode or SImode move can be done without converting one mode to another . This arrises when we have : ( SUBREG : SF ( REG : SI ... ) ) ( SUBREG : SI ( REG : SF ... ) ) and one of the values is in a floating point/vector register , where SFmode scalars are stored in DFmode format .


<s> bool nds32_expand_movmemsi ( rtx dstmem , rtx srcmem , rtx total_bytes , rtx alignment ) { if ( nds32_expand_movmemsi_unroll ( dstmem , srcmem , total_bytes , alignment ) ) return true ; if ( ! optimize_size && optimize > 2 ) return nds32_expand_movmemsi_loop ( dstmem , srcmem , total_bytes , alignment ) ; return false ; } </s>

Function to move block memory content by using load_multiple and store_multiple . This is auxiliary extern function to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> unsigned MipsSEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SW_P8 ) || ( Opc == Mips :: SD ) || ( Opc == Mips :: SD_P8 ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SWC1_P8 ) || ( Opc == Mips :: SDC1 ) || ( Opc == Mips :: SDC164 ) || ( Opc == Mips :: SDC164_P8 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
getReturnCC
(
CallConv
)
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
OutVal
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
ZExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
AExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
BCvt
:
{
assert
(
VA
.
getLocVT
(
)
==
MVT
::
i64
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f32
)
;
SDValue
Undef
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
IMPLICIT_DEF
,
DL
,
MVT
::
i64
)
,
0
)
;
SDValue
Sub_f32
=
DAG
.
getTargetConstant
(
VE
::
sub_f32
,
DL
,
MVT
::
i32
)
;
OutVal
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
INSERT_SUBREG
,
DL
,
MVT
::
i64
,
Undef
,
OutVal
,
Sub_f32
)
,
0
)
;
break
;
}
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
}
assert
(
!
VA
.
needsCustom
(
)
&&
"Unexpected custom lowering"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVal
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool ARMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Restores ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST_IMM ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register , NumAlignedDPRCS2Regs ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register , 0 ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register , 0 ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool r10k_safe_mem_expr_p ( tree expr , unsigned HOST_WIDE_INT offset ) { HOST_WIDE_INT bitoffset , bitsize ; tree inner , var_offset ; machine_mode mode ; int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi ( DECL_SIZE_UNIT ( inner ) ) ; } </s>

Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is an in-range access to an automatic variable , or to an object with a link-time-constant address .


Targets may add passes immediately before machine code is emitted in this callback .


<s>
void
aarch64_sve_op_count
::
dump
(
)
const
{
aarch64_vec_op_count
::
dump
(
)
;
dump_printf_loc
(
MSG_NOTE
,
vect_location
,
"  predicate operations = %d\n"
,
pred_ops
)
;
}
</s>


<s> static tree aarch64_fold_builtin ( tree fndecl , int nargs , tree * args , bool ) { unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return aarch64_general_fold_builtin ( subcode , type , nargs , args ) ; case AARCH64_BUILTIN_SVE : return NULL_TREE ; } gcc_unreachable ( ) ; } </s>


<s> bool mips_legitimize_move ( machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! register_operand ( src , mode ) && ( TARGET_MIPS16 || ! const_0_operand ( src , mode ) || MSA_SUPPORTED_MODE_P ( mode ) ) ) { mips_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { mips_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false ; } </s>

If ( set DEST SRC ) is not a valid instruction , emit an equivalent sequence that is valid .


<s> unsigned X86TTI :: getIntImmCost ( Intrinsic :: ID IID , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; switch ( IID ) { default : return TargetTransformInfo :: getIntImmCost ( IID , Imm , Ty ) ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; else return X86TTI :: getIntImmCost ( Imm , Ty ) ; case Intrinsic :: experimental_stackmap : case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; else return X86TTI :: getIntImmCost ( Imm , Ty ) ; } } </s>

Calculate the cost of materializing a 64-bit value .


<s> void X86AsmParser :: emitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { if ( LVIInlineAsmHardening && getSTI ( ) . getFeatureBits ( ) [ X86 :: FeatureLVIControlFlowIntegrity ] ) applyLVICFIMitigation ( Inst , Out ) ; Out . emitInstruction ( Inst , getSTI ( ) ) ; if ( LVIInlineAsmHardening && getSTI ( ) . getFeatureBits ( ) [ X86 :: FeatureLVILoadHardening ] ) applyLVILoadHardeningMitigation ( Inst , Out ) ; } </s>

Targets should implement this to emit instructions .


<s> void SICInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static int aarch64_sched_variable_issue ( FILE * , int , rtx_insn * insn , int more ) { if ( DEBUG_INSN_P ( insn ) ) return more ; rtx_code code = GET_CODE ( PATTERN ( insn ) ) ; if ( code == USE || code == CLOBBER ) return more ; if ( get_attr_type ( insn ) == TYPE_NO_INSN ) return more ; return more - 1 ; } </s>


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( EVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = ARM :: DPRRegisterClass ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = ARM :: DPRRegisterClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = ARM :: DPRRegisterClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = ARM :: DPRRegisterClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const TargetRegisterClass * RC = static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) . inMips16Mode ( ) ? & Mips :: CPU16RegsRegClass : static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool PPCTargetLowering :: SelectAddressPCRel ( SDValue N , SDValue & Base ) const { Base = N ; if ( N . getOpcode ( ) == PPCISD :: MAT_PCREL_ADDR ) return true ; if ( isValidPCRelNode < ConstantPoolSDNode > ( N ) || isValidPCRelNode < GlobalAddressSDNode > ( N ) || isValidPCRelNode < JumpTableSDNode > ( N ) || isValidPCRelNode < BlockAddressSDNode > ( N ) ) return true ; return false ; } </s>

SelectAddressPCRel - Represent the specified address as pc relative to be represented as [ pc+imm ] .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
MMIX
::
NumTargetFixupKinds
]
=
{
{
"fixup_mmix_rel_16"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_mmix_rel_24"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_mmix_h"
,
0
,
16
,
0
}
,
{
"fixup_mmix_mh"
,
0
,
16
,
0
}
,
{
"fixup_mmix_ml"
,
0
,
16
,
0
}
,
{
"fixup_mmix_l"
,
0
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static int get_num_immediates ( rtx_insn * insn , int * imm , int * imm32 , int * imm64 ) { imm_info imm_values = { 0 , 0 , 0 } ; find_constant ( insn , & imm_values ) ; * imm = imm_values . imm ; * imm32 = imm_values . imm32 ; * imm64 = imm_values . imm64 ; return imm_values . imm32 * 4 + imm_values . imm64 * 8 ; } </s>

Return total size of immediate operands of an instruction along with number of corresponding immediate-operands . It initializes its parameters to zero befor calling FIND_CONSTANT . INSN is the input instruction . IMM is the total of immediates . IMM32 is the number of 32 bit immediates . IMM64 is the number of 64 bit immediates .


<s> void sh_va_start ( tree valist , rtx nextarg ) { tree f_next_o , f_next_o_limit , f_next_fp , f_next_fp_limit , f_next_stack ; tree next_o , next_o_limit , next_fp , next_fp_limit , next_stack ; tree t , u ; int nfp , nint ; if ( TARGET_SH5 ) { expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist , nextarg ) ; return ; } if ( ( ! TARGET_SH2E && ! TARGET_SH4 ) || TARGET_HITACHI || sh_cfun_attr_renesas_p ( ) ) { std_expand_builtin_va_start ( valist , nextarg ) ; return ; } f_next_o = TYPE_FIELDS ( va_list_type_node ) ; f_next_o_limit = TREE_CHAIN ( f_next_o ) ; f_next_fp = TREE_CHAIN ( f_next_o_limit ) ; f_next_fp_limit = TREE_CHAIN ( f_next_fp ) ; f_next_stack = TREE_CHAIN ( f_next_fp_limit ) ; next_o = build ( COMPONENT_REF , TREE_TYPE ( f_next_o ) , valist , f_next_o , NULL_TREE ) ; next_o_limit = build ( COMPONENT_REF , TREE_TYPE ( f_next_o_limit ) , valist , f_next_o_limit , NULL_TREE ) ; next_fp = build ( COMPONENT_REF , TREE_TYPE ( f_next_fp ) , valist , f_next_fp , NULL_TREE ) ; next_fp_limit = build ( COMPONENT_REF , TREE_TYPE ( f_next_fp_limit ) , valist , f_next_fp_limit , NULL_TREE ) ; next_stack = build ( COMPONENT_REF , TREE_TYPE ( f_next_stack ) , valist , f_next_stack , NULL_TREE ) ; u = make_tree ( ptr_type_node , expand_builtin_saveregs ( ) ) ; t = build ( MODIFY_EXPR , ptr_type_node , next_fp , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nfp = current_function_args_info . arg_count [ SH_ARG_FLOAT ] ; if ( nfp < 8 ) nfp = 8 - nfp ; else nfp = 0 ; u = fold ( build ( PLUS_EXPR , ptr_type_node , u , build_int_cst ( NULL_TREE , UNITS_PER_WORD * nfp ) ) ) ; t = build ( MODIFY_EXPR , ptr_type_node , next_fp_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build ( MODIFY_EXPR , ptr_type_node , next_o , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nint = current_function_args_info . arg_count [ SH_ARG_INT ] ; if ( nint < 4 ) nint = 4 - nint ; else nint = 0 ; u = fold ( build ( PLUS_EXPR , ptr_type_node , u , build_int_cst ( NULL_TREE , UNITS_PER_WORD * nint ) ) ) ; t = build ( MODIFY_EXPR , ptr_type_node , next_o_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , nextarg ) ; t = build ( MODIFY_EXPR , ptr_type_node , next_stack , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s>
static
int
arm_comp_type_attributes
(
const_tree
type1
,
const_tree
type2
)
{
int
l1
,
l2
,
s1
,
s2
;
tree
attrs1
=
lookup_attribute
(
"Advanced SIMD type"
,
TYPE_ATTRIBUTES
(
type1
)
)
;
tree
attrs2
=
lookup_attribute
(
"Advanced SIMD type"
,
TYPE_ATTRIBUTES
(
type2
)
)
;
if
(
bool
(
attrs1
)
!=
bool
(
attrs2
)
)
return
0
;
if
(
attrs1
&&
!
attribute_value_equal
(
attrs1
,
attrs2
)
)
return
0
;
if
(
TREE_CODE
(
type1
)
!=
FUNCTION_TYPE
)
return
1
;
l1
=
lookup_attribute
(
"long_call"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
l2
=
lookup_attribute
(
"long_call"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
s1
=
lookup_attribute
(
"short_call"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
s2
=
lookup_attribute
(
"short_call"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
if
(
l1
|
l2
|
s1
|
s2
)
{
if
(
(
l1
!=
l2
)
||
(
s1
!=
s2
)
)
return
0
;
if
(
(
l1
&
s2
)
||
(
l2
&
s1
)
)
return
0
;
}
l1
=
lookup_attribute
(
"isr"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
if
(
!
l1
)
l1
=
lookup_attribute
(
"interrupt"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
l2
=
lookup_attribute
(
"isr"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
if
(
!
l2
)
l1
=
lookup_attribute
(
"interrupt"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
if
(
l1
!=
l2
)
return
0
;
l1
=
lookup_attribute
(
"cmse_nonsecure_call"
,
TYPE_ATTRIBUTES
(
type1
)
)
!=
;
l2
=
lookup_attribute
(
"cmse_nonsecure_call"
,
TYPE_ATTRIBUTES
(
type2
)
)
!=
;
if
(
l1
!=
l2
)
return
0
;
return
1
;
}
</s>

Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s> static bool arm_return_in_msb ( tree valtype ) { return ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE ) ) ; } </s>

Values which must be returned in the most-significant end of the return register .


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case V16QImode : case V8HImode : case V4SFmode : case V4SImode : case V2DFmode : case V2DImode : case V1TImode : case TImode : case TFmode : case KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return false ; break ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


"%qE attribute only applies to functions"

Handle an `` interrupt_handler '' attribute ; arguments as in struct attribute_spec.handler .


<s> unsigned X86TargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) { RegisterVT = MVT :: i8 ; IntermediateVT = MVT :: i1 ; NumIntermediates = VT . getVectorNumElements ( ) ; return NumIntermediates ; } if ( VT == MVT :: v64i1 && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && CC != CallingConv :: X86_RegCall ) { RegisterVT = MVT :: v32i1 ; IntermediateVT = MVT :: v32i1 ; NumIntermediates = 2 ; return 2 ; } return TargetLowering :: getVectorTypeBreakdownForCallingConv ( Context , CC , VT , IntermediateVT , NumIntermediates , RegisterVT ) ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
KindTy
::
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
.
id
(
)
;
}
</s>

Returns the register associated with this edge .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


"asm flags not supported in thumb1 mode"

Worker function for TARGET_MD_ASM_ADJUST , while in thumb1 mode . Unlike the arm version , we do NOT implement asm flag outputs .


<s> bool ix86_check_builtin_isa_match ( unsigned int fcode , HOST_WIDE_INT * pbisa , HOST_WIDE_INT * pbisa2 ) { HOST_WIDE_INT isa = ix86_isa_flags ; HOST_WIDE_INT isa2 = ix86_isa_flags2 ; HOST_WIDE_INT bisa = ix86_builtins_isa [ fcode ] . isa ; HOST_WIDE_INT bisa2 = ix86_builtins_isa [ fcode ] . isa2 ; if ( ( ( bisa & ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) == ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) && ( isa & ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ) != 0 ) isa |= ( OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) == ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) && ( isa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) != 0 ) isa |= ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) == ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) && ( isa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) != 0 ) isa |= ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ; if ( ( ( ( bisa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( bisa2 & OPTION_MASK_ISA2_AVXVNNI ) != 0 ) && ( ( ( isa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( isa2 & OPTION_MASK_ISA2_AVXVNNI ) != 0 ) ) { isa |= OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXVNNI ; } if ( ( bisa & OPTION_MASK_ISA_MMX ) && ! TARGET_MMX && TARGET_MMX_WITH_SSE && fcode != IX86_BUILTIN_MASKMOVQ ) { bisa &= ~ OPTION_MASK_ISA_MMX ; bisa |= OPTION_MASK_ISA_SSE2 ; } if ( pbisa ) * pbisa = bisa ; if ( pbisa2 ) * pbisa2 = bisa2 ; return ( bisa & isa ) == bisa && ( bisa2 & isa2 ) == bisa2 ; } </s>

Return true if the necessary isa options for this builtin exist , else false . fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ;


"the layout of aggregates containing vectors with"

" %d-byte alignment has changed in GCC 5"

Previous GCC releases forced all vector types to have 16-byte alignment .


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; Register AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> CSKYSubtarget & CSKYSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPUName , StringRef TuneCPUName , StringRef FS ) { if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; HasE1 = false ; HasE2 = false ; Has2E3 = false ; HasMP = false ; Has3E3r1 = false ; Has3r1E3r2 = false ; Has3r2E3r3 = false ; Has3E7 = false ; HasMP1E2 = false ; Has7E10 = false ; Has10E60 = false ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool WinEHStatePass :: doInitialization ( Module & M ) { TheModule = & M ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


"getJumpTargetOpValue expects only expressions"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSpill : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64Pseudo : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> unsigned getMaxInlineSizeThreshold ( ) const { return isThumb ( ) ? 0 : 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s>
void
write_fntype_init
(
char
*
str
)
{
char
*
tok
;
int
tf_found
=
strstr
(
str
,
"tf"
)
!=
;
int
dfp_found
=
(
strstr
(
str
,
"dd"
)
!=
||
strstr
(
str
,
"td"
)
!=
||
strstr
(
str
,
"sd"
)
!=
)
;
char
*
buf
=
strdup
(
str
)
;
if
(
tf_found
||
dfp_found
)
fprintf
(
init_file
,
"  tree %s = NULL_TREE;\n"
,
buf
)
;
else
fprintf
(
init_file
,
"  tree "
)
;
if
(
tf_found
)
fprintf
(
init_file
,
"  if (float128_type_node)\n    "
)
;
else
if
(
dfp_found
)
fprintf
(
init_file
,
"  if (dfloat64_type_node)\n    "
)
;
fprintf
(
init_file
,
"%s\n    = build_function_type_list ("
,
buf
)
;
tok
=
strtok
(
buf
,
"_"
)
;
write_type_node
(
tok
,
tf_found
||
dfp_found
)
;
tok
=
strtok
(
0
,
"_"
)
;
assert
(
tok
)
;
assert
(
!
strcmp
(
tok
,
"ftype"
)
)
;
tok
=
strtok
(
0
,
"_"
)
;
if
(
tok
)
fprintf
(
init_file
,
",\n\t\t\t\t"
)
;
while
(
tok
&&
strcmp
(
tok
,
"v"
)
)
{
write_type_node
(
tok
,
tf_found
||
dfp_found
)
;
tok
=
strtok
(
0
,
"_"
)
;
fprintf
(
init_file
,
",\n\t\t\t\t"
)
;
}
fprintf
(
init_file
,
"NULL_TREE);\n"
)
;
free
(
buf
)
;
}
</s>

Write an initializer for a function type identified by STR .


<s>
static
void
mips_output_cplocal
(
void
)
{
if
(
!
TARGET_EXPLICIT_RELOCS
&&
mips_must_initialize_gp_p
(
)
&&
cfun
->
machine
->
global_pointer
!=
GLOBAL_POINTER_REGNUM
)
output_asm_insn
(
".cplocal %+"
,
0
)
;
}
</s>

If we 're generating n32 or n64 abicalls , and the current function does not use $ 28 as its global pointer , emit a cplocal directive . Use pic_offset_table_rtx as the argument to the directive .


<s>
SDValue
CSKYTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
CSKYLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
CSKYLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
CCAssignFnForReturn
(
CallConv
,
IsVarArg
)
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
CSKYLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
CSKYLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
bool
IsF64OnCSKY
=
VA
.
getLocVT
(
)
==
MVT
::
i32
&&
VA
.
getValVT
(
)
==
MVT
::
f64
;
if
(
IsF64OnCSKY
)
{
assert
(
VA
.
isRegLoc
(
)
&&
"Expected return via registers"
)
;
SDValue
Split64
=
DAG
.
getNode
(
CSKYISD
::
BITCAST_TO_LOHI
,
DL
,
DAG
.
getVTList
(
MVT
::
i32
,
MVT
::
i32
)
,
Val
)
;
SDValue
Lo
=
Split64
.
getValue
(
0
)
;
SDValue
Hi
=
Split64
.
getValue
(
1
)
;
Register
RegLo
=
VA
.
getLocReg
(
)
;
assert
(
RegLo
<
CSKY
::
R31
&&
"Invalid register pair"
)
;
Register
RegHi
=
RegLo
+
1
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
RegLo
,
Lo
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
RegLo
,
MVT
::
i32
)
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
RegHi
,
Hi
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
RegHi
,
MVT
::
i32
)
)
;
}
else
{
Val
=
convertValVTToLocVT
(
DAG
,
Val
,
VA
,
DL
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
{
RetOps
.
push_back
(
Glue
)
;
}
if
(
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
return
DAG
.
getNode
(
CSKYISD
::
NIR
,
DL
,
MVT
::
Other
,
RetOps
)
;
return
DAG
.
getNode
(
CSKYISD
::
RET
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> bool ARMPassConfig :: addInstSelector ( ) { PM -> add ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> SDValue AArch64TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && Subtarget -> useRSqrt ( ) ) ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRSQRTE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setAllowReassociation ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Estimate , Flags ) ; Step = DAG . getNode ( AArch64ISD :: FRSQRTS , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Operand , Estimate , Flags ) ; ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> void aarch64_split_simd_move ( rtx dst , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { rtx ( * gen ) ( rtx , rtx ) ; gcc_assert ( VECTOR_MODE_P ( src_mode ) ) ; switch ( src_mode ) { case V16QImode : gen = gen_aarch64_split_simd_movv16qi ; break ; case V8HImode : gen = gen_aarch64_split_simd_movv8hi ; break ; case V4SImode : gen = gen_aarch64_split_simd_movv4si ; break ; case V2DImode : gen = gen_aarch64_split_simd_movv2di ; break ; case V8HFmode : gen = gen_aarch64_split_simd_movv8hf ; break ; case V4SFmode : gen = gen_aarch64_split_simd_movv4sf ; break ; case V2DFmode : gen = gen_aarch64_split_simd_movv2df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src ) ) ; return ; } } </s>


<s> static unsigned int pa_hard_regno_nregs ( unsigned int regno ATTRIBUTE_UNUSED , machine_mode mode ) { return PA_HARD_REGNO_NREGS ( regno , mode ) ; } </s>


"Unused function on X86. Otherwise need a test case."

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s>
SDValue
LC3TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> int system_reg_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { switch ( REGNO ( op ) ) { case PR_REG : case MACL_REG : case MACH_REG : return 1 ; } return 0 ; } </s>

Returns 1 if OP is MACL , MACH or PR . The input must be a REG rtx . Used only in general_movsrc_operand .


<s> const char * MMIXTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( MMIXISD :: NodeType ) Opcode ) { case MMIXISD :: FIRST_NUMBER : break ; case MMIXISD :: RET_FLAG : return "MMIXISD::RET_FLAG" ; case MMIXISD :: CALL : return "MMIXISD::CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , const_tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = DECL_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; machine_mode mode ; if ( ftype == error_mark_node ) continue ; mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && tree_fits_uhwi_p ( bit_position ( f ) ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode ) ) { unsigned n_fpreg = ( GET_MODE_SIZE ( mode ) + 7 ) >> 3 ; switch ( mode ) { case SCmode : mode = SFmode ; break ; case DCmode : mode = DFmode ; break ; case TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + 1 ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack = 1 ; } rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( mode == TFmode || mode == TDmode ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


<s> TargetTransformInfo :: PopcntSupportKind getPopcntSupport ( unsigned TyWidth ) { if ( TyWidth == 32 ) return TTI :: PSK_FastHardware ; return TTI :: PSK_Software ; } </s>

Return hardware support for population count .


<s> StringRef getSymbol ( ) const { return S ; } </s>

Get the target address and flags for the named symbol .


<s>
static
void
rs6000_sched_finish
(
FILE
*
dump
,
int
sched_verbose
)
{
int
n_groups
;
if
(
sched_verbose
)
fprintf
(
dump
,
"=== Finishing schedule.\n"
)
;
if
(
reload_completed
&&
rs6000_sched_groups
)
{
if
(
sel_sched_p
(
)
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_none
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_pad_groups
)
n_groups
=
pad_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
else
n_groups
=
redefine_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
if
(
sched_verbose
>=
6
)
{
fprintf
(
dump
,
"ngroups = %d\n"
,
n_groups
)
;
print_rtl
(
dump
,
current_sched_info
->
prev_head
)
;
fprintf
(
dump
,
"Done finish_sched\n"
)
;
}
}
}
</s>

The following function is called at the end of scheduling BB . After reload , it inserts nops at insn group bundling .


<s> void aarch64_split_simd_move ( rtx dst , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { rtx ( * gen ) ( rtx , rtx ) ; gcc_assert ( VECTOR_MODE_P ( src_mode ) ) ; switch ( src_mode ) { case E_V16QImode : gen = gen_aarch64_split_simd_movv16qi ; break ; case E_V8HImode : gen = gen_aarch64_split_simd_movv8hi ; break ; case E_V4SImode : gen = gen_aarch64_split_simd_movv4si ; break ; case E_V2DImode : gen = gen_aarch64_split_simd_movv2di ; break ; case E_V8HFmode : gen = gen_aarch64_split_simd_movv8hf ; break ; case E_V4SFmode : gen = gen_aarch64_split_simd_movv4sf ; break ; case E_V2DFmode : gen = gen_aarch64_split_simd_movv2df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src ) ) ; return ; } } </s>


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: TCRETURNdi ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) . addImm ( 0 ) ) ; return It ; } if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR , RegState :: Define ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return CallPt ; } </s>

Insert a call to an outlined function into the program .


<s> bool ARMBaseInstrInfo :: PredicateInstruction ( MachineInstr * MI , ArrayRef < MachineOperand > Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ 0 ] . getImm ( ) ) . addReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { X86AddressMode AM ; if ( ! X86SelectAddress ( LI -> getOperand ( 0 ) , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( ! Result ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> void MipsOutgoingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> bool SHUXIInstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) & X86 :: Mode64Bit ) != 0 ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool ARMTTIImpl :: isLoweredToCall ( const Function * F ) { if ( ! F -> isIntrinsic ( ) ) return BaseT :: isLoweredToCall ( F ) ; if ( F -> getName ( ) . startswith ( "llvm.arm" ) ) return false ; switch ( F -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: powi : case Intrinsic :: sin : case Intrinsic :: cos : case Intrinsic :: pow : case Intrinsic :: log : case Intrinsic :: log10 : case Intrinsic :: log2 : case Intrinsic :: exp : case Intrinsic :: exp2 : return true ; case Intrinsic :: sqrt : case Intrinsic :: fabs : case Intrinsic :: copysign : case Intrinsic :: floor : case Intrinsic :: ceil : case Intrinsic :: trunc : case Intrinsic :: rint : case Intrinsic :: nearbyint : case Intrinsic :: round : case Intrinsic :: canonicalize : case Intrinsic :: lround : case Intrinsic :: llround : case Intrinsic :: lrint : case Intrinsic :: llrint : if ( F -> getReturnType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( F -> getReturnType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return ! ST -> hasFPARMv8Base ( ) && ! ST -> hasVFP2Base ( ) ; case Intrinsic :: masked_store : case Intrinsic :: masked_load : case Intrinsic :: masked_gather : case Intrinsic :: masked_scatter : return ! ST -> hasMVEIntegerOps ( ) ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: sadd_sat : case Intrinsic :: uadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: usub_sat : return false ; } return BaseT :: isLoweredToCall ( F ) ; } </s>

Test whether calls to a function lower to actual program function calls .


Return a function that will generate a load of mode MODE_NO with speculation types TS .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned OpId ; switch ( Inst . getOpcode ( ) ) { default : OpId = 0 ; break ; case ARM :: t2WLS : case ARM :: t2LEUpdate : OpId = 2 ; break ; case ARM :: t2LE : OpId = 1 ; break ; } if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( OpId ) . getImm ( ) + 4 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> bool X86TargetLowering :: shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool ) const { if ( VT . isVector ( ) ) return false ; return VT . isSimple ( ) || ! isOperationExpand ( Opcode , VT ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr : return selectGetElementPtr ( I ) ; case Instruction :: AtomicCmpXchg : return selectAtomicCmpXchg ( cast < AtomicCmpXchgInst > ( I ) ) ; } ( void ) & CC_AArch64_DarwinPCS_VarArg ; ( void ) & CC_AArch64_Win64_VarArg ; return selectOperator ( I , I -> getOpcode ( ) ) ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool PPCFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , false , twoUniqueScratchRegsRequired ( TmpMBB ) ) ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> unsigned getOffsetOf ( MachineBasicBlock * MBB ) const { return BBInfo [ MBB -> getNumber ( ) ] . Offset ; } </s>

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> static int ix86_int_cmp_code_to_pcmp_immediate ( enum rtx_code code ) { switch ( code ) { case EQ : return 0 ; case LT : case LTU : return 1 ; case LE : case LEU : return 2 ; case NE : return 4 ; case GE : case GEU : return 5 ; case GT : case GTU : return 6 ; default : gcc_unreachable ( ) ; } } </s>

Helper for ix86_cmp_code_to_pcmp_immediate for int modes .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static unsigned int ix86_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( GENERAL_REGNO_P ( regno ) ) { if ( mode == XFmode ) return TARGET_64BIT ? 2 : 3 ; if ( mode == XCmode ) return TARGET_64BIT ? 4 : 6 ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } if ( COMPLEX_MODE_P ( mode ) ) return 2 ; if ( mode == V64SFmode || mode == V64SImode ) return 4 ; return 1 ; } </s>

Implement TARGET_HARD_REGNO_NREGS . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . Actually there are no two word move instructions for consecutive registers . And only registers 0-3 may have mov byte instructions applied to them .


"parameter passing for argument of type "

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
NumBytes
1
)
i
;
Data
[
Offset
+
Idx
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> int ix86_register_move_cost ( enum machine_mode mode , enum reg_class class1 , enum reg_class class2 ) { if ( ix86_secondary_memory_needed ( class1 , class2 , mode , 0 ) ) { int cost = 1 ; cost += MAX ( MEMORY_MOVE_COST ( mode , class1 , 0 ) , MEMORY_MOVE_COST ( mode , class1 , 1 ) ) ; cost += MAX ( MEMORY_MOVE_COST ( mode , class2 , 0 ) , MEMORY_MOVE_COST ( mode , class2 , 1 ) ) ; if ( CLASS_MAX_NREGS ( class1 , mode ) > CLASS_MAX_NREGS ( class2 , mode ) ) cost += 20 ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += 20 ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) || SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return ix86_cost -> mmxsse_to_integer ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> fp_move ; if ( MAYBE_SSE_CLASS_P ( class1 ) ) return ix86_cost -> sse_move ; if ( MAYBE_MMX_CLASS_P ( class1 ) ) return ix86_cost -> mmx_move ; return 2 ; } </s>

Return the cost of moving data from a register in class CLASS1 to one in class CLASS2 . It is not required that the cost always equal 2 when FROM is the same as TO ; on some machines it is expensive to move between registers if they are not general registers .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { auto * ReadFunc = IsLittleEndian ? support :: endian :: read32le : support :: endian :: read32be ; if ( STI . getFeatureBits ( ) [ PPC :: FeaturePrefixInstrs ] && Bytes . size ( ) >= 8 ) { uint32_t Prefix = ReadFunc ( Bytes . data ( ) ) ; uint32_t BaseInst = ReadFunc ( Bytes . data ( ) + 4 ) ; uint64_t Inst = BaseInst | ( uint64_t ) Prefix << 32 ; DecodeStatus result = decodeInstruction ( DecoderTable64 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = 8 ; return result ; } } Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint64_t Inst = ReadFunc ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } else if ( STI . getFeatureBits ( ) [ PPC :: FeatureSPE ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , DL ( computeDataLayout ( * this ) ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - 8 : - 4 ) , JITInfo ( hasSSE1 ( ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt ) ) return false ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> bool gen_ldm_seq ( rtx * operands , int nops , bool sort_regs ) { int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int i , j , base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int ldm_case ; rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == 0 ) return false ; if ( sort_regs ) for ( i = 0 ; i < nops - 1 ; i ++ ) for ( j = i + 1 ; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) { int t = regs [ i ] ; regs [ i ] = regs [ j ] ; regs [ j ] = t ; } base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; if ( TARGET_THUMB1 ) { gcc_assert ( ldm_case == 1 || ldm_case == 5 ) ; write_back = true ; for ( i = 0 ; i < nops ; i ++ ) if ( base_reg == regs [ i ] ) write_back = false ; if ( write_back && ! peep2_reg_dead_p ( nops , base_reg_rtx ) ) return false ; } if ( ldm_case == 5 ) { rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG ( SImode , regs [ 0 ] ) ; emit_insn ( gen_addsi3 ( newbase , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = 0 ; base_reg_rtx = newbase ; } for ( i = 0 ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , 0 ) ; } emit_insn ( arm_gen_load_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * 4 : 0 ) ) ; return true ; } </s>

Called from a peephole2 expander to turn a sequence of loads into an LDM instruction . OPERANDS are the operands found by the peephole matcher ; NOPS indicates how many separate loads we are trying to combine . SORT_REGS is true if we can reorder the registers because they are used commutatively subsequently . Returns true iff we could generate a new instruction .


<s> void PPC64LinuxTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s>
static
void
arm_unwind_emit_stm
(
FILE
*
asm_out_file
,
rtx
p
)
{
int
i
;
HOST_WIDE_INT
offset
;
HOST_WIDE_INT
nregs
;
int
reg_size
;
unsigned
reg
;
unsigned
lastreg
;
rtx
e
;
e
=
XVECEXP
(
p
,
0
,
0
)
;
if
(
GET_CODE
(
e
)
!=
SET
||
GET_CODE
(
XEXP
(
e
,
0
)
)
!=
REG
||
REGNO
(
XEXP
(
e
,
0
)
)
!=
SP_REGNUM
||
GET_CODE
(
XEXP
(
e
,
1
)
)
!=
PLUS
)
abort
(
)
;
offset
=
INTVAL
(
XEXP
(
XEXP
(
e
,
1
)
,
1
)
)
;
nregs
=
XVECLEN
(
p
,
0
)
1
;
reg
=
REGNO
(
XEXP
(
XVECEXP
(
p
,
0
,
1
)
,
1
)
)
;
if
(
reg
<
16
)
{
if
(
nregs
*
4
==
offset
4
)
{
fprintf
(
asm_out_file
,
"\t.pad #4\n"
)
;
offset
-=
4
;
}
reg_size
=
4
;
}
else
if
(
IS_VFP_REGNUM
(
reg
)
)
{
offset
-=
4
;
reg_size
=
8
;
}
else
if
(
reg
>=
FIRST_FPA_REGNUM
&&
reg
<=
LAST_FPA_REGNUM
)
{
asm_fprintf
(
asm_out_file
,
"\t.save %r, %wd\n"
,
reg
,
nregs
)
;
return
;
}
else
abort
(
)
;
if
(
offset
!=
nregs
*
reg_size
)
abort
(
)
;
fprintf
(
asm_out_file
,
"\t.save {"
)
;
offset
=
0
;
lastreg
=
0
;
for
(
i
=
1
;
i
<=
nregs
;
i
++
)
{
e
=
XVECEXP
(
p
,
0
,
i
)
;
if
(
GET_CODE
(
e
)
!=
SET
||
GET_CODE
(
XEXP
(
e
,
0
)
)
!=
MEM
||
GET_CODE
(
XEXP
(
e
,
1
)
)
!=
REG
)
abort
(
)
;
reg
=
REGNO
(
XEXP
(
e
,
1
)
)
;
if
(
reg
<
lastreg
)
abort
(
)
;
if
(
i
!=
1
)
fprintf
(
asm_out_file
,
", "
)
;
if
(
IS_VFP_REGNUM
(
reg
)
)
asm_fprintf
(
asm_out_file
,
"d%d"
,
(
reg
FIRST_VFP_REGNUM
)
/
2
)
;
else
asm_fprintf
(
asm_out_file
,
"%r"
,
reg
)
;
e
=
XEXP
(
XEXP
(
e
,
0
)
,
0
)
;
if
(
GET_CODE
(
e
)
==
PLUS
)
{
offset
+=
reg_size
;
if
(
GET_CODE
(
XEXP
(
e
,
0
)
)
!=
REG
||
REGNO
(
XEXP
(
e
,
0
)
)
!=
SP_REGNUM
||
GET_CODE
(
XEXP
(
e
,
1
)
)
!=
CONST_INT
||
offset
!=
INTVAL
(
XEXP
(
e
,
1
)
)
)
abort
(
)
;
}
else
if
(
i
!=
1
||
GET_CODE
(
e
)
!=
REG
||
REGNO
(
e
)
!=
SP_REGNUM
)
abort
(
)
;
}
fprintf
(
asm_out_file
,
"}\n"
)
;
}
</s>

Emit unwind directives for a store-multiple instruction . This should only ever be generated by the function prologue code , so we expect it to have a particular form .


" (e.g. %<-mfloat-abi=softfp%> %<-mfpu=neon%>)"

"%Klane index must be a constant immediate"

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s> static void pru_elf_asm_destructor ( rtx symbol , int priority ) { char buf [ 23 ] ; section * s ; if ( priority == DEFAULT_INIT_PRIORITY ) snprintf ( buf , sizeof ( buf ) , ".fini_array" ) ; else { snprintf ( buf , sizeof ( buf ) , ".fini_array.%.5u" , priority ) ; } s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s ) ; assemble_aligned_integer ( INIT_ARRAY_ENTRY_BYTES , symbol ) ; } </s>


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; Reserved . set ( ARM :: APSR_NZCV ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool fp_zero_operand ( rtx op ) { const REAL_VALUE_TYPE * r ; if ( GET_MODE ( op ) != SFmode ) return false ; r = CONST_DOUBLE_REAL_VALUE ( op ) ; return real_equal ( r , & dconst0 ) && ! REAL_VALUE_MINUS_ZERO ( * r ) ; } </s>

Returns true if OP is a floating point value with value 0.0 .


<s> bool AArch64Subtarget :: useAA ( ) const { return UseAA ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
)
return
TargetInstrInfoImpl
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
MCOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
RegState
::
Define
|
getDeadRegState
(
Reg0IsDead
)
)
.
addReg
(
Reg2
,
getKillRegState
(
Reg2IsKill
)
)
.
addReg
(
Reg1
,
getKillRegState
(
Reg1IsKill
)
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s> static void sparc_handle_vis_mul8x16 ( vec < tree > * n_elts , enum sparc_builtins fncode , tree inner_type , tree cst0 , tree cst1 ) { unsigned i , num = VECTOR_CST_NELTS ( cst0 ) ; int scale ; switch ( fncode ) { case SPARC_BUILTIN_FMUL8X16 : for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , i ) ) ) ; n_elts -> quick_push ( build_int_cst ( inner_type , val ) ) ; } break ; case SPARC_BUILTIN_FMUL8X16AU : scale = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , 0 ) ) ; for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , scale ) ; n_elts -> quick_push ( build_int_cst ( inner_type , val ) ) ; } break ; case SPARC_BUILTIN_FMUL8X16AL : scale = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst1 , 1 ) ) ; for ( i = 0 ; i < num ; ++ i ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( VECTOR_CST_ELT ( cst0 , i ) ) , scale ) ; n_elts -> quick_push ( build_int_cst ( inner_type , val ) ) ; } break ; default : gcc_unreachable ( ) ; } } </s>

Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified by FNCODE . All of the elements in ELTS0 and ELTS1 lists must be integer constants . A tree list with the results of the multiplications is returned , and each element in the list is of INNER_TYPE .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT ValTy ( VA . getValVT ( ) ) ; LLT LocTy ( VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == MVT :: i8 || VA . getValVT ( ) == MVT :: i16 ) std :: swap ( ValTy , LocTy ) ; else { assert ( LocTy . getSizeInBits ( ) == MemTy . getSizeInBits ( ) ) ; LocTy = MemTy ; } auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , LocTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: LocInfo :: ZExt : MIRBuilder . buildLoadInstr ( TargetOpcode :: G_ZEXTLOAD , ValVReg , Addr , * MMO ) ; return ; case CCValAssign :: LocInfo :: SExt : MIRBuilder . buildLoadInstr ( TargetOpcode :: G_SEXTLOAD , ValVReg , Addr , * MMO ) ; return ; default : MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; return ; } } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static void mips_annotate_pic_calls ( void ) { basic_block bb ; rtx_insn * insn ; FOR_EACH_BB_FN ( bb , cfun ) FOR_BB_INSNS ( bb , insn ) { rtx call , reg , symbol , second_call ; second_call = 0 ; call = mips_call_expr_from_insn ( insn , & second_call ) ; if ( ! call ) continue ; gcc_assert ( MEM_P ( XEXP ( call , 0 ) ) ) ; reg = XEXP ( XEXP ( call , 0 ) , 0 ) ; if ( ! REG_P ( reg ) ) continue ; symbol = mips_find_pic_call_symbol ( insn , reg , true ) ; if ( symbol ) { mips_annotate_pic_call_expr ( call , symbol ) ; if ( second_call ) mips_annotate_pic_call_expr ( second_call , symbol ) ; } } } </s>

Use DF to annotate PIC indirect calls with the function symbol they dispatch to .


<s> bool MipsPassConfig :: addInstSelector ( ) { addPass ( createMipsModuleISelDagPass ( ) ) ; addPass ( createMips16ISelDag ( getMipsTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createMipsSEISelDag ( getMipsTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> int ARMAsmParser :: tryParseRegister ( ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r13" , ARM :: SP ) . Case ( "r14" , ARM :: LR ) . Case ( "r15" , ARM :: PC ) . Case ( "ip" , ARM :: R12 ) . Case ( "a1" , ARM :: R0 ) . Case ( "a2" , ARM :: R1 ) . Case ( "a3" , ARM :: R2 ) . Case ( "a4" , ARM :: R3 ) . Case ( "v1" , ARM :: R4 ) . Case ( "v2" , ARM :: R5 ) . Case ( "v3" , ARM :: R6 ) . Case ( "v4" , ARM :: R7 ) . Case ( "v5" , ARM :: R8 ) . Case ( "v6" , ARM :: R9 ) . Case ( "v7" , ARM :: R10 ) . Case ( "v8" , ARM :: R11 ) . Case ( "sb" , ARM :: R9 ) . Case ( "sl" , ARM :: R10 ) . Case ( "fp" , ARM :: R11 ) . Default ( 0 ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - 1 ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; } Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> static const char * rs6000_xcoff_visibility ( tree decl ) { static const char * const visibility_types [ ] = { "" , ",protected" , ",hidden" , ",internal" } ; enum symbol_visibility vis = DECL_VISIBILITY ( decl ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && cgraph_node :: get ( decl ) && cgraph_node :: get ( decl ) -> instrumentation_clone && cgraph_node :: get ( decl ) -> instrumented_version ) vis = DECL_VISIBILITY ( cgraph_node :: get ( decl ) -> instrumented_version -> decl ) ; return visibility_types [ vis ] ; } </s>

Helper function to calculate visibility of a DECL and return the value as a const string .

powerpcspe "" ",protected" ",hidden" ",internal"


<s> static void pa_init_libfuncs ( void ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( sqrt_optab , TFmode , "_U_Qfsqrt" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; set_optab_libfunc ( unord_optab , TFmode , "_U_Qfunord" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" : "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_usgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_udbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , SImode , "_U_Qfcnvxf_usgl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , "_U_Qfcnvxf_udbl_to_quad" ) ; } if ( TARGET_SYNC_LIBCALL ) init_sync_libfuncs ( 8 ) ; } </s>

Initialize optabs to point to emulation routines .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MMI
=
&
getAnalysis
<
MachineModuleInfo
>
(
)
;
MCE
.
setModuleInfo
(
MMI
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getDataLayout
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
MCInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
++
NumEmitted
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static ia64_addr_area ia64_get_addr_area ( tree decl ) { tree model_attr ; model_attr = lookup_attribute ( "model" , DECL_ATTRIBUTES ( decl ) ) ; if ( model_attr ) { tree id ; init_idents ( ) ; id = TREE_VALUE ( TREE_VALUE ( model_attr ) ) ; if ( id == small_ident1 || id == small_ident2 ) return ADDR_AREA_SMALL ; } return ADDR_AREA_NORMAL ; } </s>

Retrieve the address area that has been chosen for the given decl .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool Warning ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return getParser ( ) . Warning ( L , Msg , Ranges ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


Return an array that contains the bitmask target flag values and their names .


<s> static rtx gen_safe_HIGH64 ( rtx dest , HOST_WIDE_INT val ) { return gen_rtx_SET ( dest , GEN_INT ( val & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ; } </s>

The optimizer is not to assume anything about exactly which bits are set for a HIGH , they are unspecified . Unfortunately this leads to many missed optimizations during CSE . We mask out the non-HIGH bits , and matches a plain movdi , to alleviate this problem .


<s> static bool check_required_extensions ( location_t location , tree fndecl , aarch64_feature_flags required_extensions ) { auto missing_extensions = required_extensions & ~ aarch64_asm_isa_flags ; if ( missing_extensions == 0 ) return check_required_registers ( location , fndecl ) ; static const struct { aarch64_feature_flags flag ; const char * name ; } extensions [ ] = { { AARCH64_FL_ ## IDENT , EXT_NAME } , } ; for ( unsigned int i = 0 ; i < ARRAY_SIZE ( extensions ) ; ++ i ) if ( missing_extensions & extensions [ i ] . flag ) { report_missing_extension ( location , fndecl , extensions [ i ] . name ) ; return false ; } gcc_unreachable ( ) ; } </s>

Check whether all the RVV_REQUIRE_ * values in REQUIRED_EXTENSIONS are enabled .


<s>
void
xstormy16_output_addr_vec
(
FILE
*
file
,
rtx
label
ATTRIBUTE_UNUSED
,
rtx
table
)
{
int
vlen
,
idx
;
switch_to_section
(
current_function_section
(
)
)
;
vlen
=
XVECLEN
(
table
,
0
)
;
for
(
idx
=
0
;
idx
<
vlen
;
idx
++
)
{
fputs
(
"\tjmpf "
,
file
)
;
output_asm_label
(
XEXP
(
XVECEXP
(
table
,
0
,
idx
)
,
0
)
)
;
fputc
(
'\n'
,
file
)
;
}
}
</s>

Output an ADDR_VEC . It is output as a sequence of 'jmpf ' instructions , without label or alignment or any other special constructs . We know that the previous instruction will be the ` tablejump_pcrel ' output above . TODO : it might be nice to output 'br ' instructions if they could all reach .


<s> const MCExpr * createExprForCAPIVariantKind ( const MCExpr * SubExpr , unsigned VariantKind ) override { switch ( VariantKind ) { case LLVMDisassembler_VariantKind_ARM_HI16 : return ARMMCExpr :: createUpper16 ( SubExpr , Ctx ) ; case LLVMDisassembler_VariantKind_ARM_LO16 : return ARMMCExpr :: createLower16 ( SubExpr , Ctx ) ; default : return MCRelocationInfo :: createExprForCAPIVariantKind ( SubExpr , VariantKind ) ; } } </s>

Create an MCExpr for the target-specific VariantKind .


<s> void ix86_expand_sse2_abs ( rtx target , rtx input ) { machine_mode mode = GET_MODE ( target ) ; rtx tmp0 , tmp1 , x ; switch ( mode ) { case V4SImode : tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) - 1 ) , NULL , 0 , OPTAB_DIRECT ) ; tmp1 = expand_simple_binop ( mode , XOR , tmp0 , input , NULL , 0 , OPTAB_DIRECT ) ; x = expand_simple_binop ( mode , MINUS , tmp1 , tmp0 , target , 0 , OPTAB_DIRECT ) ; break ; case V8HImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( mode , SMAX , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; case V16QImode : tmp0 = expand_unop ( mode , neg_optab , input , NULL_RTX , 0 ) ; x = expand_simple_binop ( V16QImode , UMIN , tmp0 , input , target , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } if ( x != target ) emit_move_insn ( target , x ) ; } </s>

Calculate integer abs ( ) using only SSE2 instructions .


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MoveR3216
;
else
if
(
Mips
::
CPURegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
CPU16RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
else
if
(
(
SrcReg
==
Mips
::
HI
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mfhi16
,
SrcReg
=
0
;
else
if
(
(
SrcReg
==
Mips
::
LO
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mflo16
,
SrcReg
=
0
;
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool MipsAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { const unsigned FixupKind = Fixup . getKind ( ) ; switch ( FixupKind ) { default : return false ; case Mips :: fixup_Mips_CALL_HI16 : case Mips :: fixup_Mips_CALL_LO16 : case Mips :: fixup_Mips_CALL16 : case Mips :: fixup_Mips_GOT : case Mips :: fixup_Mips_GOT_PAGE : case Mips :: fixup_Mips_GOT_OFST : case Mips :: fixup_Mips_GOT_DISP : case Mips :: fixup_Mips_GOT_HI16 : case Mips :: fixup_Mips_GOT_LO16 : case Mips :: fixup_Mips_GOTTPREL : case Mips :: fixup_Mips_DTPREL_HI : case Mips :: fixup_Mips_DTPREL_LO : case Mips :: fixup_Mips_TLSGD : case Mips :: fixup_Mips_TLSLDM : case Mips :: fixup_Mips_TPREL_HI : case Mips :: fixup_Mips_TPREL_LO : case Mips :: fixup_Mips_JALR : case Mips :: fixup_MICROMIPS_CALL16 : case Mips :: fixup_MICROMIPS_GOT_DISP : case Mips :: fixup_MICROMIPS_GOT_PAGE : case Mips :: fixup_MICROMIPS_GOT_OFST : case Mips :: fixup_MICROMIPS_GOT16 : case Mips :: fixup_MICROMIPS_GOTTPREL : case Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 : case Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 : case Mips :: fixup_MICROMIPS_TLS_GD : case Mips :: fixup_MICROMIPS_TLS_LDM : case Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 : case Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 : case Mips :: fixup_MICROMIPS_JALR : case Mips :: fixup_CHERI_CAPTAB_TLSGD_HI16 : case Mips :: fixup_CHERI_CAPTAB_TLSGD_LO16 : case Mips :: fixup_CHERI_CAPTAB_TLSLDM_HI16 : case Mips :: fixup_CHERI_CAPTAB_TLSLDM_LO16 : case Mips :: fixup_CHERI_CAPTAB_TPREL_HI16 : case Mips :: fixup_CHERI_CAPTAB_TPREL_LO16 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
static
rtx
nds32_expand_builtin_reg_ftype_imm
(
enum
insn_code
icode
,
tree
exp
,
rtx
target
)
{
struct
expand_operand
ops
[
2
]
;
tree
arg0
;
rtx
value0
;
arg0
=
CALL_EXPR_ARG
(
exp
,
0
)
;
value0
=
expand_normal
(
arg0
)
;
create_output_operand
(
&
ops
[
0
]
,
target
,
TYPE_MODE
(
TREE_TYPE
(
exp
)
)
)
;
create_input_operand
(
&
ops
[
1
]
,
value0
,
TYPE_MODE
(
TREE_TYPE
(
arg0
)
)
)
;
if
(
!
maybe_expand_insn
(
icode
,
2
,
ops
)
)
error
(
"invalid argument to built-in function"
)
;
return
target
;
}
</s>

Function to expand builtin function for ' [ ( set ( reg ) ( unspec_volatile [ ( imm ) ] ) ) ] ' .


"Should be handled target independently"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> rtx thumb_legitimize_address ( rtx x , rtx orig_x , machine_mode mode ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && ( INTVAL ( XEXP ( x , 1 ) ) >= 32 * GET_MODE_SIZE ( mode ) || INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset >= 0 && offset < 256 + 31 * GET_MODE_SIZE ( mode ) ) { HOST_WIDE_INT delta ; if ( offset >= 256 ) delta = offset - ( 256 - GET_MODE_SIZE ( mode ) ) ; else if ( offset < 32 * GET_MODE_SIZE ( mode ) + 8 ) delta = 31 * GET_MODE_SIZE ( mode ) ; else delta = offset & ( ~ 31 * GET_MODE_SIZE ( mode ) ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - delta ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , delta ) ; } else if ( offset < 0 && offset > - 256 ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , 1 ) , SImode ) && ! s_register_operand ( XEXP ( x , 0 ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , 1 ) ) ; } if ( flag_pic ) { rtx new_x = legitimize_pic_address ( orig_x , mode , NULL_RTX ) ; if ( new_x != orig_x ) x = new_x ; } return x ; } </s>

Try machine-dependent ways of modifying an illegitimate Thumb address to be legitimate . If we find one , return the new , valid address .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
STI
.
getSchedModel
(
)
,
&
STI
,
TII
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
.
begin
(
)
,
MLI
.
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>


<s> static rtx_insn * mips_epilogue_emit_cfa_restores ( void ) { rtx_insn * insn ; insn = get_last_insn ( ) ; gcc_assert ( insn && ! REG_NOTES ( insn ) ) ; if ( mips_epilogue . cfa_restores ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = mips_epilogue . cfa_restores ; mips_epilogue . cfa_restores = 0 ; } return insn ; } </s>

Attach all pending register saves to the previous instruction . Return that instruction .


<s> static bool ix86_hard_regno_scratch_ok ( unsigned int regno ) { return ( ! cfun -> machine -> no_caller_saved_registers || ( ! epilogue_completed && df_regs_ever_live_p ( regno ) ) ) ; } </s>

Return nonzero if register REGNO can be used as a scratch register in peephole2 .


<s> static int rs6000_use_sched_lookahead_guard ( rtx_insn * insn , int ready_index ) { if ( ready_index == 0 ) return 0 ; if ( rs6000_cpu_attr != CPU_CELL ) return 0 ; gcc_assert ( insn != NULL_RTX && INSN_P ( insn ) ) ; if ( ! reload_completed || is_nonpipeline_insn ( insn ) || is_microcoded_insn ( insn ) ) return 1 ; return 0 ; } </s>

We are choosing insn from the ready queue . Return zero if INSN can be chosen .


<s> void FISCAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>


<s> bool isReg ( ) const override { return Kind == KindTy :: Register ; } </s>


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == ARM :: t2LoopEndDec || MI -> getOpcode ( ) == ARM :: t2DoLoopStartTP || MI -> getOpcode ( ) == ARM :: t2WhileLoopStartLR ; } </s>

Return true if the given terminator MI is not expected to spill .


<s>
void
SystemZInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32rm
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Prm
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128rm
;
}
else
llvm_unreachable
(
"Unsupported regclass to load"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
,
FrameIdx
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool SparcFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void AArch64_ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> static bool nds32_address_register_rtx_p ( rtx x , bool strict ) { int regno ; if ( GET_CODE ( x ) != REG ) return false ; regno = REGNO ( x ) ; if ( strict ) return REGNO_OK_FOR_BASE_P ( regno ) ; else return true ; } </s>

Function that check if ' X ' is a valid address register . The variable 'STRICT ' is very important to make decision for register number . STRICT : true = > We are in reload pass or after reload pass . The register number should be strictly limited in general registers . STRICT : false = > Before reload pass , we are free to use any register number .