<s> rtx rs6000_emit_set_const ( rtx dest , enum machine_mode mode , rtx source , int n ATTRIBUTE_UNUSED ) { rtx result , insn , set ; HOST_WIDE_INT c0 , c1 ; switch ( mode ) { case QImode : case HImode : if ( dest == NULL ) dest = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , source ) ) ; return dest ; case SImode : result = no_new_pseudos ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , result , GEN_INT ( INTVAL ( source ) & ( ~ ( HOST_WIDE_INT ) 0xffff ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IOR ( SImode , result , GEN_INT ( INTVAL ( source ) & 0xffff ) ) ) ) ; result = dest ; break ; case DImode : switch ( GET_CODE ( source ) ) { case CONST_INT : c0 = INTVAL ( source ) ; c1 = - ( c0 < 0 ) ; break ; case CONST_DOUBLE : c0 = CONST_DOUBLE_LOW ( source ) ; c1 = - ( c0 < 0 ) ; c0 = CONST_DOUBLE_LOW ( source ) ; c1 = CONST_DOUBLE_HIGH ( source ) ; break ; default : gcc_unreachable ( ) ; } result = rs6000_emit_set_long_const ( dest , c0 , c1 ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , source ) ; return result ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s> std :: unique_ptr < PBQPRAConstraint > AArch64Subtarget :: getCustomPBQPConstraints ( ) const { if ( ! isCortexA57 ( ) ) return nullptr ; return llvm :: make_unique < A57ChainingConstraint > ( ) ; } </s>

Return PBQPConstraint ( s ) for the target .


<s> bool X86TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { for ( const APFloat & FPImm : LegalFPImmediates ) if ( Imm . bitwiseIsEqual ( FPImm ) ) return true ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> void FISCInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
const
char
*
aarch64_output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
output_asm_insn
(
"str\txzr, [%0]"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tb.ne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> static machine_mode rs6000_translate_mode_attribute ( machine_mode mode ) { if ( ( FLOAT128_IEEE_P ( mode ) && ieee128_float_type_node == long_double_type_node ) || ( FLOAT128_IBM_P ( mode ) && ibm128_float_type_node == long_double_type_node ) ) return COMPLEX_MODE_P ( mode ) ? E_TCmode : E_TFmode ; return mode ; } </s>

Target hook for translate_mode_attribute .


<s> bool isPredicated ( const MachineInstr * MI ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ; } </s>

Returns true if the instruction is already predicated .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return 0 ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return 0 ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( this , 0 , SawStore ) ) return 0 ; unsigned IdxEnd = ( MI -> isCommutable ( ) ) ? 2 : 1 ; for ( unsigned Idx = 0 ; Idx < IdxEnd ; Idx ++ ) { unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return 0 ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return 0 ; SmallVector < unsigned , 8 > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } if ( Idx == 1 ) { commuteInstruction ( MI , false ) ; return 0 ; } if ( MI -> isCommutable ( ) ) { MachineInstr * NewMI = commuteInstruction ( MI , false ) ; if ( ! NewMI ) return 0 ; if ( NewMI != MI ) { NewMI -> eraseFromParent ( ) ; return 0 ; } } } return 0 ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
.
getName
(
)
<<
" ------------- \n"
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> unsigned ARMFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , unsigned Op1 ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .

ARM ARM::GPRRegClass ARM::tGPRRegClass ARM::tcGPRRegClass ARM::rGPRRegClass ARM::GPRnopcRegClass ARM::t2STRi12 0 ARM


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax_rex"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
32
,
0
}
,
{
"reloc_signed_4byte_relax"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
64
,
0
}
,
{
"reloc_branch_4byte_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
assert
(
Infos
[
Kind
FirstTargetFixupKind
]
.
Name
&&
"Empty fixup name!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"interrupt and naked attributes are not compatible"

"only DWARF debug format is supported for interrupt "

Set the func_type field from the function FNDECL .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static machine_mode rx_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { unsigned f ; if ( m1 == m2 ) return m1 ; f = flags_from_mode ( m1 ) | flags_from_mode ( m2 ) ; if ( f & CC_FLAG_FP ) return VOIDmode ; return mode_from_flags ( f ) ; } </s>

Return a CC_MODE of which both M1 and M2 are subsets .


<s> static enum reg_class init_unavailable ( tag_insn_info * insn_info , tag_map_t & tag_map , du_head_p head , HARD_REG_SET * unavailable ) { unsigned dest = head -> regno ; enum reg_class super_class = NO_REGS ; machine_mode mode = GET_MODE ( insn_info -> dest ) ; CLEAR_HARD_REG_SET ( * unavailable ) ; for ( struct du_chain * tmp = head -> first ; tmp ; tmp = tmp -> next_use ) { if ( DEBUG_INSN_P ( tmp -> insn ) ) continue ; IOR_COMPL_HARD_REG_SET ( * unavailable , reg_class_contents [ tmp -> cl ] ) ; super_class = reg_class_superunion [ ( int ) super_class ] [ ( int ) tmp -> cl ] ; } for ( unsigned i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( fixed_regs [ i ] || global_regs [ i ] ) add_to_hard_reg_set ( unavailable , mode , i ) ; arg_pair_t arg = arg_pair_t ( insn_info , unavailable ) ; tag_map . traverse < arg_pair_t * , check_colliding_tags > ( & arg ) ; ignore_all_aliases ( unavailable , mode , dest & 0xf ) ; return super_class ; } </s>

Initialize and build a set of hard register numbers UNAVAILABLE to avoid for renaming . INSN_INFO is the original insn , TAG_MAP is the map of the list of insns indexed by their tags , HEAD is the def/use chain head of the destination register of the original insn . The routine returns the super class of register classes that may be used during the renaming .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static sbitmap aarch64_components_for_bb ( basic_block bb ) { bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ( ! call_used_regs [ regno ] ) && ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { unsigned regno2 , offset , offset2 ; bitmap_set_bit ( components , regno ) ; offset = cfun -> machine -> frame . reg_offset [ regno ] ; regno2 = ( ( offset & 8 ) == 0 ) ? regno + 1 : regno - 1 ; if ( regno2 <= LAST_SAVED_REGNUM ) { offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ( offset & ~ 8 ) == ( offset2 & ~ 8 ) ) bitmap_set_bit ( components , regno2 ) ; } } return components ; } </s>


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FP_TO_SINT ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::SELECT ISD::SETCC


<s> enum direction function_arg_padding ( machine_mode mode , const_tree type ) { if ( TARGET_ARCH64 && type && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

Handle the FUNCTION_ARG_PADDING macro . For the 64 bit ABI structs are always stored left shifted in their argument slot .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
void
MipsRegisterBankInfo
::
setRegBank
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
)
const
{
Register
Dest
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_STORE
:
break
;
case
TargetOpcode
::
G_CONSTANT
:
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_SELECT
:
case
TargetOpcode
::
G_PHI
:
case
TargetOpcode
::
G_IMPLICIT_DEF
:
{
assert
(
MRI
.
getType
(
Dest
)
==
LLT
::
scalar
(
32
)
&&
"Unexpected operand type."
)
;
MRI
.
setRegBank
(
Dest
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
break
;
}
case
TargetOpcode
::
G_GEP
:
{
assert
(
MRI
.
getType
(
Dest
)
.
isPointer
(
)
&&
"Unexpected operand type."
)
;
MRI
.
setRegBank
(
Dest
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
break
;
}
default
:
llvm_unreachable
(
"Unexpected opcode."
)
;
}
}
</s>

RegBankSelect determined that s64 operand is better to be split into two s32 operands in gprb .

Mips
Mips
0
32
"Unexpected operand type."
Mips::GPRBRegBankID
"Unexpected operand type."
Mips::GPRBRegBankID
"Unexpected opcode."


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
case
AArch64
::
ZPRRegClassID
:
case
AArch64
::
ZPR2RegClassID
:
case
AArch64
::
ZPR3RegClassID
:
case
AArch64
::
ZPR4RegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> void SystemZMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { unsigned Opcode = MI -> getOpcode ( ) ; if ( ! AsmPrinter . OutStreamer . hasRawTextSupport ( ) ) Opcode = getShortenedInstr ( Opcode ) ; OutMI . setOpcode ( Opcode ) ; for ( unsigned I = 0 , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ; } } </s>


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { tree type ; if ( decl ) { if ( TARGET_ALTIVEC_VRSAVE ) { for ( type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; type ; type = TREE_CHAIN ( type ) ) { if ( TREE_CODE ( TREE_VALUE ( type ) ) == VECTOR_TYPE ) return false ; } } if ( DEFAULT_ABI == ABI_DARWIN || ( * targetm . binds_local_p ) ( decl ) ) { tree attr_list = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> bool aarch_bti_enabled ( void ) { return aarch_enable_bti != 0 ; } </s>

Return TRUE if Branch Target Identification Mechanism is enabled .


"alias without a base object is not yet supported on AIX"

Set up the AsmPrinter when we are working on a new module .


<s> bool PPCFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , false , nullptr ) ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , PPC :: ZERO ) ; markSuperRegs ( Reserved , PPC :: FP ) ; markSuperRegs ( Reserved , PPC :: BP ) ; markSuperRegs ( Reserved , PPC :: CTR ) ; markSuperRegs ( Reserved , PPC :: CTR8 ) ; markSuperRegs ( Reserved , PPC :: R1 ) ; markSuperRegs ( Reserved , PPC :: LR ) ; markSuperRegs ( Reserved , PPC :: LR8 ) ; markSuperRegs ( Reserved , PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( ! TM . isPPC64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; markSuperRegs ( Reserved , PPC :: R13 ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , PPC :: R2 ) ; if ( TM . isPPC64 ( ) ) markSuperRegs ( Reserved , PPC :: R13 ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R29 ) ; else markSuperRegs ( Reserved , PPC :: R30 ) ; } if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) markSuperRegs ( Reserved , * I ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static rtx altivec_expand_st_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 ; machine_mode mode0 , mode1 ; rtx pat , op0 , op1 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_ST_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_store_v16qi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_store_v8hi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4si : icode = CODE_FOR_vector_altivec_store_v4si ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_store_v4sf ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2df : icode = CODE_FOR_vector_altivec_store_v2df ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2di : icode = CODE_FOR_vector_altivec_store_v2di ; case ALTIVEC_BUILTIN_ST_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_store_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; mode1 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp = true ; return NULL_RTX ; } </s>


<s> static inline void aarch64_sub_sp ( int scratchreg , HOST_WIDE_INT delta , bool frame_related_p ) { aarch64_add_constant_internal ( Pmode , SP_REGNUM , scratchreg , - delta , frame_related_p , true ) ; } </s>

Subtract DELTA from the stack pointer , marking the instructions frame-related if FRAME_RELATED_P . TEMP1 is available as a temporary if nonnull .


<s> const SICRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool SparcAsmPrinter :: doFinalization ( Module & M ) { for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I ) ; O << '\n' ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>


<s> extern machine_mode vax_select_cc_mode ( enum rtx_code op , rtx x ATTRIBUTE_UNUSED , rtx y ATTRIBUTE_UNUSED ) { switch ( op ) { default : gcc_unreachable ( ) ; case NE : case EQ : return CCZmode ; case GE : case LT : return CCNmode ; case GT : case LE : return CCNZmode ; case GEU : case GTU : case LEU : case LTU : return CCmode ; } } </s>

Given a comparison code ( NE , EQ , etc . ) and the operands of a COMPARE , return the mode to be used for the comparison . As we have the same interpretation of condition codes across all the instructions we just return the narrowest mode suitable for the comparison code requested .


"rs6000_get_function_version_priority (%s) => %d\n"

Return the clone id of the target we are compiling code for in a target clone . The clone id is ordered from 0 ( default ) to CLONE_MAX-1 and gives the priority list for the target clones ( ordered from lowest to highest ) .


<s> static void rs6000_expand_vector_set_var_p9 ( rtx target , rtx val , rtx idx ) { machine_mode mode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( idx ) ) ; machine_mode inner_mode = GET_MODE ( val ) ; int width = GET_MODE_SIZE ( inner_mode ) ; gcc_assert ( width >= 1 && width <= 8 ) ; int shift = exact_log2 ( width ) ; machine_mode idx_mode = GET_MODE ( idx ) ; machine_mode shift_mode ; rtx ( * gen_ashl ) ( rtx , rtx , rtx ) ; rtx ( * gen_lvsl ) ( rtx , rtx ) ; rtx ( * gen_lvsr ) ( rtx , rtx ) ; if ( TARGET_POWERPC64 ) { shift_mode = DImode ; gen_ashl = gen_ashldi3 ; gen_lvsl = gen_altivec_lvsl_reg_di ; gen_lvsr = gen_altivec_lvsr_reg_di ; } else { shift_mode = SImode ; gen_ashl = gen_ashlsi3 ; gen_lvsl = gen_altivec_lvsl_reg_si ; gen_lvsr = gen_altivec_lvsr_reg_si ; } rtx tmp = gen_reg_rtx ( shift_mode ) ; idx = convert_modes ( shift_mode , idx_mode , idx , 1 ) ; emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; rtx pcvr = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_lvsr ( pcvr , tmp ) ) ; rtx pcvl = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_lvsl ( pcvl , tmp ) ) ; rtx sub_target = simplify_gen_subreg ( V16QImode , target , mode , 0 ) ; rtx permr = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvr ) ; emit_insn ( permr ) ; rs6000_expand_vector_set ( target , val , const0_rtx ) ; rtx perml = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvl ) ; emit_insn ( perml ) ; } </s>

Insert VAL into IDX of TARGET , VAL size is same of the vector element , IDX is variable and also counts by vector element size for p9 and above .


<s> static void ia64_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS next_cum = * get_cumulative_args ( cum ) ; ia64_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , 1 ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine -> n_varargs = n ; } } </s>

Do any needed setup for a variadic function . CUM has not been updated for the last named argument which has type TYPE and mode MODE . We generate the actual spill instructions during prologue generation .


<s> static void setup_incoming_varargs_64 ( CUMULATIVE_ARGS * cum ) { rtx save_area , mem ; alias_set_type set ; int i , max ; if ( cfun -> va_list_gpr_size ) ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD ; else ix86_varargs_gpr_size = 0 ; if ( TARGET_SSE && cfun -> va_list_fpr_size ) ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16 ; else ix86_varargs_fpr_size = 0 ; if ( ! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size ) return ; save_area = frame_pointer_rtx ; set = get_varargs_alias_set ( ) ; max = cum -> regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( max > X86_64_REGPARM_MAX ) max = X86_64_REGPARM_MAX ; for ( i = cum -> regno ; i < max ; i ++ ) { mem = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , save_area , i * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( word_mode , x86_64_int_parameter_registers [ i ] ) ) ; } if ( ix86_varargs_fpr_size ) { machine_mode smode ; rtx_code_label * label ; rtx test ; label = gen_label_rtx ( ) ; test = gen_rtx_EQ ( VOIDmode , gen_rtx_REG ( QImode , AX_REG ) , const0_rtx ) ; emit_jump_insn ( gen_cbranchqi4 ( test , XEXP ( test , 0 ) , XEXP ( test , 1 ) , label ) ) ; smode = V4SFmode ; if ( crtl -> stack_alignment_needed < GET_MODE_ALIGNMENT ( smode ) ) crtl -> stack_alignment_needed = GET_MODE_ALIGNMENT ( smode ) ; max = cum -> sse_regno + cfun -> va_list_fpr_size / 16 ; if ( max > X86_64_SSE_REGPARM_MAX ) max = X86_64_SSE_REGPARM_MAX ; for ( i = cum -> sse_regno ; i < max ; ++ i ) { mem = plus_constant ( Pmode , save_area , i * 16 + ix86_varargs_gpr_size ) ; mem = gen_rtx_MEM ( smode , mem ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( smode ) ) ; emit_move_insn ( mem , gen_rtx_REG ( smode , GET_SSE_REGNO ( i ) ) ) ; } emit_label ( label ) ; } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> const uint32_t * SparcRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: SelectCC : return "MipsISD::SelectCC" ; case MipsISD :: FPSelectCC : return "MipsISD::FPSelectCC" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::Ret "MipsISD::Ret" MipsISD::SelectCC "MipsISD::SelectCC" MipsISD::FPSelectCC "MipsISD::FPSelectCC" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::FPRound "MipsISD::FPRound"


Output the assembly for a call instruction .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { return new ScheduleDAGMI ( C , std :: make_unique < SystemZPostRASchedStrategy > ( C ) , true ) ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> static rtx promote_duplicated_reg ( machine_mode mode , rtx val ) { machine_mode valmode = GET_MODE ( val ) ; rtx tmp ; int nops = mode == DImode ? 3 : 2 ; gcc_assert ( mode == SImode || mode == DImode || val == const0_rtx ) ; if ( val == const0_rtx ) return copy_to_mode_reg ( mode , CONST0_RTX ( mode ) ) ; if ( CONST_INT_P ( val ) ) { HOST_WIDE_INT v = INTVAL ( val ) & 255 ; v |= v << 8 ; v |= v << 16 ; if ( mode == DImode ) v |= ( v << 16 ) << 16 ; return copy_to_mode_reg ( mode , gen_int_mode ( v , mode ) ) ; } if ( valmode == VOIDmode ) valmode = QImode ; if ( valmode != QImode ) val = gen_lowpart ( QImode , val ) ; if ( mode == QImode ) return val ; if ( ! TARGET_PARTIAL_REG_STALL ) nops -- ; if ( ix86_cost -> mult_init [ mode == DImode ? 3 : 2 ] + ix86_cost -> mult_bit * ( mode == DImode ? 8 : 4 ) <= ( ix86_cost -> shift_const + ix86_cost -> add ) * nops + ( COSTS_N_INSNS ( TARGET_PARTIAL_REG_STALL == 0 ) ) ) { rtx reg = convert_modes ( mode , QImode , val , true ) ; tmp = promote_duplicated_reg ( mode , const1_rtx ) ; return expand_simple_binop ( mode , MULT , reg , tmp , NULL , 1 , OPTAB_DIRECT ) ; } else { rtx reg = convert_modes ( mode , QImode , val , true ) ; if ( ! TARGET_PARTIAL_REG_STALL ) emit_insn ( gen_insv_1 ( mode , reg , reg ) ) ; else { tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 8 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; } tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 16 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; if ( mode == SImode ) return reg ; tmp = expand_simple_binop ( mode , ASHIFT , reg , GEN_INT ( 32 ) , NULL , 1 , OPTAB_DIRECT ) ; reg = expand_simple_binop ( mode , IOR , reg , tmp , reg , 1 , OPTAB_DIRECT ) ; return reg ; } } </s>

Helper function for memcpy . For QImode value 0xXY produce 0xXYXYXYXY of wide specified by MODE . This is essentially a * 0x10101010 , but we can do slightly better than synth_mult by unwinding the sequence by hand on CPUs with slow multiply .


Relax the instruction in the given fragment to the next wider instruction .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = F . getFnAttribute ( "mips16" ) . isValid ( ) ; bool hasNoMips16Attr = F . getFnAttribute ( "nomips16" ) . isValid ( ) ; bool HasMicroMipsAttr = F . getFnAttribute ( "micromips" ) . isValid ( ) ; bool HasNoMicroMipsAttr = F . getFnAttribute ( "nomicromips" ) . isValid ( ) ; bool softFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


"mt_function_arg_advance: words = %2d, mode = %4s, named = %d, size = %3d\n"


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> static bool use_toc_relative_ref ( rtx sym , machine_mode mode ) { return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) ) || ( TARGET_CMODEL == CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) && GET_MODE_SIZE ( mode ) <= POWERPC64_TOC_POINTER_ALIGNMENT ) ) ; } </s>

Return true iff the given SYMBOL_REF refers to a constant pool entry that we have put in the TOC , or for cmodel=medium , if the SYMBOL_REF can be addressed relative to the toc pointer .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void rs6000_setup_reg_addr_masks ( void ) { ssize_t rc , reg , m , nregs ; addr_mask_type any_addr_mask , addr_mask ; for ( m = 0 ; m < NUM_MACHINE_MODES ; ++ m ) { machine_mode m2 = ( machine_mode ) m ; bool complex_p = false ; bool small_int_p = ( m2 == QImode || m2 == HImode || m2 == SImode ) ; size_t msize ; if ( COMPLEX_MODE_P ( m2 ) ) { complex_p = true ; m2 = GET_MODE_INNER ( m2 ) ; } msize = GET_MODE_SIZE ( m2 ) ; bool indexed_only_p = ( m == SDmode && TARGET_NO_SDMODE_STACK ) ; any_addr_mask = 0 ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = 0 ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= 0 && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > 1 || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= 8 && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ! small_int_vsx_p && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == 8 ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DFmode : case E_DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != 0 ) && ! indexed_only_p && msize <= 8 && ( rc == RELOAD_REG_GPR || ( ( msize == 8 || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM_SCALAR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != 0 ) && ! indexed_only_p && msize == 16 && TARGET_P9_DFORM_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX_TIMODE ) ) ) { addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) addr_mask |= RELOAD_REG_QUAD_OFFSET ; } if ( rc == RELOAD_REG_VMX && msize == 16 && ( addr_mask & RELOAD_REG_VALID ) != 0 ) addr_mask |= RELOAD_REG_AND_M16 ; reg_addr [ m ] . addr_mask [ rc ] = addr_mask ; any_addr_mask |= addr_mask ; } reg_addr [ m ] . addr_mask [ RELOAD_REG_ANY ] = any_addr_mask ; } } </s>

Update the addr mask bits in reg_addr to help secondary reload and go if legitimate address support to figure out the appropriate addressing to use .


<s> static inline _uw selfrel_offset31 ( const _uw * p ) { _uw offset ; offset = * p ; if ( offset & ( 1 << 30 ) ) offset |= 1u << 31 ; return offset + ( _uw ) p ; } </s>

Calculate the address encoded by a 31-bit self-relative offset at address P .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { for ( unsigned i = MI . getNumExplicitDefs ( ) , e = MI . getNumExplicitOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUndef ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) && hasUndefRegUpdate ( MI . getOpcode ( ) , i ) ) { OpNum = i ; return UndefRegClearance ; } } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; if ( MergeInit ) AU . addRequired < AAResultsWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const char * Cpu0TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Cpu0ISD :: JmpLink : return "Cpu0ISD::JmpLink" ; case Cpu0ISD :: Hi : return "Cpu0ISD::Hi" ; case Cpu0ISD :: Lo : return "Cpu0ISD::Lo" ; case Cpu0ISD :: GPRel : return "Cpu0ISD::GPRel" ; case Cpu0ISD :: Ret : return "Cpu0ISD::Ret" ; case Cpu0ISD :: RetValue : return "Cpu0ISD::RetValue" ; case Cpu0ISD :: DivRem : return "Cpu0ISD::DivRem" ; case Cpu0ISD :: DivRemU : return "Cpu0ISD::DivRemU" ; case Cpu0ISD :: Wrapper : return "Cpu0ISD::Wrapper" ; default : return NULL ; } } </s>


<s> static unsigned int parse_count ( const function_instance & instance , const char * & format ) { if ( format [ 0 ] == '*' && format [ 1 ] == 'q' ) { format += 2 ; return instance . elements_per_vq ( 0 ) ; } if ( format [ 0 ] == '*' && format [ 1 ] == 't' ) { format += 2 ; return instance . vectors_per_tuple ( ) ; } return 1 ; } </s>

Read and move past any argument count at FORMAT for the function signature of INSTANCE . The counts are : * q : one argument per element in a 128-bit quadword ( as for svdupq ) * t : one argument per vector in a tuple ( as for svcreate ) Otherwise the count is 1 .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s> static bool compute_fp_layout ( const_tree field , HOST_WIDE_INT bitpos , assign_data_t * data , int * pnregs , machine_mode * pmode ) { const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = 2 ; } else nregs = 1 ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = 1 ; if ( nregs <= 0 ) return false ; } * pnregs = nregs ; * pmode = mode ; return true ; } </s>

A subroutine of function_arg_record_value . Compute the number and the mode of the FP registers to be assigned for FIELD . Return true if at least one FP register is assigned or false otherwise .


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - 1 ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - 1 ; sign = REAL_VALUE_NEGATIVE ( r ) ? 1 : 0 ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; if ( mantissa != 0 ) return - 1 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return - 1 ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return - 1 ; gcc_assert ( mantissa >= 16 && mantissa <= 31 ) ; exponent = 5 - exponent ; if ( exponent < 0 || exponent > 7 ) return - 1 ; return ( sign << 7 ) | ( ( exponent ^ 3 ) << 4 ) | ( mantissa - 16 ) ; } </s>

Return an integer index for a VFPv3 immediate operand X suitable for the fconst [ sd ] instruction , or -1 if X is n't suitable .


<s> static void mips_emit_int_relational ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { if ( mips_relational_operand_ok_p ( code , cmp1 ) ) mips_emit_binary ( code , target , cmp0 , cmp1 ) ; else if ( mips_canonicalize_comparison ( & code , & cmp1 , GET_MODE ( target ) ) ) mips_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! mips_relational_operand_ok_p ( inv_code , cmp1 ) ) { cmp1 = force_reg ( GET_MODE ( cmp0 ) , cmp1 ) ; mips_emit_int_relational ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == 0 ) { rtx inv_target = gen_reg_rtx ( GET_MODE ( target ) ) ; mips_emit_binary ( inv_code , inv_target , cmp0 , cmp1 ) ; mips_emit_binary ( XOR , target , inv_target , const1_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; mips_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } } } </s>

Compare CMP0 and CMP1 using relational operator CODE and store the result in TARGET . CMP0 and TARGET are register_operands that have the same integer mode . If INVERT_PTR is nonnull , it 's OK to set TARGET to the inverse of the result and flip * INVERT_PTR instead .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; if ( MF . getMMI ( ) . hasEHFunclets ( ) ) { int FI = MFI -> CreateSpillStackObject ( SlotSize , SlotSize ) ; X86FI -> setHasSEHFramePtrSave ( true ) ; X86FI -> setSEHFramePtrSaveIndex ( FI ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s> static void sparc_init_libfuncs ( void ) { if ( TARGET_ARCH32 ) { set_optab_libfunc ( smul_optab , SImode , "*.umul" ) ; set_optab_libfunc ( sdiv_optab , SImode , "*.div" ) ; set_optab_libfunc ( udiv_optab , SImode , "*.udiv" ) ; set_optab_libfunc ( smod_optab , SImode , "*.rem" ) ; set_optab_libfunc ( umod_optab , SImode , "*.urem" ) ; set_optab_libfunc ( add_optab , TFmode , "_Q_add" ) ; set_optab_libfunc ( sub_optab , TFmode , "_Q_sub" ) ; set_optab_libfunc ( neg_optab , TFmode , "_Q_neg" ) ; set_optab_libfunc ( smul_optab , TFmode , "_Q_mul" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_Q_div" ) ; if ( TARGET_FPU ) set_optab_libfunc ( sqrt_optab , TFmode , "_Q_sqrt" ) ; set_optab_libfunc ( eq_optab , TFmode , "_Q_feq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_Q_fne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_Q_fgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_Q_fge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_Q_flt" ) ; set_optab_libfunc ( le_optab , TFmode , "_Q_fle" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_Q_stoq" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_Q_dtoq" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_Q_qtos" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_Q_qtod" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , "_Q_qtoi" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_Q_qtou" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_Q_itoq" ) ; if ( DITF_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , TFmode , "_Q_qtoll" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_Q_qtoull" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_Q_lltoq" ) ; } if ( SUN_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , SFmode , "__ftoll" ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , "__ftoull" ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , "__dtoll" ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , "__dtoull" ) ; } } if ( TARGET_ARCH64 ) { set_optab_libfunc ( smul_optab , SImode , 0 ) ; set_optab_libfunc ( sdiv_optab , SImode , 0 ) ; set_optab_libfunc ( udiv_optab , SImode , 0 ) ; set_optab_libfunc ( smod_optab , SImode , 0 ) ; set_optab_libfunc ( umod_optab , SImode , 0 ) ; if ( SUN_INTEGER_MULTIPLY_64 ) { set_optab_libfunc ( smul_optab , DImode , "__mul64" ) ; set_optab_libfunc ( sdiv_optab , DImode , "__div64" ) ; set_optab_libfunc ( udiv_optab , DImode , "__udiv64" ) ; set_optab_libfunc ( smod_optab , DImode , "__rem64" ) ; set_optab_libfunc ( umod_optab , DImode , "__urem64" ) ; } if ( SUN_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , SFmode , "__ftol" ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , "__ftoul" ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , "__dtol" ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , "__dtoul" ) ; } } gofast_maybe_init_libfuncs ( ) ; } </s>


<s>
const
char
*
emit_fusion_p9_store
(
rtx
mem
,
rtx
reg
,
rtx
tmp_reg
)
{
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
store_string
;
int
r
;
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_store, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
store_string
=
"stfs"
;
else
if
(
mode
==
DFmode
)
store_string
=
"stfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
ALTIVEC_REGNO_P
(
r
)
&&
TARGET_P9_DFORM_SCALAR
)
{
if
(
mode
==
SFmode
)
store_string
=
"stxssp"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
store_string
=
"stxsd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
E_QImode
:
store_string
=
"stb"
;
break
;
case
E_HImode
:
store_string
=
"sth"
;
break
;
case
E_SImode
:
case
E_SFmode
:
store_string
=
"stw"
;
break
;
case
E_DImode
:
case
E_DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
store_string
=
"std"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_store, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_store not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 store fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
store_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a store using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

powerpcspe
0
"emit_fusion_p9_store, bad reg #1"
"stfs"
"stfd"
"stxssp"
"stxsd"
"stb"
"sth"
"stw"
"std"
"emit_fusion_p9_store, bad reg #2"
"emit_fusion_p9_store not MEM"
0
"power9 store fusion"
""


<s> static bool rs6000_emit_move_si_sf_subreg ( rtx dest , rtx source , machine_mode mode ) { if ( TARGET_DIRECT_MOVE_64BIT && ! reload_completed && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ; return true ; } } return false ; } </s>

Helper function to change moves with : ( SUBREG : SF ( REG : SI ) ) and ( SUBREG : SI ( REG : SF ) ) into separate UNSPEC insns . In the PowerPC architecture , scalar SFmode values are stored as DFmode values in the VSX registers . We need to convert the bits before we can use a direct move or operate on the bits in the vector register as an integer type . Skip things like ( set ( SUBREG : SI ( ... ) ( SUBREG : SI ( ... ) ) .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool PPCTargetLowering :: SelectAddressRegRegOnly ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { if ( SelectAddressRegReg ( N , Base , Index , DAG ) ) return true ; int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD && ( ! isIntS16Immediate ( N . getOperand ( 1 ) , imm ) || ! N . getOperand ( 1 ) . hasOneUse ( ) || ! N . getOperand ( 0 ) . hasOneUse ( ) ) ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } Base = DAG . getRegister ( Subtarget . isPPC64 ( ) ? PPC :: ZERO8 : PPC :: ZERO , N . getValueType ( ) ) ; Index = N ; return true ; } </s>

SelectAddressRegRegOnly - Given the specified addressed , force it to be represented as an indexed [ r+r ] operation .


<s> void sparc_va_start ( tree valist , rtx nextarg ) { nextarg = expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void rs6000_emit_swsqrt ( rtx dst , rtx src , bool recip ) { machine_mode mode = GET_MODE ( src ) ; rtx e = gen_reg_rtx ( mode ) ; rtx g = gen_reg_rtx ( mode ) ; rtx h = gen_reg_rtx ( mode ) ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; int i ; rtx mhalf ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; mhalf = rs6000_load_constant_and_splat ( mode , dconsthalf ) ; emit_insn ( gen_rtx_SET ( e , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , src ) , UNSPEC_RSQRT ) ) ) ; if ( ! recip ) { rtx zero = force_reg ( mode , CONST0_RTX ( mode ) ) ; if ( mode == SFmode ) { rtx target = emit_conditional_move ( e , { GT , src , zero , mode } , e , zero , mode , 0 ) ; if ( target != e ) emit_move_insn ( e , target ) ; } else { rtx cond = gen_rtx_GT ( VOIDmode , e , zero ) ; rs6000_emit_vector_cond_expr ( e , e , zero , cond , src , zero ) ; } } emit_insn ( gen_mul ( g , e , src ) ) ; emit_insn ( gen_mul ( h , e , mhalf ) ) ; if ( recip ) { if ( passes == 1 ) { rtx t = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t , g , h , mhalf ) ; rs6000_emit_madd ( dst , e , t , e ) ; } else { for ( i = 0 ; i < passes ; i ++ ) { rtx t1 = gen_reg_rtx ( mode ) ; rtx g1 = gen_reg_rtx ( mode ) ; rtx h1 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t1 , g , h , mhalf ) ; rs6000_emit_madd ( g1 , g , t1 , g ) ; rs6000_emit_madd ( h1 , h , t1 , h ) ; g = g1 ; h = h1 ; } emit_insn ( gen_add3_insn ( dst , h , h ) ) ; } } else { rtx t = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( t , g , h , mhalf ) ; rs6000_emit_madd ( dst , g , t , g ) ; } return ; } </s>

Goldschmidt 's Algorithm for single/double-precision floating point sqrt and rsqrt . Assumes no trapping math and finite arguments .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> int ix86_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , enum machine_mode mode , int strict ) { if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) ) { gcc_assert ( ! strict ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ! TARGET_INTER_UNIT_MOVES && ! optimize_size ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; if ( mode == SFmode || mode == DFmode ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s>
void
execute_tag_collision_avoidance
(
)
{
struct
loop
*
loop
;
df_set_flags
(
DF_RD_PRUNE_DEAD_DEFS
)
;
df_chain_add_problem
(
DF_UD_CHAIN
)
;
df_compute_regs_ever_live
(
true
)
;
df_note_add_problem
(
)
;
df_analyze
(
)
;
df_set_flags
(
DF_DEFER_INSN_RESCAN
)
;
regrename_init
(
true
)
;
regrename_analyze
(
)
;
compute_bb_for_insn
(
)
;
calculate_dominance_info
(
CDI_DOMINATORS
)
;
loop_optimizer_init
(
AVOID_CFG_MODIFICATIONS
)
;
FOR_EACH_LOOP
(
loop
,
LI_FROM_INNERMOST
)
{
tag_map_t
tag_map
(
512
)
;
record_loads
(
tag_map
,
loop
)
;
avoid_collisions
(
tag_map
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Loop %d: Completed rename.\n"
,
loop
->
num
)
;
tag_map
.
traverse
<
void
*
,
dump_insn_list
>
(
)
;
}
tag_map
.
traverse
<
void
*
,
free_insn_info
>
(
)
;
}
loop_optimizer_finalize
(
)
;
free_dominance_info
(
CDI_DOMINATORS
)
;
regrename_finish
(
)
;
}
</s>

Tag collision avoidance pass for Falkor . The pass runs in two phases for each loop ; the first phase collects all loads that we consider as interesting for renaming into a tag-indexed map of lists . The second phase renames the destination register of the loads in an attempt to spread out the loads into different tags .


<s> static rtx gen_push ( rtx arg ) { struct machine_function * m = cfun -> machine ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) m -> fs . cfa_offset += UNITS_PER_WORD ; m -> fs . sp_offset += UNITS_PER_WORD ; if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( word_mode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , arg ) ; } </s>

Code to generate prologue and epilogue sequences


<s> bool OR1KFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool IsLittle , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new ARMFrameLowering ( * this ) : ( ARMFrameLowering * ) new Thumb1FrameLowering ( * this ) ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM ARM ARM ARM


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void emitVERegisterIgnore ( unsigned reg ) override { } </s>

Emit `` .register < reg > , # ignore '' .


<s> rtx rs6000_gen_le_vsx_permute ( rtx source , machine_mode mode ) { if ( FLOAT128_VECTOR_P ( mode ) || mode == TImode || mode == V1TImode ) return gen_rtx_ROTATE ( mode , source , GEN_INT ( 64 ) ) ; else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par ) ; } } </s>

Generate a permute rtx that represents an lxvd2x , stxvd2x , or xxpermdi for a VSX load or store operation .


<s> bool aarch64_member_type_forces_blk ( const_tree field_or_array , machine_mode mode ) { const_tree type = TREE_TYPE ( field_or_array ) ; unsigned int num_zr , num_pr ; if ( aarch64_sve :: builtin_type_p ( type , & num_zr , & num_pr ) && num_pr != 0 ) { if ( TREE_CODE ( field_or_array ) == ARRAY_TYPE ) return ! simple_cst_equal ( TYPE_SIZE ( field_or_array ) , TYPE_SIZE ( type ) ) ; return mode == VOIDmode ; } return default_member_type_forces_blk ( field_or_array , mode ) ; } </s>


<s> void mips_move_integer ( rtx temp , rtx dest , unsigned HOST_WIDE_INT value ) { struct mips_integer_op codes [ MIPS_MAX_INTEGER_OPS ] ; machine_mode mode ; unsigned int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = mips_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) { emit_insn ( gen_rtx_SET ( temp , x ) ) ; x = temp ; } else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> virtual unsigned getISAEncoding ( ) { if ( ! Subtarget -> isTargetDarwin ( ) ) return 0 ; return Subtarget -> isThumb ( ) ? ARM :: DW_ISA_ARM_thumb : ARM :: DW_ISA_ARM_arm ; } </s>

Get the value for DW_AT_APPLE_isa . Zero if no isa encoding specified .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width , 4 ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> rtx rs6000_got_register ( rtx value ATTRIBUTE_UNUSED ) { if ( ! can_create_pseudo_p ( ) && ! df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) df_set_regs_ever_live ( RS6000_PIC_OFFSET_TABLE_REGNUM , true ) ; crtl -> uses_pic_offset_table = 1 ; return pic_offset_table_rtx ; } </s>


<s> static int supersparc_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { enum attr_type insn_type ; if ( ! recog_memoized ( insn ) ) return 0 ; insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == 0 ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + 3 ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + 3 ; } if ( insn_type == TYPE_SHIFT ) return cost + 3 ; } else { if ( insn_type == TYPE_IALU || insn_type == TYPE_SHIFT ) return 0 ; } return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
cpu
=
;
const
char
*
cache
=
""
;
const
char
*
options
=
""
;
bool
arch
;
bool
assembler
;
size_t
i
;
if
(
argc
<
1
)
return
;
arch
=
strcmp
(
argv
[
0
]
,
"cpu"
)
==
0
;
assembler
=
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"asm"
)
==
0
)
;
if
(
!
arch
&&
!
assembler
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
return
;
if
(
!
assembler
)
{
cache
=
detect_caches_aix
(
)
;
cache
=
detect_caches_darwin
(
)
;
cache
=
detect_caches_freebsd
(
)
;
cache
=
""
;
cache
=
detect_caches_linux
(
)
;
cache
=
""
;
cache
=
""
;
}
cpu
=
detect_processor_aix
(
)
;
cpu
=
detect_processor_darwin
(
)
;
cpu
=
detect_processor_freebsd
(
)
;
cpu
=
detect_processor_linux
(
)
;
cpu
=
"powerpc"
;
if
(
assembler
)
{
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
asm_names
)
;
i
++
)
{
if
(
!
asm_names
[
i
]
.
cpu
||
!
strcmp
(
asm_names
[
i
]
.
cpu
,
cpu
)
)
return
asm_names
[
i
]
.
asm_sw
;
}
return
;
}
return
concat
(
cache
,
"-m"
,
argv
[
0
]
,
"="
,
cpu
,
" "
,
options
,
)
;
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> void x86_function_profiler ( FILE * file , int labelno ATTRIBUTE_UNUSED ) { if ( TARGET_64BIT ) if ( flag_pic ) { fprintf ( file , "\tleaq\t%sP%d@(%%rip),%%r11\n" , LPREFIX , labelno ) ; fprintf ( file , "\tcall\t*%s@GOTPCREL(%%rip)\n" , MCOUNT_NAME ) ; } else { fprintf ( file , "\tmovq\t$%sP%d,%%r11\n" , LPREFIX , labelno ) ; fprintf ( file , "\tcall\t%s\n" , MCOUNT_NAME ) ; } else if ( flag_pic ) { fprintf ( file , "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n" , LPREFIX , labelno , PROFILE_COUNT_REGISTER ) ; fprintf ( file , "\tcall\t*%s@GOT(%%ebx)\n" , MCOUNT_NAME ) ; } else { fprintf ( file , "\tmovl\t$%sP%d,%%%s\n" , LPREFIX , labelno , PROFILE_COUNT_REGISTER ) ; fprintf ( file , "\tcall\t%s\n" , MCOUNT_NAME ) ; } } </s>

Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry .


runOnMachineFunction - Emit the function body .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
&
*
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>


<s> bool SystemZFrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned LowReg = 0 , HighReg = 0 , StartOffset = - 1U , EndOffset = 0 ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! SystemZ :: FP64RegClass . contains ( Reg ) ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += 8 ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ( LowReg == HighReg ? SystemZ :: MOV64mr : SystemZ :: MOV64mrm ) ) ) ; MIB . addReg ( SystemZ :: R15D ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( SystemZ :: FP64RegClass . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , & SystemZ :: FP64RegClass , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool AArch64InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( getMaddPatterns ( Root , Patterns ) ) return true ; if ( getFMULPatterns ( Root , Patterns ) ) return true ; if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns , DoRegPressureReduce ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static bool aarch64_extr_rtx_p ( rtx x , rtx * res_op0 , rtx * res_op1 ) { rtx op0 , op1 ; machine_mode mode = GET_MODE ( x ) ; * res_op0 = NULL_RTX ; * res_op1 = NULL_RTX ; if ( GET_CODE ( x ) != IOR ) return false ; op0 = XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; if ( ( GET_CODE ( op0 ) == ASHIFT && GET_CODE ( op1 ) == LSHIFTRT ) || ( GET_CODE ( op1 ) == ASHIFT && GET_CODE ( op0 ) == LSHIFTRT ) ) { if ( GET_CODE ( op1 ) == ASHIFT ) std :: swap ( op0 , op1 ) ; if ( ! CONST_INT_P ( XEXP ( op0 , 1 ) ) || ! CONST_INT_P ( XEXP ( op1 , 1 ) ) ) return false ; unsigned HOST_WIDE_INT shft_amnt_0 = UINTVAL ( XEXP ( op0 , 1 ) ) ; unsigned HOST_WIDE_INT shft_amnt_1 = UINTVAL ( XEXP ( op1 , 1 ) ) ; if ( shft_amnt_0 < GET_MODE_BITSIZE ( mode ) && shft_amnt_0 + shft_amnt_1 == GET_MODE_BITSIZE ( mode ) ) { * res_op0 = XEXP ( op0 , 0 ) ; * res_op1 = XEXP ( op1 , 0 ) ; return true ; } } return false ; } </s>

Return true iff X is an rtx that will match an extr instruction i.e . as described in the * extr < mode > 5_insn family of patterns . OP0 and OP1 will be set to the operands of the shifts involved on success and will be NULL_RTX otherwise .


<s> bool MipsAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { const unsigned FixupKind = Fixup . getKind ( ) ; switch ( FixupKind ) { default : return false ; case Mips :: fixup_Mips_CALL_HI16 : case Mips :: fixup_Mips_CALL_LO16 : case Mips :: fixup_Mips_CALL16 : case Mips :: fixup_Mips_GOT : case Mips :: fixup_Mips_GOT_PAGE : case Mips :: fixup_Mips_GOT_OFST : case Mips :: fixup_Mips_GOT_DISP : case Mips :: fixup_Mips_GOT_HI16 : case Mips :: fixup_Mips_GOT_LO16 : case Mips :: fixup_Mips_GOTTPREL : case Mips :: fixup_Mips_DTPREL_HI : case Mips :: fixup_Mips_DTPREL_LO : case Mips :: fixup_Mips_TLSGD : case Mips :: fixup_Mips_TLSLDM : case Mips :: fixup_Mips_TPREL_HI : case Mips :: fixup_Mips_TPREL_LO : case Mips :: fixup_MICROMIPS_CALL16 : case Mips :: fixup_MICROMIPS_GOT_DISP : case Mips :: fixup_MICROMIPS_GOT_PAGE : case Mips :: fixup_MICROMIPS_GOT_OFST : case Mips :: fixup_MICROMIPS_GOT16 : case Mips :: fixup_MICROMIPS_GOTTPREL : case Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 : case Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 : case Mips :: fixup_MICROMIPS_TLS_GD : case Mips :: fixup_MICROMIPS_TLS_LDM : case Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 : case Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr : return selectGetElementPtr ( I ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; ( void ) & CC_AArch64_DarwinPCS_VarArg ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> static void ia64_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx addr , addr_reg , tramp , eight = GEN_INT ( 8 ) ; if ( ! TARGET_GNU_AS ) { static bool declared_ia64_trampoline = false ; if ( ! declared_ia64_trampoline ) { declared_ia64_trampoline = true ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , "__ia64_trampoline" ) ; } } addr = convert_memory_address ( Pmode , XEXP ( m_tramp , 0 ) ) ; fnaddr = convert_memory_address ( Pmode , fnaddr ) ; static_chain = convert_memory_address ( Pmode , static_chain ) ; addr_reg = copy_to_reg ( addr ) ; m_tramp = adjust_automodify_address ( m_tramp , Pmode , addr_reg , 0 ) ; tramp = gen_rtx_SYMBOL_REF ( Pmode , "__ia64_trampoline" ) ; if ( TARGET_ABI_OPEN_VMS ) { rtx reg = gen_reg_rtx ( Pmode ) ; SYMBOL_REF_FLAGS ( tramp ) |= SYMBOL_FLAG_FUNCTION ; emit_move_insn ( reg , tramp ) ; emit_move_insn ( reg , gen_rtx_MEM ( Pmode , reg ) ) ; tramp = reg ; } emit_move_insn ( m_tramp , tramp ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight ) ) ; m_tramp = adjust_automodify_address ( m_tramp , VOIDmode , NULL , 8 ) ; emit_move_insn ( m_tramp , force_reg ( Pmode , plus_constant ( Pmode , addr , 16 ) ) ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight ) ) ; m_tramp = adjust_automodify_address ( m_tramp , VOIDmode , NULL , 8 ) ; emit_move_insn ( m_tramp , force_reg ( Pmode , fnaddr ) ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight ) ) ; m_tramp = adjust_automodify_address ( m_tramp , VOIDmode , NULL , 8 ) ; emit_move_insn ( m_tramp , static_chain ) ; } </s>

Implement TARGET_TRAMPOLINE_INIT . The trampoline should set the static chain pointer to value placed into the trampoline and should branch to the specified routine . To make the normal indirect-subroutine calling convention work , the trampoline must look like a function descriptor ; the first word being the target address and the second being the target 's global pointer . We abuse the concept of a global pointer by arranging for it to point to the data we need to load . The complete trampoline has the following form : + -- -- -- -- -- -- -- -- -- -+ \ TRAMP : | __ia64_trampoline | | + -- -- -- -- -- -- -- -- -- -+ > fake function descriptor | TRAMP+16 | | + -- -- -- -- -- -- -- -- -- -+ / | target descriptor | + -- -- -- -- -- -- -- -- -- -+ | static link | + -- -- -- -- -- -- -- -- -- -+


<s> bool PPCRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; return ! Subtarget . hasROPProtect ( ) ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> static tree mips_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( mips_builtins ) ) return error_mark_node ; return mips_builtin_decls [ code ] ; } </s>


<s> void arm_output_fn_unwind ( FILE * f , bool prologue ) { if ( arm_except_unwind_info ( & global_options ) != UI_TARGET ) return ; if ( prologue ) fputs ( "\t.fnstart\n" , f ) ; else { if ( ! ( flag_unwind_tables || crtl -> uses_eh_lsda ) && ( TREE_NOTHROW ( current_function_decl ) || crtl -> all_throwers_are_sibcalls ) ) fputs ( "\t.cantunwind\n" , f ) ; fputs ( "\t.fnend\n" , f ) ; } } </s>

Output unwind directives for the start/end of a function .


<s> int loongarch_const_insns ( rtx x ) { enum loongarch_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case CONST_INT : return loongarch_integer_cost ( INTVAL ( x ) ) ; case CONST_VECTOR : case CONST_DOUBLE : return x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( loongarch_symbolic_constant_p ( x , & symbol_type ) ) return loongarch_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = loongarch_const_insns ( x ) ; if ( n != 0 ) { if ( IMM12_INT ( offset ) ) return n + 1 ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + 1 + loongarch_integer_cost ( INTVAL ( offset ) ) ; } } return 0 ; case SYMBOL_REF : case LABEL_REF : return loongarch_symbol_insns ( loongarch_classify_symbol ( x ) , MAX_MACHINE_MODE ) ; default : return 0 ; } } </s>

Return the number of instructions needed to load constant X , Return 0 if X is n't a valid constant .


<s> bool nds32_n8_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { if ( post_update_insn_p ( producer ) ) return false ; rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return n8_consumed_by_addr_in_p ( consumer , def_reg ) ; } </s>


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 1 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool SICFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == SIC :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( Ord == AtomicOrdering :: SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; if ( isReleaseOrStronger ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; return nullptr ; } </s>


<s> TargetLowering :: LegalizeAction VETargetLowering :: getCustomOperationAction ( SDNode & Op ) const { if ( isPackingSupportOpcode ( Op . getOpcode ( ) ) ) return Legal ; if ( isVVPOrVEC ( Op . getOpcode ( ) ) ) return Custom ; return Legal ; } </s>


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new X86MCAsmInfoDarwin ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: Cygwin : case Triple :: Win32 : if ( TheTriple . getEnvironment ( ) == Triple :: MachO ) return new X86MCAsmInfoDarwin ( TheTriple ) ; else return new X86MCAsmInfoCOFF ( TheTriple ) ; default : return new X86ELFMCAsmInfo ( TheTriple ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


"SystemZ DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case E_SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case E_DImode : return true ; case E_HFmode : if ( ! TARGET_VFP_FP16INST ) break ; mode = SFmode ; * op1 = convert_to_mode ( mode , * op1 , 1 ) ; * op2 = convert_to_mode ( mode , * op2 , 1 ) ; case E_SFmode : case E_DFmode : if ( ! vfp_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! vfp_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; OptBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( & MBB ) ; return Changed ; } </s>


<s> bool ARMBaseRegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return EnableLocalStackAlloc ; } </s>


Return an array that contains the direct target flag values and their names .


<s>
static
int
write_header_file
(
void
)
{
write_autogenerated_header
(
header_file
)
;
fprintf
(
header_file
,
"#ifndef _RS6000_BUILTINS_H\n"
)
;
fprintf
(
header_file
,
"#define _RS6000_BUILTINS_H 1\n\n"
)
;
write_decls
(
)
;
fprintf
(
header_file
,
"\n"
)
;
fprintf
(
header_file
,
"\n#endif\n"
)
;
return
1
;
}
</s>

Write everything to the header file ( rs6000-builtins.h ) . Return 1 if successful , 0 otherwise .

rs6000
"#ifndef _RS6000_BUILTINS_H\n"
"#define _RS6000_BUILTINS_H 1\n\n"
"\n"
"\n#endif\n"
1


<s> static int d30v_issue_rate ( ) { return 2 ; } </s>

Function which returns the number of insns that can be scheduled in the same machine cycle . This must be constant over an entire compilation . The default is 1 .


<s> bool LanaiInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
static
void
mips_output_filename
(
FILE
*
stream
,
const
char
*
name
)
{
if
(
dwarf_debuginfo_p
(
)
)
return
;
else
if
(
mips_output_filename_first_time
)
{
mips_output_filename_first_time
=
0
;
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
else
if
(
name
!=
current_function_file
&&
strcmp
(
name
,
current_function_file
)
!=
0
)
{
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
}
</s>

Emit a new filename to a stream . If we are smuggling stabs , try to put out a MIPS ECOFF file and a stab .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


"********** ARM MVE VPT Optimisations **********\n"

runOnMachineFunction - Emit the function body .


<s> SDValue AArch64TargetLowering :: BuildSREMPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( VT . isScalableVector ( ) || Subtarget -> useSVEForFixedLengthVectors ( ) ) return SDValue ( N , 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == 0 ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue CCVal , CSNeg ; if ( Lg2 == 1 ) { SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETGE , CCVal , DAG , DL ) ; SDValue And = DAG . getNode ( ISD :: AND , DL , VT , N0 , Pow2MinusOne ) ; CSNeg = DAG . getNode ( AArch64ISD :: CSNEG , DL , VT , And , And , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( And . getNode ( ) ) ; } else { SDValue CCVal = DAG . getConstant ( AArch64CC :: MI , DL , MVT_CC ) ; SDVTList VTs = DAG . getVTList ( VT , MVT :: i32 ) ; SDValue Negs = DAG . getNode ( AArch64ISD :: SUBS , DL , VTs , Zero , N0 ) ; SDValue AndPos = DAG . getNode ( ISD :: AND , DL , VT , N0 , Pow2MinusOne ) ; SDValue AndNeg = DAG . getNode ( ISD :: AND , DL , VT , Negs , Pow2MinusOne ) ; CSNeg = DAG . getNode ( AArch64ISD :: CSNEG , DL , VT , AndPos , AndNeg , CCVal , Negs . getValue ( 1 ) ) ; Created . push_back ( Negs . getNode ( ) ) ; Created . push_back ( AndPos . getNode ( ) ) ; Created . push_back ( AndNeg . getNode ( ) ) ; } return CSNeg ; } </s>

Targets may override this function to provide custom SREM lowering for power-of-2 denominators .


<s> memory_access_direction determine_access_direction ( rtx_insn * insn ) { int post_update_rtx_index ; rtx plus_rtx ; rtx mem_rtx ; rtx offset_rtx ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : gcc_assert ( parallel_elements ( insn ) >= 2 ) ; post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) plus_rtx = SET_SRC ( parallel_element ( insn , post_update_rtx_index ) ) ; else { mem_rtx = SET_SRC ( parallel_element ( insn , 1 ) ) ; if ( GET_CODE ( mem_rtx ) == UNSPEC ) mem_rtx = XVECEXP ( mem_rtx , 0 , 0 ) ; gcc_assert ( MEM_P ( mem_rtx ) ) ; plus_rtx = XEXP ( mem_rtx , 0 ) ; } break ; case TYPE_STORE_MULTIPLE : gcc_assert ( parallel_elements ( insn ) >= 2 ) ; post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) plus_rtx = SET_SRC ( parallel_element ( insn , post_update_rtx_index ) ) ; else { mem_rtx = SET_DEST ( parallel_element ( insn , 1 ) ) ; if ( GET_CODE ( mem_rtx ) == UNSPEC ) mem_rtx = XVECEXP ( mem_rtx , 0 , 0 ) ; gcc_assert ( MEM_P ( mem_rtx ) ) ; plus_rtx = XEXP ( mem_rtx , 0 ) ; } break ; case TYPE_LOAD : case TYPE_STORE : mem_rtx = extract_mem_rtx ( insn ) ; switch ( GET_CODE ( XEXP ( mem_rtx , 0 ) ) ) { case POST_INC : return MEM_ACCESS_DIR_POS ; case POST_DEC : return MEM_ACCESS_DIR_NEG ; case PLUS : plus_rtx = XEXP ( mem_rtx , 0 ) ; break ; case POST_MODIFY : plus_rtx = XEXP ( XEXP ( mem_rtx , 0 ) , 1 ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( plus_rtx ) == PLUS ) ; offset_rtx = XEXP ( plus_rtx , 1 ) ; if ( GET_CODE ( offset_rtx ) == CONST_INT ) { if ( INTVAL ( offset_rtx ) < 0 ) return MEM_ACCESS_DIR_NEG ; else return MEM_ACCESS_DIR_POS ; } return MEM_ACCESS_DIR_UNKNOWN ; } </s>

Determine the memory access direction of a load/store insn .