<s> HOST_WIDE_INT compute_frame_size ( HOST_WIDE_INT size ) { int regno ; HOST_WIDE_INT total_size ; HOST_WIDE_INT var_size ; HOST_WIDE_INT args_size ; HOST_WIDE_INT extra_size ; HOST_WIDE_INT gp_reg_rounded ; HOST_WIDE_INT gp_reg_size ; HOST_WIDE_INT fp_reg_size ; long mask ; int fp_inc ; long fp_bits ; gp_reg_size = 0 ; fp_reg_size = 0 ; mask = 0 ; extra_size = IQ2000_STACK_ALIGN ( ( 0 ) ) ; var_size = IQ2000_STACK_ALIGN ( size ) ; args_size = IQ2000_STACK_ALIGN ( current_function_outgoing_args_size ) ; if ( args_size == 0 && current_function_calls_alloca ) args_size = 4 * UNITS_PER_WORD ; total_size = var_size + args_size + extra_size ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno ) ) { gp_reg_size += GET_MODE_SIZE ( gpr_mode ) ; mask |= 1L << ( regno - GP_REG_FIRST ) ; } } if ( current_function_calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == ( int ) INVALID_REGNUM ) break ; gp_reg_size += GET_MODE_SIZE ( gpr_mode ) ; mask |= 1L << ( regno - GP_REG_FIRST ) ; } } fp_inc = 2 ; fp_bits = 3 ; gp_reg_rounded = IQ2000_STACK_ALIGN ( gp_reg_size ) ; total_size += gp_reg_rounded + IQ2000_STACK_ALIGN ( fp_reg_size ) ; if ( total_size == extra_size && ! profile_flag ) total_size = extra_size = 0 ; total_size += IQ2000_STACK_ALIGN ( current_function_pretend_args_size ) ; cfun -> machine -> total_size = total_size ; cfun -> machine -> var_size = var_size ; cfun -> machine -> args_size = args_size ; cfun -> machine -> extra_size = extra_size ; cfun -> machine -> gp_reg_size = gp_reg_size ; cfun -> machine -> fp_reg_size = fp_reg_size ; cfun -> machine -> mask = mask ; cfun -> machine -> initialized = reload_completed ; cfun -> machine -> num_gp = gp_reg_size / UNITS_PER_WORD ; if ( mask ) { unsigned long offset ; offset = ( args_size + extra_size + var_size + gp_reg_size - GET_MODE_SIZE ( gpr_mode ) ) ; cfun -> machine -> gp_sp_offset = offset ; cfun -> machine -> gp_save_offset = offset - total_size ; } else { cfun -> machine -> gp_sp_offset = 0 ; cfun -> machine -> gp_save_offset = 0 ; } cfun -> machine -> fp_sp_offset = 0 ; cfun -> machine -> fp_save_offset = 0 ; return total_size ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> static void ia64_init_dfa_pre_cycle_insn ( void ) { if ( temp_dfa_state == NULL ) { dfa_state_size = state_size ( ) ; temp_dfa_state = xmalloc ( dfa_state_size ) ; prev_cycle_state = xmalloc ( dfa_state_size ) ; } dfa_pre_cycle_insn = make_insn_raw ( gen_pre_cycle ( ) ) ; SET_PREV_INSN ( dfa_pre_cycle_insn ) = SET_NEXT_INSN ( dfa_pre_cycle_insn ) = NULL_RTX ; recog_memoized ( dfa_pre_cycle_insn ) ; dfa_stop_insn = make_insn_raw ( gen_insn_group_barrier ( GEN_INT ( 3 ) ) ) ; SET_PREV_INSN ( dfa_stop_insn ) = SET_NEXT_INSN ( dfa_stop_insn ) = NULL_RTX ; recog_memoized ( dfa_stop_insn ) ; } </s>

The following function initiates variable ` dfa_pre_cycle_insn ' .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
const
SmallVectorImpl
<
MachineOperand
>
&
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
->
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> bool PPCPassConfig :: addPreEmitPass ( ) { PM . add ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void ix86_emit_leave ( rtx_insn * insn ) { struct machine_function * m = cfun -> machine ; if ( ! insn ) insn = emit_insn ( ix86_gen_leave ( ) ) ; ix86_add_queued_cfa_restore_notes ( insn ) ; gcc_assert ( m -> fs . fp_valid ) ; m -> fs . sp_valid = true ; m -> fs . sp_realigned = false ; m -> fs . sp_offset = m -> fs . fp_offset - UNITS_PER_WORD ; m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset ) ; } </s>

Emit code and notes for the LEAVE instruction .


<s> static bool check_required_extensions ( location_t location , tree fndecl , uint64_t required_extensions ) { uint64_t missing_extensions = required_extensions & ~ aarch64_isa_flags ; if ( missing_extensions == 0 ) return check_required_registers ( location , fndecl ) ; static const struct { uint64_t flag ; const char * name ; } extensions [ ] = { SYNTHETIC , FEATURE_STRING ) \ { FLAG_CANONICAL , EXT_NAME } , } ; for ( unsigned int i = 0 ; i < ARRAY_SIZE ( extensions ) ; ++ i ) if ( missing_extensions & extensions [ i ] . flag ) { report_missing_extension ( location , fndecl , extensions [ i ] . name ) ; return false ; } gcc_unreachable ( ) ; } </s>

Check whether all the RVV_REQUIRE_ * values in REQUIRED_EXTENSIONS are enabled .


<s> bool ARMOptimizeBarriersPass :: runOnMachineFunction ( MachineFunction & MF ) { std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - 1 ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == ARM :: DMB ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( 0 ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else { IsRemovableNextDMB = true ; DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else if ( ! CanMovePastDMB ( & MI ) ) { IsRemovableNextDMB = false ; } } } for ( auto MI : ToRemove ) { MI -> eraseFromParent ( ) ; ++ NumDMBsRemoved ; } return NumDMBsRemoved > 0 ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { Register VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Sparc Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 1 ) . getImm ( ) ; return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


<s> void ARMTargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { ARMFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> bool MipsSEFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CHERICFI && STI . isCheri ( ) && ! STI . getABI ( ) . IsCheriPureCap ( ) ) for ( auto & I : CSI ) if ( I . getReg ( ) == Mips :: RA_64 ) { CSI . push_back ( CalleeSavedInfo ( Mips :: C16 , 0 ) ) ; break ; } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void ix86_option_override ( void ) { ix86_option_override_internal ( true , & global_options , & global_options_set ) ; } </s>

Implement the TARGET_OPTION_OVERRIDE hook .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { LLT p0 = LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) ; LLT SType = LLT :: scalar ( DL . getPointerSizeInBits ( 0 ) ) ; Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , STI . getRegisterInfo ( ) -> getStackRegister ( ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( SType ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static machine_mode ix86_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == m2 ) return m1 ; if ( GET_MODE_CLASS ( m1 ) != MODE_CC || GET_MODE_CLASS ( m2 ) != MODE_CC ) return VOIDmode ; if ( ( m1 == CCGCmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCGCmode ) ) return CCGCmode ; if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCSmode : case CCZmode : switch ( m2 ) { default : return VOIDmode ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCSmode : case CCZmode : return CCmode ; } case CCFPmode : case CCFPUmode : return VOIDmode ; } } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s> MachineInstr * Thumb1InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FI ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned OpNum = Ops [ 0 ] ; unsigned Opc = MI -> getOpcode ( ) ; MachineInstr * NewMI = NULL ; switch ( Opc ) { default : break ; case ARM :: tMOVr : case ARM :: tMOVtgpr2gpr : case ARM :: tMOVgpr2tgpr : case ARM :: tMOVgpr2gpr : { if ( OpNum == 0 ) { unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && ! isARMLowRegister ( SrcReg ) ) break ; NewMI = AddDefaultPred ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( ARM :: tSpill ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ) ; } else { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) && ! isARMLowRegister ( DstReg ) ) break ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; NewMI = AddDefaultPred ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( ARM :: tRestore ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( isDead ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ) ; } break ; } } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static int constant_pool_expr_1 ( rtx op , int * have_sym , int * have_toc ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : if ( RS6000_SYMBOL_REF_TLS_P ( op ) ) return 0 ; else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( op ) , Pmode ) ) { * have_sym = 1 ; return 1 ; } else return 0 ; } else if ( ! strcmp ( XSTR ( op , 0 ) , toc_label_name ) ) { * have_toc = 1 ; return 1 ; } else return 0 ; case PLUS : case MINUS : return ( constant_pool_expr_1 ( XEXP ( op , 0 ) , have_sym , have_toc ) && constant_pool_expr_1 ( XEXP ( op , 1 ) , have_sym , have_toc ) ) ; case CONST : return constant_pool_expr_1 ( XEXP ( op , 0 ) , have_sym , have_toc ) ; case CONST_INT : return 1 ; default : return 0 ; } } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address .


<s> void ix86_expand_lround ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op1 ) ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx adj ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR , dconsthalf , half_minus_pred_half ) ; adj = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ; ix86_sse_copysign_to_positive ( adj , adj , force_reg ( mode , op1 ) , NULL_RTX ) ; adj = expand_simple_binop ( mode , PLUS , adj , op1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; expand_fix ( op0 , adj , 0 ) ; } </s>

Expand SSE sequence for computing lround from OP1 storing into OP0 .


<s> static int mt_function_arg_slotno ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED , int incoming_p ATTRIBUTE_UNUSED , int * pregno ) { int regbase = FIRST_ARG_REGNUM ; int slotno = * cum ; if ( mode == VOIDmode || targetm . calls . must_pass_in_stack ( mode , type ) ) return - 1 ; if ( slotno >= MT_NUM_ARG_REGS ) return - 1 ; * pregno = regbase + slotno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Returns the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type .


<s> static void mips_deallocate_stack ( rtx base , rtx offset , HOST_WIDE_INT new_frame_size ) { if ( base == stack_pointer_rtx && offset == const0_rtx ) return ; mips_frame_barrier ( ) ; if ( offset == const0_rtx ) { emit_move_insn ( stack_pointer_rtx , base ) ; mips_epilogue_set_cfa ( stack_pointer_rtx , new_frame_size ) ; } else if ( TARGET_MIPS16 && base != stack_pointer_rtx ) { emit_insn ( gen_add3_insn ( base , base , offset ) ) ; mips_epilogue_set_cfa ( base , new_frame_size ) ; emit_move_insn ( stack_pointer_rtx , base ) ; } else { emit_insn ( gen_add3_insn ( stack_pointer_rtx , base , offset ) ) ; mips_epilogue_set_cfa ( stack_pointer_rtx , new_frame_size ) ; } } </s>

Emit code to set the stack pointer to BASE + OFFSET , given that BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame . BASE , if not the stack pointer , is available as a temporary .


<s> void MipsAsmPrinter :: emitInlineAsmStart ( ) const { MipsTargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetPush ( ) ; TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; OutStreamer -> AddBlankLine ( ) ; } </s>

Let the target do anything it needs to do before emitting inlineasm .


<s> const char * ARMTargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ! Subtarget -> hasVFP2Base ( ) ) return "r" ; if ( ConstraintVT . isFloatingPoint ( ) ) return "w" ; if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == 64 || ConstraintVT . getSizeInBits ( ) == 128 ) ) return "w" ; return "r" ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s>
void
pa_asm_output_aligned_common
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
unsigned
int
max_common_align
;
max_common_align
=
TARGET_64BIT
128
:
(
size
>=
4096
256
:
64
)
;
if
(
align
>
max_common_align
)
{
align
=
max_common_align
;
}
switch_to_section
(
bss_section
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.comm "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
MAX
(
size
,
align
/
BITS_PER_UNIT
)
)
;
}
</s>

Both the HP and GNU assemblers under HP-UX provide a .comm directive that does n't allow the alignment of global common storage to be directly specified . The SOM linker aligns common storage based on the rounded value of the NUM_BYTES parameter in the .comm directive . It 's not possible to use the .align directive as it does n't affect the alignment of the label associated with a .comm directive .


<s> static int rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; machine_mode mode = GET_MODE ( dest ) ; enum rtx_code cond_code ; rtx ( * isel_func ) ( rtx , rtx , rtx , rtx , rtx ) ; bool signedp ; if ( mode != SImode && ( ! TARGET_POWERPC64 || mode != DImode ) ) return 0 ; condition_rtx = rs6000_generate_compare ( op , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; cr = XEXP ( condition_rtx , 0 ) ; signedp = GET_MODE ( cr ) == CCmode ; isel_func = ( mode == SImode ? ( signedp ? gen_isel_signed_si : gen_isel_unsigned_si ) : ( signedp ? gen_isel_signed_di : gen_isel_unsigned_di ) ) ; switch ( cond_code ) { case LT : case GT : case LTU : case GTU : case EQ : break ; default : { std :: swap ( false_cond , true_cond ) ; PUT_CODE ( condition_rtx , reverse_condition ( cond_code ) ) ; } break ; } false_cond = force_reg ( mode , false_cond ) ; if ( true_cond != const0_rtx ) true_cond = force_reg ( mode , true_cond ) ; emit_insn ( isel_func ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return 1 ; } </s>


<s> static bool aarch64_multiply_add_p ( vec_info * vinfo , stmt_vec_info stmt_info ) { gassign * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ; if ( ! assign ) return false ; tree_code code = gimple_assign_rhs_code ( assign ) ; if ( code != PLUS_EXPR && code != MINUS_EXPR ) return false ; if ( CONSTANT_CLASS_P ( gimple_assign_rhs1 ( assign ) ) || CONSTANT_CLASS_P ( gimple_assign_rhs2 ( assign ) ) ) return false ; for ( int i = 1 ; i < 3 ; ++ i ) { tree rhs = gimple_op ( assign , i ) ; if ( TREE_CODE ( rhs ) != SSA_NAME ) continue ; stmt_vec_info def_stmt_info = vinfo -> lookup_def ( rhs ) ; if ( ! def_stmt_info || STMT_VINFO_DEF_TYPE ( def_stmt_info ) != vect_internal_def ) continue ; gassign * rhs_assign = dyn_cast < gassign * > ( def_stmt_info -> stmt ) ; if ( ! rhs_assign || gimple_assign_rhs_code ( rhs_assign ) != MULT_EXPR ) continue ; return true ; } return false ; } </s>

Return true if STMT_INFO is the second part of a two-statement multiply-add or multiply-subtract sequence that might be suitable for fusing into a single instruction .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


"unimplemented opcode in encodeInstruction()"

"Pseudo opcode found in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> inline type_suffix_index find_type_suffix ( type_class_index tclass , unsigned int element_bits ) { for ( unsigned int i = 0 ; i < NUM_TYPE_SUFFIXES ; ++ i ) if ( type_suffixes [ i ] . tclass == tclass && type_suffixes [ i ] . element_bits == element_bits ) return type_suffix_index ( i ) ; gcc_unreachable ( ) ; } </s>

Return the type suffix associated with ELEMENT_BITS-bit elements of type class TCLASS .


<s> bool constant_address_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case LABEL_REF : case CONST_INT : case HIGH : return true ; case CONST : if ( flag_pic && pic_address_needs_scratch ( x ) ) return false ; return legitimate_constant_p ( x ) ; case SYMBOL_REF : return ! flag_pic && legitimate_constant_p ( x ) ; default : return false ; } } </s>

Determine if a given RTX is a valid constant address .


<s> bool ARMTargetLowering :: isLegalInterleavedAccessType ( unsigned Factor , FixedVectorType * VecTy , Align Alignment , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == 3 ) return false ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Alignment < ElSize / 8 ) return false ; if ( Subtarget -> hasNEON ( ) && VecSize == 64 ) return true ; return VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> static void nds32_conditional_register_usage ( void ) { int regno ; if ( TARGET_HARD_FLOAT ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 0 ; if ( regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS ) call_used_regs [ regno ] = 1 ; else if ( regno >= NDS32_FIRST_FPR_REGNUM + 22 && regno < NDS32_FIRST_FPR_REGNUM + 48 ) call_used_regs [ regno ] = 1 ; else call_used_regs [ regno ] = 0 ; } } else if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) fixed_regs [ regno ] = 0 ; } } </s>


<s> static rtx_insn * rs6000_frame_related ( rtx_insn * insn , rtx reg , HOST_WIDE_INT val , rtx reg2 , rtx repl2 ) { rtx repl ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) { gcc_checking_assert ( val == 0 ) ; repl = NULL_RTX ; } else repl = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ; rtx pat = PATTERN ( insn ) ; if ( ! repl && ! reg2 ) { if ( GET_CODE ( pat ) == PARALLEL ) for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( ! REG_P ( SET_SRC ( set ) ) || interesting_frame_related_regno ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } set_used_flags ( pat ) ; if ( GET_CODE ( pat ) == SET ) { if ( repl ) pat = simplify_replace_rtx ( pat , reg , repl ) ; if ( reg2 ) pat = simplify_replace_rtx ( pat , reg2 , repl2 ) ; } else if ( GET_CODE ( pat ) == PARALLEL ) { pat = shallow_copy_rtx ( pat ) ; XVEC ( pat , 0 ) = shallow_copy_rtvec ( XVEC ( pat , 0 ) ) ; for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( repl ) set = simplify_replace_rtx ( set , reg , repl ) ; if ( reg2 ) set = simplify_replace_rtx ( set , reg2 , repl2 ) ; XVECEXP ( pat , 0 , i ) = set ; if ( ! REG_P ( SET_SRC ( set ) ) || interesting_frame_related_regno ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } } else gcc_unreachable ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , copy_rtx_if_shared ( pat ) ) ; return insn ; } </s>

Add to 'insn ' a note which is PATTERN ( INSN ) but with REG replaced with ( plus : P ( reg 1 ) VAL ) , and with REG2 replaced with RREG if REG2 is not NULL . It would be nice if dwarf2out_frame_debug_expr could deduce these equivalences by itself so it was n't necessary to hold its hand so much . Do n't be tempted to always supply d2_f_d_e with the actual cfa register , ie . r31 when we are using a hard frame pointer . That fails when saving regs off r1 , and sched moves the r31 setup past the reg saves .


<s> bool Mips16TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> unsigned SparcAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { SparcOperand & Op = ( SparcOperand & ) GOp ; if ( Op . isFloatOrDoubleReg ( ) ) { switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op . isFloatReg ( ) || SparcOperand :: MorphToDoubleReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( SparcOperand :: MorphToQuadReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } } if ( Op . isIntReg ( ) && Kind == MCK_IntPair ) { if ( SparcOperand :: MorphToIntPairReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; } if ( Op . isCoprocReg ( ) && Kind == MCK_CoprocPair ) { if ( SparcOperand :: MorphToCoprocPairReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Sparc Sparc Sparc Sparc SparcOperand::MorphToDoubleReg SparcOperand::MorphToQuadReg SparcOperand::MorphToIntPairReg SparcOperand::MorphToCoprocPairReg


<s> void ia64_unpack_assemble ( rtx out , rtx lo , rtx hi , bool highp ) { machine_mode vmode = GET_MODE ( lo ) ; unsigned int i , high , nelt = GET_MODE_NUNITS ( vmode ) ; struct expand_vec_perm_d d ; bool ok ; d . target = gen_lowpart ( vmode , out ) ; d . op0 = ( TARGET_BIG_ENDIAN ? hi : lo ) ; d . op1 = ( TARGET_BIG_ENDIAN ? lo : hi ) ; d . vmode = vmode ; d . nelt = nelt ; d . one_operand_p = false ; d . testing_p = false ; high = ( highp ? nelt / 2 : 0 ) ; for ( i = 0 ; i < nelt / 2 ; ++ i ) { d . perm [ i * 2 ] = i + high ; d . perm [ i * 2 + 1 ] = i + high + nelt ; } ok = ia64_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( ok ) ; } </s>

The vectors LO and HI each contain N halves of a double-wide vector . Reassemble either the first N/2 or the second N/2 elements .


<s> bool MipsRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; unsigned FP = Subtarget . isGP32bit ( ) ? Mips :: FP : Mips :: FP_64 ; unsigned BP = Subtarget . isGP32bit ( ) ? Mips :: S7 : Mips :: S7_64 ; if ( ! Subtarget . hasStandardEncoding ( ) ) return false ; if ( ! MF . getRegInfo ( ) . canReserveReg ( FP ) ) return false ; if ( Subtarget . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MF . getRegInfo ( ) . canReserveReg ( BP ) ; } </s>

True if the stack can be realigned for the target .


<s> unsigned char X86Subtarget :: classifyBlockAddressReference ( ) const { return classifyLocalReference ( nullptr ) ; } </s>

Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool X86FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || ( hasFP ( MF ) && ! TRI -> hasStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> unsigned MipsSEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SD ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SDC1 ) || ( Opc == Mips :: SDC164 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , Subtarget -> isABI_O32 ( ) , Subtarget -> isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget -> abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> TargetLowering :: ConstraintWeight LanaiTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & Info , const char * Constraint ) const { ConstraintWeight Weight = CW_Invalid ; Value * CallOperandVal = Info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * Constraint ) { case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ; break ; } return Weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
const
MCFixupKindInfo
&
LanaiAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
static
const
MCFixupKindInfo
Infos
[
Lanai
::
NumTargetFixupKinds
]
=
{
{
"FIXUP_LANAI_NONE"
,
0
,
32
,
0
}
,
{
"FIXUP_LANAI_21"
,
16
,
16
,
0
}
,
{
"FIXUP_LANAI_21_F"
,
16
,
16
,
0
}
,
{
"FIXUP_LANAI_25"
,
7
,
25
,
0
}
,
{
"FIXUP_LANAI_32"
,
0
,
32
,
0
}
,
{
"FIXUP_LANAI_HI16"
,
16
,
16
,
0
}
,
{
"FIXUP_LANAI_LO16"
,
16
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
EVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU64RegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
CPURegsRegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
CPU64RegsRegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
HILORegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
HILO64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
if
(
!
WidenVMOVS
||
!
MI
->
isCopy
(
)
||
Subtarget
.
isCortexA15
(
)
)
return
false
;
unsigned
DstRegS
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
SrcRegS
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
->
definesRegister
(
DstRegD
,
TRI
)
||
MI
->
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
->
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
*
MI
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
int
ImpDefIdx
=
MI
->
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
->
RemoveOperand
(
ImpDefIdx
)
;
MI
->
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
->
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
->
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
AddDefaultPred
(
MIB
)
;
MI
->
getOperand
(
1
)
.
setIsUndef
(
)
;
MIB
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
->
getOperand
(
1
)
.
isKill
(
)
)
{
MI
->
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
->
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
*
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool XNCMDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool ARMTargetLowering :: isLegalInterleavedAccessType ( VectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 ) return false ; return VecSize == 64 || VecSize % 128 == 0 ; } </s>


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: PseudoMFHI : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI ) ; break ; case Mips :: PseudoMFLO : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D32_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_W , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>


<s> void ARMHazardRecognizer :: AdvanceCycle ( ) { if ( Stalls && -- Stalls == 0 ) LastMI = 0 ; ScoreboardHazardRecognizer :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> bool TOYTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_TOY ) ) { return false ; } if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) { return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> unsigned PPCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == PPC :: INLINEASM || Opcode == PPC :: INLINEASM_BR ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { StackMapOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else { return get ( Opcode ) . getSize ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> BitVector LoongArchRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const LoongArchFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , LoongArch :: R0 ) ; markSuperRegs ( Reserved , LoongArch :: R2 ) ; markSuperRegs ( Reserved , LoongArch :: R3 ) ; markSuperRegs ( Reserved , LoongArch :: R21 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , LoongArch :: R22 ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , LoongArchABI :: getBPReg ( ) ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool ix86_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = FLAGS_REG ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: VLDR_P0_off : case ARM :: MVE_VLDRWU32 : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d8TPseudo : case ARM :: VLD1d16TPseudo : case ARM :: VLD1d32TPseudo : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d8QPseudo : case ARM :: VLD1d16QPseudo : case ARM :: VLD1d32QPseudo : case ARM :: VLD1d64QPseudo : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: MQQPRLoad : case ARM :: MQQQQPRLoad : if ( MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"LEG DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { switch ( Inst . getOpcode ( ) ) { case Mips :: JALR_HB : case Mips :: JALRC_HB_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: LWP_MM : case Mips :: LWP_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 2 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: BLEZC : case Mips :: BGEZC : case Mips :: BGTZC : case Mips :: BLTZC : case Mips :: BEQZC : case Mips :: BNEZC : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO ) return Match_RequiresNoZeroRegister ; return Match_Success ; case Mips :: BGEC : case Mips :: BLTC : case Mips :: BGEUC : case Mips :: BLTUC : case Mips :: BEQC : case Mips :: BNEC : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 1 ) . getReg ( ) == Mips :: ZERO ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; default : return Match_Success ; } } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> const MipsSubtarget * getSubtargetImpl ( ) const { if ( Subtarget ) return Subtarget ; return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
bool
SparcAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
if
(
parseBranchModifiers
(
Operands
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
||
getLexer
(
)
.
is
(
AsmToken
::
Plus
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Plus
)
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
"+"
,
Parser
.
getTok
(
)
.
getLoc
(
)
)
)
;
}
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Sparc
Sparc
SparcOperand::CreateToken
0
"unexpected token"
"unexpected token"
SparcOperand::CreateToken
"+"
"unexpected token"
"unexpected token"


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> int includes_rldic_lshift_p ( rtx shiftop , rtx andop ) { if ( GET_CODE ( andop ) == CONST_INT ) { HOST_WIDE_INT c , lsb , shift_mask ; c = INTVAL ( andop ) ; if ( c == 0 || c == ~ 0 ) return 0 ; shift_mask = ~ 0 ; shift_mask <<= INTVAL ( shiftop ) ; lsb = c & - c ; if ( - lsb != shift_mask ) return 0 ; c = ~ c ; c &= - lsb ; lsb = c & - c ; return c == - lsb ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , high , lsb ; HOST_WIDE_INT shift_mask_low , shift_mask_high ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < 64 ) high = CONST_DOUBLE_HIGH ( andop ) ; if ( ( low == 0 && ( HOST_BITS_PER_WIDE_INT >= 64 || high == 0 ) ) || ( low == ~ 0 && ( HOST_BITS_PER_WIDE_INT >= 64 || high == ~ 0 ) ) ) return 0 ; if ( HOST_BITS_PER_WIDE_INT < 64 && low == 0 ) { shift_mask_high = ~ 0 ; if ( INTVAL ( shiftop ) > 32 ) shift_mask_high <<= INTVAL ( shiftop ) - 32 ; lsb = high & - high ; if ( - lsb != shift_mask_high || INTVAL ( shiftop ) < 32 ) return 0 ; high = ~ high ; high &= - lsb ; lsb = high & - high ; return high == - lsb ; } shift_mask_low = ~ 0 ; shift_mask_low <<= INTVAL ( shiftop ) ; lsb = low & - low ; if ( - lsb != shift_mask_low ) return 0 ; if ( HOST_BITS_PER_WIDE_INT < 64 ) high = ~ high ; low = ~ low ; low &= - lsb ; if ( HOST_BITS_PER_WIDE_INT < 64 && low == 0 ) { lsb = high & - high ; return high == - lsb ; } lsb = low & - low ; return low == - lsb && ( HOST_BITS_PER_WIDE_INT >= 64 || high == ~ 0 ) ; } else return 0 ; } </s>

Return 1 if ANDOP is a mask suitable for use with an rldic insn to perform a left shift . It must have exactly SHIFTOP least significant 0 's , then one or more 1 's , then zero or more 0 's .


<s>
SDValue
VETargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ConstantPoolSDNode
*
CP
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
CP
->
getConstVal
(
)
,
CP
->
getValueType
(
0
)
,
CP
->
getAlign
(
)
,
CP
->
getOffset
(
)
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
if
(
const
JumpTableSDNode
*
JT
=
dyn_cast
<
JumpTableSDNode
>
(
Op
)
)
return
DAG
.
getTargetJumpTable
(
JT
->
getIndex
(
)
,
JT
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void VEAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; case VE :: GETGOT : lowerGETGOTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; case VE :: GETFUNPLT : lowerGETFunPLTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerVEMachineInstrToMCInst ( & * I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

Targets should implement this to emit instructions .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
DAG
->
MF
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
==
PPC
::
DIR_PWR7
||
Directive
==
PPC
::
DIR_PWR8
)
return
new
PPCDispatchGroupSBHazardRecognizer
(
II
,
DAG
)
;
if
(
Directive
!=
PPC
::
DIR_440
&&
Directive
!=
PPC
::
DIR_A2
&&
Directive
!=
PPC
::
DIR_E500mc
&&
Directive
!=
PPC
::
DIR_E5500
)
{
assert
(
DAG
->
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
DAG
)
;
}
return
new
ScoreboardHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> int mems_ok_for_quad_peep ( rtx mem1 , rtx mem2 ) { rtx addr1 , addr2 ; unsigned int reg1 , reg2 ; int offset1 , offset2 ; if ( MEM_VOLATILE_P ( mem1 ) || MEM_VOLATILE_P ( mem2 ) ) return 0 ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( GET_CODE ( XEXP ( addr1 , 0 ) ) != REG ) return 0 ; else { reg1 = REGNO ( XEXP ( addr1 , 0 ) ) ; if ( GET_CODE ( XEXP ( addr1 , 1 ) ) != CONST_INT ) return 0 ; offset1 = INTVAL ( XEXP ( addr1 , 1 ) ) ; } } else if ( GET_CODE ( addr1 ) != REG ) return 0 ; else { reg1 = REGNO ( addr1 ) ; offset1 = 0 ; } if ( GET_CODE ( addr2 ) == PLUS ) { if ( GET_CODE ( XEXP ( addr2 , 0 ) ) != REG ) return 0 ; else { reg2 = REGNO ( XEXP ( addr2 , 0 ) ) ; if ( GET_CODE ( XEXP ( addr2 , 1 ) ) != CONST_INT ) return 0 ; offset2 = INTVAL ( XEXP ( addr2 , 1 ) ) ; } } else if ( GET_CODE ( addr2 ) != REG ) return 0 ; else { reg2 = REGNO ( addr2 ) ; offset2 = 0 ; } if ( reg1 != reg2 ) return 0 ; if ( offset2 != offset1 + 8 ) return 0 ; return 1 ; } </s>

Return 1 if addr1 and addr2 are suitable for lfq or stfq insn . addr1 and addr2 must be in consecutive memory locations ( addr2 == addr1 + 8 ) .


<s> rtx aarch64_replace_reg_mode ( rtx x , machine_mode mode ) { if ( GET_MODE ( x ) == mode ) return x ; x = shallow_copy_rtx ( x ) ; set_mode_and_regno ( x , mode , REGNO ( x ) ) ; return x ; } </s>

Return a copy of X with mode MODE , without changing its other attributes . Unlike gen_lowpart , this does n't care whether the mode change is valid .


<s> static void get_pc_thunk_name ( char name [ 32 ] , unsigned int regno ) { const char * reg_name = reg_names [ regno ] ; reg_name += 1 ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__sparc_get_pc_thunk.%s" , reg_name ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LADDPC" , regno ) ; } </s>

Fills in the label name that should be used for a pc thunk for the given register .


<s> const char * getPassName ( ) const override { return AARCH64_BR_RELAX_NAME ; } </s>


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s>
const
TargetRegisterClass
*
MipsRegisterInfo
::
getPointerRegClass
(
const
MachineFunction
&
MF
,
unsigned
Kind
)
const
{
MipsABIInfo
ABI
=
MF
.
getSubtarget
<
MipsSubtarget
>
(
)
.
getABI
(
)
;
MipsPtrClass
PtrClassKind
=
static_cast
<
MipsPtrClass
>
(
Kind
)
;
switch
(
PtrClassKind
)
{
case
MipsPtrClass
::
Default
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GPR64RegClass
:
&
Mips
::
GPR32RegClass
;
case
MipsPtrClass
::
GPR16MM
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GPRMM16_64RegClass
:
&
Mips
::
GPRMM16RegClass
;
case
MipsPtrClass
::
StackPointer
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
SP64RegClass
:
&
Mips
::
SP32RegClass
;
case
MipsPtrClass
::
GlobalPointer
:
return
ABI
.
ArePtrs64bit
(
)
&
Mips
::
GP64RegClass
:
&
Mips
::
GP32RegClass
;
}
llvm_unreachable
(
"Unknown pointer kind"
)
;
}
</s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
OutOps
.
push_back
(
Op
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static void ix86_expand_ashl_const ( rtx operand , int count , machine_mode mode ) { rtx ( * insn ) ( rtx , rtx , rtx ) ; if ( count == 1 || ( count * ix86_cost -> add <= ix86_cost -> shift_const && ! optimize_insn_for_size_p ( ) ) ) { insn = mode == DImode ? gen_addsi3 : gen_adddi3 ; while ( count -- > 0 ) emit_insn ( insn ( operand , operand , operand ) ) ; } else { insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3 ; emit_insn ( insn ( operand , operand , GEN_INT ( count ) ) ) ; } } </s>

Helper function of ix86_split_ashl used to generate an SImode/DImode left shift by a constant , either using a single shift or a sequence of add instructions .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , Subtarget . isLittleEndian ( ) ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * GISel = new AArch64GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new AArch64MachineLegalizer ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( new AArch64InstructionSelector ( * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>


<s> rtx iq2000_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { int reg = GP_RETURN ; enum machine_mode mode = TYPE_MODE ( valtype ) ; int unsignedp = TYPE_UNSIGNED ( valtype ) ; mode = promote_mode ( valtype , mode , & unsignedp , 1 ) ; return gen_rtx_REG ( mode , reg ) ; } </s>

Return register to use for a function return value with VALTYPE for function FUNC .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT ; unsigned Imm , WhichResult ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTRNMask ( M , VT , WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
char
*
output_call
(
rtx_insn
*
insn
,
rtx
*
operands
,
int
dest_operand_number
,
int
cookie_operand_number
)
{
static
char
buf
[
256
]
;
if
(
darwin_emit_branch_islands
&&
GET_CODE
(
operands
[
dest_operand_number
]
)
==
SYMBOL_REF
&&
(
INTVAL
(
operands
[
cookie_operand_number
]
)
&
CALL_LONG
)
)
{
tree
labelname
;
tree
funname
=
get_identifier
(
XSTR
(
operands
[
dest_operand_number
]
,
0
)
)
;
if
(
no_previous_def
(
funname
)
)
{
rtx
label_rtx
=
gen_label_rtx
(
)
;
char
*
label_buf
,
temp_buf
[
256
]
;
ASM_GENERATE_INTERNAL_LABEL
(
temp_buf
,
"L"
,
CODE_LABEL_NUMBER
(
label_rtx
)
)
;
label_buf
=
temp_buf
[
0
]
==
'*'
temp_buf
+
1
:
temp_buf
;
labelname
=
get_identifier
(
label_buf
)
;
add_compiler_branch_island
(
labelname
,
funname
,
insn_line
(
insn
)
)
;
}
else
labelname
=
get_prev_label
(
funname
)
;
sprintf
(
buf
,
"jbsr %%z%d,%.246s"
,
dest_operand_number
,
IDENTIFIER_POINTER
(
labelname
)
)
;
}
else
sprintf
(
buf
,
"bl %%z%d"
,
dest_operand_number
)
;
return
buf
;
}
</s>

INSN is either a function call or a millicode call . It may have an unconditional jump in its delay slot . CALL_DEST is the routine we are calling .


<s> bool x86_extended_QIreg_mentioned_p ( rtx insn ) { int i ; extract_insn_cached ( insn ) ; for ( i = 0 ; i < recog_data . n_operands ; i ++ ) if ( REG_P ( recog_data . operand [ i ] ) && REGNO ( recog_data . operand [ i ] ) >= 4 ) return true ; return false ; } </s>

Return nonzero when QImode register that must be represented via REX prefix is used .


"\nrs6000_secondary_reload_gpr, type = %s\n"

Convert reloads involving 64-bit gprs and misaligned offset addressing , or multiple 32-bit gprs and offsets that are too large , to use indirect addressing .


<s> bool AArch64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( Subtarget -> isTargetILP32 ( ) && Ty -> isPointerTy ( ) ) return false ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f128 ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> void rs6000_gen_section_name ( char * * buf , const char * filename , const char * section_desc ) { const char * q , * after_last_slash , * last_period = 0 ; char * p ; int len ; after_last_slash = filename ; for ( q = filename ; * q ; q ++ ) { if ( * q == '/' ) after_last_slash = q + 1 ; else if ( * q == '.' ) last_period = q ; } len = strlen ( after_last_slash ) + strlen ( section_desc ) + 2 ; * buf = ( char * ) xmalloc ( len ) ; p = * buf ; * p ++ = '_' ; for ( q = after_last_slash ; * q ; q ++ ) { if ( q == last_period ) { strcpy ( p , section_desc ) ; p += strlen ( section_desc ) ; break ; } else if ( ISALNUM ( * q ) ) * p ++ = * q ; } if ( last_period == 0 ) strcpy ( p , section_desc ) ; else * p = '\0' ; } </s>

Generate a unique section name for FILENAME for a section type represented by SECTION_DESC . Output goes into BUF . SECTION_DESC can be any string , as long as it is different for each possible section type . We name the section in the same manner as xlc . The name begins with an underscore followed by the filename ( after stripping any leading directory names ) with the last period replaced by the string SECTION_DESC . If FILENAME does not contain a period , SECTION_DESC is appended to the end of the name .


<s> static bool sparc_vector_mode_supported_p ( machine_mode mode ) { return TARGET_VIS && VECTOR_MODE_P ( mode ) ? true : false ; } </s>

Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook . Specify whether the vector mode is supported by the hardware .


<s> std :: pair < unsigned , const TargetRegisterClass * > VETargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { const TargetRegisterClass * RC = nullptr ; if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; case 'r' : RC = & VE :: I64RegClass ; break ; case 'v' : RC = & VE :: V64RegClass ; break ; } return std :: make_pair ( 0U , RC ) ; } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> const AArch64Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static rtx rs6000_savres_routine_sym ( rs6000_stack_t * info , int sel ) { int regno = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save - 32 : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save - FIRST_ALTIVEC_REGNO : - 1 ) ; rtx sym ; int select = sel ; if ( TARGET_SPE_ABI && ( sel & SAVRES_REG ) == SAVRES_GPR && info -> spe_64bit_regs_used ) select ^= SAVRES_FPR ^ SAVRES_GPR ; gcc_assert ( FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER && select >= 0 && select <= 12 ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] ; if ( sym == NULL ) { char * name ; name = rs6000_savres_routine_name ( info , regno , sel ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_FUNCTION ; } return sym ; } </s>

Return an RTL SYMBOL_REF for an out-of-line register save/restore routine . We are saving/restoring GPRs if GPR is true .


<s> void gen_conditional_branch ( rtx operands [ ] , machine_mode mode ) { enum rtx_code test_code = GET_CODE ( operands [ 0 ] ) ; rtx cmp0 = operands [ 1 ] ; rtx cmp1 = operands [ 2 ] ; rtx reg ; int invert ; rtx label1 , label2 ; invert = 0 ; reg = gen_int_relational ( test_code , NULL_RTX , cmp0 , cmp1 , & invert ) ; if ( reg ) { cmp0 = reg ; cmp1 = const0_rtx ; test_code = NE ; } else if ( GET_CODE ( cmp1 ) == CONST_INT && INTVAL ( cmp1 ) != 0 ) cmp1 = force_reg ( mode , cmp1 ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; label2 = pc_rtx ; if ( invert ) { label2 = label1 ; label1 = pc_rtx ; } emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) , label1 , label2 ) ) ) ; } </s>

Emit the common code for doing conditional branches . operand [ 0 ] is the label to jump to . The comparison operands are saved away by cmp { si , di , sf , df } .


<s> static bool expand_vec_perm_pblendv ( struct expand_vec_perm_d * d ) { unsigned i , which , nelt = d -> nelt ; struct expand_vec_perm_d dcopy , dcopy1 ; machine_mode vmode = d -> vmode ; bool ok ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( vmode ) == 32 ) ; else if ( TARGET_AVX && ( vmode == V4DFmode || vmode == V8SFmode ) ) ; else if ( TARGET_SSE4_1 && ( GET_MODE_SIZE ( vmode ) == 16 || ( TARGET_MMX_WITH_SSE && GET_MODE_SIZE ( vmode ) == 8 ) || GET_MODE_SIZE ( vmode ) == 4 ) ) ; else return false ; for ( i = 0 , which = 0 ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e != i ) which |= ( e < nelt ? 1 : 2 ) ; } if ( which != 1 && which != 2 ) return false ; if ( d -> testing_p && GET_MODE_SIZE ( vmode ) == 16 ) return true ; dcopy = * d ; if ( which == 2 ) dcopy . op0 = dcopy . op1 = d -> op1 ; else dcopy . op0 = dcopy . op1 = d -> op0 ; if ( ! d -> testing_p ) dcopy . target = gen_reg_rtx ( vmode ) ; dcopy . one_operand_p = true ; for ( i = 0 ; i < nelt ; ++ i ) dcopy . perm [ i ] = d -> perm [ i ] & ( nelt - 1 ) ; ok = expand_vec_perm_1 ( & dcopy ) ; if ( GET_MODE_SIZE ( vmode ) != 16 && ! ok ) return false ; else gcc_assert ( ok ) ; if ( d -> testing_p ) return true ; dcopy1 = * d ; if ( which == 2 ) dcopy1 . op1 = dcopy . target ; else dcopy1 . op0 = dcopy . target ; for ( i = 0 ; i < nelt ; ++ i ) dcopy1 . perm [ i ] = ( ( d -> perm [ i ] >= nelt ) ? ( nelt + i ) : i ) ; ok = expand_vec_perm_blend ( & dcopy1 ) ; gcc_assert ( ok ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_const_1 . Try to simplify the permutation using the SSE4_1 pblendv instruction . Potentially reduces permutation from 2 pshufb and or to 1 pshufb and pblendv .


"execute-only should not generate constant pools"

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> static bool pru_repeat_loop_p ( struct pru_doloop * loop ) { struct pru_doloop_end * end ; rtx_insn * fallthrough ; if ( loop -> begin == 0 || loop -> end == 0 || loop -> begin -> next != 0 ) return false ; if ( prev_real_insn ( as_a < rtx_insn * > ( loop -> end -> label ) ) != loop -> begin -> insn ) return false ; if ( get_attr_length ( loop -> end -> insn ) != 4 ) return false ; fallthrough = loop -> end -> fallthrough ; for ( end = loop -> end -> next ; end != 0 ; end = end -> next ) if ( end -> label != loop -> end -> label || ! simplejump_p ( end -> fallthrough ) || fallthrough != next_real_insn ( JUMP_LABEL_AS_INSN ( end -> fallthrough ) ) ) return false ; return true ; } </s>

Return true if LOOP can be converted into LOOP form ( that is , if it matches cases ( 1 ) or ( 2 ) above ) .


<s> bool aarch64_harden_sls_blr_p ( void ) { return aarch64_sls_hardening & SLS_BLR ; } </s>

Return whether we should mitigatate Straight Line Speculation for the BLR instruction .


<s> static int pa_adjust_priority ( rtx insn , int priority ) { rtx set = single_set ( insn ) ; rtx src , dest ; if ( set ) { src = SET_SRC ( set ) ; dest = SET_DEST ( set ) ; if ( GET_CODE ( src ) == LO_SUM && symbolic_operand ( XEXP ( src , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( src , 1 ) , VOIDmode ) ) priority >>= 3 ; else if ( GET_CODE ( src ) == MEM && GET_CODE ( XEXP ( src , 0 ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( src , 0 ) , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( XEXP ( src , 0 ) , 1 ) , VOIDmode ) ) priority >>= 1 ; else if ( GET_CODE ( dest ) == MEM && GET_CODE ( XEXP ( dest , 0 ) ) == LO_SUM && symbolic_operand ( XEXP ( XEXP ( dest , 0 ) , 1 ) , VOIDmode ) && ! read_only_operand ( XEXP ( XEXP ( dest , 0 ) , 1 ) , VOIDmode ) ) priority >>= 3 ; } return priority ; } </s>

Adjust scheduling priorities . We use this to try and keep addil and the next use of % r1 close together .


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'U' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
->
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
->
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
!
Subtarget
->
useRetpoline
(
)
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
callRegIndirect
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


"Don't know how to handle that operation"


<s>
static
void
replace_swap_with_copy
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
copy
=
gen_rtx_SET
(
SET_DEST
(
body
)
,
src_reg
)
;
rtx_insn
*
new_insn
=
emit_insn_before
(
copy
,
insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
insn
)
)
;
df_insn_rescan
(
new_insn
)
;
if
(
dump_file
)
{
unsigned
int
new_uid
=
INSN_UID
(
new_insn
)
;
fprintf
(
dump_file
,
"Replacing swap %d with copy %d\n"
,
i
,
new_uid
)
;
}
df_insn_delete
(
insn
)
;
remove_insn
(
insn
)
;
insn
->
set_deleted
(
)
;
}
</s>

Find the insn from the Ith table entry , which is known to be a register swap Y = SWAP ( X ) . Replace it with a copy Y = X .


<s> bool ix86_notrack_prefixed_insn_p ( rtx_insn * insn ) { if ( ! insn || ! ( ( flag_cf_protection & CF_BRANCH ) ) ) return false ; if ( CALL_P ( insn ) ) { rtx call = get_call_rtx_from ( insn ) ; gcc_assert ( call != NULL_RTX ) ; rtx addr = XEXP ( call , 0 ) ; if ( MEM_P ( addr ) && GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF ) return false ; else return find_reg_note ( insn , REG_CALL_NOCF_CHECK , 0 ) ; } if ( JUMP_P ( insn ) && ! flag_cet_switch ) { rtx target = JUMP_LABEL ( insn ) ; if ( target == NULL_RTX || ANY_RETURN_P ( target ) ) return false ; rtx_insn * label = as_a < rtx_insn * > ( target ) ; rtx_insn * table = next_insn ( label ) ; if ( table == NULL_RTX || ! JUMP_TABLE_DATA_P ( table ) ) return false ; else return true ; } return false ; } </s>

Return 1 if control tansfer instruction INSN should be encoded with notrack prefix .


"getJumpTargetOpValue expects only expressions"

"unexpect opcode in getJumpAbsoluteTargetOpValue()"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> unsigned int ix86_get_callcvt ( const_tree type ) { unsigned int ret = 0 ; bool is_stdarg ; tree attrs ; if ( TARGET_64BIT ) return IX86_CALLCVT_CDECL ; attrs = TYPE_ATTRIBUTES ( type ) ; if ( attrs != NULL_TREE ) { if ( lookup_attribute ( "cdecl" , attrs ) ) ret |= IX86_CALLCVT_CDECL ; else if ( lookup_attribute ( "stdcall" , attrs ) ) ret |= IX86_CALLCVT_STDCALL ; else if ( lookup_attribute ( "fastcall" , attrs ) ) ret |= IX86_CALLCVT_FASTCALL ; else if ( lookup_attribute ( "thiscall" , attrs ) ) ret |= IX86_CALLCVT_THISCALL ; if ( ( ret & ( IX86_CALLCVT_THISCALL | IX86_CALLCVT_FASTCALL ) ) == 0 ) { if ( lookup_attribute ( "regparm" , attrs ) ) ret |= IX86_CALLCVT_REGPARM ; if ( lookup_attribute ( "sseregparm" , attrs ) ) ret |= IX86_CALLCVT_SSEREGPARM ; } if ( IX86_BASE_CALLCVT ( ret ) != 0 ) return ret ; } is_stdarg = stdarg_p ( type ) ; if ( TARGET_RTD && ! is_stdarg ) return IX86_CALLCVT_STDCALL | ret ; if ( ret != 0 || is_stdarg || TREE_CODE ( type ) != METHOD_TYPE || ix86_function_type_abi ( type ) != MS_ABI ) return IX86_CALLCVT_CDECL | ret ; return IX86_CALLCVT_THISCALL ; } </s>

This function determines from TYPE the calling-convention .


<s>
bool
SystemZInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
SystemZII
::
Branch
Branch
(
getBranchInfo
(
*
I
)
)
;
if
(
!
Branch
.
hasMBBTarget
(
)
)
return
true
;
if
(
Branch
.
Type
!=
SystemZII
::
BranchNormal
)
return
true
;
if
(
Branch
.
CCMask
==
SystemZ
::
CCMASK_ANY
)
{
if
(
!
AllowModify
)
{
TBB
=
Branch
.
getMBBTarget
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
Branch
.
getMBBTarget
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
Branch
.
getMBBTarget
(
)
;
continue
;
}
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
Branch
.
getMBBTarget
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCValid
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCMask
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
2
&&
TBB
&&
"Should have seen a conditional branch"
)
;
if
(
TBB
!=
Branch
.
getMBBTarget
(
)
)
return
true
;
unsigned
OldCCValid
=
Cond
[
0
]
.
getImm
(
)
;
unsigned
OldCCMask
=
Cond
[
1
]
.
getImm
(
)
;
if
(
OldCCValid
==
Branch
.
CCValid
&&
OldCCMask
==
Branch
.
CCMask
)
continue
;
return
false
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static bool arm_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_march_ : arm_select [ 1 ] . string = arg ; return true ; case OPT_mcpu_ : arm_select [ 0 ] . string = arg ; return true ; case OPT_mhard_float : target_float_abi_name = "hard" ; return true ; case OPT_msoft_float : target_float_abi_name = "soft" ; return true ; case OPT_mtune_ : arm_select [ 2 ] . string = arg ; return true ; default : return true ; } } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Indirect Branch Tracking"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Expected SVE area to be calculated by this point"

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> void pa_output_addr_diff_vec ( rtx lab , rtx body ) { rtx base = XEXP ( XEXP ( body , 0 ) , 0 ) ; int idx , vlen = XVECLEN ( body , 1 ) ; targetm . asm_out . internal_label ( asm_out_file , "L" , CODE_LABEL_NUMBER ( lab ) ) ; if ( TARGET_GAS ) fputs ( "\t.begin_brtab\n" , asm_out_file ) ; for ( idx = 0 ; idx < vlen ; idx ++ ) { ASM_OUTPUT_ADDR_DIFF_ELT ( asm_out_file , body , CODE_LABEL_NUMBER ( XEXP ( XVECEXP ( body , 1 , idx ) , 0 ) ) , CODE_LABEL_NUMBER ( base ) ) ; } if ( TARGET_GAS ) fputs ( "\t.end_brtab\n" , asm_out_file ) ; } </s>


<s> int memory_address_length ( rtx addr , bool lea ) { struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return 0 ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == ADDR_SPACE_GENERIC ) ? 0 : 1 ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ; if ( base && SUBREG_P ( base ) ) base = SUBREG_REG ( base ) ; if ( index && SUBREG_P ( index ) ) index = SUBREG_REG ( index ) ; gcc_assert ( base == NULL_RTX || REG_P ( base ) ) ; gcc_assert ( index == NULL_RTX || REG_P ( index ) ) ; if ( base && ! index && ! disp ) { if ( base == arg_pointer_rtx || base == frame_pointer_rtx || REGNO ( base ) == SP_REG || REGNO ( base ) == BP_REG || REGNO ( base ) == R12_REG || REGNO ( base ) == R13_REG ) len ++ ; } else if ( disp && ! base && ! index ) { len += 4 ; if ( rip_relative_addr_p ( & parts ) ) len ++ ; } else { if ( disp ) { if ( base && satisfies_constraint_K ( disp ) ) len += 1 ; else len += 4 ; } else if ( base && ( REGNO ( base ) == BP_REG || REGNO ( base ) == R13_REG ) ) len ++ ; if ( index || base == arg_pointer_rtx || base == frame_pointer_rtx || ( base && ( REGNO ( base ) == SP_REG || REGNO ( base ) == R12_REG ) ) ) len ++ ; } return len ; } </s>

Calculate the length of the memory address in the instruction encoding . Does not include the one-byte modrm , opcode , or prefix .


<s> static bool arm_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { rtx base , offset ; if ( ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P ) { split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base , INTVAL ( offset ) ) ) return true ; } return arm_tls_referenced_p ( x ) ; } </s>


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
O
<<
"0, "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static bool aarch64_pragma_target_parse ( tree args , tree pop_target ) { if ( args ) { if ( ! aarch64_process_target_attr ( args ) ) return false ; aarch64_override_options_internal ( & global_options ) ; } else { pop_target = pop_target ? pop_target : target_option_default_node ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( pop_target ) ) ; } target_option_current_node = build_target_option_node ( & global_options , & global_options_set ) ; aarch64_reset_previous_fndecl ( ) ; cpp_options * cpp_opts = cpp_get_options ( parse_in ) ; unsigned char saved_warn_unused_macros = cpp_opts -> warn_unused_macros ; cpp_opts -> warn_unused_macros = 0 ; cpp_force_token_locations ( parse_in , BUILTINS_LOCATION ) ; aarch64_update_cpp_builtins ( parse_in ) ; cpp_stop_forcing_token_locations ( parse_in ) ; cpp_opts -> warn_unused_macros = saved_warn_unused_macros ; if ( pop_target ) aarch64_save_restore_target_globals ( pop_target ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } return true ; } </s>

Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { PM . add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { PM . add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void aarch64_expand_sve_const_vector ( rtx dest , rtx src ) { machine_mode mode = GET_MODE ( src ) ; unsigned int npatterns = CONST_VECTOR_NPATTERNS ( src ) ; unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN ( src ) ; gcc_assert ( npatterns > 1 ) ; if ( nelts_per_pattern == 1 ) { scalar_int_mode int_mode ; if ( BYTES_BIG_ENDIAN ) int_mode = TImode ; else { unsigned int int_bits = GET_MODE_UNIT_BITSIZE ( mode ) * npatterns ; gcc_assert ( int_bits <= 128 ) ; int_mode = int_mode_for_size ( int_bits , 0 ) . require ( ) ; } rtx int_value = simplify_gen_subreg ( int_mode , src , mode , 0 ) ; if ( int_value && aarch64_expand_sve_widened_duplicate ( dest , int_mode , int_value ) ) return ; } rtx_vector_builder builder ; auto_vec < rtx , 16 > vectors ( npatterns ) ; for ( unsigned int i = 0 ; i < npatterns ; ++ i ) { builder . new_vector ( mode , 1 , nelts_per_pattern ) ; for ( unsigned int j = 0 ; j < nelts_per_pattern ; ++ j ) builder . quick_push ( CONST_VECTOR_ELT ( src , i + j * npatterns ) ) ; vectors . quick_push ( force_reg ( mode , builder . build ( ) ) ) ; } while ( npatterns > 1 ) { npatterns /= 2 ; for ( unsigned int i = 0 ; i < npatterns ; ++ i ) { rtx tmp = ( npatterns == 1 ? dest : gen_reg_rtx ( mode ) ) ; rtvec v = gen_rtvec ( 2 , vectors [ i ] , vectors [ i + npatterns ] ) ; emit_set_insn ( tmp , gen_rtx_UNSPEC ( mode , v , UNSPEC_ZIP1 ) ) ; vectors [ i ] = tmp ; } } gcc_assert ( vectors [ 0 ] == dest ) ; } </s>

Expand a move of general CONST_VECTOR SRC into DEST , given that it is n't a simple duplicate or series .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Emit GP Restore"
;
}
</s>


<s> static void union_defs ( swap_web_entry * insn_entry , rtx insn , df_ref use ) { struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( def_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing definitions that reach USE . Detect whether USE is live-in to the current function .


<s> void i960_initialize ( ) { if ( TARGET_IC_COMPAT2_0 ) { i960_maxbitalignment = 8 ; i960_last_maxbitalignment = 128 ; } else { i960_maxbitalignment = 128 ; i960_last_maxbitalignment = 8 ; } } </s>

Initialize variables before compiling any files .


<s> bool ARMBaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , const MachineOperand * & Destination , const MachineOperand * & Source , int64_t & Offset ) const { int Sign = 1 ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == ARM :: SUBri ) Sign = - 1 ; else if ( Opcode != ARM :: ADDri ) return false ; if ( ! MI . getOperand ( 0 ) . isReg ( ) || ! MI . getOperand ( 1 ) . isReg ( ) || ! MI . getOperand ( 2 ) . isImm ( ) ) return false ; Destination = & MI . getOperand ( 0 ) ; Source = & MI . getOperand ( 1 ) ; Offset = MI . getOperand ( 2 ) . getImm ( ) * Sign ; return true ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> static bool arm_cannot_copy_insn_p ( rtx_insn * insn ) { if ( recog_memoized ( insn ) == CODE_FOR_tlscall ) return true ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC_BASE || XINT ( x , 1 ) == UNSPEC_PIC_UNIFIED ) ) return true ; } rtx set = single_set ( insn ) ; if ( set ) { rtx src = SET_SRC ( set ) ; if ( GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , 0 ) ; if ( GET_CODE ( src ) == UNSPEC_VOLATILE && ( XINT ( src , 1 ) == VUNSPEC_LL || XINT ( src , 1 ) == VUNSPEC_LAX ) ) return true ; } return false ; } </s>

Must not copy any rtx that uses a pc-relative address .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const MipsDisassembler * Dis = static_cast < const MipsDisassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
switch
(
(
unsigned
)
Kind
)
{
case
CAHP
::
fixup_cahp_hi6
:
{
const
static
MCFixupKindInfo
info
{
"fixup_cahp_hi6"
,
0
,
16
,
0
}
;
return
info
;
}
case
CAHP
::
fixup_cahp_lo10
:
{
const
static
MCFixupKindInfo
info
{
"fixup_cahp_lo10"
,
0
,
24
,
0
}
;
return
info
;
}
case
CAHP
::
fixup_cahp_pcrel_10
:
{
const
static
MCFixupKindInfo
info
{
"fixup_cahp_pcrel_10"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
;
return
info
;
}
case
CAHP
::
fixup_cahp_pcrel_11
:
{
const
static
MCFixupKindInfo
info
{
"fixup_cahp_pcrel_11"
,
5
,
11
,
MCFixupKindInfo
::
FKF_IsPCRel
}
;
return
info
;
}
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
}
</s>


<s>
void
SparcMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
unsigned
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
if
(
Ctx
.
getAsmInfo
(
)
->
isLittleEndian
(
)
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
unsigned
tlsOpNo
=
0
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
SP
::
TLS_CALL
:
tlsOpNo
=
1
;
break
;
case
SP
::
TLS_ADDrr
:
case
SP
::
TLS_ADDXrr
:
case
SP
::
TLS_LDrr
:
case
SP
::
TLS_LDXrr
:
tlsOpNo
=
3
;
break
;
}
if
(
tlsOpNo
!=
0
)
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
tlsOpNo
)
;
uint64_t
op
=
getMachineOpValue
(
MI
,
MO
,
Fixups
,
STI
)
;
assert
(
op
==
0
&&
"Unexpected operand value!"
)
;
(
void
)
op
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( GET_CODE ( XVECEXP ( x , 0 , 0 ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s> static bool mips_print_operand_punct_valid_p ( unsigned char code ) { return mips_print_operand_punct [ code ] ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const MachineFunction & MF ) const { bool NoFloat = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? 64 : 32 ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } if ( MemVT . getSizeInBits ( ) > Subtarget . getPreferVectorWidth ( ) ) return false ; return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static void rx_get_stack_layout ( unsigned int * lowest , unsigned int * highest , unsigned int * register_mask , unsigned int * frame_size , unsigned int * stack_size ) { unsigned int reg ; unsigned int low ; unsigned int high ; unsigned int fixed_reg = 0 ; unsigned int save_mask ; unsigned int pushed_mask ; unsigned int unneeded_pushes ; if ( is_naked_func ( NULL_TREE ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = 0 ; * frame_size = 0 ; * stack_size = 0 ; return ; } for ( save_mask = high = low = 0 , reg = 1 ; reg < CC_REGNUM ; reg ++ ) { if ( ( df_regs_ever_live_p ( reg ) || ( call_used_regs [ reg ] && is_interrupt_func ( NULL_TREE ) && ! crtl -> is_leaf ) ) && ( ! call_used_regs [ reg ] || is_interrupt_func ( NULL_TREE ) || ( is_fast_interrupt_func ( NULL_TREE ) && ! IN_RANGE ( reg , 10 , 13 ) ) ) ) { if ( low == 0 ) low = reg ; high = reg ; save_mask |= 1 << reg ; } if ( low != 0 && fixed_reg == 0 && fixed_regs [ reg ] ) fixed_reg = reg ; } if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < 2 ) { save_mask |= ( 1 << 13 ) | ( 1 << 14 ) ; if ( low == 0 ) low = 13 ; if ( high == 0 || low == high ) high = low + 1 ; } pushed_mask = ( - 1 << low ) & ~ ( - 1 << ( high + 1 ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = save_mask ; } else { * lowest = low ; * highest = high ; * register_mask = 0 ; } * frame_size = rx_round_up ( get_frame_size ( ) , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( crtl -> args . size > 0 ) * frame_size += rx_round_up ( crtl -> args . size , STACK_BOUNDARY / BITS_PER_UNIT ) ; * stack_size = rx_round_up ( crtl -> outgoing_args_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>

Returns either the lowest numbered and highest numbered registers that occupy the call-saved area of the stack frame , if the registers are stored as a contiguous block , or else a bitmask of the individual registers if they are stored piecemeal . Also computes the size of the frame and the size of the outgoing arguments block ( in bytes ) .


<s> uint64_t MipsAbiFlags :: size ( ) { return sizeof ( ElfMipsAbiFlags ) ; } </s>

The number of name/type pairs is returned .


<s>
unsigned
SparcRegisterInfo
::
getRARegister
(
)
const
{
assert
(
0
&&
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s> static void ix86_emit_restore_reg_using_pop ( rtx reg ) { struct machine_function * m = cfun -> machine ; rtx insn = emit_insn ( gen_pop ( reg ) ) ; ix86_add_cfa_restore_note ( insn , reg , m -> fs . sp_offset ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; if ( m -> fs . cfa_reg == crtl -> drap_reg && REGNO ( reg ) == REGNO ( crtl -> drap_reg ) ) { add_reg_note ( insn , REG_CFA_DEF_CFA , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . drap_valid = true ; return ; } if ( m -> fs . cfa_reg == stack_pointer_rtx ) { rtx x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . cfa_offset -= UNITS_PER_WORD ; } if ( reg == hard_frame_pointer_rtx ) { m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset -= UNITS_PER_WORD ; add_reg_note ( insn , REG_CFA_DEF_CFA , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( m -> fs . cfa_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } </s>

Emit code to restore REG using a POP insn .