<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto DL = MIRBuilder . getMF ( ) . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto & Args = F . getArgumentList ( ) ; unsigned ArgIdx = 0 ; for ( auto & Arg : Args ) { ArgIdx ++ ; if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( ArgIdx > 4 && Arg . getType ( ) -> getIntegerBitWidth ( ) != 32 ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : Args ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; ArgInfos . push_back ( AInfo ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; return handleAssignments ( MIRBuilder , AssignFn , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ this ] ( const Function & F ) { return ! this -> TM -> getSubtarget < ARMSubtarget > ( F ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM


<s> unsigned ARM64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM64 :: GPR32RegClassID : case ARM64 :: GPR32spRegClassID : case ARM64 :: GPR32allRegClassID : case ARM64 :: GPR64spRegClassID : case ARM64 :: GPR64allRegClassID : case ARM64 :: GPR64RegClassID : case ARM64 :: GPR32commonRegClassID : case ARM64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case ARM64 :: FPR8RegClassID : case ARM64 :: FPR16RegClassID : case ARM64 :: FPR32RegClassID : case ARM64 :: FPR64RegClassID : case ARM64 :: FPR128RegClassID : return 32 ; case ARM64 :: DDRegClassID : case ARM64 :: DDDRegClassID : case ARM64 :: DDDDRegClassID : case ARM64 :: QQRegClassID : case ARM64 :: QQQRegClassID : case ARM64 :: QQQQRegClassID : return 32 ; case ARM64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr * MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI -> getOpcode ( ) ) ) return 0 ; OpNum = 1 ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isUndef ( ) && TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { return 16 ; } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> unsigned char X86Subtarget :: classifyLocalReference ( const GlobalValue * GV ) const { if ( is64Bit ( ) ) return X86II :: MO_NO_FLAG ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return X86II :: MO_NO_FLAG ; if ( isTargetCOFF ( ) ) return X86II :: MO_NO_FLAG ; if ( isTargetDarwin ( ) ) { if ( GV && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; return X86II :: MO_PIC_BASE_OFFSET ; } return X86II :: MO_GOTOFF ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> bool vax_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { rtx xfoo0 , xfoo1 ; if ( nonindexed_address_p ( x , strict ) ) return true ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( index_term_p ( xfoo0 , mode , strict ) && nonindexed_address_p ( xfoo1 , strict ) ) return true ; if ( index_term_p ( xfoo1 , mode , strict ) && nonindexed_address_p ( xfoo0 , strict ) ) return true ; if ( indexable_address_p ( xfoo0 , xfoo1 , mode , strict ) || indexable_address_p ( xfoo1 , xfoo0 , mode , strict ) ) return true ; return false ; } </s>

legitimate_address_p returns true if it recognizes an RTL expression `` x '' that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> static void ia64_option_override ( void ) { unsigned int i ; cl_deferred_option * opt ; vec < cl_deferred_option > * v = ( vec < cl_deferred_option > * ) ia64_deferred_options ; if ( v ) FOR_EACH_VEC_ELT ( * v , i , opt ) { switch ( opt -> opt_index ) { case OPT_mfixed_range_ : fix_range ( opt -> arg ) ; break ; default : gcc_unreachable ( ) ; } } if ( TARGET_AUTO_PIC ) target_flags |= MASK_CONST_GP ; if ( optimize >= 3 ) flag_ira_loop_pressure = 1 ; ia64_section_threshold = ( OPTION_SET_P ( g_switch_value ) ? g_switch_value : IA64_DEFAULT_GVALUE ) ; init_machine_status = ia64_init_machine_status ; if ( flag_align_functions && ! str_align_functions ) str_align_functions = "64" ; if ( flag_align_loops && ! str_align_loops ) str_align_loops = "32" ; if ( TARGET_ABI_OPEN_VMS ) flag_no_common = 1 ; ia64_override_options_after_change ( ) ; } </s>


<s> static void ix86_emit_cmove ( rtx dst , rtx src , enum rtx_code code , rtx op1 , rtx op2 ) { rtx t ; if ( TARGET_CMOVE ) { t = ix86_expand_compare ( code , op1 , op2 ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dst ) , t , src , dst ) ) ) ; } else { rtx_code_label * nomove = gen_label_rtx ( ) ; emit_cmp_and_jump_insns ( op1 , op2 , reverse_condition ( code ) , const0_rtx , GET_MODE ( op1 ) , 1 , nomove ) ; emit_move_insn ( dst , src ) ; emit_label ( nomove ) ; } } </s>

Emit conditional move of SRC to DST with condition OP1 CODE OP2 .


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; switch ( mode ) { case E_QImode : fn = gen_load_lockedqi ; break ; case E_HImode : fn = gen_load_lockedhi ; break ; case E_SImode : if ( GET_MODE ( mem ) == QImode ) fn = gen_load_lockedqi_si ; else if ( GET_MODE ( mem ) == HImode ) fn = gen_load_lockedhi_si ; else fn = gen_load_lockedsi ; break ; case E_DImode : fn = gen_load_lockeddi ; break ; case E_TImode : fn = gen_load_lockedti ; break ; default : gcc_unreachable ( ) ; } emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s>
void
SystemZPostRASchedStrategy
::
leaveMBB
(
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Leaving MBB#"
<<
MBB
->
getNumber
(
)
<<
"\n"
;
)
;
advanceTo
(
MBB
->
getFirstTerminator
(
)
)
;
}
</s>

Tell the strategy that current MBB is done .


<s> fma_node * func_fma_steering :: get_fma_node ( rtx_insn * insn ) { fma_node * * fma_slot ; fma_slot = this -> m_insn_fma_head_map -> get ( insn ) ; if ( fma_slot ) return * fma_slot ; return NULL ; } </s>

Return whether an fma_node object exists for instruction INSN and , if not , allocate one in * RET .


<s> void xstormy16_expand_move ( machine_mode mode , rtx dest , rtx src ) { if ( MEM_P ( dest ) && ( GET_CODE ( XEXP ( dest , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( dest , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( Pmode , dest_reg , dest_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; dest = gen_rtx_MEM ( mode , dest_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else if ( MEM_P ( src ) && ( GET_CODE ( XEXP ( src , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( src , 0 ) ; rtx src_reg = XEXP ( pmv , 0 ) ; rtx src_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( Pmode , src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && MEM_P ( dest ) && ( ! CONST_INT_P ( XEXP ( dest , 0 ) ) || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , 0 ) , 0 ) ) && ! xstormy16_below100_operand ( dest , mode ) && ! REG_P ( src ) && GET_CODE ( src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ; if ( reload_completed && mode != HImode && mode != QImode ) { xstormy16_split_move ( mode , dest , src ) ; return ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; } </s>

Expander for the 'move ' patterns . Emit insns to copy a value of mode MODE from SRC to DEST .


<s> int get_dest_uid ( rtx label , int max_uid ) { rtx_insn * dest = next_real_insn ( label ) ; int dest_uid ; if ( ! dest ) return 0 ; dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return 0 ; return dest_uid ; } </s>

Return the UID of the insn that follows the specified label .


<s> formatted_raw_ostream & getOStream ( ) { return OS ; } </s>

getOStream - Get the raw output stream into the graph file .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
TargetCostKind
CostKind
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
,
const
Instruction
*
CxtI
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
int
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
CostKind
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; if ( ! TARGET_64BIT ) return 0 ; if ( FUNCTION_ARG_SIZE ( mode , type ) > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + FUNCTION_ARG_SIZE ( mode , type ) <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; if ( isInt < 16 > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SaveRaF16 ) ) . addImm ( StackSize ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void aarch64_adjust_generic_arch_tuning ( struct tune_params & current_tune ) { if ( TARGET_SVE2 ) current_tune . extra_tuning_flags &= ~ AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS ; } </s>

Adjust CURRENT_TUNE ( a generic tuning struct ) with settings that are best for a generic target with the currently-enabled architecture extensions .


<s> static rtx rs6000_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; tree arglist = TREE_OPERAND ( exp , 1 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; struct builtin_description * d ; size_t i ; rtx ret ; bool success ; if ( fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE ) { int icode = ( int ) CODE_FOR_altivec_lvsr ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode = insn_data [ icode ] . operand [ 1 ] . mode ; tree arg ; rtx op , addr , pat ; gcc_assert ( TARGET_ALTIVEC ) ; arg = TREE_VALUE ( arglist ) ; gcc_assert ( TREE_CODE ( TREE_TYPE ( arg ) ) == POINTER_TYPE ) ; op = expand_expr ( arg , NULL_RTX , Pmode , EXPAND_NORMAL ) ; addr = memory_address ( mode , op ) ; if ( fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE ) op = addr ; else { op = gen_reg_rtx ( GET_MODE ( addr ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op , gen_rtx_NEG ( GET_MODE ( addr ) , addr ) ) ) ; } op = gen_rtx_MEM ( mode , op ) ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target , op ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } if ( TARGET_ALTIVEC ) { ret = altivec_expand_builtin ( exp , target , & success ) ; if ( success ) return ret ; } if ( TARGET_SPE ) { ret = spe_expand_builtin ( exp , target , & success ) ; if ( success ) return ret ; } gcc_assert ( TARGET_ALTIVEC || TARGET_SPE ) ; d = ( struct builtin_description * ) bdesc_1arg ; for ( i = 0 ; i < ARRAY_SIZE ( bdesc_1arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return rs6000_expand_unop_builtin ( d -> icode , arglist , target ) ; d = ( struct builtin_description * ) bdesc_2arg ; for ( i = 0 ; i < ARRAY_SIZE ( bdesc_2arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return rs6000_expand_binop_builtin ( d -> icode , arglist , target ) ; d = ( struct builtin_description * ) bdesc_3arg ; for ( i = 0 ; i < ARRAY_SIZE ( bdesc_3arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return rs6000_expand_ternop_builtin ( d -> icode , arglist , target ) ; gcc_unreachable ( ) ; } </s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored . Use the new builtin infrastructure .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool save_local_or_in_reg_p ( unsigned int regno , int leaf_function ) { if ( ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM ) ) return true ; return false ; } </s>

Return whether REGNO , a local or in register , must be saved/restored .


<s> static void mips_finish_stub ( mips_one_only_stub * * stub_ptr ) { mips_one_only_stub * stub = * stub_ptr ; if ( ! stub ) return ; const char * name = stub -> get_name ( ) ; mips_start_unique_function ( name ) ; mips_start_function_definition ( name , false ) ; stub -> output_body ( ) ; mips_end_function_definition ( name ) ; delete stub ; * stub_ptr = 0 ; } </s>

If * STUB_PTR points to a stub , output a comdat-style definition for it , then free * STUB_PTR .


<s> static rtx_insn * rs6000_emit_savres_rtx ( rs6000_stack_t * info , rtx frame_reg_rtx , int save_area_offset , int lr_offset , machine_mode reg_mode , int sel ) { int i ; int offset , start_reg , end_reg , n_regs , use_reg ; int reg_size = GET_MODE_SIZE ( reg_mode ) ; rtx sym ; rtvec p ; rtx par ; rtx_insn * insn ; offset = 0 ; start_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save : - 1 ) ; end_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? 32 : ( sel & SAVRES_REG ) == SAVRES_FPR ? 64 : ( sel & SAVRES_REG ) == SAVRES_VR ? LAST_ALTIVEC_REGNO + 1 : - 1 ) ; n_regs = end_reg - start_reg ; p = rtvec_alloc ( 3 + ( ( sel & SAVRES_LR ) ? 1 : 0 ) + ( ( sel & SAVRES_REG ) == SAVRES_VR ? 1 : 0 ) + n_regs ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , offset ++ ) = ret_rtx ; RTVEC_ELT ( p , offset ++ ) = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_hard_reg_clobber ( Pmode , use_reg ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , 0 ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = 0 ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != 0 ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , 0 ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) { insn = emit_jump_insn ( par ) ; JUMP_LABEL ( insn ) = ret_rtx ; } else insn = emit_insn ( par ) ; return insn ; } </s>

Construct a parallel rtx describing the effect of a call to an out-of-line register save/restore routine , and emit the insn or jump_insn as appropriate .


<s> void mips_save_gp_to_cprestore_slot ( rtx mem , rtx offset , rtx gp , rtx temp ) { if ( TARGET_CPRESTORE_DIRECTIVE ) { gcc_assert ( gp == pic_offset_table_rtx ) ; emit_insn ( PMODE_INSN ( gen_cprestore , ( mem , offset ) ) ) ; } else mips_emit_move ( mips_cprestore_slot ( temp , false ) , gp ) ; } </s>

Emit instructions to save global pointer value GP into cprestore slot MEM . OFFSET is the offset that MEM applies to the base register . MEM may not be a legitimate address . If it is n't , TEMP is a temporary register that can be used , otherwise it is a SCRATCH .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a vector or scalar argument . Return true if it is , otherwise report an appropriate error .


<s> const ARMBaseRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned SparcAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { SparcOperand & Op = ( SparcOperand & ) GOp ; if ( Op . isFloatOrDoubleReg ( ) ) { switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op . isFloatReg ( ) || SparcOperand :: MorphToDoubleReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( SparcOperand :: MorphToQuadReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } } if ( Op . isIntReg ( ) && Kind == MCK_IntPair ) { if ( SparcOperand :: MorphToIntPairReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Sparc Sparc Sparc Sparc SparcOperand::MorphToDoubleReg SparcOperand::MorphToQuadReg SparcOperand::MorphToIntPairReg


<s> static void finish_bundle_states ( void ) { struct bundle_state * curr_state , * next_state ; for ( curr_state = allocated_bundle_states_chain ; curr_state != NULL ; curr_state = next_state ) { next_state = curr_state -> allocated_states_chain ; free ( curr_state -> dfa_state ) ; free ( curr_state ) ; } } </s>

Finish work with abstract data ` bundle states ' .


<s> static bool or1k_function_ok_for_sibcall ( tree decl , tree ) { if ( ! flag_pic ) return true ; if ( decl == NULL ) return true ; return targetm . binds_local_p ( decl ) ; } </s>

Worker for TARGET_FUNCTION_OK_FOR_SIBCALL . Returns true if the function declared by DECL is ok for calling as a nested function .


<s> const ARMBaseInstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>


<s> SDValue PPCTargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) ) { RefinementSteps = Subtarget . hasRecipPrec ( ) ? 1 : 3 ; if ( VT . getScalarType ( ) == MVT :: f64 ) ++ RefinementSteps ; return DCI . DAG . getNode ( PPCISD :: FRE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static rtx sparc_got ( void ) { if ( ! sparc_got_symbol ) sparc_got_symbol = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; return sparc_got_symbol ; } </s>

Return the SYMBOL_REF for the Global Offset Table .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Address Type Promotion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"********** AArch64 Conditional Branch Tuning  **********\n"

runOnMachineFunction - Emit the function body .


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeSizeInBits
(
SubVecTy
)
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> static enum rtx_code ix86_prepare_fp_compare_args ( enum rtx_code code , rtx * pop0 , rtx * pop1 ) { machine_mode fpcmp_mode = ix86_fp_compare_mode ( code ) ; rtx op0 = * pop0 , op1 = * pop1 ; machine_mode op_mode = GET_MODE ( op0 ) ; int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( op_mode ) ; if ( ! is_sse && ( fpcmp_mode == CCFPUmode || ( op_mode == XFmode && ! ( standard_80387_constant_p ( op0 ) == 1 || standard_80387_constant_p ( op1 ) == 1 ) && GET_CODE ( op1 ) != FLOAT ) || ix86_fp_comparison_strategy ( code ) == IX86_FPCMP_COMI ) ) { op0 = force_reg ( op_mode , op0 ) ; op1 = force_reg ( op_mode , op1 ) ; } else { if ( standard_80387_constant_p ( op0 ) == 0 || ( MEM_P ( op0 ) && ! ( standard_80387_constant_p ( op1 ) == 0 || MEM_P ( op1 ) ) ) ) { enum rtx_code new_code = ix86_fp_swap_condition ( code ) ; if ( new_code != UNKNOWN ) { std :: swap ( op0 , op1 ) ; code = new_code ; } } if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == 0 ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == 1 ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( REG_P ( op1 ) || can_create_pseudo_p ( ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; } * pop0 = op0 ; * pop1 = op1 ; return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to a fp comparison . The operands are updated in place ; the new comparsion code is returned .


<s> static int epilogue_renumber ( rtx * where , int test ) { const char * fmt ; int i ; enum rtx_code code ; if ( * where == 0 ) return 0 ; code = GET_CODE ( * where ) ; switch ( code ) { case REG : if ( REGNO ( * where ) >= 8 && REGNO ( * where ) < 24 ) return 1 ; if ( ! test && REGNO ( * where ) >= 24 && REGNO ( * where ) < 32 ) * where = gen_rtx_REG ( GET_MODE ( * where ) , OUTGOING_REGNO ( REGNO ( * where ) ) ) ; case SCRATCH : case CC0 : case PC : case CONST_INT : case CONST_WIDE_INT : case CONST_DOUBLE : return 0 ; case PLUS : if ( GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM && ( GET_CODE ( XEXP ( * where , 1 ) ) != CONST_INT || INTVAL ( XEXP ( * where , 1 ) ) < SPARC_STACK_BIAS ) ) return 1 ; break ; case MEM : if ( SPARC_STACK_BIAS && GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM ) return 1 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( * where , i ) - 1 ; j >= 0 ; j -- ) if ( epilogue_renumber ( & ( XVECEXP ( * where , i , j ) ) , test ) ) return 1 ; } else if ( fmt [ i ] == 'e' && epilogue_renumber ( & ( XEXP ( * where , i ) ) , test ) ) return 1 ; } return 0 ; } </s>

Return 1 , if any of the registers of the instruction are % l [ 0-7 ] or % o [ 0-7 ] . Such instructions can not be used in the delay slot of return insn on v9 . If TEST is 0 , also rename all % i [ 0-7 ] registers to their % o [ 0-7 ] counterparts .


<s> void rs6000_sibcall_sysv ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie ) { rtx func = func_desc ; rtx func_addr ; rtx call [ 3 ] ; rtx insn ; rtx abi_reg = NULL_RTX ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( ( INTVAL ( cookie ) & CALL_LONG ) != 0 && GET_CODE ( func_desc ) == SYMBOL_REF ) { func = rs6000_longcall_ref ( func_desc , tlsarg ) ; if ( TARGET_PLTSEQ ) abi_reg = func ; } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; if ( abi_reg ) { rtvec v = gen_rtvec ( 3 , func , func_desc , tlsarg ) ; rtx mark_func = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; emit_insn ( gen_rtx_SET ( func_addr , mark_func ) ) ; v = gen_rtvec ( 2 , func_addr , func_desc ) ; func_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; } else emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = gen_rtx_USE ( VOIDmode , cookie ) ; call [ 2 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 3 , call ) ) ; insn = emit_call_insn ( insn ) ; if ( abi_reg ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , abi_reg ) ; } </s>

Expand code to perform a sibling call under the SysV4 ABI .


<s> unsigned ARMBaseInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; switch ( MI . getOpcode ( ) ) { default : return MCID . getSize ( ) ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case ARM :: CONSTPOOL_ENTRY : case ARM :: JUMPTABLE_INSTS : case ARM :: JUMPTABLE_ADDRS : case ARM :: JUMPTABLE_TBB : case ARM :: JUMPTABLE_TBH : return MI . getOperand ( 2 ) . getImm ( ) ; case ARM :: SPACE : return MI . getOperand ( 1 ) . getImm ( ) ; case ARM :: INLINEASM : case ARM :: INLINEASM_BR : { unsigned Size = getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < ARMFunctionInfo > ( ) -> isThumbFunction ( ) ) Size = alignTo ( Size , 4 ) ; return Size ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> int pa_attr_length_indirect_call ( rtx_insn * insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) return 12 ; if ( TARGET_FAST_INDIRECT_CALLS || ( ! TARGET_LONG_CALLS && ! TARGET_PORTABLE_RUNTIME && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) ) return 8 ; if ( flag_pic ) return 20 ; if ( TARGET_PORTABLE_RUNTIME ) return 16 ; return 12 ; } </s>

Return the attribute length of the indirect call instruction INSN . The length must match the code generated by output_indirect call . The returned length includes the delay slot . Currently , the delay slot of an indirect call sequence is not exposed and it is used by the sequence itself .


<s> static unsigned HOST_WIDE_INT loongarch_asan_shadow_offset ( void ) { return TARGET_64BIT ? ( HOST_WIDE_INT_1 << 46 ) : 0 ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> bool Cpu0PassConfig :: addInstSelector ( ) { addPass ( createCpu0SEISelDAG ( getCpu0TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
bool
LEAUsesAG
=
ST
.
LEAusesAG
(
)
;
bool
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
bool
UseLEAForSP
=
ST
.
useLeaForSP
(
)
;
TSM
.
init
(
&
ST
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
auto
*
PSI
=
&
getAnalysis
<
ProfileSummaryInfoWrapperPass
>
(
)
.
getPSI
(
)
;
auto
*
MBFI
=
(
PSI
&&
PSI
->
hasProfileSummary
(
)
)
&
getAnalysis
<
LazyMachineBlockFrequencyInfoPass
>
(
)
.
getBFI
(
)
:
nullptr
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
bool
OptIncDecPerBB
=
OptIncDec
||
llvm
::
shouldOptimizeForSize
(
&
MBB
,
PSI
,
MBFI
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
{
if
(
!
isLEA
(
I
->
getOpcode
(
)
)
)
continue
;
if
(
optTwoAddrLEA
(
I
,
MBB
,
OptIncDecPerBB
,
UseLEAForSP
)
)
continue
;
if
(
IsSlowLEA
)
processInstructionForSlowLEA
(
I
,
MBB
)
;
else
if
(
IsSlow3OpsLEA
)
processInstrForSlow3OpLEA
(
I
,
MBB
,
OptIncDecPerBB
)
;
}
if
(
LEAUsesAG
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
processInstruction
(
I
,
MBB
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: WRYrr , dl , MVT :: Glue , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: Glue , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDY , MVT :: i32 , SDValue ( Mul , 1 ) ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


"Should be saving %r15 and something else"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


Wrapper around the output_probe_stack_range routines .


<s>
int
AArch64AsmParser
::
tryParseRegister
(
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
unsigned
RegNum
=
matchRegisterNameAlias
(
lowerCase
,
false
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
AArch64
::
FP
)
.
Case
(
"lr"
,
AArch64
::
LR
)
.
Case
(
"x31"
,
AArch64
::
XZR
)
.
Case
(
"w31"
,
AArch64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


<s> static machine_mode mips_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ATTRIBUTE_UNUSED ) { int unsignedp ; if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( mode , unsignedp , type ) ; * punsignedp = unsignedp ; return mode ; } </s>


<s> static bool rs6000_secondary_reload_direct_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { bool ret = false ; enum insn_code icode = CODE_FOR_nothing ; int cost = 0 ; int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_POWERPC64 && size == 16 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( TARGET_POWERPC64 && mode == SFmode ) { if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } else if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 2 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } } else if ( ! TARGET_POWERPC64 && size == 8 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && ! altivec_p ) { cost = 3 ; icode = reg_addr [ mode ] . reload_fpr_gpr ; } } if ( icode != CODE_FOR_nothing ) { ret = true ; if ( sri ) { sri -> icode = icode ; sri -> extra_cost = cost ; } } return ret ; } </s>

Power8 helper function for rs6000_secondary_reload , handle all of the special direct moves that involve allocating an extra register , return the insn code of the helper function if there is such a function or CODE_FOR_nothing if not .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { if ( PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { FrameIdx = MF . getInfo < PPCFunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s>
const
char
*
pa_output_block_clear
(
rtx
*
operands
,
int
size_is_constant
ATTRIBUTE_UNUSED
)
{
int
align
=
INTVAL
(
operands
[
3
]
)
;
unsigned
long
n_bytes
=
INTVAL
(
operands
[
2
]
)
;
if
(
align
>
(
TARGET_64BIT
8
:
4
)
)
align
=
(
TARGET_64BIT
8
:
4
)
;
switch
(
align
)
{
case
8
:
operands
[
2
]
=
GEN_INT
(
n_bytes
16
)
;
output_asm_insn
(
"ldi %2,%1"
,
operands
)
;
output_asm_insn
(
"std,ma %%r0,8(%0)"
,
operands
)
;
output_asm_insn
(
"addib,>= -16,%1,.-4"
,
operands
)
;
output_asm_insn
(
"std,ma %%r0,8(%0)"
,
operands
)
;
if
(
n_bytes
%
16
!=
0
)
{
operands
[
2
]
=
GEN_INT
(
n_bytes
%
8
)
;
if
(
n_bytes
%
16
>=
8
)
output_asm_insn
(
"std,ma %%r0,8(%0)"
,
operands
)
;
if
(
n_bytes
%
8
!=
0
)
output_asm_insn
(
"stdby,e %%r0,%2(%0)"
,
operands
)
;
}
return
""
;
case
4
:
operands
[
2
]
=
GEN_INT
(
n_bytes
8
)
;
output_asm_insn
(
"ldi %2,%1"
,
operands
)
;
output_asm_insn
(
"{stws|stw},ma %%r0,4(%0)"
,
operands
)
;
output_asm_insn
(
"addib,>= -8,%1,.-4"
,
operands
)
;
output_asm_insn
(
"{stws|stw},ma %%r0,4(%0)"
,
operands
)
;
if
(
n_bytes
%
8
!=
0
)
{
operands
[
2
]
=
GEN_INT
(
n_bytes
%
4
)
;
if
(
n_bytes
%
8
>=
4
)
output_asm_insn
(
"{stws|stw},ma %%r0,4(%0)"
,
operands
)
;
if
(
n_bytes
%
4
!=
0
)
output_asm_insn
(
"{stbys|stby},e %%r0,%2(%0)"
,
operands
)
;
}
return
""
;
case
2
:
operands
[
2
]
=
GEN_INT
(
n_bytes
4
)
;
output_asm_insn
(
"ldi %2,%1"
,
operands
)
;
output_asm_insn
(
"{sths|sth},ma %%r0,2(%0)"
,
operands
)
;
output_asm_insn
(
"addib,>= -4,%1,.-4"
,
operands
)
;
output_asm_insn
(
"{sths|sth},ma %%r0,2(%0)"
,
operands
)
;
if
(
n_bytes
%
4
!=
0
)
{
if
(
n_bytes
%
4
>=
2
)
output_asm_insn
(
"{sths|sth},ma %%r0,2(%0)"
,
operands
)
;
if
(
n_bytes
%
2
!=
0
)
output_asm_insn
(
"stb %%r0,0(%0)"
,
operands
)
;
}
return
""
;
case
1
:
operands
[
2
]
=
GEN_INT
(
n_bytes
2
)
;
output_asm_insn
(
"ldi %2,%1"
,
operands
)
;
output_asm_insn
(
"{stbs|stb},ma %%r0,1(%0)"
,
operands
)
;
output_asm_insn
(
"addib,>= -2,%1,.-4"
,
operands
)
;
output_asm_insn
(
"{stbs|stb},ma %%r0,1(%0)"
,
operands
)
;
if
(
n_bytes
%
2
!=
0
)
output_asm_insn
(
"stb %%r0,0(%0)"
,
operands
)
;
return
""
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Emit code to perform a block clear . OPERANDS [ 0 ] is the destination pointer as a REG , clobbered . OPERANDS [ 1 ] is a register for temporary storage . OPERANDS [ 2 ] is the size as a CONST_INT OPERANDS [ 3 ] is the alignment safe to use , as a CONST_INT .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void SystemZPassConfig :: addIRPasses ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createSystemZTDCPass ( ) ) ; addPass ( createLoopDataPrefetchPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static unsigned parse_field ( const char * field ) { const char * rest = strchr ( field , ':' ) ; char * after ; unsigned fint = strtol ( rest + 1 , & after , 16 ) ; if ( after == rest + 1 ) return - 1 ; return fint ; } </s>

Returns the hex integer that is after ' : ' for the FIELD . Returns -1 is returned if there was problem parsing the integer .


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperLarge : return "AArch64ISD::WrapperLarge" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; case AArch64ISD :: NEON_BSL : return "AArch64ISD::NEON_BSL" ; case AArch64ISD :: NEON_MOVIMM : return "AArch64ISD::NEON_MOVIMM" ; case AArch64ISD :: NEON_MVNIMM : return "AArch64ISD::NEON_MVNIMM" ; case AArch64ISD :: NEON_FMOVIMM : return "AArch64ISD::NEON_FMOVIMM" ; case AArch64ISD :: NEON_CMP : return "AArch64ISD::NEON_CMP" ; case AArch64ISD :: NEON_CMPZ : return "AArch64ISD::NEON_CMPZ" ; case AArch64ISD :: NEON_TST : return "AArch64ISD::NEON_TST" ; case AArch64ISD :: NEON_DUPIMM : return "AArch64ISD::NEON_DUPIMM" ; case AArch64ISD :: NEON_QSHLs : return "AArch64ISD::NEON_QSHLs" ; case AArch64ISD :: NEON_QSHLu : return "AArch64ISD::NEON_QSHLu" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const TargetRegisterClass * getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const override { if ( RC == & AArch64 :: tcGPR64RegClass ) return & AArch64 :: GPR64RegClass ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


The darwin64 ABI calls for us to recurse down through structs , looking for elements passed in registers . Unfortunately , we have to track int register count here also because of misalignments in powerpc alignment mode .


<s> static bool mips_hard_regno_mode_ok_p ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 2 == 0 ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 4 == 0 ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode && ! MSA_SUPPORTED_MODE_P ( mode ) ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && MSA_SUPPORTED_MODE_P ( mode ) ) return true ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == 0 || ( MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= 4 && ( regno & 1 ) != 0 ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & 1 ) != 0 ) ; if ( TARGET_LOONGSON_VECTORS && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * 2 ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * 2 && ( ( regno - DSP_ACC_REG_FIRST ) & 1 ) == 0 ) return true ; } } if ( ALL_COP_REG_P ( regno ) ) return mclass == MODE_INT && size <= UNITS_PER_WORD ; if ( regno == GOT_VERSION_REGNUM ) return mode == SImode ; return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in mips_hard_regno_mode_ok .


<s> void ix86_expand_truncdf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , 0 , OPTAB_DIRECT ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa2 , xa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) && flag_rounding_math ) tmp = ix86_expand_sse_fabs ( tmp , NULL ) ; ix86_sse_copysign_to_positive ( res , tmp , res , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing trunc from OPERAND1 storing into OPERAND0 .


"Slot for FP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static rtx mips_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { return mips_function_value_1 ( valtype , fn_decl_or_type , VOIDmode ) ; } </s>

Implement FUNCTION_VALUE and LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits ; unsigned bitsize ; unsigned mask ; HOST_WIDE_INT val ; HOST_WIDE_INT splat_val ; HOST_WIDE_INT msb_val ; if ( mode == V2DImode || mode == V2DFmode || mode == V1TImode ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; bitsize = GET_MODE_BITSIZE ( inner ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; splat_val = val ; msb_val = val >= 0 ? 0 : - 1 ; for ( i = 2 ; i <= copies ; i *= 2 ) { HOST_WIDE_INT small_val ; bitsize /= 2 ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= 0 || ( step == 1 && copies == 1 ) ) ) ; else if ( EASY_VECTOR_MSB ( splat_val , inner ) ) ; else return false ; for ( i = 1 ; i < nunits ; ++ i ) { HOST_WIDE_INT desired_val ; unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i ; if ( ( i & ( step - 1 ) ) == 0 ) desired_val = val ; else desired_val = msb_val ; if ( desired_val != const_vector_elt_as_int ( op , elt ) ) return false ; } return true ; } </s>

Return true if OP can be synthesized with a particular vspltisb , vspltish or vspltisw instruction . OP is a CONST_VECTOR . Which instruction is used depends on STEP and COPIES , one of which will be 1 . If COPIES > 1 , all items are set to the same value and contain COPIES replicas of the vsplt 's operand ; if STEP > 1 , one in STEP elements is set to the vsplt 's operand and the others are set to the value of the operand 's msb .


<s> int aarch64_simd_attr_length_rglist ( enum machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) / UNITS_PER_VREG ) * 4 ; } </s>

Compute and return the length of aarch64_simd_reglist < mode > , where < mode > is one of VSTRUCT modes : OI , CI , EI , or XI .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static bool aarch64_bti_j_insn_p ( rtx_insn * insn ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; rtx pat = PATTERN ( insn ) ; return GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == UNSPECV_BTI_J ; } </s>


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AArch64InstrInfo
&
TII
=
*
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
int
Opcode
=
MI
->
getOpcode
(
)
;
bool
IsDestroy
=
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
MI
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
MI
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
RoundUpToAlignment
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xfff
&&
Amount
<
0xfff
&&
"call frame too large"
)
;
emitSPUpdate
(
MBB
,
MI
,
dl
,
TII
,
AArch64
::
NoRegister
,
Amount
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xfff
&&
"call frame too large"
)
;
emitSPUpdate
(
MBB
,
MI
,
dl
,
TII
,
AArch64
::
NoRegister
,
CalleePopAmount
)
;
}
MBB
.
erase
(
MI
)
;
}
</s>


<s> const TargetRegisterClass * OpenRISCRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { assert ( 0 && "Unimplemented" ) ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool X86AsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind ( ) == FK_NONE ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> Register X86TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RAX : X86 :: EAX ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> CCAssignFn * MipsTargetLowering :: CCAssignFnForReturn ( ) const { return RetCC_Mips ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


runOnMachineFunction - Emit the function body .


<s> static bool chain_already_loaded ( rtx_insn * last ) { for ( ; last != NULL ; last = PREV_INSN ( last ) ) { if ( NONJUMP_INSN_P ( last ) ) { rtx patt = PATTERN ( last ) ; if ( GET_CODE ( patt ) == SET ) { rtx lhs = XEXP ( patt , 0 ) ; if ( REG_P ( lhs ) && REGNO ( lhs ) == STATIC_CHAIN_REGNUM ) return true ; } } } return false ; } </s>

Return TRUE iff the sequence ending in LAST sets the static chain .


<s> int sh_register_move_cost ( enum machine_mode mode , enum reg_class srcclass , enum reg_class dstclass ) { if ( dstclass == T_REGS || dstclass == PR_REGS ) return 10 ; if ( dstclass == MAC_REGS && srcclass == MAC_REGS ) return 4 ; if ( mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD && REGCLASS_HAS_FP_REG ( srcclass ) && REGCLASS_HAS_FP_REG ( dstclass ) ) return 4 ; if ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == T_REGS ) return ( ( TARGET_HARD_SH4 && ! optimize_size ) ? 10 : 7 ) ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == MAC_REGS ) || ( dstclass == MAC_REGS && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return 9 ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( REGCLASS_HAS_GENERAL_REG ( dstclass ) && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return ( ( TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12 ) * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ) ; if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 5 ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return 7 ; if ( ( srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( ( dstclass ) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 20 ; if ( TARGET_SHMEDIA && ( ( srcclass ) == TARGET_REGS || ( srcclass ) == SIBCALL_REGS ) ) { if ( sh_gettrcost >= 0 ) return sh_gettrcost ; else if ( ! TARGET_PT_FIXED ) return 100 ; } if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 4 ; if ( TARGET_SHMEDIA || ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 2 * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; return 2 * ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4U ) ; } </s>

If SECONDARY * _RELOAD_CLASS says something about the src/dst pair , regclass uses this information . Hence , the general register < - > floating point register information here is not used for SFmode .


<s> const Cpu0TargetLowering * Cpu0TargetLowering :: create ( const Cpu0TargetMachine & TM , const Cpu0Subtarget & STI ) { return llvm :: createCpu0SETargetLowering ( TM , STI ) ; } </s>


<s> void convert_int_to_float128 ( rtx * operands , enum rtx_code code ) { rtx dest = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx tmp = operands [ 2 ] ; rtx cvt ; rtvec cvt_vec ; rtx cvt_unspec ; rtvec move_vec ; rtx move_unspec ; rtx unsigned_flag ; if ( GET_CODE ( tmp ) == SCRATCH ) tmp = gen_reg_rtx ( V2DImode ) ; if ( MEM_P ( src ) ) src = rs6000_address_for_fpconvert ( src ) ; if ( GET_MODE ( src ) == SImode ) { unsigned_flag = ( code == UNSIGNED_FLOAT ) ? const1_rtx : const0_rtx ; move_vec = gen_rtvec ( 2 , src , unsigned_flag ) ; } else move_vec = gen_rtvec ( 1 , src ) ; move_unspec = gen_rtx_UNSPEC ( V2DImode , move_vec , UNSPEC_IEEE128_MOVE ) ; emit_insn ( gen_rtx_SET ( tmp , move_unspec ) ) ; cvt_vec = gen_rtvec ( 1 , tmp ) ; cvt_unspec = gen_rtx_UNSPEC ( DImode , cvt_vec , UNSPEC_IEEE128_CONVERT ) ; cvt = gen_rtx_fmt_e ( code , GET_MODE ( dest ) , cvt_unspec ) ; emit_insn ( gen_rtx_SET ( dest , cvt ) ) ; } </s>

Split a conversion from an integer type to __float128 into separate insns . OPERANDS points to the destination , source , and V2DI temporary register . CODE is either FLOAT or UNSIGNED_FLOAT .


<s> std :: pair < uint16_t , uint16_t > ARMBaseInstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { if ( Subtarget . hasNEON ( ) ) { if ( MI -> getOpcode ( ) == ARM :: VMOVD && ! isPredicated ( * MI ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( * MI ) && ( MI -> getOpcode ( ) == ARM :: VMOVRS || MI -> getOpcode ( ) == ARM :: VMOVSR || MI -> getOpcode ( ) == ARM :: VMOVS ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; } unsigned Domain = MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Domain & ARMII :: DomainNEON ) return std :: make_pair ( ExeNEON , 0 ) ; if ( ( Domain & ARMII :: DomainNEONA8 ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , 0 ) ; if ( Domain & ARMII :: DomainVFP ) return std :: make_pair ( ExeVFP , 0 ) ; return std :: make_pair ( ExeGeneric , 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static bool aarch64_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_SIMD && AARCH64_VALID_SIMD_QREG_MODE ( mode ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P .


<s>
bool
CAHPAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
CAHPOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

CAHP
CAHP
CAHPOperand::createToken
"unexpected token"


<s> rtx loongarch_subword ( rtx op , bool high_p ) { unsigned int byte ; machine_mode mode ; byte = high_p ? UNITS_PER_WORD : 0 ; mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( FP_REG_RTX_P ( op ) ) return gen_rtx_REG ( word_mode , REGNO ( op ) + high_p ) ; if ( MEM_P ( op ) ) return loongarch_rewrite_small_data ( adjust_address ( op , word_mode , byte ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ; } </s>

Return one word of double-word value OP , taking into account the fixed endianness of certain registers . HIGH_P is true to select the high part , false to select the low part .


<s> SDValue LC3bTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool SystemZInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . isTerminator ( ) ) return false ; if ( TID . isBranch ( ) && ! TID . isBarrier ( ) ) return true ; if ( ! TID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : ExpandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: BuildPairF64 : ExpandBuildPairF64 ( MBB , MI ) ; break ; case Mips :: ExtractElementF64 : ExpandExtractElementF64 ( MBB , MI ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : ExpandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 1 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 2 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> static bool aarch64_is_reduction ( stmt_vec_info stmt_info ) { return ( STMT_VINFO_REDUC_DEF ( stmt_info ) || VECTORIZABLE_CYCLE_DEF ( STMT_VINFO_DEF_TYPE ( stmt_info ) ) ) ; } </s>

Return true if STMT_INFO represents part of a reduction .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( ! Subtarget . hasVLX ( ) ) break ; LLVM_FALLTHROUGH ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( ! Subtarget . hasAVX512 ( ) ) break ; LLVM_FALLTHROUGH ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s>
bool
X86ATTAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
Function
*
F
=
MF
.
getFunction
(
)
;
this
->
MF
=
&
MF
;
unsigned
CC
=
F
->
getCallingConv
(
)
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
if
(
CC
==
CallingConv
::
X86_StdCall
||
CC
==
CallingConv
::
X86_FastCall
)
FunctionInfoMap
[
F
]
=
*
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
if
(
F
->
hasDLLExportLinkage
(
)
)
DLLExportedFns
.
insert
(
Mang
->
makeNameProper
(
F
->
getName
(
)
,
""
)
)
;
emitFunctionHeader
(
MF
)
;
if
(
TAI
->
doesSupportDebugInformation
(
)
||
TAI
->
doesSupportExceptionHandling
(
)
)
DW
->
BeginFunction
(
&
MF
)
;
bool
hasAnyRealCode
=
false
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
VerboseAsm
&&
(
I
->
pred_empty
(
)
||
I
->
isOnlyReachableByFallthrough
(
)
)
)
{
}
else
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
IE
=
I
->
end
(
)
;
II
!=
IE
;
++
II
)
{
if
(
!
II
->
isLabel
(
)
)
hasAnyRealCode
=
true
;
printMachineInstruction
(
II
)
;
}
}
if
(
Subtarget
->
isTargetDarwin
(
)
&&
!
hasAnyRealCode
)
{
O
<<
"\tnop\n"
;
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size\t"
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
'\n'
;
if
(
TAI
->
doesSupportDebugInformation
(
)
)
DW
->
EndFunction
(
&
MF
)
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
O
.
flush
(
)
;
return
false
;
}
</s>


<s> static bool iq2000_pass_by_reference ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int size ; if ( cum && targetm . calls . must_pass_in_stack ( mode , type ) ) { CUMULATIVE_ARGS temp ; temp = * cum ; if ( FUNCTION_ARG ( temp , mode , type , named ) != 0 ) return 1 ; } if ( type == NULL_TREE || mode == DImode || mode == DFmode ) return 0 ; size = int_size_in_bytes ( type ) ; return size == - 1 || size > UNITS_PER_WORD ; } </s>

Return true when an argument must be passed by reference .


<s>
void
X86AvoidSFBPass
::
buildCopy
(
MachineInstr
*
LoadInst
,
unsigned
NLoadOpcode
,
int64_t
LoadDisp
,
MachineInstr
*
StoreInst
,
unsigned
NStoreOpcode
,
int64_t
StoreDisp
,
unsigned
Size
,
int64_t
LMMOffset
,
int64_t
SMMOffset
)
{
MachineOperand
&
LoadBase
=
getBaseOperand
(
LoadInst
)
;
MachineOperand
&
StoreBase
=
getBaseOperand
(
StoreInst
)
;
MachineBasicBlock
*
MBB
=
LoadInst
->
getParent
(
)
;
MachineMemOperand
*
LMMO
=
*
LoadInst
->
memoperands_begin
(
)
;
MachineMemOperand
*
SMMO
=
*
StoreInst
->
memoperands_begin
(
)
;
unsigned
Reg1
=
MRI
->
createVirtualRegister
(
TII
->
getRegClass
(
TII
->
get
(
NLoadOpcode
)
,
0
,
TRI
,
*
(
MBB
->
getParent
(
)
)
)
)
;
MachineInstr
*
NewLoad
=
BuildMI
(
*
MBB
,
LoadInst
,
LoadInst
->
getDebugLoc
(
)
,
TII
->
get
(
NLoadOpcode
)
,
Reg1
)
.
add
(
LoadBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
LoadDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
LMMO
,
LMMOffset
,
Size
)
)
;
if
(
LoadBase
.
isReg
(
)
)
getBaseOperand
(
NewLoad
)
.
setIsKill
(
false
)
;
LLVM_DEBUG
(
NewLoad
->
dump
(
)
)
;
MachineInstr
*
StInst
=
StoreInst
;
auto
PrevInstrIt
=
skipDebugInstructionsBackward
(
std
::
prev
(
MachineBasicBlock
::
instr_iterator
(
StoreInst
)
)
,
MBB
->
instr_begin
(
)
)
;
if
(
PrevInstrIt
.
getNodePtr
(
)
==
LoadInst
)
StInst
=
LoadInst
;
MachineInstr
*
NewStore
=
BuildMI
(
*
MBB
,
StInst
,
StInst
->
getDebugLoc
(
)
,
TII
->
get
(
NStoreOpcode
)
)
.
add
(
StoreBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
StoreDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addReg
(
Reg1
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
SMMO
,
SMMOffset
,
Size
)
)
;
if
(
StoreBase
.
isReg
(
)
)
getBaseOperand
(
NewStore
)
.
setIsKill
(
false
)
;
MachineOperand
&
StoreSrcVReg
=
StoreInst
->
getOperand
(
X86
::
AddrNumOperands
)
;
assert
(
StoreSrcVReg
.
isReg
(
)
&&
"Expected virtual register"
)
;
NewStore
->
getOperand
(
X86
::
AddrNumOperands
)
.
setIsKill
(
StoreSrcVReg
.
isKill
(
)
)
;
LLVM_DEBUG
(
NewStore
->
dump
(
)
)
;
}
</s>


<s> void PPCScoreboardHazardRecognizer :: Reset ( ) { ScoreboardHazardRecognizer :: Reset ( ) ; } </s>


<s> void sh_emit_scc_to_t ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx t_reg = get_t_reg_rtx ( ) ; enum rtx_code oldcode = code ; machine_mode mode ; switch ( code ) { case NE : gcc_unreachable ( ) ; case LT : code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) std :: swap ( op0 , op1 ) ; mode = GET_MODE ( op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( op1 ) ; op0 = force_reg ( mode , op0 ) ; if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; sh_emit_set_t_insn ( gen_rtx_SET ( VOIDmode , t_reg , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) , mode ) ; } </s>

Prepare the operands for an scc instruction ; make sure that the compare has been done and the result is in T_REG .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> static rtx stv_expand_builtin ( insn_code icode , rtx * op , machine_mode tmode , machine_mode smode ) { op [ 2 ] = copy_to_mode_reg ( Pmode , op [ 2 ] ) ; if ( icode == CODE_FOR_altivec_stvx_v2df || icode == CODE_FOR_altivec_stvx_v2di || icode == CODE_FOR_altivec_stvx_v4sf || icode == CODE_FOR_altivec_stvx_v4si || icode == CODE_FOR_altivec_stvx_v8hi || icode == CODE_FOR_altivec_stvx_v16qi ) { rtx rawaddr ; if ( op [ 1 ] == const0_rtx ) rawaddr = op [ 2 ] ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; rawaddr = gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ; } rtx addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - 16 ) ) ; addr = gen_rtx_MEM ( tmode , addr ) ; op [ 0 ] = copy_to_mode_reg ( tmode , op [ 0 ] ) ; emit_insn ( gen_rtx_SET ( addr , op [ 0 ] ) ) ; } else if ( icode == CODE_FOR_vsx_stxvrbx || icode == CODE_FOR_vsx_stxvrhx || icode == CODE_FOR_vsx_stxvrwx || icode == CODE_FOR_vsx_stxvrdx ) { rtx truncrtx = gen_rtx_TRUNCATE ( tmode , op [ 0 ] ) ; op [ 0 ] = copy_to_mode_reg ( E_TImode , truncrtx ) ; rtx addr ; if ( op [ 1 ] == const0_rtx ) addr = gen_rtx_MEM ( Pmode , op [ 2 ] ) ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ 0 ] ) ; if ( pat ) emit_insn ( pat ) ; } else { if ( ! insn_data [ icode ] . operand [ 1 ] . predicate ( op [ 0 ] , smode ) ) op [ 0 ] = copy_to_mode_reg ( smode , op [ 0 ] ) ; rtx addr ; if ( op [ 1 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 2 ] ) ; else { op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ 2 ] , op [ 1 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ 0 ] ) ; if ( pat ) emit_insn ( pat ) ; } return NULL_RTX ; } </s>

Expand an AltiVec vector store builtin , and return the expanded rtx .


<s> bool AArch64FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; const AArch64Subtarget & Subtarget = MF -> getSubtarget < AArch64Subtarget > ( ) ; const AArch64RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; return ! RegInfo -> needsStackRealignment ( * MF ) ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s>
static
void
ix86_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
char
*
target_string
=
ix86_target_string
(
ptr
->
x_ix86_isa_flags
,
ptr
->
x_target_flags
,
,
,
ptr
->
x_ix86_fpmath
,
false
)
;
gcc_assert
(
ptr
->
arch
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*sarch = %d (%s)\n"
,
indent
,
""
,
ptr
->
arch
,
processor_target_table
[
ptr
->
arch
]
.
name
)
;
gcc_assert
(
ptr
->
tune
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*stune = %d (%s)\n"
,
indent
,
""
,
ptr
->
tune
,
processor_target_table
[
ptr
->
tune
]
.
name
)
;
fprintf
(
file
,
"%*sbranch_cost = %d\n"
,
indent
,
""
,
ptr
->
branch_cost
)
;
if
(
target_string
)
{
fprintf
(
file
,
"%*s%s\n"
,
indent
,
""
,
target_string
)
;
free
(
target_string
)
;
}
}
</s>


"Don't know how to assign a value to an address yet"

An overload which takes an ArgInfo if additional information about the arg is needed .


"X86TargetMachine --->> In the constructor class !! \n"


<s> void rs6000_split_logical ( rtx operands [ 3 ] , enum rtx_code code , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; machine_mode sub_mode ; rtx op0 , op1 , op2 ; int sub_size , regno0 , regno1 , nregs , i ; if ( mode == DImode && ! TARGET_POWERPC64 ) { rs6000_split_logical_di ( operands , code , complement_final_p , complement_op1_p , complement_op2_p ) ; return ; } op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; op2 = ( code == NOT ) ? NULL_RTX : operands [ 2 ] ; sub_mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; sub_size = GET_MODE_SIZE ( sub_mode ) ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; gcc_assert ( reload_completed ) ; gcc_assert ( IN_RANGE ( regno0 , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; gcc_assert ( IN_RANGE ( regno1 , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; nregs = rs6000_hard_regno_nregs [ ( int ) mode ] [ regno0 ] ; gcc_assert ( nregs > 1 ) ; if ( op2 && REG_P ( op2 ) ) gcc_assert ( IN_RANGE ( REGNO ( op2 ) , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; for ( i = 0 ; i < nregs ; i ++ ) { int offset = i * sub_size ; rtx sub_op0 = simplify_subreg ( sub_mode , op0 , mode , offset ) ; rtx sub_op1 = simplify_subreg ( sub_mode , op1 , mode , offset ) ; rtx sub_op2 = ( ( code == NOT ) ? NULL_RTX : simplify_subreg ( sub_mode , op2 , mode , offset ) ) ; rs6000_split_logical_inner ( sub_op0 , sub_op1 , sub_op2 , code , sub_mode , complement_final_p , complement_op1_p , complement_op2_p ) ; } return ; } </s>

Split the insns that make up boolean operations operating on multiple GPR registers . The boolean MD patterns ensure that the inputs either are exactly the same as the output registers , or there is no overlap . OPERANDS is an array containing the destination and two input operands . CODE is the base operation ( AND , IOR , XOR , NOT ) . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> void aarch64_split_combinev16qi ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = HARD_REGNO_NREGS ( src1 , halfmode ) ; rtx destlo , desthi ; gcc_assert ( halfmode == V16QImode ) ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) && reg_overlap_mentioned_p ( operands [ 1 ] , desthi ) ) { emit_insn ( gen_xorv16qi3 ( operands [ 1 ] , operands [ 1 ] , operands [ 2 ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ 2 ] , operands [ 1 ] , operands [ 2 ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ 1 ] , operands [ 1 ] , operands [ 2 ] ) ) ; } else if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && IS_CMSE_ENTRY ( func_type ) ) return 0 ; if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s>
void
X86InstPrinterCommon
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
Op
.
getExpr
(
)
->
print
(
O
,
&
MAI
)
;
}
}
}
</s>


<s> Register PPCIncomingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; const bool IsImmutable = ! Flags . isByVal ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , IsImmutable ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; llvm :: LLT FramePtr = LLT :: pointer ( 0 , MIRBuilder . getMF ( ) . getDataLayout ( ) . getPointerSizeInBits ( ) ) ; MachineInstrBuilder AddrReg = MIRBuilder . buildFrameIndex ( FramePtr , FI ) ; StackUsed = std :: max ( StackUsed , Size + Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> Optional < RegImmPair > MipsInstrInfo :: isAddImmediate ( const MachineInstr & MI , Register Reg ) const { const MachineOperand & Op0 = MI . getOperand ( 0 ) ; if ( ! Op0 . isReg ( ) || Reg != Op0 . getReg ( ) ) return None ; switch ( MI . getOpcode ( ) ) { case Mips :: ADDiu : case Mips :: DADDiu : { const MachineOperand & Dop = MI . getOperand ( 0 ) ; const MachineOperand & Sop1 = MI . getOperand ( 1 ) ; const MachineOperand & Sop2 = MI . getOperand ( 2 ) ; if ( Dop . isReg ( ) && Sop1 . isReg ( ) && Sop2 . isImm ( ) ) return RegImmPair { Sop1 . getReg ( ) , Sop2 . getImm ( ) } ; } } return None ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> unsigned ARMTargetLowering :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return RegInfo -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = RegInfo -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( Subtarget -> isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool LC3bFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void ARMTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> bool mips_const_vector_bitimm_set_p ( rtx op , machine_mode mode ) { if ( GET_CODE ( op ) == CONST_VECTOR && op != CONST0_RTX ( mode ) ) { unsigned HOST_WIDE_INT val = UINTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) ; int vlog2 = exact_log2 ( val & GET_MODE_MASK ( GET_MODE_INNER ( mode ) ) ) ; if ( vlog2 != - 1 ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) ; gcc_assert ( vlog2 >= 0 && vlog2 <= GET_MODE_UNIT_BITSIZE ( mode ) - 1 ) ; return mips_const_vector_same_val_p ( op , mode ) ; } } return false ; } </s>

Return true if OP is a constant vector with the number of units in MODE , and each unit has the same bit set .


<s> bool PPCFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnablePEVectorSpills || MFI . hasCalls ( ) || ! Subtarget . hasP9Vector ( ) ) return false ; BitVector BVAllocatable = TRI -> getAllocatableSet ( MF ) ; BitVector BVCalleeSaved ( TRI -> getNumRegs ( ) ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) BVCalleeSaved . set ( CSRegs [ i ] ) ; for ( unsigned Reg : BVAllocatable . set_bits ( ) ) { if ( BVCalleeSaved [ Reg ] || ( ! PPC :: F8RCRegClass . contains ( Reg ) && ! PPC :: VFRCRegClass . contains ( Reg ) ) || ( MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) ) BVAllocatable . reset ( Reg ) ; } bool AllSpilledToReg = true ; for ( auto & CS : CSI ) { if ( BVAllocatable . none ( ) ) return false ; unsigned Reg = CS . getReg ( ) ; if ( ! PPC :: G8RCRegClass . contains ( Reg ) && ! PPC :: GPRCRegClass . contains ( Reg ) ) { AllSpilledToReg = false ; continue ; } unsigned VolatileVFReg = BVAllocatable . find_first ( ) ; if ( VolatileVFReg < BVAllocatable . size ( ) ) { CS . setDstReg ( VolatileVFReg ) ; BVAllocatable . reset ( VolatileVFReg ) ; } else { AllSpilledToReg = false ; } } return AllSpilledToReg ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static tree aarch64_simd_builtin_type ( enum machine_mode mode , bool unsigned_p , bool poly_p ) { if ( poly_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_poly ) ; else if ( unsigned_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ; else return aarch64_lookup_simd_builtin_type ( mode , qualifier_none ) ; } </s>

Return a type for an operand with specified mode and qualifiers .


<s> static machine_mode ix86_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == m2 ) return m1 ; if ( GET_MODE_CLASS ( m1 ) != MODE_CC || GET_MODE_CLASS ( m2 ) != MODE_CC ) return VOIDmode ; if ( ( m1 == CCGCmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCGCmode ) ) return CCGCmode ; if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCPmode : case CCSmode : case CCZmode : switch ( m2 ) { default : return VOIDmode ; case CCmode : case CCGCmode : case CCGOCmode : case CCNOmode : case CCAmode : case CCCmode : case CCOmode : case CCPmode : case CCSmode : case CCZmode : return CCmode ; } case CCFPmode : case CCFPUmode : return VOIDmode ; } } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
)
return
TargetInstrInfoImpl
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
TOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
RegState
::
Define
|
getDeadRegState
(
Reg0IsDead
)
)
.
addReg
(
Reg2
,
getKillRegState
(
Reg2IsKill
)
)
.
addReg
(
Reg1
,
getKillRegState
(
Reg1IsKill
)
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s> SDValue PPCTargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRSQRTES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRSQRTE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = ! Subtarget . needsTwoConstNR ( ) ; return DAG . getNode ( PPCISD :: FRSQRTE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; BuildMI ( MBB , I , DL , get ( ARM :: tMOVr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

ARM ARM::GPRRegClass ARM ARM::tMOVr ARMCC::AL


<s> static void arm_test_cpu_arch_data ( void ) { const arch_option * arch ; const cpu_option * cpu ; auto_sbitmap target_isa ( isa_num_bits ) ; auto_sbitmap isa1 ( isa_num_bits ) ; auto_sbitmap isa2 ( isa_num_bits ) ; for ( arch = all_architectures ; arch -> common . name != NULL ; ++ arch ) { const cpu_arch_extension * ext1 , * ext2 ; if ( arch -> common . extensions == NULL ) continue ; arm_initialize_isa ( target_isa , arch -> common . isa_bits ) ; for ( ext1 = arch -> common . extensions ; ext1 -> name != NULL ; ++ ext1 ) { if ( ext1 -> alias ) continue ; arm_initialize_isa ( isa1 , ext1 -> isa_bits ) ; for ( ext2 = ext1 + 1 ; ext2 -> name != NULL ; ++ ext2 ) { if ( ext2 -> alias || ext1 -> remove != ext2 -> remove ) continue ; arm_initialize_isa ( isa2 , ext2 -> isa_bits ) ; ASSERT_TRUE ( ! bitmap_subset_p ( isa2 , isa1 ) ) ; ASSERT_TRUE ( ! bitmap_intersect_p ( isa2 , target_isa ) ) ; } } } for ( cpu = all_cores ; cpu -> common . name != NULL ; ++ cpu ) { const cpu_arch_extension * ext1 , * ext2 ; if ( cpu -> common . extensions == NULL ) continue ; arm_initialize_isa ( target_isa , arch -> common . isa_bits ) ; for ( ext1 = cpu -> common . extensions ; ext1 -> name != NULL ; ++ ext1 ) { if ( ext1 -> alias ) continue ; arm_initialize_isa ( isa1 , ext1 -> isa_bits ) ; for ( ext2 = ext1 + 1 ; ext2 -> name != NULL ; ++ ext2 ) { if ( ext2 -> alias || ext1 -> remove != ext2 -> remove ) continue ; arm_initialize_isa ( isa2 , ext2 -> isa_bits ) ; ASSERT_TRUE ( ! bitmap_subset_p ( isa2 , isa1 ) ) ; ASSERT_TRUE ( ! bitmap_intersect_p ( isa2 , target_isa ) ) ; } } } } </s>

Scan the static data tables generated by parsecpu.awk looking for potential issues with the data . We primarily check for inconsistencies in the option extensions at present ( extensions that duplicate others but are n't marked as aliases ) . Furthermore , for correct canonicalization later options must never be a subset of an earlier option . Any extension should also only specify other feature bits and never an architecture bit . The architecture is inferred from the declaration of the extension .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned getElementSize ( ) { return CurType . ElementSize ; } </s>

Return the size of an element read or written by Inst .