<s> static void rs6000_init_dwarf_reg_sizes_extra ( tree address ) { if ( TARGET_SPE ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 4 , mode ) ; for ( i = FIRST_SPE_HIGH_REGNO ; i < LAST_SPE_HIGH_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } if ( TARGET_MACHO && ! TARGET_ALTIVEC ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( 16 , mode ) ; for ( i = FIRST_ALTIVEC_REGNO ; i < LAST_ALTIVEC_REGNO + 1 ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } } </s>

Fill in sizes of registers used by unwinder .


<s> int shl_sext_length ( rtx insn ) { rtx set_src , left_rtx , size_rtx ; int cost ; set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; left_rtx = XEXP ( XEXP ( set_src , 0 ) , 1 ) ; size_rtx = XEXP ( set_src , 1 ) ; shl_sext_kind ( left_rtx , size_rtx , & cost ) ; return cost ; } </s>

Function to be used in the length attribute of the instructions implementing this pattern .


<s> rtx_insn * mips_expand_call ( enum mips_call_type type , rtx result , rtx addr , rtx args_size , rtx aux , bool lazy_p ) { rtx orig_addr , pattern ; rtx_insn * insn ; int fp_code ; fp_code = aux == 0 ? 0 : ( int ) GET_MODE ( aux ) ; insn = mips16_build_call_stub ( result , & addr , args_size , fp_code ) ; if ( insn ) { gcc_assert ( ! lazy_p && type == MIPS_CALL_NORMAL ) ; return insn ; } orig_addr = addr ; if ( ! call_insn_operand ( addr , VOIDmode ) ) { if ( type == MIPS_CALL_EPILOGUE ) addr = MIPS_EPILOGUE_TEMP ( Pmode ) ; else addr = gen_reg_rtx ( Pmode ) ; lazy_p |= mips_load_call_address ( type , addr , orig_addr ) ; } if ( result == 0 ) { rtx ( * fn ) ( rtx , rtx ) ; if ( type == MIPS_CALL_SIBCALL ) fn = gen_sibcall_internal ; else fn = gen_call_internal ; pattern = fn ( addr , args_size ) ; } else if ( GET_CODE ( result ) == PARALLEL && XVECLEN ( result , 0 ) == 2 ) { rtx ( * fn ) ( rtx , rtx , rtx , rtx ) ; rtx reg1 , reg2 ; if ( type == MIPS_CALL_SIBCALL ) fn = gen_sibcall_value_multiple_internal ; else fn = gen_call_value_multiple_internal ; reg1 = XEXP ( XVECEXP ( result , 0 , 0 ) , 0 ) ; reg2 = XEXP ( XVECEXP ( result , 0 , 1 ) , 0 ) ; pattern = fn ( reg1 , addr , args_size , reg2 ) ; } else { rtx ( * fn ) ( rtx , rtx , rtx ) ; if ( type == MIPS_CALL_SIBCALL ) fn = gen_sibcall_value_internal ; else fn = gen_call_value_internal ; if ( GET_CODE ( result ) == PARALLEL && XVECLEN ( result , 0 ) == 1 ) result = XEXP ( XVECEXP ( result , 0 , 0 ) , 0 ) ; pattern = fn ( result , addr , args_size ) ; } return mips_emit_call_insn ( pattern , orig_addr , addr , lazy_p ) ; } </s>

Expand a call or call_value instruction . RESULT is where the result will go ( null for calls ) , ADDR is the address of the function , ARGS_SIZE is the size of the arguments and AUX is the value passed to us by mips_function_arg . SIBCALL_P is true if we are expanding a sibling call , false if we 're expanding a normal call .


<s>
const
char
*
output_jump_label_table
(
)
{
int
i
;
if
(
pool_size
)
{
fprintf
(
asm_out_file
,
"\t.align 2\n"
)
;
for
(
i
=
0
;
i
<
pool_size
;
i
++
)
{
pool_node
*
p
=
&
pool_vector
[
i
]
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
p
->
label
)
)
;
output_asm_insn
(
".long	%O0"
,
&
p
->
value
)
;
}
pool_size
=
0
;
}
return
""
;
}
</s>

Dump out any constants accumulated in the final pass . These will only be labels .


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: TargetCostInfo & TCI ) const { if ( TCI . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: TCRETURNdi ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) . addImm ( 0 ) ) ; return It ; } if ( TCI . CallConstructionID == MachineOutlinerNoLRSave || TCI . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR , RegState :: Define ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return CallPt ; } </s>

Insert a call to an outlined function into the program .


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( SYMBOL_REF_P ( XVECEXP ( x , 0 , 0 ) ) && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base_oac && tocrel_offset_oac != const0_rtx ) { if ( INTVAL ( tocrel_offset_oac ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset_oac ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s>
void
SICFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SICFunctionInfo
*
SICFI
=
MF
.
getInfo
<
SICFunctionInfo
>
(
)
;
const
SICInstrInfo
&
TII
=
*
static_cast
<
const
SICInstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
const
SICRegisterInfo
&
RegInfo
=
*
static_cast
<
const
SICRegisterInfo
*
>
(
STI
.
getRegisterInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
SICABIInfo
ABI
=
STI
.
getABI
(
)
;
unsigned
SP
=
SIC
::
X
;
const
TargetRegisterClass
*
RC
=
&
SIC
::
GPROutRegClass
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
->
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
adjustStackPtr
(
SP
,
StackSize
,
MBB
,
MBBI
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

SIC
SIC
"Shrink-wrapping not yet supported"
SIC
SIC
SIC
SIC
SIC
SIC
SIC
SIC
SIC::X
SIC::GPROutRegClass
0


"\t ! references to jmptbl section entries\n"

"\t ! references to vector section entries\n"

Function to emit isr reset handler content . Including all jmptbl/vector references , jmptbl section , vector section , nmi handler section , and warm handler section .


<s> static int rs6000_hard_regno_mode_ok_uncached ( int regno , machine_mode mode ) { int last_regno = regno + rs6000_hard_regno_nregs [ mode ] [ regno ] - 1 ; if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & 1 ) == 0 ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || ( TARGET_VSX_TIMODE && mode == TImode ) || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) != 16 && ! reg_addr [ mode ] . scalar_in_vmx_p ) return 0 ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( FLOAT128_VECTOR_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % 2 ) == 0 ) && FP_REGNO_P ( last_regno ) ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return 1 ; if ( TARGET_VSX_SMALL_INTEGER ) { if ( mode == SImode ) return 1 ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return 1 ; } } if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return 1 ; return 0 ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return 1 ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( isLoad && usePartialVectorLoads ( N , Subtarget ) ) { return false ; } if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , None ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , Align ( 4 ) ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s>
const
MCPhysReg
*
PPCRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
PPCSubtarget
&
Subtarget
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
{
if
(
!
TM
.
isPPC64
(
)
&&
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"AnyReg unimplemented on 32-bit AIX."
)
;
if
(
Subtarget
.
hasVSX
(
)
)
return
CSR_64_AllRegs_VSX_SaveList
;
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_64_AllRegs_Altivec_SaveList
;
return
CSR_64_AllRegs_SaveList
;
}
bool
SaveR2
=
MF
->
getRegInfo
(
)
.
isAllocatable
(
PPC
::
X2
)
&&
!
Subtarget
.
isUsingPCRelativeCalls
(
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Cold
)
{
if
(
Subtarget
.
isAIXABI
(
)
)
report_fatal_error
(
"Cold calling unimplemented on AIX."
)
;
if
(
TM
.
isPPC64
(
)
)
{
if
(
Subtarget
.
hasAltivec
(
)
)
return
SaveR2
CSR_SVR64_ColdCC_R2_Altivec_SaveList
:
CSR_SVR64_ColdCC_Altivec_SaveList
;
return
SaveR2
CSR_SVR64_ColdCC_R2_SaveList
:
CSR_SVR64_ColdCC_SaveList
;
}
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_SVR32_ColdCC_Altivec_SaveList
;
else
if
(
Subtarget
.
hasSPE
(
)
)
return
CSR_SVR32_ColdCC_SPE_SaveList
;
return
CSR_SVR32_ColdCC_SaveList
;
}
if
(
TM
.
isPPC64
(
)
)
{
if
(
Subtarget
.
hasAltivec
(
)
)
return
SaveR2
CSR_PPC64_R2_Altivec_SaveList
:
CSR_PPC64_Altivec_SaveList
;
return
SaveR2
CSR_PPC64_R2_SaveList
:
CSR_PPC64_SaveList
;
}
if
(
Subtarget
.
isAIXABI
(
)
)
return
CSR_AIX32_SaveList
;
if
(
Subtarget
.
hasAltivec
(
)
)
return
CSR_SVR432_Altivec_SaveList
;
else
if
(
Subtarget
.
hasSPE
(
)
)
return
CSR_SVR432_SPE_SaveList
;
return
CSR_SVR432_SaveList
;
}
</s>

PowerPC
PPC
PPC
PPC
PPC
"AnyReg unimplemented on 32-bit AIX."
PPC::X2
"Cold calling unimplemented on AIX."
PPC
PPC
PPC
PPC
PPC
PPC


aarch64
"%*sselected tune = %s\n"
""
"%*sselected arch = %s%s\n"
""


<s> const MipsRegisterInfo & MipsInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( ( Size == 64 ) && ! Subtarget -> isMClass ( ) ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void dimode_scalar_chain :: convert_registers ( ) { bitmap_iterator bi ; unsigned id ; EXECUTE_IF_SET_IN_BITMAP ( defs , 0 , id , bi ) convert_reg ( id ) ; EXECUTE_IF_AND_COMPL_IN_BITMAP ( defs_conv , defs , 0 , id , bi ) make_vector_copies ( id ) ; } </s>

Generate copies from defs used by the chain but not defined therein . Also populates defs_map which is used later by convert_insn .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
RC
->
getSize
(
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: COND_S ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> void ix86_split_copysign_var ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , scratch , op0 , op1 , mask , nmask , x ; dest = operands [ 0 ] ; scratch = operands [ 1 ] ; op0 = operands [ 2 ] ; op1 = operands [ 3 ] ; nmask = operands [ 4 ] ; mask = operands [ 5 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; if ( rtx_equal_p ( op0 , op1 ) ) { emit_move_insn ( dest , op0 ) ; return ; } if ( REG_P ( mask ) && REGNO ( dest ) == REGNO ( mask ) ) { gcc_assert ( REGNO ( op1 ) == REGNO ( scratch ) ) ; x = gen_rtx_AND ( vmode , scratch , mask ) ; emit_insn ( gen_rtx_SET ( scratch , x ) ) ; dest = mask ; op0 = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_NOT ( vmode , dest ) ; x = gen_rtx_AND ( vmode , x , op0 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } else { if ( REGNO ( op1 ) == REGNO ( scratch ) ) { x = gen_rtx_AND ( vmode , scratch , mask ) ; } else { gcc_assert ( REGNO ( mask ) == REGNO ( scratch ) ) ; op1 = lowpart_subreg ( vmode , op1 , mode ) ; x = gen_rtx_AND ( vmode , scratch , op1 ) ; } emit_insn ( gen_rtx_SET ( scratch , x ) ) ; if ( REGNO ( op0 ) == REGNO ( dest ) ) { dest = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_AND ( vmode , dest , nmask ) ; } else { gcc_assert ( REGNO ( nmask ) == REGNO ( dest ) ) ; dest = nmask ; op0 = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_AND ( vmode , dest , op0 ) ; } emit_insn ( gen_rtx_SET ( dest , x ) ) ; } x = gen_rtx_IOR ( vmode , dest , scratch ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is variable , so we have to do two masks .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


<s> const MCSection * X86ELFMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , ELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> static reg_class_t pa_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { int regno ; enum reg_class rclass = ( enum reg_class ) rclass_i ; if ( rclass == R1_REGS ) return NO_REGS ; if ( REG_P ( x ) ) { regno = REGNO ( x ) ; if ( rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER ) return NO_REGS ; } else regno = - 1 ; if ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , 0 ) ) == MEM ) return NO_REGS ; if ( flag_pic && FP_REG_CLASS_P ( rclass ) && ( GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST_DOUBLE ) ) { switch ( mode ) { case E_SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case E_DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; case E_SFmode : sri -> icode = CODE_FOR_reload_insf_r1 ; break ; case E_DFmode : sri -> icode = CODE_FOR_reload_indf_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } if ( pa_symbolic_expression_p ( x ) ) { if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; if ( flag_pic || ! read_only_operand ( x , VOIDmode ) ) { switch ( mode ) { case E_SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case E_DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } } if ( regno >= FIRST_PSEUDO_REGISTER || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( ( regno >= FIRST_PSEUDO_REGISTER || regno == - 1 ) && FP_REG_CLASS_P ( rclass ) ) { if ( MEM_P ( x ) ) { x = XEXP ( x , 0 ) ; if ( IS_INDEX_ADDR_P ( x ) ) return NO_REGS ; } sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( rclass == SHIFT_REGS ) { if ( regno >= FIRST_PSEUDO_REGISTER || regno < 0 ) { sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( FP_REG_CLASS_P ( REGNO_REG_CLASS ( regno ) ) ) return GENERAL_REGS ; } if ( regno >= 0 && regno < FIRST_PSEUDO_REGISTER && REGNO_REG_CLASS ( regno ) == SHIFT_REGS && FP_REG_CLASS_P ( rclass ) ) return GENERAL_REGS ; return NO_REGS ; } </s>

Inform reload about cases where moving X with a mode MODE to or from a register in RCLASS requires an extra scratch or immediate register . Return the class needed for the immediate register .


<s> static int flow_dependent_p ( rtx insn , rtx dep_insn ) { rtx tmp = PATTERN ( insn ) ; note_stores ( PATTERN ( dep_insn ) , flow_dependent_p_1 , & tmp ) ; return tmp == NULL_RTX ; } </s>

Check if INSN is flow-dependent on DEP_INSN . Can also be used to check if DEP_INSN is anti-flow dependent on INSN .


<s> bool isShift ( ) const { if ( ! isShiftOrExtend ( ) ) return false ; if ( ShiftExtend . ShiftType != SHKind ) return false ; return is64Bit ? ShiftExtend . Amount <= 63 : ShiftExtend . Amount <= 31 ; } </s>

Determine if the Opcode is one of the shift instructions .


<s>
static
void
csky_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
const
char
*
thiz
=
"a0"
;
const
char
*
reg0
=
"t0"
;
const
char
*
reg1
=
"t1"
;
int
maxoff
=
4096
;
final_start_function
(
emit_barrier
(
)
,
file
,
1
)
;
rtx
fnaddr
=
XEXP
(
DECL_RTL
(
function
)
,
0
)
;
if
(
CSKY_TARGET_ARCH
(
CK801
)
)
{
reg0
=
"l0"
;
reg1
=
"l1"
;
maxoff
=
256
;
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
fprintf
(
file
,
"\tpush\tl0, l1\n"
)
;
else
if
(
delta
>
maxoff
||
delta
<
maxoff
)
fprintf
(
file
,
"\tpush\tl0\n"
)
;
}
if
(
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
)
thiz
=
"a1"
;
if
(
delta
!=
0
)
{
if
(
delta
>
maxoff
||
delta
<
maxoff
)
{
fprintf
(
file
,
"\tlrw\t%s, %ld\n"
,
reg0
,
(
long
)
delta
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
thiz
,
thiz
,
reg0
)
;
}
else
fprintf
(
file
,
"\t%s\t%s, %s, %ld\n"
,
(
delta
>
0
"addi"
:
"subi"
)
,
thiz
,
thiz
,
(
long
)
(
delta
>
0
delta
:
delta
)
)
;
}
if
(
vcall_offset
!=
0
)
{
fprintf
(
file
,
"\tld.w\t%s, (%s, 0)\n"
,
reg0
,
thiz
)
;
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
{
fprintf
(
file
,
"\tlrw\t%s, %ld\n"
,
reg1
,
(
long
)
vcall_offset
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
reg0
,
reg0
,
reg1
)
;
}
else
fprintf
(
file
,
"\t%s\t%s, %s, %ld\n"
,
(
vcall_offset
>
0
"addi"
:
"subi"
)
,
reg0
,
reg0
,
(
long
)
(
vcall_offset
>
0
vcall_offset
:
vcall_offset
)
)
;
fprintf
(
file
,
"\tld.w\t%s, (%s, 0)\n"
,
reg0
,
reg0
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
thiz
,
thiz
,
reg0
)
;
}
if
(
CSKY_TARGET_ARCH
(
CK801
)
)
{
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
{
fprintf
(
file
,
"\tld.w\tl0, (sp, 0)\n"
)
;
fprintf
(
file
,
"\tld.w\tl1, (sp, 4)\n"
)
;
fprintf
(
file
,
"\taddi\t sp, sp, 8\n"
)
;
}
else
if
(
delta
>
maxoff
||
delta
<
maxoff
)
{
fprintf
(
file
,
"\tld.w\tl0, (sp, 0)\n"
)
;
fprintf
(
file
,
"\taddi\tsp, sp, 4\n"
)
;
}
}
fprintf
(
file
,
"\tjbr\t"
)
;
output_addr_const
(
file
,
fnaddr
)
;
fprintf
(
file
,
"\n"
)
;
final_end_function
(
)
;
}
</s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> void DLXInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , const DebugLoc & DL , unsigned DestinationRegister , unsigned SourceRegister , bool KillSource ) const { } </s>


<s> static ARMCC :: CondCodes getPredicate ( const MachineInstr * MI , const Thumb2InstrInfo * TII ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: tBcc || Opc == ARM :: t2Bcc ) return ARMCC :: AL ; return TII -> getPredicate ( MI ) ; } </s>

Returns the comparison predicate underlying the intrinsic .

ARM ARMCC::CondCodes ARM::tBcc ARM::t2Bcc ARMCC::AL


<s>
static
void
rs6000_darwin_file_start
(
void
)
{
static
const
struct
{
const
char
*
arg
;
const
char
*
name
;
HOST_WIDE_INT
if_set
;
}
mapping
[
]
=
{
{
"ppc64"
,
"ppc64"
,
MASK_64BIT
}
,
{
"970"
,
"ppc970"
,
MASK_PPC_GPOPT
|
MASK_MFCRF
|
MASK_POWERPC64
}
,
{
"power4"
,
"ppc970"
,
0
}
,
{
"G5"
,
"ppc970"
,
0
}
,
{
"7450"
,
"ppc7450"
,
0
}
,
{
"7400"
,
"ppc7400"
,
MASK_ALTIVEC
}
,
{
"G4"
,
"ppc7400"
,
0
}
,
{
"750"
,
"ppc750"
,
0
}
,
{
"740"
,
"ppc750"
,
0
}
,
{
"G3"
,
"ppc750"
,
0
}
,
{
"604e"
,
"ppc604e"
,
0
}
,
{
"604"
,
"ppc604"
,
0
}
,
{
"603e"
,
"ppc603"
,
0
}
,
{
"603"
,
"ppc603"
,
0
}
,
{
"601"
,
"ppc601"
,
0
}
,
{
,
"ppc"
,
0
}
}
;
const
char
*
cpu_id
=
""
;
size_t
i
;
rs6000_file_start
(
)
;
darwin_file_start
(
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
cpu_id
=
rs6000_default_cpu
;
if
(
OPTION_SET_P
(
rs6000_cpu_index
)
)
cpu_id
=
processor_target_table
[
rs6000_cpu_index
]
.
name
;
i
=
0
;
while
(
mapping
[
i
]
.
arg
!=
&&
strcmp
(
mapping
[
i
]
.
arg
,
cpu_id
)
!=
0
&&
(
mapping
[
i
]
.
if_set
&
rs6000_isa_flags
)
==
0
)
i
++
;
fprintf
(
asm_out_file
,
"\t.machine %s\n"
,
mapping
[
i
]
.
name
)
;
}
</s>

Output a .machine directive for the Darwin assembler , and call the generic start_file routine .


<s> void loongarch_expand_atomic_qihi ( union loongarch_gen_fn_ptrs generator , rtx result , rtx mem , rtx oldval , rtx newval , rtx model ) { rtx orig_addr , memsi_addr , memsi , shift , shiftsi , unshifted_mask ; rtx unshifted_mask_reg , mask , inverted_mask , si_op ; rtx res = NULL ; machine_mode mode ; mode = GET_MODE ( mem ) ; orig_addr = force_reg ( Pmode , XEXP ( mem , 0 ) ) ; memsi_addr = loongarch_force_binary ( Pmode , AND , orig_addr , force_reg ( Pmode , GEN_INT ( - 4 ) ) ) ; memsi = gen_rtx_MEM ( SImode , memsi_addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = loongarch_force_binary ( Pmode , AND , orig_addr , GEN_INT ( 3 ) ) ; loongarch_emit_binary ( ASHIFT , shift , shift , GEN_INT ( 3 ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = loongarch_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = loongarch_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = loongarch_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_7 ( res , memsi , mask , inverted_mask , oldval , newval , model ) ; else if ( result ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , model ) ; else si_op = generator . fn_5 ( memsi , mask , inverted_mask , oldval , model ) ; emit_insn ( si_op ) ; if ( result ) { loongarch_emit_binary ( AND , res , res , mask ) ; loongarch_emit_binary ( LSHIFTRT , res , res , shiftsi ) ; loongarch_emit_move ( result , gen_lowpart ( GET_MODE ( result ) , res ) ) ; } } </s>

Expand a QI or HI mode atomic memory operation . GENERATOR contains a pointer to the gen_ * function that generates the SI mode underlying atomic operation using masks that we calculate . RESULT is the return register for the operation . Its value is NULL if unused . MEM is the location of the atomic access . OLDVAL is the first operand for the operation . NEWVAL is the optional second operand for the operation . Its value is NULL if unused .


<s>
AsmToken
LexToken
(
)
{
if
(
!
Lexer
)
{
SetError
(
SMLoc
(
)
,
"No MCAsmLexer installed"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
}
switch
(
AsmInfo
.
getAssemblerDialect
(
)
)
{
default
:
SetError
(
SMLoc
(
)
,
"Unhandled dialect"
)
;
return
AsmToken
(
AsmToken
::
Error
,
""
,
0
)
;
case
0
:
return
LexTokenATT
(
)
;
case
1
:
return
LexTokenIntel
(
)
;
}
}
</s>

LexToken - Read the next token and return its code .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getTargetTriple
(
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
getOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s>
void
LanaiFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
LanaiInstrInfo
&
LII
=
*
static_cast
<
const
LanaiInstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
;
determineFrameLayout
(
MF
)
;
unsigned
StackSize
=
MFI
.
getStackSize
(
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
SW_RI
)
)
.
addReg
(
Lanai
::
FP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
4
)
.
addImm
(
LPAC
::
makePreOp
(
LPAC
::
ADD
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
ADD_I_LO
)
,
Lanai
::
FP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
if
(
StackSize
!=
0
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
SUB_I_LO
)
,
Lanai
::
SP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
StackSize
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
if
(
MFI
.
hasVarSizedObjects
(
)
)
replaceAdjDynAllocPseudo
(
MF
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static inline bool offset_12bit_unsigned_scaled_p ( machine_mode mode , HOST_WIDE_INT offset ) { return ( offset >= 0 && offset < 4096 * GET_MODE_SIZE ( mode ) && offset % GET_MODE_SIZE ( mode ) == 0 ) ; } </s>

Return true if OFFSET is an unsigned 12-bit value multiplied by the size of MODE .


<s>
static
void
ix86_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
char
*
target_string
=
ix86_target_string
(
ptr
->
x_ix86_isa_flags
,
ptr
->
x_ix86_isa_flags2
,
ptr
->
x_target_flags
,
ptr
->
x_ix86_target_flags
,
,
,
ptr
->
x_ix86_fpmath
,
false
,
true
)
;
gcc_assert
(
ptr
->
arch
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*sarch = %d (%s)\n"
,
indent
,
""
,
ptr
->
arch
,
processor_names
[
ptr
->
arch
]
)
;
gcc_assert
(
ptr
->
tune
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*stune = %d (%s)\n"
,
indent
,
""
,
ptr
->
tune
,
processor_names
[
ptr
->
tune
]
)
;
fprintf
(
file
,
"%*sbranch_cost = %d\n"
,
indent
,
""
,
ptr
->
branch_cost
)
;
if
(
target_string
)
{
fprintf
(
file
,
"%*s%s\n"
,
indent
,
""
,
target_string
)
;
free
(
target_string
)
;
}
}
</s>


<s> bool X86InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . isTerminator ( ) ) return false ; if ( TID . isBranch ( ) && ! TID . isBarrier ( ) ) return true ; if ( ! TID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool nonpic_symbol_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == PC ) return true ; if ( GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , 1 ) == UNSPEC_PIC || XINT ( x , 1 ) == UNSPEC_GOT || XINT ( x , 1 ) == UNSPEC_GOTOFF || XINT ( x , 1 ) == UNSPEC_GOTPLT || XINT ( x , 1 ) == UNSPEC_GOTTPOFF || XINT ( x , 1 ) == UNSPEC_DTPOFF || XINT ( x , 1 ) == UNSPEC_TPOFF || XINT ( x , 1 ) == UNSPEC_PLT || XINT ( x , 1 ) == UNSPEC_PCREL || XINT ( x , 1 ) == UNSPEC_SYMOFF || XINT ( x , 1 ) == UNSPEC_PCREL_SYMOFF || XINT ( x , 1 ) == UNSPEC_GOTFUNCDESC || XINT ( x , 1 ) == UNSPEC_GOTOFFFUNCDESC ) ) return false ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( nonpic_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && nonpic_symbol_mentioned_p ( XEXP ( x , i ) ) ) return true ; } return false ; } </s>

Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol is n't protected by a PIC unspec .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
MipsSubtarget
::
O32
:
return
"abi32"
;
case
MipsSubtarget
::
N32
:
return
"abiN32"
;
case
MipsSubtarget
::
N64
:
return
"abi64"
;
case
MipsSubtarget
::
EABI
:
return
"eabi32"
;
default
:
break
;
}
llvm_unreachable
(
"Unknown Mips ABI"
)
;
return
;
}
</s>


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . readMem = false ; Info . writeMem = false ; Info . vol = false ; Info . offset = 0 ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = 1 ; Info . readMem = true ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static inline bool equal ( tree_map * a , tree_map * b ) { return a -> base . from == b -> base . from ; } </s>


<s>
void
X86AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
Size
=
getFixupKindSize
(
Kind
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
if
(
(
Target
.
isAbsolute
(
)
||
IsResolved
)
&&
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
Flags
&
MCFixupKindInfo
::
FKF_IsPCRel
)
{
if
(
Size
>
0
&&
!
isIntN
(
Size
*
8
,
SignedValue
)
)
Asm
.
getContext
(
)
.
reportError
(
Fixup
.
getLoc
(
)
,
"value of "
+
Twine
(
SignedValue
)
+
" is too large for field of "
+
Twine
(
Size
)
+
(
(
Size
==
1
)
" byte."
:
" bytes."
)
)
;
}
else
{
assert
(
(
Size
==
0
||
isIntN
(
Size
*
8
+
1
,
SignedValue
)
)
&&
"Value does not fit in the Fixup field"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SystemZ Instruction Shortening"
;
}
</s>

getPassName - Return a nice clean name for a pass .

SystemZ
"SystemZ Instruction Shortening"


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s>
char
*
rx_gen_move_template
(
rtx
*
operands
,
bool
is_movu
)
{
static
char
out_template
[
64
]
;
const
char
*
extension
=
TARGET_AS100_SYNTAX
".L"
:
""
;
const
char
*
src_template
;
const
char
*
dst_template
;
rtx
dest
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
switch
(
CONST_INT_P
(
src
)
GET_MODE
(
dest
)
:
GET_MODE
(
src
)
)
{
case
E_QImode
:
if
(
!
REG_P
(
dest
)
||
!
CONST_INT_P
(
src
)
)
extension
=
".B"
;
break
;
case
E_HImode
:
if
(
!
REG_P
(
dest
)
||
!
CONST_INT_P
(
src
)
)
extension
=
".W"
;
break
;
case
E_DFmode
:
case
E_DImode
:
case
E_SFmode
:
case
E_SImode
:
extension
=
".L"
;
break
;
case
E_VOIDmode
:
break
;
default
:
debug_rtx
(
src
)
;
gcc_unreachable
(
)
;
}
if
(
MEM_P
(
src
)
&&
rx_pid_data_operand
(
XEXP
(
src
,
0
)
)
==
PID_UNENCODED
)
{
gcc_assert
(
GET_MODE
(
src
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
src
)
!=
DFmode
)
;
src_template
=
"(%A1 - __pid_base)[%P1]"
;
}
else
if
(
MEM_P
(
src
)
&&
rx_small_data_operand
(
XEXP
(
src
,
0
)
)
)
{
gcc_assert
(
GET_MODE
(
src
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
src
)
!=
DFmode
)
;
src_template
=
"%%gp(%A1)[%G1]"
;
}
else
src_template
=
"%1"
;
if
(
MEM_P
(
dest
)
&&
rx_small_data_operand
(
XEXP
(
dest
,
0
)
)
)
{
gcc_assert
(
GET_MODE
(
dest
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
dest
)
!=
DFmode
)
;
dst_template
=
"%%gp(%A0)[%G0]"
;
}
else
dst_template
=
"%0"
;
if
(
GET_MODE
(
dest
)
==
DImode
||
GET_MODE
(
dest
)
==
DFmode
)
{
gcc_assert
(
!
is_movu
)
;
if
(
REG_P
(
src
)
&&
REG_P
(
dest
)
&&
(
REGNO
(
dest
)
==
REGNO
(
src
)
+
1
)
)
sprintf
(
out_template
,
"mov.L\t%%H1, %%H0 ! mov.L\t%%1, %%0"
)
;
else
sprintf
(
out_template
,
"mov.L\t%%1, %%0 ! mov.L\t%%H1, %%H0"
)
;
}
else
sprintf
(
out_template
,
"%s%s\t%s, %s"
,
is_movu
"movu"
:
"mov"
,
extension
,
src_template
,
dst_template
)
;
return
out_template
;
}
</s>

Returns an assembler template for a move instruction .


<s> static void csky_output_constpool_label ( FILE * stream , rtx x ) { char buf [ 15 ] ; gcc_assert ( GET_CODE ( x ) == LABEL_REF ) ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == UNSPEC_VOLATILE && XINT ( x , 1 ) == VUNSPEC_POOL_LABEL ) { ASM_GENERATE_INTERNAL_LABEL ( buf , CSKY_CONSTPOOL_LABEL_PREFIX , INTVAL ( XVECEXP ( x , 0 , 0 ) ) ) ; assemble_name ( stream , buf ) ; } } </s>

Output the constpool label according to the rtx expression X .


Similarly for the start of the epilogue .


"cpu %s is not based on arch %s, ignoring the arch"

Configure a build target TARGET from the user-specified options OPTS and OPTS_SET .


<s> void ia64_vms_output_aligned_decl_common ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { tree attr = DECL_ATTRIBUTES ( decl ) ; if ( attr ) attr = lookup_attribute ( "common_object" , attr ) ; if ( attr ) { tree id = TREE_VALUE ( TREE_VALUE ( attr ) ) ; const char * name ; if ( TREE_CODE ( id ) == IDENTIFIER_NODE ) name = IDENTIFIER_POINTER ( id ) ; else if ( TREE_CODE ( id ) == STRING_CST ) name = TREE_STRING_POINTER ( id ) ; else abort ( ) ; fprintf ( file , "\t.vms_common\t\"%s\"," , name ) ; } else fprintf ( file , "%s" , COMMON_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u" , size , align / BITS_PER_UNIT ) ; fputc ( '\n' , file ) ; } </s>

Part of the low level implementation of DEC Ada pragma Common_Object .


<s> int ARMFrameInfo :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return ResolveFrameIndexReference ( MF , FI , FrameReg , 0 ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> const char * XNCMTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case XNCMISD :: RET_FLAG : return "XNCMISD::RET_FLAG" ; case XNCMISD :: RETI_FLAG : return "XNCMISD::RETI_FLAG" ; case XNCMISD :: RRA : return "XNCMISD::RRA" ; case XNCMISD :: RLA : return "XNCMISD::RLA" ; case XNCMISD :: RRC : return "XNCMISD::RRC" ; case XNCMISD :: CALL : return "XNCMISD::CALL" ; case XNCMISD :: Wrapper : return "XNCMISD::Wrapper" ; case XNCMISD :: BR_CC : return "XNCMISD::BR_CC" ; case XNCMISD :: CMP : return "XNCMISD::CMP" ; case XNCMISD :: SELECT_CC : return "XNCMISD::SELECT_CC" ; case XNCMISD :: SHL : return "XNCMISD::SHL" ; case XNCMISD :: SRA : return "XNCMISD::SRA" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

XNCM XNCM XNCMISD::RET_FLAG "XNCMISD::RET_FLAG" XNCMISD::RETI_FLAG "XNCMISD::RETI_FLAG" XNCMISD::RRA "XNCMISD::RRA" XNCMISD::RLA "XNCMISD::RLA" XNCMISD::RRC "XNCMISD::RRC" XNCMISD::CALL "XNCMISD::CALL" XNCMISD::Wrapper "XNCMISD::Wrapper" XNCMISD::BR_CC "XNCMISD::BR_CC" XNCMISD::CMP "XNCMISD::CMP" XNCMISD::SELECT_CC "XNCMISD::SELECT_CC" XNCMISD::SHL "XNCMISD::SHL" XNCMISD::SRA "XNCMISD::SRA"


<s> static tree ix86_d_handle_target_float_abi ( void ) { const char * abi ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) abi = "soft" ; else abi = "hard" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> bool X86TTIImpl :: canMacroFuseCmp ( ) { return ST -> hasMacroFusion ( ) || ST -> hasBranchFusion ( ) ; } </s>

Return true if the target can fuse a compare and branch .


<s> bool Cpu0TargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const Cpu0Subtarget & Subtarget = TM . getSubtarget < Cpu0Subtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static enum aarch64_parse_opt_result aarch64_parse_cpu ( const char * to_parse , const struct processor * * res , unsigned long * isa_flags ) { char * ext ; const struct processor * cpu ; char * str = ( char * ) alloca ( strlen ( to_parse ) + 1 ) ; size_t len ; strcpy ( str , to_parse ) ; ext = strchr ( str , '+' ) ; if ( ext != NULL ) len = ext - str ; else len = strlen ( str ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , str , len ) == 0 ) { unsigned long isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the result tuning in RES and the architecture flags in ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> bool csky_split_xor ( rtx * operands ) { HOST_WIDE_INT mask = INTVAL ( operands [ 2 ] ) ; if ( mask == 0 ) { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; return true ; } if ( mask == - 1 ) { if ( CSKY_ISA_FEATURE ( E2 ) ) emit_insn ( gen_cskyv2_one_cmplsi2 ( operands [ 0 ] , operands [ 1 ] ) ) ; else { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; emit_insn ( gen_ck801_one_cmplsi2 ( operands [ 0 ] , operands [ 0 ] ) ) ; } return true ; } if ( CSKY_ISA_FEATURE ( E2 ) && csky_arith_O_operand ( operands [ 2 ] , SImode ) ) return false ; if ( reload_completed ) { emit_move_insn ( operands [ 0 ] , operands [ 2 ] ) ; operands [ 2 ] = operands [ 1 ] ; operands [ 1 ] = operands [ 0 ] ; } else operands [ 2 ] = copy_to_mode_reg ( SImode , operands [ 2 ] ) ; return false ; } </s>

Split operands for an XOR expression when OPERANDS [ 2 ] is a constant . Note operands [ 0 ] is marked earlyclobber in this case and can be overwritten . Return true if `` DONE '' , false otherwise .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_GHC_SaveList ; else return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


<s> void aarch64_expand_sve_vec_cmp_int ( rtx target , rtx_code code , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; if ( ! aarch64_sve_cmp_operand_p ( code , op1 ) ) op1 = force_reg ( data_mode , op1 ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; rtx unspec = aarch64_gen_unspec_cond ( code , pred_mode , ptrue , op0 , op1 ) ; emit_insn ( gen_set_clobber_cc ( target , unspec ) ) ; } </s>

Expand an SVE integer comparison : TARGET = CODE ( OP0 , OP1 ) .


<s> static rtx loongarch_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct loongarch_arg_info info ; if ( arg . end_marker_p ( ) ) return NULL ; return loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; } </s>


<s> bool loongarch_unsigned_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = 0 ) { return ( x & ( ( 1 << shift ) - 1 ) ) == 0 && x < ( ( unsigned ) 1 << ( shift + bits ) ) ; } </s>

Return true if X fits within an unsigned field of BITS bits that is shifted left SHIFT bits before being used .


<s> static int rws_access_regno ( int regno , struct reg_flags flags , int pred ) { int need_barrier = 0 ; gcc_assert ( regno < NUM_REGS ) ; if ( ! PR_REGNO_P ( regno ) ) flags . is_and = flags . is_or = 0 ; if ( flags . is_write ) { int write_count ; rws_insn_set ( regno ) ; write_count = rws_sum [ regno ] . write_count ; switch ( write_count ) { case 0 : if ( ! in_safe_group_barrier ) rws_update ( regno , flags , pred ) ; break ; case 1 : if ( flags . is_and && rws_sum [ regno ] . written_by_and ) ; else if ( flags . is_or && rws_sum [ regno ] . written_by_or ) ; else need_barrier = 1 ; if ( ! in_safe_group_barrier ) rws_update ( regno , flags , pred ) ; break ; case 2 : if ( flags . is_and && rws_sum [ regno ] . written_by_and ) ; else if ( flags . is_or && rws_sum [ regno ] . written_by_or ) ; else need_barrier = 1 ; if ( ! in_safe_group_barrier ) { rws_sum [ regno ] . written_by_and = flags . is_and ; rws_sum [ regno ] . written_by_or = flags . is_or ; } break ; default : gcc_unreachable ( ) ; } } else { if ( flags . is_branch ) { if ( REGNO_REG_CLASS ( regno ) == BR_REGS || regno == AR_PFS_REGNUM ) return 0 ; if ( REGNO_REG_CLASS ( regno ) == PR_REGS && ! rws_sum [ regno ] . written_by_fp ) return 0 ; } if ( flags . is_and && rws_sum [ regno ] . written_by_and ) return 0 ; if ( flags . is_or && rws_sum [ regno ] . written_by_or ) return 0 ; switch ( rws_sum [ regno ] . write_count ) { case 0 : break ; case 1 : need_barrier = 1 ; break ; case 2 : need_barrier = 1 ; break ; default : gcc_unreachable ( ) ; } } return need_barrier ; } </s>

Handle an access to register REGNO of type FLAGS using predicate register PRED . Update rws_insn and rws_sum arrays . Return 1 if this access creates a dependency with an earlier instruction in the same group .


<s> void AArch64ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> unsigned IA64RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? IA64 :: r5 : IA64 :: r12 ; } </s>


<s>
bool
ARMTargetLowering
::
getPostIndexedAddressParts
(
SDNode
*
N
,
SDNode
*
Op
,
SDValue
&
Base
,
SDValue
&
Offset
,
ISD
::
MemIndexedMode
&
AM
,
SelectionDAG
&
DAG
)
const
{
EVT
VT
;
SDValue
Ptr
;
unsigned
Align
;
bool
isSEXTLoad
=
false
,
isNonExt
;
if
(
LoadSDNode
*
LD
=
dyn_cast
<
LoadSDNode
>
(
N
)
)
{
VT
=
LD
->
getMemoryVT
(
)
;
Ptr
=
LD
->
getBasePtr
(
)
;
Align
=
LD
->
getAlignment
(
)
;
isSEXTLoad
=
LD
->
getExtensionType
(
)
==
ISD
::
SEXTLOAD
;
isNonExt
=
LD
->
getExtensionType
(
)
==
ISD
::
NON_EXTLOAD
;
}
else
if
(
StoreSDNode
*
ST
=
dyn_cast
<
StoreSDNode
>
(
N
)
)
{
VT
=
ST
->
getMemoryVT
(
)
;
Ptr
=
ST
->
getBasePtr
(
)
;
Align
=
ST
->
getAlignment
(
)
;
isNonExt
=
!
ST
->
isTruncatingStore
(
)
;
}
else
return
false
;
if
(
Subtarget
->
isThumb1Only
(
)
)
{
assert
(
Op
->
getValueType
(
0
)
==
MVT
::
i32
&&
"Non-i32 post-inc op?!"
)
;
if
(
Op
->
getOpcode
(
)
!=
ISD
::
ADD
||
!
isNonExt
)
return
false
;
auto
*
RHS
=
dyn_cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
if
(
!
RHS
||
RHS
->
getZExtValue
(
)
!=
4
)
return
false
;
Offset
=
Op
->
getOperand
(
1
)
;
Base
=
Op
->
getOperand
(
0
)
;
AM
=
ISD
::
POST_INC
;
return
true
;
}
bool
isInc
;
bool
isLegal
=
false
;
if
(
VT
.
isVector
(
)
)
isLegal
=
Subtarget
->
hasMVEIntegerOps
(
)
&&
getMVEIndexedAddressParts
(
Op
,
VT
,
Align
,
isSEXTLoad
,
Subtarget
->
isLittle
(
)
,
Base
,
Offset
,
isInc
,
DAG
)
;
else
{
if
(
Subtarget
->
isThumb2
(
)
)
isLegal
=
getT2IndexedAddressParts
(
Op
,
VT
,
isSEXTLoad
,
Base
,
Offset
,
isInc
,
DAG
)
;
else
isLegal
=
getARMIndexedAddressParts
(
Op
,
VT
,
isSEXTLoad
,
Base
,
Offset
,
isInc
,
DAG
)
;
}
if
(
!
isLegal
)
return
false
;
if
(
Ptr
!=
Base
)
{
if
(
Ptr
==
Offset
&&
Op
->
getOpcode
(
)
==
ISD
::
ADD
&&
!
Subtarget
->
isThumb2
(
)
)
std
::
swap
(
Base
,
Offset
)
;
if
(
Ptr
!=
Base
)
return
false
;
}
AM
=
isInc
ISD
::
POST_INC
:
ISD
::
POST_DEC
;
return
true
;
}
</s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


<s> static void * rs6000_alloc_sched_context ( void ) { return xmalloc ( sizeof ( rs6000_sched_context_def ) ) ; } </s>

Allocate store for new scheduling context .


<s> bool X86PreTileConfig :: runOnMachineFunction ( MachineFunction & mf ) { MF = & mf ; MRI = & mf . getRegInfo ( ) ; ST = & mf . getSubtarget < X86Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; MachineInstr * MI = getTileConfigPoint ( ) ; if ( ! MI ) return false ; unsigned Size = ST -> getTileConfigSize ( ) ; Align Alignment = ST -> getTileConfigAlignment ( ) ; int SS = mf . getFrameInfo ( ) . CreateStackObject ( Size , Alignment , false ) ; Register CFG = buildConfigMI ( MI , SS , TII , MRI , ST ) ; addTileCFGUse ( mf , CFG ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void expand_strncmp_align_check ( rtx strncmp_label , rtx src , HOST_WIDE_INT bytes ) { rtx lab_ref = gen_rtx_LABEL_REF ( VOIDmode , strncmp_label ) ; rtx src_check = copy_addr_to_reg ( XEXP ( src , 0 ) ) ; if ( GET_MODE ( src_check ) == SImode ) emit_insn ( gen_andsi3 ( src_check , src_check , GEN_INT ( 0xfff ) ) ) ; else emit_insn ( gen_anddi3 ( src_check , src_check , GEN_INT ( 0xfff ) ) ) ; rtx cond = gen_reg_rtx ( CCmode ) ; emit_move_insn ( cond , gen_rtx_COMPARE ( CCmode , src_check , GEN_INT ( 4096 - bytes ) ) ) ; rtx cmp_rtx = gen_rtx_GE ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , lab_ref , pc_rtx ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = strncmp_label ; LABEL_NUSES ( strncmp_label ) += 1 ; } </s>

Generate page crossing check and branch code to set up for strncmp when we do n't have DI alignment . STRNCMP_LABEL is the label to branch if there is a page crossing . SRC_ADDR is the string address to be examined . BYTES is the max number of bytes to compare .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MipsABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = ABI . GetPtrAdduOp ( ) ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> isPredicable ( ) ) return false ; ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> unsigned int UPTInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return TargetInstrInfo :: isLoadFromStackSlot ( MI , FrameIndex ) ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void adjust_subreg_index ( rtx op ) { enum rtx_code code = GET_CODE ( op ) ; if ( code == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( op ) ) < GET_MODE_SIZE ( GET_MODE ( XEXP ( op , 0 ) ) ) ) ) { unsigned int index = SUBREG_BYTE ( op ) ; if ( index < 8 ) index += 8 ; else index -= 8 ; SUBREG_BYTE ( op ) = index ; } const char * fmt = GET_RTX_FORMAT ( code ) ; int i , j ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) adjust_subreg_index ( XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( op , i ) ; ++ j ) adjust_subreg_index ( XVECEXP ( op , i , j ) ) ; } </s>

Find all subregs of a vector expression that perform a narrowing , and adjust the subreg index to account for doubleword swapping .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return nullptr ; } switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: WRASRrr , dl , MVT :: i32 , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; TopPart = CurDAG -> getCopyToReg ( TopPart , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: Glue , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDASR , MVT :: i32 , CurDAG -> getRegister ( SP :: Y , MVT :: i32 ) , SDValue ( Mul , 1 ) ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f128 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: f128 ; if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: i64 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: i64 ; if ( Size >= 4 && ( memOpAlign ( SrcAlign , DstAlign , 4 ) || ( allowsMisalignedMemoryAccesses ( MVT :: i32 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> BitVector TeeRISCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { TeeRISC :: R0 , TeeRISC :: R1 , TeeRISC :: R14 , TeeRISC :: R15 , TeeRISC :: R16 , TeeRISC :: R17 , TeeRISC :: R18 , TeeRISC :: R19 , TeeRISC :: R20 , TeeRISC :: R21 , TeeRISC :: R22 , TeeRISC :: R23 , TeeRISC :: R24 , TeeRISC :: R25 , TeeRISC :: R26 , TeeRISC :: R27 , TeeRISC :: R28 , TeeRISC :: R29 , TeeRISC :: R30 , TeeRISC :: R31 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> Register ( ) { ARMTargetMachine :: registerAsmPrinter ( createARMCodePrinterPass ) ; } </s>


Allocate ORIG_SIZE bytes on the stack and probe the newly allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes . COPY_REG , if non-null , should contain a copy of the original stack pointer at exit from this function . This is subtly different than the Ada probing in that it tries hard to prevent attacks that jump the stack guard . Thus it is never allowed to allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack space without a suitable probe .


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Store Pair Suppression"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"ARM Loops: Failed to find all loop components.\n"

Dump the plan to stderr ( for debugging ) .


<s> void releaseMemory ( ) override { ShapeBBs . clear ( ) ; DefVisited . clear ( ) ; BBVisitedInfo . clear ( ) ; } </s>

releaseMemory ( ) - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed .


<s> bool Mips16RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Conditional Compares"
;
}
</s>


<s> bool DCPU16PassConfig :: addInstSelector ( ) { addPass ( createDCPU16ISelDag ( getDCPU16TargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createDCPU16Peephole ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallSet < Constant * , 8 > AlreadyChecked ; for ( auto & MBB : F ) { for ( auto & MI : MBB ) { for ( unsigned OpIdx = 0 , EndOpIdx = MI . getNumOperands ( ) ; OpIdx != EndOpIdx ; ++ OpIdx ) { Constant * Cst = dyn_cast < Constant > ( MI . getOperand ( OpIdx ) ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } } return LocalChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , const MachineInstr * Orig ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned SubIdx = Orig -> getOperand ( 0 ) . isReg ( ) ? Orig -> getOperand ( 0 ) . getSubReg ( ) : 0 ; bool ChangeSubIdx = SubIdx != 0 ; if ( SubIdx && TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) { DestReg = RI . getSubReg ( DestReg , SubIdx ) ; SubIdx = 0 ; } bool Emitted = false ; switch ( Orig -> getOpcode ( ) ) { default : break ; case X86 :: MOV8r0 : case X86 :: MOV16r0 : case X86 :: MOV32r0 : case X86 :: MOV64r0 : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { unsigned Opc = 0 ; switch ( Orig -> getOpcode ( ) ) { default : break ; case X86 :: MOV8r0 : Opc = X86 :: MOV8ri ; break ; case X86 :: MOV16r0 : Opc = X86 :: MOV16ri ; break ; case X86 :: MOV32r0 : Opc = X86 :: MOV32ri ; break ; case X86 :: MOV64r0 : Opc = X86 :: MOV64ri32 ; break ; } BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addImm ( 0 ) ; Emitted = true ; } break ; } } if ( ! Emitted ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } if ( ChangeSubIdx ) { MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> void AArch64PassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; addPass ( createAArch64PreLegalizeCombiner ( IsOptNone ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


"Stack offset for byval regs doesn't introduced anymore?"

Target-specific cleanup for formal ByVal parameters .


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr ) { int regno ; sr -> saved = false ; if ( TARGET_64BIT ) { regno = R11_REG ; } else { tree decl = current_function_decl , fntype = TREE_TYPE ( decl ) ; bool fastcall_p = lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool thiscall_p = lookup_attribute ( "thiscall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool static_chain_p = DECL_STATIC_CHAIN ( decl ) ; int regparm = ix86_function_regparm ( fntype , decl ) ; int drap_regno = crtl -> drap_reg ? REGNO ( crtl -> drap_reg ) : INVALID_REGNUM ; if ( ( regparm < 1 || ( fastcall_p && ! static_chain_p ) ) && drap_regno != AX_REG ) regno = AX_REG ; else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < 2 && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < 3 && ! fastcall_p && ! thiscall_p && ! static_chain_p && drap_regno != CX_REG ) regno = CX_REG ; else if ( ix86_save_reg ( BX_REG , true ) ) regno = BX_REG ; else if ( ! ( regparm == 3 && static_chain_p ) && ix86_save_reg ( SI_REG , true ) ) regno = SI_REG ; else if ( ix86_save_reg ( DI_REG , true ) ) regno = DI_REG ; else { regno = ( drap_regno == AX_REG ? DX_REG : AX_REG ) ; sr -> saved = true ; } } sr -> reg = gen_rtx_REG ( Pmode , regno ) ; if ( sr -> saved ) { rtx_insn * insn = emit_insn ( gen_push ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Return a short-lived scratch register for use on function entry . In 32-bit mode , it is valid only after the registers are saved in the prologue . This register must be released by means of release_scratch_register_on_entry once it is dead .


"%qE attribute only applies to interrupt functions"

Generate 'handle_interrupt ' attribute for decls


<s> void emitAssignment ( MCSymbol * Symbol , const MCExpr * Value ) override { if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; unsigned Other = MCELF :: getOther ( SymbolData ) << 2 ; Other &= ~ ELF :: STO_PPC64_LOCAL_MASK ; Other |= ( MCELF :: getOther ( Data ) << 2 ) & ELF :: STO_PPC64_LOCAL_MASK ; MCELF :: setOther ( SymbolData , Other >> 2 ) ; } </s>


<s> static rtx expand_mad ( function_expander & e , unsigned int merge_argno = DEFAULT_MERGE_ARGNO ) { if ( e . pred == PRED_x ) { insn_code icode ; if ( e . type_suffix ( 0 ) . integer_p ) icode = code_for_aarch64_pred_fma ( e . vector_mode ( 0 ) ) ; else icode = code_for_aarch64_pred ( UNSPEC_COND_FMLA , e . vector_mode ( 0 ) ) ; return e . use_pred_x_insn ( icode ) ; } insn_code icode = e . direct_optab_handler ( cond_fma_optab ) ; return e . use_cond_insn ( icode , merge_argno ) ; } </s>

Expand a call to svmad , or svmla after reordering its operands . Make _m forms merge with argument MERGE_ARGNO .


<s> unsigned PPCAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { int64_t ImmVal ; switch ( Kind ) { case MCK_0 : ImmVal = 0 ; break ; case MCK_1 : ImmVal = 1 ; break ; case MCK_2 : ImmVal = 2 ; break ; case MCK_3 : ImmVal = 3 ; break ; default : return Match_InvalidOperand ; } PPCOperand * Op = static_cast < PPCOperand * > ( AsmOp ) ; if ( Op -> isImm ( ) && Op -> getImm ( ) == ImmVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static bool exact_dependency_1 ( rtx addr , rtx insn ) { enum rtx_code code ; const char * format_ptr ; int i , j ; code = GET_CODE ( insn ) ; switch ( code ) { case MEM : if ( rtx_equal_p ( addr , insn ) ) return true ; break ; case REG : CASE_CONST_ANY : case SYMBOL_REF : case CODE_LABEL : case PC : case EXPR_LIST : return false ; default : break ; } format_ptr = GET_RTX_FORMAT ( code ) ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; i ++ ) { switch ( * format_ptr ++ ) { case 'e' : if ( exact_dependency_1 ( addr , XEXP ( insn , i ) ) ) return true ; break ; case 'E' : for ( j = 0 ; j < XVECLEN ( insn , i ) ; j ++ ) if ( exact_dependency_1 ( addr , XVECEXP ( insn , i , j ) ) ) return true ; break ; } } return false ; } </s>

Helper function for exact_store_load_dependency . Return true if addr is found in insn .


<s> rtx rs6000_emit_eqne ( machine_mode mode , rtx op1 , rtx op2 , rtx scratch ) { if ( op2 == const0_rtx ) return op1 ; if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx ( mode , op2 ) ) ) ) ; return scratch ; } </s>

Emit RTL that sets a register to zero if OP1 and OP2 are equal . SCRATCH can be used as that dest register . Return the dest register .


<s> const MCExpr * X86TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget . isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool aarch64_emit_approx_div ( rtx quo , rtx num , rtx den ) { machine_mode mode = GET_MODE ( quo ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) return false ; bool use_approx_division_p = ( flag_mlow_precision_div || ( aarch64_tune_params . approx_modes -> division & AARCH64_APPROX_MODE ( mode ) ) ) ; if ( ! flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) || ! use_approx_division_p ) return false ; if ( ! TARGET_SIMD && VECTOR_MODE_P ( mode ) ) return false ; rtx xrcp = gen_reg_rtx ( mode ) ; emit_insn ( gen_aarch64_frecpe ( mode , xrcp , den ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( flag_mlow_precision_div ) iterations -- ; rtx xtmp = gen_reg_rtx ( mode ) ; while ( iterations -- ) { emit_insn ( gen_aarch64_frecps ( mode , xtmp , xrcp , den ) ) ; if ( iterations > 0 ) emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; } if ( num != CONST1_RTX ( mode ) ) { rtx xnum = force_reg ( mode , num ) ; emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xnum ) ) ; } emit_set_insn ( quo , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; return true ; } </s>

Emit the instruction sequence to compute the approximation for the division of NUM by DEN in QUO and return whether the sequence was emitted or not .


<s> static void print_slot ( rtx_sequence * seq ) { final_scan_insn ( seq -> insn ( 1 ) , asm_out_file , optimize , 1 , NULL ) ; seq -> insn ( 1 ) -> set_deleted ( ) ; } </s>

Print an instruction which would have gone into a delay slot after another instruction , but could n't because the other instruction expanded into a sequence where putting the slot insn at the end would n't work .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createSystemZObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , op0 , mode , op1 , mode , XEXP ( rem , 0 ) , Pmode ) ; * quot_p = quot ; * rem_p = rem ; } </s>


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( * Fn . getFunction ( ) ) ) return false ; TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getSubtarget < ARMSubtarget > ( ) ; if ( ! STI -> expandMLx ( ) ) return false ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool rs6000_parm_needs_stack ( cumulative_args_t args_so_far , tree type ) { machine_mode mode ; int unsignedp ; rtx entry_parm ; if ( type == NULL || type == error_mark_node ) return true ; if ( TYPE_MODE ( type ) == VOIDmode ) return false ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) return ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) || rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) ) ; if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; if ( pass_by_reference ( get_cumulative_args ( args_so_far ) , TYPE_MODE ( type ) , type , true ) ) type = build_pointer_type ( type ) ; unsignedp = TYPE_UNSIGNED ( type ) ; mode = promote_mode ( type , TYPE_MODE ( type ) , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( mode , type ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , mode , type , true ) ; if ( entry_parm == NULL ) return true ; if ( GET_CODE ( entry_parm ) == PARALLEL && XEXP ( XVECEXP ( entry_parm , 0 , 0 ) , 0 ) == NULL_RTX ) return true ; if ( rs6000_arg_partial_bytes ( args_so_far , mode , type , true ) != 0 ) return true ; rs6000_function_arg_advance ( args_so_far , mode , type , true ) ; return false ; } </s>

Process parameter of type TYPE after ARGS_SO_FAR parameters were already processes . Return true if the parameter must be passed ( fully or partially ) on the stack .


<s> bool MipsTargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget . hasMips32 ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
.
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
.
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
!
Subtarget
->
useRetpoline
(
)
&&
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
&&
!
Subtarget
->
slowTwoMemOps
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s>
static
bool
matchBitfieldExtractFromSExtInReg
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
std
::
function
<
void
(
MachineIRBuilder
&
)
>
&
MatchInfo
)
{
assert
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
G_SEXT_INREG
)
;
Register
Dst
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
Register
Src
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
int64_t
Width
=
MI
.
getOperand
(
2
)
.
getImm
(
)
;
LLT
Ty
=
MRI
.
getType
(
Src
)
;
assert
(
(
Ty
==
LLT
::
scalar
(
32
)
||
Ty
==
LLT
::
scalar
(
64
)
)
&&
"Unexpected type for G_SEXT_INREG?"
)
;
Register
ShiftSrc
;
int64_t
ShiftImm
;
if
(
!
mi_match
(
Src
,
MRI
,
m_OneNonDBGUse
(
m_any_of
(
m_GAShr
(
m_Reg
(
ShiftSrc
)
,
m_ICst
(
ShiftImm
)
)
,
m_GLShr
(
m_Reg
(
ShiftSrc
)
,
m_ICst
(
ShiftImm
)
)
)
)
)
)
return
false
;
if
(
ShiftImm
<
0
||
ShiftImm
+
Width
>
Ty
.
getSizeInBits
(
)
)
return
false
;
MatchInfo
=
[
=
]
(
MachineIRBuilder
&
B
)
{
auto
Cst1
=
B
.
buildConstant
(
Ty
,
ShiftImm
)
;
auto
Cst2
=
B
.
buildConstant
(
Ty
,
Width
)
;
B
.
buildInstr
(
TargetOpcode
::
G_SBFX
,
{
Dst
}
,
{
ShiftSrc
,
Cst1
,
Cst2
}
)
;
}
;
return
true
;
}
</s>

Form a G_SBFX from a G_SEXT_INREG fed by a right shift .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) && hasAtomicRMW ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; return ( RealignStack && ! AFI -> isThumb1OnlyFunction ( ) && ! MFI -> hasVarSizedObjects ( ) ) ; } </s>

True if the stack can be realigned for the target .


<s> bool ARMBaseRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
static
char
*
rs6000_savres_routine_name
(
int
regno
,
int
sel
)
{
const
char
*
prefix
=
""
;
const
char
*
suffix
=
""
;
if
(
DEFAULT_ABI
==
ABI_V4
)
{
if
(
TARGET_64BIT
)
goto
aix_names
;
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_GPR
)
prefix
=
(
sel
&
SAVRES_SAVE
)
"_savegpr_"
:
"_restgpr_"
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_FPR
)
prefix
=
(
sel
&
SAVRES_SAVE
)
"_savefpr_"
:
"_restfpr_"
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_VR
)
prefix
=
(
sel
&
SAVRES_SAVE
)
"_savevr_"
:
"_restvr_"
;
else
abort
(
)
;
if
(
(
sel
&
SAVRES_LR
)
)
suffix
=
"_x"
;
}
else
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
{
gcc_assert
(
!
TARGET_AIX
||
(
sel
&
SAVRES_REG
)
!=
SAVRES_GPR
)
;
aix_names
:
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_GPR
)
prefix
=
(
(
sel
&
SAVRES_SAVE
)
(
(
sel
&
SAVRES_LR
)
"_savegpr0_"
:
"_savegpr1_"
)
:
(
(
sel
&
SAVRES_LR
)
"_restgpr0_"
:
"_restgpr1_"
)
)
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_FPR
)
{
if
(
(
sel
&
SAVRES_LR
)
)
prefix
=
(
(
sel
&
SAVRES_SAVE
)
"_savefpr_"
:
"_restfpr_"
)
;
else
{
prefix
=
(
sel
&
SAVRES_SAVE
)
SAVE_FP_PREFIX
:
RESTORE_FP_PREFIX
;
suffix
=
(
sel
&
SAVRES_SAVE
)
SAVE_FP_SUFFIX
:
RESTORE_FP_SUFFIX
;
}
}
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_VR
)
prefix
=
(
sel
&
SAVRES_SAVE
)
"_savevr_"
:
"_restvr_"
;
else
abort
(
)
;
}
if
(
DEFAULT_ABI
==
ABI_DARWIN
)
{
prefix
=
(
sel
&
SAVRES_SAVE
)
"save"
:
"rest"
;
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_GPR
)
sprintf
(
savres_routine_name
,
"*%sGPR%s%s%.0d ; %s r%d-r31"
,
prefix
,
(
(
sel
&
SAVRES_LR
)
"x"
:
""
)
,
(
regno
==
13
""
:
"+"
)
,
(
regno
13
)
*
4
,
prefix
,
regno
)
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_FPR
)
sprintf
(
savres_routine_name
,
"*%sFP%s%.0d ; %s f%d-f31"
,
prefix
,
(
regno
==
14
""
:
"+"
)
,
(
regno
14
)
*
4
,
prefix
,
regno
)
;
else
if
(
(
sel
&
SAVRES_REG
)
==
SAVRES_VR
)
sprintf
(
savres_routine_name
,
"*%sVEC%s%.0d ; %s v%d-v31"
,
prefix
,
(
regno
==
20
""
:
"+"
)
,
(
regno
20
)
*
8
,
prefix
,
regno
)
;
else
abort
(
)
;
}
else
sprintf
(
savres_routine_name
,
"%s%d%s"
,
prefix
,
regno
,
suffix
)
;
return
savres_routine_name
;
}
</s>

Return the name for an out-of-line register save/restore routine . We are saving/restoring GPRs if GPR is true .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; } </s>


<s> llvm :: FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetDarwin ( ) && ! Subtarget -> isThumb1Only ( ) && ! DisableARMFastISel ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

ARM ARM::createFastISel ARM ARM ARM ARM 0


<s> void save_restore_target_globals ( tree new_tree ) { if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else { TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } arm_option_params_internal ( ) ; } </s>

Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE .


<s> static bool aapcs_vfp_allocate ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { int rmode_size = MAX ( GET_MODE_SIZE ( pcum -> aapcs_vfp_rmode ) , GET_MODE_SIZE ( SFmode ) ) ; int shift = rmode_size / GET_MODE_SIZE ( SFmode ) ; unsigned mask = ( 1 << ( shift * pcum -> aapcs_vfp_rcount ) ) - 1 ; int regno ; for ( regno = 0 ; regno < NUM_VFP_ARG_REGS ; regno += shift ) if ( ( ( pcum -> aapcs_vfp_regs_free >> regno ) & mask ) == mask ) { pcum -> aapcs_vfp_reg_alloc = mask << regno ; if ( mode == BLKmode || ( mode == TImode && ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) || ! arm_hard_regno_mode_ok ( FIRST_VFP_REGNUM + regno , mode ) ) { int i ; int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! ( TARGET_NEON || TARGET_HAVE_MVE ) ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= 2 ; rshift /= 2 ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = 0 ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM + regno ) ; return true ; } return false ; } </s>

Implement the allocate field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s>
SDValue
MandarinTargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
ConstantPoolSDNode
*
CP
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
CP
->
getConstVal
(
)
,
CP
->
getValueType
(
0
)
,
CP
->
getAlignment
(
)
,
CP
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> void X86AvoidSFBPass :: buildCopy ( MachineInstr * LoadInst , unsigned NLoadOpcode , int64_t LoadDisp , MachineInstr * StoreInst , unsigned NStoreOpcode , int64_t StoreDisp , unsigned Size , int64_t LMMOffset , int64_t SMMOffset ) { MachineOperand & LoadBase = getBaseOperand ( LoadInst ) ; MachineOperand & StoreBase = getBaseOperand ( StoreInst ) ; MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; MachineMemOperand * LMMO = * LoadInst -> memoperands_begin ( ) ; MachineMemOperand * SMMO = * StoreInst -> memoperands_begin ( ) ; unsigned Reg1 = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( NLoadOpcode ) , 0 , TRI , * ( MBB -> getParent ( ) ) ) ) ; BuildMI ( * MBB , LoadInst , LoadInst -> getDebugLoc ( ) , TII -> get ( NLoadOpcode ) , Reg1 ) . add ( LoadBase ) . addImm ( 1 ) . addReg ( X86 :: NoRegister ) . addImm ( LoadDisp ) . addReg ( X86 :: NoRegister ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( LMMO , LMMOffset , Size ) ) ; DEBUG ( LoadInst -> getPrevNode ( ) -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; if ( StoreInst -> getPrevNode ( ) == LoadInst ) StInst = LoadInst ; BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( 1 ) . addReg ( X86 :: NoRegister ) . addImm ( StoreDisp ) . addReg ( X86 :: NoRegister ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ; DEBUG ( StInst -> getPrevNode ( ) -> dump ( ) ) ; } </s>


<s>
int
ix86_attr_length_immediate_default
(
rtx_insn
*
insn
,
bool
shortform
)
{
int
len
=
0
;
int
i
;
extract_insn_cached
(
insn
)
;
for
(
i
=
recog_data
.
n_operands
1
;
i
>=
0
;
i
)
if
(
CONSTANT_P
(
recog_data
.
operand
[
i
]
)
)
{
enum
attr_mode
mode
=
get_attr_mode
(
insn
)
;
gcc_assert
(
!
len
)
;
if
(
shortform
&&
CONST_INT_P
(
recog_data
.
operand
[
i
]
)
)
{
HOST_WIDE_INT
ival
=
INTVAL
(
recog_data
.
operand
[
i
]
)
;
switch
(
mode
)
{
case
MODE_QI
:
len
=
1
;
continue
;
case
MODE_HI
:
ival
=
trunc_int_for_mode
(
ival
,
HImode
)
;
break
;
case
MODE_SI
:
ival
=
trunc_int_for_mode
(
ival
,
SImode
)
;
break
;
default
:
break
;
}
if
(
IN_RANGE
(
ival
,
128
,
127
)
)
{
len
=
1
;
continue
;
}
}
switch
(
mode
)
{
case
MODE_QI
:
len
=
1
;
break
;
case
MODE_HI
:
len
=
2
;
break
;
case
MODE_SI
:
len
=
4
;
break
;
case
MODE_DI
:
len
=
4
;
break
;
default
:
fatal_insn
(
"unknown insn mode"
,
insn
)
;
}
}
return
len
;
}
</s>

Compute default value for `` length_immediate '' attribute . When SHORTFORM is set expect that insn have 8bit immediate alternative .


<s> bool TOYPassConfig :: addPreISel ( ) { return false ; } </s>


<s> bool requiresVirtualBaseRegisters ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
Mangler
*
Mang
,
MachineModuleInfo
*
MMI
,
unsigned
Encoding
,
MCStreamer
&
Streamer
)
const
{
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
Triple
T
(
MMI
->
getModule
(
)
->
getTargetTriple
(
)
)
;
if
(
T
.
isOSNaCl
(
)
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Mang
,
MMI
,
Encoding
,
Streamer
)
;
return
MCSymbolRefExpr
::
Create
(
Mang
->
getSymbol
(
GV
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
"Can handle absptr encoding only"
ARM


<s> bool isLegalMaskedScatter ( Type * DataType , Align Alignment ) const { return isLegalMaskedGatherScatter ( DataType ) ; } </s>

Return true if the target supports masked scatter .


<s> void or1k_expand_epilogue ( void ) { HOST_WIDE_INT reg_offset , sp_offset ; rtx insn , cfa_restores = NULL ; sp_offset = cfun -> machine -> total_size ; if ( sp_offset == 0 ) return ; reg_offset = cfun -> machine -> local_vars_size + cfun -> machine -> args_size ; if ( sp_offset >= 32768 || cfun -> calls_alloca ) { if ( frame_pointer_needed ) { sp_offset -= reg_offset ; reg_offset = 0 ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - sp_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ; } else if ( sp_offset >= 3 * 32768 ) { rtx tmp = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( tmp , GEN_INT ( reg_offset ) ) ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; sp_offset -= reg_offset ; reg_offset = 0 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ; } else { do { HOST_WIDE_INT this_offset = MIN ( reg_offset , 32764 ) ; reg_offset -= this_offset ; sp_offset -= this_offset ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( this_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ; } while ( sp_offset >= 32768 ) ; } } for ( int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regno != HARD_FRAME_POINTER_REGNUM && regno != LR_REGNUM && callee_saved_regno_p ( regno ) ) { cfa_restores = or1k_restore_reg ( regno , reg_offset , cfa_restores ) ; reg_offset += UNITS_PER_WORD ; } if ( callee_saved_regno_p ( HARD_FRAME_POINTER_REGNUM ) ) { cfa_restores = or1k_restore_reg ( HARD_FRAME_POINTER_REGNUM , reg_offset , cfa_restores ) ; reg_offset += UNITS_PER_WORD ; } if ( callee_saved_regno_p ( LR_REGNUM ) ) { cfa_restores = or1k_restore_reg ( LR_REGNUM , reg_offset , cfa_restores ) ; reg_offset += UNITS_PER_WORD ; } gcc_assert ( reg_offset == sp_offset ) ; insn = emit_insn ( gen_frame_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = cfa_restores ; add_reg_note ( insn , REG_CFA_DEF_CFA , stack_pointer_rtx ) ; if ( crtl -> calls_eh_return ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; } </s>


<s> MCSymbol * X86TargetLowering :: getPICBaseSymbol ( const MachineFunction * MF , MCContext & Ctx ) const { const MCAsmInfo & MAI = * getTargetMachine ( ) . getMCAsmInfo ( ) ; return Ctx . GetOrCreateTemporarySymbol ( Twine ( MAI . getPrivateGlobalPrefix ( ) ) + Twine ( MF -> getFunctionNumber ( ) ) + "$pb" ) ; } </s>

getPICBaseSymbol - Return a function-local symbol to represent the PIC base .


<s> bool csky_tls_referenced_p ( rtx x ) { if ( ! TARGET_TLS ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ; } return false ; } </s>

Return TRUE if X contains any references to TLS symbols .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = MF -> begin ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void OpenRISCRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { assert ( 0 && "Unimplemented" ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .