<s> void ix86_split_xorsign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = lowpart_subreg ( vmode , dest , mode ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; op0 = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_XOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>

Deconstruct an xorsign operation into bit masks .


<s> bool PPCPassConfig :: addPreSched2 ( ) { if ( getPPCSubtarget ( ) . hasVSX ( ) ) addPass ( createPPCVSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


Destroys the object . Bogus destructor overriding base class destructor .


<s>
bool
AArch64PostSelectOptimize
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Selected
)
&&
"Expected a selected MF"
)
;
bool
Changed
=
false
;
for
(
auto
&
BB
:
MF
)
Changed
|=
optimizeNZCVDefs
(
BB
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool ix86_target_stack_probe ( void ) { if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) return false ; return TARGET_STACK_PROBE ; } </s>

Decide whether we must probe the stack before any space allocation on this target . It 's essentially TARGET_STACK_PROBE except when -fstack-check causes the stack to be already probed differently .


<s> static rtx emit_adjust_base_to_offset ( rtx base , int offset ) { rtx new_base = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( new_base , GEN_INT ( offset ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_base , gen_rtx_PLUS ( Pmode , base , new_base ) ) ) ; return new_base ; } </s>

Emit code to adjust BASE to OFFSET . Return the new base .


<s> static void mips_asm_file_end ( void ) { if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ; } </s>

If we are optimizing the global pointer , emit the text section now and any small externs which did not have .comm , etc that are needed . Also , give a warning if the data area is more than 32K and -pic because 3 instructions are needed to reference the data pointers .


<s> static bool get_memref_parts ( rtx mem , rtx * base , HOST_WIDE_INT * offset , HOST_WIDE_INT * size ) { rtx addr_rtx ; if MEM_SIZE_KNOWN_P ( mem ) * size = MEM_SIZE ( mem ) ; else return false ; addr_rtx = ( XEXP ( mem , 0 ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , 1 ) ; * offset = 0 ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , 1 ) ) ) { * offset += INTVAL ( XEXP ( addr_rtx , 1 ) ) ; addr_rtx = XEXP ( addr_rtx , 0 ) ; } if ( ! REG_P ( addr_rtx ) ) return false ; * base = addr_rtx ; return true ; } </s>

Try to determine base/offset/size parts of the given MEM . Return true if successful , false if all the values could n't be determined . This function only looks for REG or REG+CONST address forms . REG+REG address form will return false .


<s> static rtx altivec_expand_vec_set_builtin ( tree arglist ) { enum machine_mode tmode , mode1 ; tree arg0 , arg1 , arg2 ; int elt ; rtx op0 , op1 ; arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; arg2 = TREE_VALUE ( TREE_CHAIN ( TREE_CHAIN ( arglist ) ) ) ; tmode = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; mode1 = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , tmode , 0 ) ; op1 = expand_expr ( arg1 , NULL_RTX , mode1 , 0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg2 ) ; if ( GET_MODE ( op1 ) != mode1 && GET_MODE ( op1 ) != VOIDmode ) op1 = convert_modes ( mode1 , GET_MODE ( op1 ) , op1 , true ) ; op0 = force_reg ( tmode , op0 ) ; op1 = force_reg ( mode1 , op1 ) ; rs6000_expand_vector_set ( op0 , op1 , elt ) ; return op0 ; } </s>


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
ModeSize
,
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
llvm
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
ModeSize
=
ModeSize
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> static int ix86_fp_comparison_sahf_cost ( enum rtx_code code ) { enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_USE_SAHF && ! optimize_size ) return 1024 ; ix86_fp_comparison_codes ( code , & bypass_code , & first_code , & second_code ) ; return ( bypass_code != UNKNOWN || second_code != UNKNOWN ) + 3 ; } </s>

Return cost of comparison done using sahf operation . See ix86_fp_comparison_arithmetics_cost for the metrics .


<s> static int eligible_for_restore_insn ( rtx trial , bool return_p ) { rtx pat = PATTERN ( trial ) ; rtx src = SET_SRC ( pat ) ; bool src_is_freg = false ; rtx src_reg ; src_reg = src ; if ( GET_CODE ( src_reg ) == SUBREG ) src_reg = SUBREG_REG ( src_reg ) ; if ( GET_CODE ( src_reg ) == REG && SPARC_FP_REG_P ( REGNO ( src_reg ) ) ) src_is_freg = true ; if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_operand ( src , GET_MODE ( src ) ) && ! src_is_freg ) { if ( TARGET_ARCH64 ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( SImode ) ; } else if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_double_operand ( src , GET_MODE ( src ) ) && ! src_is_freg ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else if ( ! TARGET_FPU && register_operand ( src , SFmode ) ) return 1 ; else if ( ! TARGET_FPU && TARGET_ARCH64 && register_operand ( src , DFmode ) ) return 1 ; else if ( return_p && TARGET_V9 && ! epilogue_renumber ( & pat , 1 ) ) return 1 ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , 0 ) , SImode ) && arith_operand ( XEXP ( src , 1 ) , SImode ) ) return 1 ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , 0 ) , DImode ) && arith_double_operand ( XEXP ( src , 1 ) , DImode ) ) return 1 ; else if ( GET_CODE ( src ) == LO_SUM && ! TARGET_CM_MEDMID && ( ( register_operand ( XEXP ( src , 0 ) , SImode ) && immediate_operand ( XEXP ( src , 1 ) , SImode ) ) || ( TARGET_ARCH64 && register_operand ( XEXP ( src , 0 ) , DImode ) && immediate_operand ( XEXP ( src , 1 ) , DImode ) ) ) ) return 1 ; else if ( GET_CODE ( src ) == ASHIFT && ( register_operand ( XEXP ( src , 0 ) , SImode ) || register_operand ( XEXP ( src , 0 ) , DImode ) ) && XEXP ( src , 1 ) == const1_rtx ) return 1 ; return 0 ; } </s>

Return nonzero if TRIAL , an insn , can be combined with a 'restore ' instruction . RETURN_P is true if the v9 variant 'return ' is to be considered in the test too . TRIAL must be a SET whose destination is a REG appropriate for the 'restore ' instruction or , if RETURN_P is true , for the 'return ' instruction .


<s> static bool aarch64_reads_global_state_p ( aarch64_simd_builtin_datum * d ) { unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_READ_FPCR ) return true ; return flags & FLAG_READ_MEMORY ; } </s>

Return true if calls to the function could read some form of global state .


<s> void Cpu0FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"PPC DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


"Disqualifying LR because GPR0 is live "


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static bool prologue_saved_reg_p ( int regno ) { gcc_assert ( GP_REG_P ( regno ) ) ; if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) return true ; if ( frame_pointer_needed && regno >= HARD_FRAME_POINTER_REGNUM && regno < HARD_FRAME_POINTER_REGNUM + GET_MODE_SIZE ( Pmode ) ) return true ; if ( regno == RA_REGNUM && df_regs_ever_live_p ( RA_REGNUM ) ) return true ; if ( regno == RA_REGNUM + 1 && df_regs_ever_live_p ( RA_REGNUM + 1 ) ) return true ; return false ; } </s>

Return true if REGNO should be saved in the prologue .


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 31 ; } </s>


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( GET_CODE ( XVECEXP ( x , 0 , 0 ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s> bool ARMFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) { CSI . emplace_back ( ARM :: FPCXTNS ) ; CSI . back ( ) . setRestored ( false ) ; } const auto & AFI = * MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI . shouldSignReturnAddress ( ) ) { CSI . insert ( find_if ( CSI , [ = ] ( const auto & CS ) { Register Reg = CS . getReg ( ) ; return Reg == ARM :: R10 || Reg == ARM :: R11 || Reg == ARM :: R8 || Reg == ARM :: R9 || ARM :: DPRRegClass . contains ( Reg ) ; } ) , CalleeSavedInfo ( ARM :: R12 ) ) ; } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> bool X86InstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI -> getOpcode ( ) ) ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .


<s> static bool r10k_safe_mem_expr_p ( tree expr , unsigned HOST_WIDE_INT offset ) { HOST_WIDE_INT bitoffset , bitsize ; tree inner , var_offset ; machine_mode mode ; int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p , false ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi ( DECL_SIZE_UNIT ( inner ) ) ; } </s>

Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is an in-range access to an automatic variable , or to an object with a link-time-constant address .


<s> void X86LowerTileCopy :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static void aapcs_layout_arg ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type , bool named ) { int nregs , nregs2 ; int ncrn ; if ( pcum -> aapcs_arg_processed ) return ; pcum -> aapcs_arg_processed = true ; if ( ! named ) return ; if ( pcum -> pcs_variant != ARM_PCS_AAPCS ) { int slot = aapcs_select_call_coproc ( pcum , mode , type ) ; pcum -> aapcs_cprc_slot = slot ; if ( slot >= 0 ) { if ( ! pcum -> aapcs_cprc_failed [ slot ] ) { if ( aapcs_cp_arg_layout [ slot ] . allocate ( pcum , mode , type ) ) return ; pcum -> aapcs_cprc_failed [ slot ] = true ; pcum -> can_split = false ; } gcc_assert ( pcum -> can_split == false ) ; return ; } } ncrn = pcum -> aapcs_ncrn ; if ( ( ncrn & 1 ) && arm_needs_doubleword_align ( mode , type ) ) ncrn ++ ; nregs = ARM_NUM_REGS2 ( mode , type ) ; gcc_assert ( nregs >= 0 ) ; nregs2 = nregs ? nregs : 1 ; if ( ncrn + nregs2 <= NUM_ARG_REGS ) { pcum -> aapcs_reg = gen_rtx_REG ( mode , ncrn ) ; pcum -> aapcs_next_ncrn = ncrn + nregs ; return ; } if ( ncrn < NUM_ARG_REGS && pcum -> can_split ) { pcum -> aapcs_reg = gen_rtx_REG ( mode , ncrn ) ; pcum -> aapcs_next_ncrn = NUM_ARG_REGS ; pcum -> aapcs_partial = ( NUM_ARG_REGS - ncrn ) * UNITS_PER_WORD ; return ; } pcum -> aapcs_next_ncrn = NUM_ARG_REGS ; return ; } </s>

Lay out a function argument using the AAPCS rules . The rule numbers referred to here are those in the AAPCS .


<s> void aarch64_d_target_versions ( void ) { d_add_builtin_version ( "AArch64" ) ; d_add_builtin_version ( "D_HardFloat" ) ; } </s>

Implement TARGET_D_CPU_VERSIONS for AArch64 targets .


<s> int ARM64TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty ) const { if ( isLegalAddressingMode ( AM , Ty ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> void MipsSETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


"ignoring %<-fschedule-insns%> because of exception "

"unwind tables currently require either a frame pointer "

"or %<-maccumulate-outgoing-args%> for correctness"

Implement TARGET_OPTION_OVERRIDE macro . Validate and override various options , and do some machine dependent initialization .


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( VECTOR_MEM_VSX_P ( mode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) reg_size = UNITS_PER_SPE_WORD ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else if ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SCmode && ! DECIMAL_FLOAT_MODE_P ( mode ) && SPE_SIMD_REGNO_P ( regno ) ) reg_size = UNITS_PER_FP_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


Emit the relocation to tie the next instruction to a previous instruction that loads up an external address . This is used to do the PCREL_OPT optimization . Note , the label is generated after the PLD of the got pc-relative address to allow for the assembler to insert NOPs before the PLD instruction . The operand is a constant integer that is the label number .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void F2003fDAGToDAGISel :: Select ( SDNode * Node ) { SDLoc dl ( Node ) ; if ( Node -> isMachineOpcode ( ) ) { Node -> setNodeId ( - 1 ) ; return ; } switch ( Node -> getOpcode ( ) ) { default : break ; case ISD :: FrameIndex : { int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; CurDAG -> SelectNodeTo ( Node , F2003f :: ATAframe , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i16 ) ) ; return ; } } SelectCode ( Node ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> void flushPendingInstructions ( MCStreamer & Out ) override { if ( ! inImplicitITBlock ( ) ) { assert ( PendingConditionalInsts . size ( ) == 0 ) ; return ; } MCInst ITInst ; ITInst . setOpcode ( ARM :: t2IT ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Cond ) ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Mask ) ) ; Out . EmitInstruction ( ITInst , getSTI ( ) ) ; assert ( PendingConditionalInsts . size ( ) <= 4 ) ; for ( const MCInst & Inst : PendingConditionalInsts ) { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } PendingConditionalInsts . clear ( ) ; ITState . Mask = 0 ; ITState . CurPosition = ~ 0U ; } </s>

Ensure that all previously parsed instructions have been emitted to the output streamer , if the target does not emit them immediately .


<s> bool LC2200InstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { const unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case LC2200 :: ADDI : return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == LC2200 :: zero ) ; } return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
VReg
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
MF
.
getDataLayout
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
)
{
MIRBuilder
.
buildUnmerge
(
Regs
,
VReg
)
;
}
)
;
FuncReturnHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
RetCC_X86
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Atom pad short functions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void rs6000_initialize_trampoline ( rtx addr , rtx fnaddr , rtx cxt ) { enum machine_mode pmode = Pmode ; int regsize = ( TARGET_32BIT ) ? 4 : 8 ; rtx ctx_reg = force_reg ( pmode , cxt ) ; switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; gen_rtx_MEM ( pmode , memory_address ( pmode , plus_constant ( addr , offset ) ) ) case ABI_AIX : { rtx fn_reg = gen_reg_rtx ( pmode ) ; rtx toc_reg = gen_reg_rtx ( pmode ) ; emit_move_insn ( fn_reg , MEM_DEREF ( fnaddr ) ) ; emit_move_insn ( toc_reg , MEM_PLUS ( fnaddr , regsize ) ) ; emit_move_insn ( MEM_DEREF ( addr ) , fn_reg ) ; emit_move_insn ( MEM_PLUS ( addr , regsize ) , toc_reg ) ; emit_move_insn ( MEM_PLUS ( addr , 2 * regsize ) , ctx_reg ) ; } break ; case ABI_DARWIN : case ABI_V4 : emit_library_call ( gen_rtx_SYMBOL_REF ( SImode , "__trampoline_setup" ) , FALSE , VOIDmode , 4 , addr , pmode , GEN_INT ( rs6000_trampoline_size ( ) ) , SImode , fnaddr , pmode , ctx_reg , pmode ) ; break ; } return ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> bool X86FixupSetCCPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 4 > ToErase ; for ( auto & MBB : MF ) { MachineInstr * FlagsDefMI = nullptr ; for ( auto & MI : MBB ) { if ( MI . definesRegister ( X86 :: EFLAGS ) ) FlagsDefMI = & MI ; if ( MI . getOpcode ( ) != X86 :: SETCCr ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( 0 ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == X86 :: MOVZX32rr8 ) ZExt = & Use ; if ( ! ZExt ) continue ; if ( ! FlagsDefMI ) continue ; if ( FlagsDefMI -> readsRegister ( X86 :: EFLAGS ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? & X86 :: GR32RegClass : & X86 :: GR32_ABCDRegClass ; Register ZeroReg = MRI -> createVirtualRegister ( RC ) ; Register InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( X86 :: MOV32r0 ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( X86 :: INSERT_SUBREG ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) ) . addImm ( X86 :: sub_8bit ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( 0 ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return Changed ; } </s>


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( ! MRI -> canReserveReg ( STI . getFramePointerReg ( ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> bool X86WinAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasWinAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = 4096 ; if ( MF . getFunction ( ) -> hasFnAttribute ( "stack-probe-size" ) ) { MF . getFunction ( ) -> getFnAttribute ( "stack-probe-size" ) . getValueAsString ( ) . getAsInteger ( 0 , StackProbeSize ) ; } LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true ; } </s>


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
int64_t
Imm
=
0
;
bool
IsConstant
=
false
;
if
(
auto
*
RE
=
dyn_cast
<
CAHPMCExpr
>
(
Expr
)
)
{
IsConstant
=
RE
->
evaluateAsConstant
(
Imm
)
;
}
else
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
{
IsConstant
=
true
;
Imm
=
CE
->
getValue
(
)
;
}
if
(
IsConstant
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
Imm
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s> bool LoongArchTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { return Outs . size ( ) <= 2 ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> Register PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = TM . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = getPointerRegClass ( MF ) ; Register BaseReg = MRI . createVirtualRegister ( RC ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; return BaseReg ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

PowerPC PPC PPC PPC::ADDI8 PPC::ADDI PPC PPC 0


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( CMP ) ; OPCODE ( UCMP ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


"LVI load hardening is only supported on 64-bit"


<s>
const
char
*
output_mov_double_fpa_from_arm
(
rtx
*
operands
)
{
int
arm_reg0
=
REGNO
(
operands
[
1
]
)
;
rtx
ops
[
2
]
;
gcc_assert
(
arm_reg0
!=
IP_REGNUM
)
;
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
arm_reg0
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
1
+
arm_reg0
)
;
output_asm_insn
(
"stm%?fd\t%|sp!, {%0, %1}"
,
ops
)
;
output_asm_insn
(
"ldf%?d\t%0, [%|sp], #8"
,
operands
)
;
return
""
;
}
</s>

Output a move from arm registers to an fpa registers . OPERANDS [ 0 ] is an fpa register . OPERANDS [ 1 ] is the first registers of an arm register pair .


<s> static void mips_emit_unary ( enum rtx_code code , rtx target , rtx op0 ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_e ( code , GET_MODE ( op0 ) , op0 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 ) ) .


<s> static unsigned HOST_WIDE_INT ix86_asan_shadow_offset ( void ) { return SUBTARGET_SHADOW_OFFSET ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


"Unknown parameter to option -mtune-ctrl: %s"

parse -mtune-ctrl= option . When DUMP is true , print the features that are explicitly set .


<s> EVT MipsTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( Subtarget . hasMips64 ( ) ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> static bool csky_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { int nregs = CSKY_NUM_REGS ( mode ) ; if ( nregs > 2 ) return false ; if ( regno < CSKY_NGPR_REGS ) { if ( nregs < 2 ) return true ; else if ( TARGET_MINI_REGISTERS ) return ( regno < CSKY_LAST_MINI_REGNUM ) ; else if ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) || ! TARGET_HIGH_REGISTERS ) return ( regno < ( CSKY_SP_REGNUM - 1 ) ) ; else return ( regno < ( CSKY_SP_REGNUM - 1 ) || ( regno >= CSKY_LR_REGNUM && regno < CSKY_LAST_HIGH_UNFIXED_REGNUM ) ) ; } else if ( regno == CSKY_CC_REGNUM ) return ( mode == CCmode ) ; else if ( regno == CSKY_HI_REGNUM || regno == CSKY_LO_REGNUM ) { if ( ! TARGET_DSP || mode == SFmode || mode == DFmode ) return false ; else if ( nregs == 2 ) return ( regno == CSKY_HI_REGNUM ) ; else return true ; } else if ( CSKY_VREG_P ( regno ) && TARGET_HARD_FLOAT ) return true ; return false ; } </s>

Implement TARGET_HARD_REGNO_MODE_OK . Return true if REGNO is a valid register for holding a quantity of type MODE .


<s> const char * getSymbol ( ) const { return S . c_str ( ) ; } </s>

Get the target address and flags for the named symbol .


<s> Register ( ) { X86TargetMachine :: registerAsmPrinter ( createX86CodePrinterPass ) ; } </s>


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb ( ) ) return false ; MVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ISD::POST_INC ISD::POST_DEC


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit , CodeGenOpt :: Level OptLevel ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , IsPPC64 ( is64Bit ) , TargetTriple ( TT ) , OptLevel ( OptLevel ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( usesGlobalOffsetTable ( ) ) return DAG . getGLOBAL_OFFSET_TABLE ( getPointerTy ( ) ) ; if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode ) ; } } </s>

Emit a sequence representing a little-endian VSX load or store , moving data from SOURCE to DEST in mode MODE . This is done separately from rs6000_emit_move to ensure it is called only during expand . LE VSX loads and stores introduced later are handled with a split . The expand-time RTL generation allows us to optimize away redundant pairs of register-permutes .


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s> bool isCtlzFast ( ) const override { return true ; } </s>

Return true if ctlz instruction is fast .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isThumb ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isThumb ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { DefRelocModel = getRelocationModel ( ) ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"FISC Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"%s instructions aren%'t allowed in a function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> virtual const TOYSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) ? 2 : 1 ; return MI . getOperand ( Idx ) ; } </s>

Returns the base register operator of a load/store .


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Don't know how to custom lower this!"
)
;
abort
(
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
CALL
:
return
LowerCALL
(
Op
,
DAG
)
;
case
ISD
::
RET
:
return
LowerRET
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
VarArgsFrameIndex
)
;
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
FORMAL_ARGUMENTS
:
return
LowerFORMAL_ARGUMENTS
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
break
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
ExpandSRx
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> static bool is_branch_slot_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ; return false ; } return false ; } </s>

The function returns true if INSN can be issued only from the branch slot .


<s> unsigned int getNumFixupKinds ( ) const override { return CSKY :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static int rename_dest ( tag_insn_info * insn_info , tag_map_t & tag_map ) { struct du_chain * chain = NULL ; du_head_p head = NULL ; int i ; unsigned dest_regno = REGNO ( insn_info -> dest ) ; if ( unsafe_rename_p ( dest_regno ) ) return - 1 ; rtx_insn * insn = insn_info -> insn ; operand_rr_info * dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; for ( i = 0 ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) if ( chain -> insn == insn ) return rename_chain ( insn_info , tag_map , head ) ; } return - 1 ; } </s>

Go through the def/use chains for the register and find the chain for this insn to rename . The function returns the hard register number in case of a successful rename and -1 otherwise .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const char * Func ) { PreAnalyzeCallOperands ( Outs , Fn , FuncArgs , Func ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> unsigned postOffset ( ) const { return Offset + Size ; } </s>

Compute the offset immediately following this block .


<s> static scalar_int_mode rs6000_abi_word_mode ( void ) { return TARGET_32BIT ? SImode : DImode ; } </s>

The mode the ABI uses for a word . This is not the same as word_mode for -m32 -mpowerpc64 . This is used to implement various target hooks .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> rtx aarch64_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; } </s>

Implement RETURN_ADDR_RTX . We do not support moving back to a previous frame .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( OutStreamer , & * I ) ) continue ; MCInst TmpInst0 ; MCInstLowering . Lower ( I , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
bool
BumpSP
=
RPII
==
RegPairs
.
rbegin
(
)
;
if
(
RPI
.
IsGPR
)
{
if
(
BumpSP
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXpre
:
AArch64
::
STRXpre
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
}
else
{
if
(
BumpSP
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDpre
:
AArch64
::
STRDpre
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
}
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
const
int
Offset
=
BumpSP
RPI
.
Offset
:
RPI
.
Offset
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
BumpSP
)
MIB
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
;
if
(
RPI
.
isPaired
(
)
)
{
MBB
.
addLiveIn
(
Reg1
)
;
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
else
{
MBB
.
addLiveIn
(
Reg1
)
;
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
BumpSP
Offset
*
8
:
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
}
return
true
;
}
</s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; IndirectTlsSegRefs = MF . getFunction ( ) . hasFnAttribute ( "indirect-tls-seg-refs" ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


Check whether or not the given MBB can be used as a epilogue for the target .


<s>
Register
SystemZTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r15"
,
SystemZ
::
R15D
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
bool
NeedShadowCallStackProlog
=
false
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
,
NeedShadowCallStackProlog
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
if
(
NeedShadowCallStackProlog
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AArch64
::
STRXpost
)
)
.
addReg
(
AArch64
::
X18
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
)
.
addReg
(
AArch64
::
X18
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MBB
.
addLiveIn
(
AArch64
::
X18
)
;
}
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
!
MRI
.
isReserved
(
Reg1
)
)
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
if
(
!
MRI
.
isReserved
(
Reg2
)
)
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
EVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU64RegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
CPURegsRegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
CPU64RegsRegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
LORegsRegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
LORegs64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerCONSTANTPOOL
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

Sparc
Sparc
"Should not custom lower this!"
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> bool aarch64_sve_ldff1_operand_p ( rtx op ) { if ( ! MEM_P ( op ) ) return false ; struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , XEXP ( op , 0 ) , GET_MODE ( op ) , false ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return known_eq ( addr . const_offset , 0 ) ; return addr . type == ADDRESS_REG_REG ; } </s>

Return true if OP is a valid MEM operand for an SVE LDFF1 instruction .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> bool CSKYFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>


<s> static tree make_dispatcher_decl ( const tree decl ) { tree func_decl ; char * func_name ; tree fn_type , func_type ; bool is_uniq = false ; if ( TREE_PUBLIC ( decl ) == 0 ) is_uniq = true ; func_name = make_name ( decl , "ifunc" , is_uniq ) ; fn_type = TREE_TYPE ( decl ) ; func_type = build_function_type ( TREE_TYPE ( fn_type ) , TYPE_ARG_TYPES ( fn_type ) ) ; func_decl = build_fn_decl ( func_name , func_type ) ; XDELETEVEC ( func_name ) ; TREE_USED ( func_decl ) = 1 ; DECL_CONTEXT ( func_decl ) = NULL_TREE ; DECL_INITIAL ( func_decl ) = error_mark_node ; DECL_ARTIFICIAL ( func_decl ) = 1 ; DECL_EXTERNAL ( func_decl ) = 1 ; TREE_PUBLIC ( func_decl ) = 1 ; return func_decl ; } </s>

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Return the decl created .


<s> bool loongarch_symbolic_constant_p ( rtx x , enum loongarch_symbol_type * symbol_type ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( SYMBOL_REF_P ( x ) || LABEL_REF_P ( x ) ) { * symbol_type = loongarch_classify_symbol ( x ) ; if ( * symbol_type == SYMBOL_TLS ) return true ; } else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_TLS_IE : case SYMBOL_TLS_LE : case SYMBOL_TLSGD : case SYMBOL_TLSLDM : case SYMBOL_PCREL : case SYMBOL_PCREL64 : return sext_hwi ( INTVAL ( offset ) , 32 ) == INTVAL ( offset ) ; case SYMBOL_GOT_DISP : case SYMBOL_TLS : return false ; } gcc_unreachable ( ) ; } </s>

Return true if X is a symbolic constant . If it is , store the type of the symbol in * SYMBOL_TYPE .


<s> MachineInstrBuilder emitInst ( unsigned Opc , unsigned DstReg ) { return BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DstReg ) ; } </s>

Callback used to implement the .inst directive .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , DL ( computeDataLayout ( TargetTriple ) ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - 8 : - 4 ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void LoongArchFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { X86PassConfig * PC = new X86PassConfig ( this , PM ) ; if ( X86EarlyIfConv && Subtarget . hasCMov ( ) ) PC -> enablePass ( & EarlyIfConverterID ) ; return PC ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static tree ix86_builtin_tm_store ( tree type ) { if ( TREE_CODE ( type ) == VECTOR_TYPE ) { switch ( tree_to_uhwi ( TYPE_SIZE ( type ) ) ) { case 64 : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M64 ) ; case 128 : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M128 ) ; case 256 : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M256 ) ; } } return NULL_TREE ; } </s>

Return the builtin decl needed to store a vector of TYPE .


<s> static void winnt_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "objectFormat" , winnt_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>

Implement TARGET_D_REGISTER_OS_TARGET_INFO for Windows targets .


<s> SDNode * Cpu0DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < Cpu0MachineFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool isMem ( ) const { return Kind == k_Memory ; } </s>


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> int sparc_check_64 ( rtx x , rtx insn ) { int set_once = 0 ; rtx y = x ; gcc_assert ( GET_CODE ( x ) == REG ) ; if ( GET_MODE ( x ) == DImode ) y = gen_rtx_REG ( SImode , REGNO ( x ) + WORDS_BIG_ENDIAN ) ; if ( flag_expensive_optimizations && REG_N_SETS ( REGNO ( y ) ) == 1 ) set_once = 1 ; if ( insn == 0 ) { if ( set_once ) insn = get_last_insn_anywhere ( ) ; else return 0 ; } while ( ( insn = PREV_INSN ( insn ) ) ) { switch ( GET_CODE ( insn ) ) { case JUMP_INSN : case NOTE : break ; case CODE_LABEL : case CALL_INSN : default : if ( ! set_once ) return 0 ; break ; case INSN : { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) return 0 ; if ( rtx_equal_p ( x , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( y && rtx_equal_p ( y , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( reg_overlap_mentioned_p ( SET_DEST ( pat ) , y ) ) return 0 ; } } } return 0 ; } </s>

Return 0 if the high 32 bits of X ( the low word of X , if DImode ) are unknown . Return 1 if the high bits are zero , -1 if the register is sign extended .


<s> void PPCLinuxAsmPrinter :: emitFunctionEntryLabel ( ) { if ( ! Subtarget -> isPPC64 ( ) && ( ! isPositionIndependent ( ) || MF -> getFunction ( ) . getParent ( ) -> getPICLevel ( ) == PICLevel :: SmallPIC ) ) return AsmPrinter :: emitFunctionEntryLabel ( ) ; if ( ! Subtarget -> isPPC64 ( ) ) { const PPCFunctionInfo * PPCFI = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( PPCFI -> usesPICBase ( ) && ! Subtarget -> isSecurePlt ( ) ) { MCSymbol * RelocSymbol = PPCFI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer -> emitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( Twine ( ".LTOC" ) ) , OutContext ) , MCSymbolRefExpr :: create ( PICBase , OutContext ) , OutContext ) ; OutStreamer -> emitValue ( OffsExpr , 4 ) ; OutStreamer -> emitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: emitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! MF -> getRegInfo ( ) . use_empty ( PPC :: X2 ) ) { const PPCFunctionInfo * PPCFI = MF -> getInfo < PPCFunctionInfo > ( ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( ".TOC." ) ) ; MCSymbol * GlobalEPSymbol = PPCFI -> getGlobalEPSymbol ( ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , MCSymbolRefExpr :: create ( GlobalEPSymbol , OutContext ) , OutContext ) ; OutStreamer -> emitLabel ( PPCFI -> getTOCOffsetSymbol ( ) ) ; OutStreamer -> emitValue ( TOCDeltaExpr , 8 ) ; } return AsmPrinter :: emitFunctionEntryLabel ( ) ; } MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; MCSectionELF * Section = OutStreamer -> getContext ( ) . getELFSection ( ".opd" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Section ) ; OutStreamer -> emitLabel ( CurrentFnSym ) ; OutStreamer -> emitValueToAlignment ( 8 ) ; MCSymbol * Symbol1 = CurrentFnSymForSize ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( Symbol1 , OutContext ) , 8 ) ; MCSymbol * Symbol2 = OutContext . getOrCreateSymbol ( StringRef ( ".TOC." ) ) ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( Symbol2 , MCSymbolRefExpr :: VK_PPC_TOCBASE , OutContext ) , 8 ) ; OutStreamer -> emitIntValue ( 0 , 8 ) ; OutStreamer -> SwitchSection ( Current . first , Current . second ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips VR4300 mulmul bugfix"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"CHERI range checker"
;
}
</s>


<s> static void moxie_print_operand_address ( FILE * file , machine_mode , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , "(%s)" , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST_INT : fprintf ( file , "%ld(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; break ; case SYMBOL_REF : output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; break ; case CONST : { rtx plus = XEXP ( XEXP ( x , 1 ) , 0 ) ; if ( GET_CODE ( XEXP ( plus , 0 ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( plus , 1 ) ) ) { output_addr_const ( file , XEXP ( plus , 0 ) ) ; fprintf ( file , "+%ld(%s)" , INTVAL ( XEXP ( plus , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else abort ( ) ; } break ; default : abort ( ) ; } break ; default : output_addr_const ( file , x ) ; break ; } } </s>


<s>
X86TargetMachine
::
X86TargetMachine
(
const
Target
&
T
,
const
std
::
string
&
TT
,
const
std
::
string
&
FS
,
bool
is64Bit
)
:
LLVMTargetMachine
(
T
,
TT
)
,
Subtarget
(
TT
,
FS
,
is64Bit
)
,
FrameInfo
(
*
this
,
Subtarget
)
,
ELFWriterInfo
(
is64Bit
,
true
)
{
DefRelocModel
=
getRelocationModel
(
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
Default
)
{
if
(
Subtarget
.
isTargetDarwin
(
)
)
{
if
(
Subtarget
.
is64Bit
(
)
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
setRelocationModel
(
Reloc
::
DynamicNoPIC
)
;
}
else
if
(
Subtarget
.
isTargetWin64
(
)
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
setRelocationModel
(
Reloc
::
Static
)
;
}
assert
(
getRelocationModel
(
)
!=
Reloc
::
Default
&&
"Relocation mode not picked"
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
{
if
(
is64Bit
)
setRelocationModel
(
Reloc
::
PIC_
)
;
else
if
(
!
Subtarget
.
isTargetDarwin
(
)
)
setRelocationModel
(
Reloc
::
Static
)
;
}
if
(
getRelocationModel
(
)
==
Reloc
::
Static
&&
Subtarget
.
isTargetDarwin
(
)
&&
is64Bit
)
setRelocationModel
(
Reloc
::
PIC_
)
;
if
(
getRelocationModel
(
)
==
Reloc
::
Static
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
)
;
}
else
if
(
Subtarget
.
is64Bit
(
)
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
RIPRel
)
;
}
else
if
(
Subtarget
.
isTargetCygMing
(
)
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
)
;
}
else
if
(
Subtarget
.
isTargetDarwin
(
)
)
{
if
(
getRelocationModel
(
)
==
Reloc
::
PIC_
)
Subtarget
.
setPICStyle
(
PICStyles
::
StubPIC
)
;
else
{
assert
(
getRelocationModel
(
)
==
Reloc
::
DynamicNoPIC
)
;
Subtarget
.
setPICStyle
(
PICStyles
::
StubDynamicNoPIC
)
;
}
}
else
if
(
Subtarget
.
isTargetELF
(
)
)
{
Subtarget
.
setPICStyle
(
PICStyles
::
GOT
)
;
}
if
(
Subtarget
.
getPICStyle
(
)
==
PICStyles
::
)
setRelocationModel
(
Reloc
::
Static
)
;
}
</s>


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> static bool mips_return_in_msb ( const_tree valtype ) { if ( ! TARGET_NEWABI || ! TARGET_BIG_ENDIAN || ! AGGREGATE_TYPE_P ( valtype ) ) return false ; tree fields [ 2 ] ; bool has_cxx_zero_width_bf = false ; bool has_cxx17_empty_base = false ; return ( mips_fpr_return_fields ( valtype , fields , & has_cxx_zero_width_bf , & has_cxx17_empty_base ) == 0 || has_cxx_zero_width_bf ) ; } </s>

Implement TARGET_RETURN_IN_MSB . For n32 & n64 , we should return a value in the most significant part of $ 2/ $ 3 if : - the target is big-endian ; - the value has a structure or union type ( we generalize this to cover aggregates from other languages too ) ; and - the structure is not returned in floating-point registers .


<s> static tree xstormy16_build_builtin_va_list ( void ) { tree f_1 , f_2 , record , type_decl ; record = ( * lang_hooks . types . make_type ) ( RECORD_TYPE ) ; type_decl = build_decl ( BUILTINS_LOCATION , TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_1 = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "base" ) , ptr_type_node ) ; f_2 = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "count" ) , unsigned_type_node ) ; DECL_FIELD_CONTEXT ( f_1 ) = record ; DECL_FIELD_CONTEXT ( f_2 ) = record ; TYPE_STUB_DECL ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_1 ; DECL_CHAIN ( f_1 ) = f_2 ; layout_type ( record ) ; return record ; } </s>

Build the va_list type . For this chip , va_list is a record containing a counter and a pointer . The counter is of type 'int ' and indicates how many bytes have been used to date . The pointer indicates the stack position for arguments that have not been passed in registers . To keep the layout nice , the pointer is first in the structure .


<s> bool load_single_p ( rtx_insn * insn ) { if ( get_attr_type ( insn ) != TYPE_LOAD ) return false ; if ( INSN_CODE ( insn ) == CODE_FOR_move_di || INSN_CODE ( insn ) == CODE_FOR_move_df ) return false ; return true ; } </s>

Functions to determine whether INSN is single-word , double-word or partial-word load/store insn .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) { } </s>


<s> const uint16_t * TOYRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { TOY :: LR , TOY :: R2 , TOY :: R3 } ; return CalleeSavedRegs ; } </s>


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . hasStandardEncoding ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static unsigned parse_env_var ( const char * str , char * * * pvalues ) { const char * curval , * nextval ; char * * values ; unsigned num = 1 , i ; curval = strchr ( str , ':' ) ; while ( curval ) { num ++ ; curval = strchr ( curval + 1 , ':' ) ; } values = ( char * * ) xmalloc ( num * sizeof ( char * ) ) ; curval = str ; nextval = strchr ( curval , ':' ) ; if ( nextval == NULL ) nextval = strchr ( curval , '\0' ) ; for ( i = 0 ; i < num ; i ++ ) { int l = nextval - curval ; values [ i ] = ( char * ) xmalloc ( l + 1 ) ; memcpy ( values [ i ] , curval , l ) ; values [ i ] [ l ] = 0 ; curval = nextval + 1 ; nextval = strchr ( curval , ':' ) ; if ( nextval == NULL ) nextval = strchr ( curval , '\0' ) ; } * pvalues = values ; return num ; } </s>

Parse STR , saving found tokens into PVALUES and return their number . Tokens are assumed to be delimited by ' : ' .


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - 1 ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - 1 ; sign = REAL_VALUE_NEGATIVE ( r ) ? 1 : 0 ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; if ( mantissa != 0 ) return - 1 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return - 1 ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return - 1 ; gcc_assert ( mantissa >= 16 && mantissa <= 31 ) ; exponent = 5 - exponent ; if ( exponent < 0 || exponent > 7 ) return - 1 ; return ( sign << 7 ) | ( ( exponent ^ 3 ) << 4 ) | ( mantissa - 16 ) ; } </s>

Return an integer index for a VFPv3 immediate operand X suitable for the fconst [ sd ] instruction , or -1 if X is n't suitable .


<s> static std :: unique_ptr < ARMOperand > CreateMem ( unsigned BaseRegNum , const MCExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E , SMLoc AlignmentLoc = SMLoc ( ) ) { auto Op = std :: make_unique < ARMOperand > ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op ; } </s>


<s>
Register
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
LLT
::
scalar
(
64
)
;
if
(
!
is64Bit
&&
VT
!=
LLT
::
scalar
(
32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
isPPC64
Register
(
)
:
PPC
::
R2
)
.
Case
(
"r13"
,
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
static
void
ATTRIBUTE_UNUSED
i386_output_dwarf_dtprel
(
FILE
*
file
,
int
size
,
rtx
x
)
{
fputs
(
ASM_LONG
,
file
)
;
output_addr_const
(
file
,
x
)
;
fputs
(
"@dtpoff"
,
file
)
;
switch
(
size
)
{
case
4
:
break
;
case
8
:
fputs
(
", 0"
,
file
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> static void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; int reg_size = TARGET_32BIT ? 4 : 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx reg = gen_rtx_REG ( Pmode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , NULL ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( Pmode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } } </s>


<s> int ix86_binary_operator_ok ( enum rtx_code code , enum machine_mode mode ATTRIBUTE_UNUSED , rtx operands [ 3 ] ) { if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_CODE ( operands [ 2 ] ) == MEM ) return 0 ; if ( CONSTANT_P ( operands [ 1 ] ) && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH ) return 0 ; if ( GET_CODE ( operands [ 0 ] ) == MEM && ! ( rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) || ( GET_RTX_CLASS ( code ) == RTX_COMM_ARITH && rtx_equal_p ( operands [ 0 ] , operands [ 2 ] ) ) ) ) return 0 ; if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH && ! rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) ) return 0 ; return 1 ; } </s>

Return TRUE or FALSE depending on whether the binary operator meets the appropriate constraints .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> enum indirect_thunk_prefix indirect_thunk_need_prefix ( rtx_insn * insn ) { enum indirect_thunk_prefix need_prefix ; if ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) && ix86_notrack_prefixed_insn_p ( insn ) ) { need_prefix = indirect_thunk_prefix_nt ; } else need_prefix = indirect_thunk_prefix_none ; return need_prefix ; } </s>

Return the prefix needed for an indirect branch INSN .


<s> rtx gen_easy_altivec_constant ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtx val = CONST_VECTOR_ELT ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; unsigned step = nunits / 4 ; unsigned copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , val ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V8HImode , gen_lowpart ( HImode , val ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V16QImode , gen_lowpart ( QImode , val ) ) ; gcc_unreachable ( ) ; } </s>

Generate a VEC_DUPLICATE representing a vspltis [ bhw ] instruction whose result is OP . Abort if it is not possible .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
OperandType
type
,
\
uint8_t
index
,
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
if
(
insn
->
rexPrefix
&&
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_TMM
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_TMM0
+
index
;
\
case
TYPE_VK
:
\
index
&=
0xf
;
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_VK_PAIR
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0_K1
+
(
index
/
2
)
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> static bool ia64_attribute_takes_identifier_p ( const_tree attr_id ) { if ( is_attribute_p ( "model" , attr_id ) ) return true ; if ( is_attribute_p ( "common_object" , attr_id ) ) return true ; return false ; } </s>

Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain identifier as an argument , so the front end should n't look it up .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AdvSIMD Scalar Operation Optimization"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> tree function_resolver :: get_vector_type ( type_suffix_index type ) { return acle_vector_types [ 0 ] [ type_suffixes [ type ] . vector_type ] ; } </s>

Return the vector type associated with type suffix TYPE .


<s> void AArch64CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , const SplitArgTy & PerformArgSplit ) const { const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( SplitVTs . size ( ) == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ 0 ] . getTypeForEVT ( Ctx ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * SplitTy , DL ) ) , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } for ( unsigned i = 0 ; i < Offsets . size ( ) ; ++ i ) PerformArgSplit ( SplitArgs [ FirstRegIdx + i ] . Reg , Offsets [ i ] * 8 ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> void AArch64PostLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < GISelCSEAnalysisWrapperPass > ( ) ; AU . addPreserved < GISelCSEAnalysisWrapperPass > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> rtx swap_endian_selector_for_mode ( machine_mode mode ) { unsigned int swap1 [ 16 ] = { 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 } ; unsigned int swap2 [ 16 ] = { 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 } ; unsigned int swap4 [ 16 ] = { 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 , 11 , 10 , 9 , 8 , 15 , 14 , 13 , 12 } ; unsigned int swap8 [ 16 ] = { 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 , 9 , 8 , 11 , 10 , 13 , 12 , 15 , 14 } ; unsigned int * swaparray , i ; rtx perm [ 16 ] ; switch ( mode ) { case E_V1TImode : swaparray = swap1 ; break ; case E_V2DFmode : case E_V2DImode : swaparray = swap2 ; break ; case E_V4SFmode : case E_V4SImode : swaparray = swap4 ; break ; case E_V8HImode : swaparray = swap8 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < 16 ; ++ i ) perm [ i ] = GEN_INT ( swaparray [ i ] ) ; return force_reg ( V16QImode , gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , perm ) ) ) ; } </s>

Return the permutation index for the swapping on the given vector mode . Note that the permutation index is correspondingly generated by endianness , it should be used by direct vector permutation .


<s> int AArch64TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != 0 && AM . Scale != 1 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static void rs6000_elf_asm_init_sections ( void ) { toc_section = get_unnamed_section ( 0 , rs6000_elf_output_toc_section_asm_op , NULL ) ; sdata2_section = get_unnamed_section ( SECTION_WRITE , output_section_asm_op , SDATA2_SECTION_ASM_OP ) ; } </s>


<s> unsigned CSKYInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case CSKY :: LD16B : case CSKY :: LD16H : case CSKY :: LD16W : case CSKY :: LD32B : case CSKY :: LD32BS : case CSKY :: LD32H : case CSKY :: LD32HS : case CSKY :: LD32W : case CSKY :: FLD_S : case CSKY :: FLD_D : case CSKY :: f2FLD_S : case CSKY :: f2FLD_D : case CSKY :: RESTORE_CARRY : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void CSKYInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { if ( PrintBranchImmAsAddress ) O << getRegisterName ( RegNo , ABIRegNames ? CSKY :: ABIRegAltName : CSKY :: NoRegAltName ) ; else O << getRegisterName ( RegNo ) ; } </s>

CSKY CSKY CSKY::ABIRegAltName CSKY::NoRegAltName


Return a mask of call-preserved registers for the given calling convention on the current function .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> bool storeOfVectorConstantIsCheap ( EVT MemVT , unsigned NumElem , unsigned AddrSpace ) const override { return NumElem > 2 ; } </s>

Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants .


<s> static unsigned long rs6000_arg_size ( machine_mode mode , const_tree type ) { unsigned long size ; if ( mode != BLKmode ) size = GET_MODE_SIZE ( mode ) ; else size = int_size_in_bytes ( type ) ; if ( TARGET_32BIT ) return ( size + 3 ) >> 2 ; else return ( size + 7 ) >> 3 ; } </s>

Compute the size ( in words ) of a function argument .


<s> static void expand_set_or_movmem_via_rep ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx orig_value , rtx count , machine_mode mode , bool issetmem ) { rtx destexp ; rtx srcexp ; rtx countreg ; HOST_WIDE_INT rounded_count ; if ( mode == QImode && CONST_INT_P ( count ) && ! ( INTVAL ( count ) & 3 ) && ( ! issetmem || orig_value == const0_rtx ) ) mode = SImode ; if ( destptr != XEXP ( destmem , 0 ) || GET_MODE ( destmem ) != BLKmode ) destmem = adjust_automodify_address_nv ( destmem , BLKmode , destptr , 0 ) ; countreg = ix86_zero_extend_to_Pmode ( scale_counter ( count , GET_MODE_SIZE ( mode ) ) ) ; if ( mode != QImode ) { destexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; destexp = gen_rtx_PLUS ( Pmode , destexp , destptr ) ; } else destexp = gen_rtx_PLUS ( Pmode , destptr , countreg ) ; if ( ( ! issetmem || orig_value == const0_rtx ) && CONST_INT_P ( count ) ) { rounded_count = ( INTVAL ( count ) & ~ ( ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) - 1 ) ) ; destmem = shallow_copy_rtx ( destmem ) ; set_mem_size ( destmem , rounded_count ) ; } else if ( MEM_SIZE_KNOWN_P ( destmem ) ) clear_mem_size ( destmem ) ; if ( issetmem ) { value = force_reg ( mode , gen_lowpart ( mode , value ) ) ; emit_insn ( gen_rep_stos ( destptr , countreg , destmem , value , destexp ) ) ; } else { if ( srcptr != XEXP ( srcmem , 0 ) || GET_MODE ( srcmem ) != BLKmode ) srcmem = adjust_automodify_address_nv ( srcmem , BLKmode , srcptr , 0 ) ; if ( mode != QImode ) { srcexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; srcexp = gen_rtx_PLUS ( Pmode , srcexp , srcptr ) ; } else srcexp = gen_rtx_PLUS ( Pmode , srcptr , countreg ) ; if ( CONST_INT_P ( count ) ) { rounded_count = ( INTVAL ( count ) & ~ ( ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) - 1 ) ) ; srcmem = shallow_copy_rtx ( srcmem ) ; set_mem_size ( srcmem , rounded_count ) ; } else { if ( MEM_SIZE_KNOWN_P ( srcmem ) ) clear_mem_size ( srcmem ) ; } emit_insn ( gen_rep_mov ( destptr , destmem , srcptr , srcmem , countreg , destexp , srcexp ) ) ; } } </s>

Output `` rep ; mov '' or `` rep ; stos '' instruction depending on ISSETMEM argument . When ISSETMEM is true , arguments SRCMEM and SRCPTR are ignored . When ISSETMEM is false , arguments VALUE and ORIG_VALUE are ignored . For setmem case , VALUE is a promoted to a wider size ORIG_VALUE . ORIG_VALUE is the original value passed to memset to fill the memory with . Other arguments have same meaning as for previous function .


<s> static inline unsigned long ia64_rse_num_regs ( unsigned long * bspstore , unsigned long * bsp ) { unsigned long slots = ( bsp - bspstore ) ; return slots - ( ia64_rse_slot_num ( bspstore ) + slots ) / 0x40 ; } </s>

Calculate the number of registers in the dirty partition starting at BSPSTORE with a size of DIRTY bytes . This is n't simply DIRTY divided by eight because the 64th slot is used to store ar.rnat .


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMicroMipsSizeReductionPass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsHazardSchedule ( ) ) ; addPass ( createMipsLongBranchPass ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
const
MCFixupKindInfo
&
X86AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_relax_rex"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
32
,
0
}
,
{
"reloc_signed_4byte_relax"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
32
,
0
}
,
{
"reloc_global_offset_table8"
,
0
,
64
,
0
}
,
{
"reloc_branch_4byte_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
assert
(
Infos
[
Kind
FirstTargetFixupKind
]
.
Name
&&
"Empty fixup name!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"MIPS Os16 Optimization"
;
}
</s>


<s> static HOST_WIDE_INT mmix_static_rtx_alignment ( machine_mode mode ) { return MAX ( GET_MODE_ALIGNMENT ( mode ) , 32 ) ; } </s>


<s>
unsigned
Mips16InstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BeqzRxImmX16
:
return
Mips
::
BnezRxImmX16
;
case
Mips
::
BnezRxImmX16
:
return
Mips
::
BeqzRxImmX16
;
case
Mips
::
BeqzRxImm16
:
return
Mips
::
BnezRxImm16
;
case
Mips
::
BnezRxImm16
:
return
Mips
::
BeqzRxImm16
;
case
Mips
::
BteqzT8CmpX16
:
return
Mips
::
BtnezT8CmpX16
;
case
Mips
::
BteqzT8SltX16
:
return
Mips
::
BtnezT8SltX16
;
case
Mips
::
BteqzT8SltiX16
:
return
Mips
::
BtnezT8SltiX16
;
case
Mips
::
Btnez16
:
return
Mips
::
Bteqz16
;
case
Mips
::
BtnezX16
:
return
Mips
::
BteqzX16
;
case
Mips
::
BtnezT8CmpiX16
:
return
Mips
::
BteqzT8CmpiX16
;
case
Mips
::
BtnezT8SltuX16
:
return
Mips
::
BteqzT8SltuX16
;
case
Mips
::
BtnezT8SltiuX16
:
return
Mips
::
BteqzT8SltiuX16
;
case
Mips
::
Bteqz16
:
return
Mips
::
Btnez16
;
case
Mips
::
BteqzX16
:
return
Mips
::
BtnezX16
;
case
Mips
::
BteqzT8CmpiX16
:
return
Mips
::
BtnezT8CmpiX16
;
case
Mips
::
BteqzT8SltuX16
:
return
Mips
::
BtnezT8SltuX16
;
case
Mips
::
BteqzT8SltiuX16
:
return
Mips
::
BtnezT8SltiuX16
;
case
Mips
::
BtnezT8CmpX16
:
return
Mips
::
BteqzT8CmpX16
;
case
Mips
::
BtnezT8SltX16
:
return
Mips
::
BteqzT8SltX16
;
case
Mips
::
BtnezT8SltiX16
:
return
Mips
::
BteqzT8SltiX16
;
}
assert
(
false
&&
"Implement this function."
)
;
return
0
;
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + 1 , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] , Regs ) ; } ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AZPR Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
SystemZInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32rm
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32rm
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64rm
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Prm
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128rm
;
}
else
llvm_unreachable
(
"Unsupported regclass to load"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
,
FrameIdx
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s>
void
SystemZPostRASchedStrategy
::
schedNode
(
SUnit
*
SU
,
bool
IsTopNode
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Scheduling SU("
<<
SU
->
NodeNum
<<
")\n"
;
)
;
Available
.
erase
(
SU
)
;
HazardRec
.
EmitInstruction
(
SU
)
;
}
</s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .

SystemZ
SystemZ
"+++ Scheduling SU("
")\n"


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> isTargetNaCl ( ) && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void ix86_emit_i387_cosh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx half = const_double_from_real_value ( dconsthalf , XFmode ) ; rtx cst1 ; emit_insn ( gen_expxf2 ( e1 , op1 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_divxf3 ( e2 , cst1 , e1 ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , e2 ) ) ; half = force_reg ( XFmode , half ) ; emit_insn ( gen_mulxf3 ( op0 , e2 , half ) ) ; } </s>

Output code to perform an cosh XFmode calculation .


<s> bool sh2a_is_function_vector_call ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { tree tr = SYMBOL_REF_DECL ( x ) ; if ( sh2a_function_vector_p ( tr ) ) return true ; } return false ; } </s>

Returns true if current function has been assigned the attribute 'function_vector ' .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::ATOMIC_FENCE
ISD::BlockAddress
ISD::ConstantPool
ISD::DYNAMIC_STACKALLOC
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::LOAD
ISD::STORE
ISD::VASTART
ISD::VAARG


<s> static bool r10k_needs_protection_p ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) return r10k_needs_protection_p_call ( PATTERN ( insn ) ) ; if ( mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE ) { note_stores ( insn , r10k_needs_protection_p_store , & insn ) ; return insn == NULL_RTX ; } return r10k_needs_protection_p_1 ( PATTERN ( insn ) , insn ) ; } </s>

Return true if instruction INSN needs to be protected by an R10K cache barrier .


<s>
void
AArch64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
,
Mnemonic
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
AArch64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
STI
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
AArch64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
const
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
STI
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
AArch64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
AArch64InstPrinter
::
printInst
(
MI
,
O
,
Annot
,
STI
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .