<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( GV && ! GV -> hasInternalLinkage ( ) && ! GV -> hasPrivateLinkage ( ) ) { if ( ! dyn_cast_or_null < Function > ( GV ) && ! GV -> isThreadDependent ( ) && ! GV -> isThreadLocal ( ) ) { return X86II :: MO_DLLIMPORT ; } } if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( isOSWindows ( ) ) return X86II :: MO_NO_FLAG ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> TargetTransformInfo SystemZTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( SystemZTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> const PPCInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( MIB ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri 0


<s>
static
rtx
mips_expand_builtin_msa_test_branch
(
enum
insn_code
icode
,
tree
exp
)
{
struct
expand_operand
ops
[
3
]
;
rtx_insn
*
cbranch
;
rtx_code_label
*
true_label
,
*
done_label
;
rtx
cmp_result
;
true_label
=
gen_label_rtx
(
)
;
done_label
=
gen_label_rtx
(
)
;
create_input_operand
(
&
ops
[
0
]
,
true_label
,
TYPE_MODE
(
TREE_TYPE
(
exp
)
)
)
;
mips_prepare_builtin_arg
(
&
ops
[
1
]
,
exp
,
0
)
;
create_fixed_operand
(
&
ops
[
2
]
,
const0_rtx
)
;
if
(
GET_CODE
(
ops
[
1
]
.
value
)
!=
REG
)
ops
[
1
]
.
value
=
force_reg
(
ops
[
1
]
.
mode
,
ops
[
1
]
.
value
)
;
if
(
(
cbranch
=
maybe_gen_insn
(
icode
,
3
,
ops
)
)
==
NULL_RTX
)
error
(
"failed to expand built-in function"
)
;
cmp_result
=
gen_reg_rtx
(
SImode
)
;
mips_emit_move
(
cmp_result
,
const0_rtx
)
;
emit_jump_insn
(
cbranch
)
;
emit_jump_insn
(
gen_jump
(
done_label
)
)
;
emit_barrier
(
)
;
emit_label
(
true_label
)
;
mips_emit_move
(
cmp_result
,
const1_rtx
)
;
emit_label
(
done_label
)
;
return
cmp_result
;
}
</s>

Expand an MSA built-in for a compare and branch instruction specified by ICODE , set a general-purpose register to 1 if the branch was taken , 0 otherwise .


<s> virtual EVT getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static void ix86_find_max_used_stack_alignment ( unsigned int & stack_alignment , bool check_stack_slot ) { HARD_REG_SET set_up_by_prologue , prologue_used ; basic_block bb ; CLEAR_HARD_REG_SET ( prologue_used ) ; CLEAR_HARD_REG_SET ( set_up_by_prologue ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , STACK_POINTER_REGNUM ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , ARG_POINTER_REGNUM ) ; add_to_hard_reg_set ( & set_up_by_prologue , Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( stack_alignment > crtl -> preferred_stack_boundary ) stack_alignment = crtl -> preferred_stack_boundary ; bool require_stack_frame = false ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) && requires_stack_frame_p ( insn , prologue_used , set_up_by_prologue ) ) { require_stack_frame = true ; if ( check_stack_slot ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) if ( MEM_P ( * iter ) && ( reg_mentioned_p ( stack_pointer_rtx , * iter ) || reg_mentioned_p ( frame_pointer_rtx , * iter ) ) ) { unsigned int alignment = MEM_ALIGN ( * iter ) ; if ( alignment > stack_alignment ) stack_alignment = alignment ; } } } } cfun -> machine -> stack_frame_required = require_stack_frame ; } </s>

Return true if stack frame is required . Update STACK_ALIGNMENT to the largest alignment , in bits , of stack slot used if stack frame is required and CHECK_STACK_SLOT is true .


"prioritized sinit and sterm functions are not yet supported on AIX"

This method emits llvm.global_ctors or llvm.global_dtors list .


<s> void AArch64AsmPrinter :: emitJumpTableInfo ( ) { const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; if ( ! MJTI ) return ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( MF -> getFunction ( ) , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; auto AFI = MF -> getInfo < AArch64FunctionInfo > ( ) ; for ( unsigned JTI = 0 , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; emitAlignment ( Align ( Size ) ) ; OutStreamer -> emitLabel ( GetJTISymbol ( JTI ) ) ; const MCSymbol * BaseSym = AArch64FI -> getJumpTableEntryPCRelSymbol ( JTI ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( BaseSym , OutContext ) ; for ( auto * JTBB : JTBBs ) { const MCExpr * Value = MCSymbolRefExpr :: create ( JTBB -> getSymbol ( ) , OutContext ) ; Value = MCBinaryExpr :: createSub ( Value , Base , OutContext ) ; if ( Size != 4 ) Value = MCBinaryExpr :: createLShr ( Value , MCConstantExpr :: create ( 2 , OutContext ) , OutContext ) ; OutStreamer -> emitValue ( Value , Size ) ; } } } </s>

Print assembly representations of the jump tables used by the current function to the current output stream .


<s> bool n10_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_PBSAD : case TYPE_MUL : case TYPE_DALU : case TYPE_DALU64 : case TYPE_DMUL : case TYPE_DPACK : case TYPE_DINSB : case TYPE_DCMP : case TYPE_DCLIP : case TYPE_DALUROUND : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : case TYPE_DMAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_DWEXT : return wext_odd_dep_p ( consumer , def_reg ) ; case TYPE_DBPICK : return bpick_ra_rb_dep_p ( consumer , def_reg ) ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> Sched :: Preference PPCTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned Directive = PPCSubTarget . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 ) return Sched :: ILP ; return TargetLowering :: getSchedulingPreference ( N ) ; } </s>


<s> bool AArch64TTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : Info . ReadMem = true ; Info . WriteMem = false ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; break ; case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : Info . ReadMem = false ; Info . WriteMem = true ; Info . PtrVal = Inst -> getArgOperand ( Inst -> getNumArgOperands ( ) - 1 ) ; break ; } switch ( Inst -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_st2 : Info . MatchingId = VECTOR_LDST_TWO_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_st3 : Info . MatchingId = VECTOR_LDST_THREE_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_st4 : Info . MatchingId = VECTOR_LDST_FOUR_ELEMENTS ; break ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static bool mayAlias ( MachineInstr & MIa , SmallVectorImpl < MachineInstr * > & MemInsns , AliasAnalysis * AA ) { for ( MachineInstr * MIb : MemInsns ) if ( mayAlias ( MIa , * MIb , AA ) ) return true ; return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


Implement TARGET_BUILD_BUILTIN_VA_LIST . Return the type to use as __builtin_va_list . AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as : struct __va_list { void * __stack ; void * __gr_top ; void * __vr_top ; int __gr_offs ; int __vr_offs ; } ;


"Register sequence is not valid. 'r4-r7' expected"

Process a single instruction and collect debug info anchors .


Return true if the vector misalignment factor is supported by the target .


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , const BranchProbability & Probability ) const { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & ARM :: CCRRegClass ) return nullptr ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s>
static
void
recombine_stvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
MEM_P
(
SET_DEST
(
body
)
)
&&
(
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
||
pattern_is_rotate64
(
body
)
)
)
;
rtx
mem
=
SET_DEST
(
body
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
auto_vec
<
rtx_insn
*
>
and_insns
;
auto_vec
<
rtx
>
and_ops
;
bool
is_any_def_and
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insns
,
&
and_ops
)
;
if
(
is_any_def_and
)
{
gcc_assert
(
and_insns
.
length
(
)
==
and_ops
.
length
(
)
)
;
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
df_ref
src_use
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_USE
(
src_use
,
insn_info
)
{
if
(
!
rtx_equal_p
(
DF_REF_REG
(
src_use
)
,
src_reg
)
)
continue
;
struct
df_link
*
link
=
DF_REF_CHAIN
(
src_use
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
new_reg
=
0
;
rtx
and_mask
=
0
;
for
(
unsigned
i
=
0
;
i
<
and_insns
.
length
(
)
;
i
++
)
{
rtx_insn
*
and_insn
=
and_insns
[
i
]
;
rtx
and_op
=
and_ops
[
i
]
;
rtx
and_base
=
XEXP
(
and_op
,
0
)
;
if
(
!
new_reg
)
{
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
and_mask
=
XEXP
(
and_op
,
1
)
;
}
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
}
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
new_reg
)
,
new_reg
,
and_mask
)
;
SET_SRC
(
body
)
=
src_reg
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"stvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the store for an stvx pattern , put it in canonical form .


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


<s> unsigned X86InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Dummy ; if ( isFrameLoadOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ; this -> TM = & static_cast < const MipsTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> unsigned SparcInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { SparcMachineFunctionInfo * SparcFI = MF -> getInfo < SparcMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = SparcFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * PtrRC = Subtarget . is64Bit ( ) ? & SP :: I64RegsRegClass : & SP :: IntRegsRegClass ; GlobalBaseReg = RegInfo . createVirtualRegister ( PtrRC ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( SP :: GETPCX ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Sparc Sparc Sparc Sparc Sparc Sparc 0 SP::I64RegsRegClass SP::IntRegsRegClass SP::GETPCX Sparc


"Handling of TOC entry displacement larger than 32767 "

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> static tree ix86_d_handle_target_object_format ( void ) { const char * objfmt = NULL ; if ( TARGET_MACHO ) objfmt = "macho" ; else if ( TARGET_COFF || TARGET_PECOFF ) objfmt = "coff" ; if ( objfmt == NULL ) return NULL_TREE ; return build_string_literal ( strlen ( objfmt ) + 1 , objfmt ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` objectFormat '' ) ' .


<s>
bool
PPCCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
,
Register
SwiftErrorVReg
)
const
{
assert
(
(
(
Val
&&
!
VRegs
.
empty
(
)
)
||
(
!
Val
&&
VRegs
.
empty
(
)
)
)
&&
"Return value without a vreg"
)
;
if
(
VRegs
.
size
(
)
>
0
)
return
false
;
MIRBuilder
.
buildInstr
(
PPC
::
BLR8
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static unsigned int mips16e_collect_argument_saves ( void ) { rtx reg_values [ FIRST_PSEUDO_REGISTER ] ; rtx_insn * insn , * next ; rtx set , dest , src ; unsigned int nargs , regno ; push_topmost_sequence ( ) ; nargs = 0 ; memset ( reg_values , 0 , sizeof ( reg_values ) ) ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( NOTE_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; if ( ! INSN_P ( insn ) ) break ; set = PATTERN ( insn ) ; if ( GET_CODE ( set ) != SET ) break ; dest = SET_DEST ( set ) ; src = SET_SRC ( set ) ; if ( mips16e_collect_argument_save_p ( dest , src , reg_values , & regno ) ) { if ( ! BITSET_P ( cfun -> machine -> frame . mask , regno ) ) { delete_insn ( insn ) ; nargs = MAX ( nargs , ( regno - GP_ARG_FIRST ) + 1 ) ; } } else if ( REG_P ( dest ) && GET_MODE ( dest ) == word_mode ) reg_values [ REGNO ( dest ) ] = mips16e_collect_propagate_value ( src , reg_values ) ; else break ; } pop_topmost_sequence ( ) ; return nargs ; } </s>

A subroutine of mips_expand_prologue , called only when generating MIPS16e SAVE instructions . Search the start of the function for any instructions that save argument registers into their caller-allocated save slots . Delete such instructions and return a value N such that saving [ GP_ARG_FIRST , GP_ARG_FIRST + N ) would make all the deleted instructions redundant .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroName = ( V && V -> isNullValue ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( bzeroName ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> bool PPCTTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getCPUDirective ( ) == PPC :: DIR_A2 ) return true ; return LoopHasReductions ; } </s>

Do n't restrict interleaved unrolling to small loops .


<s> const char * pru_output_signed_cbranch ( rtx * operands , bool is_near ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; if ( code == LT || code == LE ) return pru_output_ltle_signed_cbranch ( operands , is_near ) ; else if ( code == GT || code == GE ) return pru_output_gtge_signed_cbranch ( operands , is_near ) ; else gcc_unreachable ( ) ; } </s>

Output asm code for a signed-compare conditional branch . If IS_NEAR is true , then QBBx instructions may be used for reaching the destination label . Otherwise JMP is used , at the expense of increased code size .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < AArch64Subtarget > ( ) . isTargetMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
const
char
*
emit_fusion_gpr_load
(
rtx
target
,
rtx
mem
)
{
rtx
addis_value
;
rtx
addr
;
rtx
load_offset
;
const
char
*
load_str
=
;
machine_mode
mode
;
if
(
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
mem
=
XEXP
(
mem
,
0
)
;
gcc_assert
(
REG_P
(
target
)
&&
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
addis_value
,
&
load_offset
)
;
mode
=
GET_MODE
(
mem
)
;
switch
(
mode
)
{
case
E_QImode
:
load_str
=
"lbz"
;
break
;
case
E_HImode
:
load_str
=
"lhz"
;
break
;
case
E_SImode
:
case
E_SFmode
:
load_str
=
"lwz"
;
break
;
case
E_DImode
:
case
E_DFmode
:
gcc_assert
(
TARGET_POWERPC64
)
;
load_str
=
"ld"
;
break
;
default
:
fatal_insn
(
"Bad GPR fusion"
,
gen_rtx_SET
(
target
,
mem
)
)
;
}
emit_fusion_addis
(
target
,
addis_value
)
;
emit_fusion_load_store
(
target
,
target
,
load_offset
,
load_str
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a gpr load to the same register that we loaded up the addis instruction . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"lbz"
"lhz"
"lwz"
"ld"
"Bad GPR fusion"
""


<s> bool KudeyarDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; return Ret ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & F ) override { ARM64FI = F . getInfo < ARM64FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction ( F ) ; } </s>


<s> rtx ix86_force_to_memory ( enum machine_mode mode , rtx operand ) { rtx result ; gcc_assert ( reload_completed ) ; if ( TARGET_RED_ZONE ) { result = gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - RED_ZONE_SIZE ) ) ) ; emit_move_insn ( result , operand ) ; } else if ( ! TARGET_RED_ZONE && TARGET_64BIT ) { switch ( mode ) { case HImode : case SImode : operand = gen_lowpart ( DImode , operand ) ; case DImode : emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( DImode , gen_rtx_PRE_DEC ( DImode , stack_pointer_rtx ) ) , operand ) ) ; break ; default : gcc_unreachable ( ) ; } result = gen_rtx_MEM ( mode , stack_pointer_rtx ) ; } else { switch ( mode ) { case DImode : { rtx operands [ 2 ] ; split_di ( & operand , 1 , operands , operands + 1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , operands [ 1 ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , operands [ 0 ] ) ) ; } break ; case HImode : operand = gen_lowpart ( SImode , operand ) ; case SImode : emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( GET_MODE ( operand ) , gen_rtx_PRE_DEC ( SImode , stack_pointer_rtx ) ) , operand ) ) ; break ; default : gcc_unreachable ( ) ; } result = gen_rtx_MEM ( mode , stack_pointer_rtx ) ; } return result ; } </s>

Store OPERAND to the memory after reload is completed . This means that we ca n't easily use assign_stack_local .


"Unable to build a return instruction?!"

"The insertion did not happen where we expected"


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchRangeToICmp ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; if ( TM -> Options . JMCInstrument ) addPass ( createJMCInstrumenterPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static int ix86_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) nregs ++ ; return nregs ; } </s>

Return number of registers to be saved on the stack .


<s> static void do_ifelse ( machine_mode cmpmode , rtx_code comparison , rtx a , rtx b , rtx cr , rtx true_label ) { gcc_assert ( ( a == NULL_RTX && b == NULL_RTX && cr != NULL_RTX ) || ( a != NULL_RTX && b != NULL_RTX ) ) ; if ( cr != NULL_RTX ) gcc_assert ( GET_MODE ( cr ) == cmpmode ) ; else cr = gen_reg_rtx ( cmpmode ) ; rtx label_ref = gen_rtx_LABEL_REF ( VOIDmode , true_label ) ; if ( a != NULL_RTX ) emit_move_insn ( cr , gen_rtx_COMPARE ( cmpmode , a , b ) ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( comparison , VOIDmode , cr , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , label_ref , pc_rtx ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = true_label ; LABEL_NUSES ( true_label ) += 1 ; } </s>

Do a branch for an if/else decision . CMPMODE is the mode to use for the comparison . COMPARISON is the rtx code for the compare needed . A is the first thing to be compared . B is the second thing to be compared . CR is the condition code reg input , or NULL_RTX . TRUE_LABEL is the label to branch to if the condition is true . The return value is the CR used for the comparison . If CR is null_rtx , then a new register of CMPMODE is generated . If A and B are both null_rtx , then CR must not be null , and the compare is not generated so you can use this with a dot form insn .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
PLI
:
case
PPC
::
PLI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
XXSPLTI32DX
:
case
PPC
::
XXSPLTIW
:
case
PPC
::
XXSPLTIDP
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
case
PPC
::
XXSETACCZ
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


"instruction requires a CPU feature not currently enabled"

"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void mips_split_msa_copy_d ( rtx dest , rtx src , rtx index , rtx ( * gen_fn ) ( rtx , rtx , rtx ) ) { gcc_assert ( ( GET_MODE ( src ) == V2DImode && GET_MODE ( dest ) == DImode ) || ( GET_MODE ( src ) == V2DFmode && GET_MODE ( dest ) == DFmode ) ) ; rtx low = mips_subword ( dest , false ) ; rtx high = mips_subword ( dest , true ) ; rtx new_src = simplify_gen_subreg ( V4SImode , src , GET_MODE ( src ) , 0 ) ; emit_insn ( gen_fn ( low , new_src , GEN_INT ( INTVAL ( index ) * 2 ) ) ) ; emit_insn ( gen_fn ( high , new_src , GEN_INT ( INTVAL ( index ) * 2 + 1 ) ) ) ; } </s>

Split a COPY_S.D with operands DEST , SRC and INDEX . GEN is a function used to generate subregs .


<s> rtx_insn * sh_peephole_emit_move_insn ( rtx dst , rtx src ) { return sh_check_add_incdec_notes ( emit_move_insn ( dst , sh_remove_overlapping_post_inc ( dst , src ) ) ) ; } </s>

Emit a move insn that is safe to be used in peephole patterns .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return nullptr ; return STI . isTargetDarwin ( ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; TM = & TPC -> getTM < PPCTargetMachine > ( ) ; STI = TM -> getSubtargetImpl ( F ) ; TLI = STI -> getTargetLowering ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool mips_store_data_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { if ( GET_CODE ( PATTERN ( in_insn ) ) == UNSPEC_VOLATILE ) return false ; return store_data_bypass_p ( out_insn , in_insn ) ; } </s>

True if the dependency between OUT_INSN and IN_INSN is on the store data rather than the address . We need this because the cprestore pattern is type `` store '' , but is defined using an UNSPEC_VOLATILE , which causes the default routine to abort . We just return false for that case .


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( ! EnableX86LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { SmallVector < MachineInstr * , 16 > LEAs ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


"  Skipping pass: no machine model present.\n"


Return the output template for emitting a dbra type insn . Note it may perform some output operations on its own before returning the final output string .


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret ; } </s>


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
{
++
I
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
*
MI
;
)
;
unsigned
OutReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
const
unsigned
OrigRegs
[
]
=
{
OutReg
,
InReg
,
GPR3
}
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKDOWN
)
)
.
addImm
(
0
)
;
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
->
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
->
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKUP
)
)
.
addImm
(
0
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
->
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> void X86RegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { return applyDefaultMapping ( OpdMapper ) ; } </s>


<s> static void mips_reorg ( void ) { if ( mips_cfg_in_reorg ( ) ) compute_bb_for_insn ( ) ; mips16_lay_out_constants ( true ) ; if ( mips_cfg_in_reorg ( ) ) { mips_df_reorg ( ) ; free_bb_for_insn ( ) ; } } </s>


<s> bool LSRWithInstrQueries ( ) { return true ; } </s>

Return true if the loop strength reduce pass should make Instruction * based TTI queries to isLegalAddressingMode ( ) .


<s> MCObjectWriter * OR1KAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createOR1KELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new ARMHazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget , DAG ) ; return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> static bool unspec_caller_rtx_p ( rtx pat ) { rtx base , offset ; int i ; split_const ( pat , & base , & offset ) ; if ( GET_CODE ( base ) == UNSPEC ) { if ( XINT ( base , 1 ) == UNSPEC_CALLER ) return true ; for ( i = 0 ; i < XVECLEN ( base , 0 ) ; i ++ ) if ( unspec_caller_rtx_p ( XVECEXP ( base , 0 , i ) ) ) return true ; } return false ; } </s>

Check if PAT includes UNSPEC_CALLER unspec pattern .


<s> ISD :: NodeType getExtendForAtomicOps ( ) const override { return ISD :: SIGN_EXTEND ; } </s>

Returns how the platform 's atomic operations are extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


"OR1K DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> unsigned SparcInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { SparcMachineFunctionInfo * SparcFI = MF -> getInfo < SparcMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = SparcFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & SP :: IntRegsRegClass ) ; DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; BuildMI ( FirstMBB , MBBI , dl , get ( SP :: GETPCX ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Sparc Sparc Sparc Sparc Sparc Sparc 0 SP::IntRegsRegClass SP::GETPCX Sparc


<s> static rtx ix86_delegitimize_address ( rtx x ) { return ix86_delegitimize_address_1 ( x , false ) ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize PIC+GOTOFF and turn it back into a direct symbol reference . On Darwin , this is necessary to avoid a crash , because Darwin has a different PIC label for each routine but the DWARF debugging information is not associated with any particular routine , so it 's necessary to remove references to the PIC label from RTL stored by the DWARF output code .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cheri Addressing Mode Folder"
;
}
</s>


<s> static bool sh_cannot_copy_insn_p ( rtx_insn * insn ) { if ( ! reload_completed || ! flag_pic ) return false ; if ( ! NONJUMP_INSN_P ( insn ) ) return false ; if ( asm_noperands ( insn ) >= 0 ) return false ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == USE ) return false ; if ( TARGET_FDPIC && GET_CODE ( pat ) == PARALLEL ) { rtx t = XVECEXP ( pat , 0 , XVECLEN ( pat , 0 ) - 1 ) ; if ( GET_CODE ( t ) == USE && unspec_caller_rtx_p ( XEXP ( t , 0 ) ) ) return true ; } if ( GET_CODE ( pat ) != SET ) return false ; pat = SET_SRC ( pat ) ; if ( unspec_caller_rtx_p ( pat ) ) return true ; return false ; } </s>

Indicate that INSN can not be duplicated . This is true for insn that generates a unique label .


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) || AArch64InstrInfo :: isPreLdSt ( MI ) ? 2 : 1 ; return MI . getOperand ( Idx ) ; } </s>

Returns the base register operator of a load/store .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case 'x' : case 'C' : return C_RegisterClass ; case 'R' : return C_Memory ; } } if ( Constraint == "ZC" ) return C_Memory ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> int PPCTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCostInst ( Opcode , Idx , Imm , Ty , CostKind , Inst ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s>
const
char
*
nds32_output_16bit_store
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
char
size
;
rtx
code
=
XEXP
(
operands
[
0
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
nds32_mem_format
(
operands
[
0
]
)
)
{
case
ADDRESS_REG
:
operands
[
0
]
=
code
;
output_asm_insn
(
"swi450\t%1, [%0]"
,
operands
)
;
break
;
case
ADDRESS_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci333\t%%1, %%0"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_INC_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"swi333.bi\t%%1, %%0, 4"
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_MODIFY_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"swi333.bi\t%%1, %%0"
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_FP_IMM7U
:
output_asm_insn
(
"swi37\t%1, %0"
,
operands
)
;
break
;
case
ADDRESS_SP_IMM7U
:
operands
[
0
]
=
XEXP
(
code
,
1
)
;
output_asm_insn
(
"swi37.sp\t%1, [ + (%0)]"
,
operands
)
;
break
;
default
:
break
;
}
return
""
;
}
</s>


<s> static HOST_WIDE_INT arm_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { unsigned int factor = ( TARGET_THUMB || ! arm_tune_xscale ? 1 : 2 ) ; if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size ) return MAX ( align , BITS_PER_WORD * factor ) ; return align ; } </s>

Implement TARGET_CONSTANT_ALIGNMENT . Make strings word-aligned so strcpy from constants will be faster .


<s> Triple :: ObjectFormatType getFormat ( ) const override { return Triple :: Hex ; } </s>


<s> static int aarch64_sched_issue_rate ( void ) { return aarch64_tune_params -> issue_rate ; } </s>

Return the number of instructions that can be issued per cycle .


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case SFmode : case DFmode : if ( ! arm_float_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_float_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


<s> static void assign_fp_registers ( const_tree field , HOST_WIDE_INT bitpos , assign_data_t * data ) { int nregs ; machine_mode mode ; if ( ! compute_fp_layout ( field , bitpos , data , & nregs , & mode ) ) return ; const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; int regno = SPARC_FP_ARG_FIRST + this_slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 && ( bitpos & 32 ) != 0 ) regno ++ ; int pos = bitpos / BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; data -> nregs += 1 ; regno += GET_MODE_SIZE ( mode ) / 4 ; pos += GET_MODE_SIZE ( mode ) ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign FIELD at position BITPOS to FP registers .


<s> static int ix86_initialize_bounds ( tree var , tree lb , tree ub , tree * stmts ) { tree bnd_ptr = build_pointer_type ( pointer_sized_int_node ) ; tree lhs , modify , var_p ; ub = build1 ( BIT_NOT_EXPR , pointer_sized_int_node , ub ) ; var_p = fold_convert ( bnd_ptr , build_fold_addr_expr ( var ) ) ; lhs = build1 ( INDIRECT_REF , pointer_sized_int_node , var_p ) ; modify = build2 ( MODIFY_EXPR , TREE_TYPE ( lhs ) , lhs , lb ) ; append_to_statement_list ( modify , stmts ) ; lhs = build1 ( INDIRECT_REF , pointer_sized_int_node , build2 ( POINTER_PLUS_EXPR , bnd_ptr , var_p , TYPE_SIZE_UNIT ( pointer_sized_int_node ) ) ) ; modify = build2 ( MODIFY_EXPR , TREE_TYPE ( lhs ) , lhs , ub ) ; append_to_statement_list ( modify , stmts ) ; return 2 ; } </s>

Generate a list of statements STMTS to initialize pointer bounds variable VAR with bounds LB and UB . Return the number of generated statements .


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Store Pair Suppression"
;
}
</s>


<s>
void
ARMOperand
::
dump
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
CondCode
:
OS
<<
ARMCondCodeToString
(
getCondCode
(
)
)
;
break
;
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
Memory
:
OS
<<
"<memory>"
;
break
;
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

ARM
ARM
ARM
"<memory>"
"<register "
">"
"'"
"'"


<s>
bool
CAHPInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
CAHP
::
BEQ
:
case
CAHP
::
BNE
:
case
CAHP
::
BLT
:
case
CAHP
::
BLE
:
case
CAHP
::
BLTU
:
case
CAHP
::
BLEU
:
return
isInt
<
10
>
(
BrOffset
)
;
case
CAHP
::
JSAL
:
case
CAHP
::
JS
:
return
isInt
<
11
>
(
BrOffset
)
;
}
}
</s>

Determine if the branch target is in range .

CAHP
CAHP
"Unexpected opcode!"
CAHP::BEQ
CAHP::BNE
CAHP::BLT
CAHP::BLE
CAHP::BLTU
CAHP::BLEU
10
CAHP::JSAL
CAHP::JS
11


<s> bool LC2200InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return false ; } SmallVector < MachineInstr * , 4 > BranchInstrs ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return true ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! getAnalyzableBrOpc ( SecondLastOpc ) ) return true ; } if ( ! SecondLastOpc || ( SecondLastOpc != LC2200 :: JMP && SecondLastOpc != LC2200 :: CMP_JMP && SecondLastOpc != LC2200 :: GOTO ) ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return true ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) { return true ; } TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return false ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return true ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> const MCPhysReg * CJGRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList ; } </s>


<s> enum reg_class xstormy16_preferred_reload_class ( rtx x , enum reg_class class ) { if ( class == GENERAL_REGS && GET_CODE ( x ) == MEM ) return EIGHT_REGS ; return class ; } </s>

Worker function for TARGET_PREFERRED_RELOAD_CLASS and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS .


<s> static void sh_setup_incoming_varargs ( cumulative_args_t ca , machine_mode mode , tree type , int * pretend_arg_size , int second_time ATTRIBUTE_UNUSED ) { gcc_assert ( cfun -> stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs , anon_parm_regs ; named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , mode ) + ( mode == BLKmode ? CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) : CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > 0 ) * pretend_arg_size = anon_parm_regs * 4 ; } } </s>

We actually emit the code in sh_expand_prologue . We used to use a static variable to flag that we need to emit this code , but that does n't when inlining , when functions are deferred and then emitted later . Fortunately , we already have two flags that are part of struct function that tell if a function uses varargs or stdarg .


<s> ScheduleHazardRecognizer :: HazardType ARMBankConflictHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr & L0 = * SU -> getInstr ( ) ; if ( ! L0 . mayLoad ( ) || L0 . mayStore ( ) || L0 . getNumMemOperands ( ) != 1 ) return NoHazard ; auto MO0 = * L0 . memoperands ( ) . begin ( ) ; auto BaseVal0 = MO0 -> getValue ( ) ; auto BasePseudoVal0 = MO0 -> getPseudoValue ( ) ; int64_t Offset0 = 0 ; if ( MO0 -> getSize ( ) > 4 ) return NoHazard ; bool SPvalid = false ; const MachineOperand * SP = nullptr ; int64_t SPOffset0 = 0 ; for ( auto L1 : Accesses ) { auto MO1 = * L1 -> memoperands ( ) . begin ( ) ; auto BaseVal1 = MO1 -> getValue ( ) ; auto BasePseudoVal1 = MO1 -> getPseudoValue ( ) ; int64_t Offset1 = 0 ; if ( BaseVal0 && BaseVal1 ) { const Value * Ptr0 , * Ptr1 ; Ptr0 = GetPointerBaseWithConstantOffset ( BaseVal0 , Offset0 , DL , true ) ; Ptr1 = GetPointerBaseWithConstantOffset ( BaseVal1 , Offset1 , DL , true ) ; if ( Ptr0 == Ptr1 && Ptr0 ) return CheckOffsets ( Offset0 , Offset1 ) ; } if ( BasePseudoVal0 && BasePseudoVal1 && BasePseudoVal0 -> kind ( ) == BasePseudoVal1 -> kind ( ) && BasePseudoVal0 -> kind ( ) == PseudoSourceValue :: FixedStack ) { auto FS0 = cast < FixedStackPseudoSourceValue > ( BasePseudoVal0 ) ; auto FS1 = cast < FixedStackPseudoSourceValue > ( BasePseudoVal1 ) ; Offset0 = MF . getFrameInfo ( ) . getObjectOffset ( FS0 -> getFrameIndex ( ) ) ; Offset1 = MF . getFrameInfo ( ) . getObjectOffset ( FS1 -> getFrameIndex ( ) ) ; return CheckOffsets ( Offset0 , Offset1 ) ; } if ( BasePseudoVal0 && BasePseudoVal1 && BasePseudoVal0 -> kind ( ) == BasePseudoVal1 -> kind ( ) && BasePseudoVal0 -> isConstantPool ( ) && AssumeITCMBankConflict ) return Hazard ; if ( ! SPvalid ) { if ( ! getBaseOffset ( L0 , SP , SPOffset0 ) || SP -> getReg ( ) . id ( ) != ARM :: SP ) SP = nullptr ; SPvalid = true ; } if ( SP ) { int64_t SPOffset1 ; const MachineOperand * SP1 ; if ( getBaseOffset ( * L1 , SP1 , SPOffset1 ) && SP1 -> getReg ( ) . id ( ) == ARM :: SP ) return CheckOffsets ( SPOffset0 , SPOffset1 ) ; } } return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { initialize ( MF ) ; unskipableSimplifyCode ( ) ; if ( skipFunction ( MF . getFunction ( ) ) ) return false ; return simplifyCode ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86FrameInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; bool isWin64 = STI . isTargetWin64 ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == FPReg ) continue ; if ( ! X86 :: VR128RegClass . contains ( Reg ) && ! isWin64 ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> rtx mep_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED ) { if ( TARGET_IVC2 && VECTOR_TYPE_P ( type ) ) return gen_rtx_REG ( TYPE_MODE ( type ) , 48 ) ; return gen_rtx_REG ( TYPE_MODE ( type ) , RETURN_VALUE_REGNUM ) ; } </s>

Implement FUNCTION_VALUE . All values are returned in $ 0 .


Return a string to output before text in the current function . This function is only used with SOM . Because we do n't support named subspaces , we can only create a new subspace or switch back to the default text subspace .


"SPARC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static rtx rs6000_legitimize_tls_address_aix ( rtx addr , enum tls_model model ) { rtx sym , mem , tocref , tlsreg , tmpreg , dest , tlsaddr ; const char * name ; char * tlsname ; name = XSTR ( addr , 0 ) ; if ( name [ strlen ( name ) - 1 ] != ']' && ( TREE_PUBLIC ( SYMBOL_REF_DECL ( addr ) ) || bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ) ) { tlsname = XALLOCAVEC ( char , strlen ( name ) + 4 ) ; strcpy ( tlsname , name ) ; strcat ( tlsname , bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ? "[UL]" : "[TL]" ) ; tlsaddr = copy_rtx ( addr ) ; XSTR ( tlsaddr , 0 ) = ggc_strdup ( tlsname ) ; } else tlsaddr = addr ; sym = force_const_mem ( GET_MODE ( tlsaddr ) , tlsaddr ) ; if ( constant_pool_expr_p ( XEXP ( sym , 0 ) ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( XEXP ( sym , 0 ) ) , Pmode ) ) { tocref = create_TOC_reference ( XEXP ( sym , 0 ) , NULL_RTX ) ; mem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( mem , get_TOC_alias_set ( ) ) ; } else return sym ; if ( model == TLS_MODEL_GLOBAL_DYNAMIC || model == TLS_MODEL_LOCAL_DYNAMIC ) { name = XSTR ( XVECEXP ( XEXP ( mem , 0 ) , 0 , 0 ) , 0 ) ; tlsname = XALLOCAVEC ( char , strlen ( name ) + 1 ) ; strcpy ( tlsname , "*LCM" ) ; strcat ( tlsname , name + 3 ) ; rtx modaddr = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( tlsname ) ) ; SYMBOL_REF_FLAGS ( modaddr ) |= SYMBOL_FLAG_LOCAL ; tocref = create_TOC_reference ( modaddr , NULL_RTX ) ; rtx modmem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( modmem , get_TOC_alias_set ( ) ) ; rtx modreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , modreg , modmem ) ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmpreg , mem ) ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_32BIT ) emit_insn ( gen_tls_get_addrsi ( dest , modreg , tmpreg ) ) ; else emit_insn ( gen_tls_get_addrdi ( dest , modreg , tmpreg ) ) ; return dest ; } else if ( TARGET_32BIT ) { tlsreg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tls_get_tpointer ( tlsreg ) ) ; } else tlsreg = gen_rtx_REG ( DImode , 13 ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmpreg , mem ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_MINUS ( Pmode , addr , tlsreg ) ) ; dest = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , tmpreg , tlsreg ) ) ; return dest ; } </s>


<s> int iq2000_check_split ( rtx address , enum machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) > ( unsigned ) UNITS_PER_WORD ) return 0 ; if ( ( GET_CODE ( address ) == SYMBOL_REF ) || ( GET_CODE ( address ) == CONST && GET_CODE ( XEXP ( XEXP ( address , 0 ) , 0 ) ) == SYMBOL_REF ) || GET_CODE ( address ) == LABEL_REF ) return 1 ; return 0 ; } </s>

Return nonzero if we split the address into high and low parts .


<s>
unsigned
getPointerSize
(
)
const
{
StringRef
Name
=
TheTarget
.
getName
(
)
;
if
(
Name
==
"ppc64"
)
return
8
;
assert
(
Name
==
"ppc32"
&&
"Unknown target name!"
)
;
return
4
;
}
</s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> void sparc_emit_floatunsdi ( rtx * operands , enum machine_mode mode ) { rtx neglab , donelab , i0 , i1 , f0 , in , out ; out = operands [ 0 ] ; in = force_reg ( DImode , operands [ 1 ] ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , DImode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FLOAT ( mode , in ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_lshrdi3 ( i0 , in , const1_rtx ) ) ; emit_insn ( gen_anddi3 ( i1 , in , const1_rtx ) ) ; emit_insn ( gen_iordi3 ( i0 , i0 , i1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f0 , gen_rtx_FLOAT ( mode , i0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { EVT VT = getValueType ( DL , Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; LLVM_FALLTHROUGH ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static bool csky_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return csky_tls_referenced_p ( x ) ; } </s>

Implement TARGET_CANNOT_FORCE_CONST_MEM . Determine if it 's legal to put X into the constant pool . This is not possible for the address of thread-local symbols , which is checked above .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = RoundUpToAlignment ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = RoundUpToAlignment ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return RoundUpToAlignment ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


"' can not be undefined in a subtraction expression"


<s> StringRef X86TargetLowering :: getStackProbeSymbolName ( MachineFunction & MF ) const { if ( hasInlineStackProbe ( MF ) ) return "" ; if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) || MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) return "" ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? "___chkstk_ms" : "__chkstk" ; return Subtarget . isTargetCygMing ( ) ? "_alloca" : "_chkstk" ; } </s>

Returns the name of the symbol used to emit stack probes or the empty string if not applicable .


<s> static void rs6000_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( first + size <= 32768 ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx r0 = gen_rtx_REG ( Pmode , 0 ) ; gcc_assert ( first <= 32768 ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > 32768 ) { emit_move_insn ( r0 , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r0 , gen_rtx_PLUS ( Pmode , r12 , r0 ) ) ) ; } else emit_insn ( gen_rtx_SET ( r0 , plus_constant ( Pmode , r12 , - rounded_size ) ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_probe_stack_rangedi ( r12 , r12 , r0 ) ) ; else emit_insn ( gen_probe_stack_rangesi ( r12 , r12 , r0 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; } } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static void aarch64_update_cpp_builtins ( cpp_reader * pfile ) { aarch64_def_or_undef ( flag_unsafe_math_optimizations , "__ARM_FP_FAST" , pfile ) ; builtin_define_with_int_value ( "__ARM_ARCH" , aarch64_architecture_version ) ; builtin_define_with_int_value ( "__ARM_SIZEOF_MINIMAL_ENUM" , flag_short_enums ? 1 : 4 ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__AARCH64EB__" , pfile ) ; aarch64_def_or_undef ( TARGET_BIG_END , "__ARM_BIG_ENDIAN" , pfile ) ; aarch64_def_or_undef ( ! TARGET_BIG_END , "__AARCH64EL__" , pfile ) ; aarch64_def_or_undef ( TARGET_FLOAT , "__ARM_FEATURE_FMA" , pfile ) ; if ( TARGET_FLOAT || TARGET_SIMD ) { builtin_define_with_int_value ( "__ARM_FP" , 0x0E ) ; builtin_define ( "__ARM_FP16_FORMAT_IEEE" ) ; builtin_define ( "__ARM_FP16_ARGS" ) ; } else cpp_undef ( pfile , "__ARM_FP" ) ; aarch64_def_or_undef ( TARGET_FP_F16INST , "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_F16INST , "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_FEATURE_NUMERIC_MAXMIN" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD , "__ARM_NEON" , pfile ) ; aarch64_def_or_undef ( TARGET_CRC32 , "__ARM_FEATURE_CRC32" , pfile ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_TINY__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_SMALL__" ) ; cpp_undef ( pfile , "__AARCH64_CMODEL_LARGE__" ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : builtin_define ( "__AARCH64_CMODEL_TINY__" ) ; break ; case AARCH64_CMODEL_SMALL : case AARCH64_CMODEL_SMALL_PIC : builtin_define ( "__AARCH64_CMODEL_SMALL__" ) ; break ; case AARCH64_CMODEL_LARGE : builtin_define ( "__AARCH64_CMODEL_LARGE__" ) ; break ; default : break ; } aarch64_def_or_undef ( TARGET_ILP32 , "_ILP32" , pfile ) ; aarch64_def_or_undef ( TARGET_ILP32 , "__ILP32__" , pfile ) ; aarch64_def_or_undef ( TARGET_CRYPTO , "__ARM_FEATURE_CRYPTO" , pfile ) ; aarch64_def_or_undef ( TARGET_SIMD_RDMA , "__ARM_FEATURE_QRDMX" , pfile ) ; cpp_undef ( pfile , "__FLT_EVAL_METHOD__" ) ; builtin_define_with_int_value ( "__FLT_EVAL_METHOD__" , c_flt_eval_method ( true ) ) ; cpp_undef ( pfile , "__FLT_EVAL_METHOD_C99__" ) ; builtin_define_with_int_value ( "__FLT_EVAL_METHOD_C99__" , c_flt_eval_method ( false ) ) ; } </s>

Undefine/redefine macros that depend on the current backend state and may need to change when a target pragma modifies the backend state .


<s> FastISel * X86 :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new X86FastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool X86TargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { APInt MulC ; if ( ! ISD :: isConstantSplatVector ( C . getNode ( ) , MulC ) ) return false ; while ( getTypeAction ( Context , VT ) != TypeLegal ) VT = getTypeToTransformTo ( Context , VT ) ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; if ( isOperationLegal ( ISD :: MUL , VT ) && EltSizeInBits <= 32 && ( EltSizeInBits != 32 || ! Subtarget . isPMULLDSlow ( ) ) ) return false ; return ( MulC + 1 ) . isPowerOf2 ( ) || ( MulC - 1 ) . isPowerOf2 ( ) || ( 1 - MulC ) . isPowerOf2 ( ) || ( - ( MulC + 1 ) ) . isPowerOf2 ( ) ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) || Tail -> isBranch ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } Register PredReg ; ARMCC :: CondCodes CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugInstr ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int pad_groups ( FILE * dump , int sched_verbose , rtx_insn * prev_head_insn , rtx_insn * tail ) { rtx_insn * insn , * next_insn ; rtx nop ; int issue_rate ; int can_issue_more ; int group_end ; int group_count = 0 ; issue_rate = rs6000_issue_rate ( ) ; can_issue_more = issue_rate ; insn = get_next_active_insn ( prev_head_insn , tail ) ; next_insn = get_next_active_insn ( insn , tail ) ; while ( insn != NULL_RTX ) { can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; group_end = ( next_insn == NULL_RTX || GET_MODE ( next_insn ) == TImode ) ; if ( next_insn == NULL_RTX ) break ; if ( group_end ) { if ( can_issue_more && ( rs6000_sched_insert_nops == sched_finish_pad_groups ) && ! insn_terminates_group_p ( insn , current_group ) && ! insn_terminates_group_p ( next_insn , previous_group ) ) { if ( ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; while ( can_issue_more ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } } can_issue_more = issue_rate ; group_count ++ ; } insn = next_insn ; next_insn = get_next_active_insn ( insn , tail ) ; } return group_count ; } </s>

Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the dispatch group boundaries that the scheduler had marked . Pad with nops any dispatch groups which have vacant issue slots , in order to force the scheduler 's grouping on the processor dispatcher . The function returns the number of dispatch groups found .


Set up the AsmPrinter when we are working on a new module .


<s> static bool spe_func_has_64bit_regs_p ( void ) { rtx insns , insn ; if ( current_function_calls_eh_return || current_function_calls_setjmp || current_function_has_nonlocal_goto ) return true ; insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { enum machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && mode == DFmode ) return true ; } } } return false ; } </s>

Return true if the current function uses any GPRs in 64-bit SIMD mode .


<s>
Sparc
::
Fixups
SparcMCExpr
::
getFixupKind
(
SparcMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Unhandled SparcMCExpr::VariantKind"
)
;
case
VK_Sparc_LO
:
return
Sparc
::
fixup_sparc_lo10
;
case
VK_Sparc_HI
:
return
Sparc
::
fixup_sparc_hi22
;
case
VK_Sparc_H44
:
return
Sparc
::
fixup_sparc_h44
;
case
VK_Sparc_M44
:
return
Sparc
::
fixup_sparc_m44
;
case
VK_Sparc_L44
:
return
Sparc
::
fixup_sparc_l44
;
case
VK_Sparc_HH
:
return
Sparc
::
fixup_sparc_hh
;
case
VK_Sparc_HM
:
return
Sparc
::
fixup_sparc_hm
;
case
VK_Sparc_PC22
:
return
Sparc
::
fixup_sparc_pc22
;
case
VK_Sparc_PC10
:
return
Sparc
::
fixup_sparc_pc10
;
case
VK_Sparc_GOT22
:
return
Sparc
::
fixup_sparc_got22
;
case
VK_Sparc_GOT10
:
return
Sparc
::
fixup_sparc_got10
;
case
VK_Sparc_GOT13
:
return
Sparc
::
fixup_sparc_got13
;
case
VK_Sparc_13
:
return
Sparc
::
fixup_sparc_13
;
case
VK_Sparc_WPLT30
:
return
Sparc
::
fixup_sparc_wplt30
;
case
VK_Sparc_WDISP30
:
return
Sparc
::
fixup_sparc_call30
;
case
VK_Sparc_TLS_GD_HI22
:
return
Sparc
::
fixup_sparc_tls_gd_hi22
;
case
VK_Sparc_TLS_GD_LO10
:
return
Sparc
::
fixup_sparc_tls_gd_lo10
;
case
VK_Sparc_TLS_GD_ADD
:
return
Sparc
::
fixup_sparc_tls_gd_add
;
case
VK_Sparc_TLS_GD_CALL
:
return
Sparc
::
fixup_sparc_tls_gd_call
;
case
VK_Sparc_TLS_LDM_HI22
:
return
Sparc
::
fixup_sparc_tls_ldm_hi22
;
case
VK_Sparc_TLS_LDM_LO10
:
return
Sparc
::
fixup_sparc_tls_ldm_lo10
;
case
VK_Sparc_TLS_LDM_ADD
:
return
Sparc
::
fixup_sparc_tls_ldm_add
;
case
VK_Sparc_TLS_LDM_CALL
:
return
Sparc
::
fixup_sparc_tls_ldm_call
;
case
VK_Sparc_TLS_LDO_HIX22
:
return
Sparc
::
fixup_sparc_tls_ldo_hix22
;
case
VK_Sparc_TLS_LDO_LOX10
:
return
Sparc
::
fixup_sparc_tls_ldo_lox10
;
case
VK_Sparc_TLS_LDO_ADD
:
return
Sparc
::
fixup_sparc_tls_ldo_add
;
case
VK_Sparc_TLS_IE_HI22
:
return
Sparc
::
fixup_sparc_tls_ie_hi22
;
case
VK_Sparc_TLS_IE_LO10
:
return
Sparc
::
fixup_sparc_tls_ie_lo10
;
case
VK_Sparc_TLS_IE_LD
:
return
Sparc
::
fixup_sparc_tls_ie_ld
;
case
VK_Sparc_TLS_IE_LDX
:
return
Sparc
::
fixup_sparc_tls_ie_ldx
;
case
VK_Sparc_TLS_IE_ADD
:
return
Sparc
::
fixup_sparc_tls_ie_add
;
case
VK_Sparc_TLS_LE_HIX22
:
return
Sparc
::
fixup_sparc_tls_le_hix22
;
case
VK_Sparc_TLS_LE_LOX10
:
return
Sparc
::
fixup_sparc_tls_le_lox10
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


"Unexpected type for the widened instruction"

Called for instructions with the Custom LegalizationAction .


<s>
const
char
*
ix86_output_function_return
(
bool
long_p
)
{
output_return_instrumentation
(
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_keep
)
{
char
thunk_name
[
32
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_thunk_inline
)
{
bool
need_thunk
=
(
cfun
->
machine
->
function_return_type
==
indirect_branch_thunk
)
;
indirect_thunk_name
(
thunk_name
,
INVALID_REGNUM
,
need_prefix
,
true
)
;
indirect_return_needed
|=
need_thunk
;
fprintf
(
asm_out_file
,
"\tjmp\t"
)
;
assemble_name
(
asm_out_file
,
thunk_name
)
;
putc
(
'\n'
,
asm_out_file
)
;
}
else
output_indirect_thunk
(
INVALID_REGNUM
)
;
return
""
;
}
output_asm_insn
(
long_p
"rep%; ret"
:
"ret"
,
nullptr
)
;
return
(
ix86_harden_sls
&
harden_sls_return
)
"int3"
:
""
;
}
</s>

Output function return . CALL_OP is the jump target . Add a REP prefix to RET if LONG_P is true and function return is kept .


<s> SDValue AArch64TargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps ) const { if ( Enabled == ReciprocalEstimate :: Enabled ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRECPE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( AArch64ISD :: FRECPS , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , Flags ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> static X86Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc ) { X86Operand * Res = new X86Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> tree ix86_veclibabi_svml ( combined_fn fn , tree type_out , tree type_in ) { char name [ 20 ] ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_EXP : CASE_CFN_LOG : CASE_CFN_LOG10 : CASE_CFN_POW : CASE_CFN_TANH : CASE_CFN_TAN : CASE_CFN_ATAN : CASE_CFN_ATAN2 : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_SINH : CASE_CFN_SIN : CASE_CFN_ASINH : CASE_CFN_ASIN : CASE_CFN_COSH : CASE_CFN_COS : CASE_CFN_ACOSH : CASE_CFN_ACOS : if ( ( el_mode != DFmode || n != 2 ) && ( el_mode != SFmode || n != 4 ) ) return NULL_TREE ; break ; default : return NULL_TREE ; } tree fndecl = mathfn_built_in ( el_mode == DFmode ? double_type_node : float_type_node , fn ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; if ( DECL_FUNCTION_CODE ( fndecl ) == BUILT_IN_LOGF ) strcpy ( name , "vmlsLn4" ) ; else if ( DECL_FUNCTION_CODE ( fndecl ) == BUILT_IN_LOG ) strcpy ( name , "vmldLn2" ) ; else if ( n == 4 ) { sprintf ( name , "vmls%s" , bname + 10 ) ; name [ strlen ( name ) - 1 ] = '4' ; } else sprintf ( name , "vmld%s2" , bname + 10 ) ; name [ 4 ] &= ~ 0x20 ; arity = 0 ; for ( args = DECL_ARGUMENTS ( fndecl ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an SVML-style interface to a library with vectorized intrinsics .


<s>
static
void
ix86_test_dumping_hard_regs
(
)
{
ASSERT_RTL_DUMP_EQ
(
"(reg:SI ax)"
,
gen_raw_REG
(
SImode
,
0
)
)
;
ASSERT_RTL_DUMP_EQ
(
"(reg:SI dx)"
,
gen_raw_REG
(
SImode
,
1
)
)
;
}
</s>

Verify that hard regs are dumped as expected ( in compact mode ) .


<s> static void ix86_emit_vec_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src1 , rtx src2 ) { rtx tmp ; tmp = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ; if ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( SImode ) && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , tmp , clob ) ) ; } emit_insn ( tmp ) ; } </s>

Emit x86 binary operand CODE in mode MODE for SSE vector instructions that can be performed using GP registers .


<s> SDValue SparcTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { if ( Subtarget -> is64Bit ( ) ) return LowerReturn_64 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; return LowerReturn_32 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static tree ia64_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= IA64_BUILTIN_max ) return error_mark_node ; return ia64_builtins [ code ] ; } </s>


<s> static int sparc_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { int slotno , regno , padding ; slotno = function_arg_slotno ( get_cumulative_args ( cum ) , mode , type , named , false , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { if ( ( slotno + ( mode == BLKmode ? CEIL_NWORDS ( int_size_in_bytes ( type ) ) : CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ) ) > SPARC_INT_ARG_MAX ) return ( SPARC_INT_ARG_MAX - slotno ) * UNITS_PER_WORD ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size > UNITS_PER_WORD && ( slotno == SPARC_INT_ARG_MAX - 1 || slotno == SPARC_FP_ARG_MAX - 1 ) ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && ! ( TARGET_FPU && named ) ) ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( ( slotno + GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ) > SPARC_FP_ARG_MAX ) return UNITS_PER_WORD ; } } return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes of registers used . For args passed entirely in registers or entirely in memory , zero . Any arg that starts in the first 6 regs but wo n't entirely fit in them needs partial registers on v8 . On v9 , structures with integer values in arg slots 5,6 will be passed in % o5 and SP+176 , and complex fp values that begin in the last fp reg [ where `` last fp reg '' varies with the mode ] will be split between that reg and memory .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( MF . protectReturnPtr ( ) && ! MF . getName ( ) . equals ( "main" ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; if ( MF . protectFramePtr ( ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; } unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( CSI [ i ] . getReg ( ) == FPReg ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } bool hasGPR = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; hasGPR = true ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } if ( MF . protectCSRs ( ) && hasGPR ) { SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\t.set\tpush\n" ; O << "\t.set\tmips32r2\n" ; } printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\n\t.set\tpop" ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void AArch64TargetStreamer :: emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } getStreamer ( ) . emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


"Unable to generate load/store offset for fusion"

Emit a D-form load or store instruction that is the second instruction of a fusion sequence .


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static struct machine_function * moxie_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Zero initialization is OK for all current fields .


"\tmove\t%s,%s\t\t# save current return address\n"

"\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n"


<s> void X86PassConfig :: addPostRegAlloc ( ) { addPass ( createX86FloatingPointStackifierPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static void mips_sim_wait_regs_1 ( rtx * x , void * data ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , * x , NONCONST ) if ( REG_P ( * iter ) ) mips_sim_wait_reg ( ( struct mips_sim * ) data , mips_sim_insn , * iter ) ; } </s>

Call mips_sim_wait_regs_2 ( R , DATA ) for each register R mentioned in * X .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_VFP_BASE ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ! reg_needs_saving_p ( regno ) && ! reg_needs_saving_p ( regno + 1 ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


<s> static bool nds32_naked_function_p ( tree func ) { tree t ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; t = lookup_attribute ( "naked" , DECL_ATTRIBUTES ( func ) ) ; return ( t != NULL_TREE ) ; } </s>

Return true if FUNC is a naked function .


<s>
bool
ARMAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
MCP
=
MF
.
getConstantPool
(
)
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n"
;
O
<<
'\n'
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
llvm_unreachable
(
"Unknown linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
LinkerPrivateLinkage
:
case
Function
::
InternalLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
"\n"
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
if
(
Subtarget
->
isTargetDarwin
(
)
)
{
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
"\n"
;
O
<<
"\t.weak_definition\t"
<<
CurrentFnName
<<
"\n"
;
}
else
{
O
<<
TAI
->
getWeakRefDirective
(
)
<<
CurrentFnName
<<
"\n"
;
}
break
;
}
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
if
(
AFI
->
isThumbFunction
(
)
)
{
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
,
AFI
->
getAlign
(
)
)
;
O
<<
"\t.code\t16\n"
;
O
<<
"\t.thumb_func"
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
O
<<
"\t"
<<
CurrentFnName
;
O
<<
"\n"
;
InCPMode
=
false
;
}
else
{
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
)
;
}
O
<<
CurrentFnName
<<
":\n"
;
DW
->
BeginFunction
(
&
MF
)
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
{
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
;
if
(
++
I
==
MF
.
end
(
)
&&
MF
.
front
(
)
.
empty
(
)
)
O
<<
"\tnop\n"
;
}
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size "
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
"\n"
;
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>

ARM
ARM
ARM
"\n"
"Unknown linkage type!"
"\t.globl\t"
"\n"
"\t.globl\t"
"\n"
"\t.weak_definition\t"
"\n"
"\n"
"\t.code\t16\n"
"\t.thumb_func"
"\t"
"\n"
":\n"
"\tnop\n"
"\t.size "
", .-"
"\n"


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool MINA32FrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .