<s> rtx ix86_fixup_binary_operands ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src1 = operands [ 1 ] ; rtx src2 = operands [ 2 ] ; if ( ix86_swap_binary_operands_p ( code , mode , operands ) ) { gcc_assert ( GET_MODE ( src1 ) == GET_MODE ( src2 ) ) ; std :: swap ( src1 , src2 ) ; } if ( MEM_P ( src1 ) && MEM_P ( src2 ) ) { if ( rtx_equal_p ( src1 , src2 ) ) { src2 = force_reg ( mode , src2 ) ; src1 = src2 ; } else if ( rtx_equal_p ( dst , src1 ) ) src2 = force_reg ( mode , src2 ) ; else src1 = force_reg ( mode , src1 ) ; } if ( MEM_P ( dst ) && ! rtx_equal_p ( dst , src1 ) ) dst = gen_reg_rtx ( mode ) ; if ( CONSTANT_P ( src1 ) ) src1 = force_reg ( mode , src1 ) ; if ( MEM_P ( src1 ) && ! rtx_equal_p ( dst , src1 ) ) src1 = force_reg ( mode , src1 ) ; if ( code == PLUS && GET_MODE_CLASS ( mode ) == MODE_INT && MEM_P ( src2 ) ) src2 = force_reg ( mode , src2 ) ; operands [ 1 ] = src1 ; operands [ 2 ] = src2 ; return dst ; } </s>

Fix up OPERANDS to satisfy ix86_binary_operator_ok . Return the destination to use for the operation . If different from the true destination in operands [ 0 ] , a copy operation will be required .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; const X86RegisterInfo * X86RI = TM -> getRegisterInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; X86MachineFunctionInfo * FuncInfo = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned StackAlignment = X86RI -> getStackAlignment ( ) ; for ( unsigned i = 0 , e = RI . getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RI . getRegClass ( Reg ) -> getAlignment ( ) > StackAlignment ) { FuncInfo -> setReserveFP ( true ) ; return true ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
MCFixupKindInfo
&
SystemZMCAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SystemZ
::
NumTargetFixupKinds
]
=
{
{
"FK_390_PC12DBL"
,
4
,
12
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC16DBL"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC24DBL"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC32DBL"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_TLS_CALL"
,
0
,
0
,
0
}
,
{
"FK_390_12"
,
4
,
12
,
0
}
,
{
"FK_390_20"
,
4
,
20
,
0
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static bool call_ABI_of_interest ( tree fndecl ) { if ( rs6000_gnu_attr && symtab -> state == EXPANSION ) { struct cgraph_node * c_node ; if ( fndecl == NULL_TREE ) return true ; if ( DECL_EXTERNAL ( fndecl ) ) return true ; c_node = cgraph_node :: get ( fndecl ) ; c_node = c_node -> ultimate_alias_target ( ) ; return ! c_node -> only_called_directly_p ( ) ; } return false ; } </s>

Return TRUE if a call to function FNDECL may be one that potentially affects the function calling ABI of the object file .


<s> static sbitmap aarch64_components_for_bb ( basic_block bb ) { bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; bool simd_function = aarch64_simd_decl_p ( cfun -> decl ) ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ( ! call_used_regs [ regno ] || ( simd_function && FP_SIMD_SAVED_REGNUM_P ( regno ) ) ) && ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { unsigned regno2 , offset , offset2 ; bitmap_set_bit ( components , regno ) ; offset = cfun -> machine -> frame . reg_offset [ regno ] ; regno2 = ( ( offset & 8 ) == 0 ) ? regno + 1 : regno - 1 ; if ( regno2 <= LAST_SAVED_REGNUM ) { offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ( offset & ~ 8 ) == ( offset2 & ~ 8 ) ) bitmap_set_bit ( components , regno2 ) ; } } return components ; } </s>


<s> unsigned DLXMCCodeEmitter :: getMachineOpValue ( const MCInst & Inst , const MCOperand & MCOp , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { if ( MCOp . isReg ( ) ) return getDLXRegisterNumbering ( MCOp . getReg ( ) ) ; if ( MCOp . isImm ( ) ) return static_cast < unsigned > ( MCOp . getImm ( ) ) ; assert ( MCOp . isExpr ( ) ) ; const MCExpr * Expr = MCOp . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * BinaryExpr = static_cast < const MCBinaryExpr * > ( Expr ) ; Expr = BinaryExpr -> getLHS ( ) ; } assert ( isa < DLXMCExpr > ( Expr ) || Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , MCFixupKind ( FixupKind ( Expr ) ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> static enum mips_int_mask mips_interrupt_mask ( tree type ) { tree attr = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type ) ) ; tree args , cst ; const char * str ; if ( attr == NULL ) return INT_MASK_EIC ; args = TREE_VALUE ( attr ) ; if ( args == NULL ) return INT_MASK_EIC ; cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , "eic" ) == 0 ) return INT_MASK_EIC ; str = TREE_STRING_POINTER ( cst ) ; gcc_assert ( strlen ( str ) == strlen ( "vector=sw0" ) ) ; if ( str [ 7 ] == 's' ) return ( enum mips_int_mask ) ( INT_MASK_SW0 + ( str [ 9 ] - '0' ) ) ; return ( enum mips_int_mask ) ( INT_MASK_HW0 + ( str [ 9 ] - '0' ) ) ; } </s>

Return the mask for the `` interrupt '' attribute .


<s> void Cpu0FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool rx_is_legitimate_constant ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; gcc_assert ( ! CONST_INT_P ( x ) ) ; } switch ( GET_CODE ( x ) ) { case LABEL_REF : case SYMBOL_REF : return true ; case UNSPEC : return XINT ( x , 1 ) == UNSPEC_CONST || XINT ( x , 1 ) == UNSPEC_PID_ADDR ; default : gcc_unreachable ( ) ; } break ; case LABEL_REF : case SYMBOL_REF : return true ; case CONST_DOUBLE : return ( rx_max_constant_size == 0 || rx_max_constant_size == 4 ) ; case CONST_VECTOR : return false ; default : gcc_assert ( CONST_INT_P ( x ) ) ; break ; } return ok_for_max_constant ( INTVAL ( x ) ) ; } </s>

Returns true if X a legitimate constant for an immediate operand on the RX . X is already known to satisfy CONSTANT_P .


<s>
void
moxie_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
0
:
break
;
default
:
LOSE_AND_RETURN
(
"invalid operand modifier letter"
,
x
)
;
}
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
if
(
REGNO
(
operand
)
>
MOXIE_R13
)
internal_error
(
"internal error: bad register: %d"
,
REGNO
(
operand
)
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
return
;
case
MEM
:
output_address
(
XEXP
(
operand
,
0
)
)
;
return
;
default
:
if
(
CONSTANT_P
(
operand
)
)
{
output_addr_const
(
file
,
operand
)
;
return
;
}
LOSE_AND_RETURN
(
"unexpected operand"
,
x
)
;
}
}
</s>

moxie
0
"invalid operand modifier letter"
"internal error: bad register: %d"
"%s"
0
"unexpected operand"


<s> static void pa_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx end_addr = gen_reg_rtx ( Pmode ) ; rtx line_length = gen_reg_rtx ( Pmode ) ; rtx r_tramp , tmp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; r_tramp = force_reg ( Pmode , XEXP ( m_tramp , 0 ) ) ; if ( ! TARGET_64BIT ) { tmp = adjust_address ( m_tramp , Pmode , 36 ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , 40 ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , 44 ) ; emit_move_insn ( tmp , r_tramp ) ; tmp = adjust_address ( m_tramp , Pmode , 48 ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , 19 ) ) ; emit_insn ( gen_andsi3 ( start_addr , r_tramp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , TRAMPOLINE_CODE_SIZE - 1 ) ) ; emit_insn ( gen_andsi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushsi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushsi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } else { tmp = adjust_address ( m_tramp , Pmode , 56 ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , 64 ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , 16 ) ; emit_move_insn ( tmp , force_reg ( Pmode , plus_constant ( Pmode , r_tramp , 32 ) ) ) ; tmp = adjust_address ( m_tramp , Pmode , 24 ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , 27 ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , 32 ) ) ; emit_insn ( gen_anddi3 ( start_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , tmp , TRAMPOLINE_CODE_SIZE - 1 ) ) ; emit_insn ( gen_anddi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushdi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushdi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . Move the function address to the trampoline template at offset 36 . Move the static chain value to trampoline template at offset 40 . Move the trampoline address to trampoline template at offset 44 . Move r19 to trampoline template at offset 48 . The latter two words create a plabel for the indirect call to the trampoline . A similar sequence is used for the 64-bit port but the plabel is at the beginning of the trampoline . Finally , the cache entries for the trampoline code are flushed . This is necessary to ensure that the trampoline instruction sequence is written to memory prior to any attempts at prefetching the code sequence .


"cannot optimize division for both latency and throughput"


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
rtx
iq2000_legitimize_address
(
rtx
xinsn
,
rtx
old_x
ATTRIBUTE_UNUSED
,
machine_mode
mode
)
{
if
(
TARGET_DEBUG_B_MODE
)
{
GO_PRINTF
(
"\n========== LEGITIMIZE_ADDRESS\n"
)
;
GO_DEBUG_RTX
(
xinsn
)
;
}
if
(
iq2000_check_split
(
xinsn
,
mode
)
)
{
return
gen_rtx_LO_SUM
(
Pmode
,
copy_to_mode_reg
(
Pmode
,
gen_rtx_HIGH
(
Pmode
,
xinsn
)
)
,
xinsn
)
;
}
if
(
GET_CODE
(
xinsn
)
==
PLUS
)
{
rtx
xplus0
=
XEXP
(
xinsn
,
0
)
;
rtx
xplus1
=
XEXP
(
xinsn
,
1
)
;
enum
rtx_code
code0
=
GET_CODE
(
xplus0
)
;
enum
rtx_code
code1
=
GET_CODE
(
xplus1
)
;
if
(
code0
!=
REG
&&
code1
==
REG
)
{
xplus0
=
XEXP
(
xinsn
,
1
)
;
xplus1
=
XEXP
(
xinsn
,
0
)
;
code0
=
GET_CODE
(
xplus0
)
;
code1
=
GET_CODE
(
xplus1
)
;
}
if
(
code0
==
REG
&&
REG_MODE_OK_FOR_BASE_P
(
xplus0
,
mode
)
&&
code1
==
CONST_INT
&&
!
SMALL_INT
(
xplus1
)
)
{
rtx
int_reg
=
gen_reg_rtx
(
Pmode
)
;
rtx
ptr_reg
=
gen_reg_rtx
(
Pmode
)
;
emit_move_insn
(
int_reg
,
GEN_INT
(
INTVAL
(
xplus1
)
&
~
0x7fff
)
)
;
emit_insn
(
gen_rtx_SET
(
ptr_reg
,
gen_rtx_PLUS
(
Pmode
,
xplus0
,
int_reg
)
)
)
;
return
plus_constant
(
Pmode
,
ptr_reg
,
INTVAL
(
xplus1
)
&
0x7fff
)
;
}
}
if
(
TARGET_DEBUG_B_MODE
)
GO_PRINTF
(
"LEGITIMIZE_ADDRESS could not fix.\n"
)
;
return
xinsn
;
}
</s>

For the IQ2000 , transform : memory ( X + < large int > ) into : Y = < large int > & ~0x7fff ; Z = X + Y memory ( Z + ( < large int > & 0x7fff ) ) ;


<s> bool ARMExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified ; } </s>


<s> static rtx safe_vector_operand ( rtx x , machine_mode mode ) { if ( x != const0_rtx ) return x ; x = gen_reg_rtx ( mode ) ; emit_insn ( gen_iwmmxt_clrdi ( mode == DImode ? x : gen_rtx_SUBREG ( DImode , x , 0 ) ) ) ; return x ; } </s>

Errors in the source file can cause expand_expr to return const0_rtx where we expect a vector . To avoid crashing , use one of the vector clear instructions .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( STI -> isTargetDarwin ( ) ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool PPCInstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { const TargetRegisterClass * RCs [ ] = { & PPC :: CRRCRegClass , & PPC :: CRBITRCRegClass , & PPC :: CTRRCRegClass , & PPC :: CTRRC8RegClass } ; bool Found = false ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; for ( unsigned c = 0 ; c < array_lengthof ( RCs ) && ! Found ; ++ c ) { const TargetRegisterClass * RC = RCs [ c ] ; if ( MO . isReg ( ) ) { if ( MO . isDef ( ) && RC -> contains ( MO . getReg ( ) ) ) { Pred . push_back ( MO ) ; Found = true ; } } else if ( MO . isRegMask ( ) ) { for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , IE = RC -> end ( ) ; I != IE ; ++ I ) if ( MO . clobbersPhysReg ( * I ) ) { Pred . push_back ( MO ) ; Found = true ; } } } } return Found ; } </s>

If the specified instruction defines any predicate or condition code register ( s ) used for predication , returns true as well as the definition predicate ( s ) by reference .


"\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "

"type = %d, ind_levels = %d, win = %d, original addr:\n"

Debug version of rs6000_legitimize_reload_address .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static bool dimode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( ( GET_MODE ( src ) != DImode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFT : case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , 1 ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , 1 ) ) , 0 , 63 ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ! CONST_INT_P ( XEXP ( src , 0 ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ) ) return false ; if ( ( GET_MODE ( XEXP ( src , 0 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) || ( GET_CODE ( src ) != NEG && GET_CODE ( src ) != NOT && GET_MODE ( XEXP ( src , 1 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) ) return false ; return true ; } </s>

The DImode version of scalar_to_vector_candidate_p .


<s> bool X86FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { const X86RegisterInfo * TRI = static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; return hasReservedCallFrame ( MF ) || ( hasFP ( MF ) && ! TRI -> needsStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> getFnAttributes ( ) . hasNoImplicitFloatAttr ( ) && Subtarget -> hasNEON ( ) ) { if ( memOpAlign ( SrcAlign , DstAlign , 16 ) && Size >= 16 ) { return MVT :: v4i32 ; } else if ( memOpAlign ( SrcAlign , DstAlign , 8 ) && Size >= 8 ) { return MVT :: v2i32 ; } } if ( Size >= 4 ) { return MVT :: i32 ; } else if ( Size >= 2 ) { return MVT :: i16 ; } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
bool
ARMBaseInstrInfo
::
getRegSequenceLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
SmallVectorImpl
<
RegSubRegPairAndIdx
>
&
InputRegs
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isRegSequenceLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VMOVDRR
:
const
MachineOperand
*
MOReg
=
&
MI
.
getOperand
(
1
)
;
if
(
!
MOReg
->
isUndef
(
)
)
InputRegs
.
push_back
(
RegSubRegPairAndIdx
(
MOReg
->
getReg
(
)
,
MOReg
->
getSubReg
(
)
,
ARM
::
ssub_0
)
)
;
MOReg
=
&
MI
.
getOperand
(
2
)
;
if
(
!
MOReg
->
isUndef
(
)
)
InputRegs
.
push_back
(
RegSubRegPairAndIdx
(
MOReg
->
getReg
(
)
,
MOReg
->
getSubReg
(
)
,
ARM
::
ssub_1
)
)
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getRegSequenceInputs .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> bool aarch64_pad_arg_upward ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return true ; if ( type ? ( INTEGRAL_TYPE_P ( type ) || SCALAR_FLOAT_TYPE_P ( type ) || POINTER_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || SCALAR_FLOAT_MODE_P ( mode ) ) ) return false ; return true ; } </s>

For use by FUNCTION_ARG_PADDING ( MODE , TYPE ) . Return true if an argument passed on the stack should be padded upwards , i.e . if the least-significant byte of the stack slot has useful data . Small aggregate types are placed in the lowest memory address . The related parameter passing rules are B.4 , C.3 , C.5 and C.14 .


<s> static bool v2df_reduction_p ( rtx op ) { if ( GET_MODE ( op ) != V2DFmode ) return false ; enum rtx_code code = GET_CODE ( op ) ; if ( code != PLUS && code != SMIN && code != SMAX ) return false ; rtx concat = XEXP ( op , 0 ) ; if ( GET_CODE ( concat ) != VEC_CONCAT ) return false ; rtx select0 = XEXP ( concat , 0 ) ; rtx select1 = XEXP ( concat , 1 ) ; if ( GET_CODE ( select0 ) != VEC_SELECT || GET_CODE ( select1 ) != VEC_SELECT ) return false ; rtx reg0 = XEXP ( select0 , 0 ) ; rtx reg1 = XEXP ( select1 , 0 ) ; if ( ! rtx_equal_p ( reg0 , reg1 ) || ! REG_P ( reg0 ) ) return false ; rtx parallel0 = XEXP ( select0 , 1 ) ; rtx parallel1 = XEXP ( select1 , 1 ) ; if ( GET_CODE ( parallel0 ) != PARALLEL || GET_CODE ( parallel1 ) != PARALLEL ) return false ; if ( ! rtx_equal_p ( XVECEXP ( parallel0 , 0 , 0 ) , const1_rtx ) || ! rtx_equal_p ( XVECEXP ( parallel1 , 0 , 0 ) , const0_rtx ) ) return false ; return true ; } </s>

Return TRUE iff OP matches a V2DF reduction pattern . See the definition of vsx_reduc_ < VEC_reduc_name > _v2df in vsx.md .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> TargetPassConfig * XNCMTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new XNCMPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const unsigned CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const unsigned CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETI : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < unsigned , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( const unsigned * AsI = TRI . getOverlaps ( Reg ) ; * AsI ; ++ AsI ) Uses . insert ( * AsI ) ; } const unsigned * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


"multiple save register attributes to function %qD"

"multiple nested types attributes to function %qD"

"multiple interrupt attributes to function %qD"

"cannot use interrupt attributes to function %qD "

"cannot use exception attributes to function %qD "

"cannot use reset attributes to function %qD "

Function for nds32_merge_decl_attributes ( ) and nds32_insert_attributes ( ) to check if there are any conflict isr-specific attributes being set . We need to check : 1 . Only 'save_all ' or 'partial_save ' in the attributes . 2 . Only 'nested ' , 'not_nested ' , or 'nested_ready ' in the attributes . 3 . Only 'interrupt ' , 'exception ' , or 'reset ' in the attributes .


<s> bool PPCPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) ) ; addPass ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void ix86_run_selftests ( void ) { ix86_test_dumping_hard_regs ( ) ; ix86_test_dumping_memory_blockage ( ) ; ix86_test_loading_dump_fragment_1 ( ) ; ix86_test_loading_call_insn ( ) ; ix86_test_loading_full_dump ( ) ; ix86_test_loading_unspec ( ) ; } </s>


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void mips_restore_gp ( void ) { rtx address , slot ; gcc_assert ( TARGET_ABICALLS && TARGET_OLDABI ) ; address = mips_add_offset ( pic_offset_table_rtx , frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx , current_function_outgoing_args_size ) ; slot = gen_rtx_MEM ( Pmode , address ) ; emit_move_insn ( pic_offset_table_rtx , slot ) ; if ( ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_blockage ( ) ) ; } </s>

Restore $ gp from its save slot . Valid only when using o32 or o64 abicalls .


<s> static tree arm_mve_type_for_scalar_type ( tree eltype ) { for ( unsigned int i = 0 ; i < __TYPE_FINAL ; ++ i ) if ( arm_simd_types [ i ] . eltype == eltype && GET_MODE_SIZE ( arm_simd_types [ i ] . mode ) == 16 ) return arm_simd_types [ i ] . itype ; gcc_unreachable ( ) ; } </s>

Return the MVE abi type with element of type TYPE .


"\n%s -G value = %d, Arch = %s, ISA = %d\n"


<s> void SICPassConfig :: addPreEmitPass ( ) { SICTargetMachine & TM = getSICTargetMachine ( ) ; addPass ( createSICDelJmpPass ( TM ) ) ; return ; } </s>


<s> unsigned char ARM64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return ARM64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) return ARM64II :: MO_GOT ; if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return ( isDecl || GV -> isWeakForLinker ( ) ) ? ARM64II :: MO_GOT : ARM64II :: MO_NO_FLAG ; else return GV -> hasLocalLinkage ( ) ? ARM64II :: MO_NO_FLAG : ARM64II :: MO_GOT ; } return ARM64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> MachineBasicBlock :: iterator MINA32FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static int index_term_p ( rtx prod , enum machine_mode mode , int strict ) { rtx xfoo0 , xfoo1 ; if ( GET_MODE_SIZE ( mode ) == 1 ) return BASE_REGISTER_P ( prod , strict ) ; if ( GET_CODE ( prod ) != MULT || GET_MODE_SIZE ( mode ) > 8 ) return 0 ; xfoo0 = XEXP ( prod , 0 ) ; xfoo1 = XEXP ( prod , 1 ) ; if ( GET_CODE ( xfoo0 ) == CONST_INT && INTVAL ( xfoo0 ) == ( int ) GET_MODE_SIZE ( mode ) && INDEX_REGISTER_P ( xfoo1 , strict ) ) return 1 ; if ( GET_CODE ( xfoo1 ) == CONST_INT && INTVAL ( xfoo1 ) == ( int ) GET_MODE_SIZE ( mode ) && INDEX_REGISTER_P ( xfoo0 , strict ) ) return 1 ; return 0 ; } </s>

1 if PROD is either a reg times size of mode MODE and MODE is less than or equal 8 bytes , or just a reg if MODE is one byte .


<s> rtx mmix_get_hard_reg_initial_val ( enum machine_mode mode , int regno ) { return get_hard_reg_initial_val ( mode , regno ) ; } </s>

Wrapper for get_hard_reg_initial_val since integrate.h is n't included from insn-emit.cc .


<s> static unsigned getLinkageSize ( bool LP64 , bool isMacho ) { if ( isMacho ) return 6 * ( LP64 ? 8 : 4 ) ; return 8 ; } </s>

getLinkageSize - Return the size of the PowerPC ABI linkage area .


<s> static void rs6000_add_gc_roots ( ) { ggc_add_rtx_root ( & rs6000_compare_op0 , 1 ) ; ggc_add_rtx_root ( & rs6000_compare_op1 , 1 ) ; toc_hash_table = htab_create ( 1021 , toc_hash_function , toc_hash_eq , NULL ) ; ggc_add_root ( & toc_hash_table , 1 , sizeof ( toc_hash_table ) , toc_hash_mark_table ) ; machopic_add_gc_roots ( ) ; } </s>

Called to register all of our global variables with the garbage collector .


<s>
void
setReg
(
unsigned
Reg
)
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
Base
.
Reg
=
Reg
;
}
</s>

Assigns the associated register for this edge .


<s>
bool
PPCInstrInfo
::
FoldImmediate
(
MachineInstr
*
UseMI
,
MachineInstr
*
DefMI
,
unsigned
Reg
,
MachineRegisterInfo
*
MRI
)
const
{
unsigned
DefOpc
=
DefMI
->
getOpcode
(
)
;
if
(
DefOpc
!=
PPC
::
LI
&&
DefOpc
!=
PPC
::
LI8
)
return
false
;
if
(
!
DefMI
->
getOperand
(
1
)
.
isImm
(
)
)
return
false
;
if
(
DefMI
->
getOperand
(
1
)
.
getImm
(
)
!=
0
)
return
false
;
const
MCInstrDesc
&
UseMCID
=
UseMI
->
getDesc
(
)
;
if
(
UseMCID
.
isPseudo
(
)
)
return
false
;
unsigned
UseIdx
;
for
(
UseIdx
=
0
;
UseIdx
<
UseMI
->
getNumOperands
(
)
;
++
UseIdx
)
if
(
UseMI
->
getOperand
(
UseIdx
)
.
isReg
(
)
&&
UseMI
->
getOperand
(
UseIdx
)
.
getReg
(
)
==
Reg
)
break
;
assert
(
UseIdx
<
UseMI
->
getNumOperands
(
)
&&
"Cannot find Reg in UseMI"
)
;
assert
(
UseIdx
<
UseMCID
.
getNumOperands
(
)
&&
"No operand description for Reg"
)
;
const
MCOperandInfo
*
UseInfo
=
&
UseMCID
.
OpInfo
[
UseIdx
]
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
if
(
UseInfo
->
RegClass
!=
1
)
return
false
;
}
else
{
if
(
UseInfo
->
RegClass
!=
PPC
::
GPRC_NOR0RegClassID
&&
UseInfo
->
RegClass
!=
PPC
::
G8RC_NOX0RegClassID
)
return
false
;
}
if
(
UseInfo
->
Constraints
!=
0
)
return
false
;
unsigned
ZeroReg
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
bool
isPPC64
=
TM
.
getSubtargetImpl
(
)
->
isPPC64
(
)
;
ZeroReg
=
isPPC64
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
else
{
ZeroReg
=
UseInfo
->
RegClass
==
PPC
::
G8RC_NOX0RegClassID
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
bool
DeleteDef
=
MRI
->
hasOneNonDBGUse
(
Reg
)
;
UseMI
->
getOperand
(
UseIdx
)
.
setReg
(
ZeroReg
)
;
if
(
DeleteDef
)
DefMI
->
eraseFromParent
(
)
;
return
true
;
}
</s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void nds32_expand_epilogue ( bool sibcall_p ) { int sp_adjust ; int en4_const ; rtx Rb , Re ; rtx sp_adjust_insn ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( cfun -> machine -> va_args_size != 0 ) { sp_adjust = cfun -> machine -> va_args_size + cfun -> machine -> va_args_area_padding_bytes ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - 1 * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = nds32_force_addi_stack_int ( sp_adjust ) ; if ( sp_adjust ) { sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } } Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; en4_const = 0 ; if ( cfun -> machine -> fp_size ) en4_const += 8 ; if ( cfun -> machine -> gp_size ) en4_const += 4 ; if ( cfun -> machine -> lp_size ) en4_const += 2 ; if ( ! ( REGNO ( Rb ) == SP_REGNUM && REGNO ( Re ) == SP_REGNUM && en4_const == 0 ) ) { nds32_emit_stack_pop_multiple ( Rb , Re , GEN_INT ( en4_const ) ) ; } if ( cfun -> machine -> va_args_size != 0 ) { sp_adjust = cfun -> machine -> va_args_size + cfun -> machine -> va_args_area_padding_bytes ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; } </s>

Function for normal multiple pop epilogue .


<s> static void * ix86_init_cost ( struct loop * ) { unsigned * cost = XNEWVEC ( unsigned , 3 ) ; cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = 0 ; return cost ; } </s>


<s> const MipsTargetLowering * MipsTargetLowering :: create ( const MipsTargetMachine & TM , const MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return createMips16TargetLowering ( TM , STI ) ; return createMipsSETargetLowering ( TM , STI ) ; } </s>


<s> static void register_builtin_types ( ) { scalar_types [ VECTOR_TYPE_ ## ACLE_NAME ] = SCALAR_TYPE ; for ( unsigned int i = 0 ; i < NUM_VECTOR_TYPES ; ++ i ) { if ( vector_types [ i ] . requires_float && ! TARGET_HAVE_MVE_FLOAT ) continue ; tree eltype = scalar_types [ i ] ; tree vectype ; if ( eltype == boolean_type_node ) { vectype = get_typenode_from_name ( UINT16_TYPE ) ; gcc_assert ( GET_MODE_SIZE ( TYPE_MODE ( vectype ) ) == 2 ) ; } else { vectype = arm_mve_type_for_scalar_type ( eltype ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && GET_MODE_SIZE ( TYPE_MODE ( vectype ) ) == 16 ) ; } abi_vector_types [ i ] = vectype ; } } </s>

Register the built-in RVV ABI types , such as __rvv_int32m1_t .


<s> static void initiate_bundle_state_table ( void ) { bundle_state_table = new hash_table < bundle_state_hasher > ( 50 ) ; } </s>


<s> void split_double_concat ( machine_mode mode , rtx dst , rtx lo , rtx hi ) { rtx dlo , dhi ; int deleted_move_count = 0 ; split_double_mode ( mode , & dst , 1 , & dlo , & dhi ) ; if ( MEM_P ( lo ) && rtx_equal_p ( dlo , hi ) && reg_overlap_mentioned_p ( dhi , lo ) ) { emit_move_insn ( dhi , lo ) ; lo = dhi ; } else if ( MEM_P ( hi ) && ! MEM_P ( lo ) && ! rtx_equal_p ( dlo , lo ) && reg_overlap_mentioned_p ( dlo , hi ) ) { if ( rtx_equal_p ( dhi , lo ) ) { emit_move_insn ( dlo , hi ) ; hi = dlo ; } else { emit_move_insn ( dhi , hi ) ; hi = dhi ; } } if ( ! rtx_equal_p ( dlo , hi ) ) { if ( ! rtx_equal_p ( dlo , lo ) ) emit_move_insn ( dlo , lo ) ; else deleted_move_count ++ ; if ( ! rtx_equal_p ( dhi , hi ) ) emit_move_insn ( dhi , hi ) ; else deleted_move_count ++ ; } else if ( ! rtx_equal_p ( lo , dhi ) ) { if ( ! rtx_equal_p ( dhi , hi ) ) emit_move_insn ( dhi , hi ) ; else deleted_move_count ++ ; if ( ! rtx_equal_p ( dlo , lo ) ) emit_move_insn ( dlo , lo ) ; else deleted_move_count ++ ; } else if ( mode == TImode ) emit_insn ( gen_swapdi ( dlo , dhi ) ) ; else emit_insn ( gen_swapsi ( dlo , dhi ) ) ; if ( deleted_move_count == 2 ) emit_note ( NOTE_INSN_DELETED ) ; } </s>

Emit the double word assignment DST = { LO , HI } .


<s> static bool expand_vec_perm_movs ( struct expand_vec_perm_d * d ) { machine_mode vmode = d -> vmode ; unsigned i , nelt = d -> nelt ; rtx x ; if ( d -> one_operand_p ) return false ; if ( ! ( TARGET_SSE && ( vmode == V4SFmode || vmode == V4SImode ) ) && ! ( TARGET_MMX_WITH_SSE && ( vmode == V2SFmode || vmode == V2SImode ) ) && ! ( TARGET_SSE2 && ( vmode == V2DFmode || vmode == V2DImode ) ) ) return false ; if ( d -> perm [ 0 ] != nelt && d -> perm [ 0 ] != 0 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i + nelt - d -> perm [ 0 ] ) return false ; if ( d -> testing_p ) return true ; if ( d -> perm [ 0 ] == nelt ) x = gen_rtx_VEC_MERGE ( vmode , d -> op1 , d -> op0 , GEN_INT ( 1 ) ) ; else x = gen_rtx_VEC_MERGE ( vmode , d -> op0 , d -> op1 , GEN_INT ( 1 ) ) ; emit_insn ( gen_rtx_SET ( d -> target , x ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement D using movss or movsd .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( isConditionalBranch ( Inst ) || isUnconditionalBranch ( Inst ) ) { int64_t Imm ; Imm = Inst . getOperand ( Inst . getNumOperands ( ) - 1 ) . getImm ( ) ; Target = Addr + Imm ; return true ; } if ( Inst . getOpcode ( ) == CSKY :: BSR32 ) { Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; return true ; } switch ( Inst . getOpcode ( ) ) { default : return false ; case CSKY :: LRW16 : case CSKY :: LRW32 : case CSKY :: JSRI32 : case CSKY :: JMPI32 : int64_t Imm = Inst . getOperand ( Inst . getNumOperands ( ) - 1 ) . getImm ( ) ; Target = ( ( Addr + Imm ) & 0xFFFFFFFC ) ; return true ; } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> static bool arm_must_pass_in_stack ( const function_arg_info & arg ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( arg ) ; else return must_pass_in_stack_var_size_or_pad ( arg ) ; } </s>

Return true if a type must be passed in memory . For AAPCS , small aggregates ( padded to the size of a word ) should be passed in a register .


<s>
bool
AArch64InstrInfo
::
isCandidateToMergeOrPair
(
MachineInstr
&
MI
)
const
{
if
(
MI
.
hasOrderedMemoryRef
(
)
)
return
false
;
assert
(
MI
.
getOperand
(
1
)
.
isReg
(
)
&&
"Expected a reg operand."
)
;
if
(
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
unsigned
BaseReg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
if
(
MI
.
modifiesRegister
(
BaseReg
,
TRI
)
)
return
false
;
if
(
isLdStPairSuppressed
(
MI
)
)
return
false
;
if
(
Subtarget
.
avoidQuadLdStPairs
(
)
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDURQi
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDRQui
:
case
AArch64
::
STRQui
:
return
false
;
}
}
return
true
;
}
</s>

Return true if this is a load/store that can be potentially paired/merged .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) && ! isTargetNaCl ( ) && ! EnableARMDwarfEH ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> static int thumb_base_register_rtx_p ( rtx x , enum machine_mode mode , int strict_p ) { int regno ; if ( GET_CODE ( x ) != REG ) return 0 ; regno = REGNO ( x ) ; if ( strict_p ) return THUMB_REGNO_MODE_OK_FOR_BASE_P ( regno , mode ) ; return ( regno <= LAST_LO_REGNUM || regno > LAST_VIRTUAL_REGISTER || regno == FRAME_POINTER_REGNUM || ( GET_MODE_SIZE ( mode ) >= 4 && ( regno == STACK_POINTER_REGNUM || regno >= FIRST_PSEUDO_REGISTER || x == hard_frame_pointer_rtx || x == arg_pointer_rtx ) ) ) ; } </s>

Return nonzero if X is valid as a Thumb state base register .


<s>
const
MipsMCExpr
*
MipsMCExpr
::
create
(
MCSymbolRefExpr
::
VariantKind
VK
,
const
MCExpr
*
Expr
,
MCContext
&
Ctx
)
{
VariantKind
Kind
;
switch
(
VK
)
{
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
Kind
=
VK_Mips_LO
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
Kind
=
VK_Mips_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHER
:
Kind
=
VK_Mips_HIGHER
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHEST
:
Kind
=
VK_Mips_HIGHEST
;
break
;
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
return
new
(
Ctx
)
MipsMCExpr
(
Kind
,
Expr
)
;
}
</s>

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid kind!"
Mips


<s> void DLXFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void optimization_options ( int level , int size ATTRIBUTE_UNUSED ) { if ( level > 1 ) flag_schedule_insns = 0 ; if ( TARGET_MACHO ) flag_errno_math = 0 ; if ( optimize >= 1 ) flag_omit_frame_pointer = 2 ; flag_pcc_struct_return = 2 ; flag_asynchronous_unwind_tables = 2 ; SUBTARGET_OPTIMIZATION_OPTIONS ; } </s>

Change optimizations to be performed , depending on the optimization level . LEVEL is the optimization level specified ; 2 if ` -O2 ' is specified , 1 if ` -O ' is specified , and 0 if neither is specified . SIZE is nonzero if ` -Os ' is specified and zero otherwise .


<s> bool sh_split_movrt_negc_to_movt_xor ( rtx_insn * curr_insn , rtx operands [ ] ) { if ( ! can_create_pseudo_p ( ) ) return false ; set_of_reg t_before_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , prev_nonnote_insn_bb ) ; set_of_reg t_after_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , next_nonnote_insn_bb ) ; if ( t_before_negc . set_rtx != NULL_RTX && t_after_negc . set_rtx != NULL_RTX && rtx_equal_p ( t_before_negc . set_rtx , t_after_negc . set_rtx ) && ! reg_used_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_insn_operands_modified_between_p ( t_before_negc . insn , t_before_negc . insn , t_after_negc . insn ) && ! sh_unspec_insn_p ( t_after_negc . insn ) && ! volatile_insn_p ( PATTERN ( t_after_negc . insn ) ) && ! side_effects_p ( PATTERN ( t_after_negc . insn ) ) && ! may_trap_or_fault_p ( PATTERN ( t_after_negc . insn ) ) ) { emit_insn ( gen_movrt_xor ( operands [ 0 ] , get_t_reg_rtx ( ) ) ) ; set_insn_deleted ( t_after_negc . insn ) ; return true ; } else return false ; } </s>

Given the current insn , which is assumed to be a movrt_negc insn , try to figure out whether it should be converted into a movt-xor sequence in the movrt_negc splitter . Returns true if insns have been modified and the splitter has succeeded .


<s>
unsigned
X86TargetLowering
::
getRegisterByName
(
const
char
*
RegName
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"esp"
,
X86
::
ESP
)
.
Case
(
"rsp"
,
X86
::
RSP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> static void ix86_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS next_cum ; rtx save_area = NULL_RTX , mem ; rtx label ; rtx label_ref ; rtx tmp_reg ; rtx nsse_reg ; int set ; tree fntype ; int stdarg_p ; int i ; if ( ! TARGET_64BIT ) return ; if ( ! cfun -> va_list_gpr_size && ! cfun -> va_list_fpr_size ) return ; ix86_save_varrargs_registers = 1 ; cfun -> stack_alignment_needed = 128 ; fntype = TREE_TYPE ( current_function_decl ) ; stdarg_p = ( TYPE_ARG_TYPES ( fntype ) != 0 && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ; next_cum = * cum ; if ( stdarg_p ) function_arg_advance ( & next_cum , mode , type , 1 ) ; if ( ! no_rtl ) save_area = frame_pointer_rtx ; set = get_varargs_alias_set ( ) ; for ( i = next_cum . regno ; i < ix86_regparm && i < next_cum . regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; i ++ ) { mem = gen_rtx_MEM ( Pmode , plus_constant ( save_area , i * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , x86_64_int_parameter_registers [ i ] ) ) ; } if ( next_cum . sse_nregs && cfun -> va_list_fpr_size ) { label = gen_label_rtx ( ) ; label_ref = gen_rtx_LABEL_REF ( Pmode , label ) ; tmp_reg = gen_reg_rtx ( Pmode ) ; nsse_reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_zero_extendqidi2 ( nsse_reg , gen_rtx_REG ( QImode , 0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp_reg , gen_rtx_MULT ( Pmode , nsse_reg , GEN_INT ( 4 ) ) ) ) ; if ( next_cum . sse_regno ) emit_move_insn ( nsse_reg , gen_rtx_CONST ( DImode , gen_rtx_PLUS ( DImode , label_ref , GEN_INT ( next_cum . sse_regno * 4 ) ) ) ) ; else emit_move_insn ( nsse_reg , label_ref ) ; emit_insn ( gen_subdi3 ( nsse_reg , nsse_reg , tmp_reg ) ) ; tmp_reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp_reg , plus_constant ( save_area , 8 * REGPARM_MAX + 127 ) ) ) ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( tmp_reg , - 127 ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , BITS_PER_WORD ) ; emit_insn ( gen_sse_prologue_save ( mem , nsse_reg , GEN_INT ( next_cum . sse_regno ) , label ) ) ; } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


"Loop must have more than one incoming edge!"

Check to see if the loop has a canonical induction variable : an integer recurrence that starts at 0 and increments by one each time through the loop .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


"\nrs6000_secondary_reload_gpr, type = %s\n"

Convert reloads involving 64-bit gprs and misaligned offset addressing , or multiple 32-bit gprs and offsets that are too large , to use indirect addressing .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT ) const override { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( ( Count % 8 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 8 ) support :: endian :: write < uint64_t > ( OS , 0x7900000000000000ULL , support :: little ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = STI -> isMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> int mmix_valid_comparison ( RTX_CODE code , enum machine_mode mode , rtx op ) { if ( mode == VOIDmode && op != NULL_RTX ) mode = GET_MODE ( op ) ; if ( mode == CCmode || mode == CC_UNSmode || mode == DImode ) return 1 ; if ( ( mode == CC_FPmode || mode == DFmode ) && ( code == GT || code == LT ) ) return 1 ; if ( ( mode == CC_FPEQmode || mode == DFmode ) && ( code == EQ || code == NE ) ) return 1 ; if ( ( mode == CC_FUNmode || mode == DFmode ) && ( code == ORDERED || code == UNORDERED ) ) return 1 ; return 0 ; } </s>

Returns zero if code and mode is not a valid condition from a compare-type insn . Nonzero if it is . The parameter op , if non-NULL , is the comparison of mode is CC-somethingmode .


<s> void SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) , false ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & PostMachineSchedulerID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> int memory_ok_for_ldd ( rtx op ) { if ( ! mem_min_alignment ( op , 8 ) ) return 0 ; if ( ( reload_in_progress || reload_completed ) && ! strict_memory_address_p ( Pmode , XEXP ( op , 0 ) ) ) return 0 ; if ( lra_in_progress && ! memory_address_p ( Pmode , XEXP ( op , 0 ) ) ) return 0 ; return 1 ; } </s>

Return 1 if OP , a MEM , has an address which is known to be aligned to an 8-byte boundary .


<s> const MachineBasicBlock * getMBB ( ) const { return MBB ; } </s>

Return a reference to the basic block containing this bundle .


<s> bool fusion_gpr_load_p ( rtx addis_reg , rtx addis_value , rtx target , rtx mem ) { rtx addr ; rtx base_reg ; if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! base_reg_operand ( target , GET_MODE ( target ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( mem ) == ZERO_EXTEND || ( GET_CODE ( mem ) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN ) ) mem = XEXP ( mem , 0 ) ; if ( ! MEM_P ( mem ) ) return false ; if ( ! fusion_gpr_mem_load ( mem , GET_MODE ( mem ) ) ) return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) != PLUS && GET_CODE ( addr ) != LO_SUM ) return false ; if ( REGNO ( addis_reg ) != REGNO ( target ) ) { if ( reg_mentioned_p ( target , mem ) ) return false ; if ( ! peep2_reg_dead_p ( 2 , addis_reg ) ) return false ; if ( REG_P ( target ) && REGNO ( target ) == STACK_POINTER_REGNUM ) return false ; } base_reg = XEXP ( addr , 0 ) ; return REGNO ( addis_reg ) == REGNO ( base_reg ) ; } </s>

Return true if the peephole2 can combine a load involving a combination of an addis instruction and a load with an offset that can be fused together on a power8 .


<s> void Cpu0AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i != Size ; ++ i ) { EmitByte ( Val & 255 , OS ) ; Val >>= 8 ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static rsqrts_type get_rsqrts_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrtsdf ; case SFmode : return gen_aarch64_rsqrtssf ; case V2DFmode : return gen_aarch64_rsqrtsv2df ; case V2SFmode : return gen_aarch64_rsqrtsv2sf ; case V4SFmode : return gen_aarch64_rsqrtsv4sf ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root series step insn depending on machine mode .


<s> static void arm_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { if ( mode == SImode ) gcc_assert ( ! TARGET_IDIV ) ; scalar_int_mode libval_mode = smallest_int_mode_for_size ( 2 * GET_MODE_BITSIZE ( mode ) ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , op0 , mode , op1 , mode ) ; rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , 0 ) ; rtx remainder = simplify_gen_subreg ( mode , libval , libval_mode , GET_MODE_SIZE ( mode ) ) ; gcc_assert ( quotient ) ; gcc_assert ( remainder ) ; * quot_p = quotient ; * rem_p = remainder ; } </s>

Generate call to __aeabi_ [ mode ] divmod ( op0 , op1 ) .


"unrecognizable argument of option -foffload-abi"

Main program to convert flat files into built-in initialization code .


<s> static bool aarch64_evpc_ext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location = d -> perm [ 0 ] ; for ( i = 1 ; i < nelt ; i ++ ) { unsigned int required = location + i ; if ( d -> one_vector_p ) { required &= ( nelt - 1 ) ; } if ( d -> perm [ i ] != required ) return false ; } switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_extv16qi ; break ; case V8QImode : gen = gen_aarch64_extv8qi ; break ; case V4HImode : gen = gen_aarch64_extv4hi ; break ; case V8HImode : gen = gen_aarch64_extv8hi ; break ; case V2SImode : gen = gen_aarch64_extv2si ; break ; case V4SImode : gen = gen_aarch64_extv4si ; break ; case V4HFmode : gen = gen_aarch64_extv4hf ; break ; case V8HFmode : gen = gen_aarch64_extv8hf ; break ; case V2SFmode : gen = gen_aarch64_extv2sf ; break ; case V4SFmode : gen = gen_aarch64_extv4sf ; break ; case V2DImode : gen = gen_aarch64_extv2di ; break ; case V2DFmode : gen = gen_aarch64_extv2df ; break ; default : return false ; } if ( d -> testing_p ) return true ; if ( BYTES_BIG_ENDIAN && ( location != 0 ) ) { std :: swap ( d -> op0 , d -> op1 ) ; location = nelt - location ; } offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> SDValue Cpu0TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { return CLI . Chain ; } </s>

This hook must be implemented to lower calls into the specified DAG .


<s> bool ARMBaseInstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / 8 > 64 ) return false ; if ( ( Load1 -> getMachineOpcode ( ) != Load2 -> getMachineOpcode ( ) ) && ! ( ( Load1 -> getMachineOpcode ( ) == ARM :: t2LDRBi8 && Load2 -> getMachineOpcode ( ) == ARM :: t2LDRBi12 ) || ( Load1 -> getMachineOpcode ( ) == ARM :: t2LDRBi12 && Load2 -> getMachineOpcode ( ) == ARM :: t2LDRBi8 ) ) ) return false ; if ( NumLoads >= 3 ) return false ; return true ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> bool sh_symbian_dllimport_name_p ( const char * symbol ) { return strncmp ( DLL_IMPORT_PREFIX , symbol , strlen ( DLL_IMPORT_PREFIX ) ) == 0 ; } </s>

Return nonzero if SYMBOL is marked as being dllimport 'd .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"shouldAssumeDSOLocal gave inconsistent answer"

Classify a global function reference for the current subtarget .


<s> TargetTransformInfo VETargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( VETTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static void * rs6000_init_cost ( struct loop * loop_info ) { rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = 0 ; data -> cost [ vect_body ] = 0 ; data -> cost [ vect_epilogue ] = 0 ; rs6000_vect_nonmem = false ; return data ; } </s>


<s> const X86InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> EVT Cpu0TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> tree ix86_vectorize_builtin_gather ( const_tree mem_vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX2 || ( known_eq ( TYPE_VECTOR_SUBPARTS ( mem_vectype ) , 2u ) ? ! TARGET_USE_GATHER_2PARTS : ( known_eq ( TYPE_VECTOR_SUBPARTS ( mem_vectype ) , 4u ) ? ! TARGET_USE_GATHER_4PARTS : ! TARGET_USE_GATHER ) ) ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( mem_vectype ) ) { case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DF : IX86_BUILTIN_GATHER3DIV2DF ; else code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DF : IX86_BUILTIN_GATHER3DIV4DF ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DI : IX86_BUILTIN_GATHER3DIV2DI ; else code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DI : IX86_BUILTIN_GATHER3DIV4DI ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SF : IX86_BUILTIN_GATHER3DIV4SF ; else code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SF : IX86_BUILTIN_GATHER3ALTDIV8SF ; else code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SI : IX86_BUILTIN_GATHER3DIV4SI ; else code = si ? IX86_BUILTIN_GATHERSIV4SI : IX86_BUILTIN_GATHERDIV4SI ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SI : IX86_BUILTIN_GATHER3ALTDIV8SI ; else code = si ? IX86_BUILTIN_GATHERSIV8SI : IX86_BUILTIN_GATHERALTDIV8SI ; break ; case E_V8DFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DF : IX86_BUILTIN_GATHER3DIV8DF ; else return NULL_TREE ; break ; case E_V8DImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DI : IX86_BUILTIN_GATHER3DIV8DI ; else return NULL_TREE ; break ; case E_V16SFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SF : IX86_BUILTIN_GATHER3ALTDIV16SF ; else return NULL_TREE ; break ; case E_V16SImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SI : IX86_BUILTIN_GATHER3ALTDIV16SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return ix86_get_builtin ( code ) ; } </s>

Returns a decl of a function that implements gather load with memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE . Return NULL_TREE if it is not available .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
MipsSubtarget
::
O32
:
return
"abi32"
;
case
MipsSubtarget
::
N32
:
return
"abiN32"
;
case
MipsSubtarget
::
N64
:
return
"abi64"
;
case
MipsSubtarget
::
EABI
:
return
"eabi32"
;
default
:
llvm_unreachable
(
"Unknown Mips ABI"
)
;
;
}
}
</s>


<s> bool AArch64TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( Imm . isPosZero ( ) && ( VT == MVT :: f64 || VT == MVT :: f32 ) ) return true ; if ( VT == MVT :: f64 ) return AArch64_AM :: getFP64Imm ( Imm ) != - 1 ; else if ( VT == MVT :: f32 ) return AArch64_AM :: getFP32Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) { return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) >= TLS_MODEL_REAL ) ; } </s>

Return true if X is a symbol that refers to real ( rather than emulated ) TLS .


<s>
bool
AArch64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
if
(
!
BranchRelaxation
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64BranchRelaxation *****\n"
)
;
TII
=
(
const
AArch64InstrInfo
*
)
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
)
;
DEBUG
(
dumpBBs
(
)
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n"
)
;
DEBUG
(
dbgs
(
)
<<
'\n'
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


"%qE attribute only applies to functions"

"%qs and %qs attributes are not compatible"

Handle a `` ms_abi '' or `` sysv '' attribute ; arguments as in struct attribute_spec.handler .


<s> int sparc_split_regreg_legitimate ( rtx reg1 , rtx reg2 ) { int regno1 , regno2 ; if ( GET_CODE ( reg1 ) == SUBREG ) reg1 = SUBREG_REG ( reg1 ) ; if ( GET_CODE ( reg1 ) != REG ) return 0 ; regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return 0 ; regno2 = REGNO ( reg2 ) ; if ( SPARC_INT_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) return 1 ; if ( TARGET_VIS3 ) { if ( ( SPARC_INT_REG_P ( regno1 ) && SPARC_FP_REG_P ( regno2 ) ) || ( SPARC_FP_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) ) return 1 ; } return 0 ; } </s>

Like sparc_splitdi_legitimate but for REG < -- > REG moves .


<s> static bool rs6000_cannot_substitute_mem_equiv_p ( rtx mem ) { gcc_assert ( MEM_P ( mem ) ) ; if ( GET_CODE ( XEXP ( mem , 0 ) ) == AND ) return true ; return false ; } </s>


<s> static void ix86_emit_save_regs ( void ) { unsigned int regno ; rtx insn ; for ( regno = FIRST_PSEUDO_REGISTER ; regno -- > 0 ; ) if ( ix86_save_reg ( regno , true ) ) { insn = emit_insn ( gen_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save registers in the prologue .


"unknown architecture specific memory model"

"HLE_ACQUIRE not used with ACQUIRE or stronger memory model"

"HLE_RELEASE not used with RELEASE or stronger memory model"

Validate target specific memory model bits in VAL .


<s> bool mips_cprestore_address_p ( rtx x , bool load_p ) { rtx given_base , required_base ; HOST_WIDE_INT given_offset , required_offset ; mips_split_plus ( x , & given_base , & given_offset ) ; mips_get_cprestore_base_and_offset ( & required_base , & required_offset , load_p ) ; return given_base == required_base && given_offset == required_offset ; } </s>

Return true if X is the load or store address of the cprestore slot ; LOAD_P says which .


<s> StringRef getPassName ( ) const override { return ARM_LOW_OVERHEAD_LOOPS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool mips_mem_fits_mode_p ( machine_mode mode , rtx x ) { return ( MEM_P ( x ) && MEM_SIZE_KNOWN_P ( x ) && MEM_SIZE ( x ) == GET_MODE_SIZE ( mode ) ) ; } </s>

Return true if X is a MEM with the same size as MODE .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return ARM :: tGPRRegisterClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> unsigned getID ( ) const { return ID ; } </s>


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> X86Subtarget & X86Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void pru_compute_frame_layout ( void ) { int regno ; HARD_REG_SET * save_mask ; int total_size ; int var_size ; int out_args_size ; int save_reg_size ; gcc_assert ( ! cfun -> machine -> initialized ) ; save_mask = & cfun -> machine -> save_mask ; CLEAR_HARD_REG_SET ( * save_mask ) ; var_size = PRU_STACK_ALIGN ( ( HOST_WIDE_INT ) get_frame_size ( ) ) ; out_args_size = PRU_STACK_ALIGN ( ( HOST_WIDE_INT ) crtl -> outgoing_args_size ) ; total_size = var_size + out_args_size ; save_reg_size = 0 ; for ( regno = 0 ; regno <= LAST_GP_REGNUM ; regno ++ ) if ( prologue_saved_reg_p ( regno ) ) { SET_HARD_REG_BIT ( * save_mask , regno ) ; save_reg_size += 1 ; } save_reg_size = PRU_STACK_ALIGN ( save_reg_size ) ; total_size += save_reg_size ; total_size += PRU_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; cfun -> machine -> total_size = total_size ; cfun -> machine -> var_size = var_size ; cfun -> machine -> out_args_size = out_args_size ; cfun -> machine -> save_reg_size = save_reg_size ; cfun -> machine -> initialized = reload_completed ; cfun -> machine -> save_regs_offset = out_args_size + var_size ; } </s>


<s> bool MipsAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getTargetData
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s> bool ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return false ; unsigned PairedPhys = 0 ; if ( Register :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } return false ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> static rtx nds32_expand_binopimm_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p , const char * name ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; int op0_num = return_p ? 1 : 0 ; int op1_num = return_p ? 2 : 1 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; if ( ! nds32_check_constant_argument ( icode , op1_num , op1 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take two operands and the second is immediate .


<s> void x86_emit_floatuns ( rtx operands [ 2 ] ) { rtx_code_label * neglab , * donelab ; rtx i0 , i1 , f0 , in , out ; machine_mode mode , inmode ; inmode = GET_MODE ( operands [ 1 ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ 0 ] ; in = force_reg ( inmode , operands [ 1 ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , 0 , neglab ) ; expand_float ( out , in , 0 ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( inmode , AND , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i0 = expand_simple_binop ( inmode , IOR , i0 , i1 , i0 , 1 , OPTAB_DIRECT ) ; expand_float ( f0 , i0 , 0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode/SImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> unsigned AArch64InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return 2 ; case AArch64 :: LDPXi : case AArch64 :: LDPDi : case AArch64 :: STPXi : case AArch64 :: STPDi : case AArch64 :: LDNPXi : case AArch64 :: LDNPDi : case AArch64 :: STNPXi : case AArch64 :: STNPDi : case AArch64 :: LDPQi : case AArch64 :: STPQi : case AArch64 :: LDNPQi : case AArch64 :: STNPQi : case AArch64 :: LDPWi : case AArch64 :: LDPSi : case AArch64 :: STPWi : case AArch64 :: STPSi : case AArch64 :: LDNPWi : case AArch64 :: LDNPSi : case AArch64 :: STNPWi : case AArch64 :: STNPSi : case AArch64 :: LDG : case AArch64 :: STGPi : case AArch64 :: LD1B_IMM : case AArch64 :: LD1H_IMM : case AArch64 :: LD1W_IMM : case AArch64 :: LD1D_IMM : case AArch64 :: ST1B_IMM : case AArch64 :: ST1H_IMM : case AArch64 :: ST1W_IMM : case AArch64 :: ST1D_IMM : case AArch64 :: LD1B_H_IMM : case AArch64 :: LD1SB_H_IMM : case AArch64 :: LD1H_S_IMM : case AArch64 :: LD1SH_S_IMM : case AArch64 :: LD1W_D_IMM : case AArch64 :: LD1SW_D_IMM : case AArch64 :: ST1B_H_IMM : case AArch64 :: ST1H_S_IMM : case AArch64 :: ST1W_D_IMM : case AArch64 :: LD1B_S_IMM : case AArch64 :: LD1SB_S_IMM : case AArch64 :: LD1H_D_IMM : case AArch64 :: LD1SH_D_IMM : case AArch64 :: ST1B_S_IMM : case AArch64 :: ST1H_D_IMM : case AArch64 :: LD1B_D_IMM : case AArch64 :: LD1SB_D_IMM : case AArch64 :: ST1B_D_IMM : return 3 ; case AArch64 :: ADDG : case AArch64 :: STGOffset : case AArch64 :: LDR_PXI : case AArch64 :: STR_PXI : return 2 ; } } </s>

Returns the index for the immediate for a given instruction .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> void ia64_split_tmode_move ( rtx operands [ ] ) { rtx in [ 2 ] , out [ 2 ] , insn ; rtx fixup [ 2 ] ; bool dead = false ; bool reversed = false ; if ( GET_CODE ( operands [ 1 ] ) == MEM && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) ) { rtx base = XEXP ( operands [ 1 ] , 0 ) ; while ( GET_CODE ( base ) != REG ) base = XEXP ( base , 0 ) ; if ( REGNO ( base ) == REGNO ( operands [ 0 ] ) ) reversed = true ; dead = true ; } if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == REG && REGNO ( operands [ 0 ] ) == REGNO ( operands [ 1 ] ) + 1 ) reversed = true ; fixup [ 0 ] = ia64_split_tmode ( in , operands [ 1 ] , reversed , dead ) ; fixup [ 1 ] = ia64_split_tmode ( out , operands [ 0 ] , reversed , dead ) ; if ( GET_CODE ( EXP ) == MEM \ && ( GET_CODE ( XEXP ( EXP , 0 ) ) == POST_MODIFY \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_INC \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_DEC ) ) \ REG_NOTES ( INSN ) = gen_rtx_EXPR_LIST ( REG_INC , \ XEXP ( XEXP ( EXP , 0 ) , 0 ) , \ REG_NOTES ( INSN ) ) insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ 0 ] , in [ 0 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 0 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 0 ] ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ 1 ] , in [ 1 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 1 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 1 ] ) ; if ( fixup [ 0 ] ) emit_insn ( fixup [ 0 ] ) ; if ( fixup [ 1 ] ) emit_insn ( fixup [ 1 ] ) ; } </s>

Split a TImode or TFmode move instruction after reload . This is used by * movtf_internal and * movti_internal .


<s> bool aarch64_can_const_movi_rtx_p ( rtx x , machine_mode mode ) { if ( ! TARGET_SIMD ) return false ; machine_mode vmode ; scalar_int_mode imode ; unsigned HOST_WIDE_INT ival ; if ( GET_CODE ( x ) == CONST_DOUBLE && SCALAR_FLOAT_MODE_P ( mode ) ) { if ( ! aarch64_reinterpret_float_as_int ( x , & ival ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; imode = int_mode_for_mode ( mode ) . require ( ) ; } else if ( GET_CODE ( x ) == CONST_INT && is_a < scalar_int_mode > ( mode , & imode ) ) ival = INTVAL ( x ) ; else return false ; int width = GET_MODE_BITSIZE ( imode ) == 64 ? 128 : 64 ; vmode = aarch64_simd_container_mode ( imode , width ) ; rtx v_op = aarch64_simd_gen_const_vector_dup ( vmode , ival ) ; return aarch64_simd_valid_immediate ( v_op , NULL ) ; } </s>

Return TRUE if rtx X is immediate constant that fits in a single MOVI immediate operation .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != 128 || isOpSuitableForLDPSTP ( LI ) ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> InstructionCost getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 21 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getSExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s>
static
void
rs6000_va_start
(
tree
valist
,
rtx
nextarg
)
{
HOST_WIDE_INT
words
,
n_gpr
,
n_fpr
;
tree
f_gpr
,
f_fpr
,
f_res
,
f_ovf
,
f_sav
;
tree
gpr
,
fpr
,
ovf
,
sav
,
t
;
if
(
DEFAULT_ABI
!=
ABI_V4
)
{
std_expand_builtin_va_start
(
valist
,
nextarg
)
;
return
;
}
f_gpr
=
TYPE_FIELDS
(
TREE_TYPE
(
va_list_type_node
)
)
;
f_fpr
=
DECL_CHAIN
(
f_gpr
)
;
f_res
=
DECL_CHAIN
(
f_fpr
)
;
f_ovf
=
DECL_CHAIN
(
f_res
)
;
f_sav
=
DECL_CHAIN
(
f_ovf
)
;
valist
=
build_simple_mem_ref
(
valist
)
;
gpr
=
build3
(
COMPONENT_REF
,
TREE_TYPE
(
f_gpr
)
,
valist
,
f_gpr
,
NULL_TREE
)
;
fpr
=
build3
(
COMPONENT_REF
,
TREE_TYPE
(
f_fpr
)
,
unshare_expr
(
valist
)
,
f_fpr
,
NULL_TREE
)
;
ovf
=
build3
(
COMPONENT_REF
,
TREE_TYPE
(
f_ovf
)
,
unshare_expr
(
valist
)
,
f_ovf
,
NULL_TREE
)
;
sav
=
build3
(
COMPONENT_REF
,
TREE_TYPE
(
f_sav
)
,
unshare_expr
(
valist
)
,
f_sav
,
NULL_TREE
)
;
words
=
crtl
->
args
.
info
.
words
;
n_gpr
=
MIN
(
crtl
->
args
.
info
.
sysv_gregno
GP_ARG_MIN_REG
,
GP_ARG_NUM_REG
)
;
n_fpr
=
MIN
(
crtl
->
args
.
info
.
fregno
FP_ARG_MIN_REG
,
FP_ARG_NUM_REG
)
;
if
(
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"va_start: words = "
HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
HOST_WIDE_INT_PRINT_DEC
", n_fpr = "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
words
,
n_gpr
,
n_fpr
)
;
if
(
cfun
->
va_list_gpr_size
)
{
t
=
build2
(
MODIFY_EXPR
,
TREE_TYPE
(
gpr
)
,
gpr
,
build_int_cst
(
NULL_TREE
,
n_gpr
)
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
if
(
cfun
->
va_list_fpr_size
)
{
t
=
build2
(
MODIFY_EXPR
,
TREE_TYPE
(
fpr
)
,
fpr
,
build_int_cst
(
NULL_TREE
,
n_fpr
)
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
if
(
call_ABI_of_interest
(
cfun
->
decl
)
)
rs6000_passes_float
=
true
;
}
t
=
make_tree
(
TREE_TYPE
(
ovf
)
,
virtual_incoming_args_rtx
)
;
if
(
words
!=
0
)
t
=
fold_build_pointer_plus_hwi
(
t
,
words
*
MIN_UNITS_PER_WORD
)
;
t
=
build2
(
MODIFY_EXPR
,
TREE_TYPE
(
ovf
)
,
ovf
,
t
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
if
(
!
cfun
->
va_list_gpr_size
&&
!
cfun
->
va_list_fpr_size
&&
n_gpr
<
GP_ARG_NUM_REG
&&
n_fpr
<
FP_ARG_V4_MAX_REG
)
return
;
t
=
make_tree
(
TREE_TYPE
(
sav
)
,
virtual_stack_vars_rtx
)
;
if
(
cfun
->
machine
->
varargs_save_offset
)
t
=
fold_build_pointer_plus_hwi
(
t
,
cfun
->
machine
->
varargs_save_offset
)
;
t
=
build2
(
MODIFY_EXPR
,
TREE_TYPE
(
sav
)
,
sav
,
t
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
</s>


<s> MipsSubtarget :: MipsSubtarget ( const TargetMachine & TM , const Module & M , const std :: string & FS , bool little ) : MipsArchVersion ( Mips1 ) , MipsABI ( O32 ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , HasABICall ( true ) , HasAbsoluteCall ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasMulDivAdd ( false ) , HasMinMax ( false ) , HasSwap ( false ) , HasBitCount ( false ) { std :: string CPU = "mips1" ; ParseSubtargetFeatures ( FS , CPU ) ; const std :: string & TT = M . getTargetTriple ( ) ; SSectionThreshold = SSThreshold ; if ( TT . find ( "linux" ) == std :: string :: npos ) IsLinux = false ; if ( TT . find ( "mipsallegrex" ) != std :: string :: npos || TT . find ( "psp" ) != std :: string :: npos ) { MipsABI = EABI ; IsSingleFloat = true ; MipsArchVersion = Mips2 ; HasVFPU = true ; HasSEInReg = true ; HasBitCount = true ; HasSwap = true ; HasCondMov = true ; } if ( NotABICall || isABI_EABI ( ) || ( TM . getRelocationModel ( ) == Reloc :: Static ) ) HasABICall = false ; if ( HasABICall && AbsoluteCall ) HasAbsoluteCall = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

Mips Mips Mips Mips Mips Mips "mips1" "linux" "mipsallegrex" "psp" Mips Mips Mips


<s> SDValue LEGTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && "Unsupported" ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_LEG ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>


<s> StringRef getPassName ( ) const override { return "CheriLoopPointerDecanonicalize" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static int ix86_return_pops_args ( tree fundecl , tree funtype , int size ) { unsigned int ccvt ; if ( TARGET_64BIT ) return 0 ; ccvt = ix86_get_callcvt ( funtype ) ; if ( ( ccvt & ( IX86_CALLCVT_STDCALL | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) != 0 && ! stdarg_p ( funtype ) ) return size ; if ( aggregate_value_p ( TREE_TYPE ( funtype ) , fundecl ) && ! ix86_keep_aggregate_return_pointer ( funtype ) ) { int nregs = ix86_function_regparm ( funtype , fundecl ) ; if ( nregs == 0 ) return GET_MODE_SIZE ( Pmode ) ; } return 0 ; } </s>

Value is the number of bytes of arguments automatically popped when returning from a subroutine call . FUNDECL is the declaration node of the function ( as a tree ) , FUNTYPE is the data type of the function ( as a tree ) , or for a library call it is an identifier node for the subroutine name . SIZE is the number of bytes of arguments passed on the stack . On the 80386 , the RTD insn may be used to pop them if the number of args is fixed , but if the number is variable then the caller must pop them all . RTD ca n't be used for library calls now because the library is compiled with the Unix compiler . Use of RTD is a selectable option , since it is incompatible with standard Unix calling sequences . If the option is not selected , the caller must always pop the args . The attribute stdcall is equivalent to RTD on a per module basis .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
static
void
ia64_globalize_decl_name
(
FILE
*
stream
,
tree
decl
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
decl
)
,
0
)
,
0
)
;
tree
version_attr
=
lookup_attribute
(
"version_id"
,
DECL_ATTRIBUTES
(
decl
)
)
;
if
(
version_attr
)
{
tree
v
=
TREE_VALUE
(
TREE_VALUE
(
version_attr
)
)
;
const
char
*
p
=
TREE_STRING_POINTER
(
v
)
;
fprintf
(
stream
,
"\t.alias %s#, \"%s{%s}\"\n"
,
name
,
name
,
p
)
;
}
targetm
.
asm_out
.
globalize_label
(
stream
,
name
)
;
if
(
TREE_CODE
(
decl
)
==
FUNCTION_DECL
)
ASM_OUTPUT_TYPE_DIRECTIVE
(
stream
,
name
,
"function"
)
;
}
</s>


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "use-soft-float" ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "use-soft-float=true" "use-soft-float=false" ARM


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .