<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; uint64_t MaxReach = ( MFFrame -> estimateStackSize ( MF ) + SystemZMC :: CallFrameSize * 2 ) ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame -> CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame -> CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"Should be saving %r15 and something else"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool aarch_mm_needs_release ( rtx const_int ) { enum memmodel model = memmodel_from_int ( INTVAL ( const_int ) ) ; return ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_acquire ( model ) ) ; } </s>

Return non-zero if the RTX representing a memory model is a memory model that needs release semantics .


<s> std :: vector < std :: pair < uint64_t , uint64_t >> X86MCInstrAnalysis :: findPltEntries ( uint64_t PltSectionVA , ArrayRef < uint8_t > PltContents , uint64_t GotPltSectionVA , const Triple & TargetTriple ) const { switch ( TargetTriple . getArch ( ) ) { case Triple :: x86 : return findX86PltEntries ( PltSectionVA , PltContents , GotPltSectionVA ) ; case Triple :: x86_64 : return findX86_64PltEntries ( PltSectionVA , PltContents ) ; default : return { } ; } } </s>

Returns ( PLT virtual address , GOT virtual address ) pairs for PLT entries .


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , class loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > 4 ) mem_count += 2 ; else mem_count += 1 ; } free ( bbs ) ; if ( mem_count && mem_count <= 32 ) return MIN ( nunroll , 32 / mem_count ) ; return nunroll ; } </s>

This function adjusts the unroll factor based on the hardware capabilities . For ex , bdver3 has a loop buffer which makes unrolling of smaller loops less important . This function decides the unroll factor using number of memory references ( value 32 is used ) as a heuristic .


<s> static void aarch64_pop_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment , rtx * cfi_ops ) { machine_mode mode = aarch64_reg_save_mode ( cfun -> decl , regno1 ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg1 , * cfi_ops ) ; if ( regno2 == INVALID_REGNUM ) { rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; } } </s>

Pop the two registers numbered REGNO1 , REGNO2 from the stack , adjusting it afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> inline unsigned int function_instance :: elements_per_vq ( unsigned int i ) const { return 128 / type_suffix ( i ) . element_bits ; } </s>

Return the number of elements of type suffix I that fit within a 128-bit block .


<s> static inline void aarch64_add_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool emit_move_imm ) { aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , delta , temp1 , temp2 , true , emit_move_imm ) ; } </s>

Add DELTA to the stack pointer , marking the instructions frame-related . TEMP1 is available as a temporary if nonnull . EMIT_MOVE_IMM is false if TEMP1 already contains abs ( DELTA ) .


"Offset must be aligned to 4 bytes because memory is "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool sh_contains_memref_p ( rtx insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( MEM_P ( * iter ) ) return true ; return false ; } </s>

Return nonzero iff INSN contains a MEM .


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; unsigned DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s> static unsigned getLinkageSize ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI || isPPC64 ) return 6 * ( isPPC64 ? 8 : 4 ) ; return 8 ; } </s>

getLinkageSize - Return the size of the PowerPC ABI linkage area .


<s>
SDValue
TOYTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

TOY
TOY
"Unimplemented operand"
ISD::GlobalAddress


<s>
const
char
*
thumb_load_double_from_address
(
rtx
*
operands
)
{
rtx
addr
;
rtx
base
;
rtx
offset
;
rtx
arg1
;
rtx
arg2
;
gcc_assert
(
GET_CODE
(
operands
[
0
]
)
==
REG
)
;
gcc_assert
(
GET_CODE
(
operands
[
1
]
)
==
MEM
)
;
addr
=
XEXP
(
operands
[
1
]
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
if
(
REGNO
(
operands
[
0
]
)
==
REGNO
(
addr
)
)
{
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
}
else
{
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
}
break
;
case
CONST
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
break
;
case
PLUS
:
arg1
=
XEXP
(
addr
,
0
)
;
arg2
=
XEXP
(
addr
,
1
)
;
if
(
CONSTANT_P
(
arg1
)
)
base
=
arg2
,
offset
=
arg1
;
else
base
=
arg1
,
offset
=
arg2
;
gcc_assert
(
GET_CODE
(
base
)
==
REG
)
;
if
(
GET_CODE
(
offset
)
==
REG
)
{
int
reg_offset
=
REGNO
(
offset
)
;
int
reg_base
=
REGNO
(
base
)
;
int
reg_dest
=
REGNO
(
operands
[
0
]
)
;
asm_fprintf
(
asm_out_file
,
"\tadd\t%r, %r, %r"
,
reg_dest
+
1
,
reg_base
,
reg_offset
)
;
asm_fprintf
(
asm_out_file
,
"\tldr\t%r, [%r, #0]"
,
reg_dest
,
reg_dest
+
1
)
;
asm_fprintf
(
asm_out_file
,
"\tldr\t%r, [%r, #4]"
,
reg_dest
+
1
,
reg_dest
+
1
)
;
}
else
{
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
if
(
REGNO
(
operands
[
0
]
)
==
REGNO
(
base
)
)
{
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
}
else
{
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
}
}
break
;
case
LABEL_REF
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
""
;
}
</s>

Handle the case of a double word load into a low register from a computed memory address . The computed address may involve a register which is overwritten by the load .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"IA64 (Itanium) Bundling Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc Sparc Sparc Sparc Sparc Sparc SP::SAVEri SP::SAVErr 0 SP::ADDri SP::ADDrr SP SP::I6 SP::I7 SP::O7


"missing or badly formed return type.\n"

"return type: isvoid = %d, isconst = %d, isvector = %d, "

"issigned = %d, isunsigned = %d, isbool = %d, ispixel = %d, "

"ispointer = %d, base = %d, restr = %d, val1 = \"%s\", "

Parse a function prototype . This code is shared by the bif and overload file processing .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Thumb IT blocks insertion pass"
;
}
</s>


<s> virtual const MipsRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void sh_set_return_address ( rtx ra , rtx tmp ) { HARD_REG_SET live_regs_mask ; int d ; int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ; int pr_offset ; d = calc_live_regs ( & live_regs_mask ) ; if ( ! TEST_HARD_REG_BIT ( live_regs_mask , pr_reg ) ) { rtx rr ; if ( TARGET_SHMEDIA ) { int rr_regno = sh_media_register_for_return ( ) ; if ( rr_regno < 0 ) rr_regno = pr_reg ; rr = gen_rtx_REG ( DImode , rr_regno ) ; } else rr = gen_rtx_REG ( SImode , pr_reg ) ; emit_insn ( GEN_MOV ( rr , ra ) ) ; emit_insn ( gen_rtx_USE ( VOIDmode , rr ) ) ; return ; } if ( TARGET_SH5 ) { int offset ; save_schedule schedule ; save_entry * entry ; entry = sh5_schedule_saves ( & live_regs_mask , & schedule , 0 ) ; offset = entry [ 1 ] . offset ; for ( ; entry -> mode != VOIDmode ; entry -- ) if ( entry -> reg == pr_reg ) goto found ; gcc_unreachable ( ) ; found : offset = entry -> offset - offset ; pr_offset = ( rounded_frame_size ( d ) + offset + SHMEDIA_REGS_STACK_ADJUST ( ) ) ; } else pr_offset = rounded_frame_size ( d ) ; emit_insn ( GEN_MOV ( tmp , GEN_INT ( pr_offset ) ) ) ; emit_insn ( GEN_ADD3 ( tmp , tmp , hard_frame_pointer_rtx ) ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_insn ( GEN_MOV ( tmp , ra ) ) ; } </s>

Emit code to change the current function 's return address to RA . TEMP is available as a scratch register , if needed .


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = 0 ; if ( F . hasFnAttribute ( "prefer-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "prefer-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( "min-legal-vector-width" ) ) { StringRef Val = F . getFnAttribute ( "min-legal-vector-width" ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += ",min-legal-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVtgpr2gpr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVgpr2tgpr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s>
unsigned
X86TTI
::
getScalarizationOverhead
(
Type
*
Ty
,
bool
Insert
,
bool
Extract
)
const
{
assert
(
Ty
->
isVectorTy
(
)
&&
"Can only scalarize vectors"
)
;
unsigned
Cost
=
0
;
for
(
int
i
=
0
,
e
=
Ty
->
getVectorNumElements
(
)
;
i
<
e
;
++
i
)
{
if
(
Insert
)
Cost
+=
TopTTI
->
getVectorInstrCost
(
Instruction
::
InsertElement
,
Ty
,
i
)
;
if
(
Extract
)
Cost
+=
TopTTI
->
getVectorInstrCost
(
Instruction
::
ExtractElement
,
Ty
,
i
)
;
}
return
Cost
;
}
</s>

Estimate the overhead of scalarizing an instruction .


<s> bool isMem ( ) const override { return false ; } </s>


"target %s %qs does not accept an argument"

"target %s %qs does not allow a negated form"

Parse ARG_STR which contains the definition of one target attribute . Show appropriate errors if any or return true if the attribute is valid . PRAGMA_OR_ATTR holds the string to use in error messages about whether we 're processing a target attribute or pragma .


Emit a signed or unsigned V8QI dot product operation .


<s> static bool i386_asm_output_addr_const_extra ( FILE * file , rtx x ) { rtx op ; if ( GET_CODE ( x ) != UNSPEC ) return false ; op = XVECEXP ( x , 0 , 0 ) ; switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTTPOFF : output_addr_const ( file , op ) ; fputs ( "@gottpoff" , file ) ; break ; case UNSPEC_TPOFF : output_addr_const ( file , op ) ; fputs ( "@tpoff" , file ) ; break ; case UNSPEC_NTPOFF : output_addr_const ( file , op ) ; if ( TARGET_64BIT ) fputs ( "@tpoff" , file ) ; else fputs ( "@ntpoff" , file ) ; break ; case UNSPEC_DTPOFF : output_addr_const ( file , op ) ; fputs ( "@dtpoff" , file ) ; break ; case UNSPEC_GOTNTPOFF : output_addr_const ( file , op ) ; if ( TARGET_64BIT ) fputs ( ASSEMBLER_DIALECT == ASM_ATT ? "@gottpoff(%rip)" : "@gottpoff[rip]" , file ) ; else fputs ( "@gotntpoff" , file ) ; break ; case UNSPEC_INDNTPOFF : output_addr_const ( file , op ) ; fputs ( "@indntpoff" , file ) ; break ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , op ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; break ; case UNSPEC_STACK_CHECK : { int offset ; gcc_assert ( flag_split_stack ) ; offset = TARGET_THREAD_SPLIT_STACK_OFFSET ; gcc_unreachable ( ) ; fprintf ( file , "%s:%d" , TARGET_64BIT ? "%fs" : "%gs" , offset ) ; } break ; default : return false ; } return true ; } </s>

Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; return val > - 256 && val < 256 && ( val & 3 ) == 0 ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s> Value * AArch64TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return TargetLowering :: getIRStackGuard ( IRB ) ; const unsigned TlsOffset = 0x28 ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * ThreadPointerFunc = Intrinsic :: getDeclaration ( M , Intrinsic :: thread_pointer ) ; return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( 0 ) ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> SDValue X86TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , unsigned Depth ) const { if ( SDValue Arg = isFNEG ( DAG , Op . getNode ( ) , Depth ) ) return DAG . getBitcast ( Op . getValueType ( ) , Arg ) ; EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case ISD :: FMA : case X86ISD :: FMSUB : case X86ISD :: FNMADD : case X86ISD :: FNMSUB : case X86ISD :: FMADD_RND : case X86ISD :: FMSUB_RND : case X86ISD :: FNMADD_RND : case X86ISD :: FNMSUB_RND : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == MVT :: f32 || SVT == MVT :: f64 ) || ! isOperationLegal ( ISD :: FMA , VT ) ) break ; SmallVector < SDValue , 4 > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = 0 ; i != 3 ; ++ i ) { NegatibleCost V = getNegatibleCost ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; if ( V == NegatibleCost :: Cheaper ) NewOps [ i ] = getNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ; } bool NegA = ! ! NewOps [ 0 ] ; bool NegB = ! ! NewOps [ 1 ] ; bool NegC = ! ! NewOps [ 2 ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; for ( int i = 0 , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; } case X86ISD :: FRCP : return DAG . getNode ( Opc , SDLoc ( Op ) , VT , getNegatedExpression ( Op . getOperand ( 0 ) , DAG , LegalOperations , ForCodeSize , Depth + 1 ) ) ; } return TargetLowering :: getNegatedExpression ( Op , DAG , LegalOperations , ForCodeSize , Depth ) ; } </s>

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation .


"Can't break virtual register dependencies."

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg 32 32 ISD::InputArg 32 PPC PPC PPC


<s> bool ARMTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size == 64 ) && ! Subtarget -> isMClass ( ) ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> static bool mips_load_call_address ( enum mips_call_type type , rtx dest , rtx addr ) { if ( TARGET_EXPLICIT_RELOCS && ! ( type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP ) && mips_ok_for_lazy_binding_p ( addr ) ) { addr = mips_got_load ( dest , addr , SYMBOL_GOTOFF_CALL ) ; emit_insn ( gen_rtx_SET ( dest , addr ) ) ; return true ; } else { mips_emit_move ( dest , addr ) ; return false ; } } </s>

Load function address ADDR into register DEST . SIBCALL_P is true if the address is needed for a sibling call .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute TuneAttr = F . getFnAttribute ( "tune-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) : ( StringRef ) CPU ; StringRef FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; unsigned PreferVectorWidthOverride = 0 ; Attribute PreferVecWidthAttr = F . getFnAttribute ( "prefer-vector-width" ) ; if ( PreferVecWidthAttr . isValid ( ) ) { StringRef Val = PreferVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += "prefer-vector-width=" ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; Attribute MinLegalVecWidthAttr = F . getFnAttribute ( "min-legal-vector-width" ) ; if ( MinLegalVecWidthAttr . isValid ( ) ) { StringRef Val = MinLegalVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += "min-legal-vector-width=" ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; Key += "tune=" ; Key += TuneCPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : "+soft-float," ; Key += FS ; FS = Key . substr ( FSStart ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , TuneCPU , FS , * this , MaybeAlign ( Options . StackAlignmentOverride ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>


<s> ARMPLT1 * ARMPLT :: create ( ) { ARMPLT1 * plt1_entry = new ( std :: nothrow ) ARMPLT1 ( * m_pSectionData ) ; if ( ! plt1_entry ) fatal ( diag :: fail_allocate_memory_plt ) ; return plt1_entry ; } </s>


<s> int64_t getOffset ( ) { return Offset ; } </s>

Get the offest of a string in the string table .


<s> rtx function_expander :: use_exact_insn ( insn_code icode ) { unsigned int nops = insn_data [ icode ] . n_operands ; if ( ! function_returns_void_p ( ) ) { add_output_operand ( icode ) ; nops -= 1 ; } for ( unsigned int i = 0 ; i < nops ; ++ i ) add_input_operand ( icode , args [ i ] ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , with a 1:1 mapping between arguments and input operands .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? support :: endian :: read32le ( Bytes . data ( ) ) : support :: endian :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } else if ( STI . getFeatureBits ( ) [ PPC :: FeatureSPE ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .

PowerPC PPC 4 4 0 support::endian support::endian PPC::FeatureQPX PPC::FeatureSPE


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addPreserved < MachineModuleInfo > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; } </s>


<s> Optional < Value * > ARMTTIImpl :: simplifyDemandedVectorEltsIntrinsic ( InstCombiner & IC , IntrinsicInst & II , APInt OrigDemandedElts , APInt & UndefElts , APInt & UndefElts2 , APInt & UndefElts3 , std :: function < void ( Instruction * , unsigned , APInt , APInt & ) > SimplifyAndSetOp ) const { auto SimplifyNarrowInstrTopBottom = [ & ] ( unsigned TopOpc ) { unsigned NumElts = cast < FixedVectorType > ( II . getType ( ) ) -> getNumElements ( ) ; unsigned IsTop = cast < ConstantInt > ( II . getOperand ( TopOpc ) ) -> getZExtValue ( ) ; APInt DemandedElts = APInt :: getSplat ( NumElts , IsTop ? APInt :: getLowBitsSet ( 2 , 1 ) : APInt :: getHighBitsSet ( 2 , 1 ) ) ; SimplifyAndSetOp ( & II , 0 , OrigDemandedElts & DemandedElts , UndefElts ) ; UndefElts &= APInt :: getSplat ( NumElts , ! IsTop ? APInt :: getLowBitsSet ( 2 , 1 ) : APInt :: getHighBitsSet ( 2 , 1 ) ) ; return None ; } ; switch ( II . getIntrinsicID ( ) ) { default : break ; case Intrinsic :: arm_mve_vcvt_narrow : SimplifyNarrowInstrTopBottom ( 2 ) ; break ; case Intrinsic :: arm_mve_vqmovn : SimplifyNarrowInstrTopBottom ( 4 ) ; break ; case Intrinsic :: arm_mve_vshrn : SimplifyNarrowInstrTopBottom ( 7 ) ; break ; } return None ; } </s>

Can be used to implement target-specific instruction combining .


<s> static bool rs6000_emit_move_si_sf_subreg ( rtx dest , rtx source , machine_mode mode ) { if ( TARGET_DIRECT_MOVE_64BIT && ! reload_in_progress && ! reload_completed && ! lra_in_progress && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) { rtx inner_source = SUBREG_REG ( source ) ; machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ; return true ; } } return false ; } </s>

Helper function to change moves with : ( SUBREG : SF ( REG : SI ) ) and ( SUBREG : SI ( REG : SF ) ) into separate UNSPEC insns . In the PowerPC architecture , scalar SFmode values are stored as DFmode values in the VSX registers . We need to convert the bits before we can use a direct move or operate on the bits in the vector register as an integer type . Skip things like ( set ( SUBREG : SI ( ... ) ( SUBREG : SI ( ... ) ) .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
mf
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
RDA
=
&
getAnalysis
<
ReachingDefAnalysis
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
*
MLI
)
{
if
(
ML
->
isOutermost
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( NeedsWinCFI ) std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; bool UsesWinAAPCS = isTargetWindows ( MF ) ; if ( UsesWinAAPCS && hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) ) { int FrameIdx = MFI . CreateStackObject ( 8 , Align ( 16 ) , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlign ( * RC ) ) ; int FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; if ( hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) && ! UsesWinAAPCS && Reg == AArch64 :: FP ) { FrameIdx = MFI . CreateStackObject ( 8 , Alignment , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! hasMFENCE ( Subtarget ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SynchScope ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> bool X86AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO , O ) ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; printOperand ( MI , OpNo , O ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool rs6000_must_pass_in_stack ( const function_arg_info & arg ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( arg ) ; else return must_pass_in_stack_var_size_or_pad ( arg ) ; } </s>

Return true if TYPE must be passed on the stack and not in registers .


<s> bool MipsTTIImpl :: hasDivRemOp ( Type * DataType , bool IsSigned ) { EVT VT = TLI -> getValueType ( DL , DataType ) ; return TLI -> isOperationLegalOrCustom ( IsSigned ? ISD :: SDIVREM : ISD :: UDIVREM , VT ) ; } </s>

Return true if the target has a unified operation to calculate division and remainder .


<s> bool MipsCallEntry :: isConstant ( const MachineFrameInfo * ) const { return false ; } </s>

Returns true if we know the value of all bits .


<s> static void aarch64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = R0_REGNUM ; rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk ) ) ; if ( aarch64_bti_enabled ( ) ) emit_insn ( gen_bti_c ( ) ) ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; if ( vcall_offset == 0 ) aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - 1 ) ) == 0 ) ; addr = this_rtx ; if ( delta != 0 ) { if ( delta >= - 256 && delta < 256 ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - 256 && vcall_offset < 4096 * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx callee_abi = gen_int_mode ( fndecl_abi ( function ) . id ( ) , DImode ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , callee_abi ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk , fnname ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> void LanaiInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annotation , const MCSubtargetInfo & , raw_ostream & OS ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; if ( isa < ScalableVectorType > ( Ty ) ) { uint64_t VecElemNumBytes = DL . getTypeSizeInBits ( cast < VectorType > ( Ty ) -> getElementType ( ) ) / 8 ; return AM . HasBaseReg && ! AM . BaseOffs && ( AM . Scale == 0 || ( uint64_t ) AM . Scale == VecElemNumBytes ) ; } uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
||
STI
.
isTargetDarwin
(
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
markSuperRegs
(
Reserved
,
ARM
::
ZR
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
&
Mang
=
TM
.
getObjFileLowering
(
)
->
getMangler
(
)
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
Mang
)
;
}
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= InsertITBlocks ( MBB ) ; } return Modified ; } </s>


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( ! AFI || AFI -> hasRedZone ( ) . getValueOr ( true ) ) return false ; if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> static void mips16_rewrite_pool_constant ( struct mips16_constant_pool * pool , rtx * x ) { rtx base , offset ; rtx_code_label * label ; split_const ( * x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( base ) ) { label = mips16_add_constant ( pool , copy_rtx ( get_pool_constant ( base ) ) , get_pool_mode ( base ) ) ; base = gen_rtx_LABEL_REF ( Pmode , label ) ; * x = mips_unspec_address_offset ( base , offset , SYMBOL_PC_RELATIVE ) ; } } </s>

If * X is a symbolic constant that refers to the constant pool , add the constant to POOL and rewrite * X to use the constant 's label .


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
RoundUpToAlignment
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { if ( Subtarget . hasQPX ( ) && Op . size ( ) >= 32 && ( Op . isMemcpy ( ) || Op . size ( ) >= 64 ) && Op . isAligned ( Align ( 32 ) ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return MVT :: v4f64 ; } if ( Subtarget . hasAltivec ( ) && Op . size ( ) >= 16 && ( Op . isAligned ( Align ( 16 ) ) || ( ( Op . isMemset ( ) && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return MVT :: v4i32 ; } if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static int mips_move_to_gpr_cost ( reg_class_t from ) { switch ( from ) { case M16_REGS : case GENERAL_REGS : return 2 ; case ACC_REGS : return 6 ; case FP_REGS : return 4 ; case COP0_REGS : case COP2_REGS : case COP3_REGS : return 5 ; default : return 0 ; } } </s>

Return the cost of moving a value from a register of class FROM to a GPR . Return 0 for classes that are unions of other classes handled by this function .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
Modified
|=
runOnInstruction
(
&
MI
)
;
}
}
for
(
MachineInstr
*
MI
:
DeadInstr
)
{
MI
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
TargetSize
/
8
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> void ix86_avx_emit_vzeroupper ( HARD_REG_SET regs_live ) { int i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( regs_live , i ) && ! call_used_regs [ i ] ) return ; if ( TARGET_64BIT ) for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( regs_live , i ) && ! call_used_regs [ i ] ) return ; emit_insn ( gen_avx_vzeroupper ( ) ) ; } </s>


"Only Linux target is expected to contain LOAD_STACK_GUARD"

This function is called for all pseudo instructions that remain after register allocation .


<s> static struct gcc_regs * get_regs ( struct _Unwind_Context * context ) { const unsigned char * pc = context -> ra ; if ( * ( unsigned int * ) ( pc + 4 ) != 0x44000002 ) return NULL ; if ( * ( unsigned int * ) ( pc + 0 ) == 0x38007777 || * ( unsigned int * ) ( pc + 0 ) == 0x38000077 ) { struct sigframe { char gap [ SIGNAL_FRAMESIZE ] ; unsigned long pad [ 7 ] ; struct gcc_regs * regs ; } * frame = ( struct sigframe * ) context -> cfa ; return frame -> regs ; } else if ( * ( unsigned int * ) ( pc + 0 ) == 0x38006666 || * ( unsigned int * ) ( pc + 0 ) == 0x380000AC ) { struct rt_sigframe { char gap [ SIGNAL_FRAMESIZE + 16 ] ; char siginfo [ 128 ] ; struct gcc_ucontext uc ; } * frame = ( struct rt_sigframe * ) context -> cfa ; return frame -> uc . regs ; } return NULL ; } </s>

If PC is at a sigreturn trampoline , return a pointer to the regs . Otherwise return NULL .


<s> int borx_reg_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) != REG ) return 0 ; if ( op == virtual_incoming_args_rtx || op == virtual_stack_vars_rtx || op == virtual_stack_dynamic_rtx || op == virtual_outgoing_args_rtx || op == virtual_cfa_rtx ) return 0 ; if ( ! reload_completed && flag_omit_frame_pointer && ! current_function_calls_alloca && op == frame_pointer_rtx ) return 0 ; return register_operand ( op , mode ) ; } </s>

Return 1 if OP is valid as a base or index register in a REG+REG address .


"2003f Eliminate Pseudo Instr FI_MALKRZ"

getPassName - Return a nice clean name for a pass .


<s> rtx function_expander :: use_contiguous_store_insn ( insn_code icode ) { machine_mode mem_mode = memory_vector_mode ( ) ; add_mem_operand ( mem_mode , get_contiguous_base ( mem_mode ) ) ; add_input_operand ( icode , args . last ( ) ) ; add_input_operand ( icode , args [ 0 ] ) ; return generate_insn ( icode ) ; } </s>


<s> void ARMAsmPrinter :: emitStartOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; OutStreamer -> emitAssemblerFlag ( MCAF_SyntaxUnified ) ; if ( TT . isOSBinFormatELF ( ) ) emitAttributes ( ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) && TT . isThumb ( ) ) OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> static void ix86_emit_save_regs_using_mov ( rtx pointer , HOST_WIDE_INT offset ) { unsigned int regno ; rtx insn ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ix86_save_reg ( regno , true ) ) { insn = emit_move_insn ( adjust_address ( gen_rtx_MEM ( Pmode , pointer ) , Pmode , offset ) , gen_rtx_REG ( Pmode , regno ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; offset += UNITS_PER_WORD ; } } </s>

Emit code to save registers using MOV insns . First register is restored from POINTER + OFFSET .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr & MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex , LiveIntervals * LIS ) const { if ( NoFusing ) return nullptr ; if ( ! MF . getFunction ( ) -> optForSize ( ) && hasPartialRegUpdate ( MI . getOpcode ( ) ) ) return nullptr ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Size = MFI . getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI . getObjectAlignment ( FrameIndex ) ; if ( ! RI . needsStackRealignment ( MF ) ) Alignment = std :: min ( Alignment , Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ) ; if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; unsigned RCSize = 0 ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; RCSize = 1 ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri8 ; RCSize = 2 ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri8 ; RCSize = 4 ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri8 ; RCSize = 8 ; break ; } if ( Size < RCSize ) return nullptr ; MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return nullptr ; return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MachineOperand :: CreateFI ( FrameIndex ) , InsertPt , Size , Alignment , true ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool MipsPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } </s>


<s> static bool insn_terminates_group_p ( rtx_insn * insn , enum group_termination which_group ) { bool first , last ; if ( ! insn ) return false ; first = insn_must_be_first_in_group ( insn ) ; last = insn_must_be_last_in_group ( insn ) ; if ( first && last ) return true ; if ( which_group == current_group ) return last ; else if ( which_group == previous_group ) return first ; return false ; } </s>

Return whether the presence of INSN causes a dispatch group termination of group WHICH_GROUP . If WHICH_GROUP == current_group , this function will return true if INSN causes the termination of the current group ( i.e , the dispatch group to which INSN belongs ) . This means that INSN will be the last insn in the group it belongs to . If WHICH_GROUP == previous_group , this function will return true if INSN causes the termination of the previous group ( i.e , the dispatch group that precedes the group to which INSN belongs ) . This means that INSN will be the first insn in the group it belongs to ) .


<s> static rtx sparc_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ) { return sparc_function_value_1 ( valtype , TYPE_MODE ( valtype ) , outgoing ) ; } </s>

Handle TARGET_FUNCTION_VALUE . On the SPARC , the value is found in the first `` output '' register , but the called function leaves it in the first `` input '' register .


<s>
bool
CAHPInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;
bool
ShouldSwap
=
false
;
switch
(
Cond
[
0
]
.
getImm
(
)
)
{
case
CAHP
::
BEQ
:
Cond
[
0
]
.
setImm
(
CAHP
::
BNE
)
;
break
;
case
CAHP
::
BNE
:
Cond
[
0
]
.
setImm
(
CAHP
::
BEQ
)
;
break
;
case
CAHP
::
BLT
:
Cond
[
0
]
.
setImm
(
CAHP
::
BLE
)
;
ShouldSwap
=
true
;
break
;
case
CAHP
::
BLE
:
Cond
[
0
]
.
setImm
(
CAHP
::
BLT
)
;
ShouldSwap
=
true
;
break
;
case
CAHP
::
BLTU
:
Cond
[
0
]
.
setImm
(
CAHP
::
BLEU
)
;
ShouldSwap
=
true
;
break
;
case
CAHP
::
BLEU
:
Cond
[
0
]
.
setImm
(
CAHP
::
BLTU
)
;
ShouldSwap
=
true
;
break
;
}
if
(
ShouldSwap
)
{
using
std
::
swap
;
swap
(
Cond
[
1
]
,
Cond
[
2
]
)
;
}
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


"ADJSTACKDOWN and ADJSTACKUP should be no-ops"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> EVT X86TargetLowering :: getTypeForExtReturn ( LLVMContext & Context , EVT VT , ISD :: NodeType ExtendKind ) const { MVT ReturnMVT = MVT :: i32 ; bool Darwin = Subtarget . getTargetTriple ( ) . isOSDarwin ( ) ; if ( VT == MVT :: i1 || ( ! Darwin && ( VT == MVT :: i8 || VT == MVT :: i16 ) ) ) { ReturnMVT = MVT :: i8 ; } EVT MinVT = getRegisterType ( Context , ReturnMVT ) ; return VT . bitsLT ( MinVT ) ? MinVT : VT ; } </s>

Return the type that should be used to zero or sign extend a zeroext/signext integer return value .


<s>
bool
PPCTargetLowering
::
enableAggressiveFMAFusion
(
EVT
VT
)
const
{
assert
(
VT
.
isFloatingPoint
(
)
&&
"Non-floating-point FMA?"
)
;
return
true
;
}
</s>

Return true if target always benefits from combining into FMA for a given value type .


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDH_OP1 : case MachineCombinerPattern :: FMULADDH_OP2 : case MachineCombinerPattern :: FMULSUBH_OP1 : case MachineCombinerPattern :: FMULSUBH_OP2 : case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBH_OP1 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f16_OP1 : case MachineCombinerPattern :: FMLSv4f16_OP2 : case MachineCombinerPattern :: FMLSv8f16_OP1 : case MachineCombinerPattern :: FMLSv8f16_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : case MachineCombinerPattern :: MULADDv8i8_OP1 : case MachineCombinerPattern :: MULADDv8i8_OP2 : case MachineCombinerPattern :: MULADDv16i8_OP1 : case MachineCombinerPattern :: MULADDv16i8_OP2 : case MachineCombinerPattern :: MULADDv4i16_OP1 : case MachineCombinerPattern :: MULADDv4i16_OP2 : case MachineCombinerPattern :: MULADDv8i16_OP1 : case MachineCombinerPattern :: MULADDv8i16_OP2 : case MachineCombinerPattern :: MULADDv2i32_OP1 : case MachineCombinerPattern :: MULADDv2i32_OP2 : case MachineCombinerPattern :: MULADDv4i32_OP1 : case MachineCombinerPattern :: MULADDv4i32_OP2 : case MachineCombinerPattern :: MULSUBv8i8_OP1 : case MachineCombinerPattern :: MULSUBv8i8_OP2 : case MachineCombinerPattern :: MULSUBv16i8_OP1 : case MachineCombinerPattern :: MULSUBv16i8_OP2 : case MachineCombinerPattern :: MULSUBv4i16_OP1 : case MachineCombinerPattern :: MULSUBv4i16_OP2 : case MachineCombinerPattern :: MULSUBv8i16_OP1 : case MachineCombinerPattern :: MULSUBv8i16_OP2 : case MachineCombinerPattern :: MULSUBv2i32_OP1 : case MachineCombinerPattern :: MULSUBv2i32_OP2 : case MachineCombinerPattern :: MULSUBv4i32_OP1 : case MachineCombinerPattern :: MULSUBv4i32_OP2 : case MachineCombinerPattern :: MULADDv4i16_indexed_OP1 : case MachineCombinerPattern :: MULADDv4i16_indexed_OP2 : case MachineCombinerPattern :: MULADDv8i16_indexed_OP1 : case MachineCombinerPattern :: MULADDv8i16_indexed_OP2 : case MachineCombinerPattern :: MULADDv2i32_indexed_OP1 : case MachineCombinerPattern :: MULADDv2i32_indexed_OP2 : case MachineCombinerPattern :: MULADDv4i32_indexed_OP1 : case MachineCombinerPattern :: MULADDv4i32_indexed_OP2 : case MachineCombinerPattern :: MULSUBv4i16_indexed_OP1 : case MachineCombinerPattern :: MULSUBv4i16_indexed_OP2 : case MachineCombinerPattern :: MULSUBv8i16_indexed_OP1 : case MachineCombinerPattern :: MULSUBv8i16_indexed_OP2 : case MachineCombinerPattern :: MULSUBv2i32_indexed_OP1 : case MachineCombinerPattern :: MULSUBv2i32_indexed_OP2 : case MachineCombinerPattern :: MULSUBv4i32_indexed_OP1 : case MachineCombinerPattern :: MULSUBv4i32_indexed_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


<s> rtx sh_try_omit_signzero_extend ( rtx extended_op , rtx_insn * insn ) { if ( REG_P ( extended_op ) ) extended_op = extended_op ; else if ( GET_CODE ( extended_op ) == SUBREG && REG_P ( SUBREG_REG ( extended_op ) ) ) extended_op = SUBREG_REG ( extended_op ) ; else return NULL_RTX ; if ( GET_MODE ( extended_op ) != SImode ) return NULL_RTX ; set_of_reg s = sh_find_set_of_reg ( extended_op , insn , prev_nonnote_insn_bb ) ; if ( s . set_src == NULL_RTX ) return NULL_RTX ; if ( t_reg_operand ( s . set_src , VOIDmode ) || negt_reg_operand ( s . set_src , VOIDmode ) ) return extended_op ; else if ( sh_is_logical_t_store_expr ( s . set_src , s . insn ) ) return extended_op ; return NULL_RTX ; } </s>

Given the operand that is extended in a sign/zero extend insn , and the insn , try to figure out whether the sign/zero extension can be replaced by a simple reg-reg copy . If so , the replacement reg rtx is returned , NULL_RTX otherwise .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_SBFX
:
case
TargetOpcode
::
G_UBFX
:
return
legalizeBitfieldExtract
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ROTR
:
return
legalizeRotate
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTPOP
:
return
legalizeCTPOP
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpxchg128
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTTZ
:
return
legalizeCTTZ
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_BZERO
:
case
TargetOpcode
::
G_MEMCPY
:
case
TargetOpcode
::
G_MEMMOVE
:
case
TargetOpcode
::
G_MEMSET
:
return
legalizeMemOps
(
MI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> TargetLowering :: ConstraintWeight FISCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'c' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; if ( ! LogAlign ) return PO ; return PO + UnknownPadding ( LogAlign , internalKnownBits ( ) ) ; } </s>

Compute the offset immediately following this block .


<s>
static
void
aarch64_start_file
(
void
)
{
if
(
selected_arch
)
{
asm_fprintf
(
asm_out_file
,
"\t.arch %s"
,
selected_arch
->
name
)
;
aarch64_print_extension
(
)
;
}
else
if
(
selected_cpu
)
{
const
char
*
truncated_name
=
aarch64_rewrite_selected_cpu
(
selected_cpu
->
name
)
;
asm_fprintf
(
asm_out_file
,
"\t.cpu %s"
,
truncated_name
)
;
aarch64_print_extension
(
)
;
}
default_file_start
(
)
;
}
</s>

Implements TARGET_ASM_FILE_START . Output the assembly header .


<s> Val ( unsigned int Op , std :: vector < unsigned int > Nums ) : Op ( Op ) , Nums ( Nums ) { } </s>


"__attribute__ ((__used__, visibility (\"hidden\"),\n"

"section (\".gnu.offload_funcs\"))) = { };\n\n"

"section (\".gnu.offload_vars\"))) = { };\n\n"

"__attribute__ ((__used__, visibility (\"hidden\"))) = {\n"

"  &__offload_func_table, &__offload_funcs_end,\n"

"  &__offload_var_table, &__offload_vars_end\n"

"void target_register_lib (const void *);\n\n"

"  target_register_lib (__OFFLOAD_TARGET_TABLE__);\n"

Generates object file with the descriptor for the target library .


<s> static int thumb_find_work_register ( unsigned long pushed_regs_mask ) { int reg ; for ( reg = LAST_ARG_REGNUM ; reg >= 0 ; reg -- ) if ( ! df_regs_ever_live_p ( reg ) ) return reg ; if ( cfun -> machine -> uses_anonymous_args && crtl -> args . pretend_args_size > 0 ) return LAST_ARG_REGNUM ; if ( ! cfun -> machine -> uses_anonymous_args && crtl -> args . size >= 0 && crtl -> args . size <= ( LAST_ARG_REGNUM * UNITS_PER_WORD ) && ( TARGET_AAPCS_BASED ? crtl -> args . info . aapcs_ncrn < 4 : crtl -> args . info . nregs < 4 ) ) return LAST_ARG_REGNUM ; for ( reg = LAST_LO_REGNUM ; reg > LAST_ARG_REGNUM ; reg -- ) if ( pushed_regs_mask & ( 1 << reg ) ) return reg ; if ( TARGET_THUMB2 ) { for ( reg = FIRST_HI_REGNUM ; reg < 15 ; reg ++ ) if ( pushed_regs_mask & ( 1 << reg ) ) return reg ; } gcc_unreachable ( ) ; } </s>

Find a spare low register to use during the prolog of a function .


<s> bool X86FastISel :: isTypeLegal ( const Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> bool aarch64_and_bitmask_imm ( unsigned HOST_WIDE_INT val_in , machine_mode mode ) { scalar_int_mode int_mode ; if ( ! is_a < scalar_int_mode > ( mode , & int_mode ) ) return false ; if ( aarch64_bitmask_imm ( val_in , int_mode ) ) return false ; if ( aarch64_move_imm ( val_in , int_mode ) ) return false ; unsigned HOST_WIDE_INT imm2 = aarch64_and_split_imm2 ( val_in ) ; return aarch64_bitmask_imm ( imm2 , int_mode ) ; } </s>

Return true if VAL_IN is a valid 'and ' bitmask immediate .


"getBranchTarget26OpValue expects only expressions or immediates"

getBranchTarget26OpValue - Return binary encoding of the branch target operand .


"the layout of aggregates containing vectors with"

" %d-byte alignment has changed in GCC 5"

Previous GCC releases forced all vector types to have 16-byte alignment .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
IMMEDIATE
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
TOKEN
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
REGISTER
:
OS
<<
"Reg: %r"
<<
getReg
(
)
<<
"\n"
;
break
;
case
MEMORY_IMM
:
OS
<<
"MemImm: "
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
MEMORY_REG_IMM
:
OS
<<
"MemRegImm: "
<<
getMemBaseReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
MEMORY_REG_REG
:
assert
(
getMemOffset
(
)
==
nullptr
)
;
OS
<<
"MemRegReg: "
<<
getMemBaseReg
(
)
<<
"+"
<<
"%r"
<<
getMemOffsetReg
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

DLX
"Imm: "
"\n"
"Token: "
"\n"
"Reg: %r"
"\n"
"MemImm: "
"\n"
"MemRegImm: "
"+"
"\n"
"MemRegReg: "
"+"
"%r"
"\n"


<s> static rtx pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style , bool set_cfa ) { struct machine_function * m = cfun -> machine ; rtx insn ; bool add_frame_related_expr = false ; if ( Pmode == SImode ) insn = gen_pro_epilogue_adjust_stack_si_add ( dest , src , offset ) ; else if ( x86_64_immediate_operand ( offset , DImode ) ) insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , offset ) ; else { rtx tmp ; if ( style ) tmp = gen_rtx_REG ( DImode , R11_REG ) ; else { gcc_assert ( src != hard_frame_pointer_rtx && dest != hard_frame_pointer_rtx ) ; tmp = hard_frame_pointer_rtx ; } insn = emit_insn ( gen_rtx_SET ( tmp , offset ) ) ; if ( style < 0 ) add_frame_related_expr = true ; insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , tmp ) ; } insn = emit_insn ( insn ) ; if ( style >= 0 ) ix86_add_queued_cfa_restore_notes ( insn ) ; if ( set_cfa ) { rtx r ; gcc_assert ( m -> fs . cfa_reg == src ) ; m -> fs . cfa_offset += INTVAL ( offset ) ; m -> fs . cfa_reg = dest ; r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , r ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else if ( style < 0 ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( add_frame_related_expr ) { rtx r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , r ) ; } } if ( dest == stack_pointer_rtx ) { HOST_WIDE_INT ooffset = m -> fs . sp_offset ; bool valid = m -> fs . sp_valid ; bool realigned = m -> fs . sp_realigned ; if ( src == hard_frame_pointer_rtx ) { valid = m -> fs . fp_valid ; realigned = false ; ooffset = m -> fs . fp_offset ; } else if ( src == crtl -> drap_reg ) { valid = m -> fs . drap_valid ; realigned = false ; ooffset = 0 ; } else { gcc_checking_assert ( src == stack_pointer_rtx || offset == const0_rtx ) ; } m -> fs . sp_offset = ooffset - INTVAL ( offset ) ; m -> fs . sp_valid = valid ; m -> fs . sp_realigned = realigned ; } return insn ; } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


<s> static Mnode * move_minipool_fix_forward_ref ( Mnode * mp , Mnode * max_mp , HOST_WIDE_INT max_address ) { gcc_assert ( mp != max_mp ) ; if ( max_mp == NULL ) { if ( max_address < mp -> max_address ) mp -> max_address = max_address ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> prev -> next = mp -> next ; if ( mp -> next != NULL ) mp -> next -> prev = mp -> prev ; else minipool_vector_tail = mp -> prev ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp = mp ; while ( mp -> prev != NULL && mp -> prev -> max_address > mp -> max_address - mp -> prev -> fix_size ) { mp -> prev -> max_address = mp -> max_address - mp -> prev -> fix_size ; mp = mp -> prev ; } return max_mp ; } </s>

Move a minipool fix MP from its current location to before MAX_MP . If MAX_MP is NULL , then MP does n't need moving , but the addressing contrains may need updating .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::BlockAddress
ISD::DYNAMIC_STACKALLOC
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::VASTART
ISD::VAARG


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 || getSVEStackSize ( MF ) ) ; } </s>

Can this function use the red zone for local allocations .


<s> uint64_t evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size ) const { unsigned LblOperand = Inst . getOpcode ( ) == AArch64 :: Bcc ? 1 : 0 ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return - 1ULL ; int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ; return Addr + Imm ; } </s>

Given a branch instruction try to get the address the branch targets .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static bool aarch64_returns_value_in_sve_regs_p ( const_tree fntype ) { tree return_type = TREE_TYPE ( fntype ) ; pure_scalable_type_info pst_info ; switch ( pst_info . analyze ( return_type ) ) { case pure_scalable_type_info :: IS_PST : return ( pst_info . num_zr ( ) <= NUM_FP_ARG_REGS && pst_info . num_pr ( ) <= NUM_PR_ARG_REGS ) ; case pure_scalable_type_info :: DOESNT_MATTER : gcc_assert ( aarch64_return_in_memory_1 ( return_type ) ) ; return false ; case pure_scalable_type_info :: NO_ABI_IDENTITY : case pure_scalable_type_info :: ISNT_PST : return false ; } gcc_unreachable ( ) ; } </s>

Return true if a function with type FNTYPE returns its value in SVE vector or predicate registers .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> perm . length ( ) ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vextv16qi ; break ; case E_V8QImode : gen = gen_neon_vextv8qi ; break ; case E_V4HImode : gen = gen_neon_vextv4hi ; break ; case E_V8HImode : gen = gen_neon_vextv8hi ; break ; case E_V2SImode : gen = gen_neon_vextv2si ; break ; case E_V4SImode : gen = gen_neon_vextv4si ; break ; case E_V4HFmode : gen = gen_neon_vextv4hf ; break ; case E_V8HFmode : gen = gen_neon_vextv8hf ; break ; case E_V2SFmode : gen = gen_neon_vextv2sf ; break ; case E_V4SFmode : gen = gen_neon_vextv4sf ; break ; case E_V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> static int neon_pair_endian_lane_map ( machine_mode mode , int lane ) { int nelem = GET_MODE_NUNITS ( mode ) ; if ( BYTES_BIG_ENDIAN ) lane = neon_endian_lane_map ( mode , lane & ( nelem - 1 ) ) + ( lane & nelem ) ; return lane ; } </s>

Some permutations index into pairs of vectors , this is a helper function to map indexes into those pairs of vectors .


<s> bool ARM64RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool ARMBaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const ARMFunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } else { if ( ( MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


"Expecting an ACC register for BUILD_UACC."

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> void SystemZXPLINKFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> int MINA32FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MINA32Subtarget & Subtarget = MF . getSubtarget < MINA32Subtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MINA32RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; FrameReg = RegInfo -> getFrameRegister ( MF ) ; int64_t FrameOffset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ; FrameOffset -= getOffsetOfLocalArea ( ) ; FrameOffset += MFI . getStackSize ( ) ; return FrameOffset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"Stack realignment in presence of dynamic allocas is not supported with"

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> rtx mips_subword ( rtx op , bool high_p ) { unsigned int byte , offset ; machine_mode mode ; mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( TARGET_BIG_ENDIAN ? ! high_p : high_p ) byte = UNITS_PER_WORD ; else byte = 0 ; if ( FP_REG_RTX_P ( op ) ) { offset = ( UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0 ) ; return gen_rtx_REG ( word_mode , REGNO ( op ) + offset ) ; } if ( MEM_P ( op ) ) return mips_rewrite_small_data ( adjust_address ( op , word_mode , byte ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ; } </s>

Return one word of double-word value OP , taking into account the fixed endianness of certain registers . HIGH_P is true to select the high part , false to select the low part .


<s> bool arm_sat_operator_match ( rtx lo_bound , rtx hi_bound , int * mask , bool * signed_sat ) { int log = exact_log2 ( INTVAL ( hi_bound ) + 1 ) ; if ( log == - 1 ) return false ; if ( INTVAL ( lo_bound ) == 0 ) { if ( mask ) * mask = log ; if ( signed_sat ) * signed_sat = false ; return true ; } if ( INTVAL ( lo_bound ) == - INTVAL ( hi_bound ) - 1 ) { if ( mask ) * mask = log + 1 ; if ( signed_sat ) * signed_sat = true ; return true ; } return false ; } </s>

Match pair of min/max operators that can be implemented via usat/ssat .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
const
Function
*
F
=
MF
->
getFunction
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
CallingConv
::
ID
CC
=
F
->
getCallingConv
(
)
;
if
(
MF
->
getFunction
(
)
->
hasFnAttribute
(
"no_caller_saved_registers"
)
)
CC
=
CallingConv
::
X86_INTR
;
switch
(
CC
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_64_AllRegs_SaveList
;
return
CSR_64_AllRegs_NoSSE_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
bool
IsSwiftCC
=
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
F
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
;
if
(
IsSwiftCC
)
return
IsWin64
CSR_Win64_SwiftError_SaveList
:
CSR_64_SwiftError_SaveList
;
if
(
IsWin64
)
return
HasSSE
CSR_Win64_SaveList
:
CSR_Win64_NoSSE_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
return
CallsEHReturn
CSR_32EHRet_SaveList
:
CSR_32_SaveList
;
}
</s>


<s> void MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsHazardSchedule ( ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsConstantIslandPass ( TM ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool MipsSEInstrInfo :: isCopyInstr ( const MachineInstr & MI , MachineOperand & Src , MachineOperand & Dest ) const { bool isDSPControlWrite = false ; if ( isReadOrWritToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || ! ( MI . getOperand ( 1 ) . getImm ( ) == ( 1 << 4 ) ) ) return false ; else if ( isDSPControlWrite ) { Src = MI . getOperand ( 0 ) ; Dest = MI . getOperand ( 2 ) ; } else { Dest = MI . getOperand ( 0 ) ; Src = MI . getOperand ( 2 ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = MI . getOperand ( 0 ) ; Src = MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> int eligible_for_sibcall_delay ( rtx trial ) { rtx pat ; if ( GET_CODE ( trial ) != INSN || GET_CODE ( PATTERN ( trial ) ) != SET ) return 0 ; if ( get_attr_length ( trial ) != 1 ) return 0 ; pat = PATTERN ( trial ) ; if ( sparc_leaf_function_p ) { if ( LEAF_SIBCALL_SLOT_RESERVED_P ) return 0 ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , 1 ) , pat ) ) return 0 ; return 1 ; } if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= 8 && REGNO ( SET_DEST ( pat ) ) < 24 ) || REGNO ( SET_DEST ( pat ) ) >= 32 ) return 0 ; if ( reg_mentioned_p ( gen_rtx_REG ( Pmode , 15 ) , pat ) ) return 0 ; return eligible_for_restore_insn ( trial , false ) ; } </s>

Return nonzero if TRIAL can go into the sibling call 's delay slot .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { AArch64FI = F . getInfo < AArch64FunctionInfo > ( ) ; STI = static_cast < const AArch64Subtarget * > ( & F . getSubtarget ( ) ) ; bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; emitXRayTable ( ) ; return Result ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
Sparc
::
NumTargetFixupKinds
]
=
{
{
"fixup_sparc_call30"
,
2
,
30
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br22"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br19"
,
13
,
19
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br16_2"
,
10
,
2
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br16_14"
,
18
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_h44"
,
10
,
22
,
0
}
,
{
"fixup_sparc_m44"
,
22
,
10
,
0
}
,
{
"fixup_sparc_l44"
,
20
,
12
,
0
}
,
{
"fixup_sparc_hh"
,
10
,
22
,
0
}
,
{
"fixup_sparc_hm"
,
22
,
10
,
0
}
,
{
"fixup_sparc_pc22"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_pc10"
,
22
,
10
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_got22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_got10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_wplt30"
,
2
,
30
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_tls_gd_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_gd_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_gd_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_gd_call"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldm_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ldm_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ldm_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldm_call"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldo_hix22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ldo_lox10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ldo_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ie_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ie_ld"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_ldx"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_le_hix22"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_le_lox10"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> const char * output_mul_insn ( int unsignedp ATTRIBUTE_UNUSED , rtx insn ) { import_milli ( mulI ) ; return output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( Pmode , "$$mulI" ) ) ; } </s>

The register constraints have put the operands and return value in the proper registers .