<s> MachineInstr * SystemZInstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MFI , MachineBasicBlock :: iterator & MBBI , LiveVariables * LV ) const { MachineInstr * MI = MBBI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Opcode = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getNumOperands ( ) ; if ( TM . getSubtargetImpl ( ) -> hasDistinctOps ( ) ) { int ThreeOperandOpcode = SystemZ :: getThreeOperandOpcode ( Opcode ) ; if ( ThreeOperandOpcode >= 0 ) { MachineOperand & Dest = MI -> getOperand ( 0 ) ; MachineOperand & Src = MI -> getOperand ( 1 ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MBBI , MI -> getDebugLoc ( ) , get ( ThreeOperandOpcode ) ) . addOperand ( Dest ) ; MIB . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) ; for ( unsigned I = 2 ; I < NumOps ; ++ I ) MIB . addOperand ( MI -> getOperand ( I ) ) ; return finishConvertToThreeAddress ( MI , MIB , LV ) ; } } if ( LogicOp And = interpretAndImmediate ( Opcode ) ) { unsigned NewOpcode ; if ( And . RegSize == 64 ) NewOpcode = SystemZ :: RISBG ; else if ( TM . getSubtargetImpl ( ) -> hasHighWord ( ) ) NewOpcode = SystemZ :: RISBLG32 ; else NewOpcode = 0 ; if ( NewOpcode ) { uint64_t Imm = MI -> getOperand ( 2 ) . getImm ( ) << And . ImmLSB ; Imm |= allOnes ( And . RegSize ) & ~ ( allOnes ( And . ImmSize ) << And . ImmLSB ) ; unsigned Start , End ; if ( isRxSBGMask ( Imm , And . RegSize , Start , End ) ) { if ( NewOpcode == SystemZ :: RISBLG32 ) { Start &= 31 ; End &= 31 ; } MachineOperand & Dest = MI -> getOperand ( 0 ) ; MachineOperand & Src = MI -> getOperand ( 1 ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( NewOpcode ) ) . addOperand ( Dest ) . addReg ( 0 ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + 128 ) . addImm ( 0 ) ; return finishConvertToThreeAddress ( MI , MIB , LV ) ; } } } return 0 ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> static void mips_init_builtins ( void ) { const struct mips_builtin_description * d ; unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_builtins ) ; i ++ ) { d = & mips_builtins [ i ] ; if ( d -> avail ( ) ) { mips_builtin_decls [ i ] = add_builtin_function ( d -> name , mips_build_function_type ( d -> function_type ) , i , BUILT_IN_MD , NULL , NULL ) ; mips_get_builtin_decl_index [ d -> icode ] = i ; } } } </s>

Init builtin functions . This is called from TARGET_INIT_BUILTIN .


<s> static bool mips_callee_copies ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED , bool named ) { return mips_abi == ABI_EABI && named ; } </s>


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> char * ix86_offload_options ( void ) { if ( TARGET_LP64 ) return xstrdup ( "-foffload-abi=lp64" ) ; return xstrdup ( "-foffload-abi=ilp32" ) ; } </s>

Implement the TARGET_OFFLOAD_OPTIONS hook .


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility guarantee"

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> static rtx_insn * aarch64_prev_real_insn ( rtx_insn * insn ) { if ( ! insn ) return NULL ; do { insn = prev_real_insn ( insn ) ; } while ( insn && recog_memoized ( insn ) < 0 ) ; return insn ; } </s>

Find the first rtx_insn before insn that will generate an assembly instruction .


<s>
bool
AArch64A53Fix835769
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
const
TargetMachine
&
TM
=
F
.
getTarget
(
)
;
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64A53Fix835769 *****\n"
)
;
TII
=
TM
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
for
(
auto
&
MBB
:
F
)
{
Changed
|=
runOnBasicBlock
(
MBB
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> unsigned PPCTTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC || ClassID == VSXRC ) ; if ( ST -> hasVSX ( ) ) { assert ( ClassID == GPRRC || ClassID == VSXRC || ClassID == VRRC ) ; return ClassID == VSXRC ? 64 : 32 ; } assert ( ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC ) ; return 32 ; } </s>


<s> bool Cpu0AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Cpu0MFI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
getShiftedImmVal
(
)
->
print
(
OS
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_ShiftExtend
:
{
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> bool MipsFastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: SDiv : if ( ! selectBinaryOp ( I , ISD :: SDIV ) ) return selectDivRem ( I , ISD :: SDIV ) ; return true ; case Instruction :: UDiv : if ( ! selectBinaryOp ( I , ISD :: UDIV ) ) return selectDivRem ( I , ISD :: UDIV ) ; return true ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectDivRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectDivRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPToSI : return selectFPToInt ( I , true ) ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ICmp : case Instruction :: FCmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .

Mips Mips ISD::SDIV ISD::SDIV ISD::UDIV ISD::UDIV ISD::SREM ISD::SREM ISD::UREM ISD::UREM


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_AArch64_CXX_TLS_Darwin_RegMask ; if ( MF . getSubtarget < AArch64Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_AArch64_AAPCS_SwiftError_RegMask ; if ( CC == CallingConv :: PreserveMost ) return CSR_AArch64_RT_MostRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
static
int
match_basetype
(
typeinfo
*
typedata
)
{
consume_whitespace
(
)
;
int
oldpos
=
pos
;
char
*
token
=
match_identifier
(
)
;
if
(
!
token
)
{
diag
(
pos
,
"missing base type in return type\n"
)
;
return
0
;
}
if
(
!
strcmp
(
token
,
"char"
)
)
typedata
->
base
=
BT_CHAR
;
else
if
(
!
strcmp
(
token
,
"short"
)
)
typedata
->
base
=
BT_SHORT
;
else
if
(
!
strcmp
(
token
,
"int"
)
)
typedata
->
base
=
BT_INT
;
else
if
(
!
strcmp
(
token
,
"long"
)
)
{
consume_whitespace
(
)
;
oldpos
=
pos
;
char
*
mustbelongordbl
=
match_identifier
(
)
;
if
(
!
mustbelongordbl
)
typedata
->
base
=
BT_LONG
;
else
if
(
!
strcmp
(
mustbelongordbl
,
"long"
)
)
typedata
->
base
=
BT_LONGLONG
;
else
if
(
!
strcmp
(
mustbelongordbl
,
"double"
)
)
typedata
->
base
=
BT_LONGDOUBLE
;
else
{
typedata
->
base
=
BT_LONG
;
pos
=
oldpos
;
}
}
else
if
(
!
strcmp
(
token
,
"float"
)
)
typedata
->
base
=
BT_FLOAT
;
else
if
(
!
strcmp
(
token
,
"double"
)
)
typedata
->
base
=
BT_DOUBLE
;
else
if
(
!
strcmp
(
token
,
"__int128"
)
)
typedata
->
base
=
BT_INT128
;
else
if
(
!
strcmp
(
token
,
"_Float128"
)
)
typedata
->
base
=
BT_FLOAT128
;
else
if
(
!
strcmp
(
token
,
"bool"
)
)
typedata
->
base
=
BT_BOOL
;
else
if
(
!
strcmp
(
token
,
"string"
)
)
typedata
->
base
=
BT_STRING
;
else
if
(
!
strcmp
(
token
,
"_Decimal32"
)
)
typedata
->
base
=
BT_DECIMAL32
;
else
if
(
!
strcmp
(
token
,
"_Decimal64"
)
)
typedata
->
base
=
BT_DECIMAL64
;
else
if
(
!
strcmp
(
token
,
"_Decimal128"
)
)
typedata
->
base
=
BT_DECIMAL128
;
else
if
(
!
strcmp
(
token
,
"__ibm128"
)
)
typedata
->
base
=
BT_IBM128
;
else
{
diag
(
oldpos
,
"unrecognized base type\n"
)
;
return
0
;
}
handle_pointer
(
typedata
)
;
return
1
;
}
</s>

Match one of the allowable base types . Consumes one token unless the token is `` long '' , which must be paired with a second `` long '' . Optionally consumes a following ' * ' token for pointers . Return 1 for success , 0 for failure .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FP_TO_SINT ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::SELECT ISD::SETCC ISD::VASTART


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"addi %0,%0,%1"
,
xops
)
;
xops
[
1
]
=
gen_rtx_REG
(
Pmode
,
0
)
;
output_asm_insn
(
"stw %1,0(%0)"
,
xops
)
;
xops
[
1
]
=
reg2
;
if
(
TARGET_64BIT
)
output_asm_insn
(
"cmpd 0,%0,%1"
,
xops
)
;
else
output_asm_insn
(
"cmpw 0,%0,%1"
,
xops
)
;
fputs
(
"\tbne 0,"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { emitDataMappingSymbol ( ) ; MCObjectStreamer :: emitFill ( NumBytes , FillValue , Loc ) ; } </s>

Emit Size bytes worth of the value specified by FillValue .


<s> bool PPCPassConfig :: addPreSched2 ( ) { addPass ( createPPCVSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0x01000000 , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
void
ARMMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
uint64_t
TSFlags
=
Desc
.
TSFlags
;
if
(
(
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
Pseudo
)
return
;
int
Size
;
if
(
Desc
.
getSize
(
)
==
2
||
Desc
.
getSize
(
)
==
4
)
Size
=
Desc
.
getSize
(
)
;
else
llvm_unreachable
(
"Unexpected instruction size!"
)
;
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
if
(
isThumb
(
STI
)
&&
Size
==
4
)
{
EmitConstant
(
Binary
>>
16
,
2
,
OS
)
;
EmitConstant
(
Binary
&
0xffff
,
2
,
OS
)
;
}
else
EmitConstant
(
Binary
,
Size
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> void X86DAGToDAGISel :: PostprocessISelDAG ( ) { if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; if ( N -> getMachineOpcode ( ) != TargetOpcode :: SUBREG_TO_REG ) continue ; unsigned SubRegIdx = N -> getConstantOperandVal ( 2 ) ; if ( SubRegIdx != X86 :: sub_xmm && SubRegIdx != X86 :: sub_ymm ) continue ; SDValue Move = N -> getOperand ( 1 ) ; if ( ! Move . isMachineOpcode ( ) ) continue ; switch ( Move . getMachineOpcode ( ) ) { default : continue ; case X86 :: VMOVAPDrr : case X86 :: VMOVUPDrr : case X86 :: VMOVAPSrr : case X86 :: VMOVUPSrr : case X86 :: VMOVDQArr : case X86 :: VMOVDQUrr : case X86 :: VMOVAPDYrr : case X86 :: VMOVUPDYrr : case X86 :: VMOVAPSYrr : case X86 :: VMOVUPSYrr : case X86 :: VMOVDQAYrr : case X86 :: VMOVDQUYrr : case X86 :: VMOVAPDZ128rr : case X86 :: VMOVUPDZ128rr : case X86 :: VMOVAPSZ128rr : case X86 :: VMOVUPSZ128rr : case X86 :: VMOVDQA32Z128rr : case X86 :: VMOVDQU32Z128rr : case X86 :: VMOVDQA64Z128rr : case X86 :: VMOVDQU64Z128rr : case X86 :: VMOVAPDZ256rr : case X86 :: VMOVUPDZ256rr : case X86 :: VMOVAPSZ256rr : case X86 :: VMOVUPSZ256rr : case X86 :: VMOVDQA32Z256rr : case X86 :: VMOVDQU32Z256rr : case X86 :: VMOVDQA64Z256rr : case X86 :: VMOVDQU64Z256rr : break ; } SDValue In = Move . getOperand ( 0 ) ; if ( ! In . isMachineOpcode ( ) || In . getMachineOpcode ( ) <= TargetOpcode :: GENERIC_OP_END ) continue ; CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , In , N -> getOperand ( 2 ) ) ; if ( Move . getNode ( ) -> use_empty ( ) ) CurDAG -> RemoveDeadNode ( Move . getNode ( ) ) ; } } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


"Replacing store %d with permuted store\n"

Convert the non-permuting store INSN to a permuting one .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
else
{
const
TargetRegisterInfo
*
RegInfo
=
st
.
getRegisterInfo
(
)
;
if
(
MBB
.
computeRegisterLiveness
(
RegInfo
,
ARM
::
CPSR
,
I
)
==
MachineBasicBlock
::
LQR_Dead
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVSr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
->
addRegisterDead
(
ARM
::
CPSR
,
RegInfo
)
;
return
;
}
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARMCC::AL
ARM::CPSR
ARM::tMOVSr
ARM::CPSR
ARM::tPUSH
ARMCC::AL
ARM::tPOP
ARMCC::AL


<s> unsigned Mips16InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: STXVD2X : case PPC :: STXVX : case PPC :: QVSTFDX : case PPC :: QVSTFSXs : case PPC :: QVSTFDXb : case PPC :: SPILL_VRSAVE : case PPC :: SPILLTOVSR_ST : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) || AArch64InstrInfo :: isPreLdSt ( MI ) ? 3 : 2 ; return MI . getOperand ( Idx ) ; } </s>

Returns the immediate offset operator of a load/store .


<s> unsigned OutgoingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) { LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Mips :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getOperand ( 1 ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool HasAtomicCmpXchg = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; if ( getTargetMachine ( ) . getOptLevel ( ) != 0 && HasAtomicCmpXchg && Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ) return AtomicExpansionKind :: LLSC ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool SparcTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createSparcFPMoverPass ( * this ) ) ; PM . add ( createSparcDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static rtx altivec_expand_vec_init_builtin ( tree type , tree arglist , rtx target ) { enum machine_mode tmode = TYPE_MODE ( type ) ; enum machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; rtvec v = rtvec_alloc ( n_elt ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; for ( i = 0 ; i < n_elt ; ++ i , arglist = TREE_CHAIN ( arglist ) ) { rtx x = expand_expr ( TREE_VALUE ( arglist ) , NULL_RTX , VOIDmode , 0 ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } gcc_assert ( arglist == NULL ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_init ( target , gen_rtx_PARALLEL ( tmode , v ) ) ; return target ; } </s>


Return the first register that is required to be saved . 16 if none .


<s> enum reg_class ix86_preferred_reload_class ( rtx x , enum reg_class class ) { if ( class == NO_REGS ) return NO_REGS ; if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) return class ; if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) != VOIDmode ) { if ( reg_class_subset_p ( class , GENERAL_REGS ) ) return class ; if ( TARGET_80387 && ( TARGET_MIX_SSE_I387 || ! ( TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( GET_MODE ( x ) ) ) ) && standard_80387_constant_p ( x ) ) { if ( class == FLOAT_SSE_REGS ) return FLOAT_REGS ; if ( class == FP_TOP_SSE_REGS ) return FP_TOP_REG ; if ( class == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; if ( class == FLOAT_INT_REGS || class == FLOAT_REGS ) return class ; } return NO_REGS ; } if ( MAYBE_MMX_CLASS_P ( class ) && CONSTANT_P ( x ) ) return NO_REGS ; if ( MAYBE_SSE_CLASS_P ( class ) && CONSTANT_P ( x ) ) return NO_REGS ; if ( GET_CODE ( x ) == PLUS ) return reg_class_subset_p ( class , GENERAL_REGS ) ? class : NO_REGS ; if ( GET_MODE ( x ) == QImode && ! CONSTANT_P ( x ) ) { if ( reg_class_subset_p ( class , Q_REGS ) ) return class ; if ( reg_class_subset_p ( Q_REGS , class ) ) return Q_REGS ; return NO_REGS ; } return class ; } </s>

Put float CONST_DOUBLE in the constant pool instead of fp regs . QImode must go into class Q_REGS . Narrow ALL_REGS to GENERAL_REGS . This supports allowing movsf and movdf to do mem-to-mem moves through integer regs .


<s> bool TeeRISCPassConfig :: addInstSelector ( ) { addPass ( createTeeRISCISelDag ( getTeeRISCTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
begin
(
)
,
RPIE
=
RegPairs
.
end
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


Return a mask for the call-clobbered low registers that are unused at the end of the prologue .


<s> const SystemZInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> static bool or1k_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( REGNO_REG_CLASS ( regno ) == FLAG_REGS ) return mode == BImode ; return true ; } </s>

Worker for TARGET_HARD_REGNO_MODE_OK . Returns true if the hard register REGNO is ok for storing values of mode MODE .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool ix86_expand_vecmul_qihi ( rtx dest , rtx op1 , rtx op2 ) { machine_mode himode , qimode = GET_MODE ( dest ) ; rtx hop1 , hop2 , hdest ; rtx ( * gen_extend ) ( rtx , rtx ) ; rtx ( * gen_truncate ) ( rtx , rtx ) ; if ( qimode == E_V64QImode ) return false ; if ( ! TARGET_AVX512BW ) return false ; if ( ( qimode == V8QImode || qimode == V16QImode ) && ! TARGET_AVX512VL ) return false ; if ( qimode == V32QImode && ( TARGET_PREFER_AVX128 || TARGET_PREFER_AVX256 ) ) return false ; switch ( qimode ) { case E_V8QImode : himode = V8HImode ; gen_extend = gen_zero_extendv8qiv8hi2 ; gen_truncate = gen_truncv8hiv8qi2 ; break ; case E_V16QImode : himode = V16HImode ; gen_extend = gen_zero_extendv16qiv16hi2 ; gen_truncate = gen_truncv16hiv16qi2 ; break ; case E_V32QImode : himode = V32HImode ; gen_extend = gen_zero_extendv32qiv32hi2 ; gen_truncate = gen_truncv32hiv32qi2 ; break ; default : gcc_unreachable ( ) ; } hop1 = gen_reg_rtx ( himode ) ; hop2 = gen_reg_rtx ( himode ) ; hdest = gen_reg_rtx ( himode ) ; emit_insn ( gen_extend ( hop1 , op1 ) ) ; emit_insn ( gen_extend ( hop2 , op2 ) ) ; emit_insn ( gen_rtx_SET ( hdest , simplify_gen_binary ( MULT , himode , hop1 , hop2 ) ) ) ; emit_insn ( gen_truncate ( dest , hdest ) ) ; return true ; } </s>

Optimize vector MUL generation for V8QI , V16QI and V32QI under TARGET_AVX512BW . i.e . for v16qi a * b , it has vpmovzxbw ymm2 , xmm0 vpmovzxbw ymm3 , xmm1 vpmullw ymm4 , ymm2 , ymm3 vpmovwb xmm0 , ymm4 it would take less instructions than ix86_expand_vecop_qihi . Return true if success .


<s> void iq2000_va_start ( tree valist , rtx nextarg ) { int int_arg_words ; int gpr_save_area_size ; int_arg_words = current_function_args_info . arg_words ; if ( int_arg_words < 8 ) gpr_save_area_size = ( 8 - int_arg_words ) * UNITS_PER_WORD ; else gpr_save_area_size = 0 ; nextarg = plus_constant ( nextarg , - gpr_save_area_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>


<s> bool aarch64_operands_ok_for_ldpstp ( rtx * operands , bool load , machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; enum reg_class rclass_1 , rclass_2 ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) ) return false ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < 8 * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 ) ) ) rclass_2 = FP_REGS ; else rclass_2 = GENERAL_REGS ; if ( rclass_1 != rclass_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into ldp/stp . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool umips_load_store_pair_p_1 ( bool load_p , bool swap_p , rtx first_reg , rtx mem1 , rtx mem2 ) { rtx base1 , base2 ; HOST_WIDE_INT offset1 , offset2 ; if ( ! MEM_P ( mem1 ) || ! MEM_P ( mem2 ) ) return false ; mips_split_plus ( XEXP ( mem1 , 0 ) , & base1 , & offset1 ) ; mips_split_plus ( XEXP ( mem2 , 0 ) , & base2 , & offset2 ) ; if ( ! REG_P ( base1 ) || ! rtx_equal_p ( base1 , base2 ) ) return false ; if ( load_p && REGNO ( first_reg ) == REGNO ( base1 ) ) return false ; if ( load_p && swap_p && REGNO ( first_reg ) + 1 == REGNO ( base1 ) ) return false ; if ( offset2 != offset1 + 4 ) return false ; if ( ! UMIPS_12BIT_OFFSET_P ( offset1 ) ) return false ; return true ; } </s>

Return true if MEM1 and MEM2 use the same base register , and the offset of MEM2 equals the offset of MEM1 plus 4 . FIRST_REG is the register into ( from ) which the contents of MEM1 will be loaded ( stored ) , depending on the value of LOAD_P . SWAP_P is true when the 1st and 2nd instructions are swapped .


<s>
Register
Comet2RegisterInfo
::
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
report_fatal_error
(
"Comet2 cannot read or overwrite SP"
)
;
}
</s>


<s> bool X86PassConfig :: addPreRegAlloc ( ) { if ( EnableStackPointerTest ) { addPass ( createStackPointerTester ( getX86TargetMachine ( ) ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
machine_mode
mode
,
unsigned
width
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
=
{
NULL_RTX
,
0
,
0
,
false
,
false
}
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
mode
,
false
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
info
.
element_width
)
;
lane_count
=
width
/
info
.
element_width
;
mode
=
GET_MODE_INNER
(
mode
)
;
if
(
GET_MODE_CLASS
(
mode
)
==
MODE_FLOAT
)
{
gcc_assert
(
info
.
shift
==
0
&&
!
info
.
mvn
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
value
)
,
buf_size
,
buf_size
,
1
,
mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
mnemonic
=
info
.
mvn
"mvni"
:
"movi"
;
shift_op
=
info
.
msl
"msl"
:
"lsl"
;
gcc_assert
(
CONST_INT_P
(
info
.
value
)
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
value
)
)
;
else
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
shift_op
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


<s>
void
ARM64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARM64FrameLowering
*
TFI
=
static_cast
<
const
ARM64FrameLowering
*
>
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteARM64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
ARM64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>


<s> int cirrus_memory_offset ( rtx op ) { if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return 0 ; if ( GET_CODE ( op ) == MEM ) { rtx ind ; ind = XEXP ( op , 0 ) ; if ( GET_CODE ( ind ) == REG ) return 1 ; if ( GET_CODE ( ind ) == PLUS && GET_CODE ( XEXP ( ind , 0 ) ) == REG && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && GET_CODE ( XEXP ( ind , 1 ) ) == CONST_INT ) return 1 ; } return 0 ; } </s>

Return nonzero if OP is a valid Cirrus memory address pattern .


<s> bool X86FrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ; return ( DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void SystemZPostRASchedStrategy :: initPolicy ( MachineBasicBlock :: iterator Begin , MachineBasicBlock :: iterator End , unsigned NumRegionInstrs ) { if ( Begin -> isTerminator ( ) ) return ; advanceTo ( Begin ) ; } </s>


<s> bool LC3PassConfig :: addInstSelector ( ) { addPass ( createLC3ISelDag ( getLC3TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>


<s> void TOYInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> inline static int thumb1_index_register_rtx_p ( rtx x , int strict_p ) { return thumb1_base_register_rtx_p ( x , QImode , strict_p ) ; } </s>

Return nonzero if x is a legitimate index register . This is the case for any base register that can access a QImode object .


<s>
int
MipsRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
assert
(
0
&&
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .


<s> bool SystemZRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( ReserveR9 ) return CSR_NaCl_SaveList ; bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) { return CSR_GHC_SaveList ; } else { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } } </s>


<s> static bool mmix_function_value_regno_p ( const unsigned int regno ) { return regno == MMIX_RETURN_VALUE_REGNUM ; } </s>


<s> int sh_pr_n_sets ( ) { return REG_N_SETS ( PR_REG ) ; } </s>

For use by ALLOCATE_INITIAL_VALUE . Note that sh.md contains some 'special function ' patterns ( type sfunc ) that clobber pr , but that do not look like function calls to leaf_function_p . Hence we must do this extra check .


<s> bool X86FastISel :: isTypeLegal ( Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! shouldPerformTransformation ( MF ) ) return false ; int FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) Changed |= adjustCallSequence ( MF , * BB , I ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
unsigned
LC3MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_LC3_LO
:
{
FixupKind
=
LC3
::
fixup_lc3_mov_lo16_pcrel
;
break
;
}
case
MCSymbolRefExpr
::
VK_LC3_HI
:
{
FixupKind
=
LC3
::
fixup_lc3_mov_hi16_pcrel
;
break
;
}
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static int distance_non_agu_define_in_bb ( unsigned int regno1 , unsigned int regno2 , rtx_insn * insn , int distance , rtx_insn * start , bool * found ) { basic_block bb = start ? BLOCK_FOR_INSN ( start ) : NULL ; rtx_insn * prev = start ; rtx_insn * next = NULL ; * found = false ; while ( prev && prev != insn && distance < LEA_SEARCH_THRESHOLD ) { if ( NONDEBUG_INSN_P ( prev ) && NONJUMP_INSN_P ( prev ) ) { distance = increase_distance ( prev , next , distance ) ; if ( insn_defines_reg ( regno1 , regno2 , prev ) ) { if ( recog_memoized ( prev ) < 0 || get_attr_type ( prev ) != TYPE_LEA ) { * found = true ; return distance ; } } next = prev ; } if ( prev == BB_HEAD ( bb ) ) break ; prev = PREV_INSN ( prev ) ; } return distance ; } </s>

Search backward for non-agu definition of register number REGNO1 or register number REGNO2 in basic block starting from instruction START up to head of basic block or instruction INSN . Function puts true value into * FOUND var if definition was found and false otherwise . Distance in half-cycles between START and found instruction or head of BB is added to DISTANCE and returned .


<s> const TargetRegisterClass * SparcRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; return Subtarget . is64Bit ( ) ? & SP :: I64RegsRegClass : & SP :: IntRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

Sparc Sparc Sparc Sparc SP::I64RegsRegClass SP::IntRegsRegClass


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; int reg_size = TARGET_32BIT ? 4 : 8 ; int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( Pmode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( Pmode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
PPCTTI
::
PopcntSupportKind
PPCTTI
::
getPopcntSupport
(
unsigned
TyWidth
)
const
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
PSK_Software
;
}
</s>

Return hardware support for population count .

PowerPC
PPC
PPC
"Ty width must be power of 2"


<s> void ARMBaseRegisterInfo :: updateRegAllocHint ( unsigned Reg , unsigned NewReg , MachineFunction & MF ) const { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI -> getRegAllocationHint ( Reg ) ; if ( ( Hint . first == ( unsigned ) ARMRI :: RegPairOdd || Hint . first == ( unsigned ) ARMRI :: RegPairEven ) && TargetRegisterInfo :: isVirtualRegister ( Hint . second ) ) { unsigned OtherReg = Hint . second ; Hint = MRI -> getRegAllocationHint ( OtherReg ) ; if ( Hint . second == Reg ) { MRI -> setRegAllocationHint ( OtherReg , Hint . first , NewReg ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewReg ) ) MRI -> setRegAllocationHint ( NewReg , Hint . first == ( unsigned ) ARMRI :: RegPairOdd ? ARMRI :: RegPairEven : ARMRI :: RegPairOdd , OtherReg ) ; } } } </s>

A callback to allow target a chance to update register allocation hints when a register is `` changed '' ( e.g .

ARM ARM ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd ARMRI::RegPairEven ARMRI::RegPairOdd


<s> unsigned getNumberOfRegisters ( bool Vector ) const override { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 16 ; return 0 ; } if ( ST -> isThumb1Only ( ) ) return 8 ; return 13 ; } </s>


<s> static bool mips_vectorize_vec_perm_const ( machine_mode vmode , machine_mode op_mode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( vmode != op_mode ) return false ; struct expand_vec_perm_d d ; int i , nelt , which ; unsigned char orig_perm [ MAX_VECT_LEN ] ; bool ok ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( vmode ) ; d . testing_p = ! target ; memset ( orig_perm , 0 , MAX_VECT_LEN ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { int ei = sel [ i ] & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = d . op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = d . op0 ; d . one_vector_p = true ; break ; } if ( d . testing_p ) { d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ok ; } ok = mips_expand_vec_perm_const_1 ( & d ) ; if ( ! ok && which == 3 ) { d . op0 = op0 ; d . op1 = op1 ; d . one_vector_p = false ; memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; } return ok ; } </s>


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD


<s> static int arm_sched_variable_issue ( FILE * , int , rtx_insn * insn , int more ) { if ( DEBUG_INSN_P ( insn ) ) return more ; rtx_code code = GET_CODE ( PATTERN ( insn ) ) ; if ( code == USE || code == CLOBBER ) return more ; if ( get_attr_type ( insn ) == TYPE_NO_INSN ) return more ; return more - 1 ; } </s>


"ShadowCallStack attribute not supported on Darwin."

"ShadowCallStack attribute not supported with swifttail"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool X86ATTAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printOperand ( MI , OpNo , "mem" ) ; return false ; } } printMemReference ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; dup = gen_rtx_VEC_DUPLICATE ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; start_sequence ( ) ; XEXP ( dup , 0 ) = force_reg ( GET_MODE_INNER ( mode ) , val ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s> bool forceScalarizeMaskedScatter ( VectorType * VTy , Align Alignment ) { return forceScalarizeMaskedGather ( VTy , Alignment ) ; } </s>

Return true if the target forces scalarizing of llvm.masked.scatter intrinsics .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM A15 S->D optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void aarch64_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode , cmp_mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; cmp_mode = mode ; if ( INTVAL ( mod_f ) == MEMMODEL_ACQUIRE && INTVAL ( mod_s ) == MEMMODEL_RELEASE ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : cmp_mode = SImode ; rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : case DImode : if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( cmp_mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , bval , x ) ) ; } </s>


<s> static void ix86_check_avx_upper_stores ( rtx dest , const_rtx , void * data ) { if ( ix86_check_avx_upper_register ( dest ) ) { bool * used = ( bool * ) data ; * used = true ; } } </s>

Check if a 256bit or 512bit AVX register is referenced in stores .


"%qs attribute only applies to functions"

Handle an `` trap_exit '' attribute ; arguments as in struct attribute_spec.handler .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 branch relaxation pass"
;
}
</s>


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getMcpu ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: MCPU_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: MCPU_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: MCPU_PWR8 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: MCPU_PWR9 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> Register LC2200RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const LC2200Subtarget & Subtarget = MF . getSubtarget < LC2200Subtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? LC2200 :: fp : LC2200 :: sp ; } </s>


<s> rtx mt_return_addr_rtx ( int count ) { if ( count != 0 ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , GPR_LINK ) ; } </s>


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s>
static
tree
ix86_handle_struct_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
*
type
=
;
if
(
DECL_P
(
*
node
)
)
{
if
(
TREE_CODE
(
*
node
)
==
TYPE_DECL
)
type
=
&
TREE_TYPE
(
*
node
)
;
}
else
type
=
node
;
if
(
!
(
type
&&
(
TREE_CODE
(
*
type
)
==
RECORD_TYPE
||
TREE_CODE
(
*
type
)
==
UNION_TYPE
)
)
)
{
warning
(
OPT_Wattributes
,
"%qs attribute ignored"
,
IDENTIFIER_POINTER
(
name
)
)
;
*
no_add_attrs
=
true
;
}
else
if
(
(
is_attribute_p
(
"ms_struct"
,
name
)
&&
lookup_attribute
(
"gcc_struct"
,
TYPE_ATTRIBUTES
(
*
type
)
)
)
||
(
(
is_attribute_p
(
"gcc_struct"
,
name
)
&&
lookup_attribute
(
"ms_struct"
,
TYPE_ATTRIBUTES
(
*
type
)
)
)
)
)
{
warning
(
OPT_Wattributes
,
"%qs incompatible attribute ignored"
,
IDENTIFIER_POINTER
(
name
)
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle a `` ms_struct '' or `` gcc_struct '' attribute ; arguments as in struct attribute_spec.handler .


"insertBranch must not be told to insert a fallthrough"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool CSKYFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s>
void
scalar_chain
::
build
(
bitmap
candidates
,
unsigned
insn_uid
)
{
queue
=
BITMAP_ALLOC
(
)
;
bitmap_set_bit
(
queue
,
insn_uid
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Building chain #%d...\n"
,
chain_id
)
;
while
(
!
bitmap_empty_p
(
queue
)
)
{
insn_uid
=
bitmap_first_set_bit
(
queue
)
;
bitmap_clear_bit
(
queue
,
insn_uid
)
;
bitmap_clear_bit
(
candidates
,
insn_uid
)
;
add_insn
(
candidates
,
insn_uid
)
;
}
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Collected chain #%d...\n"
,
chain_id
)
;
fprintf
(
dump_file
,
"  insns: "
)
;
dump_bitmap
(
dump_file
,
insns
)
;
if
(
!
bitmap_empty_p
(
defs_conv
)
)
{
bitmap_iterator
bi
;
unsigned
id
;
const
char
*
comma
=
""
;
fprintf
(
dump_file
,
"  defs to convert: "
)
;
EXECUTE_IF_SET_IN_BITMAP
(
defs_conv
,
0
,
id
,
bi
)
{
fprintf
(
dump_file
,
"%sr%d"
,
comma
,
id
)
;
comma
=
", "
;
}
fprintf
(
dump_file
,
"\n"
)
;
}
}
BITMAP_FREE
(
queue
)
;
}
</s>

Build new chain starting from insn INSN_UID recursively adding all dependent uses and definitions . Return true if OK , false if the chain discovery was aborted .

i386
"Building chain #%d...\n"
"Collected chain #%d...\n"
"  insns: "
""
"  defs to convert: "
0
"%sr%d"
", "
"\n"


<s> bool ARMGlobalMerge :: doInitialization ( Module & M ) { SmallVector < GlobalVariable * , 16 > Globals , ConstGlobals , BSSGlobals ; const TargetData * TD = TLI -> getTargetData ( ) ; unsigned MaxOffset = TLI -> getMaximalGlobalOffset ( ) ; bool Changed = false ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { if ( ! I -> hasLocalLinkage ( ) || I -> isThreadLocal ( ) || I -> hasSection ( ) ) continue ; unsigned Alignment = I -> getAlignment ( ) ; Type * Ty = I -> getType ( ) -> getElementType ( ) ; if ( Alignment > TD -> getABITypeAlignment ( Ty ) ) continue ; if ( I -> getName ( ) . startswith ( "llvm." ) || I -> getName ( ) . startswith ( ".llvm." ) ) continue ; if ( TD -> getTypeAllocSize ( Ty ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > 1 ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > 1 ) Changed |= doMerge ( BSSGlobals , M , false ) ; return Changed ; } </s>

Set up the AsmPrinter when we are working on a new module .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> void X86RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool reseveCallFrame = TFI -> hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Opcode == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( Is64Bit , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool DLXDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , AluOp ; switch ( ConstraintCode ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! selectAddrRr ( Op , Op0 , Op1 , AluOp ) && ! selectAddrRi ( Op , Op0 , Op1 , AluOp ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { unsigned elements ; switch ( type_of_cost ) { case scalar_stmt : return ix86_cost -> scalar_stmt_cost ; case scalar_load : return ix86_cost -> scalar_load_cost ; case scalar_store : return ix86_cost -> scalar_store_cost ; case vector_stmt : return ix86_cost -> vec_stmt_cost ; case vector_load : return ix86_cost -> vec_align_load_cost ; case vector_store : return ix86_cost -> vec_store_cost ; case vec_to_scalar : return ix86_cost -> vec_to_scalar_cost ; case scalar_to_vec : return ix86_cost -> scalar_to_vec_cost ; case unaligned_load : case unaligned_store : return ix86_cost -> vec_unalign_load_cost ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_cost -> vec_stmt_cost ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> rtx expand ( function_expander & e ) const override { return e . use_exact_insn ( CODE_FOR_aarch64_wrffr ) ; } </s>


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void ix86_split_copysign_const ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = simplify_gen_subreg ( vmode , dest , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is known to be a constant , and so has already been expanded into a vector constant .


<s> int pa_insn_refs_are_delayed ( rtx_insn * insn ) { return ( ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != SEQUENCE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) ) ; } </s>

Return nonzero if references for INSN are delayed . Millicode insns are actually function calls with some special constraints on arguments and register usage . Millicode calls always expect their arguments in the integer argument registers , and always return their result in % r29 ( ret1 ) . They are expected to clobber their arguments , % r1 , % r29 , and the return pointer which is % r31 on 32-bit and % r2 on 64-bit , and nothing else . This function tells reorg that the references to arguments and millicode calls do not appear to happen until after the millicode call . This allows reorg to put insns which set the argument registers into the delay slot of the millicode call -- thus they act more like traditional CALL_INSNs . Note we can not consider side effects of the insn to be delayed because the branch and link insn will clobber the return pointer . If we happened to use the return pointer in the delay slot of the call , then we lose . get_attr_type will try to recognize the given insn , so make sure to filter out things it will not accept -- SEQUENCE , USE and CLOBBER insns in particular .


<s> static rtx strip_salt ( rtx x ) { rtx search = x ; if ( GET_CODE ( search ) == CONST ) search = XEXP ( search , 0 ) ; if ( GET_CODE ( search ) == UNSPEC && XINT ( search , 1 ) == UNSPEC_SALT_ADDR ) x = XVECEXP ( search , 0 , 0 ) ; return x ; } </s>

If X is an UNSPEC_SALT_ADDR expression , return the address that it wraps , otherwise return X itself .


<s> static bool arm_evpc_neon_vtbl ( struct expand_vec_perm_d * d ) { rtx rperm [ MAX_VECT_LEN ] , sel ; machine_mode vmode = d -> vmode ; unsigned int i , nelt = d -> perm . length ( ) ; if ( BYTES_BIG_ENDIAN ) return false ; if ( d -> testing_p ) return true ; if ( vmode != V8QImode && vmode != V16QImode ) return false ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( d -> perm [ i ] ) ; sel = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rperm ) ) ; sel = force_reg ( vmode , sel ) ; arm_expand_vec_perm_1 ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

The NEON VTBL instruction is a fully variable permuation that 's even stronger than what we expose via VEC_PERM_EXPR . What it does n't do is mask the index operand as VEC_PERM_EXPR requires . Therefore we can do slightly better by expanding this as a constant where we do n't have to apply a mask .


<s> static void ix86_conditional_register_usage ( void ) { int i , c_mask ; if ( cfun && cfun -> machine -> no_caller_saved_registers ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ! ix86_function_value_regno_p ( i ) ) call_used_regs [ i ] = 0 ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; } c_mask = CALL_USED_REGISTERS_MASK ( TARGET_64BIT_MS_ABI ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) accessible_reg_set &= ~ reg_class_contents [ MMX_REGS ] ; if ( ! TARGET_SSE ) accessible_reg_set &= ~ reg_class_contents [ ALL_SSE_REGS ] ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) accessible_reg_set &= ~ reg_class_contents [ FLOAT_REGS ] ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; accessible_reg_set &= ~ reg_class_contents [ ALL_MASK_REGS ] ; } } </s>

Update register usage after having seen the compiler flags .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveSparcCodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( std :: make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( ) ; } </s>


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } if ( MI . getOpcode ( ) == AArch64 :: CompilerBarrier || MI . getOpcode ( ) == AArch64 :: SPACE ) { return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint32_t > ( OS , Binary , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> const TargetRegisterClass * SystemZRegisterInfo :: getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned Idx ) const { switch ( Idx ) { default : return 0 ; case SystemZ :: subreg_32bit : if ( B == SystemZ :: ADDR32RegisterClass ) return A -> getSize ( ) == 8 ? SystemZ :: ADDR64RegisterClass : 0 ; return A ; } } </s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


Output assembly language to define a symbol as COMMON from a DECL , possibly with visibility .


<s> static rtx loongarch_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx base , addr ; HOST_WIDE_INT offset ; if ( loongarch_tls_symbol_p ( x ) ) return loongarch_legitimize_tls_address ( x ) ; loongarch_split_plus ( x , & base , & offset ) ; if ( offset != 0 ) { if ( ! loongarch_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = loongarch_add_offset ( NULL , base , offset ) ; return loongarch_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If X can be legitimized in a way that the generic machinery might not expect , return a new address , otherwise return NULL . MODE is the mode of the memory being accessed .


<s> bool PPCInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , unsigned DstReg , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( Cond . size ( ) != 2 ) return false ; if ( Cond [ 1 ] . getReg ( ) == PPC :: CTR || Cond [ 1 ] . getReg ( ) == PPC :: CTR8 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! PPC :: GPRCRegClass . hasSubClassEq ( RC ) && ! PPC :: GPRC_NOR0RegClass . hasSubClassEq ( RC ) && ! PPC :: G8RCRegClass . hasSubClassEq ( RC ) && ! PPC :: G8RC_NOX0RegClass . hasSubClassEq ( RC ) ) return false ; CondCycles = 1 ; TrueCycles = 1 ; FalseCycles = 1 ; return true ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> enum indirect_thunk_prefix indirect_thunk_need_prefix ( rtx_insn * insn ) { enum indirect_thunk_prefix need_prefix ; if ( ix86_bnd_prefixed_insn_p ( insn ) ) need_prefix = indirect_thunk_prefix_bnd ; else if ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) && ix86_notrack_prefixed_insn_p ( insn ) ) { need_prefix = indirect_thunk_prefix_nt ; } else need_prefix = indirect_thunk_prefix_none ; return need_prefix ; } </s>

Return the prefix needed for an indirect branch INSN .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Discriminate Memory Operands"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned int UPTInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return TargetInstrInfo :: isStoreToStackSlot ( MI , FrameIndex ) ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> unsigned getPrefetchDistance ( ) const override { return 2000 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; const ARMSubtarget & ST = C -> MF -> getSubtarget < ARMSubtarget > ( ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation ( createARMMacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> bool ix86_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int flags ) { struct gcc_options func_options , func_options_set ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , "default" ) == 0 ) return true ; tree old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , 0 , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( fndecl , args , & func_options , & func_options_set , flags == 1 ) ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
unsigned
Encoding
,
Mangler
&
Mang
,
const
TargetMachine
&
TM
,
MachineModuleInfo
*
MMI
,
MCStreamer
&
Streamer
)
const
{
if
(
TM
.
getMCAsmInfo
(
)
->
getExceptionHandlingType
(
)
!=
ExceptionHandling
::
ARM
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Encoding
,
Mang
,
TM
,
MMI
,
Streamer
)
;
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
return
MCSymbolRefExpr
::
create
(
TM
.
getSymbol
(
GV
,
Mang
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
ARM
"Can handle absptr encoding only"
ARM


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> tree aarch64_general_fold_builtin ( unsigned int fcode , tree type , unsigned int n_args ATTRIBUTE_UNUSED , tree * args ) { switch ( fcode ) { BUILTIN_VDQF ( UNOP , abs , 2 , ALL ) return fold_build1 ( ABS_EXPR , type , args [ 0 ] ) ; VAR1 ( UNOP , floatv2si , 2 , ALL , v2sf ) VAR1 ( UNOP , floatv4si , 2 , ALL , v4sf ) VAR1 ( UNOP , floatv2di , 2 , ALL , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ 0 ] ) ; AARCH64_SIMD_VREINTERPRET_BUILTINS return fold_build1 ( VIEW_CONVERT_EXPR , type , args [ 0 ] ) ; case AARCH64_SIMD_BUILTIN_LANE_CHECK : gcc_assert ( n_args == 3 ) ; if ( aarch64_fold_builtin_lane_check ( args [ 0 ] , args [ 1 ] , args [ 2 ] ) ) return void_node ; break ; default : break ; } return NULL_TREE ; } </s>

Try to fold a call to the built-in function with subcode FCODE . The function is passed the N_ARGS arguments in ARGS and it returns a value of type TYPE . Return the new expression on success and NULL_TREE on failure .


<s> void sparc_emit_set_const32 ( rtx op0 , rtx op1 ) { enum machine_mode mode = GET_MODE ( op0 ) ; rtx temp ; if ( reload_in_progress || reload_completed ) temp = op0 ; else temp = gen_reg_rtx ( mode ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { gcc_assert ( ! small_int_operand ( op1 , mode ) && ! const_high_operand ( op1 , mode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , GEN_INT ( INTVAL ( op1 ) & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( mode , temp , GEN_INT ( INTVAL ( op1 ) & 0x3ff ) ) ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , temp , gen_rtx_HIGH ( mode , op1 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_LO_SUM ( mode , temp , op1 ) ) ) ; } } </s>

We know it ca n't be done in one insn when we get here , the movsi expander guarentees this .


<s> static rtx emit_frame_save ( rtx frame_reg , machine_mode mode , unsigned int regno , int offset , HOST_WIDE_INT frame_reg_to_sp ) { rtx reg , insn ; gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp , NULL_RTX , NULL_RTX ) ; } </s>

Save a register into the frame , and emit RTX_FRAME_RELATED_P notes . Save REGNO into [ FRAME_REG + OFFSET ] in mode MODE .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedGPR32 [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedGPR64 [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedGPR32 ) ; ++ I ) Reserved . set ( ReservedGPR32 [ I ] ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPPos ) ; Reserved . set ( Mips :: DSPSCount ) ; Reserved . set ( Mips :: DSPCarry ) ; Reserved . set ( Mips :: DSPEFI ) ; Reserved . set ( Mips :: DSPOutFlag ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; Reserved . set ( Mips :: T0 ) ; Reserved . set ( Mips :: T1 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void X86FuchsiaTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


"dynamic alloca in the static alloca map?"

Emit an alloca address in a register using target-specific logic .


Clear caller saved registers not used to pass return values and leaked condition flags before exiting a cmse_nonsecure_entry function .


<s> static bool rs6000_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return ( opt_type == OPTIMIZE_FOR_SPEED && RS6000_RECIP_AUTO_RSQRTE_P ( mode1 ) ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> int mips_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct mips_address_info addr ; int factor ; bool msa_p = ( ! might_split_p && MSA_SUPPORTED_MODE_P ( mode ) ) ; if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; else factor = 1 ; if ( mips_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : if ( msa_p ) { if ( mips_signed_immediate_p ( INTVAL ( addr . offset ) , 10 , mips_ldst_scaled_shift ( mode ) ) ) return 1 ; else return 0 ; } if ( TARGET_MIPS16 && ! mips16_unextended_reference_p ( mode , addr . reg , UINTVAL ( addr . offset ) ) ) return factor * 2 ; return factor ; case ADDRESS_LO_SUM : return msa_p ? 0 : TARGET_MIPS16 ? factor * 2 : factor ; case ADDRESS_CONST_INT : return msa_p ? 0 : factor ; case ADDRESS_SYMBOLIC : return msa_p ? 0 : factor * mips_symbol_insns ( addr . symbol_type , mode ) ; } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at X . Return 0 if X is n't valid for MODE . For mips16 code , count extended instructions as two instructions .


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 2 ) . getImm ( ) ; replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const char * mangle_builtin_type ( const_tree type ) { if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL ) type = TREE_TYPE ( TYPE_NAME ( type ) ) ; if ( tree attr = lookup_sve_type_attribute ( type ) ) if ( tree id = TREE_VALUE ( chain_index ( 2 , TREE_VALUE ( attr ) ) ) ) return IDENTIFIER_POINTER ( id ) ; return NULL ; } </s>

If TYPE is a built-in type defined by the RVV ABI , return the mangled name , otherwise return NULL .


<s> unsigned MipsFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return MaterializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static rtx sparc_builtin_saveregs ( void ) { int first_reg = current_function_args_info . words ; rtx address ; int regno ; for ( regno = first_reg ; regno < SPARC_INT_ARG_MAX ; regno ++ ) emit_move_insn ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + ( UNITS_PER_WORD * regno ) ) ) ) , gen_rtx_REG ( word_mode , SPARC_INCOMING_INT_ARG_FIRST + regno ) ) ; address = gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + UNITS_PER_WORD * first_reg ) ) ; return address ; } </s>

Do what is necessary for ` va_start ' . We look at the current function to determine if stdarg or varargs is used and return the address of the first unnamed parameter .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { unsigned Offset = Fixup . getOffset ( ) ; MCFixupKind Kind = Fixup . getKind ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { Data [ Offset + i ] = ( uint8_t ) ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>


Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM MLA / MLS expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int mips_ldst_scaled_shift ( machine_mode mode ) { int shift = exact_log2 ( GET_MODE_UNIT_SIZE ( mode ) ) ; if ( shift < 0 || shift > 8 ) gcc_unreachable ( ) ; return shift ; } </s>

Return the scale shift that applied to MSA LD/ST address offset .


<s> static bool rs6000_attribute_takes_identifier_p ( const_tree attr_id ) { return is_attribute_p ( "altivec" , attr_id ) ; } </s>

Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain identifier as an argument , so the front end should n't look it up .


<s> void AArch64Subtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; } </s>

Override generic scheduling policy within a region .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloat ( getMipsTargetMachine ( ) ) ) ; addPass ( createPartiallyInlineLibCallsPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { ( void ) isDivergent ; if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegClass MVT::v8i64 ARM::QQQQPRRegClass