<s> int arm_coproc_mem_operand_wb ( rtx op , int wb_level ) { gcc_assert ( wb_level == 0 || wb_level == 1 || wb_level == 2 ) ; rtx ind ; if ( ! ( reload_in_progress || reload_completed || lra_in_progress ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( LABEL_REF_P ( ind ) || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( wb_level > 0 && ( GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC || ( wb_level > 1 && ( GET_CODE ( ind ) == PRE_INC || GET_CODE ( ind ) == POST_DEC ) ) ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( wb_level > 1 && ( GET_CODE ( ind ) == POST_MODIFY || GET_CODE ( ind ) == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( ind , 1 ) , 0 ) , XEXP ( ind , 0 ) ) ) ind = XEXP ( ind , 1 ) ; int factor = MIN ( GET_MODE_SIZE ( GET_MODE ( op ) ) , 4 ) ; if ( GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , 0 ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , 1 ) ) && IN_RANGE ( INTVAL ( XEXP ( ind , 1 ) ) , - 255 * factor , 255 * factor ) && ( INTVAL ( XEXP ( ind , 1 ) ) & ( factor - 1 ) ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a valid coprocessor memory address pattern . WB level is 2 if full writeback address modes are allowed , 1 if limited writeback address modes ( POST_INC and PRE_DEC ) are allowed and 0 if no writeback at all is supported .


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { X86PassConfig * PC = new X86PassConfig ( this , PM ) ; if ( Subtarget . hasCMov ( ) ) PC -> enablePass ( & EarlyIfConverterID ) ; return PC ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> int aarch64_hard_regno_nregs ( unsigned regno , machine_mode mode ) { switch ( aarch64_regno_regclass ( regno ) ) { case FP_REGS : case FP_LO_REGS : return ( GET_MODE_SIZE ( mode ) + UNITS_PER_VREG - 1 ) / UNITS_PER_VREG ; default : return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } gcc_unreachable ( ) ; } </s>


<s> void ix86_expand_binary_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx src1 , src2 , dst , op , clob ; dst = ix86_fixup_binary_operands ( code , mode , operands ) ; src1 = operands [ 1 ] ; src2 = operands [ 2 ] ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ; if ( reload_in_progress ) { gcc_assert ( code == PLUS ) ; emit_insn ( op ) ; } else if ( reload_completed && code == PLUS && ! rtx_equal_p ( dst , src1 ) ) { emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a binary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 3 separate memory references ( one output , two input ) in a single insn .


<s> static bool arm_r3_live_at_start_p ( void ) { return REGNO_REG_SET_P ( df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) , 3 ) ; } </s>

Return true if r3 is live at the start of the function .


<s> static unsigned int mips_machine_reorg2 ( void ) { mips_reorg_process_insns ( ) ; if ( ! TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN ) vr4130_align_insns ( ) ; if ( mips_expand_ghost_gp_insns ( ) ) mips_reorg_process_insns ( ) ; mips16_split_long_branches ( ) ; mips_insert_insn_pseudos ( ) ; return 0 ; } </s>

We use a machine specific pass to do a second machine dependent reorg pass after delay branch scheduling .


<s> bool PPCTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( Ty -> isVectorTy ( ) && AM . BaseOffs != 0 ) return false ; if ( AM . BaseOffs <= - ( 1LL << 16 ) || AM . BaseOffs >= ( 1LL << 16 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Cpu0
::
NumTargetFixupKinds
]
=
{
{
"fixup_Cpu0_16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_24"
,
0
,
24
,
0
}
,
{
"fixup_Cpu0_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_Global"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOT_Local"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_PC24"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Cpu0_CALL24"
,
0
,
24
,
0
}
,
{
"fixup_Cpu0_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Cpu0_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Cpu0_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Cpu0_64"
,
0
,
64
,
0
}
,
{
"fixup_Cpu0_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_DTPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_DTPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Cpu0_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
static
void
i386_output_dwarf_dtprel
(
FILE
*
file
,
int
size
,
rtx
x
)
{
fputs
(
ASM_LONG
,
file
)
;
output_addr_const
(
file
,
x
)
;
fputs
(
"@DTPOFF"
,
file
)
;
switch
(
size
)
{
case
4
:
break
;
case
8
:
fputs
(
", 0"
,
file
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> unsigned FISCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return FISC :: SP ; } </s>


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( funcInfo . MF -> getSubtarget ( ) ) ; bool UseFastISel = false ; UseFastISel |= STI . isTargetMachO ( ) && ! STI . isThumb1Only ( ) ; UseFastISel |= STI . isTargetLinux ( ) && ! STI . isThumb ( ) ; UseFastISel |= STI . isTargetNaCl ( ) && ! STI . isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new ARMFastISel ( funcInfo , libInfo ) ; } return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool mips_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align , enum by_pieces_operation op , bool speed_p ) { if ( op == STORE_BY_PIECES ) return mips_store_by_pieces_p ( size , align ) ; if ( op == MOVE_BY_PIECES && HAVE_cpymemsi ) { if ( currently_expanding_to_rtl ) return false ; if ( align < BITS_PER_WORD ) return size < UNITS_PER_WORD ; return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT ; } return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; } </s>


<s> bool LanaiTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const { return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> void fma_forest :: fma_node_created ( fma_node * node ) { bool created = ! this -> m_globals -> put_node ( node ) ; gcc_assert ( created ) ; this -> m_nb_nodes ++ ; } </s>

Act on the creation of NODE by updating statistics in FOREST and adding an entry for it in the func_fma_steering hashmap .


<s> HOST_WIDE_INT mips_debugger_offset ( rtx addr , HOST_WIDE_INT offset ) { rtx offset2 = const0_rtx ; rtx reg = eliminate_constant_term ( addr , & offset2 ) ; if ( offset == 0 ) offset = INTVAL ( offset2 ) ; if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { offset -= cfun -> machine -> frame . total_size ; if ( reg == hard_frame_pointer_rtx ) offset += cfun -> machine -> frame . hard_frame_pointer_offset ; } return offset ; } </s>

The MIPS debug format wants all automatic variables and arguments to be in terms of the virtual frame pointer ( stack pointer before any adjustment in the function ) , while the MIPS 3.0 linker wants the frame pointer to be the stack pointer after the initial adjustment . So , we do the adjustment here . The arg pointer ( which is eliminated ) points to the virtual frame pointer , while the frame pointer ( which may be eliminated ) points to the stack pointer after the initial adjustments .


<s> int standard_sse_constant_p ( rtx x , machine_mode pred_mode ) { machine_mode mode ; if ( ! TARGET_SSE ) return 0 ; mode = GET_MODE ( x ) ; if ( x == const0_rtx || const0_operand ( x , mode ) ) return 1 ; if ( x == constm1_rtx || vector_all_ones_operand ( x , mode ) || ( ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || GET_MODE_CLASS ( pred_mode ) == MODE_VECTOR_FLOAT ) && float_vector_all_ones_operand ( x , mode ) ) ) { if ( mode == VOIDmode ) mode = pred_mode ; switch ( GET_MODE_SIZE ( mode ) ) { case 64 : if ( TARGET_AVX512F ) return 2 ; break ; case 32 : if ( TARGET_AVX2 ) return 2 ; break ; case 16 : if ( TARGET_SSE2 ) return 2 ; break ; case 0 : gcc_unreachable ( ) ; default : break ; } } return 0 ; } </s>

Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> static rtx or1k_function_value ( const_tree valtype , const_tree , bool ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , RV_REGNUM ) ; } </s>

Worker for TARGET_FUNCTION_VALUE . Returns an RTX representing the location where function return values will be stored . On OpenRISC this is the register r11 . 64-bit return value 's upper 32-bits are returned in r12 , this is automatically done by GCC .


<s> static bool fpop_insn_p ( rtx_insn * insn ) { if ( GET_CODE ( PATTERN ( insn ) ) != SET ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_FPMOVE : case TYPE_FPCMOVE : case TYPE_FP : case TYPE_FPCMP : case TYPE_FPMUL : case TYPE_FPDIVS : case TYPE_FPSQRTS : case TYPE_FPDIVD : case TYPE_FPSQRTD : return true ; default : return false ; } } </s>

True if INSN is a floating-point instruction .


<s> bool isImm ( ) const override { return Kind == KindTy :: Immediate ; } </s>


<s> static void mips_set_fast_mult_zero_zero_p ( struct mips_sim * state ) { if ( TARGET_MIPS16 || ! ISA_HAS_HILO ) mips_tuning_info . fast_mult_zero_zero_p = true ; else { unsigned int true_time = mips_mult_zero_zero_cost ( state , true ) ; unsigned int false_time = mips_mult_zero_zero_cost ( state , false ) ; mips_tuning_info . fast_mult_zero_zero_p = ( true_time <= false_time ) ; } } </s>

Check the relative speeds of `` MULT $ 0 , $ 0 '' and `` MTLO $ 0 ; MTHI $ 0 '' and set up mips_tuning_info.fast_mult_zero_zero_p accordingly . Prefer MULT -- which is shorter -- in the event of a tie .


<s>
static
bool
sizeless_type_p
(
const_tree
type
)
{
if
(
type
==
error_mark_node
)
return
NULL_TREE
;
return
lookup_attribute
(
"SVE sizeless type"
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

Return true if TYPE is a sizeless type .


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


"Expected integer or floating type for store"

Load the specified register of the given register class from the specified stack frame index .


<s> static bool crx_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REGNUM ; * p2 = INVALID_REGNUM ; return true ; } </s>

Return the fixed registers used for condition codes .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= expandMBB ( * MFI ) ; if ( Modified ) MF . RenumberBlocks ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void ia64_emit_nops ( ) { rtx insn ; const struct bundle * b = 0 ; int bundle_pos = 0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx pat ; enum attr_type t ; pat = INSN_P ( insn ) ? PATTERN ( insn ) : const0_rtx ; if ( GET_CODE ( pat ) == USE || GET_CODE ( pat ) == CLOBBER ) continue ; if ( ( GET_CODE ( pat ) == UNSPEC && XINT ( pat , 1 ) == 22 ) || GET_CODE ( insn ) == CODE_LABEL ) { if ( b ) while ( bundle_pos < 3 ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } if ( GET_CODE ( insn ) != CODE_LABEL ) b = bundle + INTVAL ( XVECEXP ( pat , 0 , 0 ) ) ; else b = 0 ; bundle_pos = 0 ; continue ; } else if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == 2 ) { int t = INTVAL ( XVECEXP ( pat , 0 , 0 ) ) ; if ( b ) while ( bundle_pos < t ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } continue ; } if ( bundle_pos == 3 ) b = 0 ; if ( b && INSN_P ( insn ) ) { t = ia64_safe_type ( insn ) ; if ( asm_noperands ( PATTERN ( insn ) ) >= 0 || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) { while ( bundle_pos < 3 ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } continue ; } if ( t == TYPE_UNKNOWN ) continue ; while ( bundle_pos < 3 ) { if ( t == b -> t [ bundle_pos ] || ( t == TYPE_A && ( b -> t [ bundle_pos ] == TYPE_M || b -> t [ bundle_pos ] == TYPE_I ) ) ) break ; emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } if ( bundle_pos < 3 ) bundle_pos ++ ; } } } </s>

After the last scheduling pass , fill in NOPs . It 's easier to do this here than while scheduling .


<s> bool MipsCCState :: originalEVTTypeIsVectorFloat ( EVT Ty ) { if ( Ty . isVector ( ) && Ty . getVectorElementType ( ) . isFloatingPoint ( ) ) return true ; return false ; } </s>

Return true if the original type was vXfXX .


"%qs attribute only applies to functions"

Handle an `` interrupt '' or `` isr '' attribute ; arguments as in struct attribute_spec.handler .


<s> void Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool split_stack_arg_pointer_used_p ( void ) { if ( cfun -> machine -> split_stack_arg_pointer != NULL_RTX && ( ! REG_P ( cfun -> machine -> split_stack_arg_pointer ) || ( REGNO ( cfun -> machine -> split_stack_arg_pointer ) < FIRST_PSEUDO_REGISTER ) ) ) return true ; rtx_insn * insn ; basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) return false ; df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { rtx x = DF_REF_REG ( use ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return true ; } df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) { rtx x = DF_REF_REG ( def ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return false ; } } return bitmap_bit_p ( DF_LR_OUT ( bb ) , 12 ) ; } </s>

Return whether the split-stack arg pointer ( r12 ) is used .


<s> void MipsTargetMachine :: resetSubtarget ( MachineFunction * MF ) { LLVM_DEBUG ( dbgs ( ) << "resetSubtarget\n" ) ; Subtarget = & MF -> getSubtarget < MipsSubtarget > ( ) ; } </s>

Reset the subtarget for the Mips target .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'Y' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { enum machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , 0 ) ; if ( mode == BLKmode ) { intoffset = intoffset & - BITS_PER_WORD ; mode = word_mode ; } } else mode = word_mode ; startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


"PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."

"PRINT_OPERAND_ADDRESS, invalid insn #2"

"PRINT_OPERAND_ADDRESS, invalid insn #1"

A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR . ADDR is an RTL expression .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return Is64Bit ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC ) ; } </s>


<s> Register LoongArchRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? LoongArch :: R22 : LoongArch :: R3 ; } </s>


<s> void X86FrameLowering :: inlineStackProbe ( MachineFunction & MF , MachineBasicBlock & PrologMBB ) const { auto Where = llvm :: find_if ( PrologMBB , [ ] ( MachineInstr & MI ) { return MI . getOpcode ( ) == X86 :: STACKALLOC_W_PROBING ; } ) ; if ( Where != PrologMBB . end ( ) ) { DebugLoc DL = PrologMBB . findDebugLoc ( Where ) ; emitStackProbeInline ( MF , PrologMBB , Where , DL , true ) ; Where -> eraseFromParent ( ) ; } } </s>

Replace a StackProbe inline-stub with the actual probe code inline .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( NI != nullptr ) NI = skipDebugInstructionsForward ( NI , MBB . end ( ) ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ! doMergeWithPrevious && NI != MBB . end ( ) && NI -> getOpcode ( ) == TargetOpcode :: CFI_INSTRUCTION ) { return Offset ; } if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset += PI -> getOperand ( 4 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> void LC3bFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> void AArch64PassConfig :: addPreLegalizeMachineIR ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createAArch64O0PreLegalizerCombiner ( ) ) ; else { addPass ( createAArch64PreLegalizerCombiner ( ) ) ; if ( EnableGISelLoadStoreOptPreLegal ) addPass ( new LoadStoreOpt ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"LEG Assembly Printer"
;
}
</s>


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws"


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned DCPU16InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == DCPU16 :: MOV16rm ) { if ( MI -> getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> unsigned ARMFastISel :: constrainOperandRegClass ( const MCInstrDesc & II , unsigned Op , unsigned OpNum ) { if ( TargetRegisterInfo :: isVirtualRegister ( Op ) ) { const TargetRegisterClass * RegClass = TII . getRegClass ( II , OpNum , & TRI , * FuncInfo . MF ) ; if ( ! MRI . constrainRegClass ( Op , RegClass ) ) { unsigned NewOp = createResultReg ( RegClass ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , NewOp ) . addReg ( Op ) ) ; return NewOp ; } } return Op ; } </s>

Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { while ( MBBI -> isDebugValue ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = 0 ; return getITInstrPredicate ( * MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , 3 , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) , XEXP ( rem , 0 ) , Pmode ) ; * quot_p = quot ; * rem_p = rem ; } </s>


<s> static void mips_sim_wait_regs ( struct mips_sim * state , rtx_insn * insn ) { mips_sim_insn = insn ; note_uses ( & PATTERN ( insn ) , mips_sim_wait_regs_1 , state ) ; } </s>

Advance simulation state STATE until all of INSN 's register dependencies are satisfied .


<s> void PPCRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>


<s> Optional < MCFixupKind > ARMAsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_ARM_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_ARM_ABS8 ) . Case ( "BFD_RELOC_16" , ELF :: R_ARM_ABS16 ) . Case ( "BFD_RELOC_32" , ELF :: R_ARM_ABS32 ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( * TM . getDataLayout ( ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - 8 : - 4 ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; const TargetFrameLowering * TFI = TM -> getFrameLowering ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; X86MachineFunctionInfo * FuncInfo = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned StackAlignment = TFI -> getStackAlignment ( ) ; for ( unsigned i = 0 , e = RI . getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RI . getRegClass ( Reg ) -> getAlignment ( ) > StackAlignment ) { FuncInfo -> setForceFramePointer ( true ) ; return true ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : case Intrinsic :: ppc_vsx_lxvd2x_be : case Intrinsic :: ppc_vsx_lxvw4x_be : case Intrinsic :: ppc_vsx_lxvl : case Intrinsic :: ppc_vsx_lxvll : case Intrinsic :: ppc_mma_lxvp : { Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . ReadMem = true ; Info . WriteMem = false ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : case Intrinsic :: ppc_vsx_stxvd2x_be : case Intrinsic :: ppc_vsx_stxvw4x_be : case Intrinsic :: ppc_vsx_stxvl : case Intrinsic :: ppc_vsx_stxvll : case Intrinsic :: ppc_mma_stxvp : { Info . PtrVal = Inst -> getArgOperand ( 1 ) ; Info . ReadMem = false ; Info . WriteMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static bool aarch64_movw_imm ( HOST_WIDE_INT val , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) > 4 ) { if ( ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 32 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 48 ) ) == val ) return 1 ; } else { val &= ( HOST_WIDE_INT ) 0xffffffff ; } return ( ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 0 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xffff ) << 16 ) ) == val ) ; } </s>

Return true if val is an immediate that can be loaded into a register by a MOVZ instruction .


<s> InstructionCost X86TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; if ( BitSize > 128 ) return TTI :: TCC_Free ; if ( Imm == 0 ) return TTI :: TCC_Free ; APInt ImmVal = Imm ; if ( BitSize % 64 != 0 ) ImmVal = Imm . sext ( alignTo ( BitSize , 64 ) ) ; InstructionCost Cost = 0 ; for ( unsigned ShiftVal = 0 ; ShiftVal < BitSize ; ShiftVal += 64 ) { APInt Tmp = ImmVal . ashr ( ShiftVal ) . sextOrTrunc ( 64 ) ; int64_t Val = Tmp . getSExtValue ( ) ; Cost += getIntImmCost ( Val ) ; } return std :: max < InstructionCost > ( 1 , Cost ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; bool Promote = false ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : break ; case ISD :: LOAD : { LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; } } Promote = true ; break ; } case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : Promote = true ; break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && MayFoldIntoStore ( Op ) ) return false ; Promote = true ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote = true ; } } PVT = MVT :: i32 ; return Promote ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


"MIPS16 PIC for ABIs other than o32 and o64"

"hard-float MIPS16 code for ABIs other than o32 and o64"

Set up the target-dependent global state for ISA mode COMPRESSION_MODE , which is either MASK_MIPS16 or MASK_MICROMIPS .


<s> static void arm_elf_asm_constructor ( rtx symbol , int priority ) { arm_elf_asm_cdtor ( symbol , priority , true ) ; } </s>

Add a function to the list of static constructors .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
optForSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> const AArch64Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && VT . getSizeInBits ( ) == 128 ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT ) || isCommutedSHUFPMask ( Mask , VT ) ) ; } return false ; } </s>


<s> bool mips_expand_unaligned_load ( rtx dest , rtx src , unsigned int width , int bitpos ) { rtx left , right , temp ; if ( GET_CODE ( dest ) == SUBREG && GET_MODE ( dest ) == DImode && SUBREG_BYTE ( dest ) == 0 && GET_MODE ( SUBREG_REG ( dest ) ) == SImode ) dest = SUBREG_REG ( dest ) ; if ( GET_MODE_BITSIZE ( GET_MODE ( dest ) ) != width ) return false ; if ( ! mips_get_unaligned_mem ( & src , width , bitpos , & left , & right ) ) return false ; temp = gen_reg_rtx ( GET_MODE ( dest ) ) ; if ( GET_MODE ( dest ) == DImode ) { emit_insn ( gen_mov_ldl ( temp , src , left ) ) ; emit_insn ( gen_mov_ldr ( dest , copy_rtx ( src ) , right , temp ) ) ; } else { emit_insn ( gen_mov_lwl ( temp , src , left ) ) ; emit_insn ( gen_mov_lwr ( dest , copy_rtx ( src ) , right , temp ) ) ; } return true ; } </s>

Try to emit the equivalent of ( set DEST ( zero_extract SRC WIDTH BITPOS ) ) . Return true on success . We only handle cases where zero_extract is equivalent to sign_extract .


<s> bool LanaiTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return ( isGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> unsigned SystemZTTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( BitSize > 64 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : if ( Idx == 1 && Imm . getBitWidth ( ) <= 64 ) { if ( isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < 32 > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return SystemZTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>


<s> SDValue MipsSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , false , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , false ) ; } </s>

Emit target-specific code that performs a memmove .


"\nrs6000_mode_dependent_address: ret = %s\n"

Debug version of rs6000_mode_dependent_address .


<s> static rtx ix86_erase_embedded_rounding ( rtx pat ) { if ( GET_CODE ( pat ) == INSN ) pat = PATTERN ( pat ) ; gcc_assert ( GET_CODE ( pat ) == SET ) ; rtx src = SET_SRC ( pat ) ; gcc_assert ( XVECLEN ( src , 0 ) == 2 ) ; rtx p0 = XVECEXP ( src , 0 , 0 ) ; gcc_assert ( GET_CODE ( src ) == UNSPEC && XINT ( src , 1 ) == UNSPEC_EMBEDDED_ROUNDING ) ; rtx res = gen_rtx_SET ( SET_DEST ( pat ) , p0 ) ; return res ; } </s>

Transform pattern of following layout : ( parallel [ set ( A B ) ( unspec [ C ] UNSPEC_EMBEDDED_ROUNDING ) ] ) ] ) into : ( set ( A B ) ) Or : ( parallel [ A B ... ( unspec [ C ] UNSPEC_EMBEDDED_ROUNDING ) ... ] ) into : ( parallel [ A B ... ] )


"Altivec is not implemented on AIX yet."

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode || GET_MODE ( x ) == HFmode ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . elt ( 0 ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


<s>
bool
ARMAsmParser
::
ParseInstruction
(
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Head
=
Name
.
slice
(
Start
,
Next
)
;
unsigned
CC
=
StringSwitch
<
unsigned
>
(
Head
.
substr
(
Head
.
size
(
)
2
)
)
.
Case
(
"eq"
,
ARMCC
::
EQ
)
.
Case
(
"ne"
,
ARMCC
::
NE
)
.
Case
(
"hs"
,
ARMCC
::
HS
)
.
Case
(
"lo"
,
ARMCC
::
LO
)
.
Case
(
"mi"
,
ARMCC
::
MI
)
.
Case
(
"pl"
,
ARMCC
::
PL
)
.
Case
(
"vs"
,
ARMCC
::
VS
)
.
Case
(
"vc"
,
ARMCC
::
VC
)
.
Case
(
"hi"
,
ARMCC
::
HI
)
.
Case
(
"ls"
,
ARMCC
::
LS
)
.
Case
(
"ge"
,
ARMCC
::
GE
)
.
Case
(
"lt"
,
ARMCC
::
LT
)
.
Case
(
"gt"
,
ARMCC
::
GT
)
.
Case
(
"le"
,
ARMCC
::
LE
)
.
Case
(
"al"
,
ARMCC
::
AL
)
.
Default
(
~
0U
)
;
if
(
CC
==
~
0U
||
(
CC
==
ARMCC
::
LS
&&
(
Head
==
"vmls"
||
Head
==
"vnmls"
)
)
)
{
CC
=
ARMCC
::
AL
;
}
else
{
Head
=
Head
.
slice
(
0
,
Head
.
size
(
)
2
)
;
}
Operands
.
push_back
(
ARMOperand
::
CreateToken
(
Head
,
NameLoc
)
)
;
if
(
Head
!=
"trap"
)
Operands
.
push_back
(
ARMOperand
::
CreateCondCode
(
ARMCC
::
CondCodes
(
CC
)
,
NameLoc
)
)
;
while
(
Next
!=
StringRef
::
npos
)
{
Start
=
Next
;
Next
=
Name
.
find
(
'.'
,
Start
+
1
)
;
Head
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
ARMOperand
::
CreateToken
(
Head
,
NameLoc
)
)
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
true
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
TokError
(
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

ARM
ARM
0
2
"eq"
ARMCC::EQ
"ne"
ARMCC::NE
"hs"
ARMCC::HS
"lo"
ARMCC::LO
"mi"
ARMCC::MI
"pl"
ARMCC::PL
"vs"
ARMCC::VS
"vc"
ARMCC::VC
"hi"
ARMCC::HI
"ls"
ARMCC::LS
"ge"
ARMCC::GE
"lt"
ARMCC::LT
"gt"
ARMCC::GT
"le"
ARMCC::LE
"al"
ARMCC::AL
0U
0U
ARMCC::LS
"vmls"
"vnmls"
ARMCC::AL
0
2
ARM
"trap"
ARM
ARMCC::CondCodes
1
ARM
"unexpected token in argument list"


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame -> hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> EVT ARMTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == MVT :: v4i32 || VT == MVT :: v8i16 || VT == MVT :: v16i8 ) ) return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool rs6000_split_128bit_ok_p ( rtx operands [ ] ) { if ( ! reload_completed ) return false ; if ( ! gpr_or_gpr_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; if ( quad_load_store_p ( operands [ 0 ] , operands [ 1 ] ) ) return false ; return true ; } </s>

Return true if a 128-bit move needs to be split .


<s> static void vr4130_reorder ( rtx * ready , int nready ) { if ( vr4130_swap_insns_p ( ready [ nready - 1 ] , ready [ nready - 2 ] ) ) mips_promote_ready ( ready , nready - 2 , nready - 1 ) ; } </s>

A TUNE_MIPS4130 helper function . ( READY , NREADY ) describes a ready queue with at least two instructions . Swap the first two if vr4130_swap_insns_p says that it could be worthwhile .


<s> static void expand_setmem_epilogue_via_loop ( rtx destmem , rtx destptr , rtx value , rtx count , int max_size ) { count = expand_simple_binop ( counter_mode ( count ) , AND , count , GEN_INT ( max_size - 1 ) , count , 1 , OPTAB_DIRECT ) ; expand_set_or_cpymem_via_loop ( destmem , NULL , destptr , NULL , gen_lowpart ( QImode , value ) , count , QImode , 1 , max_size / 2 , true ) ; } </s>

Output code to set at most count & ( max_size - 1 ) bytes starting by DEST .


<s> void mips_expand_vec_cond_expr ( machine_mode mode , machine_mode vimode , rtx * operands ) { rtx cond = operands [ 3 ] ; rtx cmp_op0 = operands [ 4 ] ; rtx cmp_op1 = operands [ 5 ] ; rtx cmp_res = gen_reg_rtx ( vimode ) ; mips_expand_msa_cmp ( cmp_res , GET_CODE ( cond ) , cmp_op0 , cmp_op1 ) ; if ( operands [ 1 ] == CONSTM1_RTX ( vimode ) && operands [ 2 ] == CONST0_RTX ( vimode ) ) emit_move_insn ( operands [ 0 ] , cmp_res ) ; else { rtx src1 = gen_reg_rtx ( vimode ) ; rtx src2 = gen_reg_rtx ( vimode ) ; rtx mask = gen_reg_rtx ( vimode ) ; rtx bsel ; emit_move_insn ( mask , cmp_res ) ; if ( register_operand ( operands [ 1 ] , mode ) ) { rtx xop1 = operands [ 1 ] ; if ( mode != vimode ) { xop1 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop1 , gen_lowpart ( vimode , operands [ 1 ] ) ) ; } emit_move_insn ( src1 , xop1 ) ; } else { gcc_assert ( operands [ 1 ] == CONSTM1_RTX ( vimode ) ) ; emit_move_insn ( src1 , mask ) ; } if ( register_operand ( operands [ 2 ] , mode ) ) { rtx xop2 = operands [ 2 ] ; if ( mode != vimode ) { xop2 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop2 , gen_lowpart ( vimode , operands [ 2 ] ) ) ; } emit_move_insn ( src2 , xop2 ) ; } else { gcc_assert ( operands [ 2 ] == CONST0_RTX ( mode ) ) ; emit_move_insn ( src2 , mask ) ; } bsel = gen_rtx_IOR ( vimode , gen_rtx_AND ( vimode , gen_rtx_NOT ( vimode , mask ) , src2 ) , gen_rtx_AND ( vimode , mask , src1 ) ) ; emit_insn ( gen_rtx_SET ( mask , bsel ) ) ; emit_move_insn ( operands [ 0 ] , gen_rtx_SUBREG ( mode , mask , 0 ) ) ; } } </s>

Expand VEC_COND_EXPR , where : MODE is mode of the result VIMODE equivalent integer mode OPERANDS operands of VEC_COND_EXPR .


<s> virtual bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , const BranchProbability & Probability ) const { return true ; } </s>


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FP_TO_SINT ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::SELECT ISD::SETCC ISD::VASTART


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) { initReciprocals ( * this , Subtarget ) ; initAsmInfo ( ) ; } </s>


<s> unsigned X86TTIImpl :: getScalarizationOverhead ( VectorType * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { unsigned Cost = 0 ; if ( Insert ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ( MScalarTy == MVT :: i16 && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) || ( MScalarTy == MVT :: f32 && ST -> hasSSE41 ( ) ) ) { if ( LT . second . getSizeInBits ( ) <= 128 ) { Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , false ) ; } else { unsigned NumSubVecs = LT . second . getSizeInBits ( ) / 128 ; Cost += ( PowerOf2Ceil ( NumSubVecs ) - 1 ) * LT . first ; Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == MVT :: f32 ) for ( unsigned i = 0 , e = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; i < e ; i += 4 ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ) ; Cost += ( std :: min < unsigned > ( NumElts , Pow2Elts ) - 1 ) * LT . first ; } } if ( Extract ) Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , false , Extract ) ; return Cost ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> void ARMTargetLowering :: HandleByVal ( CCState * State , unsigned & Size , Align Alignment ) const { Alignment = std :: max ( Alignment , Align ( 4 ) ) ; unsigned Reg = State -> AllocateReg ( GPRArgRegs ) ; if ( ! Reg ) return ; unsigned AlignInRegs = Alignment . value ( ) / 4 ; unsigned Waste = ( ARM :: R4 - Reg ) % AlignInRegs ; for ( unsigned i = 0 ; i < Waste ; ++ i ) Reg = State -> AllocateReg ( GPRArgRegs ) ; if ( ! Reg ) return ; unsigned Excess = 4 * ( ARM :: R4 - Reg ) ; const unsigned NSAAOffset = State -> getNextStackOffset ( ) ; if ( NSAAOffset != 0 && Size > Excess ) { while ( State -> AllocateReg ( GPRArgRegs ) ) ; return ; } unsigned ByValRegBegin = Reg ; unsigned ByValRegEnd = std :: min < unsigned > ( Reg + Size / 4 , ARM :: R4 ) ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ; for ( unsigned i = Reg + 1 ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs ) ; Size = std :: max < int > ( Size - Excess , 0 ) ; } </s>

Target-specific cleanup for formal ByVal parameters .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void mips_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct mips_arg_info info ; mips_get_arg_info ( & info , cum , mode , type , named ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < 2 && info . fpr_p ) cum -> fp_code += ( mode == SFmode ? 1 : 2 ) << ( cum -> arg_number * 2 ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs = info . reg_offset + info . reg_words ; else if ( info . reg_words > 0 ) cum -> num_fprs += MAX_FPRS_PER_FMT ; if ( info . stack_words > 0 ) cum -> stack_words = info . stack_offset + info . stack_words ; cum -> arg_number ++ ; } </s>


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getSubtarget < ARMSubtarget > ( ) ; if ( ! STI -> isCortexA9 ( ) ) return false ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool SystemZXPLINKFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = 0 , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( SystemZ :: FP64BitRegClass . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & SystemZ :: FP64BitRegClass , TRI ) ; if ( SystemZ :: VR128BitRegClass . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & SystemZ :: VR128BitRegClass , TRI ) ; } SystemZ :: GPRRegs RestoreGPRs = ZFI -> getRestoreGPRRegs ( ) ; if ( RestoreGPRs . LowGPR ) { assert ( isInt < 20 > ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ) ; if ( RestoreGPRs . LowGPR == RestoreGPRs . HighGPR ) BuildMI ( MBB , MBBI , DL , TII -> get ( SystemZ :: LG ) , RestoreGPRs . LowGPR ) . addReg ( Regs . getStackPointerRegister ( ) ) . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) . addReg ( 0 ) ; else { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( SystemZ :: LMG ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( Regs . getStackPointerRegister ( ) ) ; MIB . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ; for ( unsigned I = 0 , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg > RestoreGPRs . LowGPR && Reg < RestoreGPRs . HighGPR ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void X86AsmInstrumentation :: EmitInstruction ( MCStreamer & Out , const MCInst & Inst , bool PrintSchedInfoEnabled ) { Out . EmitInstruction ( Inst , * STI , PrintSchedInfoEnabled ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
static_assert
(
X86
::
FP6
==
X86
::
FP0
+
6
,
"Register enums aren't sorted right!"
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
!
MRI
.
reg_nodbg_empty
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
&
MF
.
front
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
*
BB
:
depth_first_ext
(
Entry
,
Processed
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineBasicBlock
&
BB
:
MF
)
if
(
Processed
.
insert
(
&
BB
)
.
second
)
Changed
|=
processBasicBlock
(
MF
,
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>


<s>
const
char
*
getPassName
(
)
const
{
return
"TOY PreRegAlloc"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
OR1KMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
return
getOR1KRegisterNumbering
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
OR1K
::
Fixups
FixupKind
=
OR1K
::
Fixups
(
0
)
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
break
;
case
MCSymbolRefExpr
::
VK_None
:
FixupKind
=
OR1K
::
fixup_OR1K_REL26
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_ABS_HI
:
FixupKind
=
OR1K
::
fixup_OR1K_HI16_INSN
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_ABS_LO
:
FixupKind
=
OR1K
::
fixup_OR1K_LO16_INSN
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_PLT
:
FixupKind
=
OR1K
::
fixup_OR1K_PLT26
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOTPCHI
:
FixupKind
=
OR1K
::
fixup_OR1K_GOTPC_HI16
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOTPCLO
:
FixupKind
=
OR1K
::
fixup_OR1K_GOTPC_LO16
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOTOFFHI
:
FixupKind
=
OR1K
::
fixup_OR1K_GOTOFF_HI16
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOTOFFLO
:
FixupKind
=
OR1K
::
fixup_OR1K_GOTOFF_LO16
;
break
;
case
MCSymbolRefExpr
::
VK_OR1K_GOT
:
FixupKind
=
OR1K
::
fixup_OR1K_GOT16
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool useAA ( ) const override { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,15]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"Stack offset for byval regs doesn't introduced anymore?"


<s> const char * CJGTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( CJGISD :: NodeType ) Opcode ) { case CJGISD :: FIRST_NUMBER : break ; case CJGISD :: CMP : return "CJGISD::CMP" ; case CJGISD :: RET_FLAG : return "CJGISD::RET_FLAG" ; case CJGISD :: BR_CC : return "CJGISD::BR_CC" ; case CJGISD :: SELECT_CC : return "CJGISD::SELECT_CC" ; case CJGISD :: Wrapper : return "CJGISD::Wrapper" ; case CJGISD :: CALL : return "CJGISD::CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned MipsInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case Mips :: CONSTPOOL_ENTRY : return MI . getOperand ( 2 ) . getImm ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FBB , unsigned FCycles , unsigned FExtra , BranchProbability Probability ) const { if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = 1024 ; unsigned PredCost = ( TCycles + FCycles + TExtra + FExtra ) * ScalingUpFactor ; unsigned UnpredCost ; if ( ! Subtarget . hasBranchPredictor ( ) ) { unsigned NotTakenBranchCost = 1 ; unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= 1 * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > 4 ) { PredCost += ( ( TCycles + FCycles - 4 ) / 4 ) * ScalingUpFactor ; } } else { unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += 1 * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor / 10 ; } return PredCost <= UnpredCost ; } </s>


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicRMWIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicRMWInst
*
AI
,
Value
*
AlignedAddr
,
Value
*
Incr
,
Value
*
Mask
,
Value
*
ShiftAmt
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
cast
<
PointerType
>
(
AlignedAddr
->
getType
(
)
)
->
getElementType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
RMW
=
Intrinsic
::
getDeclaration
(
M
,
getIntrinsicForAtomicRMWBinOp128
(
AI
->
getOperation
(
)
)
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
IncrLo
=
Builder
.
CreateTrunc
(
Incr
,
Int64Ty
,
"incr_lo"
)
;
Value
*
IncrHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Incr
,
64
)
,
Int64Ty
,
"incr_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
RMW
,
{
Addr
,
IncrLo
,
IncrHi
}
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s> const SystemZInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
static
int
getMemSize
(
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown size!"
)
;
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
return
4
;
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
return
8
;
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
return
16
;
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
return
4
;
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
return
8
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
return
16
;
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
return
4
;
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
return
8
;
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
return
4
;
}
}
</s>

Returns the size in bytes of the memory access .


<s>
MachineBasicBlock
*
SystemZTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
SystemZInstrInfo
&
TII
=
*
TM
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
SystemZ
::
Select32
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF32
||
MI
->
getOpcode
(
)
==
SystemZ
::
Select64
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF64
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
SystemZCC
::
CondCodes
CC
=
(
SystemZCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SystemZ
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a ( possibly variable ) scalar , expecting it to have the following properties : - the type class must be the same as for type suffix 0 if EXPECTED_TCLASS is SAME_TYPE_CLASS , otherwise it must be EXPECTED_TCLASS itself . - the element size must be the same as for type suffix 0 if EXPECTED_BITS is SAME_TYPE_SIZE , otherwise it must be EXPECTED_BITS itself . Return true if the argument is valid , otherwise report an appropriate error . Note that we do n't check whether the scalar type actually has the required properties , since that 's subject to implicit promotions and conversions . Instead we just use the expected properties to tune the error message .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) || Kind . isReadOnly ( ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


"Can only put epilog before 'retl' instruction!"


<s> static rtx aarch64_expand_builtin_rsqrt ( int fcode , tree exp , rtx target ) { tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx ( * gen ) ( rtx , rtx ) ; switch ( fcode ) { case AARCH64_BUILTIN_RSQRT_DF : gen = gen_rsqrtdf2 ; break ; case AARCH64_BUILTIN_RSQRT_SF : gen = gen_rsqrtsf2 ; break ; case AARCH64_BUILTIN_RSQRT_V2DF : gen = gen_rsqrtv2df2 ; break ; case AARCH64_BUILTIN_RSQRT_V2SF : gen = gen_rsqrtv2sf2 ; break ; case AARCH64_BUILTIN_RSQRT_V4SF : gen = gen_rsqrtv4sf2 ; break ; default : gcc_unreachable ( ) ; } if ( ! target ) target = gen_reg_rtx ( GET_MODE ( op0 ) ) ; emit_insn ( gen ( target , op0 ) ) ; return target ; } </s>

Function to expand reciprocal square root builtins .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool IsLittle , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_UNKNOWN ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool nds32_rtx_costs_impl ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ) { int code = GET_CODE ( x ) ; if ( speed ) goto performance_cost ; else goto size_cost ; performance_cost : switch ( code ) { case SET : return false ; case USE : * total = 0 ; break ; case MULT : * total = COSTS_N_INSNS ( 1 ) ; break ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( 7 ) ; break ; default : * total = COSTS_N_INSNS ( 1 ) ; break ; } return true ; size_cost : switch ( code ) { case SET : return false ; case USE : * total = 0 ; break ; case CONST_INT : if ( outer_code == SET ) { if ( satisfies_constraint_Is05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else if ( satisfies_constraint_Is20 ( x ) ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; } else if ( outer_code == PLUS || outer_code == MINUS ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else if ( outer_code == ASHIFT ) { if ( satisfies_constraint_Iu03 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else if ( outer_code == ASHIFTRT || outer_code == LSHIFTRT ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else { * total = COSTS_N_INSNS ( 1 ) ; } break ; case CONST_DOUBLE : * total = COSTS_N_INSNS ( 2 ) ; break ; default : * total = COSTS_N_INSNS ( 1 ) ; break ; } return true ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const LLVM_OVERRIDE { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } addPass ( createARMOptimizeBarriersPass ( ) ) ; if ( getARMSubtarget ( ) . useConstIslands ( ) ) addPass ( createARMConstantIslandPass ( ) ) ; if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createARMNaClRewritePass ( ) ) ; } return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void mips_output_function_epilogue ( FILE * ) { const char * fnname ; SET_REGNO ( pic_offset_table_rtx , GLOBAL_POINTER_REGNUM ) ; mips_output_cplocal ( ) ; if ( cfun -> machine -> all_noreorder_p ) { mips_pop_asm_switch ( & mips_nomacro ) ; mips_pop_asm_switch ( & mips_noreorder ) ; } fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , 0 ) , 0 ) ; mips_end_function_definition ( fnname ) ; } </s>


<s> void SSEDomainFixPass :: enterBasicBlock ( ) { for ( MachineBasicBlock :: livein_iterator i = MBB -> livein_begin ( ) , e = MBB -> livein_end ( ) ; i != e ; ++ i ) { int rx = RegIndex ( * i ) ; if ( rx < 0 ) continue ; for ( MachineBasicBlock :: const_pred_iterator pi = MBB -> pred_begin ( ) , pe = MBB -> pred_end ( ) ; pi != pe ; ++ pi ) { LiveOutMap :: const_iterator fi = LiveOuts . find ( * pi ) ; if ( fi == LiveOuts . end ( ) ) continue ; DomainValue * pdv = fi -> second [ rx ] ; if ( ! pdv ) continue ; if ( ! LiveRegs || ! LiveRegs [ rx ] ) { SetLiveReg ( rx , pdv ) ; continue ; } if ( LiveRegs [ rx ] -> isCollapsed ( ) ) { unsigned domain = LiveRegs [ rx ] -> getFirstDomain ( ) ; if ( ! pdv -> isCollapsed ( ) && pdv -> hasDomain ( domain ) ) Collapse ( pdv , domain ) ; continue ; } if ( ! pdv -> isCollapsed ( ) ) Merge ( LiveRegs [ rx ] , pdv ) ; else Force ( rx , pdv -> getFirstDomain ( ) ) ; } } } </s>

Start tracking liveness from the begin of basic block MBB .


Generate rtl for an overlapping load and compare of less than a full load_mode . This assumes that the previous word is part of the block being compared so it 's ok to back up part of a word so we can compare the last unaligned full word that ends at the end of the block . LOAD_MODE is the machine mode for the loads . ISCONST tells whether the remaining length is a constant or in a register . BYTES_REM is the remaining length if ISCONST is true . DIFF is the reg for the difference . CMP_REM is the reg containing the remaining bytes to compare if ! ISCONST . DCOND is the CCUNS reg for the compare if we are doing P9 code with setb . SRC1_ADDR is the first source address . SRC2_ADDR is the second source address . ORIG_SRC1 is the original first source block 's address rtx . ORIG_SRC2 is the original second source block 's address rtx .


<s>
PPC
::
Predicate
PPC
::
getSwappedPredicate
(
PPC
::
Predicate
Opcode
)
{
switch
(
Opcode
)
{
case
PPC
::
PRED_EQ
:
return
PPC
::
PRED_EQ
;
case
PPC
::
PRED_NE
:
return
PPC
::
PRED_NE
;
case
PPC
::
PRED_LT
:
return
PPC
::
PRED_GT
;
case
PPC
::
PRED_GE
:
return
PPC
::
PRED_LE
;
case
PPC
::
PRED_GT
:
return
PPC
::
PRED_LT
;
case
PPC
::
PRED_LE
:
return
PPC
::
PRED_GE
;
case
PPC
::
PRED_NU
:
return
PPC
::
PRED_NU
;
case
PPC
::
PRED_UN
:
return
PPC
::
PRED_UN
;
case
PPC
::
PRED_EQ_MINUS
:
return
PPC
::
PRED_EQ_MINUS
;
case
PPC
::
PRED_NE_MINUS
:
return
PPC
::
PRED_NE_MINUS
;
case
PPC
::
PRED_LT_MINUS
:
return
PPC
::
PRED_GT_MINUS
;
case
PPC
::
PRED_GE_MINUS
:
return
PPC
::
PRED_LE_MINUS
;
case
PPC
::
PRED_GT_MINUS
:
return
PPC
::
PRED_LT_MINUS
;
case
PPC
::
PRED_LE_MINUS
:
return
PPC
::
PRED_GE_MINUS
;
case
PPC
::
PRED_NU_MINUS
:
return
PPC
::
PRED_NU_MINUS
;
case
PPC
::
PRED_UN_MINUS
:
return
PPC
::
PRED_UN_MINUS
;
case
PPC
::
PRED_EQ_PLUS
:
return
PPC
::
PRED_EQ_PLUS
;
case
PPC
::
PRED_NE_PLUS
:
return
PPC
::
PRED_NE_PLUS
;
case
PPC
::
PRED_LT_PLUS
:
return
PPC
::
PRED_GT_PLUS
;
case
PPC
::
PRED_GE_PLUS
:
return
PPC
::
PRED_LE_PLUS
;
case
PPC
::
PRED_GT_PLUS
:
return
PPC
::
PRED_LT_PLUS
;
case
PPC
::
PRED_LE_PLUS
:
return
PPC
::
PRED_GE_PLUS
;
case
PPC
::
PRED_NU_PLUS
:
return
PPC
::
PRED_NU_PLUS
;
case
PPC
::
PRED_UN_PLUS
:
return
PPC
::
PRED_UN_PLUS
;
}
llvm_unreachable
(
"Unknown PPC branch opcode!"
)
;
}
</s>

This is a static version that you can use without an instruction available .


<s> static void arm_emit_vfp_multi_reg_pop ( int first_reg , int num_regs , rtx base_reg ) { int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; gcc_assert ( num_regs && num_regs <= 32 ) ; if ( num_regs == 2 && ! arm_arch6 ) { if ( first_reg == 15 ) first_reg -- ; num_regs ++ ; } if ( num_regs > 16 ) { arm_emit_vfp_multi_reg_pop ( first_reg , 16 , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + 16 , num_regs - 16 , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; tmp = gen_rtx_SET ( base_reg , plus_constant ( Pmode , base_reg , 8 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 0 ) = tmp ; for ( j = 0 , i = first_reg ; j < num_regs ; i += 2 ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , 8 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + 1 ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( REGNO ( base_reg ) == IP_REGNUM ) { RTX_FRAME_RELATED_P ( par ) = 1 ; add_reg_note ( par , REG_CFA_DEF_CFA , hard_frame_pointer_rtx ) ; } else arm_add_cfa_adjust_cfa_note ( par , 2 * UNITS_PER_WORD * num_regs , base_reg , base_reg ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi of NUM_REGS consecutive VFP regs , starting at FIRST_REG . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> bool ARMBaseInstrInfo :: areLoadsFromSameBasePtr ( SDNode * Load1 , SDNode * Load2 , int64_t & Offset1 , int64_t & Offset2 ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; if ( ! Load1 -> isMachineOpcode ( ) || ! Load2 -> isMachineOpcode ( ) ) return false ; switch ( Load1 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRBi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRBi12 : case ARM :: t2LDRSHi12 : break ; } switch ( Load2 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRBi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRBi12 : case ARM :: t2LDRSHi12 : break ; } if ( Load1 -> getOperand ( 0 ) != Load2 -> getOperand ( 0 ) || Load1 -> getOperand ( 4 ) != Load2 -> getOperand ( 4 ) ) return false ; if ( Load1 -> getOperand ( 3 ) != Load2 -> getOperand ( 3 ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; return true ; } return false ; } </s>

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address .


<s> static void ix86_adjust_stack_and_probe ( const HOST_WIDE_INT size ) { const int dope = 4 * UNITS_PER_WORD ; rtx size_rtx = GEN_INT ( size ) , last ; if ( size <= 5 * PROBE_INTERVAL ) { HOST_WIDE_INT i , adjust ; bool first_probe = true ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { if ( first_probe ) { adjust = 2 * PROBE_INTERVAL + dope ; first_probe = false ; } else adjust = PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - adjust ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } if ( first_probe ) adjust = size + PROBE_INTERVAL + dope ; else adjust = size + PROBE_INTERVAL - i ; emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - adjust ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; last = emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; } else { HOST_WIDE_INT rounded_size ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = size & - PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( PROBE_INTERVAL + dope ) ) ) ) ; emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; emit_insn ( ix86_gen_adjust_stack_and_probe ( sr . reg , sr . reg , size_rtx ) ) ; if ( size != rounded_size ) { emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , rounded_size - size ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } last = emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; release_scratch_register_on_entry ( & sr ) ; } gcc_assert ( cfun -> machine -> fs . cfa_reg != stack_pointer_rtx ) ; if ( size > 0 ) { rtx expr = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( expr , 0 , 0 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - size ) ) ; XVECEXP ( expr , 0 , 1 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope + size ) ) ; add_reg_note ( last , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( last ) = 1 ; cfun -> machine -> fs . sp_offset += size ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to adjust the stack pointer by SIZE bytes while probing it .


<s> MCRegister ARMElfTargetObjectFile :: getStaticBase ( ) const { return ARM :: R9 ; } </s>

Returns the register used as static base in RWPI variants .


<s> bool ARMSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


"calling %qD with SSE caling convention without "

"this is a GCC bug that can be worked around by adding "

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 .


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperLarge : return "AArch64ISD::WrapperLarge" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; case AArch64ISD :: NEON_BSL : return "AArch64ISD::NEON_BSL" ; case AArch64ISD :: NEON_MOVIMM : return "AArch64ISD::NEON_MOVIMM" ; case AArch64ISD :: NEON_MVNIMM : return "AArch64ISD::NEON_MVNIMM" ; case AArch64ISD :: NEON_FMOVIMM : return "AArch64ISD::NEON_FMOVIMM" ; case AArch64ISD :: NEON_CMP : return "AArch64ISD::NEON_CMP" ; case AArch64ISD :: NEON_CMPZ : return "AArch64ISD::NEON_CMPZ" ; case AArch64ISD :: NEON_TST : return "AArch64ISD::NEON_TST" ; case AArch64ISD :: NEON_QSHLs : return "AArch64ISD::NEON_QSHLs" ; case AArch64ISD :: NEON_QSHLu : return "AArch64ISD::NEON_QSHLu" ; case AArch64ISD :: NEON_VDUP : return "AArch64ISD::NEON_VDUP" ; case AArch64ISD :: NEON_VDUPLANE : return "AArch64ISD::NEON_VDUPLANE" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool csky_inlinable_constant ( HOST_WIDE_INT value ) { HOST_WIDE_INT x , y ; return ( ! ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK801 ) ) && try_csky_constant_tricks ( value , & x , & y ) ) ; } </s>

This is a helper function for the Uo constraint for movsi patterns .


<s> void Warning ( SMLoc L , const Twine & Msg ) { getParser ( ) . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


Define the macros that we always expect to have on AArch64 .


<s> static rtx altivec_expand_vec_ext_builtin ( tree arglist , rtx target ) { enum machine_mode tmode , mode0 ; tree arg0 , arg1 ; int elt ; rtx op0 ; arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_extract ( target , op0 , elt ) ; return target ; } </s>


"%qE attribute only applies to functions"

Handle an `` trap_exit '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool ix86_using_red_zone ( void ) { return TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI ; } </s>


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 0 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool arm_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { if ( ! TARGET_32BIT ) return false ; * p1 = CC_REGNUM ; * p2 = TARGET_VFP_BASE ? VFPCC_REGNUM : INVALID_REGNUM ; return true ; } </s>

Implement TARGET_FIXED_CONDITION_CODE_REGS . We only have condition code registers when not targetting Thumb1 . The VFP condition register only exists when generating hard-float code .


<s> bool MMIXAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static const char * rs6000_xcoff_visibility ( tree decl ) { static const char * const visibility_types [ ] = { "" , ",protected" , ",hidden" , ",internal" } ; enum symbol_visibility vis = DECL_VISIBILITY ( decl ) ; return visibility_types [ vis ] ; } </s>

Helper function to calculate visibility of a DECL and return the value as a const string .

rs6000 "" ",protected" ",hidden" ",internal"


<s> static void mips_adjust_block_mem ( rtx mem , HOST_WIDE_INT length , rtx * loop_reg , rtx * loop_mem ) { * loop_reg = copy_addr_to_reg ( XEXP ( mem , 0 ) ) ; * loop_mem = change_address ( mem , BLKmode , * loop_reg ) ; set_mem_align ( * loop_mem , MIN ( MEM_ALIGN ( mem ) , length * BITS_PER_UNIT ) ) ; } </s>

Helper function for doing a loop-based block operation on memory reference MEM . Each iteration of the loop will operate on LENGTH bytes of MEM . Create a new base register for use within the loop and point it to the start of MEM . Create a new memory reference that uses this register . Store them in * LOOP_REG and * LOOP_MEM respectively .


<s> void ix86_expand_truncdf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , mask , TWO52 , one , res , smask , tmp ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & smask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; tmp = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = expand_simple_binop ( mode , MINUS , tmp , TWO52 , tmp , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; mask = ix86_expand_sse_compare_mask ( UNGT , res , xa , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , gen_rtx_AND ( mode , mask , one ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , res , mask , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; ix86_sse_copysign_to_positive ( res , res , force_reg ( mode , operand1 ) , smask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing trunc from OPERAND1 storing into OPERAND0 .


"/* This table has been generated by divtab-sh4.cc.  */"

"\ /* Lookup table translating positive divisor to index into table of\n\ normalized inverse.  N.B. the '0' entry is also the last entry of the\n\ previous table, and causes an unaligned access for division by zero.  */\n\ LOCAL(div_table_ix):"

"\ /* 1/64 .. 1/127, normalized.  There is an implicit leading 1 in bit 32.  */\n\ .balign 4\n\ LOCAL(zero_l):"

Main program to convert flat files into built-in initialization code .


<s>
const
char
*
Cpu0AsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getTargetABI
(
)
)
{
case
Cpu0Subtarget
::
O32
:
return
"abi32"
;
default
:
llvm_unreachable
(
"Unknown Cpu0 ABI"
)
;
;
}
}
</s>


<s> bool sh_attr_renesas_p ( const_tree td ) { if ( TARGET_HITACHI ) return true ; if ( td == NULL_TREE ) return false ; if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return false ; return lookup_attribute ( "renesas" , TYPE_ATTRIBUTES ( td ) ) != NULL_TREE ; } </s>

True if __attribute__ ( ( renesas ) ) or -mrenesas .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; } } </s>


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? 0 : llvm :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .