<s> static void free_label_states ( struct unw_labeled_state * ls ) { struct unw_labeled_state * next ; for ( ; ls ; ls = next ) { next = ls -> next ; free_state_stack ( & ls -> saved_state ) ; free_label_state ( ls ) ; } } </s>


<s> static void ix86_test_loading_full_dump ( ) { rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "x86_64/times-two.rtl" ) ) ; ASSERT_STREQ ( "times_two" , IDENTIFIER_POINTER ( DECL_NAME ( cfun -> decl ) ) ) ; rtx_insn * insn_1 = get_insn_by_uid ( 1 ) ; ASSERT_EQ ( NOTE , GET_CODE ( insn_1 ) ) ; rtx_insn * insn_7 = get_insn_by_uid ( 7 ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_7 ) ) ; ASSERT_EQ ( PARALLEL , GET_CODE ( PATTERN ( insn_7 ) ) ) ; rtx_insn * insn_15 = get_insn_by_uid ( 15 ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_15 ) ) ; ASSERT_EQ ( USE , GET_CODE ( PATTERN ( insn_15 ) ) ) ; ASSERT_EQ ( REG , GET_CODE ( crtl -> return_rtx ) ) ; ASSERT_EQ ( 0 , REGNO ( crtl -> return_rtx ) ) ; ASSERT_EQ ( SImode , GET_MODE ( crtl -> return_rtx ) ) ; } </s>

Verify that the RTL loader copes a dump from print_rtx_function . This test is target-specific since the dump contains target-specific hard reg names .


<s> machreg_t inet_ntoa ( machreg_t in ) { return _inet_ntoa ( in << SHIFT_BITS ) ; } </s>

< arpa/inet.h > has char * inet_ntoa ( struct in_addr ) ; on both IRIX 6.2 and 6.5 , with struct in_addr containing a 32-bit int .


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_HARD_FLOAT ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ( ! df_regs_ever_live_p ( regno ) || call_used_regs [ regno ] ) && ( ! df_regs_ever_live_p ( regno + 1 ) || call_used_regs [ regno + 1 ] ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


<s> unsigned getMaxPrefetchIterationsAhead ( ) const { return MaxPrefetchIterationsAhead ; } </s>

Return the maximum prefetch distance in terms of loop iterations .


<s> TargetLowering :: ConstraintWeight AArch64TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void aarch64_subvti_scratch_regs ( rtx op1 , rtx op2 , rtx * low_dest , rtx * low_in1 , rtx * low_in2 , rtx * high_dest , rtx * high_in1 , rtx * high_in2 ) { * low_dest = gen_reg_rtx ( DImode ) ; * low_in1 = simplify_gen_subreg ( DImode , op1 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * low_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * high_dest = gen_reg_rtx ( DImode ) ; * high_in1 = simplify_gen_subreg ( DImode , op1 , TImode , subreg_highpart_offset ( DImode , TImode ) ) ; * high_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_highpart_offset ( DImode , TImode ) ) ; } </s>

Generate DImode scratch registers for 128-bit ( TImode ) subtraction . This function differs from 'arch64_addti_scratch_regs ' in that OP1 can be an immediate constant ( zero ) . We must call subreg_highpart_offset with DImode and TImode arguments , otherwise VOIDmode will be used for the const_int which generates an internal error from subreg_size_highpart_offset which does not expect a size of zero . OP1 represents the TImode destination operand 1 OP2 represents the TImode destination operand 2 LOW_DEST represents the low half ( DImode ) of TImode operand 0 LOW_IN1 represents the low half ( DImode ) of TImode operand 1 LOW_IN2 represents the low half ( DImode ) of TImode operand 2 HIGH_DEST represents the high half ( DImode ) of TImode operand 0 HIGH_IN1 represents the high half ( DImode ) of TImode operand 1 HIGH_IN2 represents the high half ( DImode ) of TImode operand 2 .


<s> bool doInitialization ( Module & M ) override { SM . reset ( ) ; return AsmPrinter :: doInitialization ( M ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA15 ( ) && getARMSubtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( ) ) ; } return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> rtx mmix_function_arg ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED , int incoming ) { if ( type == void_type_node ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS && ! targetm . calls . must_pass_in_stack ( mode , type ) && ( GET_MODE_BITSIZE ( mode ) <= 64 || argsp -> lib || TARGET_LIBFUNC ) ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; } </s>

Return an rtx for a function argument to go in a register , and 0 for one that must go on stack .


<s> void aarch64_split_sve_subreg_move ( rtx dest , rtx ptrue , rtx src ) { machine_mode mode_with_wider_elts = GET_MODE ( dest ) ; machine_mode mode_with_narrower_elts = GET_MODE ( src ) ; if ( GET_MODE_UNIT_SIZE ( mode_with_wider_elts ) < GET_MODE_UNIT_SIZE ( mode_with_narrower_elts ) ) std :: swap ( mode_with_wider_elts , mode_with_narrower_elts ) ; unsigned int wider_bytes = GET_MODE_UNIT_SIZE ( mode_with_wider_elts ) ; unsigned int unspec ; if ( wider_bytes == 8 ) unspec = UNSPEC_REV64 ; else if ( wider_bytes == 4 ) unspec = UNSPEC_REV32 ; else if ( wider_bytes == 2 ) unspec = UNSPEC_REV16 ; else gcc_unreachable ( ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( wider_bytes ) . require ( ) ; ptrue = gen_lowpart ( pred_mode , ptrue ) ; dest = aarch64_replace_reg_mode ( dest , mode_with_narrower_elts ) ; src = aarch64_replace_reg_mode ( src , mode_with_narrower_elts ) ; src = gen_rtx_UNSPEC ( mode_with_narrower_elts , gen_rtvec ( 1 , src ) , unspec ) ; src = gen_rtx_UNSPEC ( mode_with_narrower_elts , gen_rtvec ( 2 , ptrue , src ) , UNSPEC_MERGE_PTRUE ) ; emit_insn ( gen_rtx_SET ( dest , src ) ) ; } </s>

Split a * aarch64_sve_mov < mode > _subreg_be pattern with the given operands .


<s> void X86PreTileConfig :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static poly_uint16 aarch64_convert_sve_vector_bits ( aarch64_sve_vector_bits_enum value ) { if ( value == SVE_SCALABLE || value == SVE_128 ) return poly_uint16 ( 2 , 2 ) ; else return ( int ) value / 64 ; } </s>

Return the VG value associated with -msve-vector-bits= value VALUE .


<s> static bool expand_vec_perm_vpermil ( struct expand_vec_perm_d * d ) { rtx rperm [ 8 ] , vperm ; unsigned i ; if ( ! TARGET_AVX || d -> vmode != V8SFmode || ! d -> one_operand_p ) return false ; for ( i = 0 ; i < 8 ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( i < 4 ? e >= 4 : e < 4 ) return false ; } if ( d -> testing_p ) return true ; for ( i = 0 ; i < 8 ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e >= 8 + 4 ) e -= 8 ; else if ( e >= 4 ) e -= 4 ; rperm [ i ] = GEN_INT ( e ) ; } vperm = gen_rtx_CONST_VECTOR ( V8SImode , gen_rtvec_v ( 8 , rperm ) ) ; vperm = force_reg ( V8SImode , vperm ) ; emit_insn ( gen_avx_vpermilvarv8sf3 ( d -> target , d -> op0 , vperm ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement D in terms of the variable form of vpermilps . Note that we will have already failed the immediate input vpermilps , which requires that the high and low part shuffle be identical ; the variable form does n't require that .


<s>
MipsSubtarget
&
MipsSubtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
,
const
TargetMachine
&
TM
)
{
std
::
string
CPUName
=
MIPS_MC
::
selectMipsCPU
(
TM
.
getTargetTriple
(
)
,
CPU
)
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
InMips16Mode
&&
!
IsSoftFloat
)
InMips16HardFloat
=
true
;
if
(
StackAlignOverride
)
stackAlignment
=
*
StackAlignOverride
;
else
if
(
isABI_N32
(
)
||
isABI_N64
(
)
)
stackAlignment
=
Align
(
16
)
;
else
{
assert
(
isABI_O32
(
)
&&
"Unknown ABI for stack alignment!"
)
;
stackAlignment
=
Align
(
8
)
;
}
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

Mips
Mips
Mips
MIPS_MC::selectMipsCPU
Mips
Mips
16
"Unknown ABI for stack alignment!"
8


<s> static bool rs6000_global_entry_point_needed_p ( void ) { if ( DEFAULT_ABI != ABI_ELFv2 ) return false ; if ( TARGET_SINGLE_PIC_BASE ) return false ; if ( cfun -> is_thunk ) return true ; return cfun -> machine -> r2_setup_needed ; } </s>

Return whether we need to emit an ELFv2 global entry point prologue .


<s> void thumb_reload_out_hi ( rtx * operands ) { emit_insn ( gen_thumb_movhi_clobber ( operands [ 0 ] , operands [ 1 ] , operands [ 2 ] ) ) ; } </s>

Handle storing a half-word to memory during reload .


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMicroMipsSizeReductionPass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsLongBranchPass ( ) ) ; addPass ( createMipsHazardSchedule ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
&&
MEM_P
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
auto_vec
<
rtx_insn
*
>
and_insns
;
auto_vec
<
rtx
>
and_ops
;
bool
is_any_def_and
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insns
,
&
and_ops
)
;
if
(
is_any_def_and
)
{
gcc_assert
(
and_insns
.
length
(
)
==
and_ops
.
length
(
)
)
;
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
new_reg
=
0
;
rtx
and_mask
=
0
;
for
(
unsigned
i
=
0
;
i
<
and_insns
.
length
(
)
;
i
++
)
{
rtx_insn
*
and_insn
=
and_insns
[
i
]
;
rtx
and_op
=
and_ops
[
i
]
;
rtx
and_base
=
XEXP
(
and_op
,
0
)
;
if
(
!
new_reg
)
{
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
and_mask
=
XEXP
(
and_op
,
1
)
;
}
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
}
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
new_reg
)
,
new_reg
,
and_mask
)
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> bool FISCPassConfig :: addPreISel ( ) { return false ; } </s>


<s> unsigned ARMAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { ARMOperand * Op = static_cast < ARMOperand * > ( AsmOp ) ; if ( Kind == MCK__35_0 && Op -> isImm ( ) ) { const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op -> getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == 0 ) return Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> bool X86AvoidSFBPass :: alias ( const MachineMemOperand & Op1 , const MachineMemOperand & Op2 ) const { if ( ! Op1 . getValue ( ) || ! Op2 . getValue ( ) ) return true ; int64_t MinOffset = std :: min ( Op1 . getOffset ( ) , Op2 . getOffset ( ) ) ; int64_t Overlapa = Op1 . getSize ( ) + Op1 . getOffset ( ) - MinOffset ; int64_t Overlapb = Op2 . getSize ( ) + Op2 . getOffset ( ) - MinOffset ; return ! AA -> isNoAlias ( MemoryLocation ( Op1 . getValue ( ) , Overlapa , Op1 . getAAInfo ( ) ) , MemoryLocation ( Op2 . getValue ( ) , Overlapb , Op2 . getAAInfo ( ) ) ) ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


<s> static void mips16_emit_constants ( struct mips16_constant * constants , rtx_insn * insn ) { int label_num = constants ? CODE_LABEL_NUMBER ( constants -> label ) : 0 ; struct mips16_constant * c , * next ; int align ; align = 0 ; if ( constants ) insn = emit_insn_after ( gen_consttable ( GEN_INT ( label_num ) ) , insn ) ; for ( c = constants ; c != NULL ; c = next ) { if ( align < GET_MODE_SIZE ( c -> mode ) ) { int align_log = floor_log2 ( GET_MODE_SIZE ( c -> mode ) ) ; insn = emit_insn_after ( gen_align ( GEN_INT ( align_log ) ) , insn ) ; } align = GET_MODE_SIZE ( c -> mode ) ; insn = emit_label_after ( c -> label , insn ) ; insn = mips16_emit_constants_1 ( c -> mode , c -> value , insn ) ; next = c -> next ; free ( c ) ; } if ( constants ) insn = emit_insn_after ( gen_consttable_end ( GEN_INT ( label_num ) ) , insn ) ; emit_barrier_after ( insn ) ; } </s>

Dump out the constants in CONSTANTS after INSN .


<s> static void register_tuple_type ( unsigned int num_vectors , unsigned int type_index ) { aarch64_simd_type_info * type = & aarch64_simd_types [ type_index ] ; const char * vector_type_name = type -> name ; char tuple_type_name [ sizeof ( "bfloat16x4x2_t" ) ] ; snprintf ( tuple_type_name , sizeof ( tuple_type_name ) , "%.*sx%d_t" , ( int ) strlen ( vector_type_name ) - 4 , vector_type_name + 2 , num_vectors ) ; tuple_type_name [ 0 ] = TOLOWER ( tuple_type_name [ 0 ] ) ; tree vector_type = type -> itype ; tree array_type = build_array_type_nelts ( vector_type , num_vectors ) ; if ( type -> mode == DImode ) { if ( num_vectors == 2 ) SET_TYPE_MODE ( array_type , V2x1DImode ) ; else if ( num_vectors == 3 ) SET_TYPE_MODE ( array_type , V3x1DImode ) ; else if ( num_vectors == 4 ) SET_TYPE_MODE ( array_type , V4x1DImode ) ; } unsigned int alignment = known_eq ( GET_MODE_SIZE ( type -> mode ) , 16 ) ? 128 : 64 ; machine_mode tuple_mode = TYPE_MODE_RAW ( array_type ) ; gcc_assert ( VECTOR_MODE_P ( tuple_mode ) && TYPE_MODE ( array_type ) == tuple_mode && TYPE_ALIGN ( array_type ) == alignment ) ; tree field = build_decl ( input_location , FIELD_DECL , get_identifier ( "val" ) , array_type ) ; tree t = lang_hooks . types . simulate_record_decl ( input_location , tuple_type_name , make_array_slice ( & field , 1 ) ) ; gcc_assert ( TYPE_MODE_RAW ( t ) == TYPE_MODE ( t ) && ( flag_pack_struct || maximum_field_alignment || ( TYPE_MODE_RAW ( t ) == tuple_mode && TYPE_ALIGN ( t ) == alignment ) ) ) ; aarch64_simd_tuple_modes [ type_index ] [ num_vectors - 2 ] = tuple_mode ; aarch64_simd_tuple_types [ type_index ] [ num_vectors - 2 ] = t ; } </s>

Register the tuple type that contains NUM_VECTORS vectors of type TYPE .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static void ix86_emit_save_regs ( void ) { unsigned int regno ; rtx_insn * insn ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno -- > 0 ; ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) { insn = emit_insn ( gen_push ( gen_rtx_REG ( word_mode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save registers in the prologue .


<s> static bool nds32_rtx_costs ( rtx x , int code , int outer_code , int opno , int * total , bool speed ) { return nds32_rtx_costs_impl ( x , code , outer_code , opno , total , speed ) ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


"The Prefetches vector should contain at least a value if "

"Unexpected change in X86 operand offset order."

runOnMachineFunction - Emit the function body .


<s> bool AArch64SIMDInstrOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const AArch64InstrInfo * AAII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( & ST ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; bool Changed = false ; for ( auto OptimizationKind : { VectorElem , Interleave } ) { if ( ! shouldExitEarly ( & MF , OptimizationKind ) ) { SmallVector < MachineInstr * , 8 > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { bool InstRewrite ; if ( OptimizationKind == VectorElem ) InstRewrite = optimizeVectElement ( MI ) ; else InstRewrite = optimizeLdStInterleave ( MI ) ; if ( InstRewrite ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent ( ) ; } } return Changed ; } </s>


"  Mark r%d def in insn %d as requiring both modes in chain #%d\n"

For DImode conversion , mark register defined by DEF as requiring conversion .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasOptNone ( ) ) OptimizationGoal = 6 ; else if ( F . hasMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . hasOptSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> emitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; emitAlignment ( Align ( 2 ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> emitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>


<s> bool AArch64TTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { default : break ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : Info . ReadMem = true ; Info . WriteMem = false ; Info . Vol = false ; Info . NumMemRefs = 1 ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; break ; case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : Info . ReadMem = false ; Info . WriteMem = true ; Info . Vol = false ; Info . NumMemRefs = 1 ; Info . PtrVal = Inst -> getArgOperand ( Inst -> getNumArgOperands ( ) - 1 ) ; break ; } switch ( Inst -> getIntrinsicID ( ) ) { default : return false ; case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_st2 : Info . MatchingId = VECTOR_LDST_TWO_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_st3 : Info . MatchingId = VECTOR_LDST_THREE_ELEMENTS ; break ; case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_st4 : Info . MatchingId = VECTOR_LDST_FOUR_ELEMENTS ; break ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static type_suffix_index parse_element_type ( const function_instance & instance , const char * & format ) { int ch = * format ++ ; if ( ch == 'f' || ch == 's' || ch == 'u' ) { type_class_index tclass = ( ch == 'f' ? TYPE_float : ch == 's' ? TYPE_signed : TYPE_unsigned ) ; char * end ; unsigned int bits = strtol ( format , & end , 10 ) ; format = end ; if ( bits == 0 || bits == 1 ) bits = instance . type_suffix ( bits ) . element_bits ; return find_type_suffix ( tclass , bits ) ; } if ( ch == 'w' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; if ( type_suffixes [ suffix ] . integer_p ) return find_type_suffix ( type_suffixes [ suffix ] . tclass , 64 ) ; return suffix ; } if ( ch == 'p' ) return TYPE_SUFFIX_b ; if ( ch == 'B' ) return TYPE_SUFFIX_bf16 ; if ( ch == 'q' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return find_type_suffix ( type_suffixes [ suffix ] . tclass , type_suffixes [ suffix ] . element_bits / 4 ) ; } if ( ch == 'h' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; if ( suffix == TYPE_SUFFIX_b ) return suffix ; return find_type_suffix ( type_suffixes [ suffix ] . tclass , type_suffixes [ suffix ] . element_bits / 2 ) ; } if ( ch == '0' || ch == '1' ) return instance . type_suffix_ids [ ch - '0' ] ; gcc_unreachable ( ) ; } </s>

Parse and move past an element type in FORMAT and return it as a type suffix . The format is : [ 01 ] - the element type in type suffix 0 or 1 of INSTANCE f < bits > - a floating-point type with the given number of bits f [ 01 ] - a floating-point type with the same width as type suffix 0 or 1 B - bfloat16_t h < elt > - a half-sized version of < elt > p - a predicate ( represented as TYPE_SUFFIX_b ) q < elt > - a quarter-sized version of < elt > s < bits > - a signed type with the given number of bits s [ 01 ] - a signed type with the same width as type suffix 0 or 1 u < bits > - an unsigned type with the given number of bits u [ 01 ] - an unsigned type with the same width as type suffix 0 or 1 w < elt > - a 64-bit version of < elt > if < elt > is integral , otherwise < elt > where < elt > is another element type .


<s> bool SystemZTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { if ( Subtarget . hasVector ( ) ) VerifyVectorTypes ( Outs ) ; for ( auto & Out : Outs ) if ( Out . ArgVT == MVT :: i128 ) return false ; SmallVector < CCValAssign , 16 > RetLocs ; CCState RetCCInfo ( CallConv , isVarArg , MF , RetLocs , Context ) ; return RetCCInfo . CheckReturn ( Outs , RetCC_SystemZ ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

SystemZ SystemZ ISD::OutputArg MVT::i128 16 SystemZ


<s> void X86InsertPrefetch :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
std
::
unique_ptr
<
LanaiOperand
>
LanaiAsmParser
::
parseIdentifier
(
)
{
SMLoc
Start
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
SMLoc
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
const
MCExpr
*
Res
,
*
RHS
=
nullptr
;
LanaiMCExpr
::
VariantKind
Kind
=
LanaiMCExpr
::
VK_Lanai_None
;
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
Identifier
)
return
nullptr
;
StringRef
Identifier
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
if
(
Identifier
.
equals_lower
(
"hi"
)
)
Kind
=
LanaiMCExpr
::
VK_Lanai_ABS_HI
;
else
if
(
Identifier
.
equals_lower
(
"lo"
)
)
Kind
=
LanaiMCExpr
::
VK_Lanai_ABS_LO
;
if
(
Kind
!=
LanaiMCExpr
::
VK_Lanai_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
LParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected '('"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
if
(
Parser
.
parseIdentifier
(
Identifier
)
)
return
nullptr
;
}
if
(
Lexer
.
getKind
(
)
==
AsmToken
::
Plus
&&
Parser
.
parseExpression
(
RHS
)
)
return
nullptr
;
if
(
Kind
!=
LanaiMCExpr
::
VK_Lanai_None
)
{
if
(
Lexer
.
getKind
(
)
!=
AsmToken
::
RParen
)
{
Error
(
Lexer
.
getLoc
(
)
,
"Expected ')'"
)
;
return
nullptr
;
}
Lexer
.
Lex
(
)
;
}
End
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
MCSymbol
*
Sym
=
getContext
(
)
.
getOrCreateSymbol
(
Identifier
)
;
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
Sym
,
getContext
(
)
)
;
Res
=
LanaiMCExpr
::
create
(
Kind
,
Expr
,
getContext
(
)
)
;
if
(
RHS
)
Res
=
MCBinaryExpr
::
createAdd
(
Res
,
RHS
,
getContext
(
)
)
;
return
LanaiOperand
::
createImm
(
Res
,
Start
,
End
)
;
}
</s>

Parse an identifier or string ( as a quoted identifier ) and set Res to the identifier contents .

Lanai
Lanai
Lanai
1
Lanai
Lanai
Lanai
"hi"
Lanai
Lanai
"lo"
Lanai
Lanai
Lanai
Lanai
"Expected '('"
Lanai
Lanai
"Expected ')'"
1
Lanai
LanaiOperand::createImm


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
.
bitcastToAPInt
(
)
.
getZExtValue
(
)
;
if
(
!
getFPImmIsExact
(
)
)
OS
<<
" (inexact)"
;
OS
<<
">"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
if
(
!
getShiftExtendAmount
(
)
&&
!
hasShiftExtendAmount
(
)
)
break
;
LLVM_FALLTHROUGH
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
" (inexact)"
">"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<register "
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> static bool sh_scalar_mode_supported_p ( machine_mode mode ) { if ( TARGET_SHMEDIA32 && mode == TImode ) return false ; return default_scalar_mode_supported_p ( mode ) ; } </s>

The scalar modes supported differs from the default version in TImode for 32-bit SHMEDIA .


<s> static int ia64_adjust_cost ( rtx_insn * insn , int dep_type1 , rtx_insn * dep_insn , int cost , dw_t dw ) { enum reg_note dep_type = ( enum reg_note ) dep_type1 ; enum attr_itanium_class dep_class ; enum attr_itanium_class insn_class ; insn_class = ia64_safe_itanium_class ( insn ) ; dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return 0 ; if ( dw == MIN_DEP_WEAK ) return param_sched_mem_true_dep_cost ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF ) return 0 ; else return cost ; } if ( dep_type != REG_DEP_OUTPUT ) return cost ; if ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF ) return 0 ; return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> static bool save_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( crtl -> calls_eh_return && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return true ; if ( TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) return true ; if ( DEFAULT_ABI == ABI_V4 && ( flag_pic == 1 || ( flag_pic && TARGET_SECURE_PLT ) ) && df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) return true ; if ( DEFAULT_ABI == ABI_DARWIN && flag_pic && crtl -> uses_pic_offset_table ) return true ; } return ! call_used_regs [ reg ] && df_regs_ever_live_p ( reg ) ; } </s>

Determine whether the REG is really used .


<s> void ARMELFStreamer :: Reset ( ) { ExTab = NULL ; FnStart = NULL ; Personality = NULL ; CantUnwind = false ; } </s>


<s> bool IA64TargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createIA64BundlingPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> inline bool isPseudo ( uint64_t TSFlags ) { return ( TSFlags & X86II :: FormMask ) == Pseudo ; } </s>

Return true if this is a pseudo instruction that does n't correspond to a real machine instruction .


"predicated instruction in conditional sequence"

Print condition code to STREAM . Helper function for arm_print_operand .


<s> static tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE ; } </s>

Target hook for early folding of built-ins , shamelessly stolen from ia64.cc .


<s> static bool rs6000_hard_regno_call_part_clobbered ( unsigned int , unsigned int regno , machine_mode mode ) { if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > 4 && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 && ! FLOAT128_2REG_P ( mode ) ) return true ; return false ; } </s>


<s> static void init_float128_ibm ( machine_mode mode ) { if ( ! TARGET_XL_COMPAT ) { set_optab_libfunc ( add_optab , mode , "__gcc_qadd" ) ; set_optab_libfunc ( sub_optab , mode , "__gcc_qsub" ) ; set_optab_libfunc ( smul_optab , mode , "__gcc_qmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "__gcc_qdiv" ) ; if ( ! ( TARGET_HARD_FLOAT && ( TARGET_FPRS || TARGET_E500_DOUBLE ) ) ) { set_optab_libfunc ( neg_optab , mode , "__gcc_qneg" ) ; set_optab_libfunc ( eq_optab , mode , "__gcc_qeq" ) ; set_optab_libfunc ( ne_optab , mode , "__gcc_qne" ) ; set_optab_libfunc ( gt_optab , mode , "__gcc_qgt" ) ; set_optab_libfunc ( ge_optab , mode , "__gcc_qge" ) ; set_optab_libfunc ( lt_optab , mode , "__gcc_qlt" ) ; set_optab_libfunc ( le_optab , mode , "__gcc_qle" ) ; set_conv_libfunc ( sext_optab , mode , SFmode , "__gcc_stoq" ) ; set_conv_libfunc ( sext_optab , mode , DFmode , "__gcc_dtoq" ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , "__gcc_qtos" ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , "__gcc_qtod" ) ; set_conv_libfunc ( sfix_optab , SImode , mode , "__gcc_qtoi" ) ; set_conv_libfunc ( ufix_optab , SImode , mode , "__gcc_qtou" ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , "__gcc_itoq" ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , "__gcc_utoq" ) ; } if ( ! ( TARGET_HARD_FLOAT && TARGET_FPRS ) ) set_optab_libfunc ( unord_optab , mode , "__gcc_qunord" ) ; } else { set_optab_libfunc ( add_optab , mode , "_xlqadd" ) ; set_optab_libfunc ( sub_optab , mode , "_xlqsub" ) ; set_optab_libfunc ( smul_optab , mode , "_xlqmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "_xlqdiv" ) ; } if ( mode == IFmode ) { set_conv_libfunc ( sext_optab , mode , SDmode , "__dpd_extendsdtf2" ) ; set_conv_libfunc ( sext_optab , mode , DDmode , "__dpd_extendddtf2" ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , "__dpd_trunctftd2" ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , "__dpd_trunctfsd2" ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , "__dpd_trunctfdd2" ) ; set_conv_libfunc ( sext_optab , TDmode , mode , "__dpd_extendtdtf2" ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , "__fixtfti" ) ; set_conv_libfunc ( ufix_optab , TImode , mode , "__fixunstfti" ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , "__floattitf" ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , "__floatuntitf" ) ; } } } </s>

Set up AIX/Darwin/64-bit Linux quad floating point routines .


<s> void MipsMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printMemReference ( MI , OpNo , O , "no-rip" ) ; return false ; } } printMemReference ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool ia64_const_ok_for_letter_p ( HOST_WIDE_INT value , char c ) { switch ( c ) { case 'I' : return CONST_OK_FOR_I ( value ) ; case 'J' : return CONST_OK_FOR_J ( value ) ; case 'K' : return CONST_OK_FOR_K ( value ) ; case 'L' : return CONST_OK_FOR_L ( value ) ; case 'M' : return CONST_OK_FOR_M ( value ) ; case 'N' : return CONST_OK_FOR_N ( value ) ; case 'O' : return CONST_OK_FOR_O ( value ) ; case 'P' : return CONST_OK_FOR_P ( value ) ; default : return false ; } } </s>


<s> static void init_insn_group_barriers ( void ) { memset ( rws_sum , 0 , sizeof ( rws_sum ) ) ; first_instruction = 1 ; } </s>

Clear out the state for group_barrier_needed_p at the start of a sequence of insns .


"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void gen_conditional_move ( rtx * operands ) { enum rtx_code code ; rtx op0 , op1 ; code = GET_CODE ( operands [ 1 ] ) ; mips_emit_compare ( & code , & op0 , & op1 , true ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ 0 ] ) , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , operands [ 2 ] , operands [ 3 ] ) ) ) ; } </s>

Emit the common code for conditional moves . OPERANDS is the array of operands passed to the conditional move define_expand .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2Base
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2Base
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
report_fatal_error
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
mf
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
&
*
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
static
void
arm_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
function
)
{
static
int
thunk_label
=
0
;
char
label
[
256
]
;
int
mi_delta
=
delta
;
const
char
*
const
mi_op
=
mi_delta
<
0
"sub"
:
"add"
;
int
shift
=
0
;
int
this_regno
=
(
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
1
:
0
)
;
if
(
mi_delta
<
0
)
mi_delta
=
mi_delta
;
if
(
TARGET_THUMB
)
{
int
labelno
=
thunk_label
++
;
ASM_GENERATE_INTERNAL_LABEL
(
label
,
"LTHUMBFUNC"
,
labelno
)
;
fputs
(
"\tldr\tr12, "
,
file
)
;
assemble_name
(
file
,
label
)
;
fputc
(
'\n'
,
file
)
;
}
while
(
mi_delta
!=
0
)
{
if
(
(
mi_delta
&
(
3
<<
shift
)
)
==
0
)
shift
+=
2
;
else
{
asm_fprintf
(
file
,
"\t%s\t%r, %r, #%d\n"
,
mi_op
,
this_regno
,
this_regno
,
mi_delta
&
(
0xff
<<
shift
)
)
;
mi_delta
&=
~
(
0xff
<<
shift
)
;
shift
+=
8
;
}
}
if
(
TARGET_THUMB
)
{
fprintf
(
file
,
"\tbx\tr12\n"
)
;
ASM_OUTPUT_ALIGN
(
file
,
2
)
;
assemble_name
(
file
,
label
)
;
fputs
(
":\n"
,
file
)
;
assemble_integer
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
4
,
BITS_PER_WORD
,
1
)
;
}
else
{
fputs
(
"\tb\t"
,
file
)
;
assemble_name
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
0
)
)
;
if
(
NEED_PLT_RELOC
)
fputs
(
"(PLT)"
,
file
)
;
fputc
(
'\n'
,
file
)
;
}
}
</s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s>
void
SystemZPostRASchedStrategy
::
leaveMBB
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Leaving "
<<
printMBBReference
(
*
MBB
)
<<
"\n"
;
)
;
advanceTo
(
MBB
->
getFirstTerminator
(
)
)
;
}
</s>

Tell the strategy that current MBB is done .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> int simd_immediate_valid_for_move ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = simd_valid_immediate ( op , mode , 0 , & tmpconst , & tmpwidth ) ; if ( retval == - 1 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use as either a Neon or MVE VMOV ( or , implicitly , VMVN ) immediate . Write back width per element to * ELEMENTWIDTH ( or zero for float elements ) , and a modified constant ( whatever should be output for a VMOV ) in * MODCONST . `` neon_immediate_valid_for_move '' function is modified to `` simd_immediate_valid_for_move '' as this function will be used both by neon and mve .


<s> const Cpu0InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static rtx altivec_expand_st_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , bool * expandedp ) { tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; tree arglist = TREE_OPERAND ( exp , 1 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 ; enum machine_mode mode0 , mode1 ; rtx pat , op0 , op1 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_ST_INTERNAL_16qi : icode = CODE_FOR_altivec_stvx_v16qi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_8hi : icode = CODE_FOR_altivec_stvx_v8hi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4si : icode = CODE_FOR_altivec_stvx_v4si ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4sf : icode = CODE_FOR_altivec_stvx_v4sf ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; mode1 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp = true ; return NULL_RTX ; } </s>


<s> static bool rs6000_secondary_reload_direct_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { bool ret = false ; enum insn_code icode = CODE_FOR_nothing ; int cost = 0 ; int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_POWERPC64 ) { if ( size == 16 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( mode == SFmode ) { if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } else if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 2 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } } } if ( TARGET_POWERPC64 && size == 16 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_vsx_gpr ; } else if ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) { cost = 3 ; icode = reg_addr [ mode ] . reload_gpr_vsx ; } } else if ( ! TARGET_POWERPC64 && size == 8 ) { if ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && ! altivec_p ) { cost = 3 ; icode = reg_addr [ mode ] . reload_fpr_gpr ; } } if ( icode != CODE_FOR_nothing ) { ret = true ; if ( sri ) { sri -> icode = icode ; sri -> extra_cost = cost ; } } return ret ; } </s>

Power8 helper function for rs6000_secondary_reload , handle all of the special direct moves that involve allocating an extra register , return the insn code of the helper function if there is such a function or CODE_FOR_nothing if not .


<s> bool FPGATTIImpl :: isLegalAddImmediate ( int64_t Imm ) { return true ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> bool isTarget64BitLP64 ( ) const { return Is64Bit && ( ! TargetTriple . isX32 ( ) && ! TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


<s>
unsigned
PPCVSXSwapRemoval
::
lookThruCopyLike
(
unsigned
SrcReg
,
unsigned
VecIdx
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
;
if
(
MI
->
isCopy
(
)
)
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
Register
::
isVirtualRegister
(
CopySrcReg
)
)
{
if
(
!
isScalarVecReg
(
CopySrcReg
)
)
SwapVector
[
VecIdx
]
.
MentionsPhysVR
=
1
;
return
CopySrcReg
;
}
return
lookThruCopyLike
(
CopySrcReg
,
VecIdx
)
;
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


<s> void ia64_split_return_addr_rtx ( rtx dest ) { rtx src ; if ( TEST_HARD_REG_BIT ( current_frame_info . mask , BR_REG ( 0 ) ) ) { if ( current_frame_info . reg_save_b0 != 0 ) src = gen_rtx_REG ( DImode , current_frame_info . reg_save_b0 ) ; else { HOST_WIDE_INT off ; unsigned int regno ; off = ( current_frame_info . spill_cfa_off + current_frame_info . spill_size ) ; for ( regno = GR_REG ( 1 ) ; regno <= GR_REG ( 31 ) ; ++ regno ) if ( TEST_HARD_REG_BIT ( current_frame_info . mask , regno ) ) off -= 8 ; if ( frame_pointer_needed ) src = hard_frame_pointer_rtx ; else { src = stack_pointer_rtx ; off += current_frame_info . total_size ; } if ( CONST_OK_FOR_I ( off ) ) emit_insn ( gen_adddi3 ( dest , src , GEN_INT ( off ) ) ) ; else { emit_move_insn ( dest , GEN_INT ( off ) ) ; emit_insn ( gen_adddi3 ( dest , src , dest ) ) ; } src = gen_rtx_MEM ( Pmode , dest ) ; } } else src = gen_rtx_REG ( DImode , BR_REG ( 0 ) ) ; emit_move_insn ( dest , src ) ; } </s>

Split this value after reload , now that we know where the return address is saved .


<s> bool ARMFrameInfo :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> void ix86_expand_vector_move_misalign ( machine_mode mode , rtx operands [ ] ) { rtx op0 , op1 , m ; op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; if ( GET_MODE_SIZE ( mode ) == 64 || optimize_insn_for_size_p ( ) ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } if ( TARGET_AVX ) { if ( GET_MODE_SIZE ( mode ) == 32 ) ix86_avx256_split_vector_move_misalign ( op0 , op1 ) ; else emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE2 && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } if ( MEM_P ( op1 ) ) { if ( TARGET_SSE2 && mode == V2DFmode ) { rtx zero ; if ( TARGET_SSE_SPLIT_REGS ) { emit_clobber ( op0 ) ; zero = op0 ; } else { zero = CONST0_RTX ( V2DFmode ) ; } m = adjust_address ( op1 , DFmode , 0 ) ; emit_insn ( gen_sse2_loadlpd ( op0 , zero , m ) ) ; m = adjust_address ( op1 , DFmode , 8 ) ; emit_insn ( gen_sse2_loadhpd ( op0 , op0 , m ) ) ; } else { rtx t ; if ( mode != V4SFmode ) t = gen_reg_rtx ( V4SFmode ) ; else t = op0 ; if ( TARGET_SSE_PARTIAL_REG_DEPENDENCY ) emit_move_insn ( t , CONST0_RTX ( V4SFmode ) ) ; else emit_clobber ( t ) ; m = adjust_address ( op1 , V2SFmode , 0 ) ; emit_insn ( gen_sse_loadlps ( t , t , m ) ) ; m = adjust_address ( op1 , V2SFmode , 8 ) ; emit_insn ( gen_sse_loadhps ( t , t , m ) ) ; if ( mode != V4SFmode ) emit_move_insn ( op0 , gen_lowpart ( mode , t ) ) ; } } else if ( MEM_P ( op0 ) ) { if ( TARGET_SSE2 && mode == V2DFmode ) { m = adjust_address ( op0 , DFmode , 0 ) ; emit_insn ( gen_sse2_storelpd ( m , op1 ) ) ; m = adjust_address ( op0 , DFmode , 8 ) ; emit_insn ( gen_sse2_storehpd ( m , op1 ) ) ; } else { if ( mode != V4SFmode ) op1 = gen_lowpart ( V4SFmode , op1 ) ; m = adjust_address ( op0 , V2SFmode , 0 ) ; emit_insn ( gen_sse_storelps ( m , op1 ) ) ; m = adjust_address ( op0 , V2SFmode , 8 ) ; emit_insn ( gen_sse_storehps ( m , copy_rtx ( op1 ) ) ) ; } } else gcc_unreachable ( ) ; } </s>

Implement the movmisalign patterns for SSE . Non-SSE modes go straight to ix86_expand_vector_move .


<s> static void cirrus_reorg ( rtx first ) { enum attr_cirrus attr ; rtx body = PATTERN ( first ) ; rtx t ; int nops ; if ( GET_CODE ( first ) == JUMP_INSN && GET_CODE ( body ) != RETURN ) { nops = 0 ; t = next_nonnote_insn ( first ) ; if ( arm_cirrus_insn_p ( t ) ) ++ nops ; if ( arm_cirrus_insn_p ( next_nonnote_insn ( t ) ) ) ++ nops ; while ( nops -- ) emit_insn_after ( gen_nop ( ) , first ) ; return ; } if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , 0 ) > 0 ) body = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( body ) == SET ) { rtx lhs = XEXP ( body , 0 ) , rhs = XEXP ( body , 1 ) ; if ( get_attr_cirrus ( first ) == CIRRUS_DOUBLE ) { if ( arm_cirrus_insn_p ( next_nonnote_insn ( first ) ) ) emit_insn_after ( gen_nop ( ) , first ) ; return ; } else if ( arm_memory_load_p ( first ) ) { unsigned int arm_regno ; if ( GET_CODE ( lhs ) == REG ) arm_regno = REGNO ( lhs ) ; else { gcc_assert ( GET_CODE ( rhs ) == REG ) ; arm_regno = REGNO ( rhs ) ; } first = next_nonnote_insn ( first ) ; if ( ! arm_cirrus_insn_p ( first ) ) return ; body = PATTERN ( first ) ; if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , 0 ) ) body = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( body ) == FLOAT ) body = XEXP ( body , 0 ) ; if ( get_attr_cirrus ( first ) == CIRRUS_MOVE && GET_CODE ( XEXP ( body , 1 ) ) == REG && arm_regno == REGNO ( XEXP ( body , 1 ) ) ) emit_insn_after ( gen_nop ( ) , first ) ; return ; } } if ( ! first || GET_CODE ( first ) != INSN || GET_CODE ( PATTERN ( first ) ) == USE || GET_CODE ( PATTERN ( first ) ) == CLOBBER ) return ; attr = get_attr_cirrus ( first ) ; if ( attr == CIRRUS_COMPARE ) { nops = 0 ; t = next_nonnote_insn ( first ) ; if ( arm_cirrus_insn_p ( t ) ) ++ nops ; if ( arm_cirrus_insn_p ( next_nonnote_insn ( t ) ) ) ++ nops ; while ( nops -- ) emit_insn_after ( gen_nop ( ) , first ) ; return ; } } </s>

Cirrus reorg for invalid instruction combinations .


<s> const char * fp_immediate_constant ( rtx x ) { REAL_VALUE_TYPE r ; int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; for ( i = 0 ; i < 8 ; i ++ ) if ( REAL_VALUES_EQUAL ( r , values_fp [ i ] ) ) return strings_fp [ i ] ; gcc_unreachable ( ) ; } </s>

If the rtx is the correct value then return the string of the number . In this way we can ensure that valid double constants are generated even when cross compiling .


<s> bool LEGRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> static bool aarch64_print_vector_float_operand ( FILE * f , rtx x , bool negate ) { rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) ) return false ; REAL_VALUE_TYPE r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst0 ) ) asm_fprintf ( f , "0.0" ) ; else if ( real_equal ( & r , & dconst1 ) ) asm_fprintf ( f , "1.0" ) ; else if ( real_equal ( & r , & dconsthalf ) ) asm_fprintf ( f , "0.5" ) ; else return false ; return true ; } </s>

Print floating-point vector immediate operand X to F , negating it first if NEGATE is true . Return true on success , false if it is n't a constant we can handle .


<s> static void ia64_soft_fp_init_libfuncs ( void ) { } </s>


<s> void aarch64_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , aarch64_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> void rs6000_asm_output_dwarf_datarel ( FILE * file , int size , const char * label ) { fputs ( integer_asm_op ( size , FALSE ) , file ) ; assemble_name ( file , label ) ; fputs ( "-__gcc_unwind_dbase" , file ) ; } </s>

Output a symbol offset relative to the dbase for the current object . We use __gcc_unwind_dbase as an arbitrary base for dbase and assume signed offsets . __gcc_unwind_dbase is embedded in all executables/libraries through libgcc/config/rs6000/crtdbase.S .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isVTRNMask ( M , VT , WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) || isVTRN_v_undef_Mask ( M , VT , WhichResult ) || isVUZP_v_undef_Mask ( M , VT , WhichResult ) || isVZIP_v_undef_Mask ( M , VT , WhichResult ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static bool mova_p ( rtx_insn * insn ) { return ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC && XINT ( SET_SRC ( PATTERN ( insn ) ) , 1 ) == UNSPEC_MOVA && GET_CODE ( MOVA_LABELREF ( insn ) ) == LABEL_REF ) ; } </s>

Return true if the specified insn is a mova insn .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
KSET0W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORWrr
)
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORWrr
)
)
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool Warning ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) ) { return Parser . Warning ( L , Msg , Ranges ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> MachineMemOperand :: Flags SystemZTargetLowering :: getTargetMMOFlags ( const Instruction & I ) const { if ( auto * SI = dyn_cast < StoreInst > ( & I ) ) if ( SI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; if ( auto * LI = dyn_cast < LoadInst > ( & I ) ) if ( LI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; if ( auto * AI = dyn_cast < AtomicRMWInst > ( & I ) ) if ( AI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; if ( auto * AI = dyn_cast < AtomicCmpXchgInst > ( & I ) ) if ( AI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; return MachineMemOperand :: MONone ; } </s>

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them .


<s> uint64_t VEMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , ( MCFixupKind ) VE :: fixup_ve_srel32 ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static bool loongarch_save_reg_p ( unsigned int regno ) { bool call_saved = ! global_regs [ regno ] && ! call_used_regs [ regno ] ; bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ; if ( call_saved && might_clobber ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && crtl -> calls_eh_return ) return true ; return false ; } </s>

Return true if the current function must save register REGNO .


<s> static void compute_save_world_info ( rs6000_stack_t * info_ptr ) { info_ptr -> world_save_p = 1 ; info_ptr -> world_save_p = ( WORLD_SAVE_P ( info_ptr ) && DEFAULT_ABI == ABI_DARWIN && ! cfun -> has_nonlocal_label && info_ptr -> first_fp_reg_save == FIRST_SAVED_FP_REGNO && info_ptr -> first_gp_reg_save == FIRST_SAVED_GP_REGNO && info_ptr -> first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info_ptr -> cr_save_p ) ; if ( WORLD_SAVE_P ( info_ptr ) ) { rtx_insn * insn ; for ( insn = get_last_insn_anywhere ( ) ; insn ; insn = PREV_INSN ( insn ) ) if ( CALL_P ( insn ) && SIBLING_CALL_P ( insn ) ) { info_ptr -> world_save_p = 0 ; break ; } } if ( WORLD_SAVE_P ( info_ptr ) ) { info_ptr -> vrsave_size = 4 ; info_ptr -> lr_save_p = 1 ; if ( info_ptr -> vrsave_mask == 0 ) info_ptr -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info_ptr -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info_ptr -> first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ; } return ; } </s>

For a very restricted set of circumstances , we can cut down the size of prologues/epilogues by calling our own save/restore-the-world routines .


<s> int pa_is_function_label_plus_const ( rtx op ) { if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , 0 ) ; return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , 0 ) , VOIDmode ) && GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT ) ; } </s>

Returns 1 if OP is a function label involved in a simple addition with a constant . Used to keep certain patterns from matching during instruction combination .


<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { const X86MemoryFoldTableEntry * I = lookupUnfoldTable ( Opc ) ; if ( I == nullptr ) return 0 ; bool FoldedLoad = I -> Flags & TB_FOLDED_LOAD ; bool FoldedStore = I -> Flags & TB_FOLDED_STORE ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; if ( LoadRegIndex ) * LoadRegIndex = I -> Flags & TB_INDEX_MASK ; return I -> DstOp ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s> static void aarch64_emit_inverted_unspec_cond ( rtx target , rtx_code code , machine_mode pred_mode , rtx ptrue , rtx pred , rtx op0 , rtx op1 , bool can_invert_p ) { if ( can_invert_p ) aarch64_emit_unspec_cond ( target , code , pred_mode , pred , op0 , op1 ) ; else { rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_unspec_cond ( tmp , code , pred_mode , pred , op0 , op1 ) ; emit_set_insn ( target , gen_rtx_AND ( pred_mode , gen_rtx_NOT ( pred_mode , tmp ) , ptrue ) ) ; } } </s>

If CAN_INVERT_P , emit an instruction : ( set TARGET ( unspec : PRED_MODE [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) ) where < X > is the operation associated with comparison CODE . Otherwise emit : ( set TMP ( unspec : PRED_MODE [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) ) ( set TARGET ( and : PRED_MODE ( not : PRED_MODE TMP ) PTRUE ) ) where the second instructions sets TARGET to the inverse of TMP .


<s> void DigitalTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const DigitalTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> static void mmix_target_asm_function_epilogue ( FILE * stream , HOST_WIDE_INT locals_size ATTRIBUTE_UNUSED ) { fputc ( '\n' , stream ) ; } </s>


<s> static void rs6000_alloc_sdmode_stack_slot ( void ) { tree t ; basic_block bb ; gimple_stmt_iterator gsi ; gcc_assert ( cfun -> machine -> sdmode_stack_slot == NULL_RTX ) ; if ( ira_use_lra_p ) return ; if ( TARGET_NO_SDMODE_STACK ) return ; FOR_EACH_BB_FN ( bb , cfun ) for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { tree ret = walk_gimple_op ( gsi_stmt ( gsi ) , rs6000_check_sdmode , NULL ) ; if ( ret ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , 0 ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , 0 ) ; return ; } } for ( t = DECL_ARGUMENTS ( cfun -> decl ) ; t ; t = DECL_CHAIN ( t ) ) { if ( TREE_TYPE ( t ) == error_mark_node ) continue ; if ( TYPE_MODE ( TREE_TYPE ( t ) ) == SDmode || TYPE_MODE ( DECL_ARG_TYPE ( t ) ) == SDmode ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , 0 ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , 0 ) ; return ; } } } </s>

Allocate a 64-bit stack slot to be used for copying SDmode values through if this function has any SDmode references . If we are on a power7 or later , we do n't need the 64-bit stack slot since the LFIWZX and STIFWX instructions can load/store the value .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: ADD : case ISD :: SUB : return OptimizeConditonalInDecrement ( N , DAG ) ; case X86ISD :: ADC : return PerformADCCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: AND : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; case X86ISD :: SETCC : return PerformSETCCCombine ( N , DAG ) ; case X86ISD :: SHUFPS : case X86ISD :: SHUFPD : case X86ISD :: PALIGN : case X86ISD :: PUNPCKHBW : case X86ISD :: PUNPCKHWD : case X86ISD :: PUNPCKHDQ : case X86ISD :: PUNPCKHQDQ : case X86ISD :: UNPCKHPS : case X86ISD :: UNPCKHPD : case X86ISD :: PUNPCKLBW : case X86ISD :: PUNPCKLWD : case X86ISD :: PUNPCKLDQ : case X86ISD :: PUNPCKLQDQ : case X86ISD :: UNPCKLPS : case X86ISD :: UNPCKLPD : case X86ISD :: VUNPCKLPS : case X86ISD :: VUNPCKLPD : case X86ISD :: VUNPCKLPSY : case X86ISD :: VUNPCKLPDY : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
unsigned
SparcMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
SparcMCExpr
*
SExpr
=
dyn_cast
<
SparcMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
EvaluateAsAbsolute
(
Res
)
)
return
Res
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> int mems_ok_for_quad_peep ( rtx mem1 , rtx mem2 ) { rtx addr1 , addr2 ; unsigned int reg1 , reg2 ; int offset1 , offset2 ; if ( MEM_VOLATILE_P ( mem1 ) || MEM_VOLATILE_P ( mem2 ) ) return 0 ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( ! REG_P ( XEXP ( addr1 , 0 ) ) ) return 0 ; else { reg1 = REGNO ( XEXP ( addr1 , 0 ) ) ; if ( ! CONST_INT_P ( XEXP ( addr1 , 1 ) ) ) return 0 ; offset1 = INTVAL ( XEXP ( addr1 , 1 ) ) ; } } else if ( ! REG_P ( addr1 ) ) return 0 ; else { reg1 = REGNO ( addr1 ) ; offset1 = 0 ; } if ( GET_CODE ( addr2 ) == PLUS ) { if ( ! REG_P ( XEXP ( addr2 , 0 ) ) ) return 0 ; else { reg2 = REGNO ( XEXP ( addr2 , 0 ) ) ; if ( ! CONST_INT_P ( XEXP ( addr2 , 1 ) ) ) return 0 ; offset2 = INTVAL ( XEXP ( addr2 , 1 ) ) ; } } else if ( ! REG_P ( addr2 ) ) return 0 ; else { reg2 = REGNO ( addr2 ) ; offset2 = 0 ; } if ( reg1 != reg2 ) return 0 ; if ( offset2 != offset1 + 8 ) return 0 ; return 1 ; } </s>

Return 1 if addr1 and addr2 are suitable for lfq or stfq insn . addr1 and addr2 must be in consecutive memory locations ( addr2 == addr1 + 8 ) .


"variadic functions must use the base AAPCS variant"

Get the PCS variant to use for this call . TYPE is the function 's type specification , DECL is the specific declartion . DECL may be null if the call could be indirect or if this is a library call .


<s> bool ARM64PassConfig :: addPreRegAlloc ( ) { addPass ( createARM64AdvSIMDScalar ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCContext & Context = MCA . getContext ( ) ; MCStreamer & OS = getStreamer ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; uint64_t Features = STI . getFeatureBits ( ) ; if ( T . isArch64Bit ( ) && ( Features & Mips :: FeatureN64 ) ) { const MCSectionELF * Sec = Context . getELFSection ( ".MIPS.options" , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 1 , 1 ) ; OS . EmitIntValue ( 40 , 1 ) ; OS . EmitIntValue ( 0 , 2 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 8 ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( ".reginfo" , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; OS . EmitIntValue ( 0 , 4 ) ; } } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> unsigned getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


Relax the instruction in the given fragment to the next wider instruction .


<s> void LanaiFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const LanaiInstrInfo & LII = * static_cast < const LanaiInstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , LII . get ( Lanai :: ADD_I_LO ) , Lanai :: SP ) . addReg ( Lanai :: FP ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , DL , LII . get ( Lanai :: LDW_RI ) , Lanai :: FP ) . addReg ( Lanai :: FP ) . addImm ( - 8 ) . addImm ( LPAC :: ADD ) ; } </s>

Lanai Lanai Lanai Lanai Lanai::ADD_I_LO Lanai::SP Lanai::FP 0 Lanai::LDW_RI Lanai::FP Lanai::FP 8


<s> bool rs6000_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; return for_each_rtx ( & x , & rs6000_tls_symbol_ref_1 , 0 ) ; } </s>

Return 1 if X contains a thread-local symbol .


<s>
SDValue
F2003fTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_F2003f
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
F2003fISD
::
DOSNUD
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void sh_set_return_address ( rtx ra , rtx tmp ) { HARD_REG_SET live_regs_mask ; int d = calc_live_regs ( & live_regs_mask ) ; if ( ! TEST_HARD_REG_BIT ( live_regs_mask , PR_REG ) ) { rtx rr = gen_rtx_REG ( SImode , PR_REG ) ; emit_insn ( GEN_MOV ( rr , ra ) ) ; emit_use ( rr ) ; return ; } int pr_offset = rounded_frame_size ( d ) ; emit_insn ( GEN_MOV ( tmp , GEN_INT ( pr_offset ) ) ) ; if ( frame_pointer_needed ) emit_insn ( GEN_ADD3 ( tmp , tmp , hard_frame_pointer_rtx ) ) ; else emit_insn ( GEN_ADD3 ( tmp , tmp , stack_pointer_rtx ) ) ; tmp = gen_frame_mem ( Pmode , tmp ) ; emit_insn ( GEN_MOV ( tmp , ra ) ) ; emit_use ( tmp ) ; } </s>

Emit code to change the current function 's return address to RA . TEMP is available as a scratch register , if needed .


"SPARC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool LanaiAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * B = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( B -> getTerminator ( ) ) ) return false ; if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) { } return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s>
SDValue
SparcTargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
ConstantPoolSDNode
*
CP
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
CP
->
getConstVal
(
)
,
CP
->
getValueType
(
0
)
,
CP
->
getAlignment
(
)
,
CP
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


<s> static int epilogue_renumber ( rtx * where , int test ) { const char * fmt ; int i ; enum rtx_code code ; if ( * where == 0 ) return 0 ; code = GET_CODE ( * where ) ; switch ( code ) { case REG : if ( REGNO ( * where ) >= 8 && REGNO ( * where ) < 24 ) return 1 ; if ( ! test && REGNO ( * where ) >= 24 && REGNO ( * where ) < 32 ) { if ( ORIGINAL_REGNO ( * where ) ) { rtx n = gen_raw_REG ( GET_MODE ( * where ) , OUTGOING_REGNO ( REGNO ( * where ) ) ) ; ORIGINAL_REGNO ( n ) = ORIGINAL_REGNO ( * where ) ; * where = n ; } else * where = gen_rtx_REG ( GET_MODE ( * where ) , OUTGOING_REGNO ( REGNO ( * where ) ) ) ; } return 0 ; case SCRATCH : case PC : case CONST_INT : case CONST_WIDE_INT : case CONST_DOUBLE : return 0 ; case PLUS : if ( GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM && ( GET_CODE ( XEXP ( * where , 1 ) ) != CONST_INT || INTVAL ( XEXP ( * where , 1 ) ) < SPARC_STACK_BIAS ) ) return 1 ; break ; case MEM : if ( SPARC_STACK_BIAS && GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM ) return 1 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( * where , i ) - 1 ; j >= 0 ; j -- ) if ( epilogue_renumber ( & ( XVECEXP ( * where , i , j ) ) , test ) ) return 1 ; } else if ( fmt [ i ] == 'e' && epilogue_renumber ( & ( XEXP ( * where , i ) ) , test ) ) return 1 ; } return 0 ; } </s>

Return 1 , if any of the registers of the instruction are % l [ 0-7 ] or % o [ 0-7 ] . Such instructions can not be used in the delay slot of return insn on v9 . If TEST is 0 , also rename all % i [ 0-7 ] registers to their % o [ 0-7 ] counterparts .


<s> static void mips_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved , fp_saved ; local_cum = * get_cumulative_args ( cum ) ; mips_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; fp_saved = ( EABI_FLOAT_VARARGS_P ? MAX_ARGS_IN_REGISTERS - local_cum . num_fprs : 0 ) ; if ( ! no_rtl ) { if ( gp_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { machine_mode mode ; int off , i ; off = ROUND_DOWN ( - gp_saved * UNITS_PER_WORD , UNITS_PER_FPVALUE ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += MAX_FPRS_PER_FMT ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; mips_emit_move ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE ; } } } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = ( gp_saved * UNITS_PER_WORD + fp_saved * UNITS_PER_FPREG ) ; } </s>


<s>
const
char
*
mips_output_conditional_branch
(
rtx_insn
*
insn
,
rtx
*
operands
,
const
char
*
branch_if_true
,
const
char
*
branch_if_false
)
{
unsigned
int
length
;
rtx
taken
;
gcc_assert
(
LABEL_P
(
operands
[
0
]
)
)
;
length
=
get_attr_length
(
insn
)
;
if
(
length
<=
8
)
{
mips_branch_likely
=
(
final_sequence
&&
INSN_ANNULLED_BRANCH_P
(
insn
)
)
;
return
branch_if_true
;
}
mips_branch_likely
=
false
;
rtx_code_label
*
not_taken
=
gen_label_rtx
(
)
;
taken
=
operands
[
0
]
;
operands
[
0
]
=
not_taken
;
output_asm_insn
(
branch_if_false
,
operands
)
;
if
(
final_sequence
)
{
if
(
!
INSN_ANNULLED_BRANCH_P
(
insn
)
)
{
final_scan_insn
(
final_sequence
->
insn
(
1
)
,
asm_out_file
,
optimize
,
1
,
)
;
final_sequence
->
insn
(
1
)
->
set_deleted
(
)
;
}
else
output_asm_insn
(
"nop"
,
0
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
}
if
(
TARGET_ABSOLUTE_JUMPS
&&
TARGET_CB_MAYBE
)
{
if
(
!
final_sequence
)
{
output_asm_insn
(
"nop\t\t# hazard nop"
,
0
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
}
output_asm_insn
(
MIPS_ABSOLUTE_JUMP
(
"bc\t%0"
)
,
&
taken
)
;
}
else
if
(
TARGET_ABSOLUTE_JUMPS
)
output_asm_insn
(
MIPS_ABSOLUTE_JUMP
(
"j\t%0%/"
)
,
&
taken
)
;
else
{
mips_output_load_label
(
taken
)
;
if
(
TARGET_CB_MAYBE
)
output_asm_insn
(
"jrc\t%@%]"
,
0
)
;
else
output_asm_insn
(
"jr\t%@%]%/"
,
0
)
;
}
if
(
final_sequence
)
{
if
(
INSN_ANNULLED_BRANCH_P
(
insn
)
)
{
final_scan_insn
(
final_sequence
->
insn
(
1
)
,
asm_out_file
,
optimize
,
1
,
)
;
final_sequence
->
insn
(
1
)
->
set_deleted
(
)
;
}
else
if
(
TARGET_CB_NEVER
)
output_asm_insn
(
"nop"
,
0
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
}
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
not_taken
)
)
;
return
""
;
}
</s>

Output assembly instructions to peform a conditional branch . INSN is the branch instruction . OPERANDS [ 0 ] is the condition . OPERANDS [ 1 ] is the target of the branch . OPERANDS [ 2 ] is the target of the first operand to the condition . If TWO_OPERANDS_P is nonzero the comparison takes two operands ; OPERANDS [ 3 ] will be the second operand . If INVERTED_P is nonzero we are to branch if the condition does not hold . If FLOAT_P is nonzero this is a floating-point comparison . LENGTH is the length ( in bytes ) of the sequence we are to generate . That tells us whether to generate a simple conditional branch , or a reversed conditional branch around a ` jr ' instruction .


<s>
unsigned
PPCTTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
OperandValueKind
Op1Info
,
OperandValueKind
Op2Info
,
OperandValueProperties
Opd1PropInfo
,
OperandValueProperties
Opd2PropInfo
)
const
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static bool loongarch_hard_regno_mode_ok_uncached ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == FCCmode ) return FCC_REG_P ( regno ) ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) ) { if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in loongarch_hard_regno_mode_ok .


"alias without a base object is not yet supported on AIX"

Set up the AsmPrinter when we are working on a new module .


<s> void ia64_split_return_addr_rtx ( rtx dest ) { rtx src ; if ( TEST_HARD_REG_BIT ( current_frame_info . mask , BR_REG ( 0 ) ) ) { if ( current_frame_info . r [ reg_save_b0 ] != 0 ) { src = gen_rtx_REG ( DImode , current_frame_info . r [ reg_save_b0 ] ) ; reg_emitted ( reg_save_b0 ) ; } else { HOST_WIDE_INT off ; unsigned int regno ; rtx off_r ; off = ( current_frame_info . spill_cfa_off + current_frame_info . spill_size ) ; for ( regno = GR_REG ( 1 ) ; regno <= GR_REG ( 31 ) ; ++ regno ) if ( TEST_HARD_REG_BIT ( current_frame_info . mask , regno ) ) off -= 8 ; if ( frame_pointer_needed ) src = hard_frame_pointer_rtx ; else { src = stack_pointer_rtx ; off += current_frame_info . total_size ; } off_r = GEN_INT ( off ) ; if ( satisfies_constraint_I ( off_r ) ) emit_insn ( gen_adddi3 ( dest , src , off_r ) ) ; else { emit_move_insn ( dest , off_r ) ; emit_insn ( gen_adddi3 ( dest , src , dest ) ) ; } src = gen_rtx_MEM ( Pmode , dest ) ; } } else src = gen_rtx_REG ( DImode , BR_REG ( 0 ) ) ; emit_move_insn ( dest , src ) ; } </s>

Split this value after reload , now that we know where the return address is saved .


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , ( MCFixupKind ) Mips :: fixup_Mips_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_CALL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_HI16 ) . Case ( "R_MIPS_CALL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_LO16 ) . Case ( "R_MIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL16 ) . Case ( "R_MIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_OFST ) . Case ( "R_MIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_DISP ) . Case ( "R_MIPS_GOT_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_HI16 ) . Case ( "R_MIPS_GOT_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_LO16 ) . Case ( "R_MIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_Mips_GOTTPREL ) . Case ( "R_MIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_HI ) . Case ( "R_MIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_LO ) . Case ( "R_MIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_Mips_TLSGD ) . Case ( "R_MIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_Mips_TLSLDM ) . Case ( "R_MIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_HI ) . Case ( "R_MIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_LO ) . Case ( "R_MICROMIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_CALL16 ) . Case ( "R_MICROMIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_DISP ) . Case ( "R_MICROMIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_PAGE ) . Case ( "R_MICROMIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_OFST ) . Case ( "R_MICROMIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT16 ) . Case ( "R_MICROMIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOTTPREL ) . Case ( "R_MICROMIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 ) . Case ( "R_MICROMIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_GD ) . Case ( "R_MICROMIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_LDM ) . Case ( "R_MICROMIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 ) . Case ( "R_MIPS_JALR" , ( MCFixupKind ) Mips :: fixup_Mips_JALR ) . Case ( "R_MICROMIPS_JALR" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_JALR ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool aarch64_use_return_insn_p ( void ) { if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; aarch64_layout_frame ( ) ; return cfun -> machine -> frame . frame_size == 0 ; } </s>

Return TRUE if we can use a simple_return insn . This function checks whether the callee saved stack is empty , which means no restore actions are need . The pro_and_epilogue will use this to check whether shrink-wrapping opt is feasible .


<s> int register_ok_for_ldd ( rtx reg ) { if ( ! REG_P ( reg ) ) return 0 ; if ( REGNO ( reg ) < FIRST_PSEUDO_REGISTER ) return ( REGNO ( reg ) % 2 == 0 ) ; return 1 ; } </s>

Return 1 if reg is a pseudo , or is the first register in a hard register pair . This makes it a candidate for use in ldd and std insns .


<s> static void mips_code_end ( void ) { mips_finish_stub ( & mips16_rdhwr_stub ) ; mips_finish_stub ( & mips16_get_fcsr_stub ) ; mips_finish_stub ( & mips16_set_fcsr_stub ) ; } </s>


<s> bool MipsPassConfig :: addPreRegAlloc ( ) { if ( ! getMipsSubtarget ( ) . hasMips64 ( ) ) PM -> add ( createMipsEmitGPRestorePass ( getMipsTargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
void
Finish
(
)
{
const
size_t
VendorHeaderSize
=
4
+
CurrentVendor
.
size
(
)
+
1
;
const
size_t
TagHeaderSize
=
1
+
4
;
Streamer
.
EmitIntValue
(
VendorHeaderSize
+
TagHeaderSize
+
ContentsSize
,
4
)
;
Streamer
.
EmitBytes
(
CurrentVendor
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
Streamer
.
EmitIntValue
(
ARMBuildAttrs
::
File
,
1
)
;
Streamer
.
EmitIntValue
(
TagHeaderSize
+
ContentsSize
,
4
)
;
for
(
unsigned
int
i
=
0
;
i
<
Contents
.
size
(
)
;
++
i
)
{
AttributeItemType
item
=
Contents
[
i
]
;
Streamer
.
EmitULEB128IntValue
(
item
.
Tag
)
;
switch
(
item
.
Type
)
{
default
:
llvm_unreachable
(
"Invalid attribute type"
)
;
case
AttributeItemType
::
NumericAttribute
:
Streamer
.
EmitULEB128IntValue
(
item
.
IntValue
)
;
break
;
case
AttributeItemType
::
TextAttribute
:
Streamer
.
EmitBytes
(
item
.
StringValue
.
upper
(
)
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
break
;
}
}
Contents
.
clear
(
)
;
}
</s>

Finish - Do final processing and write the object to the output stream .


<s> static tree aarch64_builtin_reciprocal ( tree fndecl ) { machine_mode mode = TYPE_MODE ( TREE_TYPE ( fndecl ) ) ; if ( ! use_rsqrt_p ( mode ) ) return NULL_TREE ; unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return aarch64_general_builtin_rsqrt ( subcode ) ; case AARCH64_BUILTIN_SVE : return NULL_TREE ; } gcc_unreachable ( ) ; } </s>

Function to decide when to use the approximate reciprocal square root builtin .


<s> bool sparc_expand_conditional_move ( machine_mode mode , rtx * operands ) { enum rtx_code rc = GET_CODE ( operands [ 1 ] ) ; machine_mode cmp_mode ; rtx cc_reg , dst , cmp ; cmp = operands [ 1 ] ; if ( GET_MODE ( XEXP ( cmp , 0 ) ) == DImode && ! TARGET_ARCH64 ) return false ; if ( GET_MODE ( XEXP ( cmp , 0 ) ) == TFmode && ! TARGET_HARD_QUAD ) cmp = sparc_emit_float_lib_cmp ( XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) , rc ) ; cmp_mode = GET_MODE ( XEXP ( cmp , 0 ) ) ; rc = GET_CODE ( cmp ) ; dst = operands [ 0 ] ; if ( ! rtx_equal_p ( operands [ 2 ] , dst ) && ! rtx_equal_p ( operands [ 3 ] , dst ) ) { if ( reg_overlap_mentioned_p ( dst , cmp ) ) dst = gen_reg_rtx ( mode ) ; emit_move_insn ( dst , operands [ 3 ] ) ; } else if ( operands [ 2 ] == dst ) { operands [ 2 ] = operands [ 3 ] ; if ( GET_MODE_CLASS ( cmp_mode ) == MODE_FLOAT ) rc = reverse_condition_maybe_unordered ( rc ) ; else rc = reverse_condition ( rc ) ; } if ( XEXP ( cmp , 1 ) == const0_rtx && GET_CODE ( XEXP ( cmp , 0 ) ) == REG && cmp_mode == DImode && v9_regcmp_p ( rc ) ) cc_reg = XEXP ( cmp , 0 ) ; else cc_reg = gen_compare_reg_1 ( rc , XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) ) ; cmp = gen_rtx_fmt_ee ( rc , GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_IF_THEN_ELSE ( mode , cmp , operands [ 2 ] , dst ) ) ) ; if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; return true ; } </s>

Emit code to conditionally move either OPERANDS [ 2 ] or OPERANDS [ 3 ] into OPERANDS [ 0 ] in MODE . OPERANDS [ 1 ] is the operator of the condition .


<s> bool isLegalBroadcastLoad ( Type * ElementTy , ElementCount NumElements ) const { if ( ! ST -> hasNEON ( ) || NumElements . isScalable ( ) ) return false ; switch ( unsigned ElementBits = ElementTy -> getScalarSizeInBits ( ) ) { case 8 : case 16 : case 32 : case 64 : { unsigned VectorBits = NumElements . getFixedValue ( ) * ElementBits ; return VectorBits >= 64 ; } } return false ; } </s>

\Returns true if the target supports broadcasting a load to a vector of type < NumElements x ElementTy > .


<s> bool AArch64ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; bool oclBiCall = false ; bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; oclBiCall = ( F ? F -> getCallingConv ( ) == CallingConv :: Intel_OCL_BI : false ) ; } if ( ghcCall ) return CSR_NoRegs_SaveList ; if ( oclBiCall ) { if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s>
bool
PPCLinuxAsmPrinter
::
doFinalization
(
Module
&
M
)
{
const
TargetData
*
TD
=
TM
.
getTargetData
(
)
;
bool
isPPC64
=
TD
->
getPointerSizeInBits
(
)
==
64
;
if
(
isPPC64
&&
!
TOC
.
empty
(
)
)
{
const
MCSectionELF
*
Section
=
OutStreamer
.
getContext
(
)
.
getELFSection
(
".toc"
,
ELF
::
SHT_PROGBITS
,
ELF
::
SHF_WRITE
|
ELF
::
SHF_ALLOC
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
Section
)
;
for
(
DenseMap
<
MCSymbol
*
,
MCSymbol
*
>
::
iterator
I
=
TOC
.
begin
(
)
,
E
=
TOC
.
end
(
)
;
I
!=
E
;
++
I
)
{
OutStreamer
.
EmitLabel
(
I
->
second
)
;
OutStreamer
.
EmitRawText
(
"\t.tc "
+
Twine
(
I
->
first
->
getName
(
)
)
+
"[TC],"
+
I
->
first
->
getName
(
)
)
;
}
}
return
AsmPrinter
::
doFinalization
(
M
)
;
}
</s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .

PowerPC
PPC
PPC
64
PPC
".toc"
"\t.tc "
"[TC],"


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
0
)
)
;
return
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static bool ix86_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { struct gcc_options func_options ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , "default" ) == 0 ) return true ; tree old_optimize = build_optimization_node ( & global_options ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; new_optimize = build_optimization_node ( & func_options ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> void Mips16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: Move32R16 ) , Mips :: SP ) . addReg ( Mips :: S0 ) ; if ( isInt < 16 > ( StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: RestoreRaF16 ) ) . addImm ( StackSize ) ; } </s>