<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == ISD :: SIGN_EXTEND ) { SDValue N0 = N -> getOperand ( 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( N0 . hasOneUse ( ) && N0 . getOpcode ( ) == ISD :: SRA ) { auto * SraAmt = dyn_cast < ConstantSDNode > ( N0 . getOperand ( 1 ) ) ; SDValue Inner = N0 . getOperand ( 0 ) ; if ( SraAmt && Inner . hasOneUse ( ) && Inner . getOpcode ( ) == ISD :: SHL ) { if ( auto * ShlAmt = dyn_cast < ConstantSDNode > ( Inner . getOperand ( 1 ) ) ) { unsigned Extra = ( VT . getSizeInBits ( ) - N0 . getValueType ( ) . getSizeInBits ( ) ) ; unsigned NewShlAmt = ShlAmt -> getZExtValue ( ) + Extra ; unsigned NewSraAmt = SraAmt -> getZExtValue ( ) + Extra ; EVT ShiftVT = N0 . getOperand ( 1 ) . getValueType ( ) ; SDValue Ext = DAG . getNode ( ISD :: ANY_EXTEND , SDLoc ( Inner ) , VT , Inner . getOperand ( 0 ) ) ; SDValue Shl = DAG . getNode ( ISD :: SHL , SDLoc ( Inner ) , VT , Ext , DAG . getConstant ( NewShlAmt , ShiftVT ) ) ; return DAG . getNode ( ISD :: SRA , SDLoc ( N0 ) , VT , Shl , DAG . getConstant ( NewSraAmt , ShiftVT ) ) ; } } } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: TailCall : return "MipsISD::TailCall" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: EH_RETURN : return "MipsISD::EH_RETURN" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: TruncIntFP : return "MipsISD::TruncIntFP" ; case MipsISD :: ExtractLOHI : return "MipsISD::ExtractLOHI" ; case MipsISD :: InsertLOHI : return "MipsISD::InsertLOHI" ; case MipsISD :: Mult : return "MipsISD::Mult" ; case MipsISD :: Multu : return "MipsISD::Multu" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: DivRem16 : return "MipsISD::DivRem16" ; case MipsISD :: DivRemU16 : return "MipsISD::DivRemU16" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: Wrapper : return "MipsISD::Wrapper" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; case MipsISD :: LWL : return "MipsISD::LWL" ; case MipsISD :: LWR : return "MipsISD::LWR" ; case MipsISD :: SWL : return "MipsISD::SWL" ; case MipsISD :: SWR : return "MipsISD::SWR" ; case MipsISD :: LDL : return "MipsISD::LDL" ; case MipsISD :: LDR : return "MipsISD::LDR" ; case MipsISD :: SDL : return "MipsISD::SDL" ; case MipsISD :: SDR : return "MipsISD::SDR" ; case MipsISD :: EXTP : return "MipsISD::EXTP" ; case MipsISD :: EXTPDP : return "MipsISD::EXTPDP" ; case MipsISD :: EXTR_S_H : return "MipsISD::EXTR_S_H" ; case MipsISD :: EXTR_W : return "MipsISD::EXTR_W" ; case MipsISD :: EXTR_R_W : return "MipsISD::EXTR_R_W" ; case MipsISD :: EXTR_RS_W : return "MipsISD::EXTR_RS_W" ; case MipsISD :: SHILO : return "MipsISD::SHILO" ; case MipsISD :: MTHLIP : return "MipsISD::MTHLIP" ; case MipsISD :: MULT : return "MipsISD::MULT" ; case MipsISD :: MULTU : return "MipsISD::MULTU" ; case MipsISD :: MADD_DSP : return "MipsISD::MADD_DSP" ; case MipsISD :: MADDU_DSP : return "MipsISD::MADDU_DSP" ; case MipsISD :: MSUB_DSP : return "MipsISD::MSUB_DSP" ; case MipsISD :: MSUBU_DSP : return "MipsISD::MSUBU_DSP" ; case MipsISD :: SHLL_DSP : return "MipsISD::SHLL_DSP" ; case MipsISD :: SHRA_DSP : return "MipsISD::SHRA_DSP" ; case MipsISD :: SHRL_DSP : return "MipsISD::SHRL_DSP" ; case MipsISD :: SETCC_DSP : return "MipsISD::SETCC_DSP" ; case MipsISD :: SELECT_CC_DSP : return "MipsISD::SELECT_CC_DSP" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: GPR32RegClassID : case Mips :: GPR64RegClassID : case Mips :: DSPRegsRegClassID : { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 32 ; case Mips :: AFGR64RegClassID : return 16 ; case Mips :: FGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


For stack frames that ca n't be allocated with a single ADDI instruction , compute the best value to initially allocate . It must at a minimum allocate enough space to spill the callee-saved registers .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"PowerPC Branch Selector"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned AArch64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? AArch64 :: FP : AArch64 :: SP ; } </s>


<s> static void mmix_reorg ( void ) { int regno ; for ( regno = MMIX_LAST_STACK_REGISTER_REGNUM ; regno >= 0 ; regno -- ) if ( ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || ( regno == MMIX_FRAME_POINTER_REGNUM && frame_pointer_needed ) ) break ; if ( ! TARGET_ABI_GNU && regno < current_function_args_info . regs - 1 ) { regno = current_function_args_info . regs - 1 ; if ( regno > MMIX_RETURN_VALUE_REGNUM - 1 ) regno = MMIX_RETURN_VALUE_REGNUM - 1 ; } cfun -> machine -> highest_saved_stack_register = regno ; } </s>

Implement TARGET_MACHINE_DEPENDENT_REORG . No actual rearrangements done here ; just virtually by calculating the highest saved stack register number used to modify the register numbers at output time .


<s> static machine_mode rs6000_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VSX ) switch ( mode ) { case E_DFmode : return V2DFmode ; default : ; } if ( TARGET_ALTIVEC || TARGET_VSX ) switch ( mode ) { case E_SFmode : return V4SFmode ; case E_TImode : return V1TImode ; case E_DImode : return V2DImode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; default : ; } if ( TARGET_PAIRED_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode ; } </s>


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return mode ; case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return mode ; default : gcc_unreachable ( ) ; } } </s>

Return the mode that an insn results in .


"\nStack information for function %s:\n"

Print debugging information for a frame .


<s> static bool aarch64_print_ldpstp_address ( FILE * f , machine_mode mode , rtx x ) { return aarch64_print_address_internal ( f , mode , x , ADDR_QUERY_LDP_STP ) ; } </s>

Print address ' x ' of a LDP/STP with mode 'mode ' .


<s> bool Thumb1FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) || TT . isOSWindows ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool isVerboseAsm ( ) const override { return IsVerboseAsm ; } </s>

Return true if this streamer supports verbose assembly and if it is enabled .


"%<-fsplit-stack%> does not support fastcall with "

"%<-fsplit-stack%> does not support 2 register "

"%<-fsplit-stack%> does not support 3 register parameters"

Return a scratch register to use in the split stack prologue . The split stack prologue is used for -fsplit-stack . It is the first instructions in the function , even before the regular prologue . The scratch register can be any caller-saved register which is not used for parameters or for the static chain .


<s> bool SystemZInstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & SystemZ :: FP64RegClass ) loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64rm : SystemZ :: MOV64rmm ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Define ) ; MIB . addReg ( ( RegInfo -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ) ) ; MIB . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static unsigned getTOCSaveOffset ( bool isELFv2ABI ) { return isELFv2ABI ? 24 : 40 ; } </s>

getTOCSaveOffset - Return the previous frame offset to save the TOC register � ? 64-bit SVR4 ABI only .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . hasVSX ( ) ) { if ( TM . isELFv2ABI ( ) || Subtarget . isAIXABI ( ) ) { if ( Subtarget . hasP9Vector ( ) && EnableGPRToVecSpills && RC == & PPC :: G8RCRegClass ) { InflateGP8RC ++ ; return & PPC :: SPILLTOVSRRCRegClass ; } if ( RC == & PPC :: GPRCRegClass && EnableGPRToVecSpills ) InflateGPRC ++ ; } if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; else if ( RC == & PPC :: F4RCRegClass && Subtarget . hasP8Vector ( ) ) return & PPC :: VSSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::G8RCRegClass PPC::SPILLTOVSRRCRegClass PPC::GPRCRegClass PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass PPC::F4RCRegClass PPC::VSSRCRegClass


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegUnits . init ( * TRI ) ; UsedRegUnits . init ( * TRI ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { if ( ! funcInfo . MF -> getTarget ( ) . Options . EnableFastISel ) return TargetLowering :: createFastISel ( funcInfo , libInfo ) ; return Mips :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static int arm_save_coproc_regs ( void ) { int saved_size = 0 ; unsigned reg ; unsigned start_reg ; rtx insn ; for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG ( V2SImode , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; saved_size += 8 ; } if ( TARGET_HARD_FLOAT && TARGET_VFP ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += 2 ) { if ( ( ! df_regs_ever_live_p ( reg ) || call_used_regs [ reg ] ) && ( ! df_regs_ever_live_p ( reg + 1 ) || call_used_regs [ reg + 1 ] ) ) { if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; start_reg = reg + 2 ; } } if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; } return saved_size ; } </s>

Emit RTL to save coprocessor registers on function entry . Returns the number of bytes pushed .


<s> void LEGPassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool SparcTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createSparcFPMoverPass ( * this ) ) ; PM . add ( createSparcDelaySlotFillerPass ( * this ) ) ; return true ; } </s>


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static rtx mips_expand_builtin_compare ( enum mips_builtin_type builtin_type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree arglist ) { rtx label1 , label2 , if_then_else ; rtx pat , cmp_result , ops [ MAX_RECOG_OPERANDS ] ; rtx target_if_equal , target_if_unequal ; int cmp_value , i ; if ( target == 0 || GET_MODE ( target ) != SImode ) target = gen_reg_rtx ( SImode ) ; cmp_result = mips_prepare_builtin_target ( icode , 0 , 0 ) ; for ( i = 1 ; i < insn_data [ icode ] . n_operands - 1 ; i ++ ) ops [ i ] = mips_prepare_builtin_arg ( icode , i , & arglist ) ; switch ( insn_data [ icode ] . n_operands ) { case 4 : pat = GEN_FCN ( icode ) ( cmp_result , ops [ 1 ] , ops [ 2 ] , GEN_INT ( cond ) ) ; break ; case 6 : pat = GEN_FCN ( icode ) ( cmp_result , ops [ 1 ] , ops [ 2 ] , ops [ 3 ] , ops [ 4 ] , GEN_INT ( cond ) ) ; break ; default : gcc_unreachable ( ) ; } if ( builtin_type == MIPS_BUILTIN_CMP_ALL ) { cmp_value = - 1 ; target_if_equal = const1_rtx ; target_if_unequal = const0_rtx ; } else { cmp_value = 0 ; target_if_equal = const0_rtx ; target_if_unequal = const1_rtx ; if ( builtin_type == MIPS_BUILTIN_CMP_UPPER ) cmp_result = simplify_gen_subreg ( CCmode , cmp_result , CCV2mode , 4 ) ; else if ( builtin_type == MIPS_BUILTIN_CMP_LOWER ) cmp_result = simplify_gen_subreg ( CCmode , cmp_result , CCV2mode , 0 ) ; } emit_move_insn ( target , target_if_equal ) ; emit_insn ( pat ) ; label1 = gen_label_rtx ( ) ; label2 = gen_label_rtx ( ) ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( NE , GET_MODE ( cmp_result ) , cmp_result , GEN_INT ( cmp_value ) ) , gen_rtx_LABEL_REF ( VOIDmode , label1 ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_then_else ) ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_LABEL_REF ( VOIDmode , label2 ) ) ) ; emit_barrier ( ) ; emit_label ( label1 ) ; emit_move_insn ( target , target_if_unequal ) ; emit_label ( label2 ) ; return target ; } </s>

Expand a comparison builtin of type BUILTIN_TYPE . ICODE is the code of the comparison instruction and COND is the condition it should test . ARGLIST is the list of function arguments and TARGET , if nonnull , suggests a good place to put the boolean result .


<s> static unsigned long arm_compute_func_type ( void ) { unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > 0 && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && arm_except_unwind_info ( & global_options ) != UI_SJLJ ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL ; else type |= arm_isr_value ( TREE_VALUE ( a ) ) ; if ( lookup_attribute ( "cmse_nonsecure_entry" , attr ) ) type |= ARM_FT_CMSE_ENTRY ; return type ; } </s>

Computes the type of the current function .

arm 0 "naked" "isr" "interrupt" "cmse_nonsecure_entry"


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADDCARRY
:
IsSelected
=
selectAddCarry
(
N
)
;
break
;
case
ISD
::
SUBCARRY
:
IsSelected
=
selectSubCarry
(
N
)
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
{
Register
GP
=
Subtarget
->
getInstrInfo
(
)
->
getGlobalBaseReg
(
*
MF
)
;
ReplaceNode
(
N
,
CurDAG
->
getRegister
(
GP
,
N
->
getValueType
(
0
)
)
.
getNode
(
)
)
;
IsSelected
=
true
;
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
Dl
,
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
N
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
ReplaceNode
(
N
,
CurDAG
->
getMachineNode
(
Subtarget
->
hasE2
(
)
CSKY
::
ADDI32
:
CSKY
::
ADDI16XZ
,
Dl
,
MVT
::
i32
,
TFI
,
Imm
)
)
;
IsSelected
=
true
;
break
;
}
case
ISD
::
INLINEASM
:
case
ISD
::
INLINEASM_BR
:
IsSelected
=
selectInlineAsm
(
N
)
;
break
;
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


"JIT relocation model must be set to static or default!"


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static int arm_size_return_regs ( void ) { enum machine_mode mode ; if ( current_function_return_rtx != 0 ) mode = GET_MODE ( current_function_return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; return GET_MODE_SIZE ( mode ) ; } </s>

Calculate the size of the return value that is passed in registers .


<s> static rtx altivec_expand_ld_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 ; machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_load_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_load_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_vector_altivec_load_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_load_v4sf ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2df : icode = CODE_FOR_vector_altivec_load_v2df ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2di : icode = CODE_FOR_vector_altivec_load_v2di ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_load_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ 0 ] . mode ; mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> static int rs6000_tls_symbol_ref_1 ( rtx * x , void * data ATTRIBUTE_UNUSED ) { return RS6000_SYMBOL_REF_TLS_P ( * x ) ; } </s>

Return 1 if * X is a thread-local symbol . This is the same as rs6000_tls_symbol_ref except for the type of the unused argument .


<s> virtual const SparcRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool aarch64_gimple_fold_builtin ( gimple_stmt_iterator * gsi ) { bool changed = false ; gimple stmt = gsi_stmt ( * gsi ) ; tree call = gimple_call_fn ( stmt ) ; tree fndecl ; gimple new_stmt = NULL ; if ( call ) { fndecl = gimple_call_fndecl ( stmt ) ; if ( fndecl ) { int fcode = DECL_FUNCTION_CODE ( fndecl ) ; int nargs = gimple_call_num_args ( stmt ) ; tree * args = ( nargs > 0 ? gimple_call_arg_ptr ( stmt , 0 ) : & error_mark_node ) ; switch ( fcode ) { BUILTIN_VALL ( UNOP , reduc_plus_scal_ , 10 ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_PLUS_EXPR , args [ 0 ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smax_scal_ , 10 ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umax_scal_ , 10 ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MAX_EXPR , args [ 0 ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smin_scal_ , 10 ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umin_scal_ , 10 ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MIN_EXPR , args [ 0 ] ) ; break ; default : break ; } } } if ( new_stmt ) { gsi_replace ( gsi , new_stmt , true ) ; changed = true ; } return changed ; } </s>


<s> static bool rs6000_builtin_valid_without_lhs ( enum rs6000_gen_builtins fn_code , tree fndecl ) { if ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) == void_type_node ) return true ; switch ( fn_code ) { case RS6000_BIF_STVX_V16QI : case RS6000_BIF_STVX_V8HI : case RS6000_BIF_STVX_V4SI : case RS6000_BIF_STVX_V4SF : case RS6000_BIF_STVX_V2DI : case RS6000_BIF_STVX_V2DF : case RS6000_BIF_STXVW4X_V16QI : case RS6000_BIF_STXVW4X_V8HI : case RS6000_BIF_STXVW4X_V4SF : case RS6000_BIF_STXVW4X_V4SI : case RS6000_BIF_STXVD2X_V2DF : case RS6000_BIF_STXVD2X_V2DI : return true ; default : return false ; } } </s>

Helper function to sort out which built-ins may be valid without having a LHS .


<s>
bool
LanaiInstrInfo
::
analyzeSelect
(
const
MachineInstr
&
MI
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
unsigned
&
TrueOp
,
unsigned
&
FalseOp
,
bool
&
Optimizable
)
const
{
assert
(
MI
.
getOpcode
(
)
==
Lanai
::
SELECT
&&
"unknown select instruction"
)
;
TrueOp
=
1
;
FalseOp
=
2
;
Cond
.
push_back
(
MI
.
getOperand
(
3
)
)
;
Optimizable
=
true
;
return
false
;
}
</s>

Analyze the given select instruction , returning true if it can not be understood .


<s> MCObjectWriter * MipsAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createMipsELFObjectWriter ( OS , TheTriple , IsN32 ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"%qE attribute only applies to functions"

"attribute interrupt_handler is not compatible with -m5-compact"

Handle an `` interrupt_handler '' attribute ; arguments as in struct attribute_spec.handler .


"; WARNING: The following code is valid only with MASM v8.x"

"; This version of MASM is usually shipped with Microsoft "

"; or (possible) further versions. Unfortunately, there is no "

"; dllexported symbols in the earlier versions of MASM in fully "

"_drectve\t segment info alias('.drectve')\n"

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> void F2003fMCAsmStreamer :: AddComment ( const Twine & T , bool EOL ) { if ( ! IsVerboseAsm ) return ; T . toVector ( CommentToEmit ) ; if ( EOL ) CommentToEmit . push_back ( '\n' ) ; } </s>


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && SYMBOL_REF_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) != 0 ) return true ; return TARGET_ELF && tls_referenced_p ( x ) ; } </s>


<s> static bool i386_pe_dllexport_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL && TREE_CODE ( decl ) != FUNCTION_DECL ) return false ; if ( lookup_attribute ( "dllexport" , DECL_ATTRIBUTES ( decl ) ) ) return true ; if ( associated_type ( decl ) && lookup_attribute ( "dllexport" , TYPE_ATTRIBUTES ( associated_type ( decl ) ) ) ) return i386_pe_type_dllexport_p ( decl ) ; return false ; } </s>

Return true if DECL is a dllexport 'd object .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
!=
0
)
Base_Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
<<
" Scale"
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
0
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
0
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" JT"
" Align"


<s> bool X86ATTAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
TM
=
&
Func
.
getTarget
(
)
;
const
X86Subtarget
&
ST
=
TM
->
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
static_cast
<
const
X86InstrInfo
*
>
(
TM
->
getInstrInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s> void SICMCCodeEmitter :: EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const RegisterBankInfo * AArch64Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> void X86AsmInstrumentation :: EmitInstruction ( MCStreamer & Out , const MCInst & Inst ) { Out . EmitInstruction ( Inst , STI ) ; } </s>


<s> bool isValid ( ) { return isFIBase ( ) || ( isRegBase ( ) && getReg ( ) != 0 ) ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> bool X86DAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { if ( OptLevel == CodeGenOpt :: None ) return false ; if ( ! N . hasOneUse ( ) ) return false ; if ( N . getOpcode ( ) != ISD :: LOAD ) return true ; if ( U == Root ) { switch ( U -> getOpcode ( ) ) { default : break ; case X86ISD :: ADD : case X86ISD :: SUB : case X86ISD :: AND : case X86ISD :: XOR : case X86ISD :: OR : case ISD :: ADD : case ISD :: ADDCARRY : case ISD :: AND : case ISD :: OR : case ISD :: XOR : { SDValue Op1 = U -> getOperand ( 1 ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( Imm -> getAPIntValue ( ) . isSignedIntN ( 8 ) ) return false ; if ( Op1 . getOpcode ( ) == X86ISD :: Wrapper ) { SDValue Val = Op1 . getOperand ( 0 ) ; if ( Val . getOpcode ( ) == ISD :: TargetGlobalTLSAddress ) return false ; } } } } return true ; } </s>

IsProfitableToFold - Returns true if it 's profitable to fold the specific operand node N of U during instruction selection that starts at Root .


<s> static void mips_init_libfuncs ( void ) { if ( TARGET_FIX_VR4120 ) { set_optab_libfunc ( sdiv_optab , SImode , "__vr4120_divsi3" ) ; set_optab_libfunc ( smod_optab , SImode , "__vr4120_modsi3" ) ; } if ( TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI ) { set_optab_libfunc ( add_optab , SFmode , "__mips16_addsf3" ) ; set_optab_libfunc ( sub_optab , SFmode , "__mips16_subsf3" ) ; set_optab_libfunc ( smul_optab , SFmode , "__mips16_mulsf3" ) ; set_optab_libfunc ( sdiv_optab , SFmode , "__mips16_divsf3" ) ; set_optab_libfunc ( eq_optab , SFmode , "__mips16_eqsf2" ) ; set_optab_libfunc ( ne_optab , SFmode , "__mips16_nesf2" ) ; set_optab_libfunc ( gt_optab , SFmode , "__mips16_gtsf2" ) ; set_optab_libfunc ( ge_optab , SFmode , "__mips16_gesf2" ) ; set_optab_libfunc ( lt_optab , SFmode , "__mips16_ltsf2" ) ; set_optab_libfunc ( le_optab , SFmode , "__mips16_lesf2" ) ; set_optab_libfunc ( unord_optab , SFmode , "__mips16_unordsf2" ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , "__mips16_fix_truncsfsi" ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , "__mips16_floatsisf" ) ; set_conv_libfunc ( ufloat_optab , SFmode , SImode , "__mips16_floatunsisf" ) ; if ( TARGET_DOUBLE_FLOAT ) { set_optab_libfunc ( add_optab , DFmode , "__mips16_adddf3" ) ; set_optab_libfunc ( sub_optab , DFmode , "__mips16_subdf3" ) ; set_optab_libfunc ( smul_optab , DFmode , "__mips16_muldf3" ) ; set_optab_libfunc ( sdiv_optab , DFmode , "__mips16_divdf3" ) ; set_optab_libfunc ( eq_optab , DFmode , "__mips16_eqdf2" ) ; set_optab_libfunc ( ne_optab , DFmode , "__mips16_nedf2" ) ; set_optab_libfunc ( gt_optab , DFmode , "__mips16_gtdf2" ) ; set_optab_libfunc ( ge_optab , DFmode , "__mips16_gedf2" ) ; set_optab_libfunc ( lt_optab , DFmode , "__mips16_ltdf2" ) ; set_optab_libfunc ( le_optab , DFmode , "__mips16_ledf2" ) ; set_optab_libfunc ( unord_optab , DFmode , "__mips16_unorddf2" ) ; set_conv_libfunc ( sext_optab , DFmode , SFmode , "__mips16_extendsfdf2" ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , "__mips16_truncdfsf2" ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , "__mips16_fix_truncdfsi" ) ; set_conv_libfunc ( sfloat_optab , DFmode , SImode , "__mips16_floatsidf" ) ; set_conv_libfunc ( ufloat_optab , DFmode , SImode , "__mips16_floatunsidf" ) ; } } if ( TARGET_MIPS16 ) { synchronize_libfunc = init_one_libfunc ( "__sync_synchronize" ) ; init_sync_libfuncs ( UNITS_PER_WORD ) ; } } </s>


<s> static bool rs6000_scalar_mode_supported_p ( scalar_mode mode ) { if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( TARGET_FLOAT128_TYPE && ( mode == KFmode || mode == IFmode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( * Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; return Modified ; } </s>


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintID ) { case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : default : return true ; case InlineAsm :: Constraint_m : if ( ! SelectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || mode == TFmode || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; FrameReg = ( RegInfo -> needsStackRealignment ( MF ) ) ? RegInfo -> getStackRegister ( ) : RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static rtx aarch64_gen_store_pair ( machine_mode mode , rtx mem1 , rtx reg1 , rtx mem2 , rtx reg2 ) { switch ( mode ) { case DImode : return gen_store_pairdi ( mem1 , reg1 , mem2 , reg2 ) ; case DFmode : return gen_store_pairdf ( mem1 , reg1 , mem2 , reg2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return a store pair instruction of mode MODE to store register REG1 to MEM1 and register REG2 to MEM2 .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static void indirect_thunk_name ( char name [ 32 ] , unsigned int regno , enum indirect_thunk_prefix need_prefix , bool ret_p ) { if ( regno != INVALID_REGNUM && regno != CX_REG && ret_p ) gcc_unreachable ( ) ; if ( USE_HIDDEN_LINKONCE ) { const char * prefix ; if ( need_prefix == indirect_thunk_prefix_bnd ) prefix = "_bnd" ; else if ( need_prefix == indirect_thunk_prefix_nt && regno != INVALID_REGNUM ) { prefix = "_nt" ; } else prefix = "" ; const char * ret = ret_p ? "return" : "indirect" ; if ( regno != INVALID_REGNUM ) { const char * reg_prefix ; if ( LEGACY_INT_REGNO_P ( regno ) ) reg_prefix = TARGET_64BIT ? "r" : "e" ; else reg_prefix = "" ; sprintf ( name , "__x86_%s_thunk%s_%s%s" , ret , prefix , reg_prefix , reg_names [ regno ] ) ; } else sprintf ( name , "__x86_%s_thunk%s" , ret , prefix ) ; } else { if ( regno != INVALID_REGNUM ) { if ( need_prefix == indirect_thunk_prefix_bnd ) ASM_GENERATE_INTERNAL_LABEL ( name , "LITBR" , regno ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LITR" , regno ) ; } else { if ( ret_p ) { if ( need_prefix == indirect_thunk_prefix_bnd ) ASM_GENERATE_INTERNAL_LABEL ( name , "LRTB" , 0 ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LRT" , 0 ) ; } else { if ( need_prefix == indirect_thunk_prefix_bnd ) ASM_GENERATE_INTERNAL_LABEL ( name , "LITB" , 0 ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LIT" , 0 ) ; } } } } </s>

Fills in the label name that should be used for the indirect thunk .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


<s> virtual SMLoc getStartLoc ( ) const LLVM_OVERRIDE { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> const unsigned * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { SystemZ :: R6D , SystemZ :: R7D , SystemZ :: R8D , SystemZ :: R9D , SystemZ :: R10D , SystemZ :: R11D , SystemZ :: R12D , SystemZ :: R13D , SystemZ :: R14D , SystemZ :: R15D , SystemZ :: F8L , SystemZ :: F9L , SystemZ :: F10L , SystemZ :: F11L , SystemZ :: F12L , SystemZ :: F13L , SystemZ :: F14L , SystemZ :: F15L , 0 } ; return CalleeSavedRegs ; } </s>


"block as it would convert a WLS from forward to a "

Checks if loop has a backwards branching WLS , and if possible , fixes it .


<s> void Cpu0SEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Cpu0MachineFunctionInfo * Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; const Cpu0SEInstrInfo & TII = * static_cast < const Cpu0SEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const Cpu0RegisterInfo & RegInfo = * static_cast < const Cpu0RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; Cpu0ABIInfo ABI = STI . getABI ( ) ; unsigned SP = Cpu0 :: SP ; unsigned FP = Cpu0 :: FP ; unsigned ZERO = Cpu0 :: ZERO ; unsigned ADDu = Cpu0 :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( Cpu0FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = & Cpu0 :: GPROutRegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < ABI . EhDataRegSize ( ) ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , Cpu0FI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) || ! STI . needsSwapsForVSXMemOps ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ; Changed = removeSwaps ( ) ; } delete EC ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Subtarget . isSVR4ABI ( ) && PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { if ( Subtarget . isPPC64 ( ) ) FrameIdx = 0 ; else { const PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; FrameIdx = FI -> getCRSpillFrameIndex ( ) ; } return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> char * iq2000_output_conditional_branch ( rtx_insn * insn , rtx * operands , int two_operands_p , int float_p , int inverted_p , int length ) { static char buffer [ 200 ] ; enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; int need_z_p ; const char * op1 = "%z2" ; const char * op2 = ( two_operands_p ? ",%z3" : ",%." ) ; const char * comp = ( float_p ? "%F0" : "%C0" ) ; const char * inverted_comp = ( float_p ? "%W0" : "%N0" ) ; iq2000_branch_likely = ( final_sequence && INSN_ANNULLED_BRANCH_P ( insn ) ) ; if ( ! two_operands_p ) { switch ( code ) { case GTU : code = NE ; break ; case LEU : code = EQ ; break ; case GEU : code = EQ ; op1 = "%." ; break ; case LTU : code = NE ; op1 = "%." ; break ; default : break ; } } need_z_p = ( ! float_p && code != EQ && code != NE ) ; if ( need_z_p ) op2 = "" ; buffer [ 0 ] = '\0' ; switch ( length ) { case 4 : case 8 : if ( float_p ) sprintf ( buffer , "b%s%%?\t%%Z2%%1" , inverted_p ? inverted_comp : comp ) ; else sprintf ( buffer , "b%s%s%%?\t%s%s,%%1" , inverted_p ? inverted_comp : comp , need_z_p ? "z" : "" , op1 , op2 ) ; return buffer ; case 12 : case 16 : { const char * target = ( ( iq2000_branch_likely || length == 16 ) ? ".+16" : ".+12" ) ; char * c ; c = strchr ( buffer , '\0' ) ; if ( float_p ) sprintf ( c , "b%s\t%%Z2%s" , inverted_p ? comp : inverted_comp , target ) ; else sprintf ( c , "b%s%s\t%s%s,%s" , inverted_p ? comp : inverted_comp , need_z_p ? "z" : "" , op1 , op2 , target ) ; strcat ( c , "\n\tnop\n\tj\t%1" ) ; if ( length == 16 ) strcat ( buffer , "\n\tnop" ) ; return buffer ; } default : gcc_unreachable ( ) ; } return 0 ; } </s>

Output assembly instructions to perform a conditional branch . INSN is the branch instruction . OPERANDS [ 0 ] is the condition . OPERANDS [ 1 ] is the target of the branch . OPERANDS [ 2 ] is the target of the first operand to the condition . If TWO_OPERANDS_P is nonzero the comparison takes two operands ; OPERANDS [ 3 ] will be the second operand . If INVERTED_P is nonzero we are to branch if the condition does not hold . If FLOAT_P is nonzero this is a floating-point comparison . LENGTH is the length ( in bytes ) of the sequence we are to generate . That tells us whether to generate a simple conditional branch , or a reversed conditional branch around a ` jr ' instruction .


<s> static rtx mips_force_address ( rtx x , machine_mode mode ) { if ( ! mips_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x ; } </s>

If X is not a valid address for mode MODE , force it into a register .


<s> Value * PPCTargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget . isAIXABI ( ) ) return M . getGlobalVariable ( AIXSSPCanaryWordName ) ; return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0


<s> bool AArch64TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_AArch64_WebKit_JS : RetCC_AArch64_AAPCS ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> TargetLoweringBase :: AtomicRMWExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= 128 ? AtomicRMWExpansionKind :: LLSC : AtomicRMWExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static int ia32_multipass_dfa_lookahead ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_K6 : return 1 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : return 4 ; case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_INTEL : if ( reload_completed ) return ix86_issue_rate ( ) ; return 0 ; default : return 0 ; } } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler .


<s> int getIntImmCostInst ( unsigned Opc , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst = nullptr ) { return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> int rs6000_trampoline_size ( void ) { int ret = 0 ; switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? 12 : 24 ; break ; case ABI_ELFv2 : gcc_assert ( ! TARGET_32BIT ) ; ret = 32 ; break ; case ABI_DARWIN : case ABI_V4 : ret = ( TARGET_32BIT ) ? 40 : 48 ; break ; } return ret ; } </s>

Length in units of the trampoline for entering a nested function .


<s> bool divmod_p ( rtx_insn * insn ) { gcc_assert ( get_attr_type ( insn ) == TYPE_DIV ) ; if ( INSN_CODE ( insn ) == CODE_FOR_divmodsi4 || INSN_CODE ( insn ) == CODE_FOR_udivmodsi4 ) return true ; return false ; } </s>

Check if the DIV insn needs two write ports .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> static void emit_load_locked ( enum machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; if ( mode == SImode ) fn = gen_load_locked_si ; else if ( mode == DImode ) fn = gen_load_locked_di ; emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s> static HOST_WIDE_INT rs6000_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return 0 ; return RS6000_STARTING_FRAME_OFFSET ; } </s>


<s>
static
void
rs6000_output_savres_externs
(
FILE
*
file
)
{
rs6000_stack_t
*
info
=
rs6000_stack_info
(
)
;
if
(
TARGET_DEBUG_STACK
)
debug_stack_info
(
info
)
;
if
(
info
->
first_fp_reg_save
<
64
&&
!
TARGET_MACHO
&&
!
TARGET_ELF
)
{
char
*
name
;
int
regno
=
info
->
first_fp_reg_save
32
;
if
(
(
info
->
savres_strategy
&
SAVE_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
SAVE_NOINLINE_FPRS_SAVES_LR
)
!=
0
;
int
sel
=
SAVRES_SAVE
|
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
info
,
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
if
(
(
info
->
savres_strategy
&
REST_INLINE_FPRS
)
==
0
)
{
bool
lr
=
(
info
->
savres_strategy
&
REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
)
==
0
;
int
sel
=
SAVRES_FPR
|
(
lr
SAVRES_LR
:
0
)
;
name
=
rs6000_savres_routine_name
(
info
,
regno
,
sel
)
;
fprintf
(
file
,
"\t.extern %s\n"
,
name
)
;
}
}
}
</s>

Output .extern statements for the save/restore routines we use .


<s> unsigned getNumFixupKinds ( ) const override { return MINA32 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s>
int
ARMTTIImpl
::
getNumMemOps
(
const
IntrinsicInst
*
I
)
const
{
MemOp
MOp
;
unsigned
DstAddrSpace
=
~
0u
;
unsigned
SrcAddrSpace
=
~
0u
;
const
Function
*
F
=
I
->
getParent
(
)
->
getParent
(
)
;
if
(
const
auto
*
MC
=
dyn_cast
<
MemTransferInst
>
(
I
)
)
{
ConstantInt
*
C
=
dyn_cast
<
ConstantInt
>
(
MC
->
getLength
(
)
)
;
if
(
!
C
)
return
1
;
const
unsigned
Size
=
C
->
getValue
(
)
.
getZExtValue
(
)
;
const
Align
DstAlign
=
*
MC
->
getDestAlign
(
)
;
const
Align
SrcAlign
=
*
MC
->
getSourceAlign
(
)
;
MOp
=
MemOp
::
Copy
(
Size
,
false
,
DstAlign
,
SrcAlign
,
false
,
false
)
;
DstAddrSpace
=
MC
->
getDestAddressSpace
(
)
;
SrcAddrSpace
=
MC
->
getSourceAddressSpace
(
)
;
}
else
if
(
const
auto
*
MS
=
dyn_cast
<
MemSetInst
>
(
I
)
)
{
ConstantInt
*
C
=
dyn_cast
<
ConstantInt
>
(
MS
->
getLength
(
)
)
;
if
(
!
C
)
return
1
;
const
unsigned
Size
=
C
->
getValue
(
)
.
getZExtValue
(
)
;
const
Align
DstAlign
=
*
MS
->
getDestAlign
(
)
;
MOp
=
MemOp
::
Set
(
Size
,
false
,
DstAlign
,
false
,
false
)
;
DstAddrSpace
=
MS
->
getDestAddressSpace
(
)
;
}
else
llvm_unreachable
(
"Expected a memcpy/move or memset!"
)
;
unsigned
Limit
,
Factor
=
2
;
switch
(
I
->
getIntrinsicID
(
)
)
{
case
Intrinsic
::
memcpy
:
Limit
=
TLI
->
getMaxStoresPerMemcpy
(
F
->
hasMinSize
(
)
)
;
break
;
case
Intrinsic
::
memmove
:
Limit
=
TLI
->
getMaxStoresPerMemmove
(
F
->
hasMinSize
(
)
)
;
break
;
case
Intrinsic
::
memset
:
Limit
=
TLI
->
getMaxStoresPerMemset
(
F
->
hasMinSize
(
)
)
;
Factor
=
1
;
break
;
default
:
llvm_unreachable
(
"Expected a memcpy/move or memset!"
)
;
}
std
::
vector
<
EVT
>
MemOps
;
if
(
getTLI
(
)
->
findOptimalMemOpLowering
(
MemOps
,
Limit
,
MOp
,
DstAddrSpace
,
SrcAddrSpace
,
F
->
getAttributes
(
)
)
)
return
MemOps
.
size
(
)
*
Factor
;
return
1
;
}
</s>

Given a memcpy/memset/memmove instruction , return the number of memory operations performed , via querying findOptimalMemOpLowering .


<s> bool AArch64TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( VT1 . isVector ( ) || VT2 . isVector ( ) || ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , const X86TargetMachine & TM , MaybeAlign StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : X86GenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , PICStyle ( PICStyles :: Style :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , InstrInfo ( initializeSubtargetDependencies ( CPU , TuneCPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: Style :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: Style :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: Style :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> Fragment * MipsGOTPLT :: create ( ) { return new GOTPLTEntry ( 0 , m_SectionData ) ; } </s>


<s> const TargetRegisterClass * F2003fRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & F2003f :: RegRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s> unsigned SICMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
void
MipsCodeEmitter
::
emitInstruction
(
const
MachineInstr
&
MI
)
{
DEBUG
(
errs
(
)
<<
"JIT: "
<<
(
void
*
)
MCE
.
getCurrentPCValue
(
)
<<
":\t"
<<
MI
)
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
true
)
;
if
(
(
MI
.
getDesc
(
)
.
TSFlags
&
MipsII
::
FormMask
)
==
MipsII
::
Pseudo
)
return
;
emitWord
(
getBinaryCodeForInstr
(
MI
)
)
;
++
NumEmitted
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
false
)
;
}
</s>

Targets should implement this to emit instructions .

Mips
Mips
"JIT: "
":\t"
MipsII::FormMask
MipsII::Pseudo


<s> void xstormy16_expand_call ( rtx retval , rtx dest , rtx counter ) { rtx call , temp ; machine_mode mode ; gcc_assert ( MEM_P ( dest ) ) ; dest = XEXP ( dest , 0 ) ; if ( ! CONSTANT_P ( dest ) && ! REG_P ( dest ) ) dest = force_reg ( Pmode , dest ) ; if ( retval == NULL ) mode = VOIDmode ; else mode = GET_MODE ( retval ) ; call = gen_rtx_CALL ( mode , gen_rtx_MEM ( FUNCTION_MODE , dest ) , counter ) ; if ( retval ) call = gen_rtx_SET ( VOIDmode , retval , call ) ; if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode ) ; emit_move_insn ( temp , const0_rtx ) ; } else temp = const0_rtx ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , call , gen_rtx_USE ( VOIDmode , temp ) ) ) ; emit_call_insn ( call ) ; } </s>

Expander for the ` call ' patterns . INDEX is the index of the switch statement . LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding to the first table entry . RANGE is the number of table entries . TABLE is an ADDR_VEC that is the jump table . DEFAULT_LABEL is the address to branch to if INDEX is outside the range LOWER_BOUND to LOWER_BOUND+RANGE-1 .


<s> void VEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( isLeafProc ( MF ) ) { VEMachineFunctionInfo * MFI = MF . getInfo < VEMachineFunctionInfo > ( ) ; MFI -> setLeafProc ( true ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
const
char
*
getPassName
(
)
const
{
return
"ARM64 Conditional Compares"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
&
Mang
=
TM
.
getObjFileLowering
(
)
->
getMangler
(
)
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
Mang
)
;
}
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> static tree arm_handle_notshared_attribute ( tree * node , tree name ATTRIBUTE_UNUSED , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { tree decl = TYPE_NAME ( * node ) ; if ( decl ) { DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ; DECL_VISIBILITY_SPECIFIED ( decl ) = 1 ; * no_add_attrs = false ; } return NULL_TREE ; } </s>

Handle the `` notshared '' attribute . This attribute is another way of requesting hidden visibility . ARM 's compiler supports `` __declspec ( notshared ) '' ; we support the same thing via an attribute .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 vzeroupper inserter"
;
}
</s>


"%qs attribute applies only to initialized variables"

Handle a `` selectany '' attribute ; arguments as in struct attribute_spec.handler .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { return new ScheduleDAGMI ( C , llvm :: make_unique < SystemZPostRASchedStrategy > ( C ) , true ) ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> unsigned AArch64TTIImpl :: getCacheLineSize ( ) { return ST -> getCacheLineSize ( ) ; } </s>

Return the target cache line size in bytes .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , * Subtarget -> getRegisterInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = 0 ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = 0 ; } if ( TARGET_64BIT && ( cum ? cum -> call_abi : ix86_abi ) == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else if ( TARGET_64BIT ) nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum -> force_bnd_pass = nregs ; if ( ! nregs ) cum -> bnds_in_bt = chkp_type_bounds_count ( type ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> bool UPTInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { bool HasCondBranch = false ; TBB = nullptr ; FBB = nullptr ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == UPT :: JMP ) { MachineBasicBlock * TargetBB = MI . getOperand ( 0 ) . getMBB ( ) ; if ( HasCondBranch ) { FBB = TargetBB ; } else { TBB = TargetBB ; } } else if ( MI . getOpcode ( ) == UPT :: Bcc ) { MachineBasicBlock * TargetBB = MI . getOperand ( 1 ) . getMBB ( ) ; TBB = TargetBB ; Cond . push_back ( MI . getOperand ( 0 ) ) ; HasCondBranch = true ; } } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool ARMBaseInstrInfo :: isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const { return Subtarget . isSwift ( ) ; } </s>

Return true if it 's profitable to unpredicate one side of a 'diamond ' , i.e .


<s>
static
bool
rename_single_chain
(
du_head_p
head
,
HARD_REG_SET
*
unavailable
)
{
int
best_new_reg
;
int
n_uses
=
0
;
struct
du_chain
*
tmp
;
int
reg
=
head
->
regno
;
enum
reg_class
super_class
=
NO_REGS
;
if
(
head
->
cannot_rename
)
return
false
;
if
(
fixed_regs
[
reg
]
||
global_regs
[
reg
]
||
(
frame_pointer_needed
&&
reg
==
HARD_FRAME_POINTER_REGNUM
)
)
return
false
;
for
(
tmp
=
head
->
first
;
tmp
;
tmp
=
tmp
->
next_use
)
{
if
(
DEBUG_INSN_P
(
tmp
->
insn
)
)
continue
;
n_uses
++
;
*
unavailable
|=
~
reg_class_contents
[
tmp
->
cl
]
;
super_class
=
reg_class_superunion
[
(
int
)
super_class
]
[
(
int
)
tmp
->
cl
]
;
}
if
(
n_uses
<
1
)
return
false
;
best_new_reg
=
find_rename_reg
(
head
,
super_class
,
unavailable
,
reg
,
false
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Register %s in insn %d"
,
reg_names
[
reg
]
,
INSN_UID
(
head
->
first
->
insn
)
)
;
if
(
head
->
call_abis
)
fprintf
(
dump_file
,
" crosses a call"
)
;
}
if
(
best_new_reg
==
reg
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"; no available better choice\n"
)
;
return
false
;
}
if
(
regrename_do_replace
(
head
,
best_new_reg
)
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
", renamed as %s\n"
,
reg_names
[
best_new_reg
]
)
;
df_set_regs_ever_live
(
best_new_reg
,
true
)
;
}
else
{
if
(
dump_file
)
fprintf
(
dump_file
,
", renaming as %s failed\n"
,
reg_names
[
best_new_reg
]
)
;
return
false
;
}
return
true
;
}
</s>

Rename the register HEAD- > regno in all the insns in the chain HEAD to any register not in the set UNAVAILABLE . Adapted from rename_chains in regrename.c .


<s> static tree aarch64_d_handle_target_float_abi ( void ) { const char * abi = "hard" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> bool WinEHStatePass :: doInitialization ( Module & M ) { TheModule = & M ; FrameEscape = Intrinsic :: getDeclaration ( TheModule , Intrinsic :: localescape ) ; FrameRecover = Intrinsic :: getDeclaration ( TheModule , Intrinsic :: localrecover ) ; FrameAddress = Intrinsic :: getDeclaration ( TheModule , Intrinsic :: frameaddress ) ; RestoreFrame = Intrinsic :: getDeclaration ( TheModule , Intrinsic :: x86_seh_restoreframe ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .

X86 Intrinsic::getDeclaration Intrinsic::localescape Intrinsic::getDeclaration Intrinsic::localrecover Intrinsic::getDeclaration Intrinsic::frameaddress Intrinsic::getDeclaration Intrinsic::x86_seh_restoreframe


<s> void aarch64_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , rtx sel , unsigned int nelt ) { machine_mode vmode = GET_MODE ( target ) ; bool one_vector_p = rtx_equal_p ( op0 , op1 ) ; rtx mask ; mask = aarch64_simd_gen_const_vector_dup ( vmode , one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; sel = expand_simple_binop ( vmode , AND , sel , mask , NULL , 0 , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) { if ( ! one_vector_p ) mask = aarch64_simd_gen_const_vector_dup ( vmode , nelt - 1 ) ; sel = expand_simple_binop ( vmode , XOR , sel , mask , NULL , 0 , OPTAB_LIB_WIDEN ) ; } aarch64_expand_vec_perm_1 ( target , op0 , op1 , sel ) ; } </s>

Expand a vec_perm with the operands given by TARGET , OP0 , OP1 and SEL . NELT is the number of elements in the vector .


<s> const uint32_t * ARMBaseRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> static bool mips_valid_offset_p ( rtx x , machine_mode mode ) { if ( ! const_arith_operand ( x , Pmode ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ) ) return false ; if ( MSA_SUPPORTED_MODE_P ( mode ) && ! mips_signed_immediate_p ( INTVAL ( x ) , 10 , mips_ldst_scaled_shift ( mode ) ) ) return false ; return true ; } </s>

Return true if , for every base register BASE_REG , ( plus BASE_REG X ) can address a value of mode MODE .


<s> bool PPCInstrInfo :: isPredicated ( const MachineInstr * MI ) const { return false ; } </s>

Returns true if the instruction is already predicated .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static inline int regno_or_subregno ( rtx op ) { if ( REG_P ( op ) ) return REGNO ( op ) ; else if ( SUBREG_P ( op ) ) return subreg_regno ( op ) ; else gcc_unreachable ( ) ; } </s>

Helper function to return the register number of a RTX .


<s> static rtx ix86_expand_unop1_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; rtx op1 , op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; op1 = op0 ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of three special unop insns : sqrtss , rsqrtss , rcpss .


<s> static void mark_reg_gr_used_mask ( rtx reg , void * data ATTRIBUTE_UNUSED ) { unsigned int regno = REGNO ( reg ) ; if ( regno < 32 ) { unsigned int i , n = hard_regno_nregs [ regno ] [ GET_MODE ( reg ) ] ; for ( i = 0 ; i < n ; ++ i ) current_frame_info . gr_used_mask |= 1 << ( regno + i ) ; } } </s>

Helper function for ia64_compute_frame_size , called through diddle_return_value . Mark REG in current_frame_info.gr_used_mask .


<s> static bool mips_insn_has_flexible_gp_ref_p ( rtx_insn * insn ) { return ( get_attr_got ( insn ) != GOT_UNSET || mips_small_data_pattern_p ( PATTERN ( insn ) ) || reg_overlap_mentioned_p ( pic_offset_table_rtx , PATTERN ( insn ) ) ) ; } </s>

Return true if INSN refers to the global pointer in a `` flexible '' way . See mips_cfun_has_flexible_gp_ref_p for details .


<s>
void
pa_asm_output_aligned_bss
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
switch_to_section
(
bss_section
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_TYPE_DIRECTIVE
(
stream
,
name
,
"object"
)
;
ASM_OUTPUT_SIZE_DIRECTIVE
(
stream
,
name
,
size
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_LABEL
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.block "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
size
)
;
}
</s>

This function places uninitialized global data in the bss section . The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this function on the SOM port to prevent uninitialized global data from being placed in the data section .

pa
"\t.align %u\n"
"object"
"\t.align %u\n"
"\t.block "
"\n"


<s> void mips_expand_atomic_qihi ( union mips_gen_fn_ptrs generator , rtx result , rtx mem , rtx oldval , rtx newval ) { rtx orig_addr , memsi_addr , memsi , shift , shiftsi , unshifted_mask ; rtx unshifted_mask_reg , mask , inverted_mask , si_op ; rtx res = NULL ; machine_mode mode ; mode = GET_MODE ( mem ) ; orig_addr = force_reg ( Pmode , XEXP ( mem , 0 ) ) ; memsi_addr = mips_force_binary ( Pmode , AND , orig_addr , force_reg ( Pmode , GEN_INT ( - 4 ) ) ) ; memsi = gen_rtx_MEM ( SImode , memsi_addr ) ; set_mem_alias_set ( memsi , ALIAS_SET_MEMORY_BARRIER ) ; MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = mips_force_binary ( Pmode , AND , orig_addr , GEN_INT ( 3 ) ) ; if ( TARGET_BIG_ENDIAN ) mips_emit_binary ( XOR , shift , shift , GEN_INT ( mode == QImode ? 3 : 2 ) ) ; mips_emit_binary ( ASHIFT , shift , shift , GEN_INT ( 3 ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = mips_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = mips_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = mips_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , newval ) ; else if ( result ) si_op = generator . fn_5 ( res , memsi , mask , inverted_mask , oldval ) ; else si_op = generator . fn_4 ( memsi , mask , inverted_mask , oldval ) ; emit_insn ( si_op ) ; if ( result ) { mips_emit_binary ( AND , res , res , mask ) ; mips_emit_binary ( LSHIFTRT , res , res , shiftsi ) ; mips_emit_move ( result , gen_lowpart ( GET_MODE ( result ) , res ) ) ; } } </s>

Expand a QI or HI mode atomic memory operation . GENERATOR contains a pointer to the gen_ * function that generates the SI mode underlying atomic operation using masks that we calculate . RESULT is the return register for the operation . Its value is NULL if unused . MEM is the location of the atomic access . OLDVAL is the first operand for the operation . NEWVAL is the optional second operand for the operation . Its value is NULL if unused .


<s> bool mergeStoresAfterLegalization ( EVT MemVT ) const override { return ! MemVT . isVector ( ) ; } </s>

Do not merge vector stores after legalization because that may conflict with x86-specific store splitting optimizations .


<s> const CallLowering * AArch64Subtarget :: getCallLowering ( ) const { if ( ! CallLoweringInfo ) CallLoweringInfo . reset ( new AArch64CallLowering ( TLInfo ) ) ; return CallLoweringInfo . get ( ) ; } </s>


<s> const MCExpr * PPC64LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_PPC_DTPREL , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> rtx ix86_rewrite_tls_address ( rtx pattern ) { pattern = copy_insn ( pattern ) ; ix86_rewrite_tls_address_1 ( & pattern ) ; return pattern ; } </s>

Rewrite instruction pattern involvning TLS address so that it refers to a default TLS address space .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createARMBlockPlacementPass ( ) ) ; addPass ( createARMOptimizeBarriersPass ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
void
mmix_asm_output_source_filename
(
FILE
*
stream
,
const
char
*
name
)
{
fprintf
(
stream
,
"# 1 "
)
;
OUTPUT_QUOTED_STRING
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
</s>


"a nested function is not supported for reduced registers"

"\t! This code fragment will be copied "

"\t! space for saving nested function address\n"


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_tlsreg"
,
0
,
0
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( DEBUG_INSN_P ( insn ) ) return AVX_U128_ANY ; if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { if ( GET_CODE ( XEXP ( link , 0 ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , 0 ) , 0 ) ; if ( ix86_check_avx_upper_register ( arg ) ) return AVX_U128_DIRTY ; } } bool avx_upper_reg_found = false ; note_stores ( insn , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; if ( avx_upper_reg_found ) return AVX_U128_DIRTY ; const function_abi & abi = insn_callee_abi ( insn ) ; if ( ! hard_reg_set_subset_p ( reg_class_contents [ SSE_REGS ] , abi . mode_clobbers ( V4DImode ) ) ) return AVX_U128_ANY ; return AVX_U128_CLEAN ; } subrtx_iterator :: array_type array ; rtx set = single_set ( insn ) ; if ( set ) { rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; if ( ix86_check_avx_upper_register ( dest ) ) { if ( standard_sse_constant_p ( src , GET_MODE ( dest ) ) != 1 ) return AVX_U128_DIRTY ; else return AVX_U128_ANY ; } else { FOR_EACH_SUBRTX ( iter , array , src , NONCONST ) if ( ix86_check_avx_upper_register ( * iter ) ) return AVX_U128_DIRTY ; } return AVX_U128_ANY ; } FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( ix86_check_avx_upper_register ( * iter ) ) return AVX_U128_DIRTY ; return AVX_U128_ANY ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> void OutgoingValueHandler :: assignValueToReg ( unsigned ValVReg , const CCValAssign & VA , const EVT & VT ) { unsigned PhysReg = VA . getLocReg ( ) ; const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; if ( VT == MVT :: f64 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? Mips :: ExtractElementF64_64 : Mips :: ExtractElementF64 ) . addDef ( PhysReg + ( STI . isLittle ( ) ? 1 : 0 ) ) . addUse ( ValVReg ) . addImm ( 1 ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? Mips :: ExtractElementF64_64 : Mips :: ExtractElementF64 ) . addDef ( PhysReg + ( STI . isLittle ( ) ? 0 : 1 ) ) . addUse ( ValVReg ) . addImm ( 0 ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else if ( VT == MVT :: f32 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildInstr ( Mips :: MFC1 ) . addDef ( PhysReg ) . addUse ( ValVReg ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else { unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> std :: unique_ptr < PBQPRAConstraint > AArch64Subtarget :: getCustomPBQPConstraints ( ) const { return llvm :: make_unique < A57PBQPConstraints > ( ) ; } </s>

Return PBQPConstraint ( s ) for the target .


<s> void MipsTargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size ( ) != 0 ) add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; } </s>

Add r30 to hard reg set if the prologue sets it up and it is not pic_offset_table_rtx .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s>
static
void
handle_special_swappables
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
switch
(
insn_entry
[
i
]
.
special_handling
)
{
default
:
gcc_unreachable
(
)
;
case
SH_CONST_VECTOR
:
{
gcc_assert
(
GET_CODE
(
body
)
==
SET
)
;
rtx
rhs
=
SET_SRC
(
body
)
;
swap_const_vector_halves
(
rhs
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Swapping constant halves in insn %d\n"
,
i
)
;
break
;
}
case
SH_SUBREG
:
adjust_subreg_index
(
body
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Adjusting subreg in insn %d\n"
,
i
)
;
break
;
case
SH_NOSWAP_LD
:
permute_load
(
insn
)
;
break
;
case
SH_NOSWAP_ST
:
permute_store
(
insn
)
;
break
;
case
SH_EXTRACT
:
adjust_extract
(
insn
)
;
break
;
case
SH_SPLAT
:
adjust_splat
(
insn
)
;
break
;
}
}
</s>

The insn described by INSN_ENTRY [ I ] can be swapped , but only with special handling . Take care of that here .

rs6000
"Swapping constant halves in insn %d\n"
"Adjusting subreg in insn %d\n"


<s> static bool expand_vec_perm_broadcast_1 ( struct expand_vec_perm_d * d ) { unsigned elt = d -> perm [ 0 ] , nelt2 = d -> nelt / 2 ; machine_mode vmode = d -> vmode ; unsigned char perm2 [ 4 ] ; rtx op0 = d -> op0 , dest ; bool ok ; switch ( vmode ) { case V4DFmode : case V8SFmode : gcc_unreachable ( ) ; case V2DFmode : case V2DImode : case V4SFmode : case V4SImode : gcc_unreachable ( ) ; case V8HImode : case V16QImode : if ( d -> testing_p ) return true ; do { rtx dest ; rtx ( * gen ) ( rtx , rtx , rtx ) = vmode == V16QImode ? gen_vec_interleave_lowv16qi : gen_vec_interleave_lowv8hi ; if ( elt >= nelt2 ) { gen = vmode == V16QImode ? gen_vec_interleave_highv16qi : gen_vec_interleave_highv8hi ; elt -= nelt2 ; } nelt2 /= 2 ; dest = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( dest , op0 , op0 ) ) ; vmode = get_mode_wider_vector ( vmode ) ; op0 = gen_lowpart ( vmode , dest ) ; } while ( vmode != V4SImode ) ; memset ( perm2 , elt , 4 ) ; dest = gen_reg_rtx ( V4SImode ) ; ok = expand_vselect ( dest , op0 , perm2 , 4 , d -> testing_p ) ; gcc_assert ( ok ) ; if ( ! d -> testing_p ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , dest ) ) ; return true ; case V64QImode : case V32QImode : case V16HImode : case V8SImode : case V4DImode : gcc_assert ( ! TARGET_AVX2 || d -> perm [ 0 ] ) ; return false ; default : gcc_unreachable ( ) ; } } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Implement broadcast permutations . We assume that expand_vec_perm_1 has already failed .


<s>
static
void
create_complex_muldiv
(
const
char
*
name
,
built_in_function
fncode
,
tree
fntype
)
{
tree
fndecl
=
add_builtin_function
(
name
,
fntype
,
fncode
,
BUILT_IN_NORMAL
,
name
,
NULL_TREE
)
;
set_builtin_decl
(
fncode
,
fndecl
,
true
)
;
if
(
TARGET_DEBUG_BUILTIN
)
fprintf
(
stderr
,
"create complex %s, fncode: %d\n"
,
name
,
(
int
)
fncode
)
;
return
;
}
</s>

Create a decl for either complex long double multiply or complex long double divide when long double is IEEE 128-bit floating point . We ca n't use __multc3 and __divtc3 because the original long double using IBM extended double used those names . The complex multiply/divide functions are encoded as builtin functions with a complex result and 4 scalar inputs .


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s> static rtx aarch64_expand_sve_const_pred_1 ( rtx target , rtx_vector_builder & builder , bool allow_recurse_p ) { if ( builder . encoded_nelts ( ) == 1 ) return aarch64_emit_set_immediate ( target , builder ) ; unsigned int elt_size = aarch64_widest_sve_pred_elt_size ( builder ) ; if ( int vl = aarch64_partial_ptrue_length ( builder , elt_size ) ) { machine_mode mode = aarch64_sve_pred_mode ( elt_size ) . require ( ) ; if ( aarch64_svpattern_for_vl ( mode , vl ) != AARCH64_NUM_SVPATTERNS ) return aarch64_emit_set_immediate ( target , builder ) ; return aarch64_sve_move_pred_via_while ( target , mode , vl ) ; } if ( ! allow_recurse_p ) return NULL_RTX ; if ( INTVAL ( builder . elt ( 0 ) ) == 0 ) if ( rtx res = aarch64_expand_sve_const_pred_eor ( target , builder , elt_size ) ) return res ; for ( unsigned int i = elt_size ; i <= 8 ; i *= 2 ) if ( rtx res = aarch64_expand_sve_const_pred_trn ( target , builder , elt_size , i ) ) return res ; return NULL_RTX ; } </s>

Subroutine of aarch64_expand_sve_const_pred . Try to load the VNx16BI constant in BUILDER into an SVE predicate register . Return the register on success , otherwise return null . Use TARGET for the register if nonnull and convenient . ALLOW_RECURSE_P is true if we can use methods that would call this function recursively .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget -> isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 ) { if ( Subtarget -> hasInt256 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasFp256 ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool LanaiInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Lanai :: SFSUB_F_RI_LO : case Lanai :: SFSUB_F_RI_HI : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = Register ( ) ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case Lanai :: SFSUB_F_RR : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool X86TTIImpl :: isLegalNTStore ( Type * DataType , llvm :: Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < 4 || DataSize > 32 || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == 32 ) return ST -> hasAVX ( ) ; else if ( DataSize == 16 ) return ST -> hasSSE1 ( ) ; return true ; } </s>

Return true if the target supports nontemporal store .


<s> static bool arm_xscale_rtx_costs ( rtx x , int code , int outer_code , int * total ) { enum machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = 8 ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = 30 ; return true ; } if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; unsigned HOST_WIDE_INT masked_const ; cost = 2 ; if ( ! const_ok ) cost += 1 ; masked_const = i & 0xffff8000 ; if ( masked_const != 0 && masked_const != 0xffff8000 ) { masked_const = i & 0xf8000000 ; if ( masked_const == 0 || masked_const == 0xf8000000 ) cost += 1 ; else cost += 2 ; } * total = cost ; return true ; } * total = 8 + ( REG_OR_SUBREG_REG ( XEXP ( x , 0 ) ) ? 0 : 4 ) + ( REG_OR_SUBREG_REG ( XEXP ( x , 1 ) ) ? 0 : 4 ) ; return true ; case COMPARE : if ( GET_CODE ( XEXP ( x , 0 ) ) == MULT ) * total = 4 + rtx_cost ( XEXP ( x , 0 ) , code ) ; else * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; default : * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; } } </s>

RTX cost for XScale CPUs . Thumb-2 is not supported on any xscale cores , so it can be ignored .


<s> rtx arm_gen_compare_reg ( rtx_code code , rtx x , rtx y , rtx scratch ) { if ( GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ) return arm_gen_dicompare_reg ( code , x , y , scratch ) ; machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( mode == CC_RSBmode ) { if ( ! scratch ) scratch = gen_rtx_SCRATCH ( SImode ) ; emit_insn ( gen_rsb_imm_compare_scratch ( scratch , GEN_INT ( ~ UINTVAL ( x ) ) , y ) ) ; } else emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


<s> int sh_can_redirect_branch ( rtx branch1 , rtx branch2 ) { if ( flag_expensive_optimizations && simplejump_p ( branch2 ) ) { rtx dest = XEXP ( SET_SRC ( single_set ( branch2 ) ) , 0 ) ; rtx insn ; int distance ; for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = PREV_INSN ( insn ) ) { if ( insn == dest ) return 1 ; else distance += get_attr_length ( insn ) ; } for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = NEXT_INSN ( insn ) ) { if ( insn == dest ) return 1 ; else distance += get_attr_length ( insn ) ; } } return 0 ; } </s>

Return true if it 's possible to redirect BRANCH1 to the destination of an unconditional jump BRANCH2 . We only want to do this if the resulting branch will have a short displacement .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .