<s> static inline tree def_builtin2 ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask ; if ( mask == 0 || ( mask & ix86_isa_flags2 ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values2 |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } return decl ; } </s>

Like def_builtin , but for additional isa2 flags .


<s> bool LanaiMemAluCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( DisableMemAluCombiner ) return false ; TII = MF . getSubtarget < LanaiSubtarget > ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MfIterator MFI = MF . begin ( ) ; MFI != MF . end ( ) ; ++ MFI ) { Modified |= combineMemAluInBasicBlock ( & * MFI ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned int rs6000_parm_start ( machine_mode mode , const_tree type , unsigned int nwords ) { unsigned int align ; align = rs6000_function_arg_boundary ( mode , type ) / PARM_BOUNDARY - 1 ; return nwords + ( - ( rs6000_parm_offset ( ) + nwords ) & align ) ; } </s>

For a function parm of MODE and TYPE , return the starting word in the parameter area . NWORDS of the parameter area are already used .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
4
*
8
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> const ARM64InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> unsigned AArch64TargetLowering :: getVaListSizeInBits ( const DataLayout & DL ) const { if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetWindows ( ) ) return getPointerTy ( DL ) . getSizeInBits ( ) ; return 3 * getPointerTy ( DL ) . getSizeInBits ( ) + 2 * 32 ; } </s>

Returns the size of the platform 's va_list object .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return ARM :: GPRRegisterClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> void rs6000_call_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { const bool direct_call_p = GET_CODE ( func_desc ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( func_desc ) ; rtx toc_reg = gen_rtx_REG ( Pmode , TOC_REGNUM ) ; rtx toc_load = NULL_RTX ; rtx toc_restore = NULL_RTX ; rtx func_addr ; rtx abi_reg = NULL_RTX ; rtx call [ 4 ] ; int n_call ; rtx insn ; if ( INTVAL ( cookie ) & CALL_LONG ) func_desc = rs6000_longcall_ref ( func_desc ) ; if ( GET_CODE ( func_desc ) != SYMBOL_REF || ( DEFAULT_ABI == ABI_AIX && ! SYMBOL_REF_FUNCTION_P ( func_desc ) ) ) { rtx stack_ptr = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx stack_toc_offset = GEN_INT ( RS6000_TOC_SAVE_SLOT ) ; rtx stack_toc_mem = gen_frame_mem ( Pmode , gen_rtx_PLUS ( Pmode , stack_ptr , stack_toc_offset ) ) ; rtx stack_toc_unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , stack_toc_offset ) , UNSPEC_TOCSLOT ) ; toc_restore = gen_rtx_SET ( toc_reg , stack_toc_unspec ) ; if ( TARGET_SAVE_TOC_INDIRECT && ! cfun -> calls_alloca ) cfun -> machine -> save_toc_in_prologue = true ; else { MEM_VOLATILE_P ( stack_toc_mem ) = 1 ; emit_move_insn ( stack_toc_mem , toc_reg ) ; } if ( DEFAULT_ABI == ABI_ELFv2 ) { func_addr = gen_rtx_REG ( Pmode , 12 ) ; emit_move_insn ( func_addr , func_desc ) ; abi_reg = func_addr ; } else { func_desc = force_reg ( Pmode , func_desc ) ; func_addr = gen_reg_rtx ( Pmode ) ; emit_move_insn ( func_addr , gen_rtx_MEM ( Pmode , func_desc ) ) ; rtx func_toc_offset = GEN_INT ( GET_MODE_SIZE ( Pmode ) ) ; rtx func_toc_mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , func_desc , func_toc_offset ) ) ; toc_load = gen_rtx_USE ( VOIDmode , func_toc_mem ) ; if ( ! direct_call_p && TARGET_POINTERS_TO_NESTED_FUNCTIONS && ! chain_already_loaded ( get_current_sequence ( ) -> next -> last ) ) { rtx sc_reg = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; rtx func_sc_offset = GEN_INT ( 2 * GET_MODE_SIZE ( Pmode ) ) ; rtx func_sc_mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , func_desc , func_sc_offset ) ) ; emit_move_insn ( sc_reg , func_sc_mem ) ; abi_reg = sc_reg ; } } } else { abi_reg = toc_reg ; func_addr = func_desc ; } call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; n_call = 1 ; if ( toc_load ) call [ n_call ++ ] = toc_load ; if ( toc_restore ) call [ n_call ++ ] = toc_restore ; call [ n_call ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( n_call , call ) ) ; insn = emit_call_insn ( insn ) ; if ( abi_reg ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , abi_reg ) ; } </s>

Expand code to perform a call under the AIX or ELFv2 ABI .


<s> void rbt_new ( struct rbt_strings * t ) { t -> rbt_nil = ( rbt_string_node * ) malloc ( sizeof ( rbt_string_node ) ) ; t -> rbt_nil -> color = RBT_BLACK ; t -> rbt_root = t -> rbt_nil ; } </s>


<s> int initial_elimination_offset ( int from , int to ) { const int regs_saved_rounding = 0 ; int save_flags = target_flags ; HARD_REG_SET live_regs_mask ; int regs_saved = calc_live_regs ( & live_regs_mask ) ; int total_auto_space = rounded_frame_size ( regs_saved ) - regs_saved_rounding ; target_flags = save_flags ; int total_saved_regs_space = regs_saved + regs_saved_rounding ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return total_saved_regs_space + total_auto_space ; if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return total_saved_regs_space + total_auto_space ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return 0 ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return rounded_frame_size ( 0 ) ; if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return rounded_frame_size ( 0 ) ; gcc_assert ( from == RETURN_ADDRESS_POINTER_REGNUM && ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ) ; return total_auto_space ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> void LEGInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned LEGInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createELFObjectWriter ( new X86ELFObjectWriter ( true , OSType , ELF :: EM_X86_64 , true ) , OS , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_cpu_attr ) { case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return 2 ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return 5 ; case CPU_POWER8 : return 7 ; case CPU_POWER9 : return 6 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


"No MachineFunctionInfo for this function!"


<s> bool PPCTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget . is64BitELFABI ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; const Function * Caller = CI -> getParent ( ) -> getParent ( ) ; auto Attr = Caller -> getFnAttribute ( "disable-tail-calls" ) ; if ( Attr . getValueAsString ( ) == "true" ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv ( ) ) ) return false ; return getTargetMachine ( ) . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , Callee ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case E_V2DFmode : case E_V2DImode : case E_V2SFmode : case E_V2SImode : return false ; case E_V4DImode : if ( ! TARGET_64BIT ) return false ; case E_V8HFmode : case E_V16HFmode : case E_V4DFmode : case E_V8SFmode : case E_V8SImode : case E_V16HImode : case E_V32QImode : case E_V4SFmode : case E_V4SImode : case E_V8HImode : case E_V4HImode : break ; case E_V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case E_V8QImode : if ( TARGET_MMX_WITH_SSE && TARGET_SSE4_1 ) break ; wmode = V4HImode ; goto widen ; case E_V4QImode : if ( TARGET_SSE4_1 ) break ; wmode = V2HImode ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( UINTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


<s> MCFragment * findAssociatedFragment ( ) const override { return nullptr ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s> static unsigned rs6000_hash_constant ( rtx k ) { enum rtx_code code = GET_CODE ( k ) ; machine_mode mode = GET_MODE ( k ) ; unsigned result = ( code << 3 ) ^ mode ; const char * format ; int flen , fidx ; format = GET_RTX_FORMAT ( code ) ; flen = strlen ( format ) ; fidx = 0 ; switch ( code ) { case LABEL_REF : return result * 1231 + ( unsigned ) INSN_UID ( XEXP ( k , 0 ) ) ; case CONST_WIDE_INT : { int i ; flen = CONST_WIDE_INT_NUNITS ( k ) ; for ( i = 0 ; i < flen ; i ++ ) result = result * 613 + CONST_WIDE_INT_ELT ( k , i ) ; return result ; } case CONST_DOUBLE : return real_hash ( CONST_DOUBLE_REAL_VALUE ( k ) ) * result ; case CODE_LABEL : fidx = 3 ; break ; default : break ; } for ( ; fidx < flen ; fidx ++ ) switch ( format [ fidx ] ) { case 's' : { unsigned i , len ; const char * str = XSTR ( k , fidx ) ; len = strlen ( str ) ; result = result * 613 + len ; for ( i = 0 ; i < len ; i ++ ) result = result * 613 + ( unsigned ) str [ i ] ; break ; } case 'u' : case 'e' : result = result * 1231 + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * 613 + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * 613 + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = 0 ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * 613 + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result ; } </s>


"type %qT with %<[[no_unique_address]]%> members "

"type %qT when C++17 is enabled changed to match "

Return TRUE if an argument , whose type is described by TYPE and MODE , shall be passed or returned in simd/fp register ( s ) ( providing these parameter passing registers are available ) . Upon successful return , * COUNT returns the number of needed registers , * BASE_MODE returns the mode of the individual register and when IS_HAF is not NULL , * IS_HA indicates whether or not the argument is a homogeneous floating-point aggregate or a homogeneous short-vector aggregate .


<s> static bool glibc_supports_ieee_128bit ( void ) { if ( OPTION_GLIBC && ! BYTES_BIG_ENDIAN && ( ( TARGET_GLIBC_MAJOR * 1000 ) + TARGET_GLIBC_MINOR ) >= 2032 ) return true ; return false ; } </s>

Return true if we are using GLIBC , and it supports IEEE 128-bit long double . This support is only in little endian GLIBC 2.32 or newer .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: SPERCRegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F4RCRegClassID : case PPC :: F8RCRegClassID : case PPC :: VSLRCRegClassID : return 32 - DefaultSafety ; case PPC :: VFRCRegClassID : case PPC :: VRRCRegClassID : { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! TM . getAIXExtendedAltivecABI ( ) && Subtarget . isAIXABI ( ) ) return 20 - DefaultSafety ; } return 32 - DefaultSafety ; case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : case PPC :: VSRCRegClassID : { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! TM . getAIXExtendedAltivecABI ( ) && Subtarget . isAIXABI ( ) ) return 52 - DefaultSafety ; } return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
uint32_t
AArch64MCCodeEmitter
::
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected ADR target type!"
)
;
MCFixupKind
Kind
=
MI
.
getOpcode
(
)
==
AArch64
::
BL
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_call26
)
:
MCFixupKind
(
AArch64
::
fixup_aarch64_pcrel_branch26
)
;
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
MO
.
getExpr
(
)
,
Kind
,
MI
.
getLoc
(
)
)
)
;
++
MCNumFixups
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < MipsSubtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= expandMBB ( MBB ) ; if ( Modified ) MF . RenumberBlocks ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned char X86Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return X86II :: MO_NO_FLAG ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: X86_RegCall == F -> getCallingConv ( ) ) ) return X86II :: MO_GOTPCREL ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) && is64Bit ( ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_PLT ; } if ( is64Bit ( ) ) { if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_NO_FLAG ; } return X86II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


More limited version of SimplifyDemandedBits that can be used to `` look through '' ops that do n't contribute to the DemandedBits/DemandedElts - bitwise ops etc .


<s> rtx aarch64_endian_lane_rtx ( machine_mode mode , unsigned int n ) { return gen_int_mode ( ENDIAN_LANE_N ( GET_MODE_NUNITS ( mode ) , n ) , SImode ) ; } </s>

Peform endian correction on lane number N , which indexes a vector of mode MODE , and return the result as an SImode rtx .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Cpu0 Emit GP Restore"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86FastISel :: isTypeLegal ( Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( DL , Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f64 && ! Subtarget -> hasSSE2 ( ) ) return false ; if ( VT == MVT :: f32 && ! Subtarget -> hasSSE1 ( ) ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . hasStandardEncoding ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; if ( getMipsSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createMipsNaClRewritePass ( ) ) ; } return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> static void avoid_func_arg_motion ( rtx_insn * first_arg , rtx_insn * insn ) { rtx set ; rtx tmp ; set = single_set ( insn ) ; if ( ! set ) return ; tmp = SET_DEST ( set ) ; if ( REG_P ( tmp ) ) { add_dependence ( first_arg , insn , REG_DEP_OUTPUT ) ; return ; } add_dependence ( first_arg , insn , REG_DEP_ANTI ) ; } </s>

Add output or anti dependency from insn to first_arg to restrict its code motion .


<s>
static
void
rs6000_xcoff_output_toc_section_asm_op
(
const
void
*
data
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_MINIMAL_TOC
)
{
if
(
!
toc_initialized
)
{
fputs
(
"\t.toc\nLCTOC..1:\n"
,
asm_out_file
)
;
fputs
(
"\t.tc toc_table[TC],toc_table[RW]\n"
,
asm_out_file
)
;
toc_initialized
=
1
;
}
fprintf
(
asm_out_file
,
"\t.csect toc_table[RW]%s\n"
,
(
TARGET_32BIT
""
:
",3"
)
)
;
}
else
fputs
(
"\t.toc\n"
,
asm_out_file
)
;
}
</s>

A get_unnamed_section callback , used for switching to toc_section .


<s>
void
MipsCodeEmitter
::
emitInstruction
(
MachineBasicBlock
::
instr_iterator
MI
,
MachineBasicBlock
&
MBB
)
{
DEBUG
(
errs
(
)
<<
"JIT: "
<<
(
void
*
)
MCE
.
getCurrentPCValue
(
)
<<
":\t"
<<
*
MI
)
;
if
(
(
(
MI
->
getDesc
(
)
.
TSFlags
&
MipsII
::
FormMask
)
==
MipsII
::
Pseudo
)
&&
!
expandPseudos
(
MI
,
MBB
)
)
return
;
MCE
.
processDebugLoc
(
MI
->
getDebugLoc
(
)
,
true
)
;
emitWord
(
getBinaryCodeForInstr
(
*
MI
)
)
;
++
NumEmitted
;
MCE
.
processDebugLoc
(
MI
->
getDebugLoc
(
)
,
false
)
;
}
</s>

Targets should implement this to emit instructions .

Mips
Mips
"JIT: "
":\t"
MipsII::FormMask
MipsII::Pseudo


<s> void EmitRaw ( const SmallVectorImpl < uint8_t > & Opcodes ) { Ops . insert ( Ops . end ( ) , Opcodes . begin ( ) , Opcodes . end ( ) ) ; OpBegins . push_back ( OpBegins . back ( ) + Opcodes . size ( ) ) ; } </s>


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static poly_uint16 aarch64_convert_sve_vector_bits ( aarch64_sve_vector_bits_enum value ) { if ( value == SVE_SCALABLE || ( value == SVE_128 && BYTES_BIG_ENDIAN ) ) return poly_uint16 ( 2 , 2 ) ; else return ( int ) value / 64 ; } </s>

Return the VG value associated with -msve-vector-bits= value VALUE .


<s> unsigned int mips_hard_regno_nregs ( int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


<s> bool MipsTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Mips ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


"SelectInlineAsmMemoryOperand not implemented yet!\n"

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool enableMachineSchedDefaultSched ( ) const override { return true ; } </s>

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler .


<s> virtual bool isUnconditionalBranch ( const MCInst & Inst ) const { if ( Inst . getOpcode ( ) == ARM :: Bcc && Inst . getOperand ( 1 ) . getImm ( ) == ARMCC :: AL ) return true ; return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 FP Stackifier"
;
}
</s>


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI -> getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI -> getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static inline int shiftcosts ( rtx x ) { int value ; if ( TARGET_SHMEDIA ) return 1 ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) == 1 ) return 2 ; return - 1 ; } if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return SH_DYNAMIC_SHIFT_COST ; value = INTVAL ( XEXP ( x , 1 ) ) & 31 ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > 1 + SH_DYNAMIC_SHIFT_COST ) cost = 1 + SH_DYNAMIC_SHIFT_COST ; return cost ; } else return ashl_lshr_seq [ value ] . insn_count ; } </s>


<s> static unsigned int aarch64_hard_regno_nregs ( unsigned regno , machine_mode mode ) { HOST_WIDE_INT lowest_size = constant_lower_bound ( GET_MODE_SIZE ( mode ) ) ; switch ( aarch64_regno_regclass ( regno ) ) { case FP_REGS : case FP_LO_REGS : if ( aarch64_sve_data_mode_p ( mode ) ) return exact_div ( GET_MODE_SIZE ( mode ) , BYTES_PER_SVE_VECTOR ) . to_constant ( ) ; return CEIL ( lowest_size , UNITS_PER_VREG ) ; case PR_REGS : case PR_LO_REGS : case PR_HI_REGS : return 1 ; default : return CEIL ( lowest_size , UNITS_PER_WORD ) ; } gcc_unreachable ( ) ; } </s>


<s>
bool
ARMBaseInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
nullptr
;
FBB
=
nullptr
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugValue
(
)
||
!
I
->
isTerminator
(
)
)
{
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
if
(
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
!
isPredicated
(
*
I
)
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isIndirectBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpTableBranchOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
return
true
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> void SparcRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> struct xstormy16_stack_layout xstormy16_compute_stack_layout ( void ) { struct xstormy16_stack_layout layout ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; layout . locals_size = get_frame_size ( ) ; layout . register_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) layout . register_save_size += UNITS_PER_WORD ; if ( cfun -> stdarg ) layout . stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ; else layout . stdarg_save_size = 0 ; layout . frame_size = ( layout . locals_size + layout . register_save_size + layout . stdarg_save_size ) ; if ( crtl -> args . size <= 2048 && crtl -> args . size != - 1 ) { if ( layout . frame_size - INCOMING_FRAME_SP_OFFSET + crtl -> args . size <= 2048 ) layout . fp_minus_ap = layout . frame_size - INCOMING_FRAME_SP_OFFSET ; else layout . fp_minus_ap = 2048 - crtl -> args . size ; } else layout . fp_minus_ap = ( layout . stdarg_save_size + layout . register_save_size - INCOMING_FRAME_SP_OFFSET ) ; layout . sp_minus_fp = ( layout . frame_size - INCOMING_FRAME_SP_OFFSET - layout . fp_minus_ap ) ; layout . first_local_minus_ap = layout . sp_minus_fp - layout . locals_size ; return layout ; } </s>


<s> unsigned getMaxSupportedInterleaveFactor ( ) const override { return 6 ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s> static void build_sv_offset ( function_builder & b , const char * signature , const function_group_info & group ) { build_32_64 ( b , signature , group , MODE_s32offset , MODE_s64offset ) ; build_32_64 ( b , signature , group , MODE_u32offset , MODE_u64offset ) ; } </s>

Like build_sv_index , but taking vector byte offsets instead of vector array indices .


<s> static rtx extract_sfunc_addr ( rtx insn ) { rtx pattern , part = NULL_RTX ; int len , i ; pattern = PATTERN ( insn ) ; len = XVECLEN ( pattern , 0 ) ; for ( i = 0 ; i < len ; i ++ ) { part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == Pmode && GENERAL_REGISTER_P ( true_regnum ( XEXP ( part , 0 ) ) ) ) return XEXP ( part , 0 ) ; } gcc_assert ( GET_CODE ( XVECEXP ( pattern , 0 , 0 ) ) == UNSPEC_VOLATILE ) ; return XVECEXP ( XVECEXP ( pattern , 0 , 0 ) , 0 , 1 ) ; } </s>

INSN is an sfunc ; return the rtx that describes the address used .


<s> bool SystemZMCAsmInfo :: isAcceptableChar ( char C ) const { if ( AssemblerDialect == AD_ATT ) return MCAsmInfo :: isAcceptableChar ( C ) ; return MCAsmInfo :: isAcceptableChar ( C ) || C == '#' ; } </s>

Return true if C is an acceptable character inside a symbol name .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AArch64 Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static enum ivms_arg_type ia64_arg_type ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return FS ; case E_DFmode : return FT ; default : return I64 ; } } </s>

Return ivms_arg_type based on machine_mode .


<s> int neon_immediate_valid_for_logic ( rtx op , machine_mode mode , int inverse , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = neon_valid_immediate ( op , mode , inverse , & tmpconst , & tmpwidth ) ; if ( retval < 0 || retval > 5 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use in a VORR or VBIC instruction . If the immediate is valid , write a constant suitable for using as an operand to VORR/VBIC/VAND/VORN to * MODCONST and the corresponding element width to * ELEMENTWIDTH . See neon_valid_immediate for description of INVERSE .


<s> bool isImm ( ) const { return Kind == CV_Immediate ; } </s>


<s> void SystemZHazardRecognizer :: copyState ( SystemZHazardRecognizer * Incoming ) { CurrGroupSize = Incoming -> CurrGroupSize ; DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming -> LastFPdOpCycleIdx ; GrpCount = Incoming -> GrpCount ; } </s>

Copy counters from end of single predecessor .


"********** AArch64 Conditional Compares **********\n"

runOnMachineFunction - Emit the function body .


<s>
SDValue
SystemZTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

SystemZ
SystemZ
ISD::InputArg
"Unsupported calling convention"


<s> void xstormy16_expand_arith ( enum machine_mode mode , enum rtx_code code , rtx dest , rtx src0 , rtx src1 , rtx carry ) { int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; int firstloop = 1 ; if ( code == NEG ) emit_move_insn ( src0 , const0_rtx ) ; for ( i = 0 ; i < num_words ; i ++ ) { rtx w_src0 , w_src1 , w_dest ; rtx insn ; w_src0 = simplify_gen_subreg ( word_mode , src0 , mode , i * UNITS_PER_WORD ) ; w_src1 = simplify_gen_subreg ( word_mode , src1 , mode , i * UNITS_PER_WORD ) ; w_dest = simplify_gen_subreg ( word_mode , dest , mode , i * UNITS_PER_WORD ) ; switch ( code ) { case PLUS : if ( firstloop && GET_CODE ( w_src1 ) == CONST_INT && INTVAL ( w_src1 ) == 0 ) continue ; if ( firstloop ) insn = gen_addchi4 ( w_dest , w_src0 , w_src1 , carry ) ; else insn = gen_addchi5 ( w_dest , w_src0 , w_src1 , carry , carry ) ; break ; case NEG : case MINUS : case COMPARE : if ( code == COMPARE && i == num_words - 1 ) { rtx branch , sub , clobber , sub_1 ; sub_1 = gen_rtx_MINUS ( HImode , w_src0 , gen_rtx_ZERO_EXTEND ( HImode , carry ) ) ; sub = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_MINUS ( HImode , sub_1 , w_src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , carry ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( HImode , sub_1 , w_src1 ) , pc_rtx , pc_rtx ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 3 , branch , sub , clobber ) ) ; } else if ( firstloop && code != COMPARE && GET_CODE ( w_src1 ) == CONST_INT && INTVAL ( w_src1 ) == 0 ) continue ; else if ( firstloop ) insn = gen_subchi4 ( w_dest , w_src0 , w_src1 , carry ) ; else insn = gen_subchi5 ( w_dest , w_src0 , w_src1 , carry , carry ) ; break ; case IOR : case XOR : case AND : if ( GET_CODE ( w_src1 ) == CONST_INT && INTVAL ( w_src1 ) == - ( code == AND ) ) continue ; insn = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_fmt_ee ( code , mode , w_src0 , w_src1 ) ) ; break ; case NOT : insn = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_NOT ( mode , w_src0 ) ) ; break ; default : gcc_unreachable ( ) ; } firstloop = 0 ; emit ( insn ) ; } if ( firstloop ) emit ( gen_nop ( ) ) ; } </s>

Expander for arithmetic operations ; emit insns to compute ( set DEST ( CODE : MODE SRC0 SRC1 ) ) using CARRY as a temporary . When CODE is COMPARE , a branch template is generated ( this saves duplicating code in xstormy16_split_cbranch ) .


<s> bool DCPU16FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( DCPU16 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool ARMExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const ARMBaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; STI = & MF . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
scalar_chain
::
add_insn
(
bitmap
candidates
,
unsigned
int
insn_uid
)
{
if
(
bitmap_bit_p
(
insns
,
insn_uid
)
)
return
;
if
(
dump_file
)
fprintf
(
dump_file
,
"  Adding insn %d to chain #%d\n"
,
insn_uid
,
chain_id
)
;
bitmap_set_bit
(
insns
,
insn_uid
)
;
rtx_insn
*
insn
=
DF_INSN_UID_GET
(
insn_uid
)
->
insn
;
rtx
def_set
=
single_set
(
insn
)
;
if
(
def_set
&&
REG_P
(
SET_DEST
(
def_set
)
)
&&
!
HARD_REGISTER_P
(
SET_DEST
(
def_set
)
)
)
bitmap_set_bit
(
defs
,
REGNO
(
SET_DEST
(
def_set
)
)
)
;
df_ref
ref
;
for
(
ref
=
DF_INSN_UID_DEFS
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
HARD_REGISTER_P
(
DF_REF_REG
(
ref
)
)
)
analyze_register_chain
(
candidates
,
ref
)
;
for
(
ref
=
DF_INSN_UID_USES
(
insn_uid
)
;
ref
;
ref
=
DF_REF_NEXT_LOC
(
ref
)
)
if
(
!
DF_REF_REG_MEM_P
(
ref
)
)
analyze_register_chain
(
candidates
,
ref
)
;
}
</s>

Add instruction into a chain . Return true if OK , false if the search was aborted .


<s> const TargetRegisterClass * X86RegisterInfo :: getPointerRegClass ( ) const { const X86Subtarget * Subtarget = & TM . getSubtarget < X86Subtarget > ( ) ; if ( Subtarget -> is64Bit ( ) ) return & X86 :: GR64RegClass ; else return & X86 :: GR32RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static bool aarch64_extr_rtx_p ( rtx x , rtx * res_op0 , rtx * res_op1 ) { rtx op0 , op1 ; scalar_int_mode mode ; if ( ! is_a < scalar_int_mode > ( GET_MODE ( x ) , & mode ) ) return false ; * res_op0 = NULL_RTX ; * res_op1 = NULL_RTX ; if ( GET_CODE ( x ) != IOR ) return false ; op0 = XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; if ( ( GET_CODE ( op0 ) == ASHIFT && GET_CODE ( op1 ) == LSHIFTRT ) || ( GET_CODE ( op1 ) == ASHIFT && GET_CODE ( op0 ) == LSHIFTRT ) ) { if ( GET_CODE ( op1 ) == ASHIFT ) std :: swap ( op0 , op1 ) ; if ( ! CONST_INT_P ( XEXP ( op0 , 1 ) ) || ! CONST_INT_P ( XEXP ( op1 , 1 ) ) ) return false ; unsigned HOST_WIDE_INT shft_amnt_0 = UINTVAL ( XEXP ( op0 , 1 ) ) ; unsigned HOST_WIDE_INT shft_amnt_1 = UINTVAL ( XEXP ( op1 , 1 ) ) ; if ( shft_amnt_0 < GET_MODE_BITSIZE ( mode ) && shft_amnt_0 + shft_amnt_1 == GET_MODE_BITSIZE ( mode ) ) { * res_op0 = XEXP ( op0 , 0 ) ; * res_op1 = XEXP ( op1 , 0 ) ; return true ; } } return false ; } </s>

Return true iff X is an rtx that will match an extr instruction i.e . as described in the * extr < mode > 5_insn family of patterns . OP0 and OP1 will be set to the operands of the shifts involved on success and will be NULL_RTX otherwise .


<s> bool ARMBaseRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) return AArch64II :: MO_CONSTPOOL ; else return AArch64II :: MO_GOT ; } if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return ( isDecl || GV -> isWeakForLinker ( ) ) ? AArch64II :: MO_GOT : AArch64II :: MO_NO_FLAG ; else return GV -> hasLocalLinkage ( ) ? AArch64II :: MO_NO_FLAG : AArch64II :: MO_GOT ; } return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; unsigned NumElts = SVT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && SVT . is128BitVector ( ) ) { return ( isMOVLMask ( Mask , SVT ) || isCommutedMOVLMask ( Mask , SVT , true ) || isSHUFPMask ( Mask , SVT ) || isSHUFPMask ( Mask , SVT , true ) ) ; } return false ; } </s>


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . add ( predOps ( Pred , PredReg ) ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool MipsTargetLowering :: IsEligibleForTailCallOptimization ( const MipsCC & MipsCCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! EnableMipsTailCalls ) return false ; if ( Subtarget -> inMips16Mode ( ) ) return false ; if ( MipsCCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { if ( NoFusing ) return NULL ; unsigned Alignment = 0 ; if ( LoadMI -> hasOneMemOperand ( ) ) Alignment = LoadMI -> memoperands_begin ( ) -> getAlignment ( ) ; if ( Alignment < 16 ) { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: FsANDNPDrr : case X86 :: FsANDNPSrr : case X86 :: FsANDPDrr : case X86 :: FsANDPSrr : case X86 :: FsORPDrr : case X86 :: FsORPSrr : case X86 :: FsXORPDrr : case X86 :: FsXORPSrr : return NULL ; } } if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; switch ( MI -> getOpcode ( ) ) { default : return NULL ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri32 ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return NULL ; SmallVector < MachineOperand , 4 > MOs ; if ( LoadMI -> getOpcode ( ) == X86 :: V_SET0 || LoadMI -> getOpcode ( ) == X86 :: V_SETALLONES ) { unsigned PICBase = 0 ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const VectorType * Ty = VectorType :: get ( Type :: Int32Ty , 4 ) ; Constant * C = LoadMI -> getOpcode ( ) == X86 :: V_SET0 ? ConstantVector :: getNullValue ( Ty ) : ConstantVector :: getAllOnesValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , 16 ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( 1 ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( 0 , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , 0 ) ) ; } else { unsigned NumOps = LoadMI -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - 4 ; i != NumOps ; ++ i ) MOs . push_back ( LoadMI -> getOperand ( i ) ) ; } return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MOs ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y , rtx scratch ) { machine_mode mode ; rtx cc_reg ; int dimode_comparison = GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ; if ( dimode_comparison && ! REG_P ( x ) ) x = force_reg ( DImode , x ) ; mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( dimode_comparison && mode != CC_CZmode ) { rtx clobber , set ; if ( mode == CC_Zmode && y != const0_rtx ) { gcc_assert ( ! reload_completed ) ; x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , 0 , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , const vec_perm_builder & perm ) { rtx x = expand_vec_perm_const ( vmode , op0 , op1 , perm , BLKmode , target ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave .


<s> void addInstruction ( MachineInstr * I ) { Instrs . push_back ( I ) ; } </s>

Record pressure difference induced by the given operand list to node with index Idx .


<s> static bool sparc_legitimate_constant_p ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : if ( sparc_tls_referenced_p ( x ) ) return false ; break ; case CONST_DOUBLE : if ( TARGET_VIS && SCALAR_FLOAT_MODE_P ( mode ) && ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return true ; return false ; case CONST_VECTOR : if ( TARGET_VIS && ( const_zero_operand ( x , mode ) || const_all_ones_operand ( x , mode ) ) ) return true ; return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> const VERegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s>
unsigned
assignCustomValue
(
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
assert
(
Arg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
if
(
VA
.
getValVT
(
)
!=
MVT
::
f64
)
return
0
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
Register
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildMerge
(
Arg
.
Regs
[
0
]
,
NewRegs
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> void CAHPAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst , CInst ; LowerCAHPMachineInstrToMCInst ( MI , TmpInst , * this ) ; bool Res = compressInst ( CInst , TmpInst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ; EmitToStreamer ( * OutStreamer , Res ? CInst : TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"TOY DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
&
MI
=
*
I
;
if
(
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
{
++
I
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
MI
)
;
unsigned
OutReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
const
unsigned
OrigRegs
[
]
=
{
OutReg
,
InReg
,
GPR3
}
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKDOWN
)
)
.
addImm
(
0
)
;
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
.
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
.
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKUP
)
)
.
addImm
(
0
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
.
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static rtx aarch64_strip_extend ( rtx x ) { rtx op = x ; if ( ( GET_CODE ( op ) == ZERO_EXTRACT || GET_CODE ( op ) == SIGN_EXTRACT ) && XEXP ( op , 2 ) == const0_rtx && GET_CODE ( XEXP ( op , 0 ) ) == MULT && aarch64_is_extend_from_extract ( GET_MODE ( op ) , XEXP ( XEXP ( op , 0 ) , 1 ) , XEXP ( op , 1 ) ) ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( GET_CODE ( op ) == AND && GET_CODE ( XEXP ( op , 0 ) ) == MULT && CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) && CONST_INT_P ( XEXP ( op , 1 ) ) && aarch64_uxt_size ( exact_log2 ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) , INTVAL ( XEXP ( op , 1 ) ) ) != 0 ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( GET_CODE ( op ) == ASHIFT && CONST_INT_P ( XEXP ( op , 1 ) ) && ( ( unsigned HOST_WIDE_INT ) INTVAL ( XEXP ( op , 1 ) ) ) <= 4 ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == ZERO_EXTEND || GET_CODE ( op ) == SIGN_EXTEND ) op = XEXP ( op , 0 ) ; if ( op != x ) return op ; return x ; } </s>

Helper function for rtx cost calculation . Strip an extend expression from X . Returns the inner operand if successful , or the original expression on failure . We deal with a number of possible canonicalization variations here .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
assert
(
!
IsVarArg
&&
"TODO implement var args"
)
;
assert
(
Outs
.
empty
(
)
&&
"TODO implement return values"
)
;
assert
(
OutVals
.
empty
(
)
&&
"TODO implement return values"
)
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
RetOps
[
0
]
=
Chain
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Unaligned memory access not supported: not "

"DSP extension not enabled: not running pass "

"Only supporting little endian: not running pass "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool X86InstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


"PPC DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> unsigned MipsInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case Mips :: CONSTPOOL_ENTRY : return MI . getOperand ( 2 ) . getImm ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static bool aarch64_function_value_regno_p ( const unsigned int regno ) { if ( regno == R0_REGNUM || regno == R1_REGNUM ) return true ; if ( regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS ) return TARGET_FLOAT ; return false ; } </s>

Implements TARGET_FUNCTION_VALUE_REGNO_P . Return true if REGNO is the number of a hard register in which the values of called function may come back .


<s> void FISCRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = 0 ; switch ( MI . getOpcode ( ) ) { default : return ; case FISC :: ADDri : case FISC :: LDR : case FISC :: LDRB : case FISC :: LDRH : case FISC :: LDRSW : case FISC :: LDRXR : case FISC :: LDRR : case FISC :: LDRBR : case FISC :: LDRHR : case FISC :: LDRSWR : case FISC :: LDRXRR : case FISC :: STR : case FISC :: STRB : case FISC :: STRH : case FISC :: STRW : case FISC :: STRXR : case FISC :: STRR : case FISC :: STRBR : case FISC :: STRHR : case FISC :: STRWR : case FISC :: STRXRR : ImmOpIdx = FIOperandNum + 1 ; break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) + ImmOp . getImm ( ) ; FIOp . ChangeToRegister ( FISC :: SP , false ) ; ImmOp . setImm ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

FISC FISC 0 FISC::ADDri FISC::LDR FISC::LDRB FISC::LDRH FISC::LDRSW FISC::LDRXR FISC::LDRR FISC::LDRBR FISC::LDRHR FISC::LDRSWR FISC::LDRXRR FISC::STR FISC::STRB FISC::STRH FISC::STRW FISC::STRXR FISC::STRR FISC::STRBR FISC::STRHR FISC::STRWR FISC::STRXRR 1 FISC::SP


"LowerFormalArguments Unhandled argument type: "

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void pa_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , pa_d_handle_target_float_abi } , { "objectFormat" , pa_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> Optional < MCFixupKind > X86AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; if ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; } if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> int PPCTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCost ( Opcode , Idx , Imm , Ty ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; unsigned ImmIdx = ~ 0U ; bool ShiftedFree = false , RunFree = false , UnsignedFree = false , ZeroFree = false ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: And : RunFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = 1 ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = 1 ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == 0 ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= 32 && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> isPPC64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < 16 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Free ; } return PPCTTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> unsigned PPCInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( ! ItinData || UseOldLatencyCalc ) return PPCGenInstrInfo :: getInstrLatency ( ItinData , MI , PredCost ) ; unsigned Latency = 1 ; unsigned DefClass = MI -> getDesc ( ) . getSchedClass ( ) ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isImplicit ( ) ) continue ; int Cycle = ItinData -> getOperandCycle ( DefClass , i ) ; if ( Cycle < 0 ) continue ; Latency = std :: max ( Latency , ( unsigned ) Cycle ) ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


<s> bool VEAsmParser :: parseExpression ( const MCExpr * & EVal ) { if ( getParser ( ) . parseExpression ( EVal ) ) return true ; EVal = fixupVariantKind ( EVal ) ; VEMCExpr :: VariantKind Variant ; const MCExpr * E = extractModifierFromExpr ( EVal , Variant ) ; if ( E ) EVal = VEMCExpr :: create ( Variant , E , getParser ( ) . getContext ( ) ) ; return false ; } </s>


<s> void ix86_move_vector_high_sse_to_mmx ( rtx op ) { rtx mask = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 4 , GEN_INT ( 0 ) , GEN_INT ( 2 ) , GEN_INT ( 0 ) , GEN_INT ( 0 ) ) ) ; rtx dest = lowpart_subreg ( V4SImode , op , GET_MODE ( op ) ) ; op = gen_rtx_VEC_SELECT ( V4SImode , dest , mask ) ; rtx insn = gen_rtx_SET ( dest , op ) ; emit_insn ( insn ) ; } </s>


<s>
Register
SparcTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"i0"
,
SP
::
I0
)
.
Case
(
"i1"
,
SP
::
I1
)
.
Case
(
"i2"
,
SP
::
I2
)
.
Case
(
"i3"
,
SP
::
I3
)
.
Case
(
"i4"
,
SP
::
I4
)
.
Case
(
"i5"
,
SP
::
I5
)
.
Case
(
"i6"
,
SP
::
I6
)
.
Case
(
"i7"
,
SP
::
I7
)
.
Case
(
"o0"
,
SP
::
O0
)
.
Case
(
"o1"
,
SP
::
O1
)
.
Case
(
"o2"
,
SP
::
O2
)
.
Case
(
"o3"
,
SP
::
O3
)
.
Case
(
"o4"
,
SP
::
O4
)
.
Case
(
"o5"
,
SP
::
O5
)
.
Case
(
"o6"
,
SP
::
O6
)
.
Case
(
"o7"
,
SP
::
O7
)
.
Case
(
"l0"
,
SP
::
L0
)
.
Case
(
"l1"
,
SP
::
L1
)
.
Case
(
"l2"
,
SP
::
L2
)
.
Case
(
"l3"
,
SP
::
L3
)
.
Case
(
"l4"
,
SP
::
L4
)
.
Case
(
"l5"
,
SP
::
L5
)
.
Case
(
"l6"
,
SP
::
L6
)
.
Case
(
"l7"
,
SP
::
L7
)
.
Case
(
"g0"
,
SP
::
G0
)
.
Case
(
"g1"
,
SP
::
G1
)
.
Case
(
"g2"
,
SP
::
G2
)
.
Case
(
"g3"
,
SP
::
G3
)
.
Case
(
"g4"
,
SP
::
G4
)
.
Case
(
"g5"
,
SP
::
G5
)
.
Case
(
"g6"
,
SP
::
G6
)
.
Case
(
"g7"
,
SP
::
G7
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return VT == MVT :: i32 || VT == MVT :: i64 ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + 1 ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ 0 ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( 2 , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = 1 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( 1 , reg ) , 27 ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = 0 ; i < nclobs ; ++ i ) XVECEXP ( insn , 0 , i ) = clobs [ i ] ; return insn ; } </s>

Returns an insn that has a vrsave set operation with the appropriate CLOBBERs .


<s> static void adjust_subreg_index ( rtx op ) { enum rtx_code code = GET_CODE ( op ) ; if ( code == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( op ) ) < GET_MODE_SIZE ( GET_MODE ( XEXP ( op , 0 ) ) ) ) ) { unsigned int index = SUBREG_BYTE ( op ) ; if ( index < 8 ) index += 8 ; else index -= 8 ; SUBREG_BYTE ( op ) = index ; } const char * fmt = GET_RTX_FORMAT ( code ) ; int i , j ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) adjust_subreg_index ( XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( op , i ) ; ++ j ) adjust_subreg_index ( XVECEXP ( op , i , j ) ) ; } </s>

Find all subregs of a vector expression that perform a narrowing , and adjust the subreg index to account for doubleword swapping .


<s> void aarch64_expand_sve_vec_cmp_int ( rtx target , rtx_code code , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; if ( ! aarch64_sve_cmp_operand_p ( code , op1 ) ) op1 = force_reg ( data_mode , op1 ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; rtx cond = gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ; aarch64_emit_sve_ptrue_op_cc ( target , ptrue , cond ) ; } </s>

Expand an SVE integer comparison : TARGET = CODE ( OP0 , OP1 ) .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicRMWIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicRMWInst
*
AI
,
Value
*
AlignedAddr
,
Value
*
Incr
,
Value
*
Mask
,
Value
*
ShiftAmt
,
AtomicOrdering
Ord
)
const
{
assert
(
shouldInlineQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
Incr
->
getType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
RMW
=
Intrinsic
::
getDeclaration
(
M
,
getIntrinsicForAtomicRMWBinOp128
(
AI
->
getOperation
(
)
)
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
IncrLo
=
Builder
.
CreateTrunc
(
Incr
,
Int64Ty
,
"incr_lo"
)
;
Value
*
IncrHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Incr
,
64
)
,
Int64Ty
,
"incr_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
RMW
,
{
Addr
,
IncrLo
,
IncrHi
}
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked atomicrmw using a target-specific intrinsic .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
VT
=
VA
.
getValVT
(
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VT
,
InFlag
)
.
getValue
(
1
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool isLittleEndian ( ) const { return DL . isLittleEndian ( ) ; } </s>

Tests whether the target triple is little endian .


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , outliner :: Candidate & C ) const { if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: TAILJMPd64 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


<s> bool reg_overlap_p ( rtx x , rtx in ) { if ( x == NULL_RTX || in == NULL_RTX ) return false ; return static_cast < bool > ( reg_overlap_mentioned_p ( x , in ) ) ; } </s>

A safe wrapper to the function reg_overlap_mentioned_p ( ) .


<s> static unsigned int sh_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( XD_REGISTER_P ( regno ) ) return CEIL ( GET_MODE_SIZE ( mode ) , 2 * UNITS_PER_WORD ) ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . On the SH all but the XD regs are UNITS_PER_WORD bits wide .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


<s> bool aarch64_sve_ld1ro_operand_p ( rtx op , scalar_mode elem_mode ) { return aarch64_sve_ld1rq_ld1ro_operand_p ( op , OImode , elem_mode ) ; } </s>

Return true if OP is a valid MEM operand for an SVE LD1RO instruction for accessing a vector where the element size is specified by ` elem_mode ` .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: Trap || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::Trap SystemZ::CallJG SystemZ::CallBR


<s> bool splitFramePushPop ( const MachineFunction & MF ) const { return ( useR7AsFramePointer ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ; } </s>

Returns true if the frame setup is split into two separate pushes ( first r0-r7 , lr then r8-r11 ) , principally so that the frame pointer is adjacent to lr .


<s> static void dispatch_forest ( fma_forest * forest ) { forest -> dispatch ( ) ; } </s>

Wrapper around fma_forest : :dispatch for use as parameter of function pointer type in func_fma_steering : :dfs .


<s> static unsigned estimateStackSize ( MachineFunction & MF , MachineFrameInfo * MFI ) { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; int Offset = 0 ; for ( int i = FFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - FFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = FFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( FFI -> isDeadObjectIndex ( i ) ) continue ; Offset += FFI -> getObjectSize ( i ) ; unsigned Align = FFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; } return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s> void Thumb2InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { if ( ! ARM :: GPRRegClass . contains ( DestReg , SrcReg ) ) return ARMBaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ; BuildMI ( MBB , I , DL , get ( ARM :: tMOVr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

ARM ARM::GPRRegClass ARM ARM::tMOVr ARMCC::AL


<s> static bool global_regs_p ( unsigned first , unsigned last ) { while ( first < last ) if ( global_regs [ first ++ ] ) return true ; return false ; } </s>

Look for user-defined global regs in the range FIRST to LAST-1 . We should not restore these , and so can not use lmw or out-of-line restore functions if there are any . We also ca n't save them ( well , emit frame notes for them ) , because frame unwinding during exception handling will restore saved registers .


"invalid use of MMA type %qs as a function return value"

"non-standard ABI extension with no compatibility "

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getTargetData ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> InstructionCost PPCTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( DisablePPCConstHoist ) return BaseT :: getIntImmCost ( Imm , Ty , CostKind ) ; assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return ~ 0U ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( Imm . getBitWidth ( ) <= 64 ) { if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getZExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void DCPU16InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool CSKYAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( Count % 2 ) return false ; while ( Count >= 4 ) { OS . write ( "\xc4\x00\x48\x20" , 4 ) ; Count -= 4 ; } if ( Count ) OS . write ( "\x6c\x03" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static int sh_register_move_cost ( machine_mode mode , reg_class_t srcclass , reg_class_t dstclass ) { if ( dstclass == T_REGS || dstclass == PR_REGS ) return 10 ; if ( dstclass == MAC_REGS && srcclass == MAC_REGS ) return 4 ; if ( mode == SImode && TARGET_FMOVD && REGCLASS_HAS_FP_REG ( srcclass ) && REGCLASS_HAS_FP_REG ( dstclass ) ) return 4 ; if ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == T_REGS ) return ( ( TARGET_HARD_SH4 && ! optimize_size ) ? 10 : 7 ) ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == MAC_REGS ) || ( dstclass == MAC_REGS && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return 9 ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( REGCLASS_HAS_GENERAL_REG ( dstclass ) && REGCLASS_HAS_FP_REG ( srcclass ) ) ) { int addend = ( mode == Pmode ) ? 40 : 0 ; return ( ( TARGET_FMOVD ? 8 : 12 ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 5 ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return 7 ; if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 4 ; if ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) return 2 * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; return 2 * ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4U ) ; } </s>

If SECONDARY * _RELOAD_CLASS says something about the src/dst pair , regclass uses this information . Hence , the general register < - > floating point register information here is not used for SFmode .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
static
void
ia64_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
int
mask
,
grsave
,
grsave_prev
;
if
(
current_frame_info
.
need_regstk
)
fprintf
(
file
,
"\t.regstk %d, %d, %d, %d\n"
,
current_frame_info
.
n_input_regs
,
current_frame_info
.
n_local_regs
,
current_frame_info
.
n_output_regs
,
current_frame_info
.
n_rotate_regs
)
;
if
(
ia64_except_unwind_info
(
&
global_options
)
!=
UI_TARGET
)
return
;
mask
=
0
;
grsave
=
grsave_prev
=
0
;
if
(
current_frame_info
.
r
[
reg_save_b0
]
!=
0
)
{
mask
|=
8
;
grsave
=
grsave_prev
=
current_frame_info
.
r
[
reg_save_b0
]
;
}
if
(
current_frame_info
.
r
[
reg_save_ar_pfs
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_save_ar_pfs
]
==
grsave_prev
+
1
)
)
{
mask
|=
4
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
r
[
reg_save_ar_pfs
]
;
grsave_prev
=
current_frame_info
.
r
[
reg_save_ar_pfs
]
;
}
if
(
current_frame_info
.
r
[
reg_fp
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_fp
]
==
grsave_prev
+
1
)
)
{
mask
|=
2
;
if
(
grsave_prev
==
0
)
grsave
=
HARD_FRAME_POINTER_REGNUM
;
grsave_prev
=
current_frame_info
.
r
[
reg_fp
]
;
}
if
(
current_frame_info
.
r
[
reg_save_pr
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_save_pr
]
==
grsave_prev
+
1
)
)
{
mask
|=
1
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
r
[
reg_save_pr
]
;
}
if
(
mask
&&
TARGET_GNU_AS
)
fprintf
(
file
,
"\t.prologue %d, %d\n"
,
mask
,
ia64_dbx_register_number
(
grsave
)
)
;
else
fputs
(
"\t.prologue\n"
,
file
)
;
if
(
current_frame_info
.
spill_cfa_off
!=
16
)
fprintf
(
file
,
"\t.spill %ld\n"
,
(
long
)
(
current_frame_info
.
spill_cfa_off
+
current_frame_info
.
spill_size
)
)
;
}
</s>


"insertBranch must not be told to insert a fallthrough"

"# of Mips branch conditions must be <= 3!"

Insert branch code into the end of the specified MachineBasicBlock .


"OpenRISC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static void aarch64_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { rtx reg1 = gen_rtx_REG ( Pmode , PROBE_STACK_FIRST_REG ) ; gcc_assert ( ( first % ARITH_FACTOR ) == 0 ) ; if ( size <= PROBE_INTERVAL ) { const HOST_WIDE_INT base = ROUND_UP ( size , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - ( first + base ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg1 , base - size ) ) ; } else if ( size <= 4 * PROBE_INTERVAL ) { HOST_WIDE_INT i , rem ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - ( first + PROBE_INTERVAL ) ) ) ; emit_stack_probe ( reg1 ) ; for ( i = 2 * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_set_insn ( reg1 , plus_constant ( Pmode , reg1 , - PROBE_INTERVAL ) ) ; emit_stack_probe ( reg1 ) ; } rem = size - ( i - PROBE_INTERVAL ) ; if ( rem > 256 ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg1 , plus_constant ( Pmode , reg1 , - base ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg1 , base - rem ) ) ; } else emit_stack_probe ( plus_constant ( Pmode , reg1 , - rem ) ) ; } else { rtx reg2 = gen_rtx_REG ( Pmode , PROBE_STACK_SECOND_REG ) ; HOST_WIDE_INT rounded_size = size & - PROBE_INTERVAL ; emit_set_insn ( reg1 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ; emit_set_insn ( reg2 , plus_constant ( Pmode , stack_pointer_rtx , - ( first + rounded_size ) ) ) ; emit_insn ( gen_probe_stack_range ( reg1 , reg1 , reg2 ) ) ; if ( size != rounded_size ) { HOST_WIDE_INT rem = size - rounded_size ; if ( rem > 256 ) { const HOST_WIDE_INT base = ROUND_UP ( rem , ARITH_FACTOR ) ; emit_set_insn ( reg2 , plus_constant ( Pmode , reg2 , - base ) ) ; emit_stack_probe ( plus_constant ( Pmode , reg2 , base - rem ) ) ; } else emit_stack_probe ( plus_constant ( Pmode , reg2 , - rem ) ) ; } } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> const char * KudeyarTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case KudeyarISD :: BR_CC_T : return "KudeyarISD::BR_CC_T" ; case KudeyarISD :: BR_CC_F : return "KudeyarISD::BR_CC_F" ; case KudeyarISD :: SELECT_CC_T : return "KudeyarISD::SELECT_CC_T" ; case KudeyarISD :: SELECT_CC_F : return "KudeyarISD::SELECT_CC_f" ; case KudeyarISD :: CMPEQ : return "KudeyarISD::CMPEQ" ; case KudeyarISD :: CMPGT : return "KudeyarISD::CMPGT" ; case KudeyarISD :: CMPLT : return "KudeyarISD::CMPLT" ; case KudeyarISD :: CMPGTU : return "KudeyarISD::CMPGTU" ; case KudeyarISD :: CMPLTU : return "KudeyarISD::CMPLTU" ; case KudeyarISD :: CALL : return "KudeyarISD::CALL" ; case KudeyarISD :: RET_FLAG : return "KudeyarISD::RET_FLAG" ; case KudeyarISD :: RETI_FLAG : return "KudeyarISD::RETI_FLAG" ; case KudeyarISD :: Wrapper : return "KudeyarISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> ScheduleHazardRecognizer :: HazardType Thumb2HazardRecognizer :: getHazardType ( SUnit * SU ) { if ( ITBlockSize ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) && MI != ITBlockMIs [ ITBlockSize - 1 ] ) return Hazard ; } return PostRAHazardRecognizer :: getHazardType ( SU ) ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; high = nelt / 2 ; if ( d -> perm [ 0 ] == high ) ; else if ( d -> perm [ 0 ] == 0 ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * 2 ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * 2 + 1 ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) x = out0 , out0 = out1 , out1 = x ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> unsigned PPCTTIImpl :: getPrefetchDistance ( ) const { return 300 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> const TargetRegisterClass * X86RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { if ( RC == & X86 :: GR8_NOREXRegClass ) return RC ; const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case X86 :: FR32RegClassID : case X86 :: FR64RegClassID : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: VR128RegClassID : case X86 :: VR256RegClassID : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case X86 :: FR32XRegClassID : case X86 :: FR64XRegClassID : if ( ! Subtarget . hasVLX ( ) ) break ; case X86 :: VR128XRegClassID : case X86 :: VR256XRegClassID : if ( ! Subtarget . hasAVX512 ( ) ) break ; case X86 :: GR8RegClassID : case X86 :: GR16RegClassID : case X86 :: GR32RegClassID : case X86 :: GR64RegClassID : case X86 :: RFP32RegClassID : case X86 :: RFP64RegClassID : case X86 :: RFP80RegClassID : case X86 :: VR512RegClassID : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> SDValue PPCTargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } else { return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s> void PPCDAGToDAGISel :: PostprocessISelDAG ( ) { if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; PeepholePPC64 ( ) ; PeepholeCROps ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? 0 : llvm :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> bool ix86_force_load_from_GOT_p ( rtx x , bool call_p ) { return ( ( TARGET_64BIT || ( ! flag_pic && HAVE_AS_IX86_GOT32X ) ) && ! TARGET_PECOFF && ! TARGET_MACHO && ( ! flag_pic || this_is_asm_operands ) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC && GET_CODE ( x ) == SYMBOL_REF && ( ( ! call_p && ( ! ix86_direct_extern_access || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( "nodirect_extern_access" , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) ) || ( SYMBOL_REF_FUNCTION_P ( x ) && ( ! flag_plt || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) ) ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

True if the function symbol operand X should be loaded from GOT . NB : In 32-bit mode , only non-PIC is allowed in inline assembly statements , since a PIC register could not be available at the call site .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
default
:
break
;
}
bool
IsNaCl
=
Subtarget
.
isTargetNaCl
(
)
;
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
IsNaCl
)
{
if
(
CallsEHReturn
)
return
CSR_NaCl64EHRet_SaveList
;
return
CSR_NaCl64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>