<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
0
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
0
ARM::tRestore
0


<s> unsigned CSKYInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case CSKY :: CONSTPOOL_ENTRY : return MI . getOperand ( 2 ) . getImm ( ) ; case CSKY :: SPILL_CARRY : case CSKY :: RESTORE_CARRY : case CSKY :: PseudoTLSLA32 : return 8 ; case TargetOpcode :: INLINEASM_BR : case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

PowerPC PPC PPC 0 PPC::VRSAVE PPC::CR2 PPC::CR4 PPC PPC PPC PPC::MFCR PPC::R12 PPC::STW PPC::R12 PPC::MTVSRD


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> rtx aarch64_gen_compare_reg ( RTX_CODE code , rtx x , rtx y ) { machine_mode cmp_mode = GET_MODE ( x ) ; machine_mode cc_mode ; rtx cc_reg ; if ( cmp_mode == TImode ) { gcc_assert ( code == NE ) ; cc_mode = CCmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; rtx x_lo = operand_subword ( x , 0 , 0 , TImode ) ; rtx y_lo = operand_subword ( y , 0 , 0 , TImode ) ; emit_set_insn ( cc_reg , gen_rtx_COMPARE ( cc_mode , x_lo , y_lo ) ) ; rtx x_hi = operand_subword ( x , 1 , 0 , TImode ) ; rtx y_hi = operand_subword ( y , 1 , 0 , TImode ) ; emit_insn ( gen_ccmpccdi ( cc_reg , cc_reg , x_hi , y_hi , gen_rtx_EQ ( cc_mode , cc_reg , const0_rtx ) , GEN_INT ( AARCH64_EQ ) ) ) ; } else { cc_mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , gen_rtx_COMPARE ( cc_mode , x , y ) ) ; } return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode .


<s> static int rs6000_variable_issue_1 ( rtx_insn * insn , int more ) { last_scheduled_insn = insn ; if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) { cached_can_issue_more = more ; return cached_can_issue_more ; } if ( insn_terminates_group_p ( insn , current_group ) ) { cached_can_issue_more = 0 ; return cached_can_issue_more ; } if ( recog_memoized ( insn ) < 0 ) return more ; if ( rs6000_sched_groups ) { if ( is_microcoded_insn ( insn ) ) cached_can_issue_more = 0 ; else if ( is_cracked_insn ( insn ) ) cached_can_issue_more = more > 2 ? more - 2 : 0 ; else cached_can_issue_more = more - 1 ; return cached_can_issue_more ; } if ( rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn ( insn ) ) return 0 ; cached_can_issue_more = more - 1 ; return cached_can_issue_more ; } </s>

Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle . Branches have their own dispatch slot which does not count against the GCC issue rate , but it changes the program flow so there are no other instructions to issue in this cycle .


<s> virtual void getAnalysisUsage ( AnalysisUsage & Info ) { Info . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << "[" << TRI -> getAsmName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << "]" ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum ) ; return false ; case 'P' : printOperand ( MI , OpNum ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNum ) . isReg ( ) || OpNum + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNum + 1 ) . isReg ( ) ) return true ; ++ OpNum ; } } printOperand ( MI , OpNum ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; PPCFunctionInfo * FI = MF -> getInfo < PPCFunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == PPC :: X2 || Reg == PPC :: R2 ) && MustSaveTOC ) continue ; if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>


<s> static void ix86_emit_save_reg_using_mov ( machine_mode mode , unsigned int regno , HOST_WIDE_INT cfa_offset ) { struct machine_function * m = cfun -> machine ; rtx reg = gen_rtx_REG ( mode , regno ) ; rtx mem , addr , base , insn ; addr = choose_baseaddr ( cfa_offset ) ; mem = gen_frame_mem ( mode , addr ) ; set_mem_align ( mem , GET_MODE_ALIGNMENT ( mode ) ) ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; base = addr ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , 0 ) ; gcc_checking_assert ( REG_P ( base ) ) ; if ( m -> fs . realigned ) { gcc_checking_assert ( stack_realign_drap ) ; if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( VOIDmode , mem , reg ) ) ; } } else if ( base != m -> fs . cfa_reg ) { addr = plus_constant ( Pmode , m -> fs . cfa_reg , m -> fs . cfa_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( VOIDmode , mem , reg ) ) ; } } </s>

Emit a single register save at CFA - CFA_OFFSET .


<s> bool mips_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , machine_mode mode ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( ( ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) && ( ( TARGET_FLOATXX && ! ISA_HAS_MXHC1 ) || TARGET_O32_FP64A_ABI ) && GET_MODE_SIZE ( mode ) >= 8 ) return true ; return false ; } </s>


<s> static rtx_code_label * ix86_expand_aligntest ( rtx variable , int value , bool epilogue ) { rtx_code_label * label = gen_label_rtx ( ) ; rtx tmpcount = gen_reg_rtx ( GET_MODE ( variable ) ) ; if ( GET_MODE ( variable ) == DImode ) emit_insn ( gen_anddi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; else emit_insn ( gen_andsi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; emit_cmp_and_jump_insns ( tmpcount , const0_rtx , EQ , 0 , GET_MODE ( variable ) , 1 , label ) ; if ( epilogue ) predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; else predict_jump ( REG_BR_PROB_BASE * 90 / 100 ) ; return label ; } </s>

Helper function for the string operations below . Dest VARIABLE whether it is aligned to VALUE bytes . If true , jump to the label .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NaCl Rewrites"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> BitVector MandarinRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( MD :: R30 ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( MD :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool SICTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_SIC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) Known . Zero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpequq_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtsq_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : case Intrinsic :: ppc_altivec_vcmpgtuq_p : Known . Zero = ~ 1U ; break ; } break ; } case ISD :: INTRINSIC_W_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_load2r : Known . Zero = 0xFFFF0000 ; break ; } break ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static bool ix86_unordered_fp_compare ( enum rtx_code code ) { if ( ! TARGET_IEEE_FP ) return false ; switch ( code ) { case LT : case LE : case GT : case GE : case LTGT : return false ; case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return true ; default : gcc_unreachable ( ) ; } } </s>

Figure out whether to use unordered fp comparisons .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> int ARMBaseInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { if ( ! ItinData || ItinData -> isEmpty ( ) ) return - 1 ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const MCInstrDesc * DefMCID = & DefMI -> getDesc ( ) ; const MCInstrDesc * UseMCID = & UseMI -> getDesc ( ) ; unsigned DefAdj = 0 ; if ( DefMI -> isBundle ( ) ) { DefMI = getBundledDefMI ( & getRegisterInfo ( ) , DefMI , Reg , DefIdx , DefAdj ) ; DefMCID = & DefMI -> getDesc ( ) ; } if ( DefMI -> isCopyLike ( ) || DefMI -> isInsertSubreg ( ) || DefMI -> isRegSequence ( ) || DefMI -> isImplicitDef ( ) ) { return 1 ; } unsigned UseAdj = 0 ; if ( UseMI -> isBundle ( ) ) { unsigned NewUseIdx ; const MachineInstr * NewUseMI = getBundledUseMI ( & getRegisterInfo ( ) , UseMI , Reg , NewUseIdx , UseAdj ) ; if ( ! NewUseMI ) return - 1 ; UseMI = NewUseMI ; UseIdx = NewUseIdx ; UseMCID = & UseMI -> getDesc ( ) ; } if ( Reg == ARM :: CPSR ) { if ( DefMI -> getOpcode ( ) == ARM :: FMSTAT ) { return Subtarget . isLikeA9 ( ) ? 1 : 20 ; } if ( UseMI -> isBranch ( ) ) return 0 ; unsigned Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency > 0 && Subtarget . isThumb2 ( ) ) { const MachineFunction * MF = DefMI -> getParent ( ) -> getParent ( ) ; if ( MF -> getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: OptimizeForSize ) ) -- Latency ; } return Latency ; } if ( DefMO . isImplicit ( ) || UseMI -> getOperand ( UseIdx ) . isImplicit ( ) ) return - 1 ; unsigned DefAlign = DefMI -> hasOneMemOperand ( ) ? ( * DefMI -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; unsigned UseAlign = UseMI -> hasOneMemOperand ( ) ? ( * UseMI -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Latency = getOperandLatency ( ItinData , * DefMCID , DefIdx , DefAlign , * UseMCID , UseIdx , UseAlign ) ; if ( Latency < 0 ) return Latency ; int Adj = DefAdj + UseAdj ; Adj += adjustDefLatency ( Subtarget , DefMI , DefMCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , ELFWriterInfo ( is64Bit , true ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; } </s>


<s> int AArch64FrameLowering :: getNonLocalFrameIndexReference ( const MachineFunction & MF , int FI ) const { return getSEHFrameIndexOffset ( MF , FI ) ; } </s>

getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index location .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & AArch64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>


<s> int mmix_use_simple_return ( void ) { int regno ; int stack_space_to_allocate = ( crtl -> outgoing_args_size + crtl -> args . pretend_args_size + get_frame_size ( ) + 7 ) & ~ 7 ; if ( ! TARGET_USE_RETURN_INSN || ! reload_completed ) return 0 ; for ( regno = 255 ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return 0 ; if ( frame_pointer_needed ) stack_space_to_allocate += 8 ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_allocate += 16 ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_allocate += 8 ; return stack_space_to_allocate == 0 ; } </s>

Nonzero when the function epilogue is simple enough that a single `` POP % d,0 '' should be used even within the function .


<s> static int first_altivec_reg_to_save ( void ) { int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + 1 ; for ( i = FIRST_ALTIVEC_REGNO + 20 ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) break ; return i ; } </s>


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , MCSectionELF :: SHT_INIT_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , MCSectionELF :: SHT_FINI_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , MCSectionELF :: SHT_ARM_ATTRIBUTES , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned MaxAlign = calculateMaxStackAlignment ( FFI ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum ) -> getAlignment ( ) ) ; if ( FFI -> getMaxAlignment ( ) == MaxAlign ) return false ; FFI -> setMaxAlignment ( MaxAlign ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx rs6000_gen_le_vsx_permute ( rtx source , machine_mode mode ) { if ( FLOAT128_VECTOR_P ( mode ) || mode == TImode || mode == V1TImode ) return gen_rtx_ROTATE ( mode , source , GEN_INT ( 64 ) ) ; else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par ) ; } } </s>

Generate a permute rtx that represents an lxvd2x , stxvd2x , or xxpermdi for a VSX load or store operation .


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! Subtarget . allowsUnalignedFPAccess ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool ARMTargetLowering :: isLegalT1ScaledAddressingMode ( const AddrMode & AM , EVT VT ) const { const int Scale = AM . Scale ; if ( Scale < 0 ) return false ; return ( Scale == 1 ) || ( ! AM . HasBaseReg && Scale == 2 ) ; } </s>

Returns true if the addressing mode representing by AM is legal for the Thumb1 target , for a load/store of the specified type .


<s> machine_mode select_cc_mode ( enum rtx_code op , rtx x , rtx y ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : case LTGT : return CCFPmode ; case LT : case LE : case GT : case GE : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCX_NOOVmode ; else return CC_NOOVmode ; } else { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXmode ; else return CCmode ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the first operand of a COMPARE , return the mode to be used for the comparison . For floating-point , CCFP [ E ] mode is used . CC_NOOVmode should be used when the first operand is a PLUS , MINUS , NEG , or ASHIFT . CCmode should be used when no special processing is needed .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < EdgeBundles > ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"invalid conversion from type %<__vector_quad%>"

"invalid conversion to type %<__vector_quad%>"

"invalid conversion from type %<__vector_pair%>"

"invalid conversion to type %<__vector_pair%>"


<s> bool rs6000_is_valid_2insn_and ( rtx c , machine_mode mode ) { if ( rs6000_is_valid_mask ( c , NULL , NULL , mode ) ) return true ; unsigned HOST_WIDE_INT val = INTVAL ( c ) ; unsigned HOST_WIDE_INT bit1 = val & - val ; unsigned HOST_WIDE_INT bit2 = ( val + bit1 ) & ~ val ; unsigned HOST_WIDE_INT val1 = ( val + bit1 ) & val ; unsigned HOST_WIDE_INT bit3 = val1 & - val1 ; return rs6000_is_valid_and_mask ( GEN_INT ( val + bit3 - bit2 ) , mode ) ; } </s>

Return whether an AND with C ( a CONST_INT ) in mode MODE can be done using two machine instructions .


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; auto Stubs = MMIMacho . getAuthGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( "__DATA" , "__auth_ptr" , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; emitAlignment ( Align ( 8 ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> void Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


Wrapper around the output_probe_stack_range routines .


<s> Register MMIXRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return MMIX :: r253 ; } </s>


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return ( STI . isTargetIOS ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


<s> unsigned X86TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { assert ( ! isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) ; return Subtarget . isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> void init_builtins ( ) { sve_switcher sve ; register_builtin_types ( ) ; if ( in_lto_p ) handle_arm_sve_h ( ) ; } </s>

Initialize all compiler built-ins related to RVV that should be defined at start-up .


<s> bool isLegalMaskedStore ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked store .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> unsigned size ( ) const { return Insts . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> static ARMOperand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { ARMOperand * Op = new ARMOperand ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> StringRef X86TargetLowering :: getStackProbeSymbolName ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) || MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) return "" ; if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? "___chkstk_ms" : "__chkstk" ; return Subtarget . isTargetCygMing ( ) ? "_alloca" : "_chkstk" ; } </s>

Returns the name of the symbol used to emit stack probes or the empty string if not applicable .


<s> static bool fixed_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return false ; return fixed_regs [ reg ] ; } </s>

Return whether REG is a global user reg or has been specifed by -ffixed-REG . We should not restore these , and so can not use lmw or out-of-line restore functions if there are any . We also ca n't save them ( well , emit frame notes for them ) , because frame unwinding during exception handling will restore saved registers .


<s> const CallLowering * getCallLowering ( ) const override { return CallLoweringInfo . get ( ) ; } </s>


<s> tree aarch64_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= AARCH64_BUILTIN_MAX ) return error_mark_node ; return aarch64_builtin_decls [ code ] ; } </s>


<s> bool aarch64_pad_reg_upward ( machine_mode mode , const_tree type , bool first ATTRIBUTE_UNUSED ) { if ( BYTES_BIG_ENDIAN && aarch64_composite_type_p ( type , mode ) ) { HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( size < 2 * UNITS_PER_WORD ) return true ; } return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . It specifies padding for the last ( may also be the only ) element of a block move between registers and memory . If assuming the block is in the memory , padding upward means that the last element is padded after its highest significant byte , while in downward padding , the last element is padded at the its least significant byte side . Small aggregates and small complex types are always padded upwards . We do n't need to worry about homogeneous floating-point or short-vector aggregates ; their move is not affected by the padding direction determined here . Regardless of endianness , each element of such an aggregate is put in the least significant bits of a fp/simd register . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does .


<s>
uint32_t
ARM64MCCodeEmitter
::
getBranchTargetOpValue
(
const
MCInst
&
MI
,
unsigned
OpIdx
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
OpIdx
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
&&
"Unexpected ADR target type!"
)
;
MCFixupKind
Kind
=
MI
.
getOpcode
(
)
==
ARM64
::
BL
MCFixupKind
(
ARM64
::
fixup_arm64_pcrel_call26
)
:
MCFixupKind
(
ARM64
::
fixup_arm64_pcrel_branch26
)
;
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
MO
.
getExpr
(
)
,
Kind
,
MI
.
getLoc
(
)
)
)
;
++
MCNumFixups
;
return
0
;
}
</s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static rtx arm_expand_neon_builtin ( int fcode , tree exp , rtx target ) { neon_builtin_datum * d = & neon_builtin_data [ fcode - ARM_BUILTIN_NEON_BASE ] ; enum insn_code icode = d -> code ; builtin_arg args [ SIMD_MAX_BUILTIN_ARGS ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = 0 ; int k ; is_void = ! ! ( d -> qualifiers [ 0 ] & qualifier_void ) ; num_args += is_void ; for ( k = 1 ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - 1 ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_immediate ) args [ k ] = NEON_ARG_CONSTANT ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_maybe_immediate ) { rtx arg = expand_normal ( CALL_EXPR_ARG ( exp , ( expr_args_k ) ) ) ; bool op_const_int_p = ( CONST_INT_P ( arg ) && ( * insn_data [ icode ] . operand [ operands_k ] . predicate ) ( arg , insn_data [ icode ] . operand [ operands_k ] . mode ) ) ; args [ k ] = op_const_int_p ? NEON_ARG_CONSTANT : NEON_ARG_COPY_TO_REG ; } else if ( d -> qualifiers [ qualifiers_k ] & qualifier_pointer ) args [ k ] = NEON_ARG_MEMORY ; else args [ k ] = NEON_ARG_COPY_TO_REG ; } args [ k ] = NEON_ARG_STOP ; return arm_expand_neon_args ( target , d -> mode , fcode , icode , ! is_void , exp , args [ 1 ] , args [ 2 ] , args [ 3 ] , args [ 4 ] , NEON_ARG_STOP ) ; } </s>

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Indirect Thunks"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx ix86_internal_arg_pointer ( void ) { return virtual_incoming_args_rtx ; } </s>

Handle the TARGET_INTERNAL_ARG_POINTER hook .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> const uint32_t * LC2200RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> Optional < RegImmPair > ARMBaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , Register Reg ) const { int Sign = 1 ; unsigned Opcode = MI . getOpcode ( ) ; int64_t Offset = 0 ; if ( Reg != MI . getOperand ( 0 ) . getReg ( ) ) return None ; if ( Opcode == ARM :: SUBri ) Sign = - 1 ; else if ( Opcode != ARM :: ADDri ) return None ; if ( ! MI . getOperand ( 0 ) . isReg ( ) || ! MI . getOperand ( 1 ) . isReg ( ) || ! MI . getOperand ( 2 ) . isImm ( ) ) return None ; Offset = MI . getOperand ( 2 ) . getImm ( ) * Sign ; return RegImmPair { MI . getOperand ( 1 ) . getReg ( ) , Offset } ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsRegisterInfo * RegInfo = static_cast < const MipsRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: CPU64RegsRegClass : & Mips :: CPURegsRegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips::SP_64 Mips::SP Mips::FP_64 Mips::FP Mips::ZERO_64 Mips::ZERO Mips::DADDu Mips::ADDu 0 Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass 0 0 4 Mips


<s> static void arm_init_neon_builtins ( void ) { unsigned int i , fcode = ARM_BUILTIN_NEON_PATTERN_START ; arm_init_simd_builtin_types ( ) ; arm_init_simd_builtin_scalar_types ( ) ; for ( i = 0 ; i < ARRAY_SIZE ( neon_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & neon_builtin_data [ i ] ; arm_init_builtin ( fcode , d , "__builtin_neon" ) ; } } </s>

Set up all the NEON builtins , even builtins for instructions that are not in the current target ISA to allow the user to compile particular modules with different target specific options that differ from the command line options . Such builtins will be rejected in arm_expand_builtin .


<s> bool X86TargetLowering :: shouldFoldMaskToVariableShiftPair ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( VT == MVT :: i64 && ! Subtarget . is64Bit ( ) ) return false ; return true ; } </s>

There are two ways to clear extreme bits ( either low or high ) : Mask : x & ( -1 < < y ) ( the instcombine canonical form ) Shifts : x > > y < < y Return true if the variant with 2 variable shifts is preferred .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
IMMEDIATE
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
TOKEN
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
REGISTER
:
OS
<<
"Reg: %r"
<<
getReg
(
)
<<
"\n"
;
break
;
case
MEMORY_IMM
:
OS
<<
"MemImm: "
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
MEMORY_REG_IMM
:
OS
<<
"MemRegImm: "
<<
getMemBaseReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
MEMORY_REG_REG
:
assert
(
getMemOffset
(
)
==
nullptr
)
;
OS
<<
"MemRegReg: "
<<
getMemBaseReg
(
)
<<
"+"
<<
"%r"
<<
getMemOffsetReg
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

Lanai
"Imm: "
"\n"
"Token: "
"\n"
"Reg: %r"
"\n"
"MemImm: "
"\n"
"MemRegImm: "
"+"
"\n"
"MemRegReg: "
"+"
"%r"
"\n"


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
VarArgsFrameIndex
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
FP16_TO_FP32
:
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP32_TO_FP16
:
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
break
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShift
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
SHL_PARTS
:
return
LowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
case
ISD
::
SRA_PARTS
:
return
LowerShiftRightParts
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
return
LowerCTTZ
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
VSETCC
:
return
LowerVSETCC
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned getMinPrefetchStride ( ) const { return MinPrefetchStride ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ARMISD :: FMRRD : return PerformFMRRDCombine ( N , DCI ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

ARM ARM ISD::ADD ISD::SUB ARMISD::FMRRD ISD::INTRINSIC_WO_CHAIN ISD::SHL ISD::SRA ISD::SRL ISD::SIGN_EXTEND ISD::ZERO_EXTEND ISD::ANY_EXTEND


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , 1 ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


"Interrupt handlers cannot return any value"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned TOYInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case TOY :: STORErr : if ( MI -> getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


"argument to %qs must be a 2-bit unsigned literal"


<s> static void mips_frame_barrier ( void ) { emit_clobber ( gen_frame_mem ( BLKmode , stack_pointer_rtx ) ) ; } </s>

Emit an optimisation barrier for accesses to the current frame .


<s> rtx neon_make_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; rtx target ; rtx const_vec = NULL_RTX ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_const = 0 ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL && neon_immediate_valid_for_move ( const_vec , mode , NULL , NULL ) ) return const_vec ; else if ( ( target = neon_vdup_constant ( vals ) ) != NULL_RTX ) return target ; else if ( const_vec != NULL_RTX ) return const_vec ; else return NULL_RTX ; } </s>

Generate code to load VALS , which is a PARALLEL containing only constants ( for vec_init ) or CONST_VECTOR , efficiently into a register . Returns an RTX to copy into the register , or NULL_RTX for a PARALLEL that can not be converted into a CONST_VECTOR .


"missing value in %<target()%> pragma or attribute"

"invalid feature modifier %s of value (\"%s\") in "

Parse an architecture extensions target attribute string specified in STR . For example `` +fp+nosimd '' . Show any errors if needed . Return TRUE if successful . Update aarch64_isa_flags to reflect the ISA features modified . PRAGMA_OR_ATTR is used in potential error messages .


"switch -mcpu=%s conflicts with -march=%s switch"

"Assembler does not support -mabi=ilp32"

"Return address signing is only supported for -mabi=lp64"


<s> static bool loongarch_valid_base_register_p ( rtx x , machine_mode mode , bool strict_p ) { if ( ! strict_p && SUBREG_P ( x ) ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && loongarch_regno_mode_ok_for_base_p ( REGNO ( x ) , mode , strict_p ) ) ; } </s>

Return true if X is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN ( branch ) ) ; int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , 1 ) ; dest = XEXP ( dest , 0 ) ; dest_uid = INSN_UID ( dest ) ; return INSN_ADDRESSES ( dest_uid ) ; } </s>

Return the destination address of BRANCH . We need to use this instead of get_attr_length , because the cbranch_with_nops pattern conservatively sets its length to 6 , and we still prefer to use shorter sequences .


<s> static void loongarch_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) loongarch_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > 0 ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ; } </s>


<s> void SystemZInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( LoadOpcode ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned AArch64TargetLowering :: combineRepeatedFPDivisors ( ) const { return 3 ; } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> void func_fma_steering :: execute_fma_steering ( ) { df_set_flags ( DF_LR_RUN_DCE ) ; df_note_add_problem ( ) ; df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; regrename_init ( true ) ; regrename_analyze ( NULL ) ; this -> analyze ( ) ; this -> rename_fma_trees ( ) ; regrename_finish ( ) ; } </s>


<s> static bool currently_supported_simd_type ( tree t , tree b ) { if ( COMPLEX_FLOAT_TYPE_P ( t ) ) return false ; if ( TYPE_SIZE ( t ) != TYPE_SIZE ( b ) ) return false ; return supported_simd_type ( t ) ; } </s>

Return true for types that currently are supported as SIMD return or argument types .


<s> void AArch64AsmPrinter :: emitFunctionEntryLabel ( ) { if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AArch64_VectorCall || MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AArch64_SVE_VectorCall || STI -> getRegisterInfo ( ) -> hasSVEArgsOrReturn ( MF ) ) { auto * TS = static_cast < AArch64TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TS -> emitDirectiveVariantPCS ( CurrentFnSym ) ; } return AsmPrinter :: emitFunctionEntryLabel ( ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I , * this ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( createX86InstructionSelector ( * this , * I , * RBI ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"code model %s does not support PIC mode"

Adjust target options after streaming them in . This is mainly about reconciling them with global options .


<s> bool AArch64InstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: SUBSWrr : case AArch64 :: SUBSWrs : case AArch64 :: SUBSWrx : case AArch64 :: SUBSXrr : case AArch64 :: SUBSXrs : case AArch64 :: SUBSXrx : case AArch64 :: ADDSWrr : case AArch64 :: ADDSWrs : case AArch64 :: ADDSWrx : case AArch64 :: ADDSXrr : case AArch64 :: ADDSXrs : case AArch64 :: ADDSXrx : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWri : case AArch64 :: ADDSWri : case AArch64 :: SUBSXri : case AArch64 :: ADDSXri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) != 0 ; return true ; case AArch64 :: ANDSWri : case AArch64 :: ANDSXri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = AArch64_AM :: decodeLogicalImmediate ( MI . getOperand ( 2 ) . getImm ( ) , MI . getOpcode ( ) == AArch64 :: ANDSWri ? 32 : 64 ) != 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void aarch64_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; const enum memmodel model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; const bool is_sync = is_mm_sync ( model ) ; rtx_code_label * label ; rtx x ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , 0 ) ; if ( is_sync ) aarch64_emit_load_exclusive ( mode , old_out , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , old_out , mem , model_rtx ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; } aarch64_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , model_rtx ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; if ( is_sync ) aarch64_emit_post_barrier ( model ) ; } </s>


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; int Offset = M -> getStackProtectorGuardOffset ( ) ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; StringRef GuardReg = M -> getStackProtectorGuardReg ( ) ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const override { return NumCycles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> static void ix86_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 ( & next_cum ) ; else setup_incoming_varargs_64 ( & next_cum ) ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s>
void
MandarinInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
MD
::
GenericRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
MD
::
MOVrr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
if
(
MD
::
DoubleRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
MD
::
MOV2rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
if
(
MD
::
DoubleRegsRegClass
.
contains
(
DestReg
)
&&
(
SrcReg
==
MD
::
R0
||
SrcReg
==
MD
::
R2
)
)
{
printf
(
"Registers are already there\n"
)
;
}
else
if
(
MD
::
QuadRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
MD
::
MOV4rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
if
(
MD
::
QuadRegsRegClass
.
contains
(
DestReg
)
&&
SrcReg
==
MD
::
R0
)
{
printf
(
"Registers are already there\n"
)
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>

Mandarin
MD::GenericRegsRegClass
MD::MOVrr
MD::DoubleRegsRegClass
MD::MOV2rr
MD::DoubleRegsRegClass
MD::R0
MD::R2
"Registers are already there\n"
MD::QuadRegsRegClass
MD::MOV4rr
MD::QuadRegsRegClass
MD::R0
"Registers are already there\n"
"Impossible reg-to-reg copy"


<s> static void sparc_asm_function_prologue ( FILE * file ) { if ( ! TARGET_FLAT ) gcc_assert ( sparc_leaf_function_p == crtl -> uses_only_leaf_regs ) ; sparc_output_scratch_registers ( file ) ; } </s>

This function generates the assembly code for function entry , which boils down to emitting the necessary .register directives .


<s> SDNode * SparcDAGToDAGISel :: Select ( SDValue Op ) { SDNode * N = Op . getNode ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: SDIV : case ISD :: UDIV : { SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getTargetNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getTargetNode ( SP :: WRYrr , dl , MVT :: Flag , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getTargetNode ( Opcode , dl , MVT :: i32 , MVT :: Flag , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDY , MVT :: i32 , SDValue ( Mul , 1 ) ) ; return NULL ; } } return SelectCode ( Op ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static machine_mode select_block_compare_mode ( unsigned HOST_WIDE_INT offset , unsigned HOST_WIDE_INT bytes , unsigned HOST_WIDE_INT align , bool word_mode_ok ) { unsigned HOST_WIDE_INT maxread = ROUND_UP ( bytes , align ) ; if ( word_mode_ok && bytes >= UNITS_PER_WORD ) return word_mode ; else if ( bytes == GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes == GET_MODE_SIZE ( HImode ) ) return HImode ; else if ( bytes == GET_MODE_SIZE ( QImode ) ) return QImode ; else if ( bytes < GET_MODE_SIZE ( SImode ) && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( HImode ) ) return HImode ; return QImode ; } </s>

Select the mode to be used for reading the next chunk of bytes in the compare . OFFSET is the current read offset from the beginning of the block . BYTES is the number of bytes remaining to be read . ALIGN is the minimum alignment of the memory blocks being compared in bytes .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> static bool classof ( const MipsMCSymbolRefExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> int ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= 32 ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return 0 ; } return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> unsigned ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { if ( ! ArgTy -> isVectorTy ( ) ) return DL . getABITypeAlignment ( ArgTy ) ; return std :: min ( DL . getABITypeAlignment ( ArgTy ) , ( unsigned ) DL . getStackAlignment ( ) . value ( ) ) ; } </s>

Return the correct alignment for the current calling convention .


"%qE attribute only applies to functions"

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


<s> static bool isConstantSplat ( SDValue Op , APInt & SplatVal ) { APInt UndefElts ; SmallVector < APInt , 16 > EltBits ; if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , false ) ) { int SplatIndex = - 1 ; for ( int i = 0 , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) continue ; if ( 0 <= SplatIndex && EltBits [ i ] != EltBits [ SplatIndex ] ) { SplatIndex = - 1 ; break ; } SplatIndex = i ; } if ( 0 <= SplatIndex ) { SplatVal = EltBits [ SplatIndex ] ; return true ; } } return false ; } </s>

Check if this is a constant splat , and if so , find the smallest element size that splats the vector .


<s> DecodeStatus ARM64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { CommentStream = & cs ; uint8_t bytes [ 4 ] ; Size = 0 ; if ( Region . readBytes ( Address , 4 , ( uint8_t * ) bytes ) == - 1 ) return Fail ; Size = 4 ; uint32_t insn = ( bytes [ 3 ] << 24 ) | ( bytes [ 2 ] << 16 ) | ( bytes [ 1 ] << 8 ) | ( bytes [ 0 ] << 0 ) ; return decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return NULL ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> static rtx ia64_single_set ( rtx_insn * insn ) { rtx x = PATTERN ( insn ) , ret ; if ( GET_CODE ( x ) == COND_EXEC ) x = COND_EXEC_CODE ( x ) ; if ( GET_CODE ( x ) == SET ) return x ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_prologue_allocate_stack : case CODE_FOR_prologue_allocate_stack_pr : case CODE_FOR_epilogue_deallocate_stack : case CODE_FOR_epilogue_deallocate_stack_pr : ret = XVECEXP ( x , 0 , 0 ) ; break ; default : ret = single_set_2 ( insn , x ) ; break ; } return ret ; } </s>

Helper function - like single_set , but look inside COND_EXEC .


<s> EVT ARM64TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; auto IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IDVal == ".cfi_negate_ra_state" ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == ".cfi_b_key_frame" ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == ".arch_extension" ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( auto & MI : MBB ) { if ( ! hasTOCLoReloc ( MI ) ) continue ; MI . addOperand ( MachineOperand :: CreateReg ( PPC :: X2 , false , true ) ) ; Changed = true ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


Return a nonzero value if XINSN is a legitimate address for a memory operand of the indicated MODE . STRICT is nonzero if this function is called during reload .


<s>
bool
WinEHStatePass
::
runOnFunction
(
Function
&
F
)
{
StringRef
WinEHParentName
=
F
.
getFnAttribute
(
"wineh-parent"
)
.
getValueAsString
(
)
;
if
(
WinEHParentName
!=
F
.
getName
(
)
&&
!
WinEHParentName
.
empty
(
)
)
return
false
;
if
(
!
F
.
hasPersonalityFn
(
)
)
return
false
;
PersonalityFn
=
dyn_cast
<
Function
>
(
F
.
getPersonalityFn
(
)
->
stripPointerCasts
(
)
)
;
if
(
!
PersonalityFn
)
return
false
;
Personality
=
classifyEHPersonality
(
PersonalityFn
)
;
if
(
!
isMSVCEHPersonality
(
Personality
)
)
return
false
;
F
.
addFnAttr
(
"no-frame-pointer-elim"
,
"true"
)
;
emitExceptionRegistrationRecord
(
&
F
)
;
auto
*
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
std
::
unique_ptr
<
WinEHFuncInfo
>
FuncInfoPtr
;
if
(
!
MMI
)
FuncInfoPtr
.
reset
(
new
WinEHFuncInfo
(
)
)
;
WinEHFuncInfo
&
FuncInfo
=
*
(
MMI
&
MMI
->
getWinEHFuncInfo
(
&
F
)
:
FuncInfoPtr
.
get
(
)
)
;
switch
(
Personality
)
{
default
:
llvm_unreachable
(
"unexpected personality function"
)
;
case
EHPersonality
::
MSVC_CXX
:
addCXXStateStores
(
F
,
FuncInfo
)
;
break
;
case
EHPersonality
::
MSVC_X86SEH
:
addSEHStateStores
(
F
,
FuncInfo
)
;
break
;
}
PersonalityFn
=
nullptr
;
Personality
=
EHPersonality
::
Unknown
;
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

X86
"wineh-parent"
"no-frame-pointer-elim"
"true"
"unexpected personality function"
X86


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static bool rs6000_is_costly_dependence ( dep_t dep , int cost , int distance ) { rtx insn ; rtx next ; rtx load_mem , str_mem ; if ( rs6000_sched_costly_dep == no_dep_costly ) return false ; if ( rs6000_sched_costly_dep == all_deps_costly ) return true ; insn = DEP_PRO ( dep ) ; next = DEP_CON ( dep ) ; if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) && DEP_TYPE ( dep ) == REG_DEP_TRUE && mem_locations_overlap ( str_mem , load_mem ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return false ; } </s>

Returns whether the dependence between INSN and NEXT is considered costly by the given target .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void rx_copy_reg_dead_or_unused_notes ( rtx reg , const rtx_insn * src , rtx_insn * dst ) { int regno = REGNO ( SUBREG_P ( reg ) ? SUBREG_REG ( reg ) : reg ) ; if ( rtx note = find_regno_note ( src , REG_DEAD , regno ) ) add_shallow_copy_of_reg_note ( dst , note ) ; if ( rtx note = find_regno_note ( src , REG_UNUSED , regno ) ) add_shallow_copy_of_reg_note ( dst , note ) ; } </s>

Copy dead and unused notes from SRC to DST for the specified REGNO .


<s>
bool
IA64AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
F
)
)
;
EmitAlignment
(
5
)
;
O
<<
"\t.global\t"
<<
CurrentFnName
<<
'\n'
;
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.type\t"
<<
CurrentFnName
<<
", @function\n"
;
O
<<
CurrentFnName
<<
":\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
I
->
pred_empty
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static int rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; machine_mode mode = GET_MODE ( dest ) ; enum rtx_code cond_code ; rtx ( * isel_func ) ( rtx , rtx , rtx , rtx , rtx ) ; bool signedp ; if ( mode != SImode && ( ! TARGET_POWERPC64 || mode != DImode ) ) return 0 ; condition_rtx = rs6000_generate_compare ( op , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; cr = XEXP ( condition_rtx , 0 ) ; signedp = GET_MODE ( cr ) == CCmode ; isel_func = ( mode == SImode ? ( signedp ? gen_isel_signed_si : gen_isel_unsigned_si ) : ( signedp ? gen_isel_signed_di : gen_isel_unsigned_di ) ) ; switch ( cond_code ) { case LT : case GT : case LTU : case GTU : case EQ : break ; default : { std :: swap ( false_cond , true_cond ) ; PUT_CODE ( condition_rtx , reverse_condition ( cond_code ) ) ; } break ; } false_cond = force_reg ( mode , false_cond ) ; if ( true_cond != const0_rtx ) true_cond = force_reg ( mode , true_cond ) ; emit_insn ( isel_func ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return 1 ; } </s>


<s>
bool
ARMBaseInstrInfo
::
getInsertSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPair
&
BaseReg
,
RegSubRegPairAndIdx
&
InsertedReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isInsertSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VSETLNi32
:
case
ARM
::
MVE_VMOV_to_lane_32
:
const
MachineOperand
&
MOBaseReg
=
MI
.
getOperand
(
1
)
;
const
MachineOperand
&
MOInsertedReg
=
MI
.
getOperand
(
2
)
;
if
(
MOInsertedReg
.
isUndef
(
)
)
return
false
;
const
MachineOperand
&
MOIndex
=
MI
.
getOperand
(
3
)
;
BaseReg
.
Reg
=
MOBaseReg
.
getReg
(
)
;
BaseReg
.
SubReg
=
MOBaseReg
.
getSubReg
(
)
;
InsertedReg
.
Reg
=
MOInsertedReg
.
getReg
(
)
;
InsertedReg
.
SubReg
=
MOInsertedReg
.
getSubReg
(
)
;
InsertedReg
.
SubIdx
=
ARM
::
ssub_0
+
MOIndex
.
getImm
(
)
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getInsertSubregInputs .


<s> bool ARMBaseInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == ARM :: VORRq && MI . getOperand ( 1 ) . getReg ( ) != MI . getOperand ( 2 ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> void ix86_expand_convert_uns_didf_sse ( rtx target , rtx input ) { REAL_VALUE_TYPE bias_lo_rvt , bias_hi_rvt ; rtx int_xmm , fp_xmm ; rtx biases , exponents ; rtx x ; int_xmm = gen_reg_rtx ( V4SImode ) ; if ( TARGET_INTER_UNIT_MOVES_TO_VEC ) emit_insn ( gen_movdi_to_sse ( int_xmm , input ) ) ; else if ( TARGET_SSE_SPLIT_REGS ) { emit_clobber ( int_xmm ) ; emit_move_insn ( gen_lowpart ( DImode , int_xmm ) , input ) ; } else { x = gen_reg_rtx ( V2DImode ) ; ix86_expand_vector_init_one_nonzero ( false , V2DImode , x , input , 0 ) ; emit_move_insn ( int_xmm , gen_lowpart ( V4SImode , x ) ) ; } x = gen_rtx_CONST_VECTOR ( V4SImode , gen_rtvec ( 4 , GEN_INT ( 0x43300000UL ) , GEN_INT ( 0x45300000UL ) , const0_rtx , const0_rtx ) ) ; exponents = validize_mem ( force_const_mem ( V4SImode , x ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( int_xmm , int_xmm , exponents ) ) ; fp_xmm = copy_to_mode_reg ( V2DFmode , gen_lowpart ( V2DFmode , int_xmm ) ) ; real_ldexp ( & bias_lo_rvt , & dconst1 , 52 ) ; real_ldexp ( & bias_hi_rvt , & dconst1 , 84 ) ; biases = const_double_from_real_value ( bias_lo_rvt , DFmode ) ; x = const_double_from_real_value ( bias_hi_rvt , DFmode ) ; biases = gen_rtx_CONST_VECTOR ( V2DFmode , gen_rtvec ( 2 , biases , x ) ) ; biases = validize_mem ( force_const_mem ( V2DFmode , biases ) ) ; emit_insn ( gen_subv2df3 ( fp_xmm , fp_xmm , biases ) ) ; if ( TARGET_SSE3 ) emit_insn ( gen_sse3_haddv2df3 ( fp_xmm , fp_xmm , fp_xmm ) ) ; else { x = copy_to_mode_reg ( V2DFmode , fp_xmm ) ; emit_insn ( gen_vec_interleave_highv2df ( fp_xmm , fp_xmm , fp_xmm ) ) ; emit_insn ( gen_addv2df3 ( fp_xmm , fp_xmm , x ) ) ; } ix86_expand_vector_extract ( false , target , fp_xmm , 0 ) ; } </s>

Convert an unsigned DImode value into a DFmode , using only SSE . Expects the 64-bit DImode to be supplied in a pair of integral registers . Requires SSE2 ; will use SSE3 if available . For x86_32 , -mfpmath=sse , ! optimize_size only .


<s> bool doMBBSchedRegionsTopDown ( ) const override { return true ; } </s>

If this method returns true , handling of the scheduling regions themselves ( in case of a scheduling boundary in MBB ) will be done beginning with the topmost region of MBB .


<s> bool CSKYAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".csky_attribute" ) return parseDirectiveAttribute ( ) ; return true ; } </s>


<s> unsigned getPointerSize ( ) const { return 8 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> bool TeeRISCPassConfig :: addPreEmitPass ( ) { return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool sh_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( to == SFmode && VECTOR_MODE_P ( from ) && GET_MODE_INNER ( from ) == SFmode ) return optimize ? ( reg_classes_intersect_p ( GENERAL_REGS , rclass ) ) : false ; if ( GET_MODE_SIZE ( from ) != GET_MODE_SIZE ( to ) ) { if ( TARGET_LITTLE_ENDIAN ) { if ( GET_MODE_SIZE ( to ) < 8 || GET_MODE_SIZE ( from ) < 8 ) return reg_classes_intersect_p ( DF_REGS , rclass ) ; } else { if ( GET_MODE_SIZE ( from ) < 8 ) return reg_classes_intersect_p ( DF_REGS , rclass ) ; } } return false ; } </s>

Return the class of registers for which a mode change from FROM to TO is invalid .


<s> rtx expand_builtin ( unsigned int code , tree exp , rtx target ) { registered_function & rfn = * ( * registered_functions ) [ code ] ; if ( ! check_required_extensions ( EXPR_LOCATION ( exp ) , rfn . decl , rfn . required_extensions ) ) return target ; return function_expander ( rfn . instance , rfn . decl , exp , target ) . expand ( ) ; } </s>

Expand a call to the RVV function with subcode CODE . EXP is the call expression and TARGET is the preferred location for the result . Return the value of the lhs .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MVE gather/scatter lowering"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx mark_constant_pool_use ( rtx x ) { rtx insn , lab , pattern ; if ( x == NULL ) return x ; switch ( GET_CODE ( x ) ) { case LABEL_REF : x = XEXP ( x , 0 ) ; case CODE_LABEL : break ; default : return x ; } lab = x ; for ( insn = PREV_INSN ( x ) ; insn ; insn = PREV_INSN ( insn ) ) { if ( GET_CODE ( insn ) != CODE_LABEL || LABEL_REFS ( insn ) != NEXT_INSN ( insn ) ) break ; lab = insn ; } for ( insn = LABEL_REFS ( lab ) ; insn ; insn = LABEL_REFS ( insn ) ) INSN_DELETED_P ( insn ) = 1 ; for ( insn = NEXT_INSN ( x ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) != INSN ) continue ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != UNSPEC_VOLATILE ) continue ; switch ( XINT ( pattern , 1 ) ) { case UNSPECV_CONST2 : case UNSPECV_CONST4 : case UNSPECV_CONST8 : XVECEXP ( pattern , 0 , 1 ) = const1_rtx ; break ; case UNSPECV_WINDOW_END : if ( XVECEXP ( pattern , 0 , 0 ) == x ) return lab ; break ; case UNSPECV_CONST_END : return lab ; default : break ; } } return lab ; } </s>

Mark the use of a constant in the literal table . If the constant has multiple labels , make it unique .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= 16 && ( Op . isAligned ( Align ( 16 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Op . size ( ) >= 8 && ( Op . isAligned ( Align ( 8 ) ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool PPCPassConfig :: addInstSelector ( ) { PM . add ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const char * MandarinTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case MDISD :: RET_FLAG : return "MDISD::RET_FLAG" ; case MDISD :: CMP : return "MDISD::CMP" ; case MDISD :: ICMP : return "MDISD::ICMP" ; case MDISD :: FCMP : return "MDISD::FCMP" ; case MDISD :: BR_CC : return "MDISD::BR_CC" ; case MDISD :: SELECT_CC : return "MDISD::SELECT_CC" ; case MDISD :: HIGH : return "MDISD::HIGH" ; case MDISD :: LOW : return "MDISD::LOW" ; case MDISD :: CALL : return "MDISD::CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


Return an array that contains the MMO target flag values and their names .


<s> static int ix86_i387_mode_needed ( int entity , rtx_insn * insn ) { enum attr_i387_cw mode ; if ( CALL_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && ( asm_noperands ( PATTERN ( insn ) ) >= 0 || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) ) ) return I387_CW_UNINITIALIZED ; if ( recog_memoized ( insn ) < 0 ) return I387_CW_ANY ; mode = get_attr_i387_cw ( insn ) ; switch ( entity ) { case I387_ROUNDEVEN : if ( mode == I387_CW_ROUNDEVEN ) return mode ; break ; case I387_TRUNC : if ( mode == I387_CW_TRUNC ) return mode ; break ; case I387_FLOOR : if ( mode == I387_CW_FLOOR ) return mode ; break ; case I387_CEIL : if ( mode == I387_CW_CEIL ) return mode ; break ; default : gcc_unreachable ( ) ; } return I387_CW_ANY ; } </s>

Return mode that i387 must be switched into prior to the execution of insn .


"The ABI for passing parameters with %d-byte"

Gives the alignment boundary , in bits , of an argument with the specified mode and type .


<s> void aarch64_expand_call ( rtx result , rtx mem , bool sibcall ) { rtx call , callee , tmp ; rtvec vec ; machine_mode mode ; gcc_assert ( MEM_P ( mem ) ) ; callee = XEXP ( mem , 0 ) ; mode = GET_MODE ( callee ) ; gcc_assert ( mode == Pmode ) ; if ( SYMBOL_REF_P ( callee ) ? ( aarch64_is_long_call_p ( callee ) || aarch64_is_noplt_call_p ( callee ) ) : ! REG_P ( callee ) ) XEXP ( mem , 0 ) = force_reg ( mode , callee ) ; call = gen_rtx_CALL ( VOIDmode , mem , const0_rtx ) ; if ( result != NULL_RTX ) call = gen_rtx_SET ( result , call ) ; if ( sibcall ) tmp = ret_rtx ; else tmp = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; vec = gen_rtvec ( 2 , call , tmp ) ; call = gen_rtx_PARALLEL ( VOIDmode , vec ) ; aarch64_emit_call_insn ( call ) ; } </s>

This function is used by the call expanders of the machine description . RESULT is the register in which the result is returned . It 's NULL for `` call '' and `` sibcall '' . MEM is the location of the function call . SIBCALL indicates whether this function call is normal call or sibling call . It will generate different pattern accordingly .


<s> static unsigned estimateStackSize ( MachineFunction & MF ) { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; int Offset = 0 ; for ( int i = FFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - FFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = FFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( FFI -> isDeadObjectIndex ( i ) ) continue ; Offset += FFI -> getObjectSize ( i ) ; unsigned Align = FFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; } return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < EdgeBundles > ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86WinAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; assert ( SlotSize == 4 || SlotSize == 8 ) ; unsigned RegA = ( SlotSize == 8 ) ? X86 :: RAX : X86 :: EAX ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: SUB64rr : X86 :: SUB32rr ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; } break ; } unsigned AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; for ( ; ; ) { if ( ! MRI -> use_empty ( AmountReg ) ) break ; MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ; if ( ! AmountDef ) break ; if ( AmountDef -> isCopy ( ) && AmountDef -> getOperand ( 1 ) . isReg ( ) ) AmountReg = AmountDef -> getOperand ( 1 ) . isReg ( ) ; AmountDef -> eraseFromParent ( ) ; break ; } } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> const AArch64InstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return NumRegisters ; } if ( VT == MVT :: v3f16 && Subtarget . hasFP16 ( ) ) return 1 ; if ( ! Subtarget . is64Bit ( ) && ! Subtarget . hasX87 ( ) ) { if ( VT == MVT :: f64 ) return 2 ; if ( VT == MVT :: f80 ) return 3 ; } return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static int insert_bundle_state ( struct bundle_state * bundle_state ) { struct bundle_state * * entry_ptr ; entry_ptr = bundle_state_table -> find_slot ( bundle_state , INSERT ) ; if ( * entry_ptr == NULL ) { bundle_state -> next = index_to_bundle_states [ bundle_state -> insn_num ] ; index_to_bundle_states [ bundle_state -> insn_num ] = bundle_state ; * entry_ptr = bundle_state ; return TRUE ; } else if ( bundle_state -> cost < ( * entry_ptr ) -> cost || ( bundle_state -> cost == ( * entry_ptr ) -> cost && ( ( * entry_ptr ) -> accumulated_insns_num > bundle_state -> accumulated_insns_num || ( ( * entry_ptr ) -> accumulated_insns_num == bundle_state -> accumulated_insns_num && ( ( * entry_ptr ) -> branch_deviation > bundle_state -> branch_deviation || ( ( * entry_ptr ) -> branch_deviation == bundle_state -> branch_deviation && ( * entry_ptr ) -> middle_bundle_stops > bundle_state -> middle_bundle_stops ) ) ) ) ) ) { struct bundle_state temp ; temp = * * entry_ptr ; * * entry_ptr = * bundle_state ; ( * entry_ptr ) -> next = temp . next ; * bundle_state = temp ; } return FALSE ; } </s>

The function inserts the BUNDLE_STATE into the hash table . The function returns nonzero if the bundle has been inserted into the table . The table contains the best bundle state with given key .