<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; const Module * M = MF . getMMI ( ) . getModule ( ) ; Metadata * isCFProtectionSupported = M -> getModuleFlag ( "cf-protection-branch" ) ; const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( needsPrologueENDBR ( MF , M ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && I -> getNumOperands ( ) > 0 && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( 0 ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isEHLabel ( ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCQPXLoadSplat :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; bool MadeChange = false ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( auto MFI = MF . begin ( ) , MFIE = MF . end ( ) ; MFI != MFIE ; ++ MFI ) { MachineBasicBlock * MBB = & * MFI ; SmallVector < MachineInstr * , 4 > Splats ; for ( auto MBBI = MBB -> rbegin ( ) ; MBBI != MBB -> rend ( ) ; ++ MBBI ) { MachineInstr * MI = & * MBBI ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isCall ( ) ) { Splats . clear ( ) ; continue ; } for ( auto SI = Splats . begin ( ) ; SI != Splats . end ( ) ; ) { MachineInstr * SMI = * SI ; unsigned SplatReg = SMI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = SMI -> getOperand ( 1 ) . getReg ( ) ; if ( MI -> modifiesRegister ( SrcReg , TRI ) ) { switch ( MI -> getOpcode ( ) ) { default : SI = Splats . erase ( SI ) ; continue ; case PPC :: LFS : case PPC :: LFD : case PPC :: LFSU : case PPC :: LFDU : case PPC :: LFSUX : case PPC :: LFDUX : case PPC :: LFSX : case PPC :: LFDX : case PPC :: LFIWAX : case PPC :: LFIWZX : if ( SplatReg != SrcReg ) { unsigned SubRegIndex = TRI -> getSubRegIndex ( SrcReg , MI -> getOperand ( 0 ) . getReg ( ) ) ; unsigned SplatSubReg = TRI -> getSubReg ( SplatReg , SubRegIndex ) ; MI -> getOperand ( 0 ) . setReg ( SplatSubReg ) ; MI -> substituteRegister ( SrcReg , SplatReg , 0 , * TRI ) ; } SI = Splats . erase ( SI ) ; ++ MBBI ; SMI -> eraseFromParent ( ) ; -- MBBI ; ++ NumSimplified ; MadeChange = true ; continue ; } } if ( MI -> modifiesRegister ( SplatReg , TRI ) || ( SrcReg != SplatReg && MI -> readsRegister ( SplatReg , TRI ) ) ) { SI = Splats . erase ( SI ) ; continue ; } ++ SI ; } if ( MI -> getOpcode ( ) != PPC :: QVESPLATI && MI -> getOpcode ( ) != PPC :: QVESPLATIs && MI -> getOpcode ( ) != PPC :: QVESPLATIb ) continue ; if ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) continue ; if ( ! MI -> getOperand ( 1 ) . isKill ( ) ) continue ; Splats . push_back ( MI ) ; } } return MadeChange ; } </s>


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { ArgIsFixed . clear ( ) ; for ( unsigned i = 0 ; i < Outs . size ( ) ; ++ i ) ArgIsFixed . push_back ( Outs [ i ] . IsFixed ) ; ArgIsShortVector . clear ( ) ; for ( unsigned i = 0 ; i < Outs . size ( ) ; ++ i ) ArgIsShortVector . push_back ( IsShortVectorType ( Outs [ i ] . ArgVT ) ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> static void mips_df_reorg ( void ) { df_set_flags ( DF_EQ_NOTES ) ; df_chain_add_problem ( DF_UD_CHAIN ) ; df_analyze ( ) ; if ( TARGET_RELAX_PIC_CALLS ) mips_annotate_pic_calls ( ) ; if ( mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE ) r10k_insert_cache_barriers ( ) ; df_finish_pass ( false ) ; } </s>

Subroutine of mips_reorg to manage passes that require DF .


<s> SMLoc getLoc ( ) const { return Parser . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> static rtx load_cr_save ( int regno , rtx frame_reg_rtx , int offset , bool exit_func ) { rtx mem = gen_frame_mem_offset ( SImode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx_insn * insn = emit_move_insn ( reg , mem ) ; if ( ! exit_func && DEFAULT_ABI == ABI_V4 ) { rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; rtx set = gen_rtx_SET ( reg , cr ) ; add_reg_note ( insn , REG_CFA_REGISTER , set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return reg ; } </s>

Restoring cr is a two step process : loading a reg from the frame save , then moving the reg to cr . For ABI_V4 we must let the unwinder know that the stack location is no longer valid at or before the stack deallocation , but we ca n't emit a cfa_restore for cr at the stack deallocation like we do for other registers . The trouble is that it is possible for the move to cr to be scheduled after the stack deallocation . So say exactly where cr is located on each of the two insns .


"internal error in %s, at %s:%d: %s: %s\n"

Print out the GetLastError ( ) translation .


<s> const CAHPInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
void
SystemZHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
const
MCSchedClassDesc
*
SC
=
DAG
->
getSchedClass
(
SU
)
;
DEBUG
(
dumpCurrGroup
(
"Decode group before emission"
)
;
)
;
if
(
!
fitsIntoCurrentGroup
(
SU
)
)
nextGroup
(
)
;
DEBUG
(
dbgs
(
)
<<
"+++ HazardRecognizer emitting "
;
dumpSU
(
SU
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
raw_string_ostream
cgd
(
CurGroupDbg
)
;
if
(
CurGroupDbg
.
length
(
)
)
cgd
<<
", "
;
dumpSU
(
SU
,
cgd
)
;
)
;
if
(
SU
->
getInstr
(
)
->
isCall
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Clearing state after call.\n"
;
)
;
clearProcResCounters
(
)
;
LastFPdOpCycleIdx
=
UINT_MAX
;
CurrGroupSize
+=
getNumDecoderSlots
(
SU
)
;
assert
(
CurrGroupSize
<=
3
)
;
nextGroup
(
)
;
return
;
}
for
(
TargetSchedModel
::
ProcResIter
PI
=
SchedModel
->
getWriteProcResBegin
(
SC
)
,
PE
=
SchedModel
->
getWriteProcResEnd
(
SC
)
;
PI
!=
PE
;
++
PI
)
{
if
(
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
BufferSize
==
1
)
continue
;
int
&
CurrCounter
=
ProcResourceCounters
[
PI
->
ProcResourceIdx
]
;
CurrCounter
+=
PI
->
Cycles
;
if
(
(
CurrCounter
>
ProcResCostLim
)
&&
(
CriticalResourceIdx
==
UINT_MAX
||
(
PI
->
ProcResourceIdx
!=
CriticalResourceIdx
&&
CurrCounter
>
ProcResourceCounters
[
CriticalResourceIdx
]
)
)
)
{
DEBUG
(
dbgs
(
)
<<
"+++ New critical resource: "
<<
SchedModel
->
getProcResource
(
PI
->
ProcResourceIdx
)
->
Name
<<
"\n"
;
)
;
CriticalResourceIdx
=
PI
->
ProcResourceIdx
;
}
}
if
(
SU
->
isUnbuffered
)
{
LastFPdOpCycleIdx
=
getCurrCycleIdx
(
)
;
DEBUG
(
dbgs
(
)
<<
"+++ Last FPd cycle index: "
<<
LastFPdOpCycleIdx
<<
"\n"
;
)
;
}
CurrGroupSize
+=
getNumDecoderSlots
(
SU
)
;
assert
(
CurrGroupSize
<=
3
)
;
if
(
CurrGroupSize
==
3
||
SC
->
EndGroup
)
nextGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

SystemZ
SystemZ
"Decode group before emission"
"+++ HazardRecognizer emitting "
"\n"
", "
"+++ Clearing state after call.\n"
3
1
"+++ New critical resource: "
"\n"
"+++ Last FPd cycle index: "
"\n"
3
3


<s> bool ARM64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? ARM64 :: WZR : ARM64 :: XZR ; O << ARM64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & ARM64 :: FPR8RegClass ; break ; case 'h' : RC = & ARM64 :: FPR16RegClass ; break ; case 's' : RC = & ARM64 :: FPR32RegClass ; break ; case 'd' : RC = & ARM64 :: FPR64RegClass ; break ; case 'q' : RC = & ARM64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( ARM64 :: GPR32allRegClass . contains ( Reg ) || ARM64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & ARM64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
SDValue
Base
,
Offset
,
Opc
;
if
(
!
SelectAddrMode2
(
Op
,
Op
,
Base
,
Offset
,
Opc
)
)
return
true
;
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
OutOps
.
push_back
(
Opc
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"unexpected asm memory constraint"


<s> SDValue AArch64TargetLowering :: getGOT ( NodeTy * N , SelectionDAG & DAG ) const { DEBUG ( dbgs ( ) << "AArch64TargetLowering::getGOT\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty , DAG , AArch64II :: MO_GOT ) ; return DAG . getNode ( AArch64ISD :: LOADgot , DL , Ty , GotAddr ) ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 64 && Subtarget . hasAVX512 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 512 ) ) { return Subtarget . hasBWI ( ) ? MVT :: v64i8 : MVT :: v16i32 ; } if ( Size >= 32 && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 256 ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= 128 ) ) return MVT :: v4f32 ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : case ISD :: INLINEASM_BR : { if ( tryInlineAsm ( N ) ) return ; break ; } case SPISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; return ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool aarch64_pad_reg_upward ( machine_mode mode , const_tree type , bool first ATTRIBUTE_UNUSED ) { if ( BYTES_BIG_ENDIAN && aarch64_composite_type_p ( type , mode ) ) { HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( size < 2 * UNITS_PER_WORD ) { pure_scalable_type_info pst_info ; if ( pst_info . analyze_registers ( type ) ) return false ; return true ; } } return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . It specifies padding for the last ( may also be the only ) element of a block move between registers and memory . If assuming the block is in the memory , padding upward means that the last element is padded after its highest significant byte , while in downward padding , the last element is padded at the its least significant byte side . Small aggregates and small complex types are always padded upwards . We do n't need to worry about homogeneous floating-point or short-vector aggregates ; their move is not affected by the padding direction determined here . Regardless of endianness , each element of such an aggregate is put in the least significant bits of a fp/simd register . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does .


<s> bool aarch64_sve_ld1rq_operand_p ( rtx op ) { return aarch64_sve_ld1rq_ld1ro_operand_p ( op , TImode , GET_MODE_INNER ( GET_MODE ( op ) ) ) ; } </s>

Return true if OP is a valid MEM operand for an SVE LD1RQ instruction .


<s> void ARMWinCOFFStreamer :: emitThumbFunc ( MCSymbol * Symbol ) { getAssembler ( ) . setIsThumbFunc ( Symbol ) ; } </s>

Note in the output that the specified Func is a Thumb mode function ( ARM target only ) .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
unsigned
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static bool virt_or_elim_regno_p ( unsigned regno ) { return ( ( regno >= FIRST_VIRTUAL_REGISTER && regno <= LAST_VIRTUAL_POINTER_REGISTER ) || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return true if REGNO is a virtual pointer register , or an eliminable `` soft '' frame register . Like REGNO_PTR_FRAME_P except that we do n't include stack_pointer or hard_frame_pointer .


<s> static void rs6000_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( first + size <= 32768 ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx r0 = gen_rtx_REG ( Pmode , 0 ) ; gcc_assert ( first <= 32768 ) ; rounded_size = size & - PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( VOIDmode , r12 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > 32768 ) { emit_move_insn ( r0 , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , r0 , gen_rtx_PLUS ( Pmode , r12 , r0 ) ) ) ; } else emit_insn ( gen_rtx_SET ( VOIDmode , r0 , plus_constant ( Pmode , r12 , - rounded_size ) ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_probe_stack_rangedi ( r12 , r12 , r0 ) ) ; else emit_insn ( gen_probe_stack_rangesi ( r12 , r12 , r0 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; } } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> bool ARMBaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const ARMFunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


"Intrinsic instructions can't commute operand 1"

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = IsLittleEndian ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void mips16_lay_out_constants ( void ) { struct mips16_constant_pool pool ; rtx insn , barrier ; barrier = 0 ; memset ( & pool , 0 , sizeof ( pool ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) for_each_rtx ( & PATTERN ( insn ) , mips16_rewrite_pool_refs , & pool ) ; pool . insn_address += mips16_insn_length ( insn ) ; if ( pool . first != NULL ) { if ( barrier == 0 && pool . insn_address + 4 > pool . highest_address ) { rtx label , jump ; label = gen_label_rtx ( ) ; jump = emit_jump_insn_before ( gen_jump ( label ) , insn ) ; JUMP_LABEL ( jump ) = label ; LABEL_NUSES ( label ) = 1 ; barrier = emit_barrier_after ( jump ) ; emit_label_after ( label , barrier ) ; pool . insn_address += 4 ; } if ( pool . insn_address > pool . highest_address ) { dump_constants ( pool . first , barrier ) ; pool . first = NULL ; barrier = 0 ; } else if ( BARRIER_P ( insn ) ) barrier = insn ; } } dump_constants ( pool . first , get_last_insn ( ) ) ; } </s>


<s> static bool aarch64_vector_mode_p ( machine_mode mode ) { return aarch64_vector_mode_supported_p ( mode ) || aarch64_vect_struct_mode_p ( mode ) ; } </s>

Return TRUE if MODE is any of the vector modes .


<s>
static
bool
Check
(
DecodeStatus
&
Out
,
DecodeStatus
In
)
{
switch
(
In
)
{
case
MCDisassembler
::
Success
:
return
true
;
case
MCDisassembler
::
SoftFail
:
Out
=
In
;
return
true
;
case
MCDisassembler
::
Fail
:
Out
=
In
;
return
false
;
}
llvm_unreachable
(
"Invalid DecodeStatus!"
)
;
}
</s>

Matches check string and its `` not strings '' and/or `` dag strings '' .


"AArch64 FastISel doesn't support types larger than i64"

This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the given getelementptr index value .


<s> static reg_class_t mmix_preferred_output_reload_class ( rtx x , reg_class_t rclass ) { return GET_CODE ( x ) == MOD && GET_MODE ( x ) == DImode ? REMAINDER_REG : rclass ; } </s>

PREFERRED_OUTPUT_RELOAD_CLASS . We need to extend the reload class of REMAINDER_REG and HIMULT_REG .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static MipsABIInfo Unknown ( ) { return MipsABIInfo ( ABI :: Unknown ) ; } </s>

The kind of location description being produced . More ...


<s> static rtx loongarch_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx base , addr ; HOST_WIDE_INT offset ; if ( loongarch_tls_symbol_p ( x ) ) return loongarch_legitimize_tls_address ( x ) ; if ( loongarch_split_symbol ( NULL , x , mode , & addr ) ) return loongarch_force_address ( addr , mode ) ; loongarch_split_plus ( x , & base , & offset ) ; if ( offset != 0 ) { if ( ! loongarch_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = loongarch_add_offset ( NULL , base , offset ) ; return loongarch_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If X can be legitimized in a way that the generic machinery might not expect , return a new address , otherwise return NULL . MODE is the mode of the memory being accessed .


<s> bool ARMSubtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return true ; if ( isTargetMachO ( ) && TM . isPositionIndependent ( ) && ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) ) return true ; return false ; } </s>

True if the GV will be accessed via an indirect symbol .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) || Subtarget -> outlineAtomics ( ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: None ; unsigned Size = AI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 64 ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> static void aarch64_expand_builtin_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { const CUMULATIVE_ARGS * cum ; tree f_stack , f_grtop , f_vrtop , f_groff , f_vroff ; tree stack , grtop , vrtop , groff , vroff ; tree t ; int gr_save_area_size = cfun -> va_list_gpr_size ; int vr_save_area_size = cfun -> va_list_fpr_size ; int vr_offset ; cum = & crtl -> args . info ; if ( cfun -> va_list_gpr_size ) gr_save_area_size = MIN ( ( NUM_ARG_REGS - cum -> aapcs_ncrn ) * UNITS_PER_WORD , cfun -> va_list_gpr_size ) ; if ( cfun -> va_list_fpr_size ) vr_save_area_size = MIN ( ( NUM_FP_ARG_REGS - cum -> aapcs_nvrn ) * UNITS_PER_VREG , cfun -> va_list_fpr_size ) ; if ( ! TARGET_FLOAT ) { gcc_assert ( cum -> aapcs_nvrn == 0 ) ; vr_save_area_size = 0 ; } f_stack = TYPE_FIELDS ( va_list_type_node ) ; f_grtop = DECL_CHAIN ( f_stack ) ; f_vrtop = DECL_CHAIN ( f_grtop ) ; f_groff = DECL_CHAIN ( f_vrtop ) ; f_vroff = DECL_CHAIN ( f_groff ) ; stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_stack ) , valist , f_stack , NULL_TREE ) ; grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist , f_vroff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( stack ) , virtual_incoming_args_rtx ) ; if ( cum -> aapcs_stack_size > 0 ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = ROUND_UP ( gr_save_area_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( vr_offset ) t = fold_build_pointer_plus_hwi ( t , - vr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vrtop ) , vrtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( groff ) , groff , build_int_cst ( TREE_TYPE ( groff ) , - gr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vroff ) , vroff , build_int_cst ( TREE_TYPE ( vroff ) , - vr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
uint64_t
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
{
uint64_t
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
SystemZMnemonicSpellCheck
(
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
SystemZOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void PPCAIXAsmPrinter :: SetupMachineFunction ( MachineFunction & MF ) { CurrentFnDescSym = getSymbol ( & MF . getFunction ( ) ) ; MCSectionXCOFF * FnDescSec = OutStreamer -> getContext ( ) . getXCOFFSection ( CurrentFnDescSym -> getName ( ) , XCOFF :: XMC_DS , XCOFF :: XTY_SD , XCOFF :: C_HIDEXT , SectionKind :: getData ( ) ) ; cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> setContainingCsect ( FnDescSec ) ; return AsmPrinter :: SetupMachineFunction ( MF ) ; } </s>

This should be called when a new MachineFunction is being processed from runOnMachineFunction .


<s> bool ShouldShrinkFPConstant ( EVT VT ) const override { return VT != MVT :: f64 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) && Accesses . size ( ) == 1 ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> bool TOYRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> SDValue SystemZTargetLowering :: prepareVolatileOrAtomicLoad ( SDValue Chain , SDLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( SystemZISD :: SERIALIZE , DL , MVT :: Other , Chain ) ; } </s>

This callback is used to prepare for a volatile or atomic load .

SystemZ SystemZ SystemZISD::SERIALIZE MVT::Other


<s> bool Mips16RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool sh_movsf_ie_ra_split_p ( rtx op0 , rtx op1 , rtx op2 ) { if ( rtx_equal_p ( op0 , op1 ) ) return true ; if ( GET_CODE ( op1 ) == CONST_DOUBLE && ! satisfies_constraint_G ( op1 ) && ! satisfies_constraint_H ( op1 ) && REG_P ( op0 ) && REG_P ( op2 ) ) return true ; if ( REG_P ( op0 ) && FP_REGISTER_P ( REGNO ( op0 ) ) && REG_P ( op1 ) && GENERAL_REGISTER_P ( REGNO ( op1 ) ) && REG_P ( op2 ) && ( REGNO ( op2 ) == FPUL_REG ) ) return true ; if ( REG_P ( op1 ) && FP_REGISTER_P ( REGNO ( op1 ) ) && REG_P ( op0 ) && GENERAL_REGISTER_P ( REGNO ( op0 ) ) && REG_P ( op2 ) && ( REGNO ( op2 ) == FPUL_REG ) ) return true ; return false ; } </s>

Return true if movsf insn should be splited with an additional register .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . hasVSX ( ) ) { if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass


<s> static bool moxie_function_value_regno_p ( const unsigned int regno ) { return ( regno == MOXIE_R0 ) ; } </s>

Handle TARGET_FUNCTION_VALUE_REGNO_P . We always return values in register $ r0 for moxie .


<s>
bool
X86FrameLowering
::
canUseAsPrologue
(
const
MachineBasicBlock
&
MBB
)
const
{
assert
(
MBB
.
getParent
(
)
&&
"Block is not attached to a function!"
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
if
(
!
MBB
.
isLiveIn
(
X86
::
EFLAGS
)
)
return
true
;
const
X86MachineFunctionInfo
*
X86FI
=
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
return
!
TRI
->
hasStackRealignment
(
MF
)
&&
!
X86FI
->
hasSwiftAsyncContext
(
)
;
}
</s>

Check whether or not the given MBB can be used as a prologue for the target .


"Can only insert epilog into returning blocks"


<s> ScheduleHazardRecognizer :: HazardType SystemZHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { return ( fitsIntoCurrentGroup ( SU ) ? NoHazard : Hazard ) ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> void ARMBaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? 2 : 0 ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? ARM :: tTAILJMPr : ARM :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ; } ; if ( std :: any_of ( MBB . instr_begin ( ) , MBB . instr_end ( ) , IsNonTailCall ) ) { MachineBasicBlock :: iterator It = MBB . begin ( ) ; MachineBasicBlock :: iterator Et = MBB . end ( ) ; if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) Et = std :: prev ( MBB . end ( ) ) ; if ( ! MBB . isLiveIn ( ARM :: LR ) ) MBB . addLiveIn ( ARM :: LR ) ; saveLROnStack ( MBB , It ) ; unsigned StackAlignment = Subtarget . getStackAlignment ( ) . value ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( ARM :: LR , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackAlignment ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( ARM :: CFI_INSTRUCTION ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , StackAlignment ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( ARM :: CFI_INSTRUCTION ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; restoreLRFromStack ( MBB , Et ) ; } if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) return ; BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

Insert a custom frame for outlined functions .

ARM ARM 2 0 ARM::tTAILJMPr ARM::TAILJMPr ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL ARM::LR ARM::LR ARM::LR ARM::CFI_INSTRUCTION ARM::CFI_INSTRUCTION ARMCC::AL


"ARMHWLoops: Trip count does not fit into 32bits\n"

Query the target whether it would be profitable to convert the given loop into a hardware loop .


"Blocked load and store instructions: \n"

runOnMachineFunction - Emit the function body .


<s>
const
char
*
rs6000_insn_for_insert_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
3
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
TARGET_POWERPC64
&&
(
!
dot
||
mode
==
DImode
)
&&
GET_CODE
(
operands
[
4
]
)
!=
LSHIFTRT
&&
ne
==
INTVAL
(
operands
[
2
]
)
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rldimi. %0,%1,%2,%3"
;
return
"rldimi %0,%1,%2,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
32
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlwimi. %0,%1,%2,%3,%4"
;
return
"rlwimi %0,%1,%2,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for an insert with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


<s> static inline void aarch64_sub_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool frame_related_p , bool emit_move_imm = true ) { aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta , temp1 , temp2 , frame_related_p , emit_move_imm ) ; } </s>

Subtract DELTA from the stack pointer , marking the instructions frame-related if FRAME_RELATED_P . TEMP1 is available as a temporary if nonnull .


<s> bool ARMBaseInstrInfo :: isTailCall ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case ARM :: TAILJMPd : case ARM :: TAILJMPr : case ARM :: TCRETURNdi : case ARM :: TCRETURNri : return true ; default : return false ; } } </s>

Determines whether Inst is a tail call instruction .

ARM ARM ARM::TAILJMPd ARM::TAILJMPr ARM::TCRETURNdi ARM::TCRETURNri


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || Constraint == "ws" || Constraint == "wi" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .

PowerPC PPC PPC 1 0 "wc" "wa" "wd" "wf" "ws" "wi"


<s> bool PPCPassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; if ( EnableMachineCombinerPass ) addPass ( & MachineCombinerID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> void from_compare ( rtx * operands , int code ) { enum machine_mode mode = GET_MODE ( sh_compare_op0 ) ; rtx insn ; if ( mode == VOIDmode ) mode = GET_MODE ( sh_compare_op1 ) ; if ( code != EQ || mode == DImode || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) { sh_compare_op0 = force_reg ( mode , sh_compare_op0 ) ; if ( sh_compare_op1 != const0_rtx || code == GTU || code == GEU || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) sh_compare_op1 = force_reg ( mode , sh_compare_op1 ) ; } if ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT && code == GE ) { from_compare ( operands , GT ) ; insn = gen_ieee_ccmpeqsf_t ( sh_compare_op0 , sh_compare_op1 ) ; } else insn = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , T_REG ) , gen_rtx_fmt_ee ( code , SImode , sh_compare_op0 , sh_compare_op1 ) ) ; if ( ( TARGET_SH4 || TARGET_SH2A ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , insn , gen_rtx_USE ( VOIDmode , get_fpscr_rtx ( ) ) ) ) ; ( mode == SFmode ? emit_sf_insn : emit_df_insn ) ( insn ) ; } else emit_insn ( insn ) ; } </s>

Called from the md file , set up the operands of a compare instruction .


Implement target hook libgcc_floating_mode_supported_p .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
Size
=
(
getFixupKindInfo
(
Kind
)
.
TargetSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
cpu
=
;
char
*
ret
=
;
char
buf
[
128
]
;
FILE
*
f
;
bool
arch
;
if
(
argc
<
1
)
return
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
return
;
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
fallback_cpu
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
if
(
startswith
(
buf
,
"cpu model"
)
)
{
if
(
strstr
(
buf
,
"Godson2 V0.2"
)
!=
||
strstr
(
buf
,
"Loongson-2 V0.2"
)
!=
||
strstr
(
buf
,
"Loongson-2E"
)
!=
)
cpu
=
"loongson2e"
;
else
if
(
strstr
(
buf
,
"Godson2 V0.3"
)
!=
||
strstr
(
buf
,
"Loongson-2 V0.3"
)
!=
||
strstr
(
buf
,
"Loongson-2F"
)
!=
)
cpu
=
"loongson2f"
;
else
if
(
strstr
(
buf
,
"Godson3 V0.5"
)
!=
||
strstr
(
buf
,
"Loongson-3 V0.5"
)
!=
||
strstr
(
buf
,
"Loongson-3A"
)
!=
)
cpu
=
"loongson3a"
;
else
if
(
strstr
(
buf
,
"SiByte SB1"
)
!=
)
cpu
=
"sb1"
;
else
if
(
strstr
(
buf
,
"R5000"
)
!=
)
cpu
=
"r5000"
;
else
if
(
strstr
(
buf
,
"Octeon II"
)
!=
)
cpu
=
"octeon2"
;
else
if
(
strstr
(
buf
,
"Octeon"
)
!=
)
cpu
=
"octeon"
;
break
;
}
fclose
(
f
)
;
fallback_cpu
:
ret
=
reconcat
(
ret
,
" -mnan=2008 "
,
)
;
if
(
cpu
==
)
cpu
=
(
const
char
*
)
getauxval
(
AT_BASE_PLATFORM
)
;
if
(
cpu
==
)
cpu
=
_MIPS_ARCH
;
if
(
cpu
)
ret
=
reconcat
(
ret
,
ret
,
"-m"
,
argv
[
0
]
,
"="
,
cpu
,
)
;
return
ret
;
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> bool fusion_p9_p ( rtx addis_reg , rtx addis_value , rtx dest , rtx src ) { rtx addr , mem , offset ; enum machine_mode mode = GET_MODE ( src ) ; if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( src ) == FLOAT_EXTEND || GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , 0 ) ; if ( fpr_reg_operand ( src , mode ) || int_reg_operand ( src , mode ) ) { if ( ! MEM_P ( dest ) ) return false ; mem = dest ; } else if ( MEM_P ( src ) ) { if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , 1 ) ) ; } else if ( GET_CODE ( addr ) == LO_SUM ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; offset = XEXP ( addr , 1 ) ; if ( TARGET_XCOFF || ( TARGET_ELF && TARGET_POWERPC64 ) ) return small_toc_ref ( offset , GET_MODE ( offset ) ) ; else if ( TARGET_ELF && ! TARGET_POWERPC64 ) return CONSTANT_P ( offset ) ; } return false ; } </s>

Return true if the peephole2 can combine a load/store involving a combination of an addis instruction and the memory operation . This was added to the ISA 3.0 ( power9 ) hardware .


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: TAILJMPd64 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool CheckReturn ( const SmallVectorImpl < ISD :: OutputArg > & ArgsFlags , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( ArgsFlags ) ; PreAnalyzeReturnForVectorFloat ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear ( ) ; return Return ; } </s>

CheckReturn - Analyze the return values of a function , returning true if the return can be performed without sret-demotion , and false otherwise .


<s> outliner :: TargetCostInfo X86InstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { unsigned SequenceSize = std :: accumulate ( RepeatedSequenceLocs [ 0 ] . front ( ) , std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) , 0 , [ ] ( unsigned Sum , const MachineInstr & MI ) { if ( MI . isDebugInstr ( ) || MI . isKill ( ) ) return Sum ; return Sum + 1 ; } ) ; if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) return outliner :: TargetCostInfo ( SequenceSize , 1 , 0 , MachineOutlinerTailCall , MachineOutlinerTailCall ) ; return outliner :: TargetCostInfo ( SequenceSize , 1 , 1 , MachineOutlinerDefault , MachineOutlinerDefault ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s> static unsigned int aarch64_classify_vector_mode ( machine_mode mode ) { if ( aarch64_advsimd_struct_mode_p ( mode ) ) return VEC_ADVSIMD | VEC_STRUCT ; if ( aarch64_sve_pred_mode_p ( mode ) ) return VEC_SVE_PRED ; switch ( mode ) { case E_VNx2QImode : case E_VNx4QImode : case E_VNx8QImode : case E_VNx2HImode : case E_VNx4HImode : case E_VNx2SImode : case E_VNx2HFmode : case E_VNx4HFmode : case E_VNx2SFmode : return TARGET_SVE ? VEC_SVE_DATA | VEC_PARTIAL : 0 ; case E_VNx16QImode : case E_VNx8HImode : case E_VNx4SImode : case E_VNx2DImode : case E_VNx8BFmode : case E_VNx8HFmode : case E_VNx4SFmode : case E_VNx2DFmode : return TARGET_SVE ? VEC_SVE_DATA : 0 ; case E_VNx32QImode : case E_VNx16HImode : case E_VNx8SImode : case E_VNx4DImode : case E_VNx16BFmode : case E_VNx16HFmode : case E_VNx8SFmode : case E_VNx4DFmode : case E_VNx48QImode : case E_VNx24HImode : case E_VNx12SImode : case E_VNx6DImode : case E_VNx24BFmode : case E_VNx24HFmode : case E_VNx12SFmode : case E_VNx6DFmode : case E_VNx64QImode : case E_VNx32HImode : case E_VNx16SImode : case E_VNx8DImode : case E_VNx32BFmode : case E_VNx32HFmode : case E_VNx16SFmode : case E_VNx8DFmode : return TARGET_SVE ? VEC_SVE_DATA | VEC_STRUCT : 0 ; case E_V8QImode : case E_V4HImode : case E_V2SImode : case E_V4HFmode : case E_V4BFmode : case E_V2SFmode : case E_V1DFmode : case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V8HFmode : case E_V8BFmode : case E_V4SFmode : case E_V2DFmode : return TARGET_SIMD ? VEC_ADVSIMD : 0 ; default : return 0 ; } } </s>

Return a set of flags describing the vector properties of mode MODE . Ignore modes that are not supported by the current target .


<s> static bool rs6000_member_type_forces_blk ( const_tree field , machine_mode mode ) { return ( ( TARGET_SPE && TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) ; } </s>

Return true if a structure , union or array containing FIELD should be accessed using ` BLKMODE ' . For the SPE , simd types are V2SI , and gcc can be tempted to put the entire thing in a DI and use subregs to access the internals . store_bit_field ( ) will force ( subreg : DI ( reg : V2SI x ) ) 's to the back-end . Because a single GPR can hold a V2SI , but not a DI , the best thing to do is set structs to BLKmode and avoid Severe Tire Damage . On e500 v2 , DF and DI modes suffer from the same anomaly . DF can fit into 1 , whereas DI still needs two .


<s> static void set_reg_plus_d ( int reg , int base , HOST_WIDE_INT disp , int note ) { rtx_insn * insn ; if ( VAL_14_BITS_P ( disp ) ) { insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , plus_constant ( Pmode , gen_rtx_REG ( Pmode , base ) , disp ) ) ; } else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , delta ) ; insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , gen_rtx_PLUS ( Pmode , tmpreg , basereg ) ) ; if ( DO_FRAME_NOTES ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_PLUS ( Pmode , basereg , delta ) ) ) ; } else { rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( tmpreg , gen_rtx_PLUS ( Pmode , basereg , gen_rtx_HIGH ( Pmode , delta ) ) ) ; insn = emit_move_insn ( gen_rtx_REG ( Pmode , reg ) , gen_rtx_LO_SUM ( Pmode , tmpreg , delta ) ) ; } if ( DO_FRAME_NOTES && note ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit RTL to set REG to the value specified by BASE+DISP . Handle case where DISP > 8k by using the add_high_const patterns . Note in DISP > 8k case , we will leave the high part of the address in % r1 . There is code in expand_hppa_ { prologue , epilogue } that knows this .


<s> const char * thumb1_output_casesi ( rtx * operands ) { rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ 0 ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; switch ( GET_MODE ( diff_vec ) ) { case E_QImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi" ) ; case E_HImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi" ) ; case E_SImode : return "bl\t%___gnu_thumb1_case_si" ; default : gcc_unreachable ( ) ; } } </s>

Output a Thumb-1 casesi dispatch sequence .


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return nullptr ; } switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: i32 , MulLHS , MulRHS ) ; SDValue ResultHigh = SDValue ( Mul , 1 ) ; ReplaceUses ( SDValue ( N , 0 ) , ResultHigh ) ; return nullptr ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> int num_insns_constant ( rtx op , machine_mode mode ) { HOST_WIDE_INT low , high ; switch ( GET_CODE ( op ) ) { case CONST_INT : if ( ( INTVAL ( op ) >> 31 ) != 0 && ( INTVAL ( op ) >> 31 ) != - 1 && mask64_operand ( op , mode ) ) return 2 ; else return num_insns_constant_wide ( INTVAL ( op ) ) ; case CONST_WIDE_INT : { int i ; int ins = CONST_WIDE_INT_NUNITS ( op ) - 1 ; for ( i = 0 ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) ins += num_insns_constant_wide ( CONST_WIDE_INT_ELT ( op , i ) ) ; return ins ; } case CONST_DOUBLE : if ( mode == SFmode || mode == SDmode ) { long l ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL32 ( rv , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( rv , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } long l [ 2 ] ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL64 ( rv , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( rv , l ) ; high = l [ WORDS_BIG_ENDIAN == 0 ] ; low = l [ WORDS_BIG_ENDIAN != 0 ] ; if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ; else { if ( ( high == 0 && low >= 0 ) || ( high == - 1 && low < 0 ) ) return num_insns_constant_wide ( low ) ; else if ( mask64_operand ( op , mode ) ) return 2 ; else if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } default : gcc_unreachable ( ) ; } } </s>

Return the number of instructions it takes to form a constant in as many gprs are needed for MODE .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; if ( useSmallAddressing ( ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; unsigned Align ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Align = LD -> getAlignment ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Align = ST -> getAlignment ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> void aarch64_cpu_cpp_builtins ( cpp_reader * pfile ) { aarch64_define_unconditional_macros ( pfile ) ; aarch64_update_cpp_builtins ( pfile ) ; } </s>


<s> bool nds32_gw_last_load_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; return gw_consumed_by_ex_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to EX .


<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev64v16qi ; break ; case V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev32v16qi ; break ; case V8QImode : gen = gen_neon_vrev32v8qi ; break ; case V8HImode : gen = gen_neon_vrev64v8hi ; break ; case V4HImode : gen = gen_neon_vrev64v4hi ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ; case V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> enum reg_class nds32_regno_reg_class ( int regno ) { if ( regno >= 0 && regno <= 7 ) return LOW_REGS ; else if ( regno >= 8 && regno <= 11 ) return MIDDLE_REGS ; else if ( regno >= 12 && regno <= 14 ) return HIGH_REGS ; else if ( regno == 15 ) return R15_TA_REG ; else if ( regno >= 16 && regno <= 19 ) return MIDDLE_REGS ; else if ( regno >= 20 && regno <= 31 ) return HIGH_REGS ; else if ( regno == 32 || regno == 33 ) return FRAME_REGS ; else return NO_REGS ; } </s>


<s> DecodeStatus DLXDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & , raw_ostream & ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableDLX32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
CSR_Darwin_AArch64_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> static const MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new ARMMCAsmInfoDarwin ( ) ; default : return new ARMELFMCAsmInfo ( ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> bool fusion_p9_p ( rtx addis_reg , rtx addis_value , rtx dest , rtx src ) { rtx addr , mem , offset ; machine_mode mode = GET_MODE ( src ) ; if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( src ) == FLOAT_EXTEND || GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , 0 ) ; if ( fpr_reg_operand ( src , mode ) || int_reg_operand ( src , mode ) ) { if ( ! MEM_P ( dest ) ) return false ; mem = dest ; } else if ( MEM_P ( src ) ) { if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , 1 ) ) ; } else if ( GET_CODE ( addr ) == LO_SUM ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; offset = XEXP ( addr , 1 ) ; if ( TARGET_XCOFF || ( TARGET_ELF && TARGET_POWERPC64 ) ) return small_toc_ref ( offset , GET_MODE ( offset ) ) ; else if ( TARGET_ELF && ! TARGET_POWERPC64 ) return CONSTANT_P ( offset ) ; } return false ; } </s>

Return true if the peephole2 can combine a load/store involving a combination of an addis instruction and the memory operation . This was added to the ISA 3.0 ( power9 ) hardware .


<s> unsigned VEInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: STSri || MI . getOpcode ( ) == VE :: STLri || MI . getOpcode ( ) == VE :: STUri ) { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
unsigned
AArch64InstrInfo
::
getInstSizeInBytes
(
const
MachineInstr
&
MI
)
const
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
const
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
MCAsmInfo
&
MAI
=
*
MF
.
getTarget
(
)
.
getMCAsmInfo
(
)
;
if
(
MCID
.
getSize
(
)
)
return
MCID
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
AArch64
::
INLINEASM
)
return
getInlineAsmLength
(
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
,
MAI
)
;
if
(
MI
.
isLabel
(
)
)
return
0
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
BUNDLE
:
return
getInstBundleLength
(
MI
)
;
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
PROLOG_LABEL
:
case
TargetOpcode
::
EH_LABEL
:
case
TargetOpcode
::
DBG_VALUE
:
return
0
;
case
AArch64
::
TLSDESCCALL
:
return
0
;
default
:
llvm_unreachable
(
"Unknown instruction class"
)
;
}
}
</s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void AArch64AsmPrinter :: emitEndOfAsmFile ( Module & M ) { EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; auto Stubs = MMIMacho . getAuthGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( "__DATA" , "__auth_ptr" , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; emitAlignment ( Align ( 8 ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> RegisterBankInfo :: InstructionMapping ARMRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & ARM :: ValueMappings [ 0 ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_SEXT : case G_ZEXT : OperandsMapping = & ARM :: ValueMappings [ 0 ] ; break ; case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & ARM :: ValueMappings [ 0 ] , nullptr } ) ; break ; default : return InstructionMapping { } ; } return InstructionMapping { DefaultMappingID , 1 , OperandsMapping , NumOperands } ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> unsigned ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr & MI , unsigned * PredCost ) const { if ( MI . isCopyLike ( ) || MI . isInsertSubreg ( ) || MI . isRegSequence ( ) || MI . isImplicitDef ( ) ) return 1 ; if ( MI . isBundle ( ) ) { unsigned Latency = 0 ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != ARM :: t2IT ) Latency += getInstrLatency ( ItinData , * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || ( MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) && ! Subtarget . cheapPredicableCPSRDef ( ) ) ) ) { * PredCost = 1 ; } if ( ! ItinData ) return MI . mayLoad ( ) ? 3 : 1 ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < 0 ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlign ( ) . value ( ) : 0 ; int Adj = adjustDefLatency ( Subtarget , MI , MCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute the instruction latency of a given instruction .


Convert the CONST_WIDE_INT operand OP to broadcast in MODE .


<s>
static
void
ix86_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
char
*
target_string
=
ix86_target_string
(
ptr
->
x_ix86_isa_flags
,
ptr
->
x_ix86_isa_flags2
,
ptr
->
x_target_flags
,
ptr
->
x_ix86_target_flags
,
,
,
ptr
->
x_ix86_fpmath
,
false
)
;
gcc_assert
(
ptr
->
arch
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*sarch = %d (%s)\n"
,
indent
,
""
,
ptr
->
arch
,
processor_target_table
[
ptr
->
arch
]
.
name
)
;
gcc_assert
(
ptr
->
tune
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*stune = %d (%s)\n"
,
indent
,
""
,
ptr
->
tune
,
processor_target_table
[
ptr
->
tune
]
.
name
)
;
fprintf
(
file
,
"%*sbranch_cost = %d\n"
,
indent
,
""
,
ptr
->
branch_cost
)
;
if
(
target_string
)
{
fprintf
(
file
,
"%*s%s\n"
,
indent
,
""
,
target_string
)
;
free
(
target_string
)
;
}
}
</s>


<s> bool mem_operand_ds_form ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = sext_hwi ( offset , 16 ) ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset , extra ) ; } </s>

As above , but for DS-FORM VSX insns . Unlike mem_operand_gpr , enforce an offset divisible by 4 even for 32-bit .


<s> static inline bool inline_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 , int strict ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) || MAYBE_MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class1 ) || MAYBE_MASK_CLASS_P ( class2 ) != MASK_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) || ( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . To optimize register_move_cost performance , allow inline variant . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> static rtx arm_function_value ( const_tree type , const_tree func , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsignedp ATTRIBUTE_UNUSED ; rtx r ATTRIBUTE_UNUSED ; mode = TYPE_MODE ( type ) ; if ( TARGET_AAPCS_BASED ) return aapcs_allocate_return_reg ( mode , type , func ) ; if ( INTEGRAL_TYPE_P ( type ) ) mode = arm_promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . require ( ) ; } } return arm_libcall_value_1 ( mode ) ; } </s>

Define how to find the value returned by a function .


<s> void AArch64AsmPrinter :: emitJumpTableInfo ( ) { const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; if ( ! MJTI ) return ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const Function & F = MF -> getFunction ( ) ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; bool JTInDiffSection = ! STI -> isTargetCOFF ( ) || ! TLOF . shouldPutJumpTableInFunctionSection ( MJTI -> getEntryKind ( ) == MachineJumpTableInfo :: EK_LabelDifference32 , F ) ; if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; } auto AFI = MF -> getInfo < AArch64FunctionInfo > ( ) ; for ( unsigned JTI = 0 , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; emitAlignment ( Align ( Size ) ) ; OutStreamer -> emitLabel ( GetJTISymbol ( JTI ) ) ; const MCSymbol * BaseSym = AArch64FI -> getJumpTableEntryPCRelSymbol ( JTI ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( BaseSym , OutContext ) ; for ( auto * JTBB : JTBBs ) { const MCExpr * Value = MCSymbolRefExpr :: create ( JTBB -> getSymbol ( ) , OutContext ) ; Value = MCBinaryExpr :: createSub ( Value , Base , OutContext ) ; if ( Size != 4 ) Value = MCBinaryExpr :: createLShr ( Value , MCConstantExpr :: create ( 2 , OutContext ) , OutContext ) ; OutStreamer -> emitValue ( Value , Size ) ; } } } </s>

Print assembly representations of the jump tables used by the current function to the current output stream .


<s> bool X86AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << "(%rip)" ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; printOperand ( MI , OpNo , O ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget . isABI_N64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static int ia64_function_arg_words ( tree type , enum machine_mode mode ) { int words ; if ( mode == BLKmode ) words = int_size_in_bytes ( type ) ; else words = GET_MODE_SIZE ( mode ) ; return ( words + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Return the number of words required to hold a quantity of TYPE and MODE when passed as an argument .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) { return CSR_GHC_SaveList ; } else { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } } </s>


<s> void pru_register_abicheck_pass ( void ) { opt_pass * tiabi_check = make_pass_tiabi_check ( g ) ; struct register_pass_info tiabi_check_info = { tiabi_check , "*warn_unused_result" , 1 , PASS_POS_INSERT_AFTER } ; register_pass ( & tiabi_check_info ) ; } </s>


<s> static bool is_prefetch ( rtx_insn * insn ) { return NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PREFETCH ; } </s>

Return true if insn is a prefetch instruction .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
OperandType
type
,
\
uint8_t
index
,
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
if
(
insn
->
rexPrefix
&&
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_TMM
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_TMM0
+
index
;
\
case
TYPE_VK
:
\
index
&=
0xf
;
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_VK_PAIR
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0_K1
+
(
index
/
2
)
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void mips_ls2_dfa_post_advance_cycle ( state_t state ) { if ( cpu_unit_reservation_p ( state , mips_ls2 . alu1_core_unit_code ) ) { gcc_assert ( mips_ls2 . cycle_has_multi_p ) ; mips_ls2 . alu1_turn_p = false ; } mips_ls2 . cycle_has_multi_p = false ; if ( cpu_unit_reservation_p ( state , mips_ls2 . alu2_core_unit_code ) ) mips_ls2 . alu1_turn_p = true ; if ( mips_ls2 . alu1_turn_p ) { if ( state_transition ( state , mips_ls2 . alu1_turn_enabled_insn ) >= 0 ) gcc_unreachable ( ) ; } else { if ( state_transition ( state , mips_ls2 . alu2_turn_enabled_insn ) >= 0 ) gcc_unreachable ( ) ; } if ( cpu_unit_reservation_p ( state , mips_ls2 . falu1_core_unit_code ) ) { gcc_unreachable ( ) ; mips_ls2 . falu1_turn_p = false ; } if ( cpu_unit_reservation_p ( state , mips_ls2 . falu2_core_unit_code ) ) mips_ls2 . falu1_turn_p = true ; if ( mips_ls2 . falu1_turn_p ) { if ( state_transition ( state , mips_ls2 . falu1_turn_enabled_insn ) >= 0 ) gcc_unreachable ( ) ; } else { if ( state_transition ( state , mips_ls2 . falu2_turn_enabled_insn ) >= 0 ) gcc_unreachable ( ) ; } } </s>

Initialize STATE when scheduling for Loongson 2E/2F . Support round-robin dispatch scheme by enabling only one of ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions respectively .


<s> void setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; processPHIs ( MF ) ; } </s>


<s> static rtx aarch64_extend_bitfield_pattern_p ( rtx x ) { rtx_code outer_code = GET_CODE ( x ) ; machine_mode outer_mode = GET_MODE ( x ) ; if ( outer_code != ZERO_EXTEND && outer_code != SIGN_EXTEND && outer_mode != SImode && outer_mode != DImode ) return NULL_RTX ; rtx inner = XEXP ( x , 0 ) ; rtx_code inner_code = GET_CODE ( inner ) ; machine_mode inner_mode = GET_MODE ( inner ) ; rtx op = NULL_RTX ; switch ( inner_code ) { case ASHIFT : if ( CONST_INT_P ( XEXP ( inner , 1 ) ) && ( inner_mode == QImode || inner_mode == HImode ) ) op = XEXP ( inner , 0 ) ; break ; case LSHIFTRT : if ( outer_code == ZERO_EXTEND && CONST_INT_P ( XEXP ( inner , 1 ) ) && ( inner_mode == QImode || inner_mode == HImode ) ) op = XEXP ( inner , 0 ) ; break ; case ASHIFTRT : if ( outer_code == SIGN_EXTEND && CONST_INT_P ( XEXP ( inner , 1 ) ) && ( inner_mode == QImode || inner_mode == HImode ) ) op = XEXP ( inner , 0 ) ; break ; default : break ; } return op ; } </s>

Check whether X is a bitfield operation of the form shift + extend that maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction . If so , return the operand to which the bitfield operation is applied . Otherwise return NULL_RTX .


<s>
static
const
char
*
ia64_invalid_unary_op
(
int
op
,
const_tree
type
)
{
if
(
TYPE_MODE
(
type
)
==
RFmode
&&
op
!=
CONVERT_EXPR
&&
op
!=
ADDR_EXPR
)
return
N_
(
"invalid operation on %<__fpreg%>"
)
;
return
;
}
</s>

Return the diagnostic message string if the unary operation OP is not permitted on TYPE , NULL otherwise .


<s> bool X86TargetLowering :: SimplifyDemandedBitsForTargetNode ( SDValue Op , const APInt & OriginalDemandedBits , KnownBits & Known , TargetLoweringOpt & TLO , unsigned Depth ) const { unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case X86ISD :: PMULDQ : case X86ISD :: PMULUDQ : { KnownBits KnownOp ; SDValue LHS = Op . getOperand ( 0 ) ; SDValue RHS = Op . getOperand ( 1 ) ; APInt DemandedMask = APInt :: getLowBitsSet ( 64 , 32 ) ; if ( SimplifyDemandedBits ( LHS , DemandedMask , KnownOp , TLO , Depth + 1 ) ) return true ; if ( SimplifyDemandedBits ( RHS , DemandedMask , KnownOp , TLO , Depth + 1 ) ) return true ; break ; } } return TargetLowering :: SimplifyDemandedBitsForTargetNode ( Op , OriginalDemandedBits , Known , TLO , Depth ) ; } </s>

Attempt to simplify any target nodes based on the demanded bits/elts , returning true on success .


<s> bool ARMSubtarget :: enablePostRAMachineScheduler ( ) const { if ( ! enableMachineScheduler ( ) ) return false ; if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only ( ) ; } </s>

True if the subtarget should run a machine scheduler after register allocation .


<s>
const
char
*
emit_fusion_p9_load
(
rtx
reg
,
rtx
mem
,
rtx
tmp_reg
)
{
enum
machine_mode
mode
=
GET_MODE
(
reg
)
;
rtx
hi
;
rtx
lo
;
rtx
addr
;
const
char
*
load_string
;
int
r
;
if
(
GET_CODE
(
mem
)
==
FLOAT_EXTEND
||
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
{
mem
=
XEXP
(
mem
,
0
)
;
mode
=
GET_MODE
(
mem
)
;
}
if
(
GET_CODE
(
reg
)
==
SUBREG
)
{
gcc_assert
(
SUBREG_BYTE
(
reg
)
==
0
)
;
reg
=
SUBREG_REG
(
reg
)
;
}
if
(
!
REG_P
(
reg
)
)
fatal_insn
(
"emit_fusion_p9_load, bad reg #1"
,
reg
)
;
r
=
REGNO
(
reg
)
;
if
(
FP_REGNO_P
(
r
)
)
{
if
(
mode
==
SFmode
)
load_string
=
"lfs"
;
else
if
(
mode
==
DFmode
||
mode
==
DImode
)
load_string
=
"lfd"
;
else
gcc_unreachable
(
)
;
}
else
if
(
INT_REGNO_P
(
r
)
)
{
switch
(
mode
)
{
case
QImode
:
load_string
=
"lbz"
;
break
;
case
HImode
:
load_string
=
"lhz"
;
break
;
case
SImode
:
case
SFmode
:
load_string
=
"lwz"
;
break
;
case
DImode
:
case
DFmode
:
if
(
!
TARGET_POWERPC64
)
gcc_unreachable
(
)
;
load_string
=
"ld"
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
fatal_insn
(
"emit_fusion_p9_load, bad reg #2"
,
reg
)
;
if
(
!
MEM_P
(
mem
)
)
fatal_insn
(
"emit_fusion_p9_load not MEM"
,
mem
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
hi
,
&
lo
)
;
emit_fusion_addis
(
tmp_reg
,
hi
,
"power9 load fusion"
,
GET_MODE_NAME
(
mode
)
)
;
emit_fusion_load_store
(
reg
,
tmp_reg
,
lo
,
load_string
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a load using extended fusion . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"emit_fusion_p9_load, bad reg #1"
"lfs"
"lfd"
"lbz"
"lhz"
"lwz"
"ld"
"emit_fusion_p9_load, bad reg #2"
"emit_fusion_p9_load not MEM"
0
"power9 load fusion"
""


<s> static bool mips_rtx_constant_in_small_data_p ( machine_mode mode ) { return ( ! TARGET_EMBEDDED_DATA && TARGET_LOCAL_SDATA && GET_MODE_SIZE ( mode ) <= mips_small_data_threshold ) ; } </s>

Return true if rtx constants of mode MODE should be put into a small data section .


<s> static void rs6000_override_options_after_change ( void ) { if ( ( OPTION_SET_P ( flag_unroll_loops ) && flag_unroll_loops ) || ( OPTION_SET_P ( flag_unroll_all_loops ) && flag_unroll_all_loops ) ) { if ( ! OPTION_SET_P ( unroll_only_small_loops ) ) unroll_only_small_loops = 0 ; if ( ! OPTION_SET_P ( flag_rename_registers ) ) flag_rename_registers = 1 ; if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = 1 ; } else if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = flag_peel_loops || optimize >= 3 ; if ( rs6000_rop_protect ) flag_shrink_wrap = 0 ; } </s>

This target function is similar to the hook TARGET_OPTION_OVERRIDE but is called when the optimize level is changed via an attribute or pragma or when it is reset at the end of the code affected by the attribute or pragma . It is not called at the beginning of compilation when TARGET_OPTION_OVERRIDE is called so if you want to perform these actions then , you should have TARGET_OPTION_OVERRIDE call TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static bool rs6000_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p ) { static int recurse = 0 ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > 1 ) && in_section != toc_section && ! recurse && ! CONST_SCALAR_INT_P ( x ) && CONSTANT_P ( x ) ) { char buf [ 256 ] ; recurse = 1 ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , fixuplabelno ) ; fixuplabelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\t.long\t(" ) ; output_addr_const ( asm_out_file , x ) ; fprintf ( asm_out_file , ")@fixup\n" ) ; fprintf ( asm_out_file , "\t.section\t\".fixup\",\"aw\"\n" ) ; ASM_OUTPUT_ALIGN ( asm_out_file , 2 ) ; fprintf ( asm_out_file , "\t.long\t" ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\n\t.previous\n" ) ; recurse = 0 ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , 0 ) [ 0 ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , 0 ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , "\t.long\t%s\n" , name ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The powerpc version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined . It also needs to handle DI-mode objects on 64-bit targets .


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86ISelDag ( * this , OptLevel ) ) ; PM . add ( createX87FPRegKillInserterPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const SystemZSubtarget & Subtarget = MF -> getSubtarget < SystemZSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return CSR_SystemZ_NoRegs_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_SystemZ_AllRegs_Vector_SaveList : CSR_SystemZ_AllRegs_SaveList ; if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_SaveList ; return CSR_SystemZ_SaveList ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool ARMInstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( ARM :: tPOP ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; PopMI -> setDesc ( get ( ARM :: tPOP_RET ) ) ; MBB . erase ( MI ) ; } PopMI -> addOperand ( MachineOperand :: CreateReg ( Reg , true ) ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static inline bool inline_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 , int strict ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) || MAYBE_MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class1 ) || MAYBE_MASK_CLASS_P ( class2 ) != MASK_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) { if ( ! ( INTEGER_CLASS_P ( class1 ) || INTEGER_CLASS_P ( class2 ) ) || GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; } if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ! ( INTEGER_CLASS_P ( class1 ) || INTEGER_CLASS_P ( class2 ) ) ) return true ; int msize = GET_MODE_SIZE ( mode ) ; if ( msize > UNITS_PER_WORD ) return true ; int minsize = GET_MODE_SIZE ( TARGET_SSE2 ? HImode : SImode ) ; if ( msize < minsize ) return true ; if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) || ( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . To optimize register_move_cost performance , allow inline variant . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , MVT :: Other , MVT :: Glue ) ; SDValue Unused = DAG . getNode ( SystemZISD :: STRCMP , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; Chain = Unused . getValue ( 1 ) ; SDValue Glue = Chain . getValue ( 2 ) ; return std :: make_pair ( addIPMSequence ( DL , Glue , DAG ) , Chain ) ; } </s>

Emit target-specific code that performs a strcmp , in cases where that is faster than a libcall .


<s> HOST_WIDE_INT rs6000_initial_elimination_offset ( int from , int to ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; HOST_WIDE_INT offset ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? 0 : - info -> total_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { offset = info -> push_p ? 0 : - info -> total_size ; if ( FRAME_GROWS_DOWNWARD ) offset += info -> fixed_size + info -> vars_size + info -> parm_size ; } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = FRAME_GROWS_DOWNWARD ? info -> fixed_size + info -> vars_size + info -> parm_size : 0 ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = info -> total_size ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? info -> total_size : 0 ; else if ( from == RS6000_PIC_OFFSET_TABLE_REGNUM ) offset = 0 ; else gcc_unreachable ( ) ; return offset ; } </s>

Define the offset between two registers , FROM to be eliminated and its replacement TO , at the start of a routine .


<s> bool AArch64TargetLowering :: isExtFreeImpl ( const Instruction * Ext ) const { if ( isa < FPExtInst > ( Ext ) ) return false ; if ( Ext -> getType ( ) -> isVectorTy ( ) ) return false ; for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( 1 ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; auto & DL = Ext -> getModule ( ) -> getDataLayout ( ) ; std :: advance ( GTI , U . getOperandNo ( ) - 1 ) ; Type * IdxTy = GTI . getIndexedType ( ) ; uint64_t ShiftAmt = countTrailingZeros ( DL . getTypeStoreSizeInBits ( IdxTy ) ) - 3 ; if ( ShiftAmt == 0 || ShiftAmt > 4 ) return false ; break ; } case Instruction :: Trunc : if ( Instr -> getType ( ) == Ext -> getOperand ( 0 ) -> getType ( ) ) continue ; LLVM_FALLTHROUGH ; default : return false ; } } return true ; } </s>

Return true if the extension represented by I is free .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> const TargetRegisterClass * Mips16RegisterInfo :: intRegClass ( unsigned Size ) const { assert ( Size == 4 ) ; return & Mips :: CPU16RegsRegClass ; } </s>


<s> Optional < ParamLoadedValue > AArch64InstrInfo :: describeLoadedValue ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case AArch64 :: MOVZWi : case AArch64 :: MOVZXi : if ( ! MI . getOperand ( 1 ) . isImm ( ) ) return None ; int Immediate = MI . getOperand ( 1 ) . getImm ( ) ; int Shift = MI . getOperand ( 2 ) . getImm ( ) ; return ParamLoadedValue ( MachineOperand :: CreateImm ( Immediate << Shift ) , nullptr ) ; } return TargetInstrInfo :: describeLoadedValue ( MI ) ; } </s>

Produce the expression describing the MI loading a value into the physical register Reg .


<s> const char * arithmetic_instr ( rtx op , int shift_first_arg ) { switch ( GET_CODE ( op ) ) { case PLUS : return "add" ; case MINUS : return shift_first_arg ? "rsb" : "sub" ; case IOR : return "orr" ; case XOR : return "eor" ; case AND : return "and" ; default : gcc_unreachable ( ) ; } } </s>

Return the appropriate ARM instruction for the operation code . The returned result should not be overwritten . OP is the rtx of the operation . SHIFT_FIRST_ARG is TRUE if the first argument of the operator was shifted .