<s> bool Thumb1FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned CFSize = MFI . getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> inline static rtx next_consecutive_mem ( rtx mem ) { machine_mode mode = GET_MODE ( mem ) ; HOST_WIDE_INT offset = GET_MODE_SIZE ( mode ) ; rtx addr = plus_constant ( Pmode , XEXP ( mem , 0 ) , offset ) ; return adjust_automodify_address ( mem , mode , addr , offset ) ; } </s>

Helper for gen_movmem_ldrd_strd . Increase the address of memory rtxby mode size .


<s> static bool mips_valid_lo_sum_p ( enum mips_symbol_type symbol_type , machine_mode mode ) { if ( mips_symbol_insns ( symbol_type , mode ) == 0 ) return false ; if ( mips_lo_relocs [ symbol_type ] == NULL ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) return false ; if ( MSA_SUPPORTED_MODE_P ( mode ) ) return false ; return true ; } </s>

Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYMBOL_TYPE .


<s> bool arm_coproc_builtin_available ( enum unspecv builtin ) { if ( TARGET_THUMB1 ) return false ; switch ( builtin ) { case VUNSPEC_CDP : case VUNSPEC_LDC : case VUNSPEC_LDCL : case VUNSPEC_STC : case VUNSPEC_STCL : case VUNSPEC_MCR : case VUNSPEC_MRC : if ( arm_arch4 ) return true ; break ; case VUNSPEC_CDP2 : case VUNSPEC_LDC2 : case VUNSPEC_LDC2L : case VUNSPEC_STC2 : case VUNSPEC_STC2L : case VUNSPEC_MCR2 : case VUNSPEC_MRC2 : if ( arm_arch5 ) return true ; break ; case VUNSPEC_MCRR : case VUNSPEC_MRRC : if ( arm_arch6 || arm_arch5te ) return true ; break ; case VUNSPEC_MCRR2 : case VUNSPEC_MRRC2 : if ( arm_arch6 ) return true ; break ; default : gcc_unreachable ( ) ; } return false ; } </s>

This function checks for the availability of the coprocessor builtin passed in BUILTIN for the current target . Returns true if it is available and false otherwise . If a BUILTIN is passed for which this function has not been implemented it will cause an exception .


<s> bool FISCRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; MVT SrcVT = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( TLI ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static bool iq2000_pass_by_reference ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int size ; if ( cum && targetm . calls . must_pass_in_stack ( arg ) ) { CUMULATIVE_ARGS temp ; temp = * cum ; if ( iq2000_function_arg ( pack_cumulative_args ( & temp ) , arg ) != 0 ) return 1 ; } if ( arg . type == NULL_TREE || arg . mode == DImode || arg . mode == DFmode ) return 0 ; size = int_size_in_bytes ( arg . type ) ; return size == - 1 || size > UNITS_PER_WORD ; } </s>

Return true when an argument must be passed by reference .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || MFI -> hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"mt_final_prescan_insn, invalid insn #1"

The following determines the number of nops that need to be inserted between the previous instructions and current instruction to avoid pipeline hazards on the mt processor . Remember that the function is not called for asm insns .


<s> static void rx_get_stack_layout ( unsigned int * lowest , unsigned int * highest , unsigned int * register_mask , unsigned int * frame_size , unsigned int * stack_size ) { unsigned int reg ; unsigned int low ; unsigned int high ; unsigned int fixed_reg = 0 ; unsigned int save_mask ; unsigned int pushed_mask ; unsigned int unneeded_pushes ; if ( is_naked_func ( NULL_TREE ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = 0 ; * frame_size = 0 ; * stack_size = 0 ; return ; } for ( save_mask = high = low = 0 , reg = 1 ; reg < CC_REGNUM ; reg ++ ) { if ( ( df_regs_ever_live_p ( reg ) || ( call_used_regs [ reg ] && is_interrupt_func ( NULL_TREE ) && ! crtl -> is_leaf ) ) && ( ! call_used_regs [ reg ] || is_interrupt_func ( NULL_TREE ) || ( is_fast_interrupt_func ( NULL_TREE ) && ! IN_RANGE ( reg , 10 , 13 ) ) ) ) { if ( low == 0 ) low = reg ; high = reg ; save_mask |= 1 << reg ; } if ( low != 0 && fixed_reg == 0 && fixed_regs [ reg ] ) fixed_reg = reg ; } if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < 2 ) { save_mask |= ( 1 << 13 ) | ( 1 << 14 ) ; if ( low == 0 ) low = 13 ; if ( high == 0 || low == high ) high = low + 1 ; } pushed_mask = ( HOST_WIDE_INT_M1U << low ) & ~ ( HOST_WIDE_INT_M1U << ( high + 1 ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = save_mask ; } else { * lowest = low ; * highest = high ; * register_mask = 0 ; } * frame_size = rx_round_up ( get_frame_size ( ) , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( crtl -> args . size > 0 ) * frame_size += rx_round_up ( crtl -> args . size , STACK_BOUNDARY / BITS_PER_UNIT ) ; * stack_size = rx_round_up ( crtl -> outgoing_args_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>

Returns either the lowest numbered and highest numbered registers that occupy the call-saved area of the stack frame , if the registers are stored as a contiguous block , or else a bitmask of the individual registers if they are stored piecemeal . Also computes the size of the frame and the size of the outgoing arguments block ( in bytes ) .


<s> Register SparcRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return SP :: I6 ; } </s>


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { return new ScheduleDAGMI ( C , make_unique < SystemZPostRASchedStrategy > ( C ) , true ) ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) { } </s>


<s> const ARMSubtarget * getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


This method may be implemented by targets that want to run passes immediately before register allocation .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> void MipsRegisterInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: SP ) . addReg ( Mips :: FP ) . addReg ( Mips :: ZERO ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; } if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: LW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( NumBytes ) ; } } </s>

Mips Mips Mips Mips Mips Mips Mips Mips::ADDu Mips::SP Mips::FP Mips::ZERO Mips::LW Mips::FP Mips::SP Mips::LW Mips::RA Mips::SP Mips::ADDiu Mips::SP Mips::SP


<s> bool aarch64_sve_float_mul_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_DOUBLE_P ( elt ) && ( real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconsthalf ) || real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconst2 ) ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE FMUL instruction .


"malformed %<target()%> pragma or attribute"

"pragma or attribute %<target(\"%s\")%> does not accept an argument"

"pragma or attribute %<target(\"%s\")%> does not allow a negated form"

"pragma or attribute %<target(\"%s=%s\")%> is not valid"

Parse ARG_STR which contains the definition of one target attribute . Show appropriate errors if any or return true if the attribute is valid . PRAGMA_OR_ATTR holds the string to use in error messages about whether we 're processing a target attribute or pragma .


<s> static void * rs6000_init_cost ( struct loop * loop_info ) { rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = 0 ; data -> cost [ vect_body ] = 0 ; data -> cost [ vect_epilogue ] = 0 ; return data ; } </s>


<s> EVT CSKYTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
CE
->
getValue
(
)
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s> static RegDomain getDomain ( const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) { if ( isGPR ( RC ) ) return GPRDomain ; if ( isMask ( RC , TRI ) ) return MaskDomain ; return OtherDomain ; } </s>

Get the MDNode for this AliasScopeNode 's domain .


<s> bool XNCMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; XNCMMachineFunctionInfo * MFI = MF . getInfo < XNCMMachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static int arm_get_strip_length ( int c ) { switch ( c ) { ARM_NAME_ENCODING_LENGTHS default : return 0 ; } } </s>

Return the length of a function name prefix that starts with the character ' c ' .


<s> static rtx construct_plt_address ( rtx symbol ) { rtx tmp , unspec ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; gcc_assert ( ix86_cmodel == CM_LARGE_PIC && ! TARGET_PECOFF ) ; gcc_assert ( Pmode == DImode ) ; tmp = gen_reg_rtx ( Pmode ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , symbol ) , UNSPEC_PLTOFF ) ; emit_move_insn ( tmp , gen_rtx_CONST ( Pmode , unspec ) ) ; emit_insn ( gen_add2_insn ( tmp , pic_offset_table_rtx ) ) ; return tmp ; } </s>

For given symbol ( function ) construct code to compute address of it 's PLT entry in large x86-64 PIC model .


<s> void mmix_conditional_register_usage ( void ) { int i ; if ( TARGET_ABI_GNU ) { static const int gnu_abi_reg_alloc_order [ ] = MMIX_GNU_ABI_REG_ALLOC_ORDER ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = gnu_abi_reg_alloc_order [ i ] ; for ( i = 15 ; i <= 30 ; i ++ ) call_used_regs [ i ] = 0 ; for ( i = MMIX_RESERVED_GNU_ARG_0_REGNUM ; i < MMIX_RESERVED_GNU_ARG_0_REGNUM + MMIX_MAX_ARGS_IN_REGS ; i ++ ) fixed_regs [ i ] = 0 ; } if ( ! TARGET_TOPLEVEL_SYMBOLS ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( reg_names [ i ] [ 0 ] == ':' ) reg_names [ i ] ++ ; } </s>


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
getARMRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
TargetInstrDesc
&
TID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
TID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> DecodeStatus FISCDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return Result ; Result = decodeInstruction ( DecoderTableFISC32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> static void ia64_hpux_init_libfuncs ( void ) { ia64_init_libfuncs ( ) ; set_optab_libfunc ( sdiv_optab , SImode , 0 ) ; set_optab_libfunc ( udiv_optab , SImode , 0 ) ; set_optab_libfunc ( smod_optab , SImode , 0 ) ; set_optab_libfunc ( umod_optab , SImode , 0 ) ; set_optab_libfunc ( sdiv_optab , DImode , "__milli_divI" ) ; set_optab_libfunc ( udiv_optab , DImode , "__milli_divU" ) ; set_optab_libfunc ( smod_optab , DImode , "__milli_remI" ) ; set_optab_libfunc ( umod_optab , DImode , "__milli_remU" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qfmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; cmptf_libfunc = init_one_libfunc ( "_U_Qfcmp" ) ; set_optab_libfunc ( eq_optab , TFmode , 0 ) ; set_optab_libfunc ( ne_optab , TFmode , 0 ) ; set_optab_libfunc ( gt_optab , TFmode , 0 ) ; set_optab_libfunc ( ge_optab , TFmode , 0 ) ; set_optab_libfunc ( lt_optab , TFmode , 0 ) ; set_optab_libfunc ( le_optab , TFmode , 0 ) ; } </s>

Rename all the TFmode libfuncs using the HPUX conventions .


<s> bool ix86_lea_for_add_ok ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 = true_regnum ( operands [ 0 ] ) ; unsigned int regno1 = true_regnum ( operands [ 1 ] ) ; unsigned int regno2 = true_regnum ( operands [ 2 ] ) ; if ( regno0 != regno1 && regno0 != regno2 ) return true ; if ( ! TARGET_OPT_AGU || optimize_function_for_size_p ( cfun ) ) return false ; return ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , 0 , false ) ; } </s>

Return true if it is ok to optimize an ADD operation to LEA operation to avoid flag register consumation . For most processors , ADD is faster than LEA . For the processors like BONNELL , if the destination register of LEA holds an actual address which will be used soon , LEA is better and otherwise ADD is better .


<s> unsigned int arm_dbx_register_number ( unsigned int regno ) { if ( regno < 16 ) return regno ; if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return 64 + regno - FIRST_VFP_REGNUM ; else return 256 + ( regno - FIRST_VFP_REGNUM ) / 2 ; } if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return 104 + regno - FIRST_IWMMXT_GR_REGNUM ; if ( IS_IWMMXT_REGNUM ( regno ) ) return 112 + regno - FIRST_IWMMXT_REGNUM ; gcc_unreachable ( ) ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s> bool X86TTI :: isLegalMaskedStore ( Type * DataType , int Consecutive ) const { return isLegalMaskedLoad ( DataType , Consecutive ) ; } </s>

Return true if the target supports masked store .


<s> void aarch64_expand_mov_immediate ( rtx dest , rtx imm ) { machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( mode == SImode || mode == DImode ) ; if ( GET_CODE ( imm ) == SYMBOL_REF || GET_CODE ( imm ) == LABEL_REF || GET_CODE ( imm ) == CONST ) { rtx mem , base , offset ; enum aarch64_symbol_type sty ; split_const ( imm , & base , & offset ) ; sty = aarch64_classify_symbol ( base , offset ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( offset != const0_rtx && targetm . cannot_force_const_mem ( mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( aarch64_nopcrelative_literal_loads ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , 0 ) ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : case SYMBOL_TLSLE12 : case SYMBOL_TLSLE24 : case SYMBOL_TLSLE32 : case SYMBOL_TLSLE48 : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_CODE ( imm ) == HIGH ) emit_insn ( gen_rtx_SET ( dest , imm ) ) ; else { rtx mem = force_const_mem ( mode , imm ) ; gcc_assert ( mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; } return ; } aarch64_internal_mov_immediate ( dest , imm , true , GET_MODE ( dest ) ) ; } </s>

Set DEST to immediate IMM . For SVE vector modes , GEN_VEC_DUPLICATE is a pattern that can be used to set DEST to a replicated scalar element .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy ) { if ( isa < VectorType > ( DataTy ) && ! isPowerOf2_32 ( DataTy -> getVectorNumElements ( ) ) ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth == 32 || DataWidth == 64 ) && ST -> hasAVX512 ( ) ; } </s>

Return true if the target supports masked gather .


<s> bool n13_consumed_by_e2_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_STORE : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_rt_dep_reg_p ( consumer , def_reg ) ; case TYPE_STORE_MULTIPLE : use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; case TYPE_BRANCH : use_rtx = extract_branch_condition_rtx ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at E2 .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; if ( VT . getScalarType ( ) == MVT :: i1 ) return false ; if ( VT . getSizeInBits ( ) == 64 ) return false ; return isTypeLegal ( VT . getSimpleVT ( ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> TargetIRAnalysis AArch64TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( AArch64TTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> static rtx aarch64_expand_sve_const_vector_sel ( rtx target , rtx src ) { gcc_assert ( CONST_VECTOR_NELTS_PER_PATTERN ( src ) == 2 ) ; machine_mode mode = GET_MODE ( src ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( mode ) ; unsigned int npatterns = CONST_VECTOR_NPATTERNS ( src ) ; if ( aarch64_svpattern_for_vl ( pred_mode , npatterns ) == AARCH64_NUM_SVPATTERNS ) return NULL_RTX ; rtx_vector_builder pred_builder ( pred_mode , npatterns , 2 ) ; rtx_vector_builder true_builder ( mode , npatterns , 1 ) ; rtx_vector_builder false_builder ( mode , npatterns , 1 ) ; for ( unsigned int i = 0 ; i < npatterns ; ++ i ) { true_builder . quick_push ( CONST_VECTOR_ENCODED_ELT ( src , i ) ) ; pred_builder . quick_push ( CONST1_RTX ( BImode ) ) ; } for ( unsigned int i = 0 ; i < npatterns ; ++ i ) { false_builder . quick_push ( CONST_VECTOR_ENCODED_ELT ( src , i + npatterns ) ) ; pred_builder . quick_push ( CONST0_RTX ( BImode ) ) ; } expand_operand ops [ 4 ] ; create_output_operand ( & ops [ 0 ] , target , mode ) ; create_input_operand ( & ops [ 1 ] , true_builder . build ( ) , mode ) ; create_input_operand ( & ops [ 2 ] , false_builder . build ( ) , mode ) ; create_input_operand ( & ops [ 3 ] , pred_builder . build ( ) , pred_mode ) ; expand_insn ( code_for_vcond_mask ( mode , mode ) , 4 , ops ) ; return target ; } </s>

SRC is an SVE CONST_VECTOR that contains N `` foreground '' values followed by N `` background '' values . Try to move it into TARGET using : PTRUE PRED. < T > , VL < N > MOV TRUE. < T > , # < foreground > MOV FALSE. < T > , # < background > SEL TARGET. < T > , PRED. < T > , TRUE. < T > , FALSE. < T > The PTRUE is always a single instruction but the MOVs might need a longer sequence . If the background value is zero ( as it often is ) , the sequence can sometimes collapse to a PTRUE followed by a zero-predicated move . Return the target on success , otherwise return null .


Clear caller saved registers not used to pass return values and leaked condition flags before exiting a cmse_nonsecure_entry function .


<s>
void
X86AsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
bool
Is16BitMode
=
STI
.
getFeatureBits
(
)
[
X86
::
Mode16Bit
]
;
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
,
Is16BitMode
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Inst
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } } </s>


<s> virtual const MipsInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


<s> bool AArch64TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { return ExtVal . getValueType ( ) . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( ExtVal . getValueType ( ) , true ) ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool sparc_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( TARGET_ARCH64 && GET_MODE_SIZE ( from ) == 4 && GET_MODE_SIZE ( to ) != 4 ) return ! reg_classes_intersect_p ( rclass , FP_REGS ) ; return true ; } </s>

Implement TARGET_CAN_CHANGE_MODE_CLASS . Borrowed from the PA port . SImode loads to floating-point registers are not zero-extended . The definition for LOAD_EXTEND_OP specifies that integer loads narrower than BITS_PER_WORD will be zero-extended . As a result , we inhibit changes from SImode unless they are to a mode that is identical in size . Likewise for SFmode , since word-mode paradoxical subregs are problematic on big-endian architectures .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
*
RC
=
&
ARM
::
GPRPairRegClass
;
for
(
TargetRegisterClass
::
iterator
I
=
RC
->
begin
(
)
,
E
=
RC
->
end
(
)
;
I
!=
E
;
++
I
)
for
(
MCSubRegIterator
SI
(
*
I
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
*
I
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
int
AArch64InstrInfo
::
getMemScale
(
unsigned
Opc
)
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSpre
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWpre
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRSpre
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
STRWpre
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRDpre
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
LDRXpre
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRDpre
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
STRXpre
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
STRQpre
:
case
AArch64
::
LDPQi
:
case
AArch64
::
LDRQpre
:
case
AArch64
::
STPQi
:
case
AArch64
::
STGOffset
:
case
AArch64
::
STZGOffset
:
case
AArch64
::
ST2GOffset
:
case
AArch64
::
STZ2GOffset
:
case
AArch64
::
STGPi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; const TargetRegisterClass * RC = Subtarget . isPPC64 ( ) ? G8RC : GPRC ; unsigned Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCRpseud ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( PPC :: RLWINM ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( PPCRegisterInfo :: getRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( PPC :: STW ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( 1 ) . getImm ( ) ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { printInstFlags ( MI , OS , STI ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Is16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const SystemZInstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s>
SDValue
XNCMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XNCM
XNCM
ISD::SHL
ISD::SRL
ISD::SRA
ISD::GlobalAddress
ISD::BlockAddress
ISD::ExternalSymbol
ISD::BR_CC
ISD::SELECT_CC
ISD::SIGN_EXTEND
"unimplemented operand"


<s> bool AArch64InstrInfo :: isStridedAccess ( const MachineInstr & MI ) const { return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOStridedAccess ; } ) ; } </s>

Return true if the given load or store is a strided memory access .


<s> static SDValue getTruncateOrZeroExtend ( SDValue V , SelectionDAG & DAG , MVT ToVT ) { SDNodeTreeBuilder b ( V , & DAG ) ; MVT VT = V . getSimpleValueType ( ) ; if ( VT . bitsLT ( ToVT ) ) return b . ZERO_EXTEND ( V , ToVT ) ; else if ( VT . bitsGT ( ToVT ) ) return b . TRUNCATE ( V , ToVT ) ; return V ; } </s>

Return a SCEV corresponding to a conversion of the input value to the specified type .


<s> static void emit_unspec2 ( rtx target , int code , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_UNSPEC ( GET_MODE ( target ) , gen_rtvec ( 2 , op0 , op1 ) , code ) ) ) ; } </s>

Generate ( set TARGET ( unspec [ OP0 OP1 ] CODE ) ) .


";;\tatom sched_reorder: put %d insn on top\n"

";;\tslm sched_reorder: swap %d and %d insns\n"

Perform possible reodering of ready list for Atom/Silvermont only . Return issue rate .


<s> bool aarch64_split_128bit_move_p ( rtx dst , rtx src ) { return ( ! REG_P ( src ) || ! ( FP_REGNUM_P ( REGNO ( dst ) ) && FP_REGNUM_P ( REGNO ( src ) ) ) ) ; } </s>

Return true if we should split a move from 128-bit value SRC to 128-bit register DEST .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const Thumb1RegisterInfo & MRI , int NumBytes ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , TII , MRI ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> Sparc :: Fixups getFixupKind ( ) const { return getFixupKind ( Kind ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return getFramePointerReg ( STI ) ; return ARM :: SP ; } </s>


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
Reg
)
;
if
(
STI
.
getFeatureBits
(
)
[
ARM
::
HasMVEIntegerOps
]
)
return
RegNo
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s>
void
dump
(
)
{
errs
(
)
<<
"XNCMISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
0
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

XNCM
"XNCMISelAddressMode "
0
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s> bool vax_maybe_split_dimode_move ( rtx * operands ) { return ( TARGET_QMATH && ( ! MEM_P ( operands [ 0 ] ) || GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) == PRE_DEC || GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) == POST_INC || ! illegal_addsub_di_memory_operand ( operands [ 0 ] , DImode ) ) && ( ( CONST_INT_P ( operands [ 1 ] ) && ( unsigned HOST_WIDE_INT ) INTVAL ( operands [ 1 ] ) >= 64 ) || GET_CODE ( operands [ 1 ] ) == CONST_DOUBLE ) ) ; } </s>


<s> const PPCSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"too many opcodes for __aeabi_unwind_cpp_pr0"

Finalize the unwind opcode sequence for emitBytes ( )


" (e.g. %<-mfloat-abi=softfp%> %<-mfpu=neon%>)"

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s> void gen_shifty_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; value = value & 31 ; if ( value == 31 ) { if ( code == LSHIFTRT ) { emit_insn ( gen_rotlsi3_1 ( operands [ 0 ] , operands [ 0 ] ) ) ; emit_insn ( gen_movt ( operands [ 0 ] , get_t_reg_rtx ( ) ) ) ; return ; } else if ( code == ASHIFT ) { if ( REG_P ( operands [ 0 ] ) && REGNO ( operands [ 0 ] ) == 0 ) { emit_insn ( gen_andsi3 ( operands [ 0 ] , operands [ 0 ] , const1_rtx ) ) ; emit_insn ( gen_rotlsi3_31 ( operands [ 0 ] , operands [ 0 ] ) ) ; return ; } } } else if ( value == 0 ) { emit_insn ( gen_rtx_SET ( operands [ 0 ] , operands [ 0 ] ) ) ; return ; } max = ashl_lshr_seq [ value ] . insn_count ; for ( i = 0 ; i < max ; i ++ ) gen_ashift ( code , ashl_lshr_seq [ value ] . amount [ i ] , operands [ 0 ] ) ; } </s>

Output RTL to split a constant shift into its component SH constant shift instructions .


<s> static void mmix_file_end ( void ) { data_section ( ) ; } </s>


<s>
char
*
rx_gen_move_template
(
rtx
*
operands
,
bool
is_movu
)
{
static
char
out_template
[
64
]
;
const
char
*
extension
=
TARGET_AS100_SYNTAX
".L"
:
""
;
const
char
*
src_template
;
const
char
*
dst_template
;
rtx
dest
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
switch
(
CONST_INT_P
(
src
)
GET_MODE
(
dest
)
:
GET_MODE
(
src
)
)
{
case
QImode
:
if
(
!
REG_P
(
dest
)
||
!
CONST_INT_P
(
src
)
)
extension
=
".B"
;
break
;
case
HImode
:
if
(
!
REG_P
(
dest
)
||
!
CONST_INT_P
(
src
)
)
extension
=
".W"
;
break
;
case
DFmode
:
case
DImode
:
case
SFmode
:
case
SImode
:
extension
=
".L"
;
break
;
case
VOIDmode
:
break
;
default
:
debug_rtx
(
src
)
;
gcc_unreachable
(
)
;
}
if
(
MEM_P
(
src
)
&&
rx_pid_data_operand
(
XEXP
(
src
,
0
)
)
==
PID_UNENCODED
)
{
gcc_assert
(
GET_MODE
(
src
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
src
)
!=
DFmode
)
;
src_template
=
"(%A1 - __pid_base)[%P1]"
;
}
else
if
(
MEM_P
(
src
)
&&
rx_small_data_operand
(
XEXP
(
src
,
0
)
)
)
{
gcc_assert
(
GET_MODE
(
src
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
src
)
!=
DFmode
)
;
src_template
=
"%%gp(%A1)[%G1]"
;
}
else
src_template
=
"%1"
;
if
(
MEM_P
(
dest
)
&&
rx_small_data_operand
(
XEXP
(
dest
,
0
)
)
)
{
gcc_assert
(
GET_MODE
(
dest
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
dest
)
!=
DFmode
)
;
dst_template
=
"%%gp(%A0)[%G0]"
;
}
else
dst_template
=
"%0"
;
if
(
GET_MODE
(
dest
)
==
DImode
||
GET_MODE
(
dest
)
==
DFmode
)
{
gcc_assert
(
!
is_movu
)
;
if
(
REG_P
(
src
)
&&
REG_P
(
dest
)
&&
(
REGNO
(
dest
)
==
REGNO
(
src
)
+
1
)
)
sprintf
(
out_template
,
"mov.L\t%%H1, %%H0 ! mov.L\t%%1, %%0"
)
;
else
sprintf
(
out_template
,
"mov.L\t%%1, %%0 ! mov.L\t%%H1, %%H0"
)
;
}
else
sprintf
(
out_template
,
"%s%s\t%s, %s"
,
is_movu
"movu"
:
"mov"
,
extension
,
src_template
,
dst_template
)
;
return
out_template
;
}
</s>

Returns an assembler template for a move instruction .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = static_cast < const ARMTargetMachine & > ( TM ) . TargetABI == ARMTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI && ! Triple ( TM . getTargetTriple ( ) ) . isOSNaCl ( ) ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; } </s>

This method must be called before any actual lowering is done .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void PPCRegisterInfo :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> hasCalls ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = PPCFrameInfo :: getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> const DLXMCExpr * DLXMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) DLXMCExpr ( Kind , Expr ) ; } </s>


<s> void ix86_expand_unary_operator ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { int matching_memory ; rtx src , dst , op , clob ; dst = operands [ 0 ] ; src = operands [ 1 ] ; matching_memory = 0 ; if ( MEM_P ( dst ) ) { if ( rtx_equal_p ( dst , src ) ) matching_memory = 1 ; else dst = gen_reg_rtx ( mode ) ; } if ( MEM_P ( src ) && ! matching_memory ) src = force_reg ( mode , src ) ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_e ( code , mode , src ) ) ; if ( reload_in_progress || code == NOT ) { gcc_assert ( code == NOT ) ; emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a unary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 2 separate memory references ( one output , one input ) in a single insn .


<s> static rtx rs6000_parallel_return ( machine_mode mode , int n_elts , machine_mode elt_mode , unsigned int regno , unsigned int reg_stride ) { rtx par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( n_elts ) ) ; int i ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx r = gen_rtx_REG ( elt_mode , regno ) ; rtx off = GEN_INT ( i * GET_MODE_SIZE ( elt_mode ) ) ; XVECEXP ( par , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; regno += reg_stride ; } return par ; } </s>

Return an rtx describing a return value of MODE as a PARALLEL in N_ELTS registers , each of mode ELT_MODE , starting at REGNO , stride REG_STRIDE .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


"cannot return value in vector register because"

" altivec instructions are disabled, use -maltivec"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - MF . getTarget ( ) . getSubtarget < SparcSubtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc Sparc Sparc Sparc Sparc Sparc SP::SAVEri SP::SAVErr 0 SP::ADDri SP::ADDrr Sparc SP SP::I6 SP::I7 SP::O7


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool ARMSubtarget :: enableMachineScheduler ( ) const { if ( isMClass ( ) && hasMinSize ( ) ) return false ; return useMachineScheduler ( ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> bool PPCSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; if ( isPPC64 ( ) ) CriticalPathRCs . push_back ( & PPC :: G8RCRegClass ) ; else CriticalPathRCs . push_back ( & PPC :: GPRCRegClass ) ; CriticalPathRCs . push_back ( & PPC :: F8RCRegClass ) ; CriticalPathRCs . push_back ( & PPC :: VRRCRegClass ) ; return OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .

PowerPC PPC PPC PPC::G8RCRegClass PPC::GPRCRegClass PPC::F8RCRegClass PPC::VRRCRegClass


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned ADDu = ABI . GetPtrAdduOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
unsigned
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
unsigned
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> int arm_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( TARGET_32BIT ) { if ( ( IS_VFP_CLASS ( from ) && ! IS_VFP_CLASS ( to ) ) || ( ! IS_VFP_CLASS ( from ) && IS_VFP_CLASS ( to ) ) ) return 15 ; else if ( ( from == IWMMXT_REGS && to != IWMMXT_REGS ) || ( from != IWMMXT_REGS && to == IWMMXT_REGS ) ) return 4 ; else if ( from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS ) return 20 ; else return 2 ; } else { if ( from == HI_REGS || to == HI_REGS ) return 4 ; else return 2 ; } } </s>

Implement TARGET_REGISTER_MOVE_COST . Moves between VFP_REGS and GENERAL_REGS are a single insn , but it is typically more expensive than a single memory access . We set the cost to less than two memory accesses so that floating point to integer conversion does not go through memory .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> poly_int64 xstormy16_push_rounding ( poly_int64 bytes ) { return ( bytes + 1 ) & ~ 1 ; } </s>


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_aarch64_override_tune_string = opts -> x_aarch64_override_tune_string ; } </s>


Finalize stack_realign_needed flag , which will guide prologue/epilogue to be generated in correct form .


"the destination register can't equal the base register in an "

"instruction that modifies the base register."

ParseInstruction - Parse one assembly instruction .


<s> static enum rs6000_reg_type register_to_reg_type ( rtx reg , bool * is_altivec ) { HOST_WIDE_INT regno ; enum reg_class rclass ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; if ( ! REG_P ( reg ) ) return NO_REG_TYPE ; regno = REGNO ( reg ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { if ( ! lra_in_progress && ! reload_in_progress && ! reload_completed ) return PSEUDO_REG_TYPE ; regno = true_regnum ( reg ) ; if ( regno < 0 || regno >= FIRST_PSEUDO_REGISTER ) return PSEUDO_REG_TYPE ; } gcc_assert ( regno >= 0 ) ; if ( is_altivec && ALTIVEC_REGNO_P ( regno ) ) * is_altivec = true ; rclass = rs6000_regno_regclass [ regno ] ; return reg_class_to_reg_type [ ( int ) rclass ] ; } </s>

Classify a register type . Because the FMRGOW/FMRGEW instructions only work on traditional floating point registers , and the VMRGOW/VMRGEW instructions only work on the traditional altivec registers , note if an altivec register was chosen .


"%qE attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s>
unsigned
CAHPMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style ) { rtx insn ; if ( ! TARGET_64BIT ) insn = emit_insn ( gen_pro_epilogue_adjust_stack_1 ( dest , src , offset ) ) ; else if ( x86_64_immediate_operand ( offset , DImode ) ) insn = emit_insn ( gen_pro_epilogue_adjust_stack_rex64 ( dest , src , offset ) ) ; else { rtx r11 ; gcc_assert ( style ) ; r11 = gen_rtx_REG ( DImode , FIRST_REX_INT_REG + 3 ) ; insn = emit_insn ( gen_rtx_SET ( DImode , r11 , offset ) ) ; if ( style < 0 ) RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_pro_epilogue_adjust_stack_rex64_2 ( dest , src , r11 , offset ) ) ; } if ( style < 0 ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


<s> bool shouldConvertFpToSat ( unsigned Op , EVT FPVT , EVT VT ) const override { return Op != ISD :: FP_TO_UINT_SAT && isOperationLegalOrCustom ( Op , VT ) ; } </s>

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min ( max ( fptoi ) ) saturation patterns .


<s> int pa_shadd_constant_p ( int val ) { if ( val == 1 || val == 2 || val == 3 ) return 1 ; else return 0 ; } </s>

Return 1 if the given constant is 2 , 4 , or 8 . These are the valid constants for shadd instructions .


<s> static void or1k_compute_frame_layout ( void ) { HOST_WIDE_INT local_vars_size , args_size , save_reg_size ; local_vars_size = get_frame_size ( ) ; local_vars_size = ROUND_UP ( local_vars_size , UNITS_PER_WORD ) ; args_size = crtl -> outgoing_args_size ; args_size = ROUND_UP ( args_size , UNITS_PER_WORD ) ; save_reg_size = 0 ; for ( int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( callee_saved_regno_p ( regno ) ) save_reg_size += UNITS_PER_WORD ; cfun -> machine -> local_vars_size = local_vars_size ; cfun -> machine -> args_size = args_size ; cfun -> machine -> callee_saved_reg_size = save_reg_size ; cfun -> machine -> total_size = save_reg_size + local_vars_size + args_size ; } </s>

Worker for TARGET_COMPUTE_FRAME_LAYOUT . Compute and populate machine specific function attributes which are globally accessible via cfun- > machine . These include the sizes needed for stack stored local variables , callee saved registers and space for stack arguments which may be passed to a next function . The values are used for the epilogue , prologue and eliminations . OpenRISC stack grows downwards and contains : -- -- previous frame -- -- -- -- current func arg [ n ] current func arg [ 0 ] < -- r2 [ HFP , AP ] -- -- current stack frame -- - ^ -- -\ return address r9 | | old frame pointer r2 ( + ) | -- machine- > total_size callee saved regs | | > machine- > callee_saved_reg_size local variables | | > machine- > local_vars_size < -FP next function args < -- r1 [ SP ] -- -/ > machine- > args_size -- -- -- -- -- -- -- -- -- -- -- -- -- -- | ( - ) ( future ) | V All of these contents are optional .


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMipsExpandPseudoPass ( ) ) ; addPass ( createMicroMipsSizeReducePass ( ) ) ; if ( EnableMulMulFix ) addPass ( createMipsMulMulBugPass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsBranchExpansion ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU64RegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
CPURegsRegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
CPU64RegsRegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
LORegsRegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
LORegs64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s>
bool
AArch64AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
&&
ExtraCode
[
0
]
!=
'a'
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
AArch64InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void TOYInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( TOY :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


Return the output template for emitting a dbra type insn . Note it may perform some output operations on its own before returning the final output string .


<s> unsigned ARMFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ARMMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return ARMMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return ARMMaterializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> void SVEVecStackRegion :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , uint64_t & AddedSize , unsigned & Basereg , uint64_t Offset ) const { if ( RegionSize == 0 ) return ; if ( CSRs . size ( ) == 0 ) { AddedSize += this -> getRegionSize ( ) ; return ; } bool BPChanged = false ; if ( CSRs . size ( ) > 0 && ( ( AddedSize + Offset ) - Scale ) > ( uint64_t ) Scale * 255 ) { Basereg = adjustRegBySVE ( MF , MBB , MBBI , DL , Basereg , AddedSize + Offset , true ) ; AddedSize = 0 ; Offset = 0 ; BPChanged = true ; } SaveRestoreSVEFromPointer ( MF , MBB , MBBI , DL , AddedSize + Offset , Basereg , false ) ; if ( ! BPChanged ) AddedSize += this -> getRegionSize ( ) ; } </s>


<s> bool AArch64InstrInfo :: isPreLd ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: LDRWpre : case AArch64 :: LDRXpre : case AArch64 :: LDRSpre : case AArch64 :: LDRDpre : case AArch64 :: LDRQpre : return true ; } } </s>

Returns whether the instruction is a pre-indexed load .


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn ) { PreAnalyzeFormalArgumentsForF128 ( Ins ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear ( ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .


"attribute %<target%> argument not a string"

"invalid fpu for attribute(target(\"%s\"))"

"auto fpu selection not currently permitted here"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> static machine_mode rs6000_preferred_simd_mode ( scalar_mode mode ) { opt_machine_mode vmode = mode_for_vector ( mode , 16 / GET_MODE_SIZE ( mode ) ) ; if ( vmode . exists ( ) && ! VECTOR_MEM_NONE_P ( vmode . require ( ) ) ) return vmode . require ( ) ; return word_mode ; } </s>


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

Perform target-specific instruction verification .


<s> const TargetRegisterClass * X86RegisterInfo :: getSubClassWithSubReg ( const TargetRegisterClass * RC , unsigned Idx ) const { if ( ! Is64Bit && Idx == X86 :: sub_8bit ) Idx = X86 :: sub_8bit_hi ; return X86GenRegisterInfo :: getSubClassWithSubReg ( RC , Idx ) ; } </s>

Returns the largest legal sub-class of RC that supports the sub-register index Idx .


<s> void split_double_mode ( machine_mode mode , rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { machine_mode half_mode ; unsigned int byte ; switch ( mode ) { case TImode : half_mode = DImode ; break ; case DImode : half_mode = SImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { lo_half [ num ] = adjust_address ( op , half_mode , 0 ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; } else { lo_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , byte ) ; } } } </s>

Split one or more double-mode RTL references into pairs of half-mode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of double-mode RTLs to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
getParser
(
)
.
setParsingInlineAsm
(
false
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
getParser
(
)
.
setParsingInlineAsm
(
true
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> static void sparc64_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , GEN_INT ( trunc_int_for_mode ( 0x83414000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , GEN_INT ( trunc_int_for_mode ( 0xca586018 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , GEN_INT ( trunc_int_for_mode ( 0x81c14000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , GEN_INT ( trunc_int_for_mode ( 0xca586010 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 16 ) , cxt ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 24 ) , fnaddr ) ; emit_insn ( gen_flush ( DImode , validize_mem ( adjust_address ( m_tramp , DImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 && sparc_cpu != PROCESSOR_NIAGARA7 && sparc_cpu != PROCESSOR_M8 ) emit_insn ( gen_flush ( DImode , validize_mem ( adjust_address ( m_tramp , DImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

The 64 bit version is simpler because it makes more sense to load the values as `` immediate '' data out of the trampoline . It 's also easier since we can read the PC without clobbering a register .


<s> void RegDefsUses :: init ( const MachineInstr & MI ) { update ( MI , 0 , MI . getDesc ( ) . getNumOperands ( ) ) ; if ( MI . isCall ( ) ) Defs . set ( Mips :: RA ) ; if ( MI . isBranch ( ) ) { update ( MI , MI . getDesc ( ) . getNumOperands ( ) , MI . getNumOperands ( ) ) ; Defs . reset ( Mips :: AT ) ; } } </s>

Initialize the machine model for instruction scheduling .


<s> void ARMInstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void MipsAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : case Mips :: fixup_MICROMIPS_PC10_S1 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static rtx_code_label * add_constant ( rtx x , machine_mode mode , rtx last_value ) { int i ; rtx_code_label * lab , * new_rtx ; label_ref_list_t ref , newref ; for ( i = 0 ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , 3 ) != XINT ( pool_vector [ i ] . value , 3 ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new_rtx = 0 ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - 1 ] . value ) ) { new_rtx = gen_label_rtx ( ) ; LABEL_REFS ( new_rtx ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new_rtx ; } if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new_rtx ) pool_window_label = new_rtx ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - 1 ] . value ) ) { lab = 0 ; pool_vector [ pool_size - 1 ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == 0 ) ; if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size ; pool_size ++ ; return lab ; } </s>

Add a constant to the pool and return its label .


<s> bool SystemZTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createSystemZISelDag ( * this , OptLevel ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> int single_const_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( big_const_operand ( op , mode ) || GET_CODE ( op ) == CONST || GET_CODE ( op ) == LABEL_REF || GET_CODE ( op ) == SYMBOL_REF ) return 0 ; return 1 ; } </s>

Return truth value of whether OP is a constant that require only one load to put in a register .


"Pointer Checker requires MPX support on this target."

Return mode to be used for bounds or VOIDmode if bounds are not supported .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ReachingDefAnalysis > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_74KC : case PROCESSOR_74KF2_1 : case PROCESSOR_74KF1_1 : case PROCESSOR_74KF3_2 : case PROCESSOR_R10000 : return 4 ; case PROCESSOR_20KC : case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R5900 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : case PROCESSOR_OCTEON : case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : return 2 ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return 3 ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_LOONGSON_3A : case PROCESSOR_P5600 : return 4 ; case PROCESSOR_XLP : return ( reload_completed ? 4 : 3 ) ; default : return 1 ; } } </s>

Return the number of instructions that can be issued per cycle .


<s> void SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) , false ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
llvm_report_error
(
"SSE register return with SSE disabled"
)
;
}
if
(
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
}
SDValue
Val
;
if
(
Is64Bit
&&
CopyVT
.
isVector
(
)
&&
CopyVT
.
getSizeInBits
(
)
==
64
)
{
if
(
VA
.
getLocReg
(
)
==
X86
::
XMM0
||
VA
.
getLocReg
(
)
==
X86
::
XMM1
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
v2i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
Val
=
DAG
.
getNode
(
ISD
::
EXTRACT_VECTOR_ELT
,
dl
,
MVT
::
i64
,
Val
,
DAG
.
getConstant
(
0
,
MVT
::
i64
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
Val
=
DAG
.
getNode
(
ISD
::
BIT_CONVERT
,
dl
,
CopyVT
,
Val
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
{
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static int mep_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { int cost_specified ; if ( REG_NOTE_KIND ( link ) != 0 ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT && global_reg_mentioned_p ( PATTERN ( insn ) ) && global_reg_mentioned_p ( PATTERN ( dep_insn ) ) ) return 1 ; return 0 ; } if ( recog_memoized ( dep_insn ) < 0 ) return cost ; if ( ! TARGET_H1 ) { cost_specified = get_attr_latency ( dep_insn ) ; if ( cost_specified != 0 ) return cost_specified ; } return cost ; } </s>

Scheduling hooks for VLIW mode . Conceptually this is very simple : we have a two-pack architecture that takes one core insn and one coprocessor insn to make up either a 32- or 64-bit instruction word ( depending on the option bit set in the chip ) . I.e . in VL32 mode , we can pack one 16-bit core insn and one 16-bit cop insn ; in VL64 mode we can pack one 16-bit core insn and one 48-bit cop insn or two 32-bit core/cop insns . In practice , instruction selection will be a bear . Consider in VL64 mode the following insns add $ 1 , 1 cmov $ cr0 , $ 0 these can not pack , since the add is a 16-bit core insn and cmov is a 32-bit cop insn . However , add3 $ 1 , $ 1 , 1 cmov $ cr0 , $ 0 packs just fine . For good VLIW code generation in VL64 mode , we will have to have 32-bit alternatives for many of the common core insns . Not implemented .


"\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "

"type = %d, ind_levels = %d, win = %d, original addr:\n"

Debug version of rs6000_legitimize_reload_address .


<s> static bool aarch64_tls_symbol_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; x = strip_salt ( x ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; return SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return true if SYMBOL_REF X is thread local


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case 'x' : return C_RegisterClass ; case 'R' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( parseOptionalToken ( AsmToken :: Plus ) ) { NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( parseOptionalToken ( AsmToken :: Minus ) ) { NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( parseOptionalToken ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( ! parseOptionalToken ( AsmToken :: EndOfStatement ) ) { if ( parseToken ( AsmToken :: Comma ) || ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { bool HasAtomicCmpXchg = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; if ( getTargetMachine ( ) . getOptLevel ( ) != 0 && HasAtomicCmpXchg ) return AtomicExpansionKind :: LLSC ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> bool AArch64TargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s>
void
ARM64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & CmpMask , int64_t & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : case ARM :: tCMPi8 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : case ARM :: tCMPr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVSX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> static rtx ldv_expand_builtin ( rtx target , insn_code icode , rtx * op , machine_mode tmode ) { if ( target == 0 || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; bool blk = ( icode == CODE_FOR_altivec_lvlx || icode == CODE_FOR_altivec_lvlxl || icode == CODE_FOR_altivec_lvrx || icode == CODE_FOR_altivec_lvrxl ) ; if ( icode == CODE_FOR_altivec_lvx_v1ti || icode == CODE_FOR_altivec_lvx_v2df || icode == CODE_FOR_altivec_lvx_v2di || icode == CODE_FOR_altivec_lvx_v4sf || icode == CODE_FOR_altivec_lvx_v4si || icode == CODE_FOR_altivec_lvx_v8hi || icode == CODE_FOR_altivec_lvx_v16qi ) { rtx rawaddr ; if ( op [ 0 ] == const0_rtx ) rawaddr = op [ 1 ] ; else { op [ 0 ] = copy_to_mode_reg ( Pmode , op [ 0 ] ) ; rawaddr = gen_rtx_PLUS ( Pmode , op [ 1 ] , op [ 0 ] ) ; } rtx addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - 16 ) ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode , addr ) ; emit_insn ( gen_rtx_SET ( target , addr ) ) ; } else { rtx addr ; if ( op [ 0 ] == const0_rtx ) addr = gen_rtx_MEM ( blk ? BLKmode : tmode , op [ 1 ] ) ; else { op [ 0 ] = copy_to_mode_reg ( Pmode , op [ 0 ] ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode , gen_rtx_PLUS ( Pmode , op [ 1 ] , op [ 0 ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; } return target ; } </s>

Expand an AltiVec vector load builtin , and return the expanded rtx .


<s> rtx loongarch_rewrite_small_data ( rtx pattern ) { pattern = copy_insn ( pattern ) ; loongarch_rewrite_small_data_1 ( & pattern ) ; return pattern ; } </s>

Rewrite instruction pattern PATTERN so that it refers to small data using explicit relocations .


<s> static void rws_update ( int regno , struct reg_flags flags , int pred ) { if ( pred ) rws_sum [ regno ] . write_count ++ ; else rws_sum [ regno ] . write_count = 2 ; rws_sum [ regno ] . written_by_fp |= flags . is_fp ; rws_sum [ regno ] . written_by_and = flags . is_and ; rws_sum [ regno ] . written_by_or = flags . is_or ; rws_sum [ regno ] . first_pred = pred ; } </s>

Update * RWS for REGNO , which is being written by the current instruction , with predicate PRED , and associated register flags in FLAGS .


<s> unsigned SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ; } </s>


<s> unsigned PPCTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == MVT :: f64 ) return 2 ; return PPCTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static inline int shiftcosts ( rtx x ) { if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) == 1 ) return 2 ; return - 1 ; } if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return SH_DYNAMIC_SHIFT_COST ; int value = INTVAL ( XEXP ( x , 1 ) ) & 31 ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > 1 + SH_DYNAMIC_SHIFT_COST ) cost = 1 + SH_DYNAMIC_SHIFT_COST ; return cost ; } else return ashl_lshr_seq [ value ] . insn_count ; } </s>


<s>
static
void
arm_unwind_emit_set
(
FILE
*
asm_out_file
,
rtx
p
)
{
rtx
e0
;
rtx
e1
;
e0
=
XEXP
(
p
,
0
)
;
e1
=
XEXP
(
p
,
1
)
;
switch
(
GET_CODE
(
e0
)
)
{
case
MEM
:
if
(
GET_CODE
(
XEXP
(
e0
,
0
)
)
!=
PRE_DEC
||
GET_CODE
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
!=
REG
||
REGNO
(
XEXP
(
XEXP
(
e0
,
0
)
,
0
)
)
!=
SP_REGNUM
)
abort
(
)
;
asm_fprintf
(
asm_out_file
,
"\t.save "
)
;
if
(
IS_VFP_REGNUM
(
REGNO
(
e1
)
)
)
asm_fprintf
(
asm_out_file
,
"{d%d}\n"
,
(
REGNO
(
e1
)
FIRST_VFP_REGNUM
)
/
2
)
;
else
asm_fprintf
(
asm_out_file
,
"{%r}\n"
,
REGNO
(
e1
)
)
;
break
;
case
REG
:
if
(
REGNO
(
e0
)
==
SP_REGNUM
)
{
if
(
GET_CODE
(
e1
)
!=
PLUS
||
GET_CODE
(
XEXP
(
e1
,
0
)
)
!=
REG
||
REGNO
(
XEXP
(
e1
,
0
)
)
!=
SP_REGNUM
||
GET_CODE
(
XEXP
(
e1
,
1
)
)
!=
CONST_INT
)
abort
(
)
;
asm_fprintf
(
asm_out_file
,
"\t.pad #%wd\n"
,
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
REGNO
(
e0
)
==
HARD_FRAME_POINTER_REGNUM
)
{
HOST_WIDE_INT
offset
;
unsigned
reg
;
if
(
GET_CODE
(
e1
)
==
PLUS
)
{
if
(
GET_CODE
(
XEXP
(
e1
,
0
)
)
!=
REG
||
GET_CODE
(
XEXP
(
e1
,
1
)
)
!=
CONST_INT
)
abort
(
)
;
reg
=
REGNO
(
XEXP
(
e1
,
0
)
)
;
offset
=
INTVAL
(
XEXP
(
e1
,
1
)
)
;
asm_fprintf
(
asm_out_file
,
"\t.setfp %r, %r, #%wd\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
,
INTVAL
(
XEXP
(
e1
,
1
)
)
)
;
}
else
if
(
GET_CODE
(
e1
)
==
REG
)
{
reg
=
REGNO
(
e1
)
;
asm_fprintf
(
asm_out_file
,
"\t.setfp %r, %r\n"
,
HARD_FRAME_POINTER_REGNUM
,
reg
)
;
}
else
abort
(
)
;
}
else
if
(
GET_CODE
(
e1
)
==
REG
&&
REGNO
(
e1
)
==
SP_REGNUM
)
{
asm_fprintf
(
asm_out_file
,
"\t.movsp %r\n"
,
REGNO
(
e0
)
)
;
}
else
abort
(
)
;
break
;
default
:
abort
(
)
;
}
}
</s>


<s> static int try_issue_insn ( struct bundle_state * curr_state , rtx insn ) { if ( insn && state_transition ( curr_state -> dfa_state , insn ) >= 0 ) { free_bundle_state ( curr_state ) ; return FALSE ; } return TRUE ; } </s>

The following function tries to issue INSN for the current state without advancing processor cycle . If it failed , the function returns FALSE and frees the current state .