<s> void xstormy16_expand_move ( machine_mode mode , rtx dest , rtx src ) { if ( MEM_P ( dest ) && ( GET_CODE ( XEXP ( dest , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( dest , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( dest_reg , dest_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; dest = gen_rtx_MEM ( mode , dest_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else if ( MEM_P ( src ) && ( GET_CODE ( XEXP ( src , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( src , 0 ) ; rtx src_reg = XEXP ( pmv , 0 ) ; rtx src_mod = XEXP ( pmv , 1 ) ; rtx set = gen_rtx_SET ( src_reg , src_mod ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && MEM_P ( dest ) && ( ! CONST_INT_P ( XEXP ( dest , 0 ) ) || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , 0 ) , 0 ) ) && ! xstormy16_below100_operand ( dest , mode ) && ! REG_P ( src ) && GET_CODE ( src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ; if ( reload_completed && mode != HImode && mode != QImode ) { xstormy16_split_move ( mode , dest , src ) ; return ; } emit_insn ( gen_rtx_SET ( dest , src ) ) ; } </s>

Expander for the 'move ' patterns . Emit insns to copy a value of mode MODE from SRC to DEST .


<s> void MipsTargetStreamer :: emitStoreWithImmOffset ( unsigned Opcode , unsigned SrcReg , unsigned BaseReg , int64_t Offset , std :: function < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { if ( isInt < 16 > ( Offset ) ) { emitRRI ( Opcode , SrcReg , BaseReg , Offset , IDLoc , STI ) ; return ; } unsigned ATReg = GetATReg ( ) ; if ( ! ATReg ) return ; unsigned LoOffset = Offset & 0x0000ffff ; unsigned HiOffset = ( Offset & 0xffff0000 ) >> 16 ; if ( LoOffset & 0x8000 ) HiOffset ++ ; emitRI ( Mips :: LUi , ATReg , HiOffset , IDLoc , STI ) ; if ( BaseReg != Mips :: ZERO ) emitRRR ( Mips :: ADDu , ATReg , ATReg , BaseReg , IDLoc , STI ) ; emitRRI ( Opcode , SrcReg , ATReg , LoOffset , IDLoc , STI ) ; } </s>

Emit a store instruction with an offset .


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> perm . length ( ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; if ( d -> vmode == E_DImode ) return false ; emit_insn ( gen_neon_vext ( d -> vmode , d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> static bool pru_valid_const_ubyte_offset ( machine_mode mode , HOST_WIDE_INT offset ) { bool valid = UBYTE_INT ( offset ) ; if ( valid && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SImode ) ) valid = UBYTE_INT ( offset + GET_MODE_SIZE ( mode ) - 1 ) ; return valid ; } </s>

Return true if given xbbo constant OFFSET is valid .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".hword" ) parseDirectiveWord ( 2 , Loc ) ; else if ( IDVal == ".word" ) parseDirectiveWord ( 4 , Loc ) ; else if ( IDVal == ".xword" ) parseDirectiveWord ( 8 , Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else return true ; } else if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , 257 ) ; } else { unsigned Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> bool ARMBaseRegisterInfo :: isInlineAsmReadOnlyReg ( const MachineFunction & MF , unsigned PhysReg ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , ARM :: PC ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , STI . getFramePointerReg ( ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved . test ( PhysReg ) ; } </s>

Returns true if PhysReg can not be written to in inline asm statements .


<s> static rtx ia64_function_incoming_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { return ia64_function_arg_1 ( cum , mode , type , named , true ) ; } </s>

Implement TARGET_FUNCION_INCOMING_ARG target hook .


<s> static machine_mode mips_dwarf_frame_reg_mode ( int regno ) { machine_mode mode = default_dwarf_frame_reg_mode ( regno ) ; if ( FP_REG_P ( regno ) && mips_abi == ABI_32 && TARGET_FLOAT64 ) mode = SImode ; return mode ; } </s>


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { KnownBits Known2 ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known , Depth + 1 ) ; DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known2 , Depth + 1 ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
case
Mips
::
BEQZC_MM
:
return
Mips
::
BNEZC_MM
;
case
Mips
::
BNEZC_MM
:
return
Mips
::
BEQZC_MM
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> bool mips16e_save_restore_pattern_p ( rtx pattern , HOST_WIDE_INT adjust , struct mips16e_save_restore_info * info ) { unsigned int i , nargs , mask , extra ; HOST_WIDE_INT top_offset , save_offset , offset ; rtx set , reg , mem , base ; int n ; if ( ! GENERATE_MIPS16E_SAVE_RESTORE ) return false ; top_offset = adjust > 0 ? adjust : 0 ; save_offset = top_offset - UNITS_PER_WORD ; mask = 0 ; nargs = 0 ; i = 0 ; for ( n = 1 ; n < XVECLEN ( pattern , 0 ) ; n ++ ) { set = XVECEXP ( pattern , 0 , n ) ; if ( GET_CODE ( set ) != SET ) return false ; mem = adjust > 0 ? SET_SRC ( set ) : SET_DEST ( set ) ; if ( ! MEM_P ( mem ) ) return false ; mips_split_plus ( XEXP ( mem , 0 ) , & base , & offset ) ; if ( base != stack_pointer_rtx ) return false ; reg = adjust > 0 ? SET_DEST ( set ) : SET_SRC ( set ) ; if ( ! REG_P ( reg ) ) return false ; if ( offset == top_offset + nargs * UNITS_PER_WORD && REGNO ( reg ) == GP_ARG_FIRST + nargs ) nargs ++ ; else if ( offset == save_offset ) { while ( mips16e_save_restore_regs [ i ++ ] != REGNO ( reg ) ) if ( i == ARRAY_SIZE ( mips16e_save_restore_regs ) ) return false ; mask |= 1 << REGNO ( reg ) ; save_offset -= UNITS_PER_WORD ; } else return false ; } extra = 0 ; mips16e_mask_registers ( & mask , mips16e_s2_s8_regs , ARRAY_SIZE ( mips16e_s2_s8_regs ) , & extra ) ; mips16e_mask_registers ( & mask , mips16e_a0_a3_regs , ARRAY_SIZE ( mips16e_a0_a3_regs ) , & extra ) ; if ( extra != 0 ) return false ; if ( nargs > 0 && BITSET_P ( mask , GP_ARG_FIRST + nargs - 1 ) ) return false ; if ( info ) { info -> nargs = nargs ; info -> mask = mask ; info -> size = ( adjust > 0 ? adjust : - adjust ) ; } return true ; } </s>

PATTERN is a PARALLEL whose first element adds ADJUST to the stack pointer . Return true if PATTERN matches the kind of instruction generated by mips16e_build_save_restore . If INFO is nonnull , initialize it when returning true .


<s> const MCExpr * X86_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( ( Encoding & DW_EH_PE_indirect ) && ( Encoding & DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( 4 , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) == ARMISD :: VMOVRRD ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , 2 > Copies ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies . insert ( * UI ) ; } if ( Copies . size ( ) > 2 ) return false ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { SDValue UseChain = UI -> getOperand ( 0 ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = * UI ; else TCChain = UseChain ; } } else if ( Copy -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != ISD :: CopyToReg || ! Copy -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Chain = Copy -> getOperand ( 0 ) ; } else { return false ; } bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


See whether TYPE is a record whose fields should be returned in one floating-point register and one integer register . If so , populate FIELDS accordingly .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


"passing %qT to argument %d of %qE, which"

" expects a single SVE vector rather than a tuple"

"passing single vector %qT to argument %d"

" of %qE, which expects a tuple of %d vectors"

Require argument ARGNO to be a single vector or a tuple of NUM_VECTORS vectors ; NUM_VECTORS is 1 for the former . Return the associated type suffix on success , using TYPE_SUFFIX_b for predicates . Report an error and return NUM_TYPE_SUFFIXES on failure .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - ( STI -> isTargetDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void ARMTargetStreamer :: emitCurrentConstantPool ( ) { ConstantPools -> emitForCurrentSection ( Streamer ) ; } </s>

Callback used to implement the .ltorg directive .


"Lanai DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> TargetPassConfig * DigitalTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new DigitalPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const TargetFrameLowering :: SpillSlot * SystemZFrameLowering :: getCalleeSavedSpillSlots ( unsigned & NumEntries ) const { NumEntries = array_lengthof ( SpillOffsetTable ) ; return SpillOffsetTable ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> bool isThumb ( const MCSubtargetInfo & STI ) const { return ( STI . getFeatureBits ( ) & ARM :: ModeThumb ) != 0 ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( isDarwin ( ) ) { if ( IDVal == ".machine" ) ParseDarwinDirectiveMachine ( DirectiveID . getLoc ( ) ) ; else return true ; } else if ( IDVal == ".word" ) ParseDirectiveWord ( 2 , DirectiveID ) ; else if ( IDVal == ".llong" ) ParseDirectiveWord ( 8 , DirectiveID ) ; else if ( IDVal == ".tc" ) ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID ) ; else if ( IDVal == ".machine" ) ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".abiversion" ) ParseDirectiveAbiVersion ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".localentry" ) ParseDirectiveLocalEntry ( DirectiveID . getLoc ( ) ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? support :: endian :: read32le ( Bytes . data ( ) ) : support :: endian :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; MI . clear ( ) ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool ix86_tls_address_pattern_p ( rtx op ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , op , ALL ) { rtx op = * iter ; if ( MEM_P ( op ) ) { rtx * x = & XEXP ( op , 0 ) ; while ( GET_CODE ( * x ) == PLUS ) { int i ; for ( i = 0 ; i < 2 ; i ++ ) { rtx u = XEXP ( * x , i ) ; if ( GET_CODE ( u ) == ZERO_EXTEND ) u = XEXP ( u , 0 ) ; if ( GET_CODE ( u ) == UNSPEC && XINT ( u , 1 ) == UNSPEC_TP ) return true ; } x = & XEXP ( * x , 0 ) ; } iter . skip_subrtxes ( ) ; } } return false ; } </s>

Return true if OP refers to a TLS address .


<s> Reloc :: Model MipsSubtarget :: getRelocationModel ( ) const { return TM . getRelocationModel ( ) ; } </s>

Returns the code generation relocation model .


<s> bool quad_address_p ( rtx addr , machine_mode mode , bool strict ) { rtx op0 , op1 ; if ( GET_MODE_SIZE ( mode ) != 16 ) return false ; if ( legitimate_indirect_address_p ( addr , strict ) ) return true ; if ( VECTOR_MODE_P ( mode ) && ! mode_supports_vsx_dform_quad ( mode ) ) return false ; if ( GET_CODE ( addr ) != PLUS ) return false ; op0 = XEXP ( addr , 0 ) ; if ( ! REG_P ( op0 ) || ! INT_REG_OK_FOR_BASE_P ( op0 , strict ) ) return false ; op1 = XEXP ( addr , 1 ) ; if ( ! CONST_INT_P ( op1 ) ) return false ; return quad_address_offset_p ( INTVAL ( op1 ) ) ; } </s>

Return true if the ADDR is an acceptable address for a quad memory operation of mode MODE ( either LQ/STQ for general purpose registers , or LXV/STXV for vector registers under ISA 3.0 . GPR_P is true if this address is intended for LQ/STQ . If it is false , the address is intended for the ISA 3.0 LXV/STXV instruction .


<s>
void
Finish
(
)
{
const
size_t
VendorHeaderSize
=
4
+
CurrentVendor
.
size
(
)
+
1
;
const
size_t
TagHeaderSize
=
1
+
4
;
Streamer
.
EmitIntValue
(
VendorHeaderSize
+
TagHeaderSize
+
ContentsSize
,
4
)
;
Streamer
.
EmitBytes
(
CurrentVendor
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
Streamer
.
EmitIntValue
(
ARMBuildAttrs
::
File
,
1
)
;
Streamer
.
EmitIntValue
(
TagHeaderSize
+
ContentsSize
,
4
)
;
for
(
unsigned
int
i
=
0
;
i
<
Contents
.
size
(
)
;
++
i
)
{
AttributeItemType
item
=
Contents
[
i
]
;
Streamer
.
EmitULEB128IntValue
(
item
.
Tag
,
0
)
;
switch
(
item
.
Type
)
{
default
:
llvm_unreachable
(
"Invalid attribute type"
)
;
case
AttributeItemType
::
NumericAttribute
:
Streamer
.
EmitULEB128IntValue
(
item
.
IntValue
,
0
)
;
break
;
case
AttributeItemType
::
TextAttribute
:
Streamer
.
EmitBytes
(
item
.
StringValue
.
upper
(
)
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
break
;
}
}
Contents
.
clear
(
)
;
}
</s>

Finish - Do final processing and write the object to the output stream .


<s> bool mep_secondary_memory_needed ( enum reg_class rclass1 , enum reg_class rclass2 , machine_mode mode ATTRIBUTE_UNUSED ) { if ( ! mep_have_core_copro_moves_p ) { if ( reg_classes_intersect_p ( rclass1 , CR_REGS ) && reg_classes_intersect_p ( rclass2 , GENERAL_REGS ) ) return true ; if ( reg_classes_intersect_p ( rclass2 , CR_REGS ) && reg_classes_intersect_p ( rclass1 , GENERAL_REGS ) ) return true ; if ( ! mep_have_copro_copro_moves_p && reg_classes_intersect_p ( rclass1 , CR_REGS ) && reg_classes_intersect_p ( rclass2 , CR_REGS ) ) return true ; } return false ; } </s>


<s> void UnwindOpcodeAssembler :: EmitRegSave ( uint32_t RegSave ) { if ( RegSave == 0u ) return ; if ( RegSave & ( 1u << 4 ) ) { uint32_t Mask = RegSave & 0xff0u ; uint32_t Range = countTrailingOnes ( Mask >> 5 ) ; Mask &= ~ ( 0xffffffe0u << Range ) ; uint32_t UnmaskedReg = RegSave & 0xfff0u & ( ~ Mask ) ; if ( UnmaskedReg == 0u ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4 | Range ) ; RegSave &= 0x000fu ; } else if ( UnmaskedReg == ( 1u << 14 ) ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range ) ; RegSave &= 0x000fu ; } } if ( ( RegSave & 0xfff0u ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK_R4 | ( RegSave >> 4 ) ) ; if ( ( RegSave & 0x000fu ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK | ( RegSave & 0x000fu ) ) ; } </s>

Emit unwind opcodes for .save directives .


<s> unsigned int mips_case_values_threshold ( void ) { if ( TARGET_MIPS16 && optimize_size ) return 10 ; else return default_case_values_threshold ( ) ; } </s>


<s> void TOYInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { } </s>


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 branch fixup pass"
;
}
</s>


<s> MipsInstrInfo :: BranchType MipsInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify , SmallVectorImpl < MachineInstr * > & BranchInstrs ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return BT_NoBranch ; } MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_CondUncond ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> SDValue X86SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= 256 || SrcPtrInfo . getAddrSpace ( ) >= 256 ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: ECX , X86 :: ESI , X86 :: EDI } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; const X86Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < X86Subtarget > ( ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Align , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> unsigned SparcInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { SparcMachineFunctionInfo * SparcFI = MF -> getInfo < SparcMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = SparcFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & SP :: IntRegsRegClass ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( SP :: GETPCX ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Sparc Sparc Sparc Sparc Sparc Sparc 0 SP::IntRegsRegClass SP::GETPCX Sparc


<s> static unsigned int ix86_minimum_incoming_stack_boundary ( bool sibcall ) { unsigned int incoming_stack_boundary ; if ( cfun -> machine -> func_type != TYPE_NORMAL ) incoming_stack_boundary = TARGET_64BIT ? 128 : MIN_STACK_BOUNDARY ; else if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == 128 ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ; if ( incoming_stack_boundary > MIN_STACK_BOUNDARY && lookup_attribute ( "force_align_arg_pointer" , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; if ( incoming_stack_boundary < crtl -> parm_stack_boundary ) incoming_stack_boundary = crtl -> parm_stack_boundary ; if ( incoming_stack_boundary > MAIN_STACK_BOUNDARY && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) incoming_stack_boundary = MAIN_STACK_BOUNDARY ; return incoming_stack_boundary ; } </s>

Return minimum incoming stack alignment .


<s> void gen_shifty_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; value = value & 31 ; if ( value == 31 ) { if ( code == LSHIFTRT ) { emit_insn ( gen_rotlsi3_1 ( operands [ 0 ] , operands [ 0 ] ) ) ; emit_insn ( gen_movt ( operands [ 0 ] , get_t_reg_rtx ( ) ) ) ; return ; } else if ( code == ASHIFT ) { if ( REG_P ( operands [ 0 ] ) && REGNO ( operands [ 0 ] ) == 0 ) { emit_insn ( gen_andsi3 ( operands [ 0 ] , operands [ 0 ] , const1_rtx ) ) ; emit_insn ( gen_rotlsi3_31 ( operands [ 0 ] , operands [ 0 ] ) ) ; return ; } } } else if ( value == 0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , operands [ 0 ] ) ) ; return ; } max = ashl_lshr_seq [ value ] . insn_count ; for ( i = 0 ; i < max ; i ++ ) gen_ashift ( code , ashl_lshr_seq [ value ] . amount [ i ] , operands [ 0 ] ) ; } </s>

Output RTL to split a constant shift into its component SH constant shift instructions .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
,
MipsTargetMachine
*
_TM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
AllowMixed16_32
(
Mixed16_32
|
Mips_Os16
)
,
Os16
(
Mips_Os16
)
,
RM
(
_RM
)
,
OverrideMode
(
NoOverride
)
,
TM
(
_TM
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
PreviousInMips16Mode
=
InMips16Mode
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
static
void
adjust_concat
(
rtx_insn
*
insn
)
{
rtx
set
=
PATTERN
(
insn
)
;
rtx
concat
=
XEXP
(
set
,
1
)
;
rtx
src0
=
XEXP
(
concat
,
0
)
;
XEXP
(
concat
,
0
)
=
XEXP
(
concat
,
1
)
;
XEXP
(
concat
,
1
)
=
src0
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Reversing inputs for concat %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a VEC_CONCAT operation of two doublewords , reverse the order of those inputs .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> inline tree function_instance :: scalar_type ( unsigned int i ) const { return scalar_types [ type_suffix ( i ) . vector_type ] ; } </s>

Return the scalar type associated with type suffix I .


<s> const char * rs6000_xcoff_strip_dollar ( const char * name ) { char * strip , * p ; const char * q ; size_t len ; q = ( const char * ) strchr ( name , '$' ) ; if ( q == 0 || q == name ) return name ; len = strlen ( name ) ; strip = XALLOCAVEC ( char , len + 1 ) ; strcpy ( strip , name ) ; p = strip + ( q - name ) ; while ( p ) { * p = '_' ; p = strchr ( p + 1 , '$' ) ; } return ggc_alloc_string ( strip , len ) ; } </s>

Return a GGC-allocated character string translating dollar signs in input NAME to underscores . Used by XCOFF ASM_OUTPUT_LABELREF .


<s> static machine_mode aarch64_preferred_simd_mode ( scalar_mode mode ) { poly_int64 bits = TARGET_SVE ? BITS_PER_SVE_VECTOR : 128 ; return aarch64_simd_container_mode ( mode , bits ) ; } </s>

Return 128-bit container as the preferred SIMD mode for MODE .


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) || thumb_far_jump_used_p ( ) || regs_ever_live [ LR_REGNUM ] ) ; } </s>

Return true if the current function needs to save/restore LR .


"64-bit code requested on a subtarget that doesn't support it!"

"Segmented stacks are only implemented on ELF."


<s> bool SICTargetLowering :: isEligibleForTailCallOptimization ( const SICCC & SICCCInfo , unsigned NextStackOffset , const SICFunctionInfo & FI ) const { return false ; if ( SICCCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s> const char * output_fix_trunc ( rtx_insn * insn , rtx * operands , bool fisttp ) { bool stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) ; bool dimode_p = GET_MODE ( operands [ 0 ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; static char buf [ 40 ] ; const char * p ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( "fld\t%y1" , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ 1 ] ) ) ; gcc_assert ( MEM_P ( operands [ 0 ] ) ) ; gcc_assert ( GET_MODE ( operands [ 1 ] ) != TFmode ) ; if ( fisttp ) return "fisttp%Z0\t%0" ; strcpy ( buf , "fist" ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%3" , operands ) ; p = "p%Z0\t%0" ; strcat ( buf , p + ! ( stack_top_dies || dimode_p ) ) ; output_asm_insn ( buf , operands ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( "fldcw\t%2" , operands ) ; return "" ; } </s>

Output code for INSN to convert a float to a signed int . OPERANDS are the insn operands . The output may be [ HSD ] Imode and the input operand may be [ SDX ] Fmode .


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static machine_mode rs6000_floatn_mode ( int n , bool extended ) { if ( extended ) { switch ( n ) { case 32 : return DFmode ; case 64 : if ( TARGET_FLOAT128_KEYWORD ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return VOIDmode ; case 128 : return VOIDmode ; default : gcc_unreachable ( ) ; } } else { switch ( n ) { case 32 : return SFmode ; case 64 : return DFmode ; case 128 : if ( TARGET_FLOAT128_KEYWORD ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return VOIDmode ; default : return VOIDmode ; } } } </s>


<s> static int epilogue_renumber ( register rtx * where , int test ) { register const char * fmt ; register int i ; register enum rtx_code code ; if ( * where == 0 ) return 0 ; code = GET_CODE ( * where ) ; switch ( code ) { case REG : if ( REGNO ( * where ) >= 8 && REGNO ( * where ) < 24 ) return 1 ; if ( ! test && REGNO ( * where ) >= 24 && REGNO ( * where ) < 32 ) * where = gen_rtx_REG ( GET_MODE ( * where ) , OUTGOING_REGNO ( REGNO ( * where ) ) ) ; case SCRATCH : case CC0 : case PC : case CONST_INT : case CONST_DOUBLE : return 0 ; case PLUS : if ( GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM && ( GET_CODE ( XEXP ( * where , 1 ) ) != CONST_INT || INTVAL ( XEXP ( * where , 1 ) ) < SPARC_STACK_BIAS ) ) return 1 ; break ; case MEM : if ( SPARC_STACK_BIAS && GET_CODE ( XEXP ( * where , 0 ) ) == REG && REGNO ( XEXP ( * where , 0 ) ) == HARD_FRAME_POINTER_REGNUM ) return 1 ; break ; default : break ; } fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( * where , i ) - 1 ; j >= 0 ; j -- ) if ( epilogue_renumber ( & ( XVECEXP ( * where , i , j ) ) , test ) ) return 1 ; } else if ( fmt [ i ] == 'e' && epilogue_renumber ( & ( XEXP ( * where , i ) ) , test ) ) return 1 ; } return 0 ; } </s>

Return 1 , if any of the registers of the instruction are % l [ 0-7 ] or % o [ 0-7 ] . Such instructions can not be used in the delay slot of return insn on v9 . If TEST is 0 , also rename all % i [ 0-7 ] registers to their % o [ 0-7 ] counterparts .


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : break ; } unsigned Idx = 1 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > 4 ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; Idx = 0 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> inline bool bundle_state_hasher :: equal ( const bundle_state * state1 , const bundle_state * state2 ) { return ( state1 -> insn_num == state2 -> insn_num && memcmp ( state1 -> dfa_state , state2 -> dfa_state , dfa_state_size ) == 0 ) ; } </s>


<s> void LanaiPassConfig :: addPreSched2 ( ) { addPass ( createLanaiMemAluCombinerPass ( ) ) ; addPass ( createLanaiSetflagAluCombinerPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static bool is_fmul_op ( enum attr_type t ) { return ( t == TYPE_FMULS ) || ( t == TYPE_FMULD ) || ( t == TYPE_NEON_FP_MUL_S ) ; } </s>

Return whether T is the attribute of a FMUL instruction .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
isReg
(
)
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: WRYrr , dl , MVT :: Flag , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: Flag , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDY , MVT :: i32 , SDValue ( Mul , 1 ) ) ; return NULL ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool SparcInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == 1 ) ; SPCC :: CondCodes CC = static_cast < SPCC :: CondCodes > ( Cond [ 0 ] . getImm ( ) ) ; Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( CC ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool X86FastTileConfig :: runOnMachineFunction ( MachineFunction & MFunc ) { MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; ST = & MFunc . getSubtarget < X86Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = MFunc . getSubtarget ( ) . getInstrInfo ( ) ; return fastTileConfig ( ) ; } </s>

runOnMachineFunction - Emit the function body .


"%qE attribute is supported only for SH2A"

"%qE attribute only applies to functions"


<s> bool PPCRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , int64_t Offset ) const { return MI -> getOpcode ( ) == PPC :: DBG_VALUE || ( isInt < 16 > ( Offset ) && ( ! usesIXAddr ( * MI ) || ( Offset & 3 ) == 0 ) ) ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool isFpMLxInstruction ( unsigned Opcode ) const { return MLxEntryMap . count ( Opcode ) ; } </s>

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to .


<s> static unsigned long rs6000_arg_size ( machine_mode mode , const_tree type ) { unsigned long size ; if ( mode != BLKmode ) size = GET_MODE_SIZE ( mode ) ; else size = int_size_in_bytes ( type ) ; if ( TARGET_32BIT ) return ( size + 3 ) >> 2 ; else return ( size + 7 ) >> 3 ; } </s>

Compute the size ( in words ) of a function argument .


aarch64
"%*sselected tune = %s\n"
""
"%*sselected arch = %s%s\n"
""


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getOptLevel ( ) <= EnableGlobalISelAtO ) setGlobalISel ( true ) ; setMachineOutliner ( true ) ; } </s>


<s>
static
void
ix86_avoid_jump_mispredicts
(
void
)
{
rtx_insn
*
insn
,
*
start
=
get_insns
(
)
;
int
nbytes
=
0
,
njumps
=
0
;
bool
isjump
=
false
;
for
(
insn
=
start
;
insn
;
insn
=
NEXT_INSN
(
insn
)
)
{
int
min_size
;
if
(
LABEL_P
(
insn
)
)
{
int
align
=
label_to_alignment
(
insn
)
;
int
max_skip
=
label_to_max_skip
(
insn
)
;
if
(
max_skip
>
15
)
max_skip
=
15
;
if
(
align
<=
0
||
(
align
<=
3
&&
max_skip
!=
(
1
<<
align
)
1
)
)
max_skip
=
0
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Label %i with max_skip %i\n"
,
INSN_UID
(
insn
)
,
max_skip
)
;
if
(
max_skip
)
{
while
(
nbytes
+
max_skip
>=
16
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
JUMP_P
(
start
)
&&
asm_noperands
(
PATTERN
(
start
)
)
<
0
)
||
CALL_P
(
start
)
)
njumps
,
isjump
=
true
;
else
isjump
=
false
;
nbytes
-=
ix86_min_insn_size
(
start
)
;
}
}
continue
;
}
min_size
=
ix86_min_insn_size
(
insn
)
;
nbytes
+=
min_size
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Insn %i estimated to %i bytes\n"
,
INSN_UID
(
insn
)
,
min_size
)
;
if
(
(
JUMP_P
(
insn
)
&&
asm_noperands
(
PATTERN
(
insn
)
)
<
0
)
||
CALL_P
(
insn
)
)
njumps
++
;
else
continue
;
while
(
njumps
>
3
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
JUMP_P
(
start
)
&&
asm_noperands
(
PATTERN
(
start
)
)
<
0
)
||
CALL_P
(
start
)
)
njumps
,
isjump
=
true
;
else
isjump
=
false
;
nbytes
-=
ix86_min_insn_size
(
start
)
;
}
gcc_assert
(
njumps
>=
0
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Interval %i to %i has %i bytes\n"
,
INSN_UID
(
start
)
,
INSN_UID
(
insn
)
,
nbytes
)
;
if
(
njumps
==
3
&&
isjump
&&
nbytes
<
16
)
{
int
padsize
=
15
nbytes
+
ix86_min_insn_size
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Padding insn %i by %i bytes!\n"
,
INSN_UID
(
insn
)
,
padsize
)
;
emit_insn_before
(
gen_pad
(
GEN_INT
(
padsize
)
)
,
insn
)
;
}
}
}
</s>

AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte window .


<s> static rtx rs6000_longcall_ref ( rtx call_ref , rtx arg ) { const char * call_name = XSTR ( call_ref , 0 ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; tree node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } if ( TARGET_PLTSEQ ) { rtx base = const0_rtx ; int regno = 12 ; if ( rs6000_pcrel_p ( ) ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx u = gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( 3 , base , call_ref , arg ) , UNSPECV_PLT_PCREL ) ; emit_insn ( gen_rtx_SET ( reg , u ) ) ; return reg ; } if ( DEFAULT_ABI == ABI_ELFv2 ) base = gen_rtx_REG ( Pmode , TOC_REGISTER ) ; else { if ( flag_pic ) base = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; regno = 11 ; } rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx hi = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 3 , base , call_ref , arg ) , UNSPEC_PLT16_HA ) ; rtx lo = gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( 3 , reg , call_ref , arg ) , UNSPECV_PLT16_LO ) ; emit_insn ( gen_rtx_SET ( reg , hi ) ) ; emit_insn ( gen_rtx_SET ( reg , lo ) ) ; return reg ; } return force_reg ( Pmode , call_ref ) ; } </s>

Return a reference suitable for calling a function with the longcall attribute .


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( Subtarget . isTargetAndroid ( ) ) { unsigned Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x18 , getAddressSpace ( ) ) ; } return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret ; } </s>


<s> int memory_address_length ( rtx addr , bool lea ) { struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return 0 ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == ADDR_SPACE_GENERIC ) ? 0 : 1 ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ; if ( base && SUBREG_P ( base ) ) base = SUBREG_REG ( base ) ; if ( index && SUBREG_P ( index ) ) index = SUBREG_REG ( index ) ; gcc_assert ( base == NULL_RTX || REG_P ( base ) ) ; gcc_assert ( index == NULL_RTX || REG_P ( index ) ) ; if ( base && ! index && ! disp ) { if ( base == arg_pointer_rtx || base == frame_pointer_rtx || REGNO ( base ) == SP_REG || REGNO ( base ) == BP_REG || REGNO ( base ) == R12_REG || REGNO ( base ) == R13_REG ) len ++ ; } else if ( disp && ! base && ! index ) { len += 4 ; if ( ! ix86_rip_relative_addr_p ( & parts ) ) len ++ ; } else { if ( disp ) { if ( base && satisfies_constraint_K ( disp ) ) len += 1 ; else len += 4 ; } else if ( base && ( REGNO ( base ) == BP_REG || REGNO ( base ) == R13_REG ) ) len ++ ; if ( index || base == arg_pointer_rtx || base == frame_pointer_rtx || ( base && ( REGNO ( base ) == SP_REG || REGNO ( base ) == R12_REG ) ) ) len ++ ; } return len ; } </s>

Calculate the length of the memory address in the instruction encoding . Does not include the one-byte modrm , opcode , or prefix .


<s> static int mips16_insn_length ( rtx_insn * insn ) { if ( JUMP_TABLE_DATA_P ( insn ) ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == ADDR_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , 0 ) ; else if ( GET_CODE ( body ) == ADDR_DIFF_VEC ) return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , 1 ) ; else gcc_unreachable ( ) ; } return get_attr_length ( insn ) ; } </s>


<s>
SDValue
LEGTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_LEG
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
LEGISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void KudeyarInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << markup ( "<reg:" ) << getRegisterName ( RegNo ) << markup ( ">" ) ; } </s>


<s> InstructionCost ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: GetElementPtr && Idx != 0 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= 32 ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return 0 ; } return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s>
SDValue
VECustomDAG
::
getLegalReductionOpVVP
(
unsigned
VVPOpcode
,
EVT
ResVT
,
SDValue
StartV
,
SDValue
VectorV
,
SDValue
Mask
,
SDValue
AVL
,
SDNodeFlags
Flags
)
const
{
bool
scalarizeStartParam
=
StartV
&&
!
hasReductionStartParam
(
VVPOpcode
)
;
bool
IsMaskReduction
=
isMaskType
(
VectorV
.
getValueType
(
)
)
;
assert
(
!
IsMaskReduction
&&
"TODO Implement"
)
;
auto
AttachStartValue
=
[
&
]
(
SDValue
ReductionResV
)
{
if
(
!
scalarizeStartParam
)
return
ReductionResV
;
auto
ScalarOC
=
getScalarReductionOpcode
(
VVPOpcode
,
IsMaskReduction
)
;
return
getNode
(
ScalarOC
,
ResVT
,
{
StartV
,
ReductionResV
}
)
;
}
;
if
(
!
scalarizeStartParam
&&
StartV
)
{
assert
(
hasReductionStartParam
(
VVPOpcode
)
)
;
return
AttachStartValue
(
getNode
(
VVPOpcode
,
ResVT
,
{
StartV
,
VectorV
,
Mask
,
AVL
}
,
Flags
)
)
;
}
else
return
AttachStartValue
(
getNode
(
VVPOpcode
,
ResVT
,
{
VectorV
,
Mask
,
AVL
}
,
Flags
)
)
;
}
</s>

VE
VECustomDAG::getLegalReductionOpVVP
"TODO Implement"


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s>
bool
AArch64InstrInfo
::
isLdStPairSuppressed
(
const
MachineInstr
*
MI
)
const
{
static_assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
,
"Too many target MO flags"
)
;
for
(
auto
*
MM
:
MI
->
memoperands
(
)
)
{
if
(
MM
->
getFlags
(
)
&
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
)
{
return
true
;
}
}
return
false
;
}
</s>

Return true if pairing the given load or store is hinted to be unprofitable .


<s>
static
void
AnalyzeArguments
(
CCState
&
State
,
SmallVectorImpl
<
CCValAssign
>
&
ArgLocs
,
const
SmallVectorImpl
<
ArgT
>
&
Args
)
{
static
const
MCPhysReg
RegList
[
]
=
{
CJG
::
R24
,
CJG
::
R25
,
CJG
::
R26
,
CJG
::
R27
,
CJG
::
R28
,
CJG
::
R29
,
CJG
::
R30
,
CJG
::
R31
}
;
static
const
unsigned
NbRegs
=
array_lengthof
(
RegList
)
;
if
(
State
.
isVarArg
(
)
)
{
llvm_unreachable
(
"Cannot support var args"
)
;
}
SmallVector
<
unsigned
,
4
>
ArgsParts
;
ParseFunctionArgs
(
Args
,
ArgsParts
)
;
unsigned
RegsLeft
=
NbRegs
;
bool
UseStack
=
false
;
unsigned
ValNo
=
0
;
for
(
unsigned
i
=
0
,
e
=
ArgsParts
.
size
(
)
;
i
!=
e
;
i
++
)
{
MVT
ArgVT
=
Args
[
ValNo
]
.
VT
;
ISD
::
ArgFlagsTy
ArgFlags
=
Args
[
ValNo
]
.
Flags
;
MVT
LocVT
=
ArgVT
;
CCValAssign
::
LocInfo
LocInfo
=
CCValAssign
::
Full
;
if
(
ArgFlags
.
isByVal
(
)
)
{
State
.
HandleByVal
(
ValNo
++
,
ArgVT
,
LocVT
,
LocInfo
,
4
,
4
,
ArgFlags
)
;
continue
;
}
unsigned
Parts
=
ArgsParts
[
i
]
;
if
(
!
UseStack
&&
Parts
<=
RegsLeft
)
{
unsigned
FirstVal
=
ValNo
;
for
(
unsigned
j
=
0
;
j
<
Parts
;
j
++
)
{
unsigned
Reg
=
State
.
AllocateReg
(
RegList
)
;
State
.
addLoc
(
CCValAssign
::
getReg
(
ValNo
++
,
ArgVT
,
Reg
,
LocVT
,
LocInfo
)
)
;
RegsLeft
;
}
SmallVectorImpl
<
CCValAssign
>
::
iterator
B
=
ArgLocs
.
begin
(
)
+
FirstVal
;
std
::
reverse
(
B
,
B
+
Parts
)
;
}
else
{
UseStack
=
true
;
for
(
unsigned
j
=
0
;
j
<
Parts
;
j
++
)
CC_CJG
(
ValNo
++
,
ArgVT
,
LocVT
,
LocInfo
,
ArgFlags
,
State
)
;
}
}
}
</s>

The function will invoke AnalyzeCallOperands .


<s> void arm_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , arm_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return SystemZ :: R6D ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s>
void
ARMConstantIslands
::
verify
(
)
{
assert
(
std
::
is_sorted
(
MF
->
begin
(
)
,
MF
->
end
(
)
,
[
this
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> SMLoc getLoc ( ) const { return Parser . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasRAS ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TT . find ( "eabi" ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ 2 ] ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 0 ] , 0 ) ) && ! reload_in_progress ) operands [ 0 ] = replace_equiv_address ( operands [ 0 ] , copy_addr_to_reg ( XEXP ( operands [ 0 ] , 0 ) ) ) ; if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_CODE ( XEXP ( operands [ 1 ] , 0 ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 1 ] , 0 ) ) && ! reload_in_progress ) operands [ 1 ] = replace_equiv_address ( operands [ 1 ] , copy_addr_to_reg ( XEXP ( operands [ 1 ] , 0 ) ) ) ; } </s>

Helper for the following . Get rid of [ r+r ] memory refs in cases where it wo n't work ( TImode , TFmode ) .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
(
Divisor
)
.
isPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasCMov
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
(
1ULL
<<
Lg2
)
1
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i64
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


"Hard-float can't be used with current CPU,"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; auto FIReg = MIRBuilder . buildFrameIndex ( p0 , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( 0 ) ; } auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( AArch64 :: SP ) ) ; auto OffsetReg = MIRBuilder . buildConstant ( s64 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool legitimate_pic_operand_p ( rtx x ) { rtx inner ; switch ( GET_CODE ( x ) ) { case CONST : inner = XEXP ( x , 0 ) ; if ( GET_CODE ( inner ) == PLUS && CONST_INT_P ( XEXP ( inner , 1 ) ) ) inner = XEXP ( inner , 0 ) ; if ( GET_CODE ( inner ) == UNSPEC ) switch ( XINT ( inner , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : x = XVECEXP ( inner , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_MACHOPIC_OFFSET : return legitimate_pic_address_disp_p ( x ) ; default : return false ; } case SYMBOL_REF : case LABEL_REF : return legitimate_pic_address_disp_p ( x ) ; default : return true ; } } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> static void mips_emit_unary ( enum rtx_code code , rtx target , rtx op0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_e ( code , GET_MODE ( op0 ) , op0 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 ) ) .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict , const_rtx * tocrel_base_ret , const_rtx * tocrel_offset_ret ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; } const_rtx tocrel_base = op ; const_rtx tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } if ( tocrel_base_ret ) * tocrel_base_ret = tocrel_base ; if ( tocrel_offset_ret ) * tocrel_offset_ret = tocrel_offset ; return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL && REG_P ( XVECEXP ( tocrel_base , 0 , 1 ) ) && REGNO ( XVECEXP ( tocrel_base , 0 , 1 ) ) == TOC_REGISTER ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


<s> xlogue_layout :: xlogue_layout ( HOST_WIDE_INT stack_align_off_in , bool hfp ) : m_hfp ( hfp ) , m_nregs ( hfp ? 17 : 18 ) , m_stack_align_off_in ( stack_align_off_in ) { HOST_WIDE_INT offset = stack_align_off_in ; unsigned i , j ; for ( i = j = 0 ; i < MAX_REGS ; ++ i ) { unsigned regno = REG_ORDER [ i ] ; if ( regno == BP_REG && hfp ) continue ; if ( SSE_REGNO_P ( regno ) ) { offset += 16 ; gcc_assert ( ! ( ( stack_align_off_in + offset ) & 15 ) ) ; } else offset += 8 ; m_regs [ j ] . regno = regno ; m_regs [ j ++ ] . offset = offset - STUB_INDEX_OFFSET ; } gcc_assert ( j == m_nregs ) ; } </s>


<s> const TargetRegisterClass * MipsRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; return Subtarget . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

Mips Mips Mips Mips Mips::GPR64RegClass Mips::GPR32RegClass


<s> int rs6000_reg_parm_stack_space ( tree fun , bool incoming ) { int reg_parm_stack_space ; switch ( DEFAULT_ABI ) { default : reg_parm_stack_space = 0 ; break ; case ABI_AIX : case ABI_DARWIN : reg_parm_stack_space = TARGET_64BIT ? 64 : 32 ; break ; case ABI_ELFv2 : if ( rs6000_function_parms_need_stack ( fun , incoming ) ) reg_parm_stack_space = TARGET_64BIT ? 64 : 32 ; else reg_parm_stack_space = 0 ; break ; } return reg_parm_stack_space ; } </s>

Return the size of the REG_PARM_STACK_SPACE are for FUN . This is usually a constant depending on the ABI . However , in the ELFv2 ABI the register parameter area is optional when calling a function that has a prototype is scope , has no variable argument list , and passes all parameters in registers .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> unsigned AArch64TTIImpl :: getMinPrefetchStride ( ) { return ST -> getMinPrefetchStride ( ) ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


"force: group count = %d, can_issue_more = %d\n"

"done force: group count = %d, can_issue_more = %d\n"

Utility of the function redefine_groups . Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS in the same dispatch group . If so , insert nops before NEXT_INSN , in order to keep it `` far '' ( in a separate group ) from GROUP_INSNS , following one of the following schemes , depending on the value of the flag -minsert_sched_nops = X : ( 1 ) X == sched_finish_regroup_exact : insert exactly as many nops as needed in order to force NEXT_INSN into a separate group . ( 2 ) X < sched_finish_regroup_exact : insert exactly X nops . GROUP_END , CAN_ISSUE_MORE and GROUP_COUNT record the state after nop insertion ( has a group just ended , how many vacant issue slots remain in the last group , and how many dispatch groups were encountered so far ) .


<s>
static
void
recombine_stvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_DEST
(
body
)
)
==
MEM
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
)
;
rtx
mem
=
SET_DEST
(
body
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx_insn
*
and_insn
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insn
)
;
if
(
and_operation
!=
0
)
{
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
df_ref
src_use
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_USE
(
src_use
,
insn_info
)
{
if
(
!
rtx_equal_p
(
DF_REF_REG
(
src_use
)
,
src_reg
)
)
continue
;
struct
df_link
*
link
=
DF_REF_CHAIN
(
src_use
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
and_base
=
XEXP
(
and_operation
,
0
)
;
rtx
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
and_base
)
,
new_reg
,
XEXP
(
and_operation
,
1
)
)
;
SET_SRC
(
body
)
=
src_reg
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"stvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the store for an stvx pattern , put it in canonical form .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; bool oclBiCall = false ; bool hipeCall = false ; bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; oclBiCall = ( F ? F -> getCallingConv ( ) == CallingConv :: Intel_OCL_BI : false ) ; hipeCall = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; } if ( ghcCall || hipeCall ) return CSR_NoRegs_SaveList ; if ( oclBiCall ) { if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


Hook to validate attribute ( ( target ( `` ... '' ) ) ) .


<s> static rtx or1k_restore_reg ( int regno , HOST_WIDE_INT offset , rtx cfa_restores ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; emit_move_insn ( reg , mem ) ; return alloc_reg_note ( REG_CFA_RESTORE , reg , cfa_restores ) ; } </s>

Emit rtl to restore register REGNO contents from stack memory at the given OFFSET from the current stack pointer .


<s> static rtx_insn * maybe_dead_move ( rtx dest , rtx src , bool ATTRIBUTE_UNUSED maybe_dead_p ) { rtx_insn * insn = emit_move_insn ( dest , src ) ; if ( maybe_dead_p ) REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_MAYBE_DEAD , const0_rtx , NULL ) ; return insn ; } </s>

Move SRC to DEST . Mark the move as being potentially dead if MAYBE_DEAD_P .


<s> rtx arm_load_function_descriptor ( rtx funcdesc ) { rtx fnaddr_reg = gen_reg_rtx ( Pmode ) ; rtx pic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; rtx fnaddr = gen_rtx_MEM ( Pmode , funcdesc ) ; rtx gotaddr = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , funcdesc , 4 ) ) ; emit_move_insn ( fnaddr_reg , fnaddr ) ; emit_insn ( gen_restore_pic_register_after_call ( pic_reg , gotaddr ) ) ; return fnaddr_reg ; } </s>

Emit insns to load the function address from FUNCDESC ( an FDPIC function descriptor ) into a register and the GOT address into the FDPIC register , returning an rtx for the register holding the function address .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool AArch64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count & 3 ) != 0 ) { for ( uint64_t i = 0 , e = ( Count & 3 ) ; i != e ; ++ i ) OW -> Write8 ( 0 ) ; } Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> Write32 ( 0xd503201f ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool X86TargetLowering :: hasCopyImplyingStackAdjustment ( MachineFunction * MF ) const { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; return any_of ( MRI . reg_instructions ( X86 :: EFLAGS ) , [ ] ( const MachineInstr & RI ) { return RI . isCopy ( ) ; } ) ; } </s>

Returns true if the function contains operations which will lower down to instructions which manipulate the stack pointer .


<s> static void aarch64_run_selftests ( void ) { aarch64_test_loading_full_dump ( ) ; } </s>


<s> static void sparc_asm_function_epilogue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { rtx insn , last_real_insn ; insn = get_last_insn ( ) ; last_real_insn = prev_real_insn ( insn ) ; if ( last_real_insn && NONJUMP_INSN_P ( last_real_insn ) && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE ) last_real_insn = XVECEXP ( PATTERN ( last_real_insn ) , 0 , 0 ) ; if ( last_real_insn && CALL_P ( last_real_insn ) && ! SIBLING_CALL_P ( last_real_insn ) ) fputs ( "\tnop\n" , file ) ; sparc_output_deferred_case_vectors ( ) ; } </s>

This function generates the assembly code for function exit .


<s> static void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0 , op1 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 OP1 ) ) .


<s> void rs6000_aix_emit_builtin_unwind_init ( ) { rtx mem ; rtx stack_top = gen_reg_rtx ( Pmode ) ; rtx opcode_addr = gen_reg_rtx ( Pmode ) ; insn_after_throw = gen_reg_rtx ( SImode ) ; mem = gen_rtx_MEM ( Pmode , hard_frame_pointer_rtx ) ; emit_move_insn ( stack_top , mem ) ; mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_top , GEN_INT ( 2 * GET_MODE_SIZE ( Pmode ) ) ) ) ; emit_move_insn ( opcode_addr , mem ) ; emit_move_insn ( insn_after_throw , gen_rtx_MEM ( SImode , opcode_addr ) ) ; } </s>

If _Unwind_ * has been called from within the same module , toc register is not guaranteed to be saved to 40 ( 1 ) on function entry . Save it there in that case .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsResolved
,
Ctx
,
STI
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
Endian
==
support
::
big
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , Register DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , Register PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . add ( predOps ( Pred , PredReg ) ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool ARMSubtarget :: ignoreCSRForAllocationOrder ( const MachineFunction & MF , unsigned PhysReg ) const { return isThumb2 ( ) && MF . getFunction ( ) . hasMinSize ( ) && ARM :: GPRRegClass . contains ( PhysReg ) ; } </s>

True if the register allocator should use the allocation orders exactly as written in the tablegen descriptions , false if it should allocate the specified physical register later if is it callee-saved .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { TM = & F . getTarget ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; if ( Changed ) F . getRegInfo ( ) . invalidateLiveness ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
.
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getLocVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
||
CopyVT
==
MVT
::
f128
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
.
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
bool
RoundAfterCopy
=
false
;
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
if
(
!
Subtarget
.
hasX87
(
)
)
report_fatal_error
(
"X87 register return with X87 disabled"
)
;
CopyVT
=
MVT
::
f80
;
RoundAfterCopy
=
(
CopyVT
!=
VA
.
getLocVT
(
)
)
;
}
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
RoundAfterCopy
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
,
dl
)
)
;
if
(
VA
.
isExtInLoc
(
)
&&
VA
.
getValVT
(
)
.
getScalarType
(
)
==
MVT
::
i1
)
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static unsigned int rs6000_hard_regno_nregs_hook ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_nregs [ mode ] [ regno ] ; } </s>


<s> int mmix_starting_frame_offset ( ) { return ( - 8 + ( MMIX_CFUN_HAS_LANDING_PAD ? - 16 : ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? - 8 : 0 ) ) ) ; } </s>


<s> static void sh_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { enum rtx_code tmp_code = ( enum rtx_code ) * code ; sh_canonicalize_comparison ( tmp_code , * op0 , * op1 , VOIDmode , op0_preserve_value ) ; * code = ( int ) tmp_code ; } </s>

This function implements the canonicalize_comparison target hook . This wrapper around the internally used sh_canonicalize_comparison function is needed to do the enum rtx_code < - > int conversion . Target hooks can not use enum rtx_code in its definition .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( this , nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> inline bool function_call_info :: function_returns_void_p ( ) { return TREE_TYPE ( TREE_TYPE ( fndecl ) ) == void_type_node ; } </s>

Return true if the function has no return value .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

ARM ARM ARM::SP ARM::PC ARM::FPSCR ARM::R9


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( TM . getDataLayout ( ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; if ( Reg == FPReg ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>


<s> virtual void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const uint32_t * F2003fRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_NoRegs_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
static
void
printPCRelImm
(
X86AsmPrinter
&
P
,
const
MachineInstr
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"Unknown pcrel immediate operand"
)
;
case
MachineOperand
::
MO_Register
:
printOperand
(
P
,
MI
,
OpNo
,
O
)
;
return
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
P
,
MO
,
O
)
;
return
;
}
}
</s>


<s> const uint32_t * Cpu0RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CSR_O32_RegMask ; } </s>


<s> bool PPCInstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : case PPC :: QVFADD : case PPC :: QVFADDS : case PPC :: QVFADDSs : case PPC :: QVFMUL : case PPC :: QVFMULS : case PPC :: QVFMULSs : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::QVFADD PPC::QVFADDS PPC::QVFADDSs PPC::QVFMUL PPC::QVFMULS PPC::QVFMULSs


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

PowerPC PPC 0 PPCISD::FSEL "PPCISD::FSEL" PPCISD::FCFID "PPCISD::FCFID" PPCISD::FCTIDZ "PPCISD::FCTIDZ" PPCISD::FCTIWZ "PPCISD::FCTIWZ" PPCISD::STFIWX "PPCISD::STFIWX" PPCISD::VMADDFP "PPCISD::VMADDFP" PPCISD::VNMSUBFP "PPCISD::VNMSUBFP" PPCISD::VPERM "PPCISD::VPERM" PPCISD::Hi "PPCISD::Hi" PPCISD::Lo "PPCISD::Lo" PPCISD::TOC_ENTRY "PPCISD::TOC_ENTRY" PPCISD::TOC_RESTORE "PPCISD::TOC_RESTORE" PPCISD::LOAD "PPCISD::LOAD" PPCISD::LOAD_TOC "PPCISD::LOAD_TOC" PPCISD::DYNALLOC "PPCISD::DYNALLOC" PPCISD::GlobalBaseReg "PPCISD::GlobalBaseReg" PPCISD::SRL "PPCISD::SRL" PPCISD::SRA "PPCISD::SRA" PPCISD::SHL "PPCISD::SHL" PPCISD::EXTSW_32 "PPCISD::EXTSW_32" PPCISD::STD_32 "PPCISD::STD_32" PPCISD::CALL_SVR4 "PPCISD::CALL_SVR4" PPCISD::CALL_Darwin "PPCISD::CALL_Darwin" PPCISD::NOP "PPCISD::NOP" PPCISD::MTCTR "PPCISD::MTCTR" PPCISD::BCTRL_Darwin "PPCISD::BCTRL_Darwin" PPCISD::BCTRL_SVR4 "PPCISD::BCTRL_SVR4" PPCISD::RET_FLAG "PPCISD::RET_FLAG" PPCISD::MFCR "PPCISD::MFCR" PPCISD::VCMP "PPCISD::VCMP" PPCISD::VCMPo "PPCISD::VCMPo" PPCISD::LBRX "PPCISD::LBRX" PPCISD::STBRX "PPCISD::STBRX" PPCISD::LARX "PPCISD::LARX" PPCISD::STCX "PPCISD::STCX" PPCISD::COND_BRANCH "PPCISD::COND_BRANCH" PPCISD::MFFS "PPCISD::MFFS" PPCISD::MTFSB0 "PPCISD::MTFSB0" PPCISD::MTFSB1 "PPCISD::MTFSB1" PPCISD::FADDRTZ "PPCISD::FADDRTZ" PPCISD::MTFSF "PPCISD::MTFSF" PPCISD::TC_RETURN "PPCISD::TC_RETURN"


<s> bool AArch64InstrInfo :: isTailCall ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case AArch64 :: TCRETURNdi : case AArch64 :: TCRETURNri : return true ; default : return false ; } } </s>

Determines whether Inst is a tail call instruction .


"Offset must be aligned to 4 bytes because memory is "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> int general_scalar_chain :: vector_const_cost ( rtx exp ) { gcc_assert ( CONST_INT_P ( exp ) ) ; if ( standard_sse_constant_p ( exp , vmode ) ) return ix86_cost -> sse_op ; return ix86_cost -> sse_load [ smode == DImode ? 1 : 0 ] ; } </s>

Return a cost of building a vector costant instead of using a scalar one .


<s> const SICInstrInfo * SICInstrInfo :: create ( SICSubtarget & STI ) { return new SICInstrInfo ( STI ) ; } </s>


<s> bool X86PartialReduction :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < X86TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * BO = dyn_cast < BinaryOperator > ( & I ) ; if ( ! BO ) continue ; if ( ! isVectorReductionOp ( * BO ) ) continue ; if ( BO -> getOpcode ( ) == Instruction :: Add ) { if ( tryMAddPattern ( BO ) ) { MadeChange = true ; continue ; } if ( trySADPattern ( BO ) ) { MadeChange = true ; continue ; } } } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>