<s> static unsigned int aarch64_autovectorize_vector_modes ( vector_modes * modes , bool ) { static const machine_mode sve_modes [ ] = { VNx16QImode , VNx8QImode , VNx4QImode , VNx2QImode } ; static const machine_mode advsimd_modes [ ] = { V16QImode , V8QImode , V4HImode , V2SImode } ; bool only_asimd_p = aarch64_autovec_preference == 1 ; bool only_sve_p = aarch64_autovec_preference == 2 ; unsigned int sve_i = ( TARGET_SVE && ! only_asimd_p ) ? 0 : ARRAY_SIZE ( sve_modes ) ; unsigned int advsimd_i = 0 ; while ( ! only_sve_p && advsimd_i < ARRAY_SIZE ( advsimd_modes ) ) { if ( sve_i < ARRAY_SIZE ( sve_modes ) && aarch64_cmp_autovec_modes ( sve_modes [ sve_i ] , advsimd_modes [ advsimd_i ] ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; else modes -> safe_push ( advsimd_modes [ advsimd_i ++ ] ) ; } while ( sve_i < ARRAY_SIZE ( sve_modes ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; unsigned int flags = 0 ; if ( TARGET_SVE && aarch64_sve_compare_costs ) flags |= VECT_COMPARE_COSTS ; return flags ; } </s>

Return a list of possible vector sizes for the vectorizer to iterate over .


<s> virtual const IA64RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else if ( Subtarget -> hasMVEIntegerOps ( ) && ( isVMOVNMask ( M , VT , true , false ) || isVMOVNMask ( M , VT , false , false ) || isVMOVNMask ( M , VT , true , true ) ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool nds32_can_use_btgl_p ( HOST_WIDE_INT ival ) { int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) & mask ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'btgl ' instruction can be used with IVAL .


<s> static void split_quadword_operands ( rtx insn , enum rtx_code code , rtx * operands , rtx * low , int n ) { int i ; for ( i = 0 ; i < n ; i ++ ) low [ i ] = 0 ; for ( i = 0 ; i < n ; i ++ ) { if ( MEM_P ( operands [ i ] ) && ( GET_CODE ( XEXP ( operands [ i ] , 0 ) ) == PRE_DEC || GET_CODE ( XEXP ( operands [ i ] , 0 ) ) == POST_INC ) ) { rtx addr = XEXP ( operands [ i ] , 0 ) ; operands [ i ] = low [ i ] = gen_rtx_MEM ( SImode , addr ) ; } else if ( optimize_size && MEM_P ( operands [ i ] ) && REG_P ( XEXP ( operands [ i ] , 0 ) ) && ( code != MINUS || operands [ 1 ] != const0_rtx ) && find_regno_note ( insn , REG_DEAD , REGNO ( XEXP ( operands [ i ] , 0 ) ) ) ) { low [ i ] = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( Pmode , XEXP ( operands [ i ] , 0 ) ) ) ; operands [ i ] = gen_rtx_MEM ( SImode , XEXP ( operands [ i ] , 0 ) ) ; } else { low [ i ] = operand_subword ( operands [ i ] , 0 , 0 , DImode ) ; operands [ i ] = operand_subword ( operands [ i ] , 1 , 0 , DImode ) ; } } } </s>

This is like nonimmediate_operand with a restriction on the type of MEM .


<s> void rs6000_emit_cbranch ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx , loc_ref ; condition_rtx = rs6000_generate_compare ( operands [ 0 ] , mode ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s>
static
void
moxie_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
0
:
break
;
default
:
LOSE_AND_RETURN
(
"invalid operand modifier letter"
,
x
)
;
}
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
if
(
REGNO
(
operand
)
>
MOXIE_R13
)
internal_error
(
"internal error: bad register: %d"
,
REGNO
(
operand
)
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
return
;
case
MEM
:
output_address
(
GET_MODE
(
XEXP
(
operand
,
0
)
)
,
XEXP
(
operand
,
0
)
)
;
return
;
default
:
if
(
CONSTANT_P
(
operand
)
)
{
output_addr_const
(
file
,
operand
)
;
return
;
}
LOSE_AND_RETURN
(
"unexpected operand"
,
x
)
;
}
}
</s>


<s> virtual bool requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s>
bool
MMIXAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
MMIXOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

MMIX
MMIX
MMIXOperand::createToken
"unexpected token"


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void * aarch64_init_cost ( class loop * ) { return new aarch64_vector_costs ; } </s>


<s> bool nds32_can_use_bset_p ( HOST_WIDE_INT ival ) { int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) & mask ) ; return ( TARGET_EXT_PERF && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bset ' instruction can be used with IVAL .


<s> static machine_mode rs6000_c_mode_for_suffix ( char suffix ) { if ( TARGET_FLOAT128 ) { if ( suffix == 'q' || suffix == 'Q' ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; } return VOIDmode ; } </s>


<s>
void
X86FastPreTileConfig
::
spill
(
MachineBasicBlock
::
iterator
Before
,
Register
VirtReg
,
bool
Kill
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Spilling "
<<
printReg
(
VirtReg
,
TRI
)
<<
" \n"
)
;
int
FI
=
getStackSpaceFor
(
VirtReg
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" to stack slot #"
<<
FI
<<
'\n'
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
->
getRegClass
(
VirtReg
)
;
TII
->
storeRegToStackSlot
(
*
MBB
,
Before
,
VirtReg
,
Kill
,
FI
,
&
RC
,
TRI
)
;
++
NumStores
;
}
</s>

spill - Spill the LRE.getParent ( ) live interval .


<s> bool SystemZAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { SystemZInstPrinter :: printAddress ( MAI , MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + 1 ) . getImm ( ) , MI -> getOperand ( OpNo + 2 ) . getReg ( ) , OS ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static pad_direction rs6000_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! AGGREGATE_PADDING_FIXED ) { if ( BYTES_BIG_ENDIAN ) { HOST_WIDE_INT size = 0 ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == 1 || size == 2 || size == 4 ) return PAD_DOWNWARD ; } return PAD_UPWARD ; } if ( AGGREGATES_PAD_UPWARD_ALWAYS ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return PAD_UPWARD ; } return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . For the AIX ABI structs are always stored left shifted in their argument slot .


<s> static bool aarch64_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( CONST_INT_P ( x ) || ( CONST_DOUBLE_P ( x ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) || GET_CODE ( x ) == CONST_VECTOR ) return true ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags == ( VEC_ADVSIMD | VEC_STRUCT ) ) return false ; if ( vec_flags & VEC_ANY_SVE ) return aarch64_simd_valid_immediate ( x , NULL ) ; if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; poly_int64 offset ; if ( poly_int_rtx_p ( x , & offset ) ) return aarch64_offset_temporaries ( false , offset ) <= 1 ; x = strip_offset ( x , & offset ) ; if ( ! offset . is_constant ( ) && aarch64_offset_temporaries ( true , offset ) > 0 ) return false ; if ( maybe_ne ( offset , 0 ) && SYMBOL_REF_P ( x ) && SYMBOL_REF_ANCHOR_P ( x ) ) return false ; if ( SYMBOL_REF_P ( x ) && ! SYMBOL_REF_TLS_MODEL ( x ) ) return true ; if ( GET_CODE ( x ) == LABEL_REF ) return true ; return false ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P hook . Return true for constants that should be rematerialized rather than spilled .


<s> std :: pair < uint16_t , uint16_t > ARMBaseInstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == ARM :: VMOVD && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == ARM :: VMOVRS || MI -> getOpcode ( ) == ARM :: VMOVSR || MI -> getOpcode ( ) == ARM :: VMOVS ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; unsigned Domain = MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Domain & ARMII :: DomainNEON ) return std :: make_pair ( ExeNEON , 0 ) ; if ( ( Domain & ARMII :: DomainNEONA8 ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , 0 ) ; if ( Domain & ARMII :: DomainVFP ) return std :: make_pair ( ExeVFP , 0 ) ; return std :: make_pair ( ExeGeneric , 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> static inline bool ia64_reg_ok_for_base_p ( const_rtx reg , bool strict ) { if ( strict && REGNO_OK_FOR_BASE_P ( REGNO ( reg ) ) ) return true ; else if ( ! strict && ( GENERAL_REGNO_P ( REGNO ( reg ) ) || ! HARD_REGISTER_P ( reg ) ) ) return true ; else return false ; } </s>

Returns true if REG ( assumed to be a ` reg ' RTX ) is valid for use as a base register .


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: tLDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == 0 ) return true ; return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
bool
PPCInstrInfo
::
FoldImmediate
(
MachineInstr
&
UseMI
,
MachineInstr
&
DefMI
,
unsigned
Reg
,
MachineRegisterInfo
*
MRI
)
const
{
unsigned
DefOpc
=
DefMI
.
getOpcode
(
)
;
if
(
DefOpc
!=
PPC
::
LI
&&
DefOpc
!=
PPC
::
LI8
)
return
false
;
if
(
!
DefMI
.
getOperand
(
1
)
.
isImm
(
)
)
return
false
;
if
(
DefMI
.
getOperand
(
1
)
.
getImm
(
)
!=
0
)
return
false
;
const
MCInstrDesc
&
UseMCID
=
UseMI
.
getDesc
(
)
;
if
(
UseMCID
.
isPseudo
(
)
)
return
false
;
unsigned
UseIdx
;
for
(
UseIdx
=
0
;
UseIdx
<
UseMI
.
getNumOperands
(
)
;
++
UseIdx
)
if
(
UseMI
.
getOperand
(
UseIdx
)
.
isReg
(
)
&&
UseMI
.
getOperand
(
UseIdx
)
.
getReg
(
)
==
Reg
)
break
;
assert
(
UseIdx
<
UseMI
.
getNumOperands
(
)
&&
"Cannot find Reg in UseMI"
)
;
assert
(
UseIdx
<
UseMCID
.
getNumOperands
(
)
&&
"No operand description for Reg"
)
;
const
MCOperandInfo
*
UseInfo
=
&
UseMCID
.
OpInfo
[
UseIdx
]
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
if
(
UseInfo
->
RegClass
!=
1
)
return
false
;
}
else
{
if
(
UseInfo
->
RegClass
!=
PPC
::
GPRC_NOR0RegClassID
&&
UseInfo
->
RegClass
!=
PPC
::
G8RC_NOX0RegClassID
)
return
false
;
}
if
(
UseInfo
->
Constraints
!=
0
)
return
false
;
unsigned
ZeroReg
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
ZeroReg
=
isPPC64
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
else
{
ZeroReg
=
UseInfo
->
RegClass
==
PPC
::
G8RC_NOX0RegClassID
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
bool
DeleteDef
=
MRI
->
hasOneNonDBGUse
(
Reg
)
;
UseMI
.
getOperand
(
UseIdx
)
.
setReg
(
ZeroReg
)
;
if
(
DeleteDef
)
DefMI
.
eraseFromParent
(
)
;
return
true
;
}
</s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> rtx mmix_dynamic_chain_address ( rtx frame ) { return plus_constant ( Pmode , frame , - 8 ) ; } </s>


<s> bool ARMSubtarget :: enablePostRAScheduler ( ) const { if ( getSchedModel ( ) . isOutOfOrder ( ) && isSwift ( ) ) return false ; return ( ! isThumb ( ) || hasThumb2 ( ) ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool loongarch_symbolic_constant_p ( rtx x , enum loongarch_symbol_type * symbol_type ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( SYMBOL_REF_P ( x ) || LABEL_REF_P ( x ) ) { * symbol_type = loongarch_classify_symbol ( x ) ; if ( * symbol_type == SYMBOL_TLS ) return true ; } else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_GOT_DISP : case SYMBOL_TLSGD : case SYMBOL_TLSLDM : case SYMBOL_TLS : return false ; } gcc_unreachable ( ) ; } </s>

Return true if X is a symbolic constant . If it is , store the type of the symbol in * SYMBOL_TYPE .


<s>
unsigned
SICABIInfo
::
GetCalleeAllocdArgSizeInBytes
(
CallingConv
::
ID
CC
)
const
{
if
(
IsO32
(
)
)
return
CC
!=
0
;
if
(
IsS32
(
)
)
return
0
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

Obtain the size of the area allocated by the callee for arguments .


<s> bool csky_split_ior ( rtx * operands ) { HOST_WIDE_INT mask = INTVAL ( operands [ 2 ] ) ; int i ; if ( mask == 0 ) { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; return true ; } if ( mask == - 1 ) { emit_move_insn ( operands [ 0 ] , gen_int_mode ( - 1 , SImode ) ) ; return true ; } if ( CSKY_ISA_FEATURE ( E2 ) && csky_literal_I_operand ( operands [ 2 ] , SImode ) ) return false ; if ( popcount_hwi ( mask & 0xffffffff ) <= ( reload_completed && ! CSKY_ISA_FEATURE ( E2 ) ? 1 : 2 ) ) { rtx input = operands [ 1 ] ; if ( ! CSKY_ISA_FEATURE ( E2 ) ) { emit_move_insn ( operands [ 0 ] , input ) ; input = operands [ 0 ] ; } for ( i = 0 ; i < 32 ; i ++ ) if ( mask & ( 1 << i ) ) { emit_insn ( gen_bseti ( operands [ 0 ] , input , GEN_INT ( i ) ) ) ; input = operands [ 0 ] ; } return true ; } if ( reload_completed ) { emit_move_insn ( operands [ 0 ] , operands [ 2 ] ) ; operands [ 2 ] = operands [ 1 ] ; operands [ 1 ] = operands [ 0 ] ; } else operands [ 2 ] = copy_to_mode_reg ( SImode , operands [ 2 ] ) ; return false ; } </s>

Split operands for an IOR expression when OPERANDS [ 2 ] is a constant . Note operands [ 0 ] is marked earlyclobber in this case and can be overwritten . Return true if `` DONE '' , false otherwise .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Sparc Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned X86AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: EVEX ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX || ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: VEX ) return Match_Unsupported ; if ( MCID . TSFlags & X86II :: ExplicitVEXPrefix && ( ForcedVEXEncoding != VEXEncoding_VEX && ForcedVEXEncoding != VEXEncoding_VEX2 && ForcedVEXEncoding != VEXEncoding_VEX3 ) ) return Match_Unsupported ; switch ( Opc ) { case X86 :: VCVTSD2SIZrm_Int : case X86 :: VCVTSD2SI64Zrm_Int : case X86 :: VCVTSS2SIZrm_Int : case X86 :: VCVTSS2SI64Zrm_Int : case X86 :: VCVTTSD2SIZrm : case X86 :: VCVTTSD2SIZrm_Int : case X86 :: VCVTTSD2SI64Zrm : case X86 :: VCVTTSD2SI64Zrm_Int : case X86 :: VCVTTSS2SIZrm : case X86 :: VCVTTSS2SIZrm_Int : case X86 :: VCVTTSS2SI64Zrm : case X86 :: VCVTTSS2SI64Zrm_Int : if ( ForcedVEXEncoding != VEXEncoding_EVEX ) return Match_Unsupported ; break ; } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s>
unsigned
SparcCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
TM
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Sparc
Sparc
"Unable to encode MachineOperand!"
0


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3orAVX ( ) ) ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3orAVX ( ) ) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
void
machopic_output_stub
(
FILE
*
file
,
const
char
*
symb
,
const
char
*
stub
)
{
unsigned
int
length
;
char
*
symbol_name
,
*
lazy_ptr_name
;
char
*
local_label_0
;
static
unsigned
label
=
0
;
symb
=
(
*
targetm
.
strip_name_encoding
)
(
symb
)
;
length
=
strlen
(
symb
)
;
symbol_name
=
XALLOCAVEC
(
char
,
length
+
32
)
;
GEN_SYMBOL_NAME_FOR_SYMBOL
(
symbol_name
,
symb
,
length
)
;
lazy_ptr_name
=
XALLOCAVEC
(
char
,
length
+
32
)
;
GEN_LAZY_PTR_NAME_FOR_SYMBOL
(
lazy_ptr_name
,
symb
,
length
)
;
if
(
MACHOPIC_PURE
)
{
switch_to_section
(
darwin_sections
[
machopic_picsymbol_stub1_section
]
)
;
fprintf
(
file
,
"\t.align 5\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
label
++
;
local_label_0
=
XALLOCAVEC
(
char
,
16
)
;
sprintf
(
local_label_0
,
"L%u$spb"
,
label
)
;
fprintf
(
file
,
"\tmflr r0\n"
)
;
fprintf
(
file
,
"\tbcl 20,31,%s\n"
,
local_label_0
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
fprintf
(
file
,
"\taddis r11,r11,ha16(%s-%s)\n"
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtlr r0\n"
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s-%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
else
{
switch_to_section
(
darwin_sections
[
machopic_symbol_stub1_section
]
)
;
fprintf
(
file
,
"\t.align 4\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"\tlis r11,ha16(%s)\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
switch_to_section
(
darwin_sections
[
machopic_lazy_symbol_ptr_section
]
)
;
fprintf
(
file
,
"%s:\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"%sdyld_stub_binding_helper\n"
,
(
TARGET_64BIT
DOUBLE_INT_ASM_OP
:
"\t.long\t"
)
)
;
}
</s>

Generate external symbol indirection stubs ( PIC and non-PIC ) .

rs6000
0
32
32
"\t.align 5\n"
"%s:\n"
"\t.indirect_symbol %s\n"
16
"L%u$spb"
"\tmflr r0\n"
"\tbcl 20,31,%s\n"
"%s:\n\tmflr r11\n"
"\taddis r11,r11,ha16(%s-%s)\n"
"\tmtlr r0\n"
"\t%s r12,lo16(%s-%s)(r11)\n"
"ldu"
"lwzu"
"\tmtctr r12\n"
"\tbctr\n"
"\t.align 4\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"\tlis r11,ha16(%s)\n"
"\t%s r12,lo16(%s)(r11)\n"
"ldu"
"lwzu"
"\tmtctr r12\n"
"\tbctr\n"
"%s:\n"
"\t.indirect_symbol %s\n"
"%sdyld_stub_binding_helper\n"
"\t.long\t"


<s> Register MINA32RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? MINA32 :: R11 : MINA32 :: SP ; } </s>


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SystemZMCInstLower Lower ( Mang , MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; Lower . lower ( MI , LoweredMI ) ; OutStreamer . EmitInstruction ( LoweredMI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
bool
X86InstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
X86
::
MOV8rm
:
case
X86
::
MOV16rm
:
case
X86
::
MOV32rm
:
case
X86
::
MOV64rm
:
case
X86
::
LD_Fp64m
:
case
X86
::
MOVSSrm
:
case
X86
::
MOVSDrm
:
case
X86
::
MOVAPSrm
:
case
X86
::
MOVAPDrm
:
case
X86
::
MOVDQArm
:
case
X86
::
MMX_MOVD64rm
:
case
X86
::
MMX_MOVQ64rm
:
{
if
(
MI
->
getOperand
(
1
)
.
isReg
(
)
&&
MI
->
getOperand
(
2
)
.
isImm
(
)
&&
MI
->
getOperand
(
3
)
.
isReg
(
)
&&
MI
->
getOperand
(
3
)
.
getReg
(
)
==
0
&&
(
MI
->
getOperand
(
4
)
.
isCPI
(
)
||
(
MI
->
getOperand
(
4
)
.
isGlobal
(
)
&&
isGVStub
(
MI
->
getOperand
(
4
)
.
getGlobal
(
)
,
TM
)
)
)
)
{
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
BaseReg
==
0
)
return
true
;
if
(
!
ReMatPICStubLoad
&&
MI
->
getOperand
(
4
)
.
isGlobal
(
)
)
return
false
;
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
bool
isPICBase
=
false
;
for
(
MachineRegisterInfo
::
def_iterator
I
=
MRI
.
def_begin
(
BaseReg
)
,
E
=
MRI
.
def_end
(
)
;
I
!=
E
;
++
I
)
{
MachineInstr
*
DefMI
=
I
.
getOperand
(
)
.
getParent
(
)
;
if
(
DefMI
->
getOpcode
(
)
!=
X86
::
MOVPC32r
)
return
false
;
assert
(
!
isPICBase
&&
"More than one PIC base?"
)
;
isPICBase
=
true
;
}
return
isPICBase
;
}
return
false
;
}
case
X86
::
LEA32r
:
case
X86
::
LEA64r
:
{
if
(
MI
->
getOperand
(
2
)
.
isImm
(
)
&&
MI
->
getOperand
(
3
)
.
isReg
(
)
&&
MI
->
getOperand
(
3
)
.
getReg
(
)
==
0
&&
!
MI
->
getOperand
(
4
)
.
isReg
(
)
)
{
if
(
!
MI
->
getOperand
(
1
)
.
isReg
(
)
)
return
true
;
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
BaseReg
==
0
)
return
true
;
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
return
regIsPICBase
(
BaseReg
,
MRI
)
;
}
return
false
;
}
}
return
true
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'v' : case 'Y' : case 'l' : return C_RegisterClass ; case 'k' : case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'Y' : switch ( Constraint [ 1 ] ) { default : break ; case 'k' : return C_Register ; } } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static int ix86_mode_exit ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return X86_DIRFLAG_ANY ; case AVX_U128 : return ix86_avx_u128_mode_exit ( ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function exit .


<s> const ARM64RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
Mips16FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
Mips16InstrInfo
&
TII
=
*
static_cast
<
const
Mips16InstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
->
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineLocation
DstML
,
SrcML
;
TII
.
makeFrame
(
Mips
::
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
->
getCalleeSavedInfo
(
)
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
->
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
unsigned
DReg
=
MRI
->
getDwarfRegNum
(
Reg
,
true
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
DReg
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
if
(
hasFP
(
MF
)
)
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Mips
::
MoveR3216
)
,
Mips
::
S0
)
.
addReg
(
Mips
::
SP
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips
Mips
"Shrink-wrapping not yet supported"
Mips
Mips
0
Mips::SP
Mips::MoveR3216
Mips::S0
Mips::SP


<s> static bool ix86_legitimate_constant_p ( machine_mode , rtx x ) { if ( POINTER_BOUNDS_MODE_P ( GET_MODE ( x ) ) ) return false ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) == TImode && x != CONST0_RTX ( TImode ) && ! TARGET_64BIT ) return false ; break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x ) ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> void ARMTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { ARMELFStreamer & Streamer = getStreamer ( ) ; if ( ! Streamer . IsThumb ) return ; const MCSymbolData & SD = Streamer . getOrCreateSymbolData ( Symbol ) ; unsigned Type = MCELF :: GetType ( SD ) ; if ( Type == ELF_STT_Func || Type == ELF_STT_GnuIFunc ) Streamer . EmitThumbFunc ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s> bool PPCTargetLowering :: preferIncOfAddToSubOfNot ( EVT VT ) const { return VT . isScalarInteger ( ) ; } </s>

These two forms are equivalent : sub y , ( xor x , -1 ) add ( add x , 1 ) , y The variant with two add 's is IR-canonical .


<s>
static
void
dump_target_flag_bits
(
const
int
flags
)
{
if
(
flags
&
MASK_64BIT
)
fprintf
(
stderr
,
"64BIT "
)
;
if
(
flags
&
MASK_APP_REGS
)
fprintf
(
stderr
,
"APP_REGS "
)
;
if
(
flags
&
MASK_FASTER_STRUCTS
)
fprintf
(
stderr
,
"FASTER_STRUCTS "
)
;
if
(
flags
&
MASK_FLAT
)
fprintf
(
stderr
,
"FLAT "
)
;
if
(
flags
&
MASK_FMAF
)
fprintf
(
stderr
,
"FMAF "
)
;
if
(
flags
&
MASK_FPU
)
fprintf
(
stderr
,
"FPU "
)
;
if
(
flags
&
MASK_HARD_QUAD
)
fprintf
(
stderr
,
"HARD_QUAD "
)
;
if
(
flags
&
MASK_POPC
)
fprintf
(
stderr
,
"POPC "
)
;
if
(
flags
&
MASK_PTR64
)
fprintf
(
stderr
,
"PTR64 "
)
;
if
(
flags
&
MASK_STACK_BIAS
)
fprintf
(
stderr
,
"STACK_BIAS "
)
;
if
(
flags
&
MASK_UNALIGNED_DOUBLES
)
fprintf
(
stderr
,
"UNALIGNED_DOUBLES "
)
;
if
(
flags
&
MASK_V8PLUS
)
fprintf
(
stderr
,
"V8PLUS "
)
;
if
(
flags
&
MASK_VIS
)
fprintf
(
stderr
,
"VIS "
)
;
if
(
flags
&
MASK_VIS2
)
fprintf
(
stderr
,
"VIS2 "
)
;
if
(
flags
&
MASK_VIS3
)
fprintf
(
stderr
,
"VIS3 "
)
;
if
(
flags
&
MASK_VIS4
)
fprintf
(
stderr
,
"VIS4 "
)
;
if
(
flags
&
MASK_CBCOND
)
fprintf
(
stderr
,
"CBCOND "
)
;
if
(
flags
&
MASK_DEPRECATED_V8_INSNS
)
fprintf
(
stderr
,
"DEPRECATED_V8_INSNS "
)
;
if
(
flags
&
MASK_SPARCLET
)
fprintf
(
stderr
,
"SPARCLET "
)
;
if
(
flags
&
MASK_SPARCLITE
)
fprintf
(
stderr
,
"SPARCLITE "
)
;
if
(
flags
&
MASK_V8
)
fprintf
(
stderr
,
"V8 "
)
;
if
(
flags
&
MASK_V9
)
fprintf
(
stderr
,
"V9 "
)
;
}
</s>

sparc
"64BIT "
"APP_REGS "
"FASTER_STRUCTS "
"FLAT "
"FMAF "
"FPU "
"HARD_QUAD "
"POPC "
"PTR64 "
"STACK_BIAS "
"UNALIGNED_DOUBLES "
"V8PLUS "
"VIS "
"VIS2 "
"VIS3 "
"VIS4 "
"CBCOND "
"DEPRECATED_V8_INSNS "
"SPARCLET "
"SPARCLITE "
"V8 "
"V9 "


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . isTargetNaCl ( ) ) { static const uint16_t PnaclReservedCPURegs [ ] = { Mips :: T6 , Mips :: T7 , Mips :: T8 } ; for ( unsigned I = 0 ; I < array_lengthof ( PnaclReservedCPURegs ) ; ++ I ) Reserved . set ( PnaclReservedCPURegs [ I ] ) ; } for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPCtrl ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void assign_int_registers ( int bitpos , assign_data_t * data ) { int intoffset = data -> intoffset ; machine_mode mode ; int nregs ; if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != 0 ) mode = smallest_int_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; data -> nregs += 1 ; mode = word_mode ; regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign the bits of the structure between PARMS- > intoffset and BITPOS to integer registers .


<s> bool SystemZTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static int sparc_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ) { int slotno , regno , padding ; slotno = function_arg_slotno ( cum , mode , type , named , 0 , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { if ( ( slotno + ( mode == BLKmode ? ROUND_ADVANCE ( int_size_in_bytes ( type ) ) : ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) ) ) > SPARC_INT_ARG_MAX ) return ( SPARC_INT_ARG_MAX - slotno ) * UNITS_PER_WORD ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && ! ( TARGET_FPU && named ) ) ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( ( slotno + GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ) > SPARC_FP_ARG_MAX ) return UNITS_PER_WORD ; } } return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes of registers used . For args passed entirely in registers or entirely in memory , zero . Any arg that starts in the first 6 regs but wo n't entirely fit in them needs partial registers on v8 . On v9 , structures with integer values in arg slots 5,6 will be passed in % o5 and SP+176 , and complex fp values that begin in the last fp reg [ where `` last fp reg '' varies with the mode ] will be split between that reg and memory .


<s> static tree sparc_gimplify_va_arg ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { HOST_WIDE_INT size , rsize , align ; tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_va_arg_by_reference ( type ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = 0 ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ROUND_UP ( size , UNITS_PER_WORD ) ; align = 0 ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= 2 * ( unsigned ) BITS_PER_WORD ) align = 2 * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == 0 ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold_build_pointer_plus_hwi ( incr , align - 1 ) ; incr = fold_convert ( sizetype , incr ) ; incr = fold_build2 ( BIT_AND_EXPR , sizetype , incr , size_int ( - align ) ) ; incr = fold_convert ( ptr_type_node , incr ) ; } gimplify_expr ( & incr , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = incr ; if ( BYTES_BIG_ENDIAN && size < rsize ) addr = fold_build_pointer_plus_hwi ( incr , rsize - size ) ; if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ; } else if ( align == 0 && TYPE_ALIGN ( type ) > BITS_PER_WORD ) { tree tmp = create_tmp_var ( type , "va_arg_tmp" ) ; tree dest_addr = build_fold_addr_expr ( tmp ) ; tree copy = build_call_expr ( builtin_decl_implicit ( BUILT_IN_MEMCPY ) , 3 , dest_addr , addr , size_int ( rsize ) ) ; TREE_ADDRESSABLE ( tmp ) = 1 ; gimplify_and_add ( copy , pre_p ) ; addr = dest_addr ; } else addr = fold_convert ( ptrtype , addr ) ; incr = fold_build_pointer_plus_hwi ( incr , rsize ) ; gimplify_assign ( valist , incr , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>


<s> bool isReg ( ) const override { return Kind == REGISTER ; } </s>


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 128 ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; if ( Subtarget -> hasLSE ( ) && Size < 128 ) return AtomicExpansionKind :: None ; if ( Subtarget -> outlineAtomics ( ) && Size < 128 ) { if ( AI -> getOperation ( ) != AtomicRMWInst :: Min && AI -> getOperation ( ) != AtomicRMWInst :: Max && AI -> getOperation ( ) != AtomicRMWInst :: UMin && AI -> getOperation ( ) != AtomicRMWInst :: UMax ) { return AtomicExpansionKind :: None ; } } return AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s>
SUnit
*
SystemZPostRASchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
IsTopNode
=
true
;
if
(
Available
.
empty
(
)
)
return
nullptr
;
if
(
Available
.
size
(
)
==
1
)
{
DEBUG
(
dbgs
(
)
<<
"** Only one: "
;
HazardRec
->
dumpSU
(
*
Available
.
begin
(
)
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
return
*
Available
.
begin
(
)
;
}
DEBUG
(
dbgs
(
)
<<
"** Available: "
;
Available
.
dump
(
*
HazardRec
)
;
)
;
Candidate
Best
;
for
(
auto
*
SU
:
Available
)
{
Candidate
c
(
SU
,
*
HazardRec
)
;
if
(
Best
.
SU
==
nullptr
||
c
<
Best
)
{
Best
=
c
;
DEBUG
(
dbgs
(
)
<<
"** Best so far: "
;
)
;
}
else
DEBUG
(
dbgs
(
)
<<
"** Tried      : "
;
)
;
DEBUG
(
HazardRec
->
dumpSU
(
c
.
SU
,
dbgs
(
)
)
;
c
.
dumpCosts
(
)
;
dbgs
(
)
<<
" Height:"
<<
c
.
SU
->
getHeight
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
if
(
!
SU
->
isScheduleHigh
&&
Best
.
noCost
(
)
)
break
;
}
assert
(
Best
.
SU
!=
nullptr
)
;
return
Best
.
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

SystemZ
SystemZ
1
"** Only one: "
"\n"
"** Available: "
"** Best so far: "
"** Tried      : "
" Height:"
"\n"


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetMachO ( ) || Subtarget -> isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


"%qs and floating point or vector arguments"


<s> void PPCPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( createPPCVSXSwapRemovalPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SystemZ Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; default : return NULL_TREE ; } return ix86_builtins [ code ] ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; Reserved . set ( ARM :: APSR_NZCV ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> static void fold_mergehl_helper ( gimple_stmt_iterator * gsi , gimple * stmt , int use_high ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree lhs_type = TREE_TYPE ( lhs ) ; int n_elts = TYPE_VECTOR_SUBPARTS ( lhs_type ) ; int midpoint = n_elts / 2 ; int offset = 0 ; if ( use_high == 1 ) offset = midpoint ; tree permute_type ; permute_type = map_to_integral_tree_type ( lhs_type ) ; tree_vector_builder elts ( permute_type , VECTOR_CST_NELTS ( arg0 ) , 1 ) ; for ( int i = 0 ; i < midpoint ; i ++ ) { elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , offset + i ) ) ; elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , offset + n_elts + i ) ) ; } tree permute = elts . build ( ) ; gimple * g = gimple_build_assign ( lhs , VEC_PERM_EXPR , arg0 , arg1 , permute ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the vector merge [ hl ] built-ins . The implementation difference between h and l versions for this code are in the values used when building of the permute vector for high word versus low word merge . The variance is keyed off the use_high parameter .


<s> Register MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
TargetLowering
::
ConstraintWeight
AArch64TargetLowering
::
getSingleConstraintMatchWeight
(
AsmOperandInfo
&
Info
,
const
char
*
Constraint
)
const
{
llvm_unreachable
(
"Constraint weight unimplemented"
)
;
}
</s>

Examine constraint string and operand type and determine a weight value .


<s> static rtx mark_constant_pool_use ( rtx x ) { rtx_insn * insn , * lab ; rtx pattern ; if ( x == NULL_RTX ) return x ; switch ( GET_CODE ( x ) ) { case LABEL_REF : x = XEXP ( x , 0 ) ; case CODE_LABEL : break ; default : return x ; } lab = as_a < rtx_insn * > ( x ) ; for ( insn = PREV_INSN ( lab ) ; insn ; insn = PREV_INSN ( insn ) ) { if ( ! LABEL_P ( insn ) || LABEL_REFS ( insn ) != NEXT_INSN ( insn ) ) break ; lab = insn ; } for ( rtx insn = LABEL_REFS ( lab ) ; insn ; insn = LABEL_REFS ( insn ) ) as_a < rtx_insn * > ( insn ) -> set_deleted ( ) ; for ( insn = NEXT_INSN ( as_a < rtx_insn * > ( x ) ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! NONJUMP_INSN_P ( insn ) ) continue ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != UNSPEC_VOLATILE ) continue ; switch ( XINT ( pattern , 1 ) ) { case UNSPECV_CONST2 : case UNSPECV_CONST4 : case UNSPECV_CONST8 : XVECEXP ( pattern , 0 , 1 ) = const1_rtx ; break ; case UNSPECV_WINDOW_END : if ( XVECEXP ( pattern , 0 , 0 ) == x ) return lab ; break ; case UNSPECV_CONST_END : return lab ; default : break ; } } return lab ; } </s>

Mark the use of a constant in the literal table . If the constant has multiple labels , make it unique .


<s> bool PPCInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned OpC = MI . getOpcode ( ) ; switch ( OpC ) { default : return false ; case PPC :: B : case PPC :: BLR : case PPC :: BLR8 : case PPC :: BCTR : case PPC :: BCTR8 : case PPC :: BCTRL : case PPC :: BCTRL8 : return true ; } } </s>

Return true if the specified instruction can be predicated .

PowerPC PPC PPC::B PPC::BLR PPC::BLR8 PPC::BCTR PPC::BCTR8 PPC::BCTRL PPC::BCTRL8


<s> static void aarch64_pop_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment , rtx * cfi_ops ) { machine_mode mode = ( regno1 <= R30_REGNUM ) ? DImode : DFmode ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg1 , * cfi_ops ) ; if ( regno2 == INVALID_REGNUM ) { rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_rtx_MEM ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; } } </s>

Pop the two registers numbered REGNO1 , REGNO2 from the stack , adjusting it afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> bool PPCTTIImpl :: enableInterleavedAccessVectorization ( ) { return true ; } </s>

Enable matching of interleaved access groups .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N -> getOperand ( 0 ) ; SDValue N1 = N -> getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool Cpu0FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const MCPhysReg ReservedGPR32 [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const MCPhysReg ReservedGPR64 [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; for ( MCPhysReg R : ReservedGPR32 ) Reserved . set ( R ) ; if ( Subtarget . isTargetNaCl ( ) ) { Reserved . set ( Mips :: T6 ) ; Reserved . set ( Mips :: T7 ) ; Reserved . set ( Mips :: T8 ) ; } for ( MCPhysReg R : ReservedGPR64 ) Reserved . set ( R ) ; if ( ! Subtarget . isABICalls ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } if ( Subtarget . isFP64bit ( ) ) { for ( MCPhysReg Reg : Mips :: AFGR64RegClass ) Reserved . set ( Reg ) ; } else { for ( MCPhysReg Reg : Mips :: FGR64RegClass ) Reserved . set ( Reg ) ; } if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; if ( hasStackRealignment ( MF ) && MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { Reserved . set ( Mips :: S7 ) ; Reserved . set ( Mips :: S7_64 ) ; } } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: DSPPos ) ; Reserved . set ( Mips :: DSPSCount ) ; Reserved . set ( Mips :: DSPCarry ) ; Reserved . set ( Mips :: DSPEFI ) ; Reserved . set ( Mips :: DSPOutFlag ) ; for ( MCPhysReg Reg : Mips :: MSACtrlRegClass ) Reserved . set ( Reg ) ; if ( Subtarget . inMips16Mode ( ) ) { const MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; Reserved . set ( Mips :: T0 ) ; Reserved . set ( Mips :: T1 ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "saveS2" ) || MipsFI -> hasSaveS2 ( ) ) Reserved . set ( Mips :: S2 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool rs6000_return_in_msb ( const_tree valtype ) { return ( DEFAULT_ABI == ABI_ELFv2 && BYTES_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && FUNCTION_ARG_PADDING ( TYPE_MODE ( valtype ) , valtype ) == upward ) ; } </s>

Specify whether values returned in registers should be at the most significant end of a register . We want aggregates returned by value to match the way aggregates are passed to functions .


<s> ARMConstantPoolSymbol * ARMConstantPoolSymbol :: Create ( LLVMContext & C , StringRef s , ARMCP :: ARMCPModifier Modifier ) { return new ARMConstantPoolSymbol ( C , s , 0 , 0 , Modifier , false ) ; } </s>

Construct a unary instruction , given the opcode and an operand .

ARM ARM ARM ARMCP::ARMCPModifier ARM 0 0


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , neg_bval ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = ( operands [ 5 ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ 6 ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 7 ] ) ) ; neg_bval = TARGET_THUMB1 ? operands [ 0 ] : operands [ 8 ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_release ( mod_s ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_acquire ( mod_s ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; if ( TARGET_32BIT ) { cond = arm_gen_compare_reg ( NE , rval , oldval , neg_bval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { emit_move_insn ( neg_bval , const1_rtx ) ; cond = gen_rtx_NE ( VOIDmode , rval , oldval ) ; if ( thumb1_cmpneg_operand ( oldval , SImode ) ) emit_unlikely_jump ( gen_cbranchsi4_scratch ( neg_bval , rval , oldval , label2 , cond ) ) ; else emit_unlikely_jump ( gen_cbranchsi4_insn ( cond , rval , oldval , label2 ) ) ; } arm_emit_store_exclusive ( mode , neg_bval , mem , newval , use_release ) ; if ( TARGET_32BIT ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , neg_bval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , neg_bval , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , neg_bval , const0_rtx , label1 ) ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> TargetTransformInfo PPCTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( PPCTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static rtx scale_counter ( rtx countreg , int scale ) { rtx sc ; if ( scale == 1 ) return countreg ; if ( CONST_INT_P ( countreg ) ) return GEN_INT ( INTVAL ( countreg ) / scale ) ; gcc_assert ( REG_P ( countreg ) ) ; sc = expand_simple_binop ( GET_MODE ( countreg ) , LSHIFTRT , countreg , GEN_INT ( exact_log2 ( scale ) ) , NULL , 1 , OPTAB_DIRECT ) ; return sc ; } </s>


<s> bool Thumb1RegisterInfo :: hasReservedCallFrame ( MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> int aarch64_epilogue_uses ( int regno ) { if ( epilogue_completed ) { if ( regno == LR_REGNUM ) return 1 ; if ( aarch64_simd_decl_p ( cfun -> decl ) && FP_SIMD_SAVED_REGNUM_P ( regno ) ) return 1 ; } return 0 ; } </s>

Return 1 if the register is used by the epilogue . We need to say the return register is used , but only after epilogue generation is complete . Note that in the case of sibcalls , the values `` used by the epilogue '' are considered live at the start of the called function . For SIMD functions we need to return 1 for FP registers that are saved and restored by a function but are not zero in call_used_regs . If we do not do this optimizations may remove the restore of the register .


<s> const char * ARMRelocator :: getName ( Relocator :: Type pType ) const { return ApplyFunctions [ pType ] . name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> std :: string getDataLayout ( ) const { return "e-p:32:32-i:32:32-f:32:32" ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == 64 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 64 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


<s> void AArch64InstrInfo :: suppressLdStPair ( MachineInstr & MI ) { if ( MI . memoperands_empty ( ) ) return ; ( * MI . memoperands_begin ( ) ) -> setFlags ( MOSuppressPair ) ; } </s>

Hint that pairing the given load or store is unprofitable .


" is allocatable: function has no frame pointer"

Return the register ID of the name passed in .


<s> bool ARMTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return ARM_AM :: getSOImmVal ( Imm ) != - 1 ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void SICTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const SICTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> static machine_mode aarch64_simd_container_mode ( machine_mode mode , unsigned width ) { gcc_assert ( width == 64 || width == 128 ) ; if ( TARGET_SIMD ) { if ( width == 128 ) switch ( mode ) { case DFmode : return V2DFmode ; case SFmode : return V4SFmode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; case DImode : return V2DImode ; default : break ; } else switch ( mode ) { case SFmode : return V2SFmode ; case SImode : return V2SImode ; case HImode : return V4HImode ; case QImode : return V8QImode ; default : break ; } } return word_mode ; } </s>

Return appropriate SIMD container for MODE within a vector of WIDTH bits .


<s> static int rank_for_reorder ( const void * x , const void * y ) { rtx tmp = * ( const rtx * ) y ; rtx tmp2 = * ( const rtx * ) x ; if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? 1 : - 1 ; return INSN_LUID ( tmp ) - INSN_LUID ( tmp2 ) ; } </s>

Comparison function for ready queue sorting .


<s> opt_machine_mode aarch64_vq_mode ( scalar_mode mode ) { switch ( mode ) { case E_DFmode : return V2DFmode ; case E_SFmode : return V4SFmode ; case E_HFmode : return V8HFmode ; case E_BFmode : return V8BFmode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; case E_DImode : return V2DImode ; default : return opt_machine_mode ( ) ; } } </s>

Return the 128-bit Advanced SIMD vector mode for element mode MODE , if it exists .


"%qE attribute only applies to functions"

Handle a `` longcall '' attribute ; arguments as in struct attribute_spec.handler .


<s> static bool loongarch_tls_symbol_p ( rtx x ) { return SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return true if X is a thread-local symbol .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : if ( ! Subtarget . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVSX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> static rtx mips16_gp_pseudo_reg ( void ) { if ( cfun -> machine -> mips16_gp_pseudo_rtx == NULL_RTX ) { rtx_insn * scan ; cfun -> machine -> mips16_gp_pseudo_rtx = gen_reg_rtx ( Pmode ) ; push_topmost_sequence ( ) ; scan = get_insns ( ) ; while ( NEXT_INSN ( scan ) && ! INSN_P ( NEXT_INSN ( scan ) ) ) scan = NEXT_INSN ( scan ) ; rtx set = gen_load_const_gp ( cfun -> machine -> mips16_gp_pseudo_rtx ) ; rtx_insn * insn = emit_insn_after ( set , scan ) ; INSN_LOCATION ( insn ) = 0 ; pop_topmost_sequence ( ) ; } return cfun -> machine -> mips16_gp_pseudo_rtx ; } </s>

If we can access small data directly ( using gp-relative relocation operators ) return the small data pointer , otherwise return null . For each mips16 function which refers to GP relative symbols , we use a pseudo register , initialized at the start of the function , to hold the $ gp value .


<s>
char
*
output_call
(
rtx_insn
*
insn
,
rtx
*
operands
,
int
dest_operand_number
,
int
cookie_operand_number
)
{
static
char
buf
[
256
]
;
if
(
darwin_emit_branch_islands
&&
GET_CODE
(
operands
[
dest_operand_number
]
)
==
SYMBOL_REF
&&
(
INTVAL
(
operands
[
cookie_operand_number
]
)
&
CALL_LONG
)
)
{
tree
labelname
;
tree
funname
=
get_identifier
(
XSTR
(
operands
[
dest_operand_number
]
,
0
)
)
;
if
(
no_previous_def
(
funname
)
)
{
rtx
label_rtx
=
gen_label_rtx
(
)
;
char
*
label_buf
,
temp_buf
[
256
]
;
ASM_GENERATE_INTERNAL_LABEL
(
temp_buf
,
"L"
,
CODE_LABEL_NUMBER
(
label_rtx
)
)
;
label_buf
=
temp_buf
[
0
]
==
'*'
temp_buf
+
1
:
temp_buf
;
labelname
=
get_identifier
(
label_buf
)
;
add_compiler_branch_island
(
labelname
,
funname
,
insn_line
(
insn
)
)
;
}
else
labelname
=
get_prev_label
(
funname
)
;
sprintf
(
buf
,
"jbsr %%z%d,%.246s"
,
dest_operand_number
,
IDENTIFIER_POINTER
(
labelname
)
)
;
}
else
sprintf
(
buf
,
"bl %%z%d"
,
dest_operand_number
)
;
return
buf
;
}
</s>

INSN is either a function call or a millicode call . It may have an unconditional jump in its delay slot . CALL_DEST is the routine we are calling .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return true ; if ( Kind == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; AArch64MCExpr :: VariantKind RefKind = static_cast < AArch64MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; AArch64MCExpr :: VariantKind SymLoc = AArch64MCExpr :: getSymbolLoc ( RefKind ) ; if ( Kind == AArch64 :: fixup_aarch64_ldr_pcrel_imm19 && SymLoc == AArch64MCExpr :: VK_GOT ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static void ix86_store_bounds ( rtx ptr , rtx slot , rtx bounds , rtx slot_no ) { rtx addr ; addr = ix86_get_arg_address_for_bt ( slot , slot_no , stack_pointer_rtx ) ; if ( ! ptr ) { gcc_assert ( MEM_P ( slot ) ) ; ptr = copy_addr_to_reg ( slot ) ; } if ( ! register_operand ( ptr , Pmode ) ) ptr = ix86_zero_extend_to_Pmode ( ptr ) ; gcc_assert ( POINTER_BOUNDS_MODE_P ( GET_MODE ( bounds ) ) ) ; if ( ! register_operand ( bounds , BNDmode ) ) bounds = copy_to_mode_reg ( BNDmode , bounds ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_stx ( addr , ptr , bounds ) : gen_bnd32_stx ( addr , ptr , bounds ) ) ; } </s>

Expand pass uses this hook to store BOUNDS for call argument PTR passed in SLOT in case BOUNDS are not passed in a register . If SLOT is a memory , then BOUNDS are stored as for regular pointer stored in memory . PTR may be NULL in case SLOT is a memory . In such case value of PTR ( if required ) may be loaded from SLOT . If SLOT is NULL or a register then SLOT_NO is an integer constant holding number of the target dependent special slot which should be used to store BOUNDS .


<s> unsigned TOYInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function * F = MF . getFunction ( ) ; if ( ! F -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( F -> hasAddressTaken ( ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F -> hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s>
unsigned
assignCustomValue
(
const
CallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
unsigned
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
MIRBuilder
.
buildExtract
(
NewRegs
[
0
]
,
Arg
.
Reg
,
0
)
;
MIRBuilder
.
buildExtract
(
NewRegs
[
1
]
,
Arg
.
Reg
,
32
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>


<s> static rtx alignment_mask ( rtx_insn * insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != AND || ! REG_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 0 ; rtx mask = XEXP ( SET_SRC ( body ) , 1 ) ; if ( GET_CODE ( mask ) == CONST_INT ) { if ( INTVAL ( mask ) == - 16 ) return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; else return 0 ; } if ( ! REG_P ( mask ) ) return 0 ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; rtx real_mask = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( use ) , mask ) ) continue ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return 0 ; rtx_insn * const_insn = DF_REF_INSN ( def_link -> ref ) ; rtx const_body = PATTERN ( const_insn ) ; if ( GET_CODE ( const_body ) != SET ) return 0 ; real_mask = SET_SRC ( const_body ) ; if ( GET_CODE ( real_mask ) != CONST_INT || INTVAL ( real_mask ) != - 16 ) return 0 ; } if ( real_mask == 0 ) return 0 ; return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; } </s>

Check whether an rtx is an alignment mask , and if so , return a fully-expanded rtx for the masking operation .


<s> static bool aarch64_expand_sve_ld1rq ( rtx dest , rtx src ) { src = force_const_mem ( GET_MODE ( src ) , src ) ; if ( ! src ) return false ; if ( ! aarch64_sve_ld1rq_operand_p ( src ) ) { rtx addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; src = replace_equiv_address ( src , addr ) ; } machine_mode mode = GET_MODE ( dest ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( mode ) ; rtx ptrue = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_sve_ld1rq ( mode , dest , src , ptrue ) ) ; return true ; } </s>

Try to force 128-bit vector value SRC into memory and use LD1RQ to fetch the memory image into DEST . Return true on success .


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { switch ( MI -> getOpcode ( ) ) { default : break ; } if ( ! printAliasInstr ( MI , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static int mips_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & arg ) { struct mips_arg_info info ; mips_get_arg_info ( & info , get_cumulative_args ( cum ) , arg . mode , arg . type , arg . named ) ; return info . stack_words > 0 ? info . reg_words * UNITS_PER_WORD : 0 ; } </s>


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
unsigned
OutgoingValueHandler
::
extendRegister
(
unsigned
ValReg
,
const
CCValAssign
&
VA
)
{
LLT
LocTy
{
VA
.
getLocVT
(
)
}
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
SExt
:
{
unsigned
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildSExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
ZExt
:
{
unsigned
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildZExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
AExt
:
{
unsigned
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildAnyExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
Full
:
return
ValReg
;
default
:
break
;
}
llvm_unreachable
(
"unable to extend register"
)
;
}
</s>

Extend a register to the location type given in VA , capped at extending to at most MaxSize bits .


<s> static void loongarch_save_restore_reg ( machine_mode mode , int regno , HOST_WIDE_INT offset , loongarch_save_restore_fn fn ) { rtx mem ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode , regno ) , mem ) ; } </s>

Use FN to save or restore register REGNO . MODE is the register 's mode and OFFSET is the offset of its save slot from the current stack pointer .


<s> bool X86Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> void MipsTargetStreamer :: emitStoreWithImmOffset ( unsigned Opcode , unsigned SrcReg , unsigned BaseReg , int64_t Offset , function_ref < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { if ( isInt < 16 > ( Offset ) ) { emitRRI ( Opcode , SrcReg , BaseReg , Offset , IDLoc , STI ) ; return ; } unsigned ATReg = GetATReg ( ) ; if ( ! ATReg ) return ; unsigned LoOffset = Offset & 0x0000ffff ; unsigned HiOffset = ( Offset & 0xffff0000 ) >> 16 ; if ( LoOffset & 0x8000 ) HiOffset ++ ; emitRI ( Mips :: LUi , ATReg , HiOffset , IDLoc , STI ) ; if ( BaseReg != Mips :: ZERO ) emitRRR ( Mips :: ADDu , ATReg , ATReg , BaseReg , IDLoc , STI ) ; emitRRI ( Opcode , SrcReg , ATReg , LoOffset , IDLoc , STI ) ; } </s>

Emit a store instruction with an offset .


<s> bool isLittleEndian ( ) const { return IsLittleEndian ; } </s>

Tests whether the target triple is little endian .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( PPC :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
{
OS
<<
getPSBHintName
(
)
;
break
;
}
case
k_ShiftExtend
:
{
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<register "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> static int rs6000_emit_p9_fp_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode result_mode = GET_MODE ( dest ) ; rtx compare_rtx ; rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return 0 ; switch ( code ) { case EQ : case GE : case GT : break ; case NE : case LT : case LE : code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : return 0 ; } compare_rtx = gen_rtx_fmt_ee ( code , CCFPmode , op0 , op1 ) ; cmove_rtx = gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , compare_rtx , true_cond , false_cond ) ) ; clobber_rtx = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( V2DImode ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , cmove_rtx , clobber_rtx ) ) ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) conditional move subcase to emit XSCMP { EQ , GE , GT , NE } DP and XXSEL instructions for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s> static bool mips_lra_p ( void ) { return mips_lra_flag ; } </s>


This function will set the fpscr from memory . MODE is the mode we are setting it to .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { Align Alignment = Subtarget . isPPC64 ( ) ? Align ( 8 ) : Align ( 4 ) ; if ( Subtarget . hasAltivec ( ) ) getMaxByValAlign ( Ty , Alignment , Align ( 16 ) ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) reg_size = UNITS_PER_SPE_WORD ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else if ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SCmode && ! DECIMAL_FLOAT_MODE_P ( mode ) && SPE_SIMD_REGNO_P ( regno ) ) reg_size = UNITS_PER_FP_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


<s> static bool swap_top_of_ready_list ( rtx_insn * * ready , int n_ready ) { rtx_insn * top = ready [ n_ready - 1 ] ; rtx_insn * next = ready [ n_ready - 2 ] ; rtx set ; sd_iterator_def sd_it ; dep_t dep ; int clock1 = - 1 ; int clock2 = - 1 ; if ( ! TARGET_SILVERMONT && ! TARGET_INTEL ) return false ; if ( ! NONDEBUG_INSN_P ( top ) ) return false ; if ( ! NONJUMP_INSN_P ( top ) ) return false ; if ( ! NONDEBUG_INSN_P ( next ) ) return false ; if ( ! NONJUMP_INSN_P ( next ) ) return false ; set = single_set ( top ) ; if ( ! set ) return false ; set = single_set ( next ) ; if ( ! set ) return false ; if ( INSN_PRIORITY_KNOWN ( top ) && INSN_PRIORITY_KNOWN ( next ) ) { if ( INSN_PRIORITY ( top ) != INSN_PRIORITY ( next ) ) return false ; FOR_EACH_DEP ( top , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock1 ) clock1 = INSN_TICK ( pro ) ; } FOR_EACH_DEP ( next , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock2 ) clock2 = INSN_TICK ( pro ) ; } if ( clock1 == clock2 ) { enum attr_memory memory1 , memory2 ; memory1 = get_attr_memory ( top ) ; memory2 = get_attr_memory ( next ) ; if ( memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD ) return true ; } return ( bool ) ( clock2 < clock1 ) ; } return false ; } </s>

Try to find the best candidate on the top of ready list if two insns have the same priority - candidate is best if its dependees were scheduled earlier . Applied for Silvermont only . Return true if top 2 insns must be interchanged .


<s> bool ELFAArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( ( uint32_t ) Fixup . getKind ( ) == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && IS_CMSE_ENTRY ( func_type ) ) return 0 ; if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
static
void
aarch64_parse_cpu
(
void
)
{
char
*
ext
;
const
struct
processor
*
cpu
;
char
*
str
=
(
char
*
)
alloca
(
strlen
(
aarch64_cpu_string
)
+
1
)
;
size_t
len
;
strcpy
(
str
,
aarch64_cpu_string
)
;
ext
=
strchr
(
str
,
'+'
)
;
if
(
ext
!=
)
len
=
ext
str
;
else
len
=
strlen
(
str
)
;
if
(
len
==
0
)
{
error
(
"missing cpu name in -mcpu=%qs"
,
str
)
;
return
;
}
for
(
cpu
=
all_cores
;
cpu
->
name
!=
;
cpu
++
)
{
if
(
strlen
(
cpu
->
name
)
==
len
&&
strncmp
(
cpu
->
name
,
str
,
len
)
==
0
)
{
selected_cpu
=
cpu
;
aarch64_isa_flags
=
selected_cpu
->
flags
;
if
(
ext
!=
)
{
aarch64_parse_extension
(
ext
)
;
}
return
;
}
}
error
(
"unknown value %qs for -mcpu"
,
str
)
;
return
;
}
</s>

Parse the TO_PARSE string and put the result tuning in RES and the architecture flags in ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && INTVAL ( mod_f ) == MEMMODEL_ACQUIRE && INTVAL ( mod_s ) == MEMMODEL_RELEASE ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , bval , x ) ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Cpu0 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
.
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getLocVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
||
CopyVT
==
MVT
::
f128
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
.
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
bool
RoundAfterCopy
=
false
;
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
if
(
!
Subtarget
.
hasX87
(
)
)
report_fatal_error
(
"X87 register return with X87 disabled"
)
;
CopyVT
=
MVT
::
f80
;
RoundAfterCopy
=
(
CopyVT
!=
VA
.
getLocVT
(
)
)
;
}
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
RoundAfterCopy
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
,
dl
)
)
;
if
(
VA
.
isExtInLoc
(
)
&&
VA
.
getValVT
(
)
.
getScalarType
(
)
==
MVT
::
i1
)
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void mips_order_regs_for_local_alloc ( void ) { register int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = i ; if ( TARGET_MIPS16 ) { reg_alloc_order [ 0 ] = 24 ; reg_alloc_order [ 24 ] = 0 ; } } </s>

On the mips16 , we want to allocate $ 24 ( T_REG ) before other registers for instructions for which it is possible . This helps avoid shuffling registers around in order to set up for an xor , encouraging the compiler to use a cmp instead .


<s>
void
SystemZAsmPrinter
::
emitFunctionEntryLabel
(
)
{
const
SystemZSubtarget
&
Subtarget
=
MF
->
getSubtarget
<
SystemZSubtarget
>
(
)
;
if
(
Subtarget
.
getTargetTriple
(
)
.
isOSzOS
(
)
)
{
MCContext
&
OutContext
=
OutStreamer
->
getContext
(
)
;
std
::
string
N
(
MF
->
getFunction
(
)
.
hasName
(
)
Twine
(
MF
->
getFunction
(
)
.
getName
(
)
)
.
concat
(
"_"
)
.
str
(
)
:
""
)
;
CurrentFnEPMarkerSym
=
OutContext
.
createTempSymbol
(
Twine
(
"EPM_"
)
.
concat
(
N
)
.
str
(
)
,
true
)
;
CurrentFnPPA1Sym
=
OutContext
.
createTempSymbol
(
Twine
(
"PPA1_"
)
.
concat
(
N
)
.
str
(
)
,
true
)
;
const
MachineFrameInfo
&
MFFrame
=
MF
->
getFrameInfo
(
)
;
bool
IsUsingAlloca
=
MFFrame
.
hasVarSizedObjects
(
)
;
uint8_t
Flags
=
0
;
if
(
IsUsingAlloca
)
Flags
|=
0x04
;
uint32_t
DSASize
=
MFFrame
.
getStackSize
(
)
;
uint32_t
DSAAndFlags
=
DSASize
&
0xFFFFFFE0
;
DSAAndFlags
|=
Flags
;
OutStreamer
->
AddComment
(
"XPLINK Routine Layout Entry"
)
;
OutStreamer
->
emitLabel
(
CurrentFnEPMarkerSym
)
;
OutStreamer
->
AddComment
(
"Eyecatcher 0x00C300C500C500"
)
;
OutStreamer
->
emitIntValueInHex
(
0x00C300C500C500
,
7
)
;
OutStreamer
->
AddComment
(
"Mark Type C'1'"
)
;
OutStreamer
->
emitInt8
(
0xF1
)
;
OutStreamer
->
AddComment
(
"Offset to PPA1"
)
;
OutStreamer
->
emitAbsoluteSymbolDiff
(
CurrentFnPPA1Sym
,
CurrentFnEPMarkerSym
,
4
)
;
if
(
OutStreamer
->
isVerboseAsm
(
)
)
{
OutStreamer
->
AddComment
(
"DSA Size 0x"
+
Twine
::
utohexstr
(
DSASize
)
)
;
OutStreamer
->
AddComment
(
"Entry Flags"
)
;
if
(
Flags
&
0x04
)
OutStreamer
->
AddComment
(
"  Bit 2: 1 = Uses alloca"
)
;
else
OutStreamer
->
AddComment
(
"  Bit 2: 0 = Does not use alloca"
)
;
}
OutStreamer
->
emitInt32
(
DSAAndFlags
)
;
}
AsmPrinter
::
emitFunctionEntryLabel
(
)
;
}
</s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .