<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , DataLayout ( "E-p:32:32-f128:128:128" ) , Subtarget ( TT , FS ) , TLInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , 8 , 0 ) { } </s>


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; PPCFunctionInfo * FI = MF -> getInfo < PPCFunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == PPC :: X2 || Reg == PPC :: R2 ) && MustSaveTOC ) continue ; if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( ! Subtarget . is32BitELFABI ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . storeRegToStackSlotNoUpd ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; else TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n"


<s> int vfp3_const_double_rtx ( rtx x ) { if ( ! TARGET_VFP3 ) return 0 ; return vfp3_const_double_index ( x ) != - 1 ; } </s>

Return TRUE if rtx X is a valid immediate VFPv3 constant .


<s> rtx mmix_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { return count == 0 ? ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? validize_mem ( gen_rtx_MEM ( Pmode , plus_constant ( frame_pointer_rtx , - 16 ) ) ) : get_hard_reg_initial_val ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ) : NULL_RTX ; } </s>


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Tile Register Pre-configure"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"calling %qD with attribute sseregparm without "

"calling %qT with attribute sseregparm without "

Return 1 or 2 , if we can pass up to SSE_REGPARM_MAX SFmode ( 1 ) and DFmode ( 2 ) arguments in SSE registers for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall . Otherwise return 0 .


<s> rtx extract_nth_ls2_access_reg ( rtx_insn * insn , int n ) { rtx reg ; machine_mode mode ; if ( post_update_insn_p ( insn ) ) { memory_access_direction direction = determine_access_direction ( insn ) ; gcc_assert ( direction != MEM_ACCESS_DIR_UNKNOWN ) ; if ( direction == MEM_ACCESS_DIR_NEG ) n = - 1 * n - 1 ; } if ( n < - 2 || n > 1 ) return NULL_RTX ; if ( n < 0 ) n = 2 + n ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : reg = SET_DEST ( PATTERN ( insn ) ) ; break ; case TYPE_STORE : reg = SET_SRC ( PATTERN ( insn ) ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( REG_P ( reg ) || GET_CODE ( reg ) == SUBREG ) ; switch ( GET_MODE ( reg ) ) { case E_DImode : mode = SImode ; break ; case E_DFmode : mode = SFmode ; break ; default : gcc_unreachable ( ) ; } if ( n == 0 ) return gen_lowpart ( mode , reg ) ; else return gen_highpart ( mode , reg ) ; } </s>

Returns the register operated by the nth load/store operation in the real micro-operation accessing order . This function assumes INSN must be a double-word load/store insn .


<s> static void arm_init_vfp_builtins ( void ) { unsigned int i , fcode = ARM_BUILTIN_VFP_PATTERN_START ; for ( i = 0 ; i < ARRAY_SIZE ( vfp_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & vfp_builtin_data [ i ] ; arm_init_builtin ( fcode , d , "__builtin_neon" ) ; } } </s>

Set up all the scalar floating point builtins .


<s> bool sh_cfun_trap_exit_p ( void ) { return lookup_attribute ( "trap_exit" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ; } </s>

Returns true if the current function has a `` trap_exit '' attribute set .


<s>
bool
ARMBlockPlacement
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
ST
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
DEBUG_PREFIX
<<
"Running on "
<<
MF
.
getName
(
)
<<
"\n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
MF
.
RenumberBlocks
(
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
RevertedWhileLoops
.
clear
(
)
;
for
(
auto
*
ML
:
*
MLI
)
Changed
|=
processPostOrderLoops
(
ML
)
;
for
(
auto
*
WlsInstr
:
RevertedWhileLoops
)
Changed
|=
revertWhileToDoLoop
(
WlsInstr
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"Running on "
"\n"
ARM
ARM
ARM


<s> inline void classify_registers ( const_tree , HOST_WIDE_INT bitpos , bool fp , classify_data_t * data ) { if ( fp ) { data -> fp_regs = true ; if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word = true ; } } </s>

A subroutine of function_arg_slotno . Classify the field .


<s> pure_scalable_type_info :: analysis_result pure_scalable_type_info :: analyze_record ( const_tree type ) { for ( tree field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( DECL_SIZE ( field ) && integer_zerop ( DECL_SIZE ( field ) ) ) continue ; pure_scalable_type_info field_info ; analysis_result subresult = field_info . analyze ( TREE_TYPE ( field ) ) ; if ( subresult == NO_ABI_IDENTITY ) continue ; if ( subresult != IS_PST ) return subresult ; tree bitpos = bit_position ( field ) ; gcc_assert ( poly_int_tree_p ( bitpos ) ) ; poly_widest_int wide_bytepos = exact_div ( wi :: to_poly_widest ( bitpos ) , BITS_PER_UNIT ) ; poly_uint64 bytepos ; if ( ! wide_bytepos . to_uhwi ( & bytepos ) || pieces . length ( ) + field_info . pieces . length ( ) > MAX_PIECES ) return DOESNT_MATTER ; gcc_assert ( ! field_info . pieces . is_empty ( ) ) ; for ( unsigned int i = 0 ; i < field_info . pieces . length ( ) ; ++ i ) { piece p = field_info . pieces [ i ] ; p . offset += bytepos ; add_piece ( p ) ; } } return pieces . is_empty ( ) ? NO_ABI_IDENTITY : IS_PST ; } </s>

Subroutine of analyze for handling RECORD_TYPEs .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BR_JT : return lowerBR_JT ( Op , DAG ) ; case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return lowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: ADD : return lowerADD ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BR_JT ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SELECT_CC ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::ADD ISD::FP_TO_SINT


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , 1 ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , MVT :: i32 ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , 0 ) ; OutOps . push_back ( NewOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void ix86_emit_i387_round ( rtx op0 , rtx op1 ) { machine_mode inmode = GET_MODE ( op1 ) ; machine_mode outmode = GET_MODE ( op0 ) ; rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx half = const_double_from_real_value ( dconsthalf , XFmode ) ; rtx res = gen_reg_rtx ( outmode ) ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx ( * floor_insn ) ( rtx , rtx ) ; rtx ( * neg_insn ) ( rtx , rtx ) ; rtx_insn * insn ; rtx tmp ; switch ( inmode ) { case E_SFmode : case E_DFmode : tmp = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_FLOAT_EXTEND ( XFmode , op1 ) ) ) ; op1 = tmp ; break ; case E_XFmode : break ; default : gcc_unreachable ( ) ; } switch ( outmode ) { case E_SFmode : floor_insn = gen_frndintxf2_floor ; neg_insn = gen_negsf2 ; break ; case E_DFmode : floor_insn = gen_frndintxf2_floor ; neg_insn = gen_negdf2 ; break ; case E_XFmode : floor_insn = gen_frndintxf2_floor ; neg_insn = gen_negxf2 ; break ; case E_HImode : floor_insn = gen_lfloorxfhi2 ; neg_insn = gen_neghi2 ; break ; case E_SImode : floor_insn = gen_lfloorxfsi2 ; neg_insn = gen_negsi2 ; break ; case E_DImode : floor_insn = gen_lfloorxfdi2 ; neg_insn = gen_negdi2 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e1 , op1 ) ) ; half = force_reg ( XFmode , half ) ; emit_insn ( gen_rtx_SET ( e2 , gen_rtx_PLUS ( XFmode , e1 , half ) ) ) ; switch ( outmode ) { case E_SFmode : case E_DFmode : { tmp = gen_reg_rtx ( XFmode ) ; emit_insn ( floor_insn ( tmp , e2 ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_UNSPEC ( outmode , gen_rtvec ( 1 , tmp ) , UNSPEC_TRUNC_NOOP ) ) ) ; } break ; default : emit_insn ( floor_insn ( res , e2 ) ) ; } emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( neg_insn ( res , res ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; emit_move_insn ( op0 , res ) ; } </s>


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


"unimplemented opcode in encodeInstruction()"

"Pseudo opcode found in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , Align Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> static int arm_first_cycle_multipass_dfa_lookahead ( void ) { int issue_rate = arm_issue_rate ( ) ; return issue_rate > 1 && ! sched_fusion ? issue_rate : 0 ; } </s>

Return how many instructions should scheduler lookahead to choose the best one .


<s> void SystemZPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createPartiallyInlineLibCallsPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void ix86_expand_reduc_v4sf ( rtx ( * fn ) ( rtx , rtx , rtx ) , rtx dest , rtx in ) { rtx tmp1 , tmp2 , tmp3 ; tmp1 = gen_reg_rtx ( V4SFmode ) ; tmp2 = gen_reg_rtx ( V4SFmode ) ; tmp3 = gen_reg_rtx ( V4SFmode ) ; emit_insn ( gen_sse_movhlps ( tmp1 , in , in ) ) ; emit_insn ( fn ( tmp2 , tmp1 , in ) ) ; emit_insn ( gen_sse_shufps_1 ( tmp3 , tmp2 , tmp2 , GEN_INT ( 1 ) , GEN_INT ( 1 ) , GEN_INT ( 1 + 4 ) , GEN_INT ( 1 + 4 ) ) ) ; emit_insn ( fn ( dest , tmp2 , tmp3 ) ) ; } </s>

Expand a vector reduction on V4SFmode for SSE1 . FN is the binary pattern to reduce ; DEST is the destination ; IN is the input vector .


<s> void CSKYPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>


<s> static enum attr_type mt_get_attr_type ( rtx complete_insn ) { rtx insn = PATTERN ( complete_insn ) ; if ( JUMP_P ( complete_insn ) ) return TYPE_BRANCH ; if ( CALL_P ( complete_insn ) ) return TYPE_BRANCH ; if ( GET_CODE ( insn ) != SET ) return TYPE_ARITH ; if ( SET_DEST ( insn ) == pc_rtx ) return TYPE_BRANCH ; if ( GET_CODE ( SET_DEST ( insn ) ) == MEM ) return TYPE_STORE ; if ( GET_CODE ( SET_SRC ( insn ) ) == MEM ) return TYPE_LOAD ; return TYPE_ARITH ; } </s>

Given an insn , return whether it 's a memory operation or a branch operation , otherwise return TYPE_ARITH .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 cmov Conversion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlignment ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> static bool zero_all_mm_registers ( HARD_REG_SET need_zeroed_hardregs , unsigned int ret_mmx_regno ) { bool need_zero_all_mm = false ; for ( unsigned int regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( STACK_REGNO_P ( regno ) && TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { need_zero_all_mm = true ; break ; } if ( ! need_zero_all_mm ) return false ; machine_mode mode = V2SImode ; for ( unsigned int regno = FIRST_MMX_REG ; regno <= LAST_MMX_REG ; regno ++ ) if ( regno != ret_mmx_regno ) { rtx reg = gen_rtx_REG ( mode , regno ) ; emit_insn ( gen_rtx_SET ( reg , CONST0_RTX ( mode ) ) ) ; } return true ; } </s>

When the routine exit in MMX mode , if any ST register needs to be zeroed , we should clear all MMX registers except the RET_MMX_REGNO that holds the return value .


<s> void AArch64PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AssertZext : return performAssertZextCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::AssertZext ISD::SHL


<s> EVT X86TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget -> hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; const unsigned NumElts = VT . getVectorNumElements ( ) ; const EVT EltVT = VT . getVectorElementType ( ) ; if ( VT . is512BitVector ( ) ) { if ( Subtarget -> hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget -> hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( VT . is256BitVector ( ) || VT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } if ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; case 32 : return MVT :: v32i1 ; } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static tree add_attribute ( const char * name , tree attrs ) { return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ; } </s>


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool isTarget64BitLP64 ( ) const { if ( NaClDontBreakABI ) { return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 ) ; } return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 && ! TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


<s> void DLXFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const DLXRegisterInfo * LRI = static_cast < const DLXRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; int Offset = - 4 ; MFI . CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; MFI . CreateFixedObject ( 4 , Offset , true ) ; Offset -= 4 ; if ( LRI -> hasBasePointer ( MF ) ) { MFI . CreateFixedObject ( 4 , Offset , true ) ; SavedRegs . reset ( LRI -> getBaseRegister ( ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getLoadRegOpcode ( RC , isAligned ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void ix86_expand_lfloorceil ( rtx op0 , rtx op1 , bool do_floor ) { machine_mode fmode = GET_MODE ( op1 ) ; machine_mode imode = GET_MODE ( op0 ) ; rtx ireg , freg , tmp ; rtx_code_label * label ; ireg = gen_reg_rtx ( imode ) ; expand_fix ( ireg , op1 , 0 ) ; freg = gen_reg_rtx ( fmode ) ; expand_float ( freg , ireg , 0 ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , freg , op1 , ! do_floor ) ; tmp = expand_simple_binop ( imode , do_floor ? MINUS : PLUS , ireg , const1_rtx , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( ireg , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( op0 , ireg ) ; } </s>

Expand SSE2 sequence for computing lround from OPERAND1 storing into OPERAND0 .


<s> static void aarch64_record_vector_load_arg ( tree addr ) { tree decl = aarch64_vector_load_decl ( addr ) ; if ( ! decl ) return ; if ( ! cfun -> machine -> vector_load_decls ) cfun -> machine -> vector_load_decls = hash_set < tree > :: create_ggc ( 31 ) ; cfun -> machine -> vector_load_decls -> add ( decl ) ; } </s>

We 've seen a vector load from address ADDR . Record it in vector_load_decls , if appropriate .


<s> void SystemZAsmPrinter :: emitFunctionBodyEnd ( ) { if ( TM . getTargetTriple ( ) . isOSzOS ( ) ) { MCSymbol * FnEndSym = createTempSymbol ( "func_end" ) ; OutStreamer -> emitLabel ( FnEndSym ) ; OutStreamer -> PushSection ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getPPA1Section ( ) ) ; emitPPA1 ( FnEndSym ) ; OutStreamer -> PopSection ( ) ; CurrentFnPPA1Sym = nullptr ; CurrentFnEPMarkerSym = nullptr ; } } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! EnableARMTailCalls && ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; return ! Subtarget -> isThumb1Only ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED , rtx pic_reg ) { rtx l1 , labelno , pic_tmp , pic_rtx ; if ( crtl -> uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; pic_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; pic_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pic_rtx ) , UNSPEC_GOTSYM_OFF ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; if ( TARGET_32BIT ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } else { if ( arm_pic_register != INVALID_REGNUM && REGNO ( pic_reg ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb1 ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_reg , pic_reg , labelno ) ) ; } else if ( arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && REGNO ( pic_reg ) <= LAST_LO_REGNUM ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; emit_move_insn ( gen_rtx_REG ( Pmode , arm_pic_register ) , pic_reg ) ; emit_use ( gen_rtx_REG ( Pmode , arm_pic_register ) ) ; } else emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } } emit_use ( pic_reg ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


<s> SDValue PPCTargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasQPX ( ) ) || ( VT == MVT :: v4f64 && Subtarget . hasQPX ( ) ) ) { TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; std :: string RecipOp = getRecipOp ( "div" , VT ) ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; return DCI . DAG . getNode ( PPCISD :: FRE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Cpu0 Del Useless jmp"
;
}
</s>


<s> static void rs6000_function_specific_save ( struct cl_target_option * ptr , struct gcc_options * opts , struct gcc_options * ) { ptr -> x_rs6000_isa_flags = opts -> x_rs6000_isa_flags ; ptr -> x_rs6000_isa_flags_explicit = opts -> x_rs6000_isa_flags_explicit ; } </s>


<s> TargetPassConfig * CAHPTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new CAHPPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
&&
MIa
->
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
&&
MIb
->
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> Register getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static rtx function_arg_union_value ( int size , enum machine_mode mode , int slotno , int regno ) { int nwords = ROUND_ADVANCE ( size ) , i ; rtx regs ; if ( nwords == 0 ) return gen_rtx_REG ( mode , regno ) ; if ( slotno == SPARC_INT_ARG_MAX - 1 ) nwords = 1 ; regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( i = 0 ; i < nwords ; i ++ ) { XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , GEN_INT ( UNITS_PER_WORD * i ) ) ; regno ++ ; } return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions of the 64-bit ABI for passing and returning unions . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the union . MODE is the argument 's machine mode . REGNO is the hard register the union will be passed in .


"alias without a base object is not yet supported on AIX"

Set up the AsmPrinter when we are working on a new module .


<s>
const
char
*
output_fp_compare
(
rtx
insn
,
rtx
*
operands
,
bool
eflags_p
,
bool
unordered_p
)
{
int
stack_top_dies
;
rtx
cmp_op0
,
cmp_op1
;
int
is_sse
=
SSE_REG_P
(
operands
[
0
]
)
||
SSE_REG_P
(
operands
[
1
]
)
;
if
(
eflags_p
)
{
cmp_op0
=
operands
[
0
]
;
cmp_op1
=
operands
[
1
]
;
}
else
{
cmp_op0
=
operands
[
1
]
;
cmp_op1
=
operands
[
2
]
;
}
if
(
is_sse
)
{
if
(
GET_MODE
(
operands
[
0
]
)
==
SFmode
)
if
(
unordered_p
)
return
"%vucomiss\t{%1, %0|%0, %1}"
;
else
return
"%vcomiss\t{%1, %0|%0, %1}"
;
else
if
(
unordered_p
)
return
"%vucomisd\t{%1, %0|%0, %1}"
;
else
return
"%vcomisd\t{%1, %0|%0, %1}"
;
}
gcc_assert
(
STACK_TOP_P
(
cmp_op0
)
)
;
stack_top_dies
=
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
)
!=
0
;
if
(
cmp_op1
==
CONST0_RTX
(
GET_MODE
(
cmp_op1
)
)
)
{
if
(
stack_top_dies
)
{
output_asm_insn
(
"ftst\n\tfnstsw\t%0"
,
operands
)
;
return
output_387_ffreep
(
operands
,
1
)
;
}
else
return
"ftst\n\tfnstsw\t%0"
;
}
if
(
STACK_REG_P
(
cmp_op1
)
&&
stack_top_dies
&&
find_regno_note
(
insn
,
REG_DEAD
,
REGNO
(
cmp_op1
)
)
&&
REGNO
(
cmp_op1
)
!=
FIRST_STACK_REG
)
{
if
(
eflags_p
)
{
if
(
unordered_p
)
output_asm_insn
(
"fucomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
else
output_asm_insn
(
"fcomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
return
output_387_ffreep
(
operands
,
0
)
;
}
else
{
if
(
unordered_p
)
return
"fucompp\n\tfnstsw\t%0"
;
else
return
"fcompp\n\tfnstsw\t%0"
;
}
}
else
{
static
const
char
*
const
alt
[
16
]
=
{
"fcom%Z2\t%y2\n\tfnstsw\t%0"
,
"fcomp%Z2\t%y2\n\tfnstsw\t%0"
,
"fucom%Z2\t%y2\n\tfnstsw\t%0"
,
"fucomp%Z2\t%y2\n\tfnstsw\t%0"
,
"ficom%Z2\t%y2\n\tfnstsw\t%0"
,
"ficomp%Z2\t%y2\n\tfnstsw\t%0"
,
,
,
"fcomi\t{%y1, %0|%0, %y1}"
,
"fcomip\t{%y1, %0|%0, %y1}"
,
"fucomi\t{%y1, %0|%0, %y1}"
,
"fucomip\t{%y1, %0|%0, %y1}"
,
,
,
,
}
;
int
mask
;
const
char
*
ret
;
mask
=
eflags_p
<<
3
;
mask
|=
(
GET_MODE_CLASS
(
GET_MODE
(
cmp_op1
)
)
==
MODE_INT
)
<<
2
;
mask
|=
unordered_p
<<
1
;
mask
|=
stack_top_dies
;
gcc_assert
(
mask
<
16
)
;
ret
=
alt
[
mask
]
;
gcc_assert
(
ret
)
;
return
ret
;
}
}
</s>

Output code for INSN to compare OPERANDS . EFLAGS_P is 1 when fcomi should be used and 2 when fnstsw should be used . UNORDERED_P is true when fucom should be used .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( EVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? ( const TargetRegisterClass * ) & X86 :: GR64RegClass : ( const TargetRegisterClass * ) & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static inline CSKYTargetStreamer :: SymbolIndex getTombstoneKey ( ) { return { nullptr , CSKYMCExpr :: VK_CSKY_Invalid } ; } </s>

Difference in tombstone is that the Optional is meaningful .


<s> void ARMDAGToDAGISel :: PreprocessISelDAG ( ) { if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SDNode & N : llvm :: make_early_inc_range ( CurDAG -> allnodes ( ) ) ) { if ( N . getOpcode ( ) != ISD :: ADD ) continue ; SDValue N0 = N . getOperand ( 0 ) ; SDValue N1 = N . getOperand ( 1 ) ; unsigned And_imm = 0 ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , ISD :: AND , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , ISD :: AND , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != 1 && TZ != 2 ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + 1 ) ) continue ; SDValue Srl = N1 . getOperand ( 0 ) ; unsigned Srl_imm = 0 ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , ISD :: SRL , Srl_imm ) || ( Srl_imm <= 2 ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( ISD :: SRL , SDLoc ( Srl ) , MVT :: i32 , Srl . getOperand ( 0 ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: AND , SDLoc ( N1 ) , MVT :: i32 , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , MVT :: i32 ) ) ; N1 = CurDAG -> getNode ( ISD :: SHL , SDLoc ( N1 ) , MVT :: i32 , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , MVT :: i32 ) ) ; CurDAG -> UpdateNodeOperands ( & N , N0 , N1 ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
void
PPCInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLWINM
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
MB
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
bool
useSubstituteMnemonic
=
false
;
if
(
SH
<=
31
&&
MB
==
0
&&
ME
==
(
31
SH
)
)
{
O
<<
"\tslwi "
;
useSubstituteMnemonic
=
true
;
}
if
(
SH
<=
31
&&
MB
==
(
32
SH
)
&&
ME
==
31
)
{
O
<<
"\tsrwi "
;
useSubstituteMnemonic
=
true
;
SH
=
32
SH
;
}
if
(
useSubstituteMnemonic
)
{
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
}
if
(
(
MI
->
getOpcode
(
)
==
PPC
::
OR
||
MI
->
getOpcode
(
)
==
PPC
::
OR8
)
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
O
<<
"\tmr "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLDICR
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
63
SH
==
ME
)
{
O
<<
"\tsldi "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
}
if
(
MI
->
getOpcode
(
)
==
TargetOpcode
::
COPY_TO_REGCLASS
)
return
;
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void AArch64PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool sh_symbian_dllexport_name_p ( const char * symbol ) { return strncmp ( DLL_EXPORT_PREFIX , symbol , strlen ( DLL_EXPORT_PREFIX ) ) == 0 ; } </s>

Return nonzero if SYMBOL is marked as being dllexport 'd .


<s> rtx pru_get_return_address ( int count ) { if ( count != 0 ) return NULL_RTX ; return get_hard_reg_initial_val ( HImode , RA_REGNUM ) ; } </s>

Implement RETURN_ADDR_RTX . Note , we do not support moving back to a previous frame .


<s> int aarch_accumulator_forwarding ( rtx_insn * producer , rtx_insn * consumer ) { rtx producer_set = single_set ( producer ) ; rtx consumer_set = single_set ( consumer ) ; if ( ! producer_set || ! consumer_set ) return 0 ; rtx dest = SET_DEST ( producer_set ) ; rtx mla = SET_SRC ( consumer_set ) ; if ( ! REG_P ( dest ) ) return 0 ; rtx accumulator ; if ( GET_CODE ( mla ) == ZERO_EXTEND ) mla = XEXP ( mla , 0 ) ; switch ( GET_CODE ( mla ) ) { case PLUS : if ( GET_CODE ( XEXP ( mla , 0 ) ) == MULT ) accumulator = XEXP ( mla , 1 ) ; else return 0 ; break ; case MINUS : if ( GET_CODE ( XEXP ( mla , 1 ) ) == MULT ) accumulator = XEXP ( mla , 0 ) ; else return 0 ; break ; case FMA : { if ( REG_P ( XEXP ( mla , 1 ) ) && REG_P ( XEXP ( mla , 2 ) ) && ( REG_P ( XEXP ( mla , 0 ) ) || GET_CODE ( XEXP ( mla , 0 ) ) == NEG ) ) { accumulator = XEXP ( mla , 2 ) ; } else if ( REG_P ( XEXP ( mla , 1 ) ) && GET_CODE ( XEXP ( mla , 2 ) ) == NEG && ( REG_P ( XEXP ( mla , 0 ) ) || GET_CODE ( XEXP ( mla , 0 ) ) == NEG ) ) { accumulator = XEXP ( XEXP ( mla , 2 ) , 0 ) ; } else return 0 ; break ; } default : return 0 ; } if ( SUBREG_P ( accumulator ) ) accumulator = SUBREG_REG ( accumulator ) ; if ( ! REG_P ( accumulator ) ) return 0 ; return ( REGNO ( dest ) == REGNO ( accumulator ) ) ; } </s>

Return non-zero if the destination of PRODUCER feeds the accumulator operand of an MLA-like operation .


<s> bool OR1KAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> void OR1KInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>


<s>
static
char
*
match_integer
(
void
)
{
int
startpos
=
pos
;
if
(
linebuf
[
pos
]
==
'-'
)
safe_inc_pos
(
)
;
int
lastpos
=
pos
1
;
while
(
lastpos
<
LINELEN
1
&&
isdigit
(
linebuf
[
lastpos
+
1
]
)
)
++
lastpos
;
if
(
lastpos
>=
LINELEN
1
)
{
diag
(
lastpos
,
"line length overrun.\n"
)
;
exit
(
1
)
;
}
if
(
lastpos
<
pos
)
return
;
pos
=
lastpos
+
1
;
char
*
buf
=
(
char
*
)
malloc
(
lastpos
startpos
+
2
)
;
memcpy
(
buf
,
&
linebuf
[
startpos
]
,
lastpos
startpos
+
1
)
;
buf
[
lastpos
startpos
+
1
]
=
'\0'
;
return
buf
;
}
</s>

Match an integer and return the string representing its value , or a null string on failure .


<s> static std :: unique_ptr < OR1KOperand > CreateMem ( unsigned BaseNum , const MCExpr * Off , SMLoc S , SMLoc E ) { auto Op = make_unique < OR1KOperand > ( k_Memory ) ; Op -> Mem . BaseNum = BaseNum ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> unsigned int call_properties ( const function_instance & ) const override { return CP_WRITE_MEMORY ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


"without AVX512F enabled changes the ABI"

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


<s> void PPCInstrInfo :: genAlternativeCodeSequence ( MachineInstr & Root , MachineCombinerPattern Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr * > & DelInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg ) const { switch ( Pattern ) { case MachineCombinerPattern :: REASSOC_XY_AMM_BMM : case MachineCombinerPattern :: REASSOC_XMM_AMM_BMM : reassociateFMA ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; default : TargetInstrInfo :: genAlternativeCodeSequence ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; } } </s>

When getMachineCombinerPatterns ( ) finds potential patterns , this function generates the instructions that could replace the original code sequence .


<s> rtx gen_df_reg ( rtx reg , int low ) { int regno = REGNO ( reg ) ; if ( ( WORDS_BIG_ENDIAN == 0 ) ^ ( low != 0 ) ) regno += ( TARGET_ARCH64 && SPARC_INT_REG_P ( regno ) ) ? 1 : 2 ; return gen_rtx_REG ( DFmode , regno ) ; } </s>

Generate a DFmode part of a hard TFmode register . REG is the TFmode hard register , LOW is 1 for the low 64bit of the register and 0 otherwise .


<s>
bool
X86LoadValueInjectionRetHardeningPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"***** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
" *****\n"
)
;
const
X86Subtarget
*
Subtarget
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
Subtarget
->
useLVIControlFlowIntegrity
(
)
||
!
Subtarget
->
is64Bit
(
)
)
return
false
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
if
(
!
F
.
hasOptNone
(
)
&&
skipFunction
(
F
)
)
return
false
;
++
NumFunctionsConsidered
;
const
X86RegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
X86InstrInfo
*
TII
=
Subtarget
->
getInstrInfo
(
)
;
bool
Modified
=
false
;
for
(
auto
&
MBB
:
MF
)
{
for
(
auto
MBBI
=
MBB
.
begin
(
)
;
MBBI
!=
MBB
.
end
(
)
;
++
MBBI
)
{
if
(
MBBI
->
getOpcode
(
)
!=
X86
::
RET64
)
continue
;
unsigned
ClobberReg
=
TRI
->
findDeadCallerSavedReg
(
MBB
,
MBBI
)
;
if
(
ClobberReg
!=
X86
::
NoRegister
)
{
BuildMI
(
MBB
,
MBBI
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
POP64r
)
)
.
addReg
(
ClobberReg
,
RegState
::
Define
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
BuildMI
(
MBB
,
MBBI
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
LFENCE
)
)
;
BuildMI
(
MBB
,
MBBI
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
JMP64r
)
)
.
addReg
(
ClobberReg
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
MachineInstr
*
Fence
=
BuildMI
(
MBB
,
MBBI
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
LFENCE
)
)
;
addRegOffset
(
BuildMI
(
MBB
,
Fence
,
DebugLoc
(
)
,
TII
->
get
(
X86
::
SHL64mi
)
)
,
X86
::
RSP
,
false
,
0
)
.
addImm
(
0
)
->
addRegisterDead
(
X86
::
EFLAGS
,
TRI
)
;
}
++
NumFences
;
Modified
=
true
;
break
;
}
}
if
(
Modified
)
++
NumFunctionsMitigated
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; NumBytes += 92 ; NumBytes = ( NumBytes + 7 ) & ~ 7 ; NumBytes = - NumBytes ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { X86MachineFunctionInfo * MFI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> void OutgoingValueHandler :: assignValueToReg ( unsigned ValVReg , unsigned PhysReg ) { MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static tree ix86_md_asm_clobbers ( tree outputs ATTRIBUTE_UNUSED , tree inputs ATTRIBUTE_UNUSED , tree clobbers ) { clobbers = tree_cons ( NULL_TREE , build_string ( 5 , "flags" ) , clobbers ) ; clobbers = tree_cons ( NULL_TREE , build_string ( 4 , "fpsr" ) , clobbers ) ; clobbers = tree_cons ( NULL_TREE , build_string ( 7 , "dirflag" ) , clobbers ) ; return clobbers ; } </s>

Worker function for TARGET_MD_ASM_CLOBBERS . We do this in the new i386 backend to maintain source compatibility with the old cc0-based compiler .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return NumRegisters ; } if ( VT == MVT :: v3f16 && Subtarget . hasFP16 ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> MCELFStreamer & Comet2TargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> static void loongarch_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( ( TARGET_64BIT && ( first + size <= 32768 ) ) || ( ! TARGET_64BIT && ( first + size <= 2048 ) ) ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r13 = LARCH_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = LARCH_PROLOGUE_TEMP2 ( Pmode ) ; rtx r14 = LARCH_PROLOGUE_TEMP3 ( Pmode ) ; gcc_assert ( first <= 16384 ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; if ( first != 0 ) { emit_move_insn ( r14 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( r13 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; } else emit_move_insn ( r13 , stack_pointer_rtx ) ; emit_move_insn ( r14 , GEN_INT ( PROBE_INTERVAL ) ) ; if ( rounded_size == 0 ) emit_move_insn ( r12 , r13 ) ; else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , r13 , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , r13 , r13 , r12 , r14 ) ) ; } if ( size != rounded_size ) { if ( TARGET_64BIT ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; else { HOST_WIDE_INT i ; for ( i = 2048 ; i < ( size - rounded_size ) ; i += 2048 ) { emit_stack_probe ( plus_constant ( Pmode , r12 , - i ) ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , r12 , - 2048 ) ) ) ; } rtx r1 = plus_constant ( Pmode , r12 , - ( size - rounded_size - i + 2048 ) ) ; emit_stack_probe ( r1 ) ; } } } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 || ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( const SDNode * U : Copy -> uses ( ) ) { if ( U -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; if ( U -> getNumOperands ( ) > 4 ) return false ; if ( U -> getNumOperands ( ) == 4 && U -> getOperand ( U -> getNumOperands ( ) - 1 ) . getValueType ( ) != MVT :: Glue ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> rtx arm_function_value ( tree type , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode ; int unsignedp ATTRIBUTE_UNUSED ; rtx r ATTRIBUTE_UNUSED ; mode = TYPE_MODE ( type ) ; if ( INTEGRAL_TYPE_P ( type ) ) PROMOTE_FUNCTION_MODE ( mode , unsignedp , type ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } } return LIBCALL_VALUE ( mode ) ; } </s>

Define how to find the value returned by a function .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MMI
=
&
getAnalysis
<
MachineModuleInfo
>
(
)
;
MCE
.
setModuleInfo
(
MMI
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
MCInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
++
NumEmitted
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>


<s> rtx extract_nth_lmsw_access_reg ( rtx_insn * insn , int n ) { rtx nth_rtx = extract_nth_access_rtx ( insn , n ) ; if ( nth_rtx == NULL_RTX ) return NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : return SET_DEST ( nth_rtx ) ; case TYPE_STORE_MULTIPLE : return SET_SRC ( nth_rtx ) ; default : gcc_unreachable ( ) ; } } </s>

Returns the register operated by the nth load/store operation in the real micro-operation accessing order . This function assumes INSN must be a multiple-word load/store insn .


<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const X86RegisterInfo * RegInfo = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) FrameReg = RegInfo -> getStackRegister ( ) ; else FrameReg = RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createX86IndirectBranchTrackingPass ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } addPass ( createX86DiscriminateMemOpsPass ( ) ) ; addPass ( createX86InsertPrefetchPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void X86RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { unsigned Opc = getSUBriOpcode ( Is64Bit , CalleeAmt ) ; MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool pa_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { bool result ; tree decl = NULL ; if ( GET_CODE ( x ) == SYMBOL_REF ) { decl = SYMBOL_REF_DECL ( x ) ; if ( decl ) { assemble_external ( decl ) ; SET_SYMBOL_REF_DECL ( x , NULL ) ; } } if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == 8 ? "\t.dword\t" : "\t.word\t" , asm_out_file ) ; if ( ! TARGET_FAST_INDIRECT_CALLS ) fputs ( "P%" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; result = true ; } else result = default_assemble_integer ( x , size , aligned_p ) ; if ( decl ) SET_SYMBOL_REF_DECL ( x , decl ) ; return result ; } </s>

Target hook for assembling integer objects . This code handles aligned SI and DI integers specially , since function references must be preceded by P % .


<s>
MCSymbol
*
X86MCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
switch
(
MO
.
getTargetFlags
(
)
)
{
case
X86II
::
MO_DLLIMPORT
:
Name
+=
"__imp_"
;
break
;
case
X86II
::
MO_COFFSTUB
:
Name
+=
".refptr."
;
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
Suffix
=
"$non_lazy_ptr"
;
break
;
}
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
break
;
case
X86II
::
MO_COFFSTUB
:
{
MachineModuleInfoCOFF
&
MMICOFF
=
MF
.
getMMI
(
)
.
getObjFileInfo
<
MachineModuleInfoCOFF
>
(
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MMICOFF
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
true
)
;
}
break
;
}
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
)
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
break
;
}
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> inline static rtx emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( VOIDmode , x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> const uint32_t * CSKYRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const CSKYSubtarget & STI = MF . getSubtarget < CSKYSubtarget > ( ) ; return CSR_I32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned getNumFixupKinds ( ) const { return Sparc :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned RA = ABI . IsN64 ( ) ? Mips :: RA_64 : Mips :: RA ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) { setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( MF ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( MF ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? 10 : 16 , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
ARMBaseTargetMachine
::
ARMBaseTargetMachine
(
const
Target
&
T
,
const
Triple
&
TT
,
StringRef
CPU
,
StringRef
FS
,
const
TargetOptions
&
Options
,
Optional
<
Reloc
::
Model
>
RM
,
CodeModel
::
Model
CM
,
CodeGenOpt
::
Level
OL
,
bool
isLittle
)
:
LLVMTargetMachine
(
T
,
computeDataLayout
(
TT
,
CPU
,
Options
,
isLittle
)
,
TT
,
CPU
,
FS
,
Options
,
getEffectiveRelocModel
(
TT
,
RM
)
,
CM
,
OL
)
,
TargetABI
(
computeTargetABI
(
TT
,
CPU
,
Options
)
)
,
TLOF
(
createTLOF
(
getTargetTriple
(
)
)
)
,
Subtarget
(
TT
,
CPU
,
FS
,
*
this
,
isLittle
)
,
isLittle
(
isLittle
)
{
if
(
Options
.
FloatABIType
==
FloatABI
::
Default
)
this
->
Options
.
FloatABIType
=
Subtarget
.
isTargetHardFloat
(
)
FloatABI
::
Hard
:
FloatABI
::
Soft
;
if
(
Options
.
EABIVersion
==
EABI
::
Default
||
Options
.
EABIVersion
==
EABI
::
Unknown
)
{
if
(
Subtarget
.
isTargetGNUAEABI
(
)
||
Subtarget
.
isTargetMuslAEABI
(
)
)
this
->
Options
.
EABIVersion
=
EABI
::
GNU
;
else
this
->
Options
.
EABIVersion
=
EABI
::
EABI5
;
}
initAsmInfo
(
)
;
if
(
!
Subtarget
.
isThumb
(
)
&&
!
Subtarget
.
hasARMOps
(
)
)
report_fatal_error
(
"CPU: '"
+
Subtarget
.
getCPUString
(
)
+
"' does not "
"support ARM mode execution!"
)
;
}
</s>

ARM
ARM
ARM
ARM
"CPU: '"
"' does not "
"support ARM mode execution!"


<s> static tree associated_type ( tree decl ) { return ( DECL_CONTEXT ( decl ) && TYPE_P ( DECL_CONTEXT ( decl ) ) ) ? DECL_CONTEXT ( decl ) : NULL_TREE ; } </s>

Return the type that we should use to determine if DECL is imported or exported .


<s> void TOYAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool AArch64TargetLowering :: isExtFreeImpl ( const Instruction * Ext ) const { if ( isa < FPExtInst > ( Ext ) ) return false ; if ( Ext -> getType ( ) -> isVectorTy ( ) ) return false ; for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( 1 ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; auto & DL = Ext -> getModule ( ) -> getDataLayout ( ) ; std :: advance ( GTI , U . getOperandNo ( ) - 1 ) ; Type * IdxTy = GTI . getIndexedType ( ) ; uint64_t ShiftAmt = countTrailingZeros ( DL . getTypeStoreSizeInBits ( IdxTy ) . getFixedSize ( ) ) - 3 ; if ( ShiftAmt == 0 || ShiftAmt > 4 ) return false ; break ; } case Instruction :: Trunc : if ( Instr -> getType ( ) == Ext -> getOperand ( 0 ) -> getType ( ) ) continue ; LLVM_FALLTHROUGH ; default : return false ; } } return true ; } </s>

Return true if the extension represented by I is free .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> int arm_no_early_store_addr_dep ( rtx producer , rtx consumer ) { rtx value = PATTERN ( producer ) ; rtx addr = PATTERN ( consumer ) ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , 0 , 0 ) ; value = XEXP ( value , 0 ) ; if ( GET_CODE ( addr ) == COND_EXEC ) addr = COND_EXEC_CODE ( addr ) ; if ( GET_CODE ( addr ) == PARALLEL ) addr = XVECEXP ( addr , 0 , 0 ) ; addr = XEXP ( addr , 0 ) ; return ! reg_overlap_mentioned_p ( value , addr ) ; } </s>

Return nonzero if the CONSUMER instruction ( a store ) does not need PRODUCER 's value to calculate the address .


<s> int expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; bool constp = CONST_INT_P ( bytes_rtx ) ; HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return 0 ; gcc_assert ( CONST_INT_P ( align_rtx ) ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return 1 ; if ( TARGET_ALTIVEC && ( align >= 128 || TARGET_EFFICIENT_UNALIGNED_VSX ) ) clear_step = 16 ; else if ( TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) clear_step = 8 ; else clear_step = 4 ; if ( optimize_size && bytes > 3 * clear_step ) return 0 ; if ( ! optimize_size && bytes > 8 * clear_step ) return 0 ; bool unaligned_vsx_ok = ( bytes >= 32 && TARGET_EFFICIENT_UNALIGNED_VSX ) ; for ( offset = 0 ; bytes > 0 ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( TARGET_ALTIVEC && ( bytes >= 16 && ( align >= 128 || unaligned_vsx_ok ) ) ) { clear_bytes = 16 ; mode = V4SImode ; } else if ( bytes >= 8 && TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 8 ; mode = DImode ; if ( offset == 0 && align < 64 ) { rtx addr ; addr = XEXP ( orig_dest , 0 ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , 1 ) ) && ( INTVAL ( XEXP ( addr , 1 ) ) & 3 ) != 0 ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= 4 && ( align >= 32 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 4 ; mode = SImode ; } else if ( bytes >= 2 && ( align >= 16 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 2 ; mode = HImode ; } else { clear_bytes = 1 ; mode = QImode ; } dest = adjust_address ( orig_dest , mode , offset ) ; emit_move_insn ( dest , CONST0_RTX ( mode ) ) ; } return 1 ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> int ARMAsmParser :: tryParseRegister ( ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r13" , ARM :: SP ) . Case ( "r14" , ARM :: LR ) . Case ( "r15" , ARM :: PC ) . Case ( "ip" , ARM :: R12 ) . Case ( "a1" , ARM :: R0 ) . Case ( "a2" , ARM :: R1 ) . Case ( "a3" , ARM :: R2 ) . Case ( "a4" , ARM :: R3 ) . Case ( "v1" , ARM :: R4 ) . Case ( "v2" , ARM :: R5 ) . Case ( "v3" , ARM :: R6 ) . Case ( "v4" , ARM :: R7 ) . Case ( "v5" , ARM :: R8 ) . Case ( "v6" , ARM :: R9 ) . Case ( "v7" , ARM :: R10 ) . Case ( "v8" , ARM :: R11 ) . Case ( "sb" , ARM :: R9 ) . Case ( "sl" , ARM :: R10 ) . Case ( "fp" , ARM :: R11 ) . Default ( 0 ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - 1 ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; } if ( ! hasD32 ( ) && RegNum >= ARM :: D16 && RegNum <= ARM :: D31 ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> bool ix86_expand_fp_vcond ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; rtx cmp ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & operands [ 4 ] , & operands [ 5 ] ) ; if ( code == UNKNOWN ) return false ; if ( ix86_expand_sse_fp_minmax ( operands [ 0 ] , code , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ) return true ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , operands [ 4 ] , operands [ 5 ] , operands [ 1 ] , operands [ 2 ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , cmp , operands [ 1 ] , operands [ 2 ] ) ; return true ; } </s>

Expand a floating-point vector conditional move ; a vcond operation rather than a movcc operation .


";; sched_reorder for cycle %d with %d insns in ready list\n"

";; sched_reorder nothing to reorder as no younger\n"

";; sched_reorder nothing to reorder as no older_only\n"

";; cortexa7_sched_reorder insn %d before %d\n"

Look for an instruction that can dual issue only as an older instruction , and move it in front of any instructions that can dual-issue as younger , while preserving the relative order of all other instructions in the ready list . This is a hueuristic to help dual-issue in later cycles , by postponing issue of more flexible instructions . This heuristic may affect dual issue opportunities in the current cycle .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && ( STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) ) { MCInst Data32MI ( * MI ) ; Data32MI . setOpcode ( X86 :: DATA32_PREFIX ) ; printInstruction ( & Data32MI , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> rtl_opt_pass * make_pass_fma_steering ( gcc :: context * ctxt ) { return new pass_fma_steering ( ctxt ) ; } </s>

Create a new fma steering pass instance .


<s> void mips_expand_vector_init ( rtx target , rtx vals ) { machine_mode vmode = GET_MODE ( target ) ; machine_mode imode = GET_MODE_INNER ( vmode ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; unsigned nvar = 0 , one_var = - 1u ; bool all_same = true ; rtx x ; for ( i = 0 ; i < nelt ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! mips_constant_elt_p ( x ) ) nvar ++ , one_var = i ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( nvar == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , XVEC ( vals , 0 ) ) ) ; return ; } if ( nelt == 2 ) { rtx op0 = force_reg ( imode , XVECEXP ( vals , 0 , 0 ) ) ; rtx op1 = force_reg ( imode , XVECEXP ( vals , 0 , 1 ) ) ; x = gen_rtx_VEC_CONCAT ( vmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return ; } gcc_assert ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ; if ( all_same ) { mips_expand_vi_broadcast ( vmode , target , XVECEXP ( vals , 0 , 0 ) ) ; return ; } if ( nvar == 1 && vmode == V4HImode ) { mips_expand_vi_loongson_one_pinsrh ( target , vals , one_var ) ; return ; } mips_expand_vi_general ( vmode , imode , nelt , nvar , target , vals ) ; } </s>


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Cond
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
getCMovFromCond
(
(
X86
::
CondCode
)
Cond
[
0
]
.
getImm
(
)
,
MRI
.
getRegClass
(
DstReg
)
->
getSize
(
)
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & FS , bool isT ) : ARMArchVersion ( V4 ) , ARMFPUType ( None ) , UseNEONForSinglePrecisionFP ( UseNEONFP ) , IsThumb ( isT ) , ThumbMode ( Thumb1 ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( UseMOVT ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; if ( CPUString == "generic" && ( FS . empty ( ) || FS == "generic" ) ) ARMArchVersion = V4T ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 5 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { ARMArchVersion = V7A ; } else if ( SubVer == '6' ) { ARMArchVersion = V6 ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == '2' ) ARMArchVersion = V6T2 ; } else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + 2 && TT [ Idx + 1 ] == 't' ) ARMArchVersion = V4T ; else ARMArchVersion = V4 ; } } if ( ARMArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) ARMArchVersion = V6T2 ; if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( ARMArchVersion < V6 ) ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( CPUString == "cortex-a8" ) { if ( UseNEONFP . getPosition ( ) == 0 ) UseNEONForSinglePrecisionFP = true ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Kind
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsResolved
,
Ctx
,
STI
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
Endian
==
support
::
big
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Kind
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
Endian
==
support
::
little
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool mips_in_small_data_p ( tree decl ) { HOST_WIDE_INT size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TARGET_ABICALLS ) return false ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_SECTION_NAME ( decl ) != 0 ) { const char * name ; name = TREE_STRING_POINTER ( DECL_SECTION_NAME ( decl ) ) ; if ( strcmp ( name , ".sdata" ) != 0 && strcmp ( name , ".sbss" ) != 0 ) return false ; if ( TARGET_EXPLICIT_RELOCS || ! DECL_EXTERNAL ( decl ) ) return true ; } else if ( TARGET_EMBEDDED_DATA ) { if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) return false ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return ( size > 0 && size <= mips_section_threshold ) ; } </s>

Implement TARGET_IN_SMALL_DATA_P . Return true if it would be safe to access DECL using % gp_rel ( ... ) ( $ gp ) .


"%Kargument %d must be a constant immediate"

Expand a FCMLA lane expression EXP with code FCODE and result going to TARGET if that is convenient .


<s>
char
*
aarch64_output_sve_addvl_addpl
(
rtx
offset
)
{
static
char
buffer
[
sizeof
(
"addpl\t%x0, %x1, #-"
)
+
3
*
sizeof
(
int
)
]
;
poly_int64
offset_value
=
rtx_to_poly_int64
(
offset
)
;
gcc_assert
(
aarch64_sve_addvl_addpl_immediate_p
(
offset_value
)
)
;
int
factor
=
offset_value
.
coeffs
[
1
]
;
if
(
(
factor
&
15
)
==
0
)
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"addvl\t%%x0, %%x1, #%d"
,
factor
/
16
)
;
else
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"addpl\t%%x0, %%x1, #%d"
,
factor
/
2
)
;
return
buffer
;
}
</s>

Return the asm string for adding ADDVL or ADDPL immediate X to operand 1 and storing the result in operand 0 .


<s> const MINA32RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool SystemZShortenInst :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; LiveRegs . clear ( ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto MBBI = MBB . rbegin ( ) , MBBE = MBB . rend ( ) ; MBBI != MBBE ; ++ MBBI ) { MachineInstr & MI = * MBBI ; switch ( MI . getOpcode ( ) ) { case SystemZ :: IILF : Changed |= shortenIIF ( MI , SystemZ :: LLILL , SystemZ :: LLILH ) ; break ; case SystemZ :: IIHF : Changed |= shortenIIF ( MI , SystemZ :: LLIHL , SystemZ :: LLIHH ) ; break ; case SystemZ :: WFADB : Changed |= shortenOn001AddCC ( MI , SystemZ :: ADBR ) ; break ; case SystemZ :: WFDDB : Changed |= shortenOn001 ( MI , SystemZ :: DDBR ) ; break ; case SystemZ :: WFIDB : Changed |= shortenFPConv ( MI , SystemZ :: FIDBRA ) ; break ; case SystemZ :: WLDEB : Changed |= shortenOn01 ( MI , SystemZ :: LDEBR ) ; break ; case SystemZ :: WLEDB : Changed |= shortenFPConv ( MI , SystemZ :: LEDBRA ) ; break ; case SystemZ :: WFMDB : Changed |= shortenOn001 ( MI , SystemZ :: MDBR ) ; break ; case SystemZ :: WFLCDB : Changed |= shortenOn01 ( MI , SystemZ :: LCDFR ) ; break ; case SystemZ :: WFLNDB : Changed |= shortenOn01 ( MI , SystemZ :: LNDFR ) ; break ; case SystemZ :: WFLPDB : Changed |= shortenOn01 ( MI , SystemZ :: LPDFR ) ; break ; case SystemZ :: WFSQDB : Changed |= shortenOn01 ( MI , SystemZ :: SQDBR ) ; break ; case SystemZ :: WFSDB : Changed |= shortenOn001AddCC ( MI , SystemZ :: SDBR ) ; break ; case SystemZ :: WFCDB : Changed |= shortenOn01 ( MI , SystemZ :: CDBR ) ; break ; case SystemZ :: VL32 : Changed |= shortenOn0 ( MI , SystemZ :: LDE32 ) ; break ; case SystemZ :: VST32 : Changed |= shortenOn0 ( MI , SystemZ :: STE ) ; break ; case SystemZ :: VL64 : Changed |= shortenOn0 ( MI , SystemZ :: LD ) ; break ; case SystemZ :: VST64 : Changed |= shortenOn0 ( MI , SystemZ :: STD ) ; break ; } LiveRegs . stepBackward ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ SystemZ::IILF SystemZ::LLILL SystemZ::LLILH SystemZ::IIHF SystemZ::LLIHL SystemZ::LLIHH SystemZ::WFADB SystemZ::ADBR SystemZ::WFDDB SystemZ::DDBR SystemZ::WFIDB SystemZ::FIDBRA SystemZ::WLDEB SystemZ::LDEBR SystemZ::WLEDB SystemZ::LEDBRA SystemZ::WFMDB SystemZ::MDBR SystemZ::WFLCDB SystemZ::LCDFR SystemZ::WFLNDB SystemZ::LNDFR SystemZ::WFLPDB SystemZ::LPDFR SystemZ::WFSQDB SystemZ::SQDBR SystemZ::WFSDB SystemZ::SDBR SystemZ::WFCDB SystemZ::CDBR SystemZ::VL32 SystemZ::LDE32 SystemZ::VST32 SystemZ::STE SystemZ::VL64 SystemZ::LD SystemZ::VST64 SystemZ::STD


<s> TargetLoweringBase :: LegalizeTypeAction AArch64TargetLowering :: getPreferredVectorAction ( EVT VT ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( SVT == MVT :: v1i8 || SVT == MVT :: v1i16 || SVT == MVT :: v1i32 || SVT == MVT :: v1f32 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> int VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( FuncInfo -> isLeafProc ( ) ) { FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = VE :: SX17 ; else FrameReg = VE :: SX11 ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch"

"assembler does not support %<-mabi=ilp32%>"

"return address signing is only supported for %<-mabi=lp64%>"


<s> static void sparc32_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , 10 , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x03000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , 10 , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x05000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x81c06000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , cxt , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x8410a000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_insn ( gen_flushsi ( validize_mem ( adjust_address ( m_tramp , SImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 && sparc_cpu != PROCESSOR_NIAGARA7 ) emit_insn ( gen_flushsi ( validize_mem ( adjust_address ( m_tramp , SImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . This takes 16 insns : 2 shifts & 2 ands ( to split up addresses ) , 4 sethi ( to load in opcodes ) , 4 iors ( to merge address and opcodes ) , and 4 writes ( to store insns ) . This is a bit excessive . Perhaps a different mechanism would be better here . Emit enough FLUSH insns to synchronize the data and instruction caches .


<s> const PPCMCExpr * PPCMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { int AssemblerDialect = Ctx . getAsmInfo ( ) -> getAssemblerDialect ( ) ; return new ( Ctx ) PPCMCExpr ( Kind , Expr , AssemblerDialect ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & FS , bool is64Bit ) : StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , DarwinVers ( 0 ) { std :: string CPU = "generic" ; CPU = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( FS , CPU ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( TT . length ( ) > 7 ) { size_t DarwinPos = TT . find ( "-darwin" ) ; if ( DarwinPos != std :: string :: npos ) { if ( isdigit ( TT [ DarwinPos + 7 ] ) ) DarwinVers = atoi ( & TT [ DarwinPos + 7 ] ) ; else DarwinVers = 8 ; } } if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: GPRPairRegClassID : return Super ; case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : if ( MF . getSubtarget < ARMSubtarget > ( ) . hasNEON ( ) ) return Super ; break ; case ARM :: MQPRRegClassID : case ARM :: MQQPRRegClassID : case ARM :: MQQQQPRRegClassID : if ( MF . getSubtarget < ARMSubtarget > ( ) . hasMVEIntegerOps ( ) ) return Super ; break ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM::GPRRegClassID ARM::SPRRegClassID ARM::DPRRegClassID ARM::GPRPairRegClassID ARM::QPRRegClassID ARM::QQPRRegClassID ARM::QQQQPRRegClassID ARM ARM::MQPRRegClassID ARM::MQQPRRegClassID ARM::MQQQQPRRegClassID ARM


<s> static int extended_reg_mentioned_1 ( rtx * p , void * data ATTRIBUTE_UNUSED ) { unsigned int regno ; if ( ! REG_P ( * p ) ) return 0 ; regno = REGNO ( * p ) ; return REX_INT_REGNO_P ( regno ) || REX_SSE_REGNO_P ( regno ) ; } </s>

Return nonzero when P points to register encoded via REX prefix . Called via for_each_rtx .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
FixupKind
>=
FirstLiteralRelocationKind
)
return
true
;
if
(
FixupKind
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


<s> void csky_init_expanders ( void ) { init_machine_status = csky_init_machine_status ; } </s>


<s> inline void classify_registers ( const_tree , int bitpos , bool fp , classify_data_t * data ) { if ( fp ) { data -> fp_regs = true ; if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word = true ; } } </s>

A subroutine of function_arg_slotno . Classify the field .


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( createAArch64ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; addPass ( createAArch64VectorByElementOptPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> unsigned getPrefetchDistance ( ) { return 2000 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> static bool use_skip_p ( rtx_insn * insn ) { rtx_insn * jump_insn = next_active_insn ( JUMP_LABEL ( insn ) ) ; while ( insn ) { insn = next_active_insn ( insn ) ; if ( ! insn || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || extract_asm_operands ( PATTERN ( insn ) ) != NULL_RTX ) break ; if ( get_attr_length ( insn ) == 4 && jump_insn == next_active_insn ( insn ) ) return TRUE ; if ( get_attr_length ( insn ) > 0 ) break ; } return FALSE ; } </s>

Return TRUE if INSN , a forward jump insn , can use nullification to skip the following instruction . This avoids an extra cycle due to a mis-predicted branch when we fall through .


<s>
void
MipsSEInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LW_P8
:
Mips
::
LW
;
else
if
(
Mips
::
CPU64RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LD_P8
:
Mips
::
LD
;
else
if
(
Mips
::
FGR32RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LWC1_P8
:
Mips
::
LWC1
;
else
if
(
Mips
::
AFGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
LDC1
;
else
if
(
Mips
::
FGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LDC164_P8
:
Mips
::
LDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool X86Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtarget :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtarget :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> uint64_t ARMGOT :: emit ( MemoryRegion & pRegion ) { uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; ARMGOTEntry * got = NULL ; uint64_t result = 0x0 ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < ARMGOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += ARMGOTEntry :: EntrySize ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .

ARM ARM ARM 0x0 ARM ARMGOTEntry::EntrySize


<s> bool Mips16TargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { return false ; } </s>

Returns true if the call can be lowered as a tail call .


<s> bool SystemZAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode ) return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; SystemZInstPrinter :: printOperand ( MO , MAI , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const MipsSubtarget & ST = MF . getTarget ( ) . getSubtarget < MipsSubtarget > ( ) ; const TargetRegisterClass * RC ; if ( ST . inMips16Mode ( ) ) RC = ( const TargetRegisterClass * ) & Mips :: CPU16RegsRegClass ; else RC = ST . isABI_N64 ( ) ? ( const TargetRegisterClass * ) & Mips :: CPU64RegsRegClass : ( const TargetRegisterClass * ) & Mips :: CPURegsRegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips Mips Mips Mips Mips Mips::CPU16RegsRegClass Mips::CPU64RegsRegClass Mips::CPURegsRegClass