<s> void aarch64_split_128bit_move ( rtx dst , rtx src ) { rtx dst_lo , dst_hi ; rtx src_lo , src_hi ; machine_mode mode = GET_MODE ( dst ) ; gcc_assert ( mode == TImode || mode == TFmode ) ; gcc_assert ( ! ( side_effects_p ( src ) || side_effects_p ( dst ) ) ) ; gcc_assert ( mode == GET_MODE ( src ) || GET_MODE ( src ) == VOIDmode ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { int src_regno = REGNO ( src ) ; int dst_regno = REGNO ( dst ) ; if ( FP_REGNUM_P ( dst_regno ) && GP_REGNUM_P ( src_regno ) ) { src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart ( word_mode , src ) ; emit_insn ( gen_aarch64_movlow_di ( mode , dst , src_lo ) ) ; emit_insn ( gen_aarch64_movhigh_di ( mode , dst , src_hi ) ) ; return ; } else if ( GP_REGNUM_P ( dst_regno ) && FP_REGNUM_P ( src_regno ) ) { dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; emit_insn ( gen_aarch64_movdi_low ( mode , dst_lo , src ) ) ; emit_insn ( gen_aarch64_movdi_high ( mode , dst_hi , src ) ) ; return ; } } dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart_mode ( word_mode , mode , src ) ; if ( reg_overlap_mentioned_p ( dst_lo , src_hi ) ) { aarch64_emit_move ( dst_hi , src_hi ) ; aarch64_emit_move ( dst_lo , src_lo ) ; } else { aarch64_emit_move ( dst_lo , src_lo ) ; aarch64_emit_move ( dst_hi , src_hi ) ; } } </s>

Split a 128-bit move operation into two 64-bit move operations , taking care to handle partial overlap of register to register copies . Special cases are needed when moving between GP regs and FP regs . SRC can be a register , constant or memory ; DST a register or memory . If either operand is memory it must not have any side effects .


<s> unsigned getNumFixupKinds ( ) const override { return CJG :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool ARMSubtarget :: useFastISel ( ) const { return TM . Options . EnableFastISel && ( ( isTargetMachO ( ) && ! isThumb1Only ( ) ) || ( isTargetLinux ( ) && ! isThumb ( ) ) || ( isTargetNaCl ( ) && ! isThumb ( ) ) ) ; } </s>


<s> static bool or1k_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( rclass == FLAG_REGS ) return from == to ; return true ; } </s>

Worker for TARGET_CAN_CHANGE_MODE_CLASS . Returns true if its ok to change a register in class RCLASS from mode FROM to mode TO . In general OpenRISC registers , other than special flags , handle all supported classes .


<s>
unsigned
getReg
(
)
const
{
if
(
Kind
==
k_RegisterIndex
&&
RegIdx
.
Index
==
0
&&
RegIdx
.
Kind
&
RegKind_GPR
)
return
getGPR32Reg
(
)
;
assert
(
Kind
==
k_PhysRegister
&&
"Invalid access!"
)
;
return
PhysReg
.
Num
;
}
</s>

Returns the register associated with this edge .


Generate external symbol indirection stubs ( PIC and non-PIC ) .


<s>
void
init_cumulative_args
(
CUMULATIVE_ARGS
*
cum
,
tree
fntype
,
rtx
libname
,
tree
fndecl
)
{
static
CUMULATIVE_ARGS
zero_cum
;
tree
param
,
next_param
;
if
(
TARGET_DEBUG_ARG
)
{
fprintf
(
stderr
,
"\ninit_cumulative_args ("
)
;
if
(
fntype
)
fprintf
(
stderr
,
"fntype code = %s, ret code = %s"
,
tree_code_name
[
(
int
)
TREE_CODE
(
fntype
)
]
,
tree_code_name
[
(
int
)
TREE_CODE
(
TREE_TYPE
(
fntype
)
)
]
)
;
else
fprintf
(
stderr
,
"no fntype"
)
;
if
(
libname
)
fprintf
(
stderr
,
", libname = %s"
,
XSTR
(
libname
,
0
)
)
;
}
*
cum
=
zero_cum
;
cum
->
nregs
=
ix86_regparm
;
if
(
TARGET_SSE
)
cum
->
sse_nregs
=
SSE_REGPARM_MAX
;
if
(
TARGET_MMX
)
cum
->
mmx_nregs
=
MMX_REGPARM_MAX
;
cum
->
warn_sse
=
true
;
cum
->
warn_mmx
=
true
;
cum
->
maybe_vaarg
=
false
;
if
(
fntype
&&
!
TARGET_64BIT
)
{
if
(
lookup_attribute
(
"fastcall"
,
TYPE_ATTRIBUTES
(
fntype
)
)
)
{
cum
->
nregs
=
2
;
cum
->
fastcall
=
1
;
}
else
cum
->
nregs
=
ix86_function_regparm
(
fntype
,
fndecl
)
;
}
cum
->
float_in_sse
=
ix86_function_sseregparm
(
fntype
,
fndecl
)
;
if
(
cum
->
nregs
||
cum
->
mmx_nregs
||
cum
->
sse_nregs
)
{
for
(
param
=
(
fntype
)
TYPE_ARG_TYPES
(
fntype
)
:
0
;
param
!=
0
;
param
=
next_param
)
{
next_param
=
TREE_CHAIN
(
param
)
;
if
(
next_param
==
0
&&
TREE_VALUE
(
param
)
!=
void_type_node
)
{
if
(
!
TARGET_64BIT
)
{
cum
->
nregs
=
0
;
cum
->
sse_nregs
=
0
;
cum
->
mmx_nregs
=
0
;
cum
->
warn_sse
=
0
;
cum
->
warn_mmx
=
0
;
cum
->
fastcall
=
0
;
cum
->
float_in_sse
=
0
;
}
cum
->
maybe_vaarg
=
true
;
}
}
}
if
(
(
!
fntype
&&
!
libname
)
||
(
fntype
&&
!
TYPE_ARG_TYPES
(
fntype
)
)
)
cum
->
maybe_vaarg
=
true
;
if
(
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
", nregs=%d )\n"
,
cum
->
nregs
)
;
return
;
}
</s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
for
(
MachineInstr
&
MI
:
MBB
)
{
if
(
!
MI
.
isFullCopy
(
)
)
continue
;
MachineOperand
&
DstMO
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
SrcMO
=
MI
.
getOperand
(
1
)
;
if
(
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
!
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
SrcRC
=
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown source for a VSX copy"
)
;
unsigned
NewVReg
=
MRI
.
createVirtualRegister
(
SrcRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
SUBREG_TO_REG
)
,
NewVReg
)
.
addImm
(
1
)
.
addOperand
(
SrcMO
)
.
addImm
(
PPC
::
sub_64
)
;
SrcMO
.
setReg
(
NewVReg
)
;
}
else
if
(
!
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
DstRC
=
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
DstMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown destination for a VSX copy"
)
;
unsigned
NewVReg
=
MRI
.
createVirtualRegister
(
DstRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
NewVReg
)
.
addOperand
(
SrcMO
)
;
SrcMO
.
setReg
(
NewVReg
)
;
SrcMO
.
setSubReg
(
PPC
::
sub_64
)
;
}
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && frame_pointer_needed ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( current_function_pretend_args_size || cfun -> machine -> uses_anonymous_args || current_function_calls_eh_return || current_function_calls_alloca || ! ( stack_adjust == 0 || ( frame_pointer_needed && stack_adjust == 4 ) ) ) return 0 ; saved_int_regs = arm_compute_save_reg_mask ( ) ; if ( stack_adjust == 4 && ! arm_arch5 ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( GET_CODE ( sibling ) == CALL_INSN ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ) return 0 ; } if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_FPA ) for ( regno = FIRST_FPA_REGNUM ; regno <= LAST_FPA_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> virtual bool useAA ( ) const LLVM_OVERRIDE { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> unsigned int ix86_local_alignment ( tree exp , machine_mode mode , unsigned int align ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( ! TARGET_64BIT && align == 64 && ix86_preferred_stack_boundary < 64 && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = 32 ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , 128 ) && align < 128 ) return 128 ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> rtx ix86_build_const_vector ( machine_mode mode , bool vect , rtx value ) { int i , n_elt ; rtvec v ; machine_mode scalar_mode ; switch ( mode ) { case V64QImode : case V32QImode : case V16QImode : case V32HImode : case V16HImode : case V8HImode : case V16SImode : case V8SImode : case V4SImode : case V8DImode : case V4DImode : case V2DImode : gcc_assert ( vect ) ; case V16SFmode : case V8SFmode : case V4SFmode : case V8DFmode : case V4DFmode : case V2DFmode : n_elt = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( n_elt ) ; scalar_mode = GET_MODE_INNER ( mode ) ; RTVEC_ELT ( v , 0 ) = value ; for ( i = 1 ; i < n_elt ; ++ i ) RTVEC_ELT ( v , i ) = vect ? value : CONST0_RTX ( scalar_mode ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; default : gcc_unreachable ( ) ; } } </s>

A subroutine of ix86_build_signbit_mask . If VECT is true , then replicate the value for all elements of the vector register .


<s> static void aarch64_emit_sve_invert_fp_cond ( rtx target , rtx_code code , rtx pred , bool known_ptrue_p , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( pred ) ; rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_sve_fp_cond ( tmp , code , pred , known_ptrue_p , op0 , op1 ) ; aarch64_emit_unop ( target , one_cmpl_optab , tmp ) ; } </s>

Emit the SVE equivalent of : ( set TMP ( unspec [ PRED KNOWN_PTRUE_P OP0 OP1 ] UNSPEC_COND_ < X > ) ) ( set TARGET ( not TMP ) ) where < X > is the operation associated with comparison CODE . KNOWN_PTRUE_P is true if PRED is known to be a PTRUE .


<s>
bool
X86IntelAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
unsigned
CC
=
F
->
getCallingConv
(
)
;
if
(
CC
==
CallingConv
::
X86_StdCall
||
CC
==
CallingConv
::
X86_FastCall
)
FunctionInfoMap
[
F
]
=
*
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
decorateName
(
CurrentFnName
,
F
)
;
SwitchToTextSection
(
"_text"
,
F
)
;
unsigned
FnAlign
=
4
;
if
(
F
->
hasFnAttr
(
Attribute
::
OptimizeForSize
)
)
FnAlign
=
1
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
assert
(
0
&&
"Unsupported linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
InternalLinkage
:
EmitAlignment
(
FnAlign
)
;
break
;
case
Function
::
DLLExportLinkage
:
DLLExportedFns
.
insert
(
CurrentFnName
)
;
case
Function
::
ExternalLinkage
:
O
<<
"\tpublic "
<<
CurrentFnName
<<
"\n"
;
EmitAlignment
(
FnAlign
)
;
break
;
}
O
<<
CurrentFnName
<<
"\tproc near\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
I
->
pred_empty
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
O
<<
CurrentFnName
<<
"\tendp\n"
;
O
.
flush
(
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
void
X86InstPrinterCommon
::
printPCRelImm
(
const
MCInst
*
MI
,
uint64_t
Address
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
{
if
(
PrintBranchImmAsAddress
)
{
uint64_t
Target
=
Address
+
Op
.
getImm
(
)
;
if
(
MAI
.
getCodePointerSize
(
)
==
4
)
Target
&=
0xffffffff
;
O
<<
formatHex
(
Target
)
;
}
else
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
}
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
Op
.
getExpr
(
)
->
print
(
O
,
&
MAI
)
;
}
}
}
</s>


"preferPredicateOverEpilogue: not a single block "

"preferPredicateOverEpilogue: hardware-loop is not "

Query the target whether it would be prefered to create a predicated vector loop , which can avoid the need to emit a scalar epilogue loop .


<s> void sh_mark_label ( rtx address , int nuses ) { if ( GOTOFF_P ( address ) ) { address = XEXP ( address , 0 ) ; if ( GET_CODE ( address ) == PLUS ) address = XEXP ( address , 0 ) ; address = XVECEXP ( address , 0 , 0 ) ; } if ( GET_CODE ( address ) == LABEL_REF && LABEL_P ( XEXP ( address , 0 ) ) ) LABEL_NUSES ( XEXP ( address , 0 ) ) += nuses ; } </s>

If ADDRESS refers to a CODE_LABEL , add NUSES to the number of times that label is used .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool IsN64 = Subtarget . isABI_N64 ( ) ; if ( Subtarget . inMips16Mode ( ) ) return TFI -> hasFP ( MF ) ? Mips :: S0 : Mips :: SP ; else return TFI -> hasFP ( MF ) ? ( IsN64 ? Mips :: FP_64 : Mips :: FP ) : ( IsN64 ? Mips :: SP_64 : Mips :: SP ) ; } </s>

Mips Mips Mips Mips::S0 Mips::SP Mips::FP_64 Mips::FP Mips::SP_64 Mips::SP


<s>
void
rs6000_xcoff_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
tree
decl
)
{
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
1
)
;
char
*
p
;
int
dollar_inside
=
0
;
struct
declare_alias_data
data
=
{
file
,
false
}
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
decl
)
)
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.globl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
}
else
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.lglobl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
fputs
(
"\t.csect "
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
TARGET_32BIT
"[DS]\n"
:
"[DS],3\n"
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
fputs
(
TARGET_32BIT
"\t.long ."
:
"\t.llong ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
", TOC[tc0], 0\n"
,
file
)
;
in_section
=
;
switch_to_section
(
function_section
(
decl
)
)
;
putc
(
'.'
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
data
.
function_descriptor
=
true
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
if
(
!
DECL_IGNORED_P
(
decl
)
)
{
if
(
write_symbols
==
DBX_DEBUG
||
write_symbols
==
XCOFF_DEBUG
)
xcoffout_declare_function
(
file
,
decl
,
buffer
)
;
else
if
(
write_symbols
==
DWARF2_DEBUG
)
{
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
fprintf
(
file
,
"\t.function .%s,.%s,2,0\n"
,
name
,
name
)
;
}
}
return
;
}
</s>

This macro produces the initial definition of a function name . On the RS/6000 , we need to place an extra ' . ' in the function name and output the function descriptor . Dollar signs are converted to underscores . The csect for the function will have already been created when text_section was selected . We do have to go back to that csect , however . The third and fourth parameters to the .function pseudo-op ( 16 and 044 ) are placeholders which no longer have any use . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * GISel = new AArch64GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new AArch64LegalizerInfo ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( createAArch64InstructionSelector ( * this , * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void rs6000_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , rs6000_d_handle_target_float_abi } , { "objectFormat" , rs6000_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> bool Cpu0TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> ARMSubtarget & ARMSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
MachineBasicBlock
*
CSKYTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
CSKY
::
FSELS
:
case
CSKY
::
FSELD
:
if
(
Subtarget
.
hasE2
(
)
)
return
emitSelectPseudo
(
MI
,
BB
,
CSKY
::
BT32
)
;
else
return
emitSelectPseudo
(
MI
,
BB
,
CSKY
::
BT16
)
;
case
CSKY
::
ISEL32
:
return
emitSelectPseudo
(
MI
,
BB
,
CSKY
::
BT32
)
;
case
CSKY
::
ISEL16
:
return
emitSelectPseudo
(
MI
,
BB
,
CSKY
::
BT16
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void Cpu0AsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( "\t.frame\t$" + StringRef ( Cpu0InstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + "," + Twine ( stackSize ) + ",$" + StringRef ( Cpu0InstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ; } </s>


<s> UPTSubtarget & UPTSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic-upt" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
getARMRegisterNumbering
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry .


<s> FastISel * MipsTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { if ( ! EnableMipsFastISel ) return TargetLowering :: createFastISel ( funcInfo , libInfo ) ; return Mips :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static void mips_output_32bit_xfer ( char direction , unsigned int gpreg , unsigned int fpreg ) { fprintf ( asm_out_file , "\tm%cc1\t%s,%s\n" , direction , reg_names [ gpreg ] , reg_names [ fpreg ] ) ; } </s>

Write instructions to move a 32-bit value between general register GPREG and floating-point register FPREG . DIRECTION is 't ' to move from GPREG to FPREG and ' f ' to move in the opposite direction .


<s> const SICSubtarget * getSubtargetImpl ( ) const { return & DefaultSubtarget ; } </s>


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { Align Alignment = Subtarget . isPPC64 ( ) ? Align ( 8 ) : Align ( 4 ) ; if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Alignment , Subtarget . hasQPX ( ) ? Align ( 32 ) : Align ( 16 ) ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? 0 : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> int pa_fmpysuboperands ( rtx * operands ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( ! ( mode == GET_MODE ( operands [ 1 ] ) && mode == GET_MODE ( operands [ 2 ] ) && mode == GET_MODE ( operands [ 3 ] ) && mode == GET_MODE ( operands [ 4 ] ) && mode == GET_MODE ( operands [ 5 ] ) ) ) return 0 ; if ( ! ( GET_CODE ( operands [ 1 ] ) == REG && GET_CODE ( operands [ 2 ] ) == REG && GET_CODE ( operands [ 3 ] ) == REG && GET_CODE ( operands [ 4 ] ) == REG && GET_CODE ( operands [ 5 ] ) == REG ) ) return 0 ; if ( ! rtx_equal_p ( operands [ 3 ] , operands [ 4 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 5 ] , operands [ 0 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 3 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 1 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 2 ] ) ) return 0 ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ 0 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 1 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 2 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 3 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 4 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 5 ] ) ) != FPUPPER_REGS ) ) return 0 ; return 1 ; } </s>

Returns 1 if the 6 operands specified in OPERANDS are suitable for use in fmpysub instructions .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; genExecuteOnly = ARM_TM . getSubtargetImpl ( ) -> genExecuteOnly ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_ARM_PURECODE ; TextSection = Ctx . getELFSection ( ".text" , Type , Flags , 0 , "" , 0U ) ; } } </s>

This method must be called before any actual lowering is done .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
getARMRegisterNumbering
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) PM -> add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) PM -> add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; if ( ! Subtarget -> isThumb1Only ( ) && Subtarget -> hasV6T2Ops ( ) ) { SDValue R = PerformCMOVToBFICombine ( N , DAG ) ; if ( R ) return R ; } SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . computeKnownBits ( SDValue ( N , 0 ) , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s> bool ARMOptimizeBarriersPass :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - 1 ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == ARM :: DMB ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( 0 ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else { IsRemovableNextDMB = true ; DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else if ( ! CanMovePastDMB ( & MI ) ) { IsRemovableNextDMB = false ; } } } for ( auto MI : ToRemove ) { MI -> eraseFromParent ( ) ; ++ NumDMBsRemoved ; } return NumDMBsRemoved > 0 ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool SystemZAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".insn" ) return ParseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "sinl" , "sqrtl" , "truncl" } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < 0 ; } ; assert ( std :: is_sorted ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s>
void
Cpu0InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Cpu0
::
ADD
,
ZeroReg
=
Cpu0
::
ZERO
;
else
if
(
SrcReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MFLO
,
SrcReg
=
0
;
}
else
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MTLO
,
DestReg
=
0
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( AFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> static unsigned long arm_compute_save_reg0_reg12_mask ( void ) { unsigned long func_type = arm_current_func_type ( ) ; unsigned long save_reg_mask = 0 ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = 7 ; else max_reg = 12 ; for ( reg = 0 ; reg <= max_reg ; reg ++ ) if ( reg_needs_saving_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; if ( PIC_REGISTER_MAY_NEED_SAVING && crtl -> uses_pic_offset_table ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } else if ( IS_VOLATILE ( func_type ) ) { if ( frame_pointer_needed ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( ARM_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( THUMB_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= 1 << THUMB_HARD_FRAME_POINTER_REGNUM ; } else { for ( reg = 0 ; reg <= 11 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) save_reg_mask |= ( 1 << reg ) ; if ( frame_pointer_needed ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( PIC_REGISTER_MAY_NEED_SAVING && ( df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) || crtl -> uses_pic_offset_table ) ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( IS_STACKALIGN ( func_type ) ) save_reg_mask |= 1 ; } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; i ++ ) { reg = EH_RETURN_DATA_REGNO ( i ) ; if ( reg == INVALID_REGNUM ) break ; save_reg_mask |= 1 << reg ; } } return save_reg_mask ; } </s>

Compute the register save mask for registers 0 through 12 inclusive . This code is used by arm_compute_save_reg_mask .


<s> static void r10k_needs_protection_p_store ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx_insn * * insn_ptr ; insn_ptr = ( rtx_insn * * ) data ; if ( * insn_ptr && r10k_needs_protection_p_1 ( x , * insn_ptr ) ) * insn_ptr = NULL ; } </s>

A note_stores callback for which DATA points to an instruction pointer . If * DATA is nonnull , make it null if it X contains a MEM that is not safe from R10K speculation .


<s> unsigned getNumFixupKinds ( ) const override { return LC3 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { if ( GET_CODE ( XEXP ( link , 0 ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , 0 ) , 0 ) ; if ( ix86_check_avx256_register ( arg ) ) return AVX_U128_DIRTY ; } } return AVX_U128_CLEAN ; } subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( ix86_check_avx256_register ( * iter ) ) return AVX_U128_DIRTY ; return AVX_U128_ANY ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
UP
.
UpperBound
=
true
;
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
unsigned
UnrollCount
=
4
;
if
(
ST
->
isThumb1Only
(
)
)
{
unsigned
ExitingValues
=
0
;
SmallVector
<
BasicBlock
*
,
4
>
ExitBlocks
;
L
->
getExitBlocks
(
ExitBlocks
)
;
for
(
auto
*
Exit
:
ExitBlocks
)
{
unsigned
LiveOuts
=
count_if
(
Exit
->
phis
(
)
,
[
]
(
auto
&
PH
)
{
return
PH
.
getNumOperands
(
)
!=
1
||
!
isa
<
GetElementPtrInst
>
(
PH
.
getOperand
(
0
)
)
;
}
)
;
ExitingValues
=
ExitingValues
<
LiveOuts
LiveOuts
:
ExitingValues
;
}
if
(
ExitingValues
)
UnrollCount
/=
ExitingValues
;
if
(
UnrollCount
<=
1
)
return
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Default Runtime Unroll Count: "
<<
UnrollCount
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
UnrollCount
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , ARM :: tGPRRegisterClass ) ; else return RCPair ( 0U , ARM :: GPRRegisterClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , ARM :: hGPRRegisterClass ) ; break ; case 'r' : return RCPair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return RCPair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , ARM :: DPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , ARM :: QPRRegisterClass ) ; break ; case 'x' : if ( VT == MVT :: f32 ) return RCPair ( 0U , ARM :: SPR_8RegisterClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , ARM :: DPR_8RegisterClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , ARM :: QPR_8RegisterClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , ARM :: SPRRegisterClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , ARM :: CCRRegisterClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> int registers_ok_for_ldd_peep ( rtx reg1 , rtx reg2 ) { if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return 0 ; if ( REGNO ( reg1 ) % 2 != 0 ) return 0 ; if ( TARGET_V9 && REGNO ( reg1 ) < 32 ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) is even and REGNO ( reg1 ) == REGNO ( reg2 ) - 1 . This makes them candidates for using ldd and std insns . Note reg1 and reg2 * must * be hard registers .


"getJumpOffset16OpValue expects only expressions or an immediate"

getJumpOffset16OpValue - Return binary encoding of the jump target operand .


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; switch ( mode ) { case QImode : fn = gen_load_lockedqi ; break ; case HImode : fn = gen_load_lockedhi ; break ; case SImode : if ( GET_MODE ( mem ) == QImode ) fn = gen_load_lockedqi_si ; else if ( GET_MODE ( mem ) == HImode ) fn = gen_load_lockedhi_si ; else fn = gen_load_lockedsi ; break ; case DImode : fn = gen_load_lockeddi ; break ; case TImode : fn = gen_load_lockedti ; break ; default : gcc_unreachable ( ) ; } emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s> virtual const LanaiRegisterInfo & getRegisterInfo ( ) const { return RegisterInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createX86IndirectBranchTrackingPass ( ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; addPass ( createX86EvexToVexInsts ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool global_reg_mentioned_p_1 ( const_rtx x ) { int regno ; switch ( GET_CODE ( x ) ) { case SUBREG : if ( REG_P ( SUBREG_REG ( x ) ) ) { if ( REGNO ( SUBREG_REG ( x ) ) < FIRST_PSEUDO_REGISTER && global_regs [ subreg_regno ( x ) ] ) return true ; return false ; } break ; case REG : regno = REGNO ( x ) ; if ( regno < FIRST_PSEUDO_REGISTER && global_regs [ regno ] ) return true ; return false ; case CALL : return true ; default : break ; } return false ; } </s>

A subroutine of global_reg_mentioned_p , returns 1 if * LOC mentions a global register .


<s> bool isImm ( ) const override { return Kind == IMMEDIATE ; } </s>


" was Pass-through, is now Dirty-out.\n"

runOnMachineFunction - Emit the function body .


<s> void SystemZPostRASchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DAG = dag ; HazardRec . setDAG ( dag ) ; HazardRec . Reset ( ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> static void swap_reorder ( rtx_insn * * a , int n ) { rtx_insn * insn = a [ n - 1 ] ; int i = n - 2 ; while ( i >= 0 && rank_for_reorder ( a + i , & insn ) >= 0 ) { a [ i + 1 ] = a [ i ] ; i -= 1 ; } a [ i + 1 ] = insn ; } </s>

Resort the array A in which only element at index N may be out of order .


<s> static void loongarch_emit_int_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 ) { static const enum rtx_code mag_comparisons [ ] [ 2 ] = { { LEU , LTU } , { GTU , GEU } , { LE , LT } , { GT , GE } } ; if ( splittable_const_int_operand ( * op1 , VOIDmode ) ) { HOST_WIDE_INT rhs = INTVAL ( * op1 ) ; if ( * code == EQ || * code == NE ) { if ( IMM12_OPERAND ( - rhs ) ) { * op0 = loongarch_force_binary ( GET_MODE ( * op0 ) , PLUS , * op0 , GEN_INT ( - rhs ) ) ; * op1 = const0_rtx ; } } else { for ( size_t i = 0 ; i < ARRAY_SIZE ( mag_comparisons ) ; i ++ ) { HOST_WIDE_INT new_rhs ; bool increment = * code == mag_comparisons [ i ] [ 0 ] ; bool decrement = * code == mag_comparisons [ i ] [ 1 ] ; if ( ! increment && ! decrement ) continue ; new_rhs = rhs + ( increment ? 1 : - 1 ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) && ( rhs < 0 ) == ( new_rhs < 0 ) ) { * op1 = GEN_INT ( new_rhs ) ; * code = mag_comparisons [ i ] [ increment ] ; } break ; } } } loongarch_extend_comparands ( * code , op0 , op1 ) ; * op0 = force_reg ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = force_reg ( word_mode , * op1 ) ; } </s>

Convert a comparison into something that can be used in a branch . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update them to describe the final comparison .


<s> const char * LC3TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case LC3ISD :: RET_FLAG : return "RetFlag" ; case LC3ISD :: LOAD_SYM : return "LOAD_SYM" ; case LC3ISD :: MOVEi16 : return "MOVEi16" ; case LC3ISD :: CALL : return "CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> StringRef getPassName ( ) const override { return THUMB2_SIZE_REDUCE_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool isLegalMaskedStore ( Type * DataType ) { return ST -> hasSVE ( ) ; } </s>

Return true if the target supports masked store .


<s> Register ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return STI . getFramePointerReg ( ) ; return ARM :: SP ; } </s>


<s>
bool
ARMCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
)
const
{
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
auto
const
&
ST
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
;
unsigned
Opcode
=
ST
.
getReturnOpcode
(
)
;
auto
Ret
=
MIRBuilder
.
buildInstrNoInsert
(
Opcode
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
if
(
!
lowerReturnVal
(
MIRBuilder
,
Val
,
VRegs
,
Ret
)
)
return
false
;
MIRBuilder
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

ARM
ARM
"Return value without a vreg"
ARM
ARMCC::AL


Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some ordering condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; OPERANDS [ 3 ] is the second operand and may be zero or a register .


<s> static int distance_agu_use ( unsigned int regno0 , rtx_insn * insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; int distance = 0 ; bool found = false ; bool redefined = false ; if ( insn != BB_END ( bb ) ) distance = distance_agu_use_in_bb ( regno0 , insn , distance , NEXT_INSN ( insn ) , & found , & redefined ) ; if ( ! found && ! redefined && distance < LEA_SEARCH_THRESHOLD ) { edge e ; edge_iterator ei ; bool simple_loop = false ; FOR_EACH_EDGE ( e , ei , bb -> succs ) if ( e -> dest == bb ) { simple_loop = true ; break ; } if ( simple_loop ) distance = distance_agu_use_in_bb ( regno0 , insn , distance , BB_HEAD ( bb ) , & found , & redefined ) ; else { int shortest_dist = - 1 ; bool found_in_bb = false ; bool redefined_in_bb = false ; FOR_EACH_EDGE ( e , ei , bb -> succs ) { int bb_dist = distance_agu_use_in_bb ( regno0 , insn , distance , BB_HEAD ( e -> dest ) , & found_in_bb , & redefined_in_bb ) ; if ( found_in_bb ) { if ( shortest_dist < 0 ) shortest_dist = bb_dist ; else if ( bb_dist > 0 ) shortest_dist = MIN ( bb_dist , shortest_dist ) ; found = true ; } } distance = shortest_dist ; } } if ( ! found || redefined ) return - 1 ; return distance >> 1 ; } </s>

Return the distance between INSN and the next insn that uses register number REGNO0 in memory address . Return -1 if no such a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set .


<s> void MipsAsmPrinter :: emitFunctionBodyEnd ( ) { MipsTargetStreamer & TS = getTargetStreamer ( ) ; if ( ! Subtarget -> inMips16Mode ( ) ) { TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; } TS . emitDirectiveEnd ( CurrentFnSym -> getName ( ) ) ; if ( ! InConstantPool ) return ; InConstantPool = false ; OutStreamer -> emitDataRegion ( MCDR_DataRegionEnd ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> static rtx rs6000_load_constant_and_splat ( machine_mode mode , REAL_VALUE_TYPE dconst ) { rtx reg ; if ( mode == SFmode || mode == DFmode ) { rtx d = const_double_from_real_value ( dconst , mode ) ; reg = force_reg ( mode , d ) ; } else if ( mode == V4SFmode ) { rtx d = const_double_from_real_value ( dconst , SFmode ) ; rtvec v = gen_rtvec ( 4 , d , d , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else if ( mode == V2DFmode ) { rtx d = const_double_from_real_value ( dconst , DFmode ) ; rtvec v = gen_rtvec ( 2 , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else gcc_unreachable ( ) ; return reg ; } </s>

Load up a constant . If the mode is a vector mode , splat the value across all of the vector elements .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NeedsPop = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( MBB . succ_empty ( ) ) { if ( isVarArg ) continue ; if ( ! STI . hasV5TOps ( ) ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; if ( MI != MBB . end ( ) ) MIB . copyImplicitOps ( * MI ) ; MI = MBB . erase ( MI ) ; } else continue ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NeedsPop = true ; } if ( NeedsPop ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool LC3RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> void pa_output_global_address ( FILE * file , rtx x , int round_constant ) { if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF && read_only_operand ( x , VOIDmode ) ) output_addr_const ( file , x ) ; else if ( GET_CODE ( x ) == SYMBOL_REF && ! flag_pic ) { output_addr_const ( file , x ) ; fputs ( "-$global$" , file ) ; } else if ( GET_CODE ( x ) == CONST ) { const char * sep = "" ; int offset = 0 ; rtx base = NULL_RTX ; switch ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , 0 ) , 0 ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , 0 ) , 1 ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ; break ; default : gcc_unreachable ( ) ; } if ( round_constant ) offset = ( ( offset + 0x1000 ) & ~ 0x1fff ) ; switch ( GET_CODE ( XEXP ( x , 0 ) ) ) { case PLUS : if ( offset < 0 ) { offset = - offset ; sep = "-" ; } else sep = "+" ; break ; case MINUS : gcc_assert ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF ) ; sep = "-" ; break ; default : gcc_unreachable ( ) ; } if ( ! read_only_operand ( base , VOIDmode ) && ! flag_pic ) fputs ( "-$global$" , file ) ; if ( offset ) fprintf ( file , "%s%d" , sep , offset ) ; } else output_addr_const ( file , x ) ; } </s>

output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF .


<s> const MCPhysReg * CSKYRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const CSKYSubtarget & STI = MF -> getSubtarget < CSKYSubtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { return CSR_GPR_ISR_SaveList ; } return CSR_I32_SaveList ; } </s>


<s> bool PPCTargetLowering :: SelectAddressEVXRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { for ( SDNode * U : N -> uses ( ) ) { if ( MemSDNode * Memop = dyn_cast < MemSDNode > ( U ) ) { if ( Memop -> getMemoryVT ( ) == MVT :: f64 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressEVXRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> const MCExpr * X86TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget . isPICStyleRIPRel ( ) || Subtarget . is64Bit ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s>
static
void
mips_file_end
(
void
)
{
tree
name_tree
;
struct
extern_list
*
p
;
if
(
extern_head
)
{
fputs
(
"\n"
,
asm_out_file
)
;
for
(
p
=
extern_head
;
p
!=
0
;
p
=
p
->
next
)
{
name_tree
=
get_identifier
(
p
->
name
)
;
if
(
!
TREE_ASM_WRITTEN
(
name_tree
)
&&
TREE_SYMBOL_REFERENCED
(
name_tree
)
)
{
TREE_ASM_WRITTEN
(
name_tree
)
=
1
;
if
(
TARGET_IRIX
&&
mips_abi
==
ABI_32
&&
p
->
size
==
1
)
{
fputs
(
"\t.globl "
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
p
->
name
)
;
fputs
(
" .text\n"
,
asm_out_file
)
;
}
else
{
fputs
(
"\t.extern\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
p
->
name
)
;
fprintf
(
asm_out_file
,
", %d\n"
,
p
->
size
)
;
}
}
}
}
}
</s>

Implement TARGET_ASM_FILE_END . When using assembler macros , emit .externs for any small-data variables that turned out to be external .


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : case ARM :: tCMPi8 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : case ARM :: tCMPr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void split_double_mode ( machine_mode mode , rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { machine_mode half_mode ; unsigned int byte ; switch ( mode ) { case E_TImode : half_mode = DImode ; break ; case E_DImode : half_mode = SImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { lo_half [ num ] = adjust_address ( op , half_mode , 0 ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; } else { lo_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , byte ) ; } } } </s>

Split one or more double-mode RTL references into pairs of half-mode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of double-mode RTLs to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s> bool FISCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".byte" ) return parseDirectiveWord ( 1 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".half" ) return parseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".nword" ) return parseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
.
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getLocVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
||
CopyVT
==
MVT
::
f128
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
.
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
bool
RoundAfterCopy
=
false
;
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
RoundAfterCopy
=
(
CopyVT
!=
VA
.
getLocVT
(
)
)
;
}
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
RoundAfterCopy
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
,
dl
)
)
;
if
(
VA
.
isExtInLoc
(
)
&&
VA
.
getValVT
(
)
.
getScalarType
(
)
==
MVT
::
i1
)
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . addRequired < LiveIntervals > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ix86_force_load_from_GOT_p ( rtx x ) { return ( ( TARGET_64BIT || ( ! flag_pic && HAVE_AS_IX86_GOT32X ) ) && ! TARGET_PECOFF && ! TARGET_MACHO && ( ! flag_pic || this_is_asm_operands ) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) && ( ! flag_plt || ( SYMBOL_REF_DECL ( x ) && lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( SYMBOL_REF_DECL ( x ) ) ) ) ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

True if the function symbol operand X should be loaded from GOT . NB : In 32-bit mode , only non-PIC is allowed in inline assembly statements , since a PIC register could not be available at the call site .


"SystemZ does do not have assembler relaxation"

Relax the instruction in the given fragment to the next wider instruction .


<s>
void
X86AsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>


<s> static void aarch64_init_bf16_types ( void ) { aarch64_bf16_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( aarch64_bf16_type_node ) = 16 ; SET_TYPE_MODE ( aarch64_bf16_type_node , BFmode ) ; layout_type ( aarch64_bf16_type_node ) ; lang_hooks . types . register_builtin_type ( aarch64_bf16_type_node , "__bf16" ) ; aarch64_bf16_ptr_type_node = build_pointer_type ( aarch64_bf16_type_node ) ; } </s>

Initialize the backend REAL_TYPE type supporting bfloat types .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool nds32_can_use_bitci_p ( HOST_WIDE_INT ival ) { return ( TARGET_ISA_V3 && ( ival < 0 ) && satisfies_constraint_Iu15 ( gen_int_mode ( ~ ival , SImode ) ) ) ; } </s>

Function to check if 'bitci ' instruction can be used with IVAL .


<s> Instruction * getRoot ( ) { return Root ; } </s>

Similar to getMemoryRoot , but also flushes PendingConstrainedFP ( Strict ) items .


<s> static void mips_multi_write ( void ) { struct mips_multi_member * member ; unsigned int i ; FOR_EACH_VEC_ELT ( mips_multi_members , i , member ) if ( member -> is_label_p ) fprintf ( asm_out_file , "%s\n" , member -> format ) ; else output_asm_insn ( member -> format , member -> operands ) ; } </s>

Write out the asm code for the current multi-insn sequence .


<s> Value * X86TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { return M . getFunction ( "__security_check_cookie" ) ; } return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s> static machine_mode mips_preferred_simd_mode ( machine_mode mode ATTRIBUTE_UNUSED ) { if ( TARGET_PAIRED_SINGLE_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode ; } </s>


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; const TargetRegisterClass * RC = Subtarget . isPPC64 ( ) ? G8RC : GPRC ; unsigned Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; bool LP64 = Subtarget . isPPC64 ( ) ; BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCRpseud ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( PPC :: RLWINM ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( getPPCRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( 1 ) . getImm ( ) ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV32rm : case X86 :: MOV64rm : case X86 :: LD_Fp64m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MOVAPSrm : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 4 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 1 && MI -> getOperand ( 3 ) . getReg ( ) == 0 && MI -> getOperand ( 4 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void DLXMCCodeEmitter :: encodeInstruction ( const MCInst & Inst , raw_ostream & Ostream , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { unsigned Value = getBinaryCodeForInstr ( Inst , Fixups , SubtargetInfo ) ; ++ MCNumEmitted ; for ( int i = ( 4 - 1 ) * 8 ; i >= 0 ; i -= 8 ) Ostream << static_cast < char > ( ( Value >> i ) & 0xff ) ; } </s>

Encode the given Inst to bytes and append to CB .


"Suitable Machine Function for outlining must track liveness"

Optional target hook that returns true if MBB is safe to outline from , and returns any target-specific information in Flags .


<s> static void add_insn_window ( rtx_insn * insn , dispatch_windows * window_list , int num_uops ) { int byte_len = min_insn_size ( insn ) ; int num_insn = window_list -> num_insn ; int imm_size ; sched_insn_info * window = window_list -> window ; enum dispatch_group group = get_insn_group ( insn ) ; enum insn_path path = get_insn_path ( insn ) ; int num_imm_operand ; int num_imm32_operand ; int num_imm64_operand ; if ( ! window_list -> violation && group != disp_cmp && ! fits_dispatch_window ( insn ) ) window_list -> violation = true ; imm_size = get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; window [ num_insn ] . insn = insn ; window [ num_insn ] . byte_len = byte_len ; window [ num_insn ] . group = group ; window [ num_insn ] . path = path ; window [ num_insn ] . imm_bytes = imm_size ; window_list -> window_size += byte_len ; window_list -> num_insn = num_insn + 1 ; window_list -> num_uops = window_list -> num_uops + num_uops ; window_list -> imm_size += imm_size ; window_list -> num_imm += num_imm_operand ; window_list -> num_imm_32 += num_imm32_operand ; window_list -> num_imm_64 += num_imm64_operand ; if ( group == disp_store ) window_list -> num_stores += 1 ; else if ( group == disp_load || group == disp_prefetch ) window_list -> num_loads += 1 ; else if ( group == disp_load_store ) { window_list -> num_stores += 1 ; window_list -> num_loads += 1 ; } } </s>

Add an instruction INSN with NUM_UOPS micro-operations to the dispatch window WINDOW_LIST .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . hasMSInlineAsm ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "sinl" , "sqrtl" , "truncl" } ; const char * const * End = LibCalls + array_lengthof ( LibCalls ) ; MipsTargetLowering :: LTStr Comp ; for ( const char * const * I = LibCalls ; I < End - 1 ; ++ I ) assert ( Comp ( * I , * ( I + 1 ) ) ) ; return std :: binary_search ( LibCalls , End , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s> static bool ix86_check_avx256_register ( const_rtx exp ) { if ( SUBREG_P ( exp ) ) exp = SUBREG_REG ( exp ) ; return ( REG_P ( exp ) && VALID_AVX256_REG_OR_OI_MODE ( GET_MODE ( exp ) ) ) ; } </s>

Check if a 256bit AVX register is referenced inside of EXP .


<s> bool PPCFunctionInfo :: isLiveInZExt ( Register VReg ) const { for ( const std :: pair < Register , ISD :: ArgFlagsTy > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isZExt ( ) ; return false ; } </s>

This function returns true if the specified vreg is a live-in register and zero-extended .


<s> void aarch64_expand_sve_vcond ( machine_mode data_mode , machine_mode cmp_mode , rtx * ops ) { machine_mode pred_mode = aarch64_get_mask_mode ( GET_MODE_NUNITS ( cmp_mode ) , GET_MODE_SIZE ( cmp_mode ) ) . require ( ) ; rtx pred = gen_reg_rtx ( pred_mode ) ; if ( FLOAT_MODE_P ( cmp_mode ) ) { if ( aarch64_expand_sve_vec_cmp_float ( pred , GET_CODE ( ops [ 3 ] ) , ops [ 4 ] , ops [ 5 ] , true ) ) std :: swap ( ops [ 1 ] , ops [ 2 ] ) ; } else aarch64_expand_sve_vec_cmp_int ( pred , GET_CODE ( ops [ 3 ] ) , ops [ 4 ] , ops [ 5 ] ) ; rtvec vec = gen_rtvec ( 3 , pred , ops [ 1 ] , ops [ 2 ] ) ; emit_set_insn ( ops [ 0 ] , gen_rtx_UNSPEC ( data_mode , vec , UNSPEC_SEL ) ) ; } </s>

Expand an SVE vcond pattern with operands OPS . DATA_MODE is the mode of the data being selected and CMP_MODE is the mode of the values being compared .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

"Incorrect array index for MVE_VMOV_q_rr"

Perform target-specific instruction verification .


<s> void LC2200AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( LowerLC2200MachineOperandToMCOperand ( MO , MCOp , * this ) ) TmpInst . addOperand ( MCOp ) ; } EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static rtx ix86_expand_store_builtin ( enum insn_code icode , tree arglist ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; return 0 ; } </s>

Subroutine of ix86_expand_builtin to take care of stores .


<s> static sbitmap rs6000_get_separate_components ( void ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( WORLD_SAVE_P ( info ) ) return NULL ; gcc_assert ( ! ( info -> savres_strategy & SAVE_MULTIPLE ) && ! ( info -> savres_strategy & REST_MULTIPLE ) ) ; cfun -> machine -> n_components = 64 ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; int reg_size = TARGET_32BIT ? 4 : 8 ; int fp_reg_size = 8 ; if ( ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) ) { int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += reg_size ; } } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( ( TARGET_TOC && TARGET_MINIMAL_TOC ) || ( flag_pic == 1 && DEFAULT_ABI == ABI_V4 ) || ( flag_pic && DEFAULT_ABI == ABI_DARWIN ) ) bitmap_clear_bit ( components , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) ) { int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) { if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) && save_reg_p ( regno ) ) bitmap_set_bit ( components , regno ) ; offset += fp_reg_size ; } } if ( info -> lr_save_p && ! ( flag_pic && ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) ) && ( info -> savres_strategy & SAVE_INLINE_GPRS ) && ( info -> savres_strategy & REST_INLINE_GPRS ) && ( info -> savres_strategy & SAVE_INLINE_FPRS ) && ( info -> savres_strategy & REST_INLINE_FPRS ) && ( info -> savres_strategy & SAVE_INLINE_VRS ) && ( info -> savres_strategy & REST_INLINE_VRS ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; if ( IN_RANGE ( offset , - 0x8000 , 0x7fff ) ) bitmap_set_bit ( components , 0 ) ; } if ( cfun -> machine -> save_toc_in_prologue ) bitmap_set_bit ( components , 2 ) ; return components ; } </s>


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == ISD :: ADD && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::ADD ISD::POST_INC ISD::POST_DEC


<s> static rtx iq2000_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( ( ( GET_MODE_CLASS ( mode ) != MODE_INT || GET_MODE_SIZE ( mode ) >= 4 ) ? mode : SImode ) , GP_RETURN ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static void mips_emit_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 , bool need_eq_ne_p ) { rtx cmp_op0 = * op0 ; rtx cmp_op1 = * op1 ; if ( GET_MODE_CLASS ( GET_MODE ( * op0 ) ) == MODE_INT ) { if ( ! need_eq_ne_p && * op1 == const0_rtx ) ; else if ( * code == EQ || * code == NE ) { if ( need_eq_ne_p ) { * op0 = mips_zero_if_equal ( cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; } else * op1 = force_reg ( GET_MODE ( cmp_op0 ) , cmp_op1 ) ; } else if ( ! need_eq_ne_p && TARGET_CB_MAYBE ) { bool swap = false ; switch ( * code ) { case LE : swap = true ; * code = GE ; break ; case GT : swap = true ; * code = LT ; break ; case LEU : swap = true ; * code = GEU ; break ; case GTU : swap = true ; * code = LTU ; break ; case GE : case LT : case GEU : case LTU : break ; default : gcc_unreachable ( ) ; } * op1 = force_reg ( GET_MODE ( cmp_op0 ) , cmp_op1 ) ; if ( swap ) { rtx tmp = * op1 ; * op1 = * op0 ; * op0 = tmp ; } } else { bool invert = false ; * op0 = gen_reg_rtx ( GET_MODE ( cmp_op0 ) ) ; mips_emit_int_order_test ( * code , & invert , * op0 , cmp_op0 , cmp_op1 ) ; * code = ( invert ? EQ : NE ) ; * op1 = const0_rtx ; } } else if ( ALL_FIXED_POINT_MODE_P ( GET_MODE ( cmp_op0 ) ) ) { * op0 = gen_rtx_REG ( CCDSPmode , CCDSP_CC_REGNUM ) ; mips_emit_binary ( * code , * op0 , cmp_op0 , cmp_op1 ) ; * code = NE ; * op1 = const0_rtx ; } else { enum rtx_code cmp_code ; cmp_code = * code ; if ( ISA_HAS_CCF ) { * code = NE ; * op0 = gen_reg_rtx ( CCFmode ) ; } else { * code = mips_reversed_fp_cond ( & cmp_code ) ? EQ : NE ; if ( ISA_HAS_8CC ) * op0 = mips_allocate_fcc ( CCmode ) ; else * op0 = gen_rtx_REG ( CCmode , FPSW_REGNUM ) ; } * op1 = const0_rtx ; mips_emit_binary ( cmp_code , * op0 , cmp_op0 , cmp_op1 ) ; } } </s>

Convert a comparison into something that can be used in a branch or conditional move . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update * CODE , * OP0 and * OP1 so that they describe the final comparison . If NEED_EQ_NE_P , then only EQ or NE comparisons against zero are possible , otherwise any standard branch condition can be used . The standard branch conditions are : - EQ or NE between two registers . - any comparison between a register and zero .


<s> unsigned constant_generates_xxspltiw ( vec_const_128bit_type * vsx_const ) { if ( ! TARGET_SPLAT_WORD_CONSTANT || ! TARGET_PREFIXED || ! TARGET_VSX ) return 0 ; if ( ! vsx_const -> all_words_same ) return 0 ; if ( vsx_const -> all_bytes_same ) return 0 ; if ( vsx_const -> all_half_words_same ) { unsigned short h_word = vsx_const -> half_words [ 0 ] ; short sign_h_word = ( ( h_word & 0xffff ) ^ 0x8000 ) - 0x8000 ; if ( EASY_VECTOR_15 ( sign_h_word ) ) return 0 ; } unsigned int word = vsx_const -> words [ 0 ] ; int sign_word = ( ( word & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( EASY_VECTOR_15 ( sign_word ) ) return 0 ; return vsx_const -> words [ 0 ] ; } </s>

Determine if a vector constant can be loaded with XXSPLTIW . Return zero if the XXSPLTIW instruction can not be used . Otherwise return the immediate value to be used with the XXSPLTIW instruction .


<s> static int ix86_cmp_code_to_pcmp_immediate ( enum rtx_code code , machine_mode mode ) { if ( FLOAT_MODE_P ( mode ) ) return ix86_fp_cmp_code_to_pcmp_immediate ( code ) ; return ix86_int_cmp_code_to_pcmp_immediate ( code ) ; } </s>

Return immediate value to be used in UNSPEC_PCMP for comparison CODE in MODE .


<s> size_t AArch64CA53ErratumStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> bool ExpandPseudo :: expand ( ) { bool Expanded = false ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BBEnd = MF . end ( ) ; BB != BBEnd ; ++ BB ) for ( Iter I = BB -> begin ( ) , End = BB -> end ( ) ; I != End ; ) Expanded |= expandInstr ( * BB , I ++ ) ; return Expanded ; } </s>

expand - Expand a record into a set of elements if possible .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass || RC == ARM :: GPRnopcRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass ARM::GPRnopcRegisterClass ARM::t2STRi12 0 ARM


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; return CSR_O32_SaveList ; } </s>


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"argument of type %qT not permitted with -mgeneral-regs-only"

Return true if an argument whose type is TYPE , or mode is MODE , is suitable for passing or returning in VFP registers for the PCS variant selected . If it is , then * BASE_MODE is updated to contain a machine mode describing each element of the argument 's type and * COUNT to hold the number of such elements .


This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


<s> static inline void desc_abi ( unsigned char abi , unsigned char context , struct unw_state_record * sr ) { sr -> unwabi = ( abi << 8 ) | context ; } </s>


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
(
unsigned
)
Fixup
.
getKind
(
)
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


<s> void aarch64_init_fcmla_laneq_builtins ( void ) { unsigned int i = 0 ; for ( i = 0 ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_lookup_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_lookup_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_std_type ( SImode , qualifier_lane_pair_index ) ; tree ftype = build_function_type_list ( argtype , argtype , argtype , quadtype , lanetype , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , d -> mode ) ; tree fndecl = aarch64_general_add_builtin ( d -> name , ftype , d -> fcode , attrs ) ; aarch64_builtin_decls [ d -> fcode ] = fndecl ; } } </s>

Due to the architecture not providing lane variant of the lane instructions for fcmla we ca n't use the standard simd builtin expansion code , but we still want the majority of the validation that would normally be done .


<s> bool nds32_n9_3r2w_mm_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , 0 ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , 1 ) ) ; return ( n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg1 ) || n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg ) ; } </s>


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || N -> getOpcode ( ) == X86ISD :: TC_RETURN ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , NULL , 0 , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , NULL , 0 , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> const MCPhysReg * F2003fRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_NoRegs_SaveList ; } </s>


<s> static bool ix86_member_type_forces_blk ( const_tree field , machine_mode mode ) { return ( mode == XFmode && ( TREE_CODE ( DECL_FIELD_CONTEXT ( field ) ) == UNION_TYPE || TREE_CODE ( DECL_FIELD_CONTEXT ( field ) ) == QUAL_UNION_TYPE ) ) ; } </s>

Return true if a structure , union or array with MODE containing FIELD should be accessed using BLKmode .


<s> static inline int arm_const_inline_cost ( enum rtx_code code , rtx val ) { return arm_gen_constant ( code , SImode , NULL_RTX , INTVAL ( val ) , NULL_RTX , NULL_RTX , 1 , 0 ) ; } </s>


<s> void Cpu0InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>