<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned DLXRegisterInfo :: getRARegister ( ) const { return DLX :: RA ; } </s>

This method should return the register where the return address can be found .


<s> bool csky_emit_compare_float ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx cc_reg = gen_rtx_REG ( CCmode , CSKY_CC_REGNUM ) ; bool invert ; machine_mode mode = GET_MODE ( op1 ) ; if ( op1 != CONST0_RTX ( mode ) ) op1 = force_reg ( mode , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; break ; case GT : case LT : case LE : if ( op1 == CONST0_RTX ( mode ) && TARGET_SUPPORT_FPV2 ) op1 = force_reg ( mode , op1 ) ; break ; case ORDERED : code = UNORDERED ; invert = true ; break ; default : break ; } emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 ) ) ) ; return invert ; } </s>

Emit a comparison insn for float values . Return true if the comparison is inverted .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> StringRef AArch64NamedImmMapper :: toString ( uint32_t Value , bool & Valid ) const { for ( unsigned i = 0 ; i < NumMappings ; ++ i ) { if ( Mappings [ i ] . Value == Value ) { Valid = true ; return Mappings [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


"********** AArch64 Conditional Compares **********\n"

runOnMachineFunction - Emit the function body .


<s> static HOST_WIDE_INT aarch64_estimated_poly_value ( poly_int64 val , poly_value_estimate_kind kind = POLY_VALUE_LIKELY ) { enum aarch64_sve_vector_bits_enum width_source = aarch64_tune_params . sve_width ; if ( width_source == SVE_SCALABLE ) switch ( kind ) { case POLY_VALUE_MIN : case POLY_VALUE_LIKELY : return val . coeffs [ 0 ] ; case POLY_VALUE_MAX : return val . coeffs [ 0 ] + val . coeffs [ 1 ] * 15 ; } HOST_WIDE_INT over_128 = width_source - 128 ; return val . coeffs [ 0 ] + val . coeffs [ 1 ] * over_128 / 128 ; } </s>

Implement TARGET_ESTIMATED_POLY_VALUE . Look into the tuning structure for an estimate . KIND specifies the type of requested estimate : min , max or likely . For cores with a known SVE width all three estimates are the same . For generic SVE tuning we want to distinguish the maximum estimate from the minimum and likely ones . The likely estimate is the same as the minimum in that case to give a conservative behavior of auto-vectorizing with SVE when it is a win even for 128-bit SVE . When SVE width information is available VAL.coeffs [ 1 ] is multiplied by the number of VQ chunks over the initial Advanced SIMD 128 bits .


<s> void X86AsmPrinter :: emitFunctionBodyEnd ( ) { if ( EmitFPOData ) { if ( auto * XTS = static_cast < X86TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) XTS -> emitFPOEndProc ( ) ; } } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> static void enable_mask_for_builtins ( struct builtin_description * desc , int size , enum rs6000_builtins start , enum rs6000_builtins end ) { int i ; for ( i = 0 ; i < size ; ++ i ) if ( desc [ i ] . code == start ) break ; if ( i == size ) return ; for ( ; i < size ; ++ i ) { desc [ i ] . mask = target_flags ; if ( desc [ i ] . code == end ) break ; } } </s>

Search through a set of builtins and enable the mask bits . DESC is an array of builtins . SIZE is the total number of builtins . START is the builtin enum at which to start . END is the builtin enum at which to end .


<s> static bool hppa_rtx_costs ( rtx x , int code , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int factor ; switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == 0 ) * total = 0 ; else if ( INT_14_BITS ( x ) ) * total = 1 ; else * total = 2 ; return true ; case HIGH : * total = 2 ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = 4 ; return true ; case CONST_DOUBLE : if ( ( x == CONST0_RTX ( DFmode ) || x == CONST0_RTX ( SFmode ) ) && outer_code != SET ) * total = 0 ; else * total = 8 ; return true ; case MULT : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( 3 ) ; return true ; } factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / 4 ; if ( factor == 0 ) factor = 1 ; if ( TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT ) * total = factor * factor * COSTS_N_INSNS ( 8 ) ; else * total = factor * factor * COSTS_N_INSNS ( 20 ) ; return true ; case DIV : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( 14 ) ; return true ; } case UDIV : case MOD : case UMOD : factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / 4 ; if ( factor == 0 ) factor = 1 ; * total = factor * factor * COSTS_N_INSNS ( 60 ) ; return true ; case PLUS : case MINUS : if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { * total = COSTS_N_INSNS ( 3 ) ; return true ; } factor = GET_MODE_SIZE ( GET_MODE ( x ) ) / UNITS_PER_WORD ; if ( factor == 0 ) factor = 1 ; * total = factor * COSTS_N_INSNS ( 1 ) ; return true ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( 1 ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> static int mips_symbol_insns ( enum mips_symbol_type type , machine_mode mode ) { if ( mode != MAX_MACHINE_MODE && MSA_SUPPORTED_MODE_P ( mode ) ) return 0 ; return mips_symbol_insns_1 ( type , mode ) * ( TARGET_MIPS16 ? 2 : 1 ) ; } </s>

Return the number of instructions needed to load a symbol of the given type into a register . If valid in an address , the same number of instructions are needed for loads and stores . Treat extended mips16 instructions as two instructions .


<s> bool enableInterleavedAccessVectorization ( ) { return true ; } </s>

Enable matching of interleaved access groups .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) && MMI . usePreciseUnwindInfo ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } if ( DwarfCFI && ! hasFP ( MF ) ) { int CFAOffset = Amount ; if ( ! MMI . usePreciseUnwindInfo ( ) ) CFAOffset += InternalAmt ; CFAOffset = isDestroy ? - CFAOffset : CFAOffset ; BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CFAOffset ) ) ; } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
0
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
unsigned
DestReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
0
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( 0 ) ; break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : SubIdx = 1 ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : SubIdx = 3 ; break ; case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : SubIdx = 4 ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> void scalar_chain :: replace_with_subreg_in_insn ( rtx_insn * insn , rtx reg , rtx new_reg ) { replace_with_subreg ( single_set ( insn ) , reg , new_reg ) ; } </s>

Replace REG in INSN with a V2DI subreg of NEW_REG .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
else
{
const
TargetRegisterInfo
*
RegInfo
=
st
.
getRegisterInfo
(
)
;
if
(
MBB
.
computeRegisterLiveness
(
RegInfo
,
ARM
::
CPSR
,
I
)
==
MachineBasicBlock
::
LQR_Dead
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVSr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
->
addRegisterDead
(
ARM
::
CPSR
,
RegInfo
)
;
return
;
}
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARMCC::AL
ARM::CPSR
ARM::tMOVSr
ARM::CPSR
ARM::tPUSH
ARMCC::AL
ARM::tPOP
ARMCC::AL


<s> static rtx rs6000_mixed_function_arg ( machine_mode mode , const_tree type , int align_words ) { int n_units ; int i , k ; rtx rvec [ GP_ARG_NUM_REG + 1 ] ; if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; n_units = rs6000_arg_size ( mode , type ) ; if ( n_units == 0 || ( n_units == 1 && mode != BLKmode ) ) return gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; k = 0 ; if ( align_words + n_units > GP_ARG_NUM_REG ) rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; i = 0 ; do { rtx r = gen_rtx_REG ( SImode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * 4 ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_units != 0 ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( k , rvec ) ) ; } </s>

Determine where to place an argument in 64-bit mode with 32-bit ABI .


<s> void TOYFrameLowering :: emitPrologue ( MachineFunction & MF ) const { const TOYInstrInfo & TII = * static_cast < const TOYInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int StackSize = ( int ) MFI -> getStackSize ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: ADDri ) , TOY :: SP ) . addReg ( TOY :: SP ) . addImm ( StackSize ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

TOY TOY TOY TOY TOY::ADDri TOY::SP TOY::SP


<s> void build_mask64_2_operands ( rtx in , rtx * out ) { unsigned HOST_WIDE_INT c , lsb , m1 , m2 ; int shift ; gcc_assert ( GET_CODE ( in ) == CONST_INT ) ; c = INTVAL ( in ) ; if ( c & 1 ) { c = ~ c ; lsb = c & - c ; m1 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = 0 ; while ( ( lsb >>= 1 ) != 0 ) shift ++ ; m1 <<= 64 - shift ; m1 = ~ m1 ; m2 = ~ c ; } else { lsb = c & - c ; m2 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = 0 ; while ( ( lsb >>= 1 ) != 0 ) shift ++ ; m1 = ~ c ; m1 >>= shift ; m1 = ~ m1 ; } out [ 0 ] = GEN_INT ( 64 - shift ) ; out [ 1 ] = GEN_INT ( m1 ) ; out [ 2 ] = GEN_INT ( shift ) ; out [ 3 ] = GEN_INT ( m2 ) ; } </s>

Generates shifts and masks for a pair of rldicl or rldicr insns to implement ANDing by the mask IN .


<s> bool isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == MVT :: f64 && X86ScalarSSEf64 ) || ( VT == MVT :: f32 && X86ScalarSSEf32 ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) GlobalBaseReg = PPC :: R30 ; else GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; if ( PPCSubTarget -> isTargetELF ( ) ) { unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: GetGBRO ) , TempReg ) . addReg ( GlobalBaseReg ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC MVT::i32 PPC PPC::R30 PPC::GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::GPRCRegClass PPC::GetGBRO PPC::UpdateGBR PPC PPC::G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> bool KudeyarFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static rtx arm_gen_store_multiple_1 ( int count , int * regs , rtx * mems , rtx basereg , HOST_WIDE_INT wback_offset ) { int i = 0 , j ; rtx result ; if ( GET_CODE ( basereg ) == PLUS ) basereg = XEXP ( basereg , 0 ) ; if ( ! multiple_operation_profitable_p ( false , count , 0 ) ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( mems [ i ] , gen_rtx_REG ( SImode , regs [ i ] ) ) ; if ( wback_offset != 0 ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != 0 ? 1 : 0 ) ) ) ; if ( wback_offset != 0 ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) XVECEXP ( result , 0 , i ) = gen_rtx_SET ( mems [ j ] , gen_rtx_REG ( SImode , regs [ j ] ) ) ; return result ; } </s>

Generate a store-multiple instruction . COUNT is the number of stores in the instruction ; REGS and MEMS are arrays containing the operands . BASEREG is the base register to be used in addressing the memory operands . WBACK_OFFSET is nonzero if the instruction should update the base register .


<s>
static
void
ia64_output_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
int
mask
,
grsave
,
grsave_prev
;
if
(
current_frame_info
.
need_regstk
)
fprintf
(
file
,
"\t.regstk %d, %d, %d, %d\n"
,
current_frame_info
.
n_input_regs
,
current_frame_info
.
n_local_regs
,
current_frame_info
.
n_output_regs
,
current_frame_info
.
n_rotate_regs
)
;
if
(
!
flag_unwind_tables
&&
(
!
flag_exceptions
||
USING_SJLJ_EXCEPTIONS
)
)
return
;
mask
=
0
;
grsave
=
grsave_prev
=
0
;
if
(
current_frame_info
.
reg_save_b0
!=
0
)
{
mask
|=
8
;
grsave
=
grsave_prev
=
current_frame_info
.
reg_save_b0
;
}
if
(
current_frame_info
.
reg_save_ar_pfs
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
reg_save_ar_pfs
==
grsave_prev
+
1
)
)
{
mask
|=
4
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
reg_save_ar_pfs
;
grsave_prev
=
current_frame_info
.
reg_save_ar_pfs
;
}
if
(
current_frame_info
.
reg_fp
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
reg_fp
==
grsave_prev
+
1
)
)
{
mask
|=
2
;
if
(
grsave_prev
==
0
)
grsave
=
HARD_FRAME_POINTER_REGNUM
;
grsave_prev
=
current_frame_info
.
reg_fp
;
}
if
(
current_frame_info
.
reg_save_pr
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
reg_save_pr
==
grsave_prev
+
1
)
)
{
mask
|=
1
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
reg_save_pr
;
}
if
(
mask
&&
TARGET_GNU_AS
)
fprintf
(
file
,
"\t.prologue %d, %d\n"
,
mask
,
ia64_dbx_register_number
(
grsave
)
)
;
else
fputs
(
"\t.prologue\n"
,
file
)
;
if
(
current_frame_info
.
spill_cfa_off
!=
16
)
fprintf
(
file
,
"\t.spill %ld\n"
,
(
long
)
(
current_frame_info
.
spill_cfa_off
+
current_frame_info
.
spill_size
)
)
;
}
</s>


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static HOST_WIDE_INT loongarch_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> static void aarch64_emit_store_exclusive ( machine_mode mode , rtx bval , rtx rval , rtx mem , rtx model_rtx ) { emit_insn ( gen_aarch64_store_exclusive ( mode , bval , rval , mem , model_rtx ) ) ; } </s>


<s> SMLoc getOffsetOfLoc ( ) const { return OffsetOfLoc ; } </s>

getOffsetOfLoc - Get the location of the offset operator .


<s> static inline int abi_default_cpu_arch ( struct loongarch_abi abi ) { switch ( abi . base ) { case ABI_BASE_LP64D : case ABI_BASE_LP64F : case ABI_BASE_LP64S : if ( abi . ext == ABI_EXT_BASE ) return CPU_LOONGARCH64 ; } gcc_unreachable ( ) ; } </s>

The behavior of this function should be consistent with config.gcc .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> isTargetNaCl ( ) && ( N -> getOpcode ( ) == X86ISD :: CALL || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool CSKYAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < CSKYSubtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
aarch64_simd_lane_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
,
const_tree
exp
)
{
HOST_WIDE_INT
lane
;
gcc_assert
(
CONST_INT_P
(
operand
)
)
;
lane
=
INTVAL
(
operand
)
;
if
(
lane
<
low
||
lane
>=
high
)
{
if
(
exp
)
error
(
"%Klane %wd out of range %wd - %wd"
,
exp
,
lane
,
low
,
high
1
)
;
else
error
(
"lane %wd out of range %wd - %wd"
,
lane
,
low
,
high
1
)
;
}
}
</s>

Bounds-check lanes . Ensure OPERAND lies between LOW ( inclusive ) and HIGH ( exclusive ) .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isABI_N64 ( ) || Subtarget . isABI_N32 ( ) ) ReginfoSection = getContext ( ) . getELFSection ( ".MIPS.options" , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) ) ; else ReginfoSection = getContext ( ) . getELFSection ( ".reginfo" , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) ) ; if ( Subtarget . isTargetNaCl ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , ELF :: SHT_INIT_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , ELF :: SHT_FINI_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } } </s>

This method must be called before any actual lowering is done .


<s>
void
AArch64FrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
AArch64RegisterInfo
*
RegInfo
=
static_cast
<
const
AArch64RegisterInfo
*
>
(
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
)
;
DebugLoc
DL
;
bool
IsTailCallReturn
=
false
;
if
(
MBB
.
end
(
)
!=
MBBI
)
{
DL
=
MBBI
->
getDebugLoc
(
)
;
unsigned
RetOpcode
=
MBBI
->
getOpcode
(
)
;
IsTailCallReturn
=
RetOpcode
==
AArch64
::
TCRETURNdi
||
RetOpcode
==
AArch64
::
TCRETURNri
;
}
int
NumBytes
=
MFI
->
getStackSize
(
)
;
const
AArch64FunctionInfo
*
AFI
=
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
if
(
MF
.
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
;
uint64_t
ArgumentPopSize
=
0
;
if
(
IsTailCallReturn
)
{
MachineOperand
&
StackAdjust
=
MBBI
->
getOperand
(
1
)
;
ArgumentPopSize
=
StackAdjust
.
getImm
(
)
;
}
else
{
ArgumentPopSize
=
AFI
->
getArgumentStackToRestore
(
)
;
}
NumBytes
+=
ArgumentPopSize
;
unsigned
NumRestores
=
0
;
MachineBasicBlock
::
iterator
LastPopI
=
MBB
.
getFirstTerminator
(
)
;
const
MCPhysReg
*
CSRegs
=
RegInfo
->
getCalleeSavedRegs
(
&
MF
)
;
if
(
LastPopI
!=
MBB
.
begin
(
)
)
{
do
{
++
NumRestores
;
LastPopI
;
}
while
(
LastPopI
!=
MBB
.
begin
(
)
&&
isCSRestore
(
LastPopI
,
CSRegs
)
)
;
if
(
!
isCSRestore
(
LastPopI
,
CSRegs
)
)
{
++
LastPopI
;
NumRestores
;
}
}
NumBytes
-=
NumRestores
*
16
;
assert
(
NumBytes
>=
0
&&
"Negative stack allocation size!?"
)
;
if
(
!
hasFP
(
MF
)
)
{
if
(
!
canUseRedZone
(
MF
)
)
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
NumBytes
,
TII
)
;
return
;
}
if
(
NumBytes
||
MFI
->
hasVarSizedObjects
(
)
)
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
FP
,
(
NumRestores
1
)
*
16
,
TII
,
MachineInstr
::
NoFlags
)
;
}
</s>


<s> static int ia64_unspec_may_trap_p ( const_rtx x , unsigned flags ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_LDA : case UNSPEC_LDS : case UNSPEC_LDSA : case UNSPEC_LDCCLR : case UNSPEC_CHKACLR : case UNSPEC_CHKS : return may_trap_p_1 ( XVECEXP ( x , 0 , 0 ) , flags ) ; } return default_unspec_may_trap_p ( x , flags ) ; } </s>

Implement targetm.unspec_may_trap_p hook .


<s> bool ARMSubtarget :: enableMachinePipeliner ( ) const { return getSchedModel ( ) . hasInstrSchedModel ( ) && useMachinePipeliner ( ) ; } </s>

True if the subtarget should run MachinePipeliner .


<s> bool ix86_binary_operator_ok ( enum rtx_code code , machine_mode mode , rtx operands [ 3 ] ) { rtx dst = operands [ 0 ] ; rtx src1 = operands [ 1 ] ; rtx src2 = operands [ 2 ] ; if ( ( MEM_P ( src1 ) || bcst_mem_operand ( src1 , mode ) ) && ( MEM_P ( src2 ) || bcst_mem_operand ( src2 , mode ) ) ) return false ; if ( ix86_swap_binary_operands_p ( code , mode , operands ) ) std :: swap ( src1 , src2 ) ; if ( MEM_P ( dst ) && ! rtx_equal_p ( dst , src1 ) ) return false ; if ( CONSTANT_P ( src1 ) ) return false ; if ( MEM_P ( src1 ) && ! rtx_equal_p ( dst , src1 ) ) return ( code == AND && ( mode == HImode || mode == SImode || ( TARGET_64BIT && mode == DImode ) ) && satisfies_constraint_L ( src2 ) ) ; return true ; } </s>

Return TRUE or FALSE depending on whether the binary operator meets the appropriate constraints .


"Can only insert epilog into returning blocks"


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a vector base in a gather-style address . Return its type on success , otherwise return NUM_VECTOR_TYPES .


Define the macros that we always expect to have on AArch64 .


<s>
const
MCFixupKindInfo
&
OR1KAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
OR1K
::
NumTargetFixupKinds
]
=
{
{
"fixup_OR1K_NONE"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_32"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_8"
,
0
,
8
,
0
}
,
{
"fixup_OR1K_LO16_INSN"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_HI16_INSN"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_REL26"
,
0
,
26
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_PCREL8"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_GOTPC_HI16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_GOTPC_LO16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_GOT16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_PLT26"
,
0
,
26
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_OR1K_GOTOFF_HI16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_GOTOFF_LO16"
,
0
,
16
,
0
}
,
{
"fixup_OR1K_COPY"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_GLOB_DAT"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_JMP_SLOT"
,
0
,
32
,
0
}
,
{
"fixup_OR1K_RELATIVE"
,
0
,
32
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"Only FP0 could be passed as an argument"


<s> void MipsTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , PPC :: G8RCRegisterClass ) ; return std :: make_pair ( 0U , PPC :: GPRCRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , PPC :: F4RCRegisterClass ) ; else if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , PPC :: F8RCRegisterClass ) ; break ; case 'v' : return std :: make_pair ( 0U , PPC :: VRRCRegisterClass ) ; case 'y' : return std :: make_pair ( 0U , PPC :: CRRCRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> SDValue AArch64TargetLowering :: getGOT ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { LLVM_DEBUG ( dbgs ( ) << "AArch64TargetLowering::getGOT\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty , DAG , AArch64II :: MO_GOT | Flags ) ; return DAG . getNode ( AArch64ISD :: LOADgot , DL , Ty , GotAddr ) ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void mips_emit_save_slot_move ( rtx dest , rtx src , rtx temp ) { unsigned int regno ; rtx mem ; if ( REG_P ( src ) ) { regno = REGNO ( src ) ; mem = dest ; } else { regno = REGNO ( dest ) ; mem = src ; } if ( regno == cfun -> machine -> global_pointer && ! mips_must_initialize_gp_p ( ) ) { if ( TARGET_64BIT ) emit_insn ( gen_move_gpdi ( dest , src ) ) ; else emit_insn ( gen_move_gpsi ( dest , src ) ) ; return ; } if ( regno == HI_REGNUM ) { if ( REG_P ( dest ) ) { mips_emit_move ( temp , src ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthidi_ti ( gen_rtx_REG ( TImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( DImode , LO_REGNUM ) ) ) ; else emit_insn ( gen_mthisi_di ( gen_rtx_REG ( DImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( SImode , LO_REGNUM ) ) ) ; } else { if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( temp , gen_rtx_REG ( TImode , MD_REG_FIRST ) ) ) ; else emit_insn ( gen_mfhisi_di ( temp , gen_rtx_REG ( DImode , MD_REG_FIRST ) ) ) ; mips_emit_move ( dest , temp ) ; } } else if ( mips_direct_save_slot_move_p ( regno , mem , mem == src ) ) mips_emit_move ( dest , src ) ; else { gcc_assert ( ! reg_overlap_mentioned_p ( dest , temp ) ) ; mips_emit_move ( temp , src ) ; mips_emit_move ( dest , temp ) ; } if ( MEM_P ( dest ) ) mips_set_frame_expr ( mips_frame_set ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST , given that one of them is a register save slot and that the other is a register . TEMP is a temporary GPR of the same mode that is available if need be .


<s> const char * ix86_output_indirect_function_return ( rtx ret_op ) { if ( cfun -> machine -> function_return_type != indirect_branch_keep ) { char thunk_name [ 32 ] ; enum indirect_thunk_prefix need_prefix = indirect_thunk_need_prefix ( current_output_insn ) ; unsigned int regno = REGNO ( ret_op ) ; gcc_assert ( regno == CX_REG ) ; if ( cfun -> machine -> function_return_type != indirect_branch_thunk_inline ) { bool need_thunk = ( cfun -> machine -> function_return_type == indirect_branch_thunk ) ; indirect_thunk_name ( thunk_name , regno , need_prefix , true ) ; if ( need_thunk ) { indirect_return_via_cx = true ; indirect_thunks_used |= 1 << CX_REG ; } fprintf ( asm_out_file , "\tjmp\t%s\n" , thunk_name ) ; } else output_indirect_thunk ( regno ) ; return "" ; } else return "%!jmp\t%A0" ; } </s>

Output indirect function return . RET_OP is the function return target .


<s> unsigned internalKnownBits ( ) const { return Unalign ? Unalign : KnownBits ; } </s>

Compute the number of known offset bits internally to this block .


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != 0 ) { Amount = alignTo ( Amount , getStackAlignment ( ) ) ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

ARM 0 ARM::ADJCALLSTACKDOWN ARM::tADJCALLSTACKDOWN ARM::ADJCALLSTACKUP ARM::tADJCALLSTACKUP


<s> MachineBasicBlock :: iterator ARMBaseInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { MachineInstrBuilder MIB ; MachineBasicBlock :: iterator CallPt ; unsigned Opc ; bool isThumb = Subtarget . isThumb ( ) ; if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( ARMCC :: AL ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? ARM :: tBL : ARM :: BL ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( ARMCC :: AL ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; It = MBB . insert ( It , CallMIB ) ; return It ; } </s>

Insert a call to an outlined function into the program .

ARM ARM ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL ARM::tBL ARM::BL ARMCC::AL


<s> void ix86_expand_floorceil ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xi , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xi = gen_reg_rtx ( mode == DFmode ? DImode : SImode ) ; expand_fix ( xi , res , 0 ) ; expand_float ( xa , xi , 0 ) ; one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , do_floor ? MINUS : PLUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) ix86_sse_copysign_to_positive ( res , res , force_reg ( mode , operand1 ) , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> void AArch64PassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; if ( ! IsOptNone ) { addPass ( createAArch64PostLegalizerCombiner ( IsOptNone ) ) ; if ( EnableGISelLoadStoreOptPostLegal ) addPass ( new LoadStoreOpt ( ) ) ; } addPass ( createAArch64PostLegalizerLowering ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


<s> bool X86FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && ! MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
getParser
(
)
.
setParsingInlineAsm
(
false
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
getParser
(
)
.
setParsingInlineAsm
(
true
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , 0 , "_GLOBAL_OFFSET_TABLE_" ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; ARMConstantPoolValue * CPV = ARMConstantPoolConstant :: Create ( GV , Id ) ; unsigned Align = TM -> getTargetData ( ) -> getPrefTypeAlignment ( GV -> getType ( ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM 0 ARM ARM 0 "_GLOBAL_OFFSET_TABLE_" ARM ARM ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0


";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n"


<s> static bool x86_can_output_mi_thunk ( const_tree , HOST_WIDE_INT , HOST_WIDE_INT vcall_offset , const_tree function ) { if ( TARGET_64BIT ) return true ; if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < 3 ) return true ; if ( vcall_offset ) return false ; if ( flag_pic && ! targetm . binds_local_p ( function ) ) return false ; return true ; } </s>

Determine whether x86_output_mi_thunk can succeed .


<s> PPCSubtarget :: PPCSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const PPCTargetMachine & TM ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , IsPPC64 ( TargetTriple . getArch ( ) == Triple :: ppc64 || TargetTriple . getArch ( ) == Triple :: ppc64le ) , TM ( TM ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( * this ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
GlobalTLSAddress
:
assert
(
0
&&
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerCONSTANTPOOL
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
CALL
:
return
LowerCALL
(
Op
,
DAG
)
;
case
ISD
::
RET
:
return
LowerRET
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


Maybe decorate and get a new identifier for the DECL of a stdcall or fastcall function . The original identifier is supplied in ID .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const unsigned ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: GP , Mips :: SP , Mips :: FP , Mips :: RA , 0 } ; static const unsigned ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: GP_64 , Mips :: SP_64 , Mips :: FP_64 , Mips :: RA_64 , 0 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( const unsigned * Reg = ReservedCPURegs ; * Reg ; ++ Reg ) Reserved . set ( * Reg ) ; if ( Subtarget . hasMips64 ( ) ) { for ( const unsigned * Reg = ReservedCPU64Regs ; * Reg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: AFGR64RegisterClass -> begin ( ) ; Reg != Mips :: AFGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegisterClass -> begin ( ) ; Reg != Mips :: CPU64RegsRegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegisterClass -> begin ( ) ; Reg != Mips :: FGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool SystemZInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isTerminator ( ) ) return false ; if ( MCID . isBranch ( ) && ! MCID . isBarrier ( ) ) return true ; if ( ! MCID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return Subtarget . inMips16Mode ( ) ? nullptr : & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool targetHandlesStackFrameRounding ( ) const override { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s> static int sh_round_reg ( const CUMULATIVE_ARGS & cum , machine_mode mode ) { return ( ( ( TARGET_ALIGN_DOUBLE || ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && ( mode == DFmode || mode == DCmode ) && cum . arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( mode ) ) ) && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_WORD ) ? ( cum . arg_count [ ( int ) GET_SH_ARG_CLASS ( mode ) ] + ( cum . arg_count [ ( int ) GET_SH_ARG_CLASS ( mode ) ] & 1 ) ) : cum . arg_count [ ( int ) GET_SH_ARG_CLASS ( mode ) ] ) ; } </s>

Round a register number up to a proper boundary for an arg of mode MODE . The SH does n't care about double alignment , so we only round doubles to even regs when asked to explicitly .


<s>
SDValue
TeeRISCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
MF
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_TeeRISC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
TeeRISC
::
R1
,
MVT
::
i32
)
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
RVLocs
[
i
]
.
getValVT
(
)
!=
RVLocs
[
i
]
.
getLocVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
dl
,
RVLocs
[
i
]
.
getLocVT
(
)
,
Val
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
TeeRISC_ISD
::
RET
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
MachineBasicBlock
*
FISCTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
assert
(
MI
->
getOpcode
(
)
==
FISC
::
Select
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
ThisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
Copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
Copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
Copy0MBB
)
;
F
->
insert
(
I
,
Copy1MBB
)
;
Copy1MBB
->
splice
(
Copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
Copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
Copy0MBB
)
;
BB
->
addSuccessor
(
Copy1MBB
)
;
BuildMI
(
BB
,
DL
,
TII
.
get
(
FISC
::
Bcc
)
)
.
addOperand
(
MI
->
getOperand
(
3
)
)
.
addMBB
(
Copy1MBB
,
FISCII
::
MO_CALL19
)
;
BB
=
Copy0MBB
;
BB
->
addSuccessor
(
Copy1MBB
)
;
BB
=
Copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
DL
,
TII
.
get
(
FISC
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
Copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
ThisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned getNumFixupKinds ( ) const override { return X86 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_RegMask ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86TargetLowering :: hasStackProbeSymbol ( MachineFunction & MF ) const { return ! getStackProbeSymbolName ( MF ) . empty ( ) ; } </s>

Returns true if stack probing through a function call is requested .


<s> void aarch64_post_cfi_startproc ( FILE * f , tree ignored ATTRIBUTE_UNUSED ) { if ( cfun -> machine -> frame . laid_out && aarch64_return_address_signing_enabled ( ) && aarch64_ra_sign_key == AARCH64_KEY_B ) asm_fprintf ( f , "\t.cfi_b_key_frame\n" ) ; } </s>

Triggered after a .cfi_startproc directive is emitted into the assembly file . Used to output the .cfi_b_key_frame directive when signing the current function with the B key .


<s> unsigned getMaxInlineSizeThreshold ( ) const { return isThumb1Only ( ) ? 0 : 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> StringRef getPassName ( ) const override { return STPSUPPRESS_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? 10 : 16 , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? Mips :: GPR64RegClass : Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> registered_function & function_builder :: add_function ( const function_instance & instance , const char * name , tree fntype , tree attrs , uint64_t required_extensions , bool overloaded_p , bool placeholder_p ) { unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_SVE ; tree decl = placeholder_p ? integer_zero_node : simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function > ( ) ; rfn . instance = instance ; rfn . decl = decl ; rfn . required_extensions = required_extensions ; rfn . overloaded_p = overloaded_p ; vec_safe_push ( registered_functions , & rfn ) ; return rfn ; } </s>

Add a function called NAME with type FNTYPE and attributes ATTRS . INSTANCE describes what the function does .


<s> bool sh_legitimate_index_p ( machine_mode mode , rtx op , bool consider_sh2a , bool allow_zero ) { if ( ! CONST_INT_P ( op ) ) return false ; { const HOST_WIDE_INT offset = INTVAL ( op ) ; const int max_disp = sh_max_mov_insn_displacement ( mode , consider_sh2a ) ; const int align_mask = mov_insn_alignment_mask ( mode , consider_sh2a ) ; if ( ! allow_zero && max_disp < 1 ) return false ; return offset >= 0 && offset <= max_disp && ( offset & align_mask ) == 0 ; } } </s>

Return TRUE for a valid displacement for the REG+disp addressing with MODE .


<s> void ix86_emit_swdivsf ( rtx res , rtx a , rtx b , machine_mode mode ) { rtx x0 , x1 , e0 , e1 ; x0 = gen_reg_rtx ( mode ) ; e0 = gen_reg_rtx ( mode ) ; e1 = gen_reg_rtx ( mode ) ; x1 = gen_reg_rtx ( mode ) ; b = force_reg ( mode , b ) ; if ( mode == V16SFmode || mode == V8DFmode ) { if ( TARGET_AVX512ER ) { emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , b ) , UNSPEC_RCP28 ) ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_MULT ( mode , a , x0 ) ) ) ; return ; } else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , b ) , UNSPEC_RCP14 ) ) ) ; } else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , b ) , UNSPEC_RCP ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , b ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( e1 , gen_rtx_PLUS ( mode , x0 , x0 ) ) ) ; emit_insn ( gen_rtx_SET ( x1 , gen_rtx_MINUS ( mode , e1 , e0 ) ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_MULT ( mode , a , x1 ) ) ) ; } </s>


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & FS , bool isThumb ) : ARMArchVersion ( V4T ) , ARMFPUType ( None ) , UseNEONForSinglePrecisionFP ( false ) , IsThumb ( isThumb ) , ThumbMode ( Thumb1 ) , IsR9Reserved ( ReserveR9 ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 5 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer > '4' && SubVer <= '9' ) { if ( SubVer >= '7' ) { ARMArchVersion = V7A ; } else if ( SubVer == '6' ) { ARMArchVersion = V6 ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == '2' ) ARMArchVersion = V6T2 ; } else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } if ( ARMArchVersion >= V6T2 ) ThumbMode = Thumb2 ; } } if ( ARMArchVersion < V6T2 && ThumbMode >= Thumb2 ) ARMArchVersion = V6T2 ; if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( ARMArchVersion < V6 ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool xstormy16_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return regno != 16 || mode == BImode ; } </s>


runOnMachineFunction - Emit the function body .


<s>
Register
ARMTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .

ARM
ARM
"sp"
ARM::SP
0
"Invalid register name \""
"\"."


"Only optimizing constant comparisons so far"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> static inline unsigned char * unw_decode ( unsigned char * dp , int inside_body , void * arg ) { unw_decoder decoder ; unsigned char code ; code = * dp ++ ; decoder = unw_decode_table [ inside_body ] [ code >> 5 ] ; dp = ( * decoder ) ( dp , code , arg ) ; return dp ; } </s>

Decode one descriptor and return address of next descriptor .


<s> bool ia64_expand_load_address ( rtx dest , rtx src ) { gcc_assert ( GET_CODE ( dest ) == REG ) ; if ( GET_MODE ( dest ) != Pmode ) dest = gen_rtx_REG_offset ( dest , Pmode , REGNO ( dest ) , byte_lowpart_offset ( Pmode , GET_MODE ( dest ) ) ) ; if ( TARGET_NO_PIC ) return false ; if ( small_addr_symbolic_operand ( src , VOIDmode ) ) return false ; if ( TARGET_AUTO_PIC ) emit_insn ( gen_load_gprel64 ( dest , src ) ) ; else if ( GET_CODE ( src ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( src ) ) emit_insn ( gen_load_fptr ( dest , src ) ) ; else if ( sdata_symbolic_operand ( src , VOIDmode ) ) emit_insn ( gen_load_gprel ( dest , src ) ) ; else if ( local_symbolic_operand64 ( src , VOIDmode ) ) { emit_insn ( gen_load_gprel64 ( dest , src ) ) ; } else { HOST_WIDE_INT addend = 0 ; rtx tmp ; if ( GET_CODE ( src ) == CONST ) { HOST_WIDE_INT hi , lo ; hi = INTVAL ( XEXP ( XEXP ( src , 0 ) , 1 ) ) ; lo = ( ( hi & 0x3fff ) ^ 0x2000 ) - 0x2000 ; hi = hi - lo ; if ( lo != 0 ) { addend = lo ; src = plus_constant ( Pmode , XEXP ( XEXP ( src , 0 ) , 0 ) , hi ) ; } } tmp = gen_rtx_HIGH ( Pmode , src ) ; tmp = gen_rtx_PLUS ( Pmode , tmp , pic_offset_table_rtx ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; tmp = gen_rtx_LO_SUM ( Pmode , gen_const_mem ( Pmode , dest ) , src ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; if ( addend ) { tmp = gen_rtx_PLUS ( Pmode , dest , GEN_INT ( addend ) ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; } } return true ; } </s>


<s> AArch64GenInstrInfo :: MachineOutlinerInstrType AArch64InstrInfo :: getOutliningType ( MachineInstr & MI ) const { MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; AArch64FunctionInfo * FuncInfo = MF -> getInfo < AArch64FunctionInfo > ( ) ; if ( FuncInfo -> getLOHRelated ( ) . count ( & MI ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( MI . isTerminator ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . modifiesRegister ( AArch64 :: LR , & RI ) || MI . readsRegister ( AArch64 :: LR , & RI ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . modifiesRegister ( AArch64 :: SP , & RI ) || MI . readsRegister ( AArch64 :: SP , & RI ) ) { if ( MI . mayLoadOrStore ( ) ) { unsigned Base ; int64_t Offset ; unsigned DummyWidth ; if ( ! getMemOpBaseRegImmOfsWidth ( MI , Base , Offset , DummyWidth , & RI ) || Base != AArch64 :: SP ) return MachineOutlinerInstrType :: Illegal ; int64_t MinOffset , MaxOffset ; unsigned DummyScale ; getMemOpInfo ( MI . getOpcode ( ) , DummyScale , DummyWidth , MinOffset , MaxOffset ) ; if ( Offset + 16 < MinOffset || Offset + 16 > MaxOffset ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } return MachineOutlinerInstrType :: Illegal ; } return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( ) == 8 ; return createPPCELFObjectWriter ( OS , is64 , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void ix86_expand_rint ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx res , xa , TWO52 , mask ; rtx_code_label * label ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; TWO52 = ix86_gen_TWO52 ( mode ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa , res , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand rint ( IEEE round to nearest ) rounding OPERAND1 and storing the result in OPERAND0 .


<s> static bool loongarch_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ; } </s>

Implement TARGET_CAN_ELIMINATE . Make sure that we 're not trying to eliminate to the wrong hard frame pointer .


<s> bool aarch64_float_const_representable_p ( rtx x ) { int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; int exponent ; unsigned HOST_WIDE_INT mantissa , mask ; REAL_VALUE_TYPE r , m ; bool fail ; x = unwrap_const_vec_duplicate ( x ) ; if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( GET_MODE ( x ) == VOIDmode || ( GET_MODE ( x ) == HFmode && ! TARGET_FP_F16INST ) ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return false ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; if ( w . ulow ( ) != 0 ) return false ; mantissa = w . elt ( 1 ) ; point_pos -= HOST_BITS_PER_WIDE_INT ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return false ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return false ; mantissa &= ~ ( 1 << 4 ) ; gcc_assert ( mantissa <= 15 ) ; exponent = 5 - exponent ; return ( exponent >= 0 && exponent <= 7 ) ; } </s>

Return true iff X can be represented by a quarter-precision floating point immediate operand X . Note , we can not represent 0.0 .


<s> bool PPCSubtarget :: useDFAforSMS ( ) const { return false ; } </s>

Default to DFA for resource management , return false when target will use ProcResource in InstrSchedModel instead .


<s> static tree mips_std_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { tree addr , t , type_size , rounded_size , valist_tmp ; unsigned HOST_WIDE_INT align , boundary ; bool indirect ; indirect = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( indirect ) type = build_pointer_type ( type ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = targetm . calls . function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; if ( boundary > align ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - 1 ) ) ; gimplify_and_add ( t , pre_p ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build2 ( BIT_AND_EXPR , TREE_TYPE ( valist ) , valist_tmp , build_int_cst ( TREE_TYPE ( valist ) , - boundary ) ) ) ; gimplify_and_add ( t , pre_p ) ; } else boundary = align ; boundary *= BITS_PER_UNIT ; if ( boundary < TYPE_ALIGN ( type ) ) { type = build_variant_type_copy ( type ) ; TYPE_ALIGN ( type ) = boundary ; } type_size = size_in_bytes ( type ) ; rounded_size = round_up ( type_size , align ) ; gimplify_expr ( & rounded_size , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = valist_tmp ; if ( PAD_VARARGS_DOWN && ! integer_zerop ( rounded_size ) ) { t = fold_build2_loc ( input_location , GT_EXPR , sizetype , rounded_size , size_int ( align ) ) ; t = fold_build3 ( COND_EXPR , sizetype , t , size_zero_node , size_binop ( MINUS_EXPR , rounded_size , type_size ) ) ; addr = fold_build_pointer_plus ( addr , t ) ; } t = fold_build_pointer_plus ( valist_tmp , rounded_size ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( indirect ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>

Like std_gimplify_va_arg_expr , but apply alignment to zero-sized types as well .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> MVT MipsTargetLowering :: getSetCCResultType ( MVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static scalar_int_mode aarch64_sve_element_int_mode ( machine_mode mode ) { poly_uint64 vector_bits = ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ; unsigned int elt_bits = vector_element_size ( vector_bits , GET_MODE_NUNITS ( mode ) ) ; return int_mode_for_size ( elt_bits , 0 ) . require ( ) ; } </s>

Return the integer element mode associated with SVE mode MODE .


<s> unsigned ARMTTIImpl :: getFPOpCost ( Type * Ty ) { if ( ST -> hasVFP2 ( ) && ! ST -> isThumb1Only ( ) ) { if ( Ty -> isFloatTy ( ) ) { return TargetTransformInfo :: TCC_Basic ; } if ( Ty -> isDoubleTy ( ) ) { return ST -> isFPOnlySP ( ) ? TargetTransformInfo :: TCC_Expensive : TargetTransformInfo :: TCC_Basic ; } } return TargetTransformInfo :: TCC_Expensive ; } </s>

Return the expected cost of supporting the floating point operation of the specified type .


<s> bool mips_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( GET_MODE_SIZE ( from ) == 8 && GET_MODE_SIZE ( to ) == 8 && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return false ; return reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


<s> rtx ix86_gen_scratch_sse_rtx ( machine_mode mode ) { return gen_reg_rtx ( mode ) ; } </s>

Implement the TARGET_GEN_MEMSET_SCRATCH_RTX hook . Return a scratch register in MODE for vector load and store .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( Subtarget . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( TM . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( PPC :: X2 ) ; else Reserved . reset ( PPC :: R2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SystemZ_SaveList ; } </s>


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
uint64_t
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0ULL
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
&
)
*
Operands
[
ErrorInfo
]
)
.
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
void
i386_pe_file_end
(
void
)
{
struct
extern_list
*
p
;
for
(
p
=
extern_head
;
p
!=
;
p
=
p
->
next
)
{
tree
decl
;
decl
=
p
->
decl
;
if
(
!
TREE_ASM_WRITTEN
(
decl
)
&&
TREE_SYMBOL_REFERENCED
(
DECL_ASSEMBLER_NAME
(
decl
)
)
)
{
const
char
*
realsym
=
i386_find_on_wrapper_list
(
p
->
name
)
;
if
(
realsym
)
i386_pe_declare_function_type
(
asm_out_file
,
concat
(
"__real_"
,
realsym
,
)
,
TREE_PUBLIC
(
decl
)
)
;
TREE_ASM_WRITTEN
(
decl
)
=
1
;
i386_pe_declare_function_type
(
asm_out_file
,
p
->
name
,
TREE_PUBLIC
(
decl
)
)
;
}
}
if
(
export_head
)
{
struct
export_list
*
q
;
drectve_section
(
)
;
for
(
q
=
export_head
;
q
!=
;
q
=
q
->
next
)
{
fprintf
(
asm_out_file
,
"\t.ascii \" -export:\\\"%s\\\"%s\"\n"
,
default_strip_name_encoding
(
q
->
name
)
,
(
q
->
is_data
",data"
:
""
)
)
;
}
}
if
(
stub_head
)
{
struct
stub_list
*
q
;
for
(
q
=
stub_head
;
q
!=
;
q
=
q
->
next
)
{
const
char
*
name
=
q
->
name
;
const
char
*
oname
;
if
(
name
[
0
]
==
'*'
)
++
name
;
oname
=
name
;
if
(
name
[
0
]
==
'.'
)
++
name
;
if
(
!
startswith
(
name
,
"refptr."
)
)
continue
;
name
+=
7
;
fprintf
(
asm_out_file
,
"\t.section\t.rdata$%s, \"dr\"\n"
"\t.globl\t%s\n"
"\t.linkonce\tdiscard\n"
,
oname
,
oname
)
;
fprintf
(
asm_out_file
,
"%s:\n\t.quad\t%s\n"
,
oname
,
name
)
;
}
}
}
</s>

This is called at the end of assembly . For each external function which has not been defined , we output a declaration now . We also output the .drectve section .


<s> bool swiftAsyncContextIsDynamicallySet ( ) const { const Triple & TT = getTargetTriple ( ) ; unsigned Major , Minor , Micro ; TT . getOSVersion ( Major , Minor , Micro ) ; switch ( TT . getOS ( ) ) { default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < 15 ; case Triple :: WatchOS : return Major < 8 ; case Triple :: MacOSX : case Triple :: Darwin : return Major < 12 ; } } </s>

Return whether FrameLowering should always set the `` extended frame present '' bit in FP , or set it based on a symbol in the runtime .


<s> bool csky_legitimate_pic_operand_p ( rtx x ) { if ( tls_unspec_mentioned_p ( x ) ) return true ; if ( csky_symbol_mentioned_p ( x ) || csky_label_mentioned_p ( x ) ) return false ; return true ; } </s>


<s> int64_t getStackPointerBias ( ) const { return is64Bit ( ) ? 2047 : 0 ; } </s>

The 64-bit ABI uses biased stack and frame pointers , so the stack frame of the current function is the area from [ sp+BIAS ] to [ fp+BIAS ] .


<s> bool Mips16TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function_p ) { int outgoing_args_size = ( current_function_outgoing_args_size + REG_PARM_STACK_SPACE ( current_function_decl ) ) ; int n_regs = 0 ; int i ; if ( TARGET_ARCH64 ) { for ( i = 0 ; i < 8 ; i ++ ) if ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) n_regs += 2 ; } else { for ( i = 0 ; i < 8 ; i += 2 ) if ( ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) || ( regs_ever_live [ i + 1 ] && ! call_used_regs [ i + 1 ] ) ) n_regs += 2 ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) || ( regs_ever_live [ i + 1 ] && ! call_used_regs [ i + 1 ] ) ) n_regs += 2 ; num_gfregs = n_regs ; if ( leaf_function_p && n_regs == 0 && size == 0 && current_function_outgoing_args_size == 0 ) actual_fsize = apparent_fsize = 0 ; else { apparent_fsize = ( size - STARTING_FRAME_OFFSET + 7 ) & - 8 ; apparent_fsize += n_regs * 4 ; actual_fsize = apparent_fsize + ( ( outgoing_args_size + 7 ) & - 8 ) ; } if ( ! leaf_function_p || size > 0 ) actual_fsize += FIRST_PARM_OFFSET ( current_function_decl ) ; return SPARC_STACK_ALIGN ( actual_fsize ) ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> void gen_shifty_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; value = value & 0x1f ; if ( value == 31 ) { if ( code == LSHIFTRT ) { emit_insn ( gen_rotlsi3_1 ( operands [ 0 ] , operands [ 0 ] ) ) ; emit_insn ( gen_movt ( operands [ 0 ] ) ) ; return ; } else if ( code == ASHIFT ) { if ( GET_CODE ( operands [ 0 ] ) == REG && REGNO ( operands [ 0 ] ) == 0 ) { emit_insn ( gen_andsi3 ( operands [ 0 ] , operands [ 0 ] , const1_rtx ) ) ; emit_insn ( gen_rotlsi3_31 ( operands [ 0 ] , operands [ 0 ] ) ) ; return ; } } } else if ( value == 0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , operands [ 0 ] ) ) ; return ; } max = shift_insns [ value ] ; for ( i = 0 ; i < max ; i ++ ) gen_ashift ( code , shift_amounts [ value ] [ i ] , operands [ 0 ] ) ; } </s>

Output RTL to split a constant shift into its component SH constant shift instructions .


<s> unsigned int darwin_rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; if ( TYPE_PACKED ( type ) ) return align ; do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return align ; } </s>

Darwin increases record alignment to the natural alignment of the first field .


<s> static void aarch64_emit_unlikely_jump ( rtx insn ) { rtx_insn * jump = emit_jump_insn ( insn ) ; add_reg_br_prob_note ( jump , profile_probability :: very_unlikely ( ) ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> InstructionCost X86TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != 0 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcodeBranch ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ) return true ; if ( MCDisableArithRelaxation ) return false ; if ( getRelaxedOpcodeArith ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; bool hasExp = false ; bool hasRIP = false ; for ( unsigned i = 0 ; i < Inst . getNumOperands ( ) ; ++ i ) { const MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isExpr ( ) ) hasExp = true ; if ( Op . isReg ( ) && Op . getReg ( ) == X86 :: RIP ) hasRIP = true ; } return hasExp && ! hasRIP ; } </s>

Check whether the given instruction may need relaxation .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER


<s> static rtx emit_memset ( rtx destmem , rtx destptr , rtx promoted_val , HOST_WIDE_INT size_to_move ) { rtx dst = destmem ; enum insn_code code ; machine_mode move_mode ; int piece_size , i ; move_mode = GET_MODE ( promoted_val ) ; if ( move_mode == VOIDmode ) move_mode = QImode ; if ( size_to_move < GET_MODE_SIZE ( move_mode ) ) { unsigned int move_bits = size_to_move * BITS_PER_UNIT ; move_mode = int_mode_for_size ( move_bits , 0 ) . require ( ) ; promoted_val = gen_lowpart ( move_mode , promoted_val ) ; } piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; gcc_assert ( code != CODE_FOR_nothing && promoted_val != NULL_RTX ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , 0 ) ; gcc_assert ( size_to_move % piece_size == 0 ) ; for ( i = 0 ; i < size_to_move ; i += piece_size ) { if ( piece_size <= GET_MODE_SIZE ( word_mode ) ) { emit_insn ( gen_strset ( destptr , dst , promoted_val ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; continue ; } emit_insn ( GEN_FCN ( code ) ( dst , promoted_val ) ) ; emit_move_insn ( destptr , plus_constant ( Pmode , copy_rtx ( destptr ) , piece_size ) ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , piece_size ) ; } return dst ; } </s>

This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM with value PROMOTED_VAL . SRC is passed by pointer to be updated on return . Return value is updated DST .


<s> Instruction * PPCTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { if ( Ord == SequentiallyConsistent ) return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; else if ( isAtLeastRelease ( Ord ) ) return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; else return nullptr ; } </s>


<s> static reg_class_t csky_spill_class ( reg_class_t rclass , machine_mode mode ATTRIBUTE_UNUSED ) { if ( ( rclass == MINI_REGS && ! TARGET_MINI_REGISTERS ) || ( rclass == LOW_REGS && TARGET_HIGH_REGISTERS ) ) return GENERAL_REGS ; return NO_REGS ; } </s>

Implement TARGET_SPILL_CLASS . Try spilling to a larger register class before spilling to memory .


<s> bool MipsBranchExpansion :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const MipsInstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; bool Changed = longBranchChanged || forbiddenSlotChanged || fpuDelaySlotChanged ; while ( forbiddenSlotChanged ) { longBranchChanged = handlePossibleLongBranch ( ) ; fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; if ( ! longBranchChanged && ! fpuDelaySlotChanged ) break ; forbiddenSlotChanged = handleForbiddenSlot ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned int mips_load_label_num_insns ( void ) { if ( cfun -> machine -> load_label_num_insns == 0 ) { mips_process_load_label ( pc_rtx ) ; cfun -> machine -> load_label_num_insns = mips_multi_num_insns ; } return cfun -> machine -> load_label_num_insns ; } </s>

Return the number of instructions needed to load a label into $ AT .


<s> static void arm_set_default_type_attributes ( tree type ) { if ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) { tree type_attr_list , attr_name ; type_attr_list = TYPE_ATTRIBUTES ( type ) ; if ( arm_pragma_long_calls == LONG ) attr_name = get_identifier ( "long_call" ) ; else if ( arm_pragma_long_calls == SHORT ) attr_name = get_identifier ( "short_call" ) ; else return ; type_attr_list = tree_cons ( attr_name , NULL_TREE , type_attr_list ) ; TYPE_ATTRIBUTES ( type ) = type_attr_list ; } } </s>

Assigns default attributes to newly defined type . This is used to set short_call/long_call attributes for function types of functions defined inside corresponding # pragma scopes .


<s> void PPCAsmPrinter :: PrintSymbolOperand ( const MachineOperand & MO , raw_ostream & O ) { const GlobalValue * GV = MO . getGlobal ( ) ; getSymbol ( GV ) -> print ( O , MAI ) ; printOffset ( MO . getOffset ( ) , O ) ; } </s>


<s> bool ia64_legitimate_constant_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case LABEL_REF : return true ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode ) return true ; return CONST_DOUBLE_OK_FOR_G ( x ) ; case CONST : case SYMBOL_REF : return tls_symbolic_operand_type ( x ) == 0 ; case CONST_VECTOR : { enum machine_mode mode = GET_MODE ( x ) ; if ( mode == V2SFmode ) return ia64_extra_constraint ( x , 'Y' ) ; return ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT && GET_MODE_SIZE ( mode ) <= 8 ) ; } default : return false ; } } </s>

Return true if X is a constant that is valid for some immediate field in an instruction .


<s>
void
SystemZInstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Pred
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
unsigned
Opc
;
if
(
SystemZ
::
GRX32BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELRMux
;
else
if
(
STI
.
hasLoadStoreOnCond2
(
)
)
Opc
=
SystemZ
::
LOCRMux
;
else
{
Opc
=
SystemZ
::
LOCR
;
MRI
.
constrainRegClass
(
DstReg
,
&
SystemZ
::
GR32BitRegClass
)
;
unsigned
TReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
unsigned
FReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
TReg
)
.
addReg
(
TrueReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
FReg
)
.
addReg
(
FalseReg
)
;
TrueReg
=
TReg
;
FalseReg
=
FReg
;
}
}
else
if
(
SystemZ
::
GR64BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasMiscellaneousExtensions3
(
)
)
Opc
=
SystemZ
::
SELGR
;
else
Opc
=
SystemZ
::
LOCGR
;
}
else
llvm_unreachable
(
"Invalid register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> static rtx aapcs_vfp_allocate_return_reg ( enum arm_pcs pcs_variant ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { if ( ! use_vfp_abi ( pcs_variant , false ) ) return NULL ; if ( mode == BLKmode || ( mode == TImode && ! TARGET_NEON ) ) { int count ; machine_mode ag_mode ; int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! TARGET_NEON ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= 2 ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } return gen_rtx_REG ( mode , FIRST_VFP_REGNUM ) ; } </s>

Implement the allocate_return_reg field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> static struct rbt_string_node * rbt_create_node ( struct rbt_strings * t , char * str ) { struct rbt_string_node * nodeptr = ( struct rbt_string_node * ) malloc ( sizeof ( rbt_string_node ) ) ; nodeptr -> str = str ; nodeptr -> left = t -> rbt_nil ; nodeptr -> right = t -> rbt_nil ; nodeptr -> par = NULL ; nodeptr -> color = RBT_RED ; return nodeptr ; } </s>

Create a new node to be inserted into the red-black tree . An inserted node starts out red .


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( StringRef Name ) { const MipsCallEntry * & E = ExternalCallEntries [ Name ] ; if ( ! E ) E = new MipsCallEntry ( Name ) ; return MachinePointerInfo ( E ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> bool X86TTIImpl :: isLegalNTLoad ( Type * DataType , unsigned Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( Alignment >= DataSize && ( DataSize == 16 || DataSize == 32 ) ) return DataSize == 16 ? ST -> hasSSE1 ( ) : ST -> hasAVX2 ( ) ; return false ; } </s>

Return true if the target supports nontemporal load .


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONPreAllocPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .