<s> bool ix86_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , machine_mode mode , int strict ) { return inline_secondary_memory_needed ( class1 , class2 , mode , strict ) ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> static void sparc_init_pic_reg ( void ) { edge entry_edge ; rtx_insn * seq ; if ( ! crtl -> uses_pic_offset_table ) return ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , got_register_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } </s>


<s> size_t MipsLA25Stub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


"internal error: builtin function %qs already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> static unsigned aarch64_add_stmt_cost ( class vec_info * vinfo , void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , tree vectype , int misalign , enum vect_cost_model_location where ) { auto * costs = static_cast < aarch64_vector_costs * > ( data ) ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { int stmt_cost = aarch64_builtin_vectorization_cost ( kind , vectype , misalign ) ; loop_vec_info loop_vinfo = dyn_cast < loop_vec_info > ( vinfo ) ; bb_vec_info bb_vinfo = dyn_cast < bb_vec_info > ( vinfo ) ; if ( ! costs -> analyzed_vinfo && aarch64_use_new_vector_costs_p ( ) ) { if ( loop_vinfo ) aarch64_analyze_loop_vinfo ( loop_vinfo , costs ) ; else aarch64_analyze_bb_vinfo ( bb_vinfo , costs ) ; costs -> analyzed_vinfo = true ; } if ( stmt_info && aarch64_use_new_vector_costs_p ( ) ) { if ( vectype && aarch64_sve_only_stmt_p ( stmt_info , vectype ) ) costs -> saw_sve_only_op = true ; stmt_cost = aarch64_detect_scalar_stmt_subtype ( vinfo , kind , stmt_info , stmt_cost ) ; if ( vectype && costs -> vec_flags ) stmt_cost = aarch64_detect_vector_stmt_subtype ( vinfo , kind , stmt_info , vectype , where , stmt_cost ) ; } if ( stmt_info && vectype && aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) ) stmt_cost = aarch64_sve_adjust_stmt_cost ( vinfo , kind , stmt_info , vectype , stmt_cost ) ; if ( stmt_info && aarch64_use_new_vector_costs_p ( ) ) { stmt_cost = aarch64_adjust_stmt_cost ( kind , stmt_info , vectype , stmt_cost ) ; auto * issue_info = aarch64_tune_params . vec_costs -> issue_info ; if ( loop_vinfo && issue_info && costs -> vec_flags && where == vect_body && vectype && stmt_cost != 0 ) { aarch64_count_ops ( vinfo , costs , count , kind , stmt_info , vectype , 0 , & costs -> scalar_ops , issue_info -> scalar , vect_nunits_for_cost ( vectype ) ) ; if ( aarch64_sve_mode_p ( vinfo -> vector_mode ) && issue_info -> sve ) { aarch64_count_ops ( vinfo , costs , count , kind , stmt_info , vectype , VEC_ADVSIMD , & costs -> advsimd_ops , issue_info -> advsimd , aarch64_estimated_sve_vq ( ) ) ; aarch64_count_ops ( vinfo , costs , count , kind , stmt_info , vectype , VEC_ANY_SVE , & costs -> sve_ops , issue_info -> sve , 1 ) ; } else aarch64_count_ops ( vinfo , costs , count , kind , stmt_info , vectype , VEC_ADVSIMD , & costs -> advsimd_ops , issue_info -> advsimd , 1 ) ; } if ( where == vect_body && costs -> unrolled_advsimd_niters ) costs -> unrolled_advsimd_stmts += count * costs -> unrolled_advsimd_niters ; } if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( vinfo , stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; costs -> region [ where ] += retval ; } return retval ; } </s>


<s> bool X86InstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return ! ( RC == & X86 :: CCRRegClass || RC == & X86 :: DFCCRRegClass || RC == & X86 :: RFP32RegClass || RC == & X86 :: RFP64RegClass || RC == & X86 :: RFP80RegClass ) ; } </s>

isSafeToMoveRegClassDefs - Return true if it 's safe to move a machine instruction that defines the specified register class .


<s>
void
ARMConstantIslands
::
verify
(
)
{
assert
(
std
::
is_sorted
(
MF
->
begin
(
)
,
MF
->
end
(
)
,
[
this
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> bool X86InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == X86 :: ENDBR64 || Opcode == X86 :: ENDBR32 || Opcode == X86 :: LDTILECFG ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool Cpu0FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> unsigned PPCTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == MVT :: f64 ) return 2 ; return PPCTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> int shl_and_scr_length ( rtx insn ) { rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; int len = ashl_lshr_seq [ INTVAL ( XEXP ( set_src , 1 ) ) & 31 ] . insn_count ; rtx op = XEXP ( set_src , 0 ) ; len += ashl_lshr_seq [ INTVAL ( XEXP ( op , 1 ) ) & 31 ] . insn_count + 1 ; op = XEXP ( XEXP ( op , 0 ) , 0 ) ; return len + ashl_lshr_seq [ INTVAL ( XEXP ( op , 1 ) ) & 31 ] . insn_count ; } </s>

This is used in length attribute of the and_shl_scratch instruction .


<s> int pa_reloc_needed ( tree exp ) { int reloc = 0 ; switch ( TREE_CODE ( exp ) ) { case ADDR_EXPR : return 1 ; case POINTER_PLUS_EXPR : case PLUS_EXPR : case MINUS_EXPR : reloc = pa_reloc_needed ( TREE_OPERAND ( exp , 0 ) ) ; reloc |= pa_reloc_needed ( TREE_OPERAND ( exp , 1 ) ) ; break ; CASE_CONVERT : case NON_LVALUE_EXPR : reloc = pa_reloc_needed ( TREE_OPERAND ( exp , 0 ) ) ; break ; case CONSTRUCTOR : { tree value ; unsigned HOST_WIDE_INT ix ; FOR_EACH_CONSTRUCTOR_VALUE ( CONSTRUCTOR_ELTS ( exp ) , ix , value ) if ( value ) reloc |= pa_reloc_needed ( value ) ; } break ; case ERROR_MARK : break ; default : break ; } return reloc ; } </s>

Examine EXP and return nonzero if it contains an ADDR_EXPR ( meaning it will need a link/runtime reloc ) .


<s> SDValue MipsSETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: SMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Mult , true , true , DAG ) ; case ISD :: UMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Multu , true , true , DAG ) ; case ISD :: MULHS : return lowerMulDiv ( Op , MipsISD :: Mult , false , true , DAG ) ; case ISD :: MULHU : return lowerMulDiv ( Op , MipsISD :: Multu , false , true , DAG ) ; case ISD :: MUL : return lowerMulDiv ( Op , MipsISD :: Mult , true , false , DAG ) ; case ISD :: SDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRem , true , true , DAG ) ; case ISD :: UDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRemU , true , true , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_VOID : return lowerINTRINSIC_VOID ( Op , DAG ) ; case ISD :: EXTRACT_VECTOR_ELT : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case ISD :: BUILD_VECTOR : return lowerBUILD_VECTOR ( Op , DAG ) ; case ISD :: VECTOR_SHUFFLE : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; } return MipsTargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::LOAD ISD::STORE ISD::SMUL_LOHI MipsISD::Mult ISD::UMUL_LOHI MipsISD::Multu ISD::MULHS MipsISD::Mult ISD::MULHU MipsISD::Multu ISD::MUL MipsISD::Mult ISD::SDIVREM MipsISD::DivRem ISD::UDIVREM MipsISD::DivRemU ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_VOID ISD::EXTRACT_VECTOR_ELT ISD::BUILD_VECTOR ISD::VECTOR_SHUFFLE ISD::SELECT Mips


<s> bool LEGFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>


<s> void X86RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool reseveCallFrame = TFI -> hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( Is64Bit , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! llvm :: prior ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR8 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> void ix86_expand_vector_logical_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx op1 = NULL_RTX , op2 = NULL_RTX ; if ( GET_CODE ( operands [ 1 ] ) == SUBREG ) { op1 = operands [ 1 ] ; op2 = operands [ 2 ] ; } else if ( GET_CODE ( operands [ 2 ] ) == SUBREG ) { op1 = operands [ 2 ] ; op2 = operands [ 1 ] ; } if ( op1 && ! TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL && ( ( GET_CODE ( op2 ) == SUBREG || GET_CODE ( op2 ) == CONST_VECTOR ) ) && GET_MODE_CLASS ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == MODE_VECTOR_FLOAT && GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( op1 ) ) ) == GET_MODE_SIZE ( mode ) && SUBREG_BYTE ( op1 ) == 0 && ( GET_CODE ( op2 ) == CONST_VECTOR || ( GET_MODE ( SUBREG_REG ( op1 ) ) == GET_MODE ( SUBREG_REG ( op2 ) ) && SUBREG_BYTE ( op2 ) == 0 ) ) && can_create_pseudo_p ( ) ) { rtx dst ; switch ( GET_MODE ( SUBREG_REG ( op1 ) ) ) { case V4SFmode : case V8SFmode : case V16SFmode : case V2DFmode : case V4DFmode : case V8DFmode : dst = gen_reg_rtx ( GET_MODE ( SUBREG_REG ( op1 ) ) ) ; if ( GET_CODE ( op2 ) == CONST_VECTOR ) { op2 = gen_lowpart ( GET_MODE ( dst ) , op2 ) ; op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } else { op1 = operands [ 1 ] ; op2 = SUBREG_REG ( operands [ 2 ] ) ; if ( ! nonimmediate_operand ( op2 , GET_MODE ( dst ) ) ) op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } op1 = SUBREG_REG ( op1 ) ; if ( ! nonimmediate_operand ( op1 , GET_MODE ( dst ) ) ) op1 = force_reg ( GET_MODE ( dst ) , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , GET_MODE ( dst ) , op1 , op2 ) ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( mode , dst ) ) ; return ; default : break ; } } if ( ! nonimmediate_operand ( operands [ 1 ] , mode ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; if ( ! nonimmediate_operand ( operands [ 2 ] , mode ) ) operands [ 2 ] = force_reg ( mode , operands [ 2 ] ) ; ix86_fixup_binary_operands_no_copy ( code , mode , operands ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_fmt_ee ( code , mode , operands [ 1 ] , operands [ 2 ] ) ) ) ; } </s>

Expand vector logical operation CODE ( AND , IOR , XOR ) in MODE with the given OPERANDS .


<s> static bool moxie_reg_ok_for_base_p ( const_rtx reg , bool strict_p ) { int regno = REGNO ( reg ) ; if ( strict_p ) return HARD_REGNO_OK_FOR_BASE_P ( regno ) || HARD_REGNO_OK_FOR_BASE_P ( reg_renumber [ regno ] ) ; else return ! HARD_REGISTER_NUM_P ( regno ) || HARD_REGNO_OK_FOR_BASE_P ( regno ) ; } </s>

Helper function for ` moxie_legitimate_address_p ' .


<s> static rtx arm_expand_unop_builtin ( enum insn_code icode , tree exp , rtx target , int do_load ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = NULL_RTX ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; bool builtin_sha1h_p = false ; if ( insn_data [ icode ] . n_operands == 3 ) { gcc_assert ( icode == CODE_FOR_crypto_sha1h ) ; builtin_sha1h_p = true ; } if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } if ( builtin_sha1h_p ) op1 = GEN_INT ( TARGET_BIG_END ? 1 : 0 ) ; if ( builtin_sha1h_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of unop insns .


<s> rtx function_expander :: generate_insn ( insn_code icode ) { expand_insn ( icode , m_ops . length ( ) , m_ops . address ( ) ) ; return function_returns_void_p ( ) ? const0_rtx : m_ops [ 0 ] . value ; } </s>

Generate instruction ICODE , given that its operands have already been added to M_OPS . Return the value of the first operand .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return combineVECTOR_SHUFFLE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: STRICT_FP_ROUND : case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: STRICT_FP_EXTEND : case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return combineINT_TO_FP ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; case ISD :: INTRINSIC_W_CHAIN : case ISD :: INTRINSIC_VOID : return combineINTRINSIC ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static int num_insns_constant_gpr ( HOST_WIDE_INT value ) { if ( ( ( unsigned HOST_WIDE_INT ) value + 0x8000 ) < 0x10000 ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 ) return num_insns_constant_gpr ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_gpr ( low ) + 1 ; else return ( num_insns_constant_gpr ( high ) + num_insns_constant_gpr ( low ) + 1 ) ; } else return 2 ; } </s>

Helper for num_insns_constant . Calculate number of instructions to load VALUE to a single gpr using combinations of addi , addis , ori , oris , sldi and rldimi instructions .


<s>
const
ArrayRef
<
MCPhysReg
>
Cpu0ABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsS32
(
)
)
return
makeArrayRef
(
S32IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


<s> MachineInstr * ARMBaseInstrInfo :: duplicate ( MachineInstr * Orig , MachineFunction & MF ) const { MachineInstr * MI = TargetInstrInfoImpl :: duplicate ( Orig , MF ) ; switch ( Orig -> getOpcode ( ) ) { case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { unsigned CPI = Orig -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; Orig -> getOperand ( 1 ) . setIndex ( CPI ) ; Orig -> getOperand ( 2 ) . setImm ( PCLabelId ) ; break ; } } return MI ; } </s>

Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * MF . getTarget ( ) . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = RoundUpToAlignment ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = RoundUpToAlignment ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return RoundUpToAlignment ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s> FastISel * PPC :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const TargetMachine & TM = FuncInfo . MF -> getTarget ( ) ; const PPCSubtarget * Subtarget = & TM . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget -> isPPC64 ( ) && Subtarget -> isSVR4ABI ( ) ) return new PPCFastISel ( FuncInfo , LibInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

PowerPC PPC::createFastISel PPC PPC PPC PPC 0


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>


<s> void x86_emit_floatuns ( rtx operands [ 2 ] ) { rtx_code_label * neglab , * donelab ; rtx i0 , i1 , f0 , in , out ; machine_mode mode , inmode ; inmode = GET_MODE ( operands [ 1 ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ 0 ] ; in = force_reg ( inmode , operands [ 1 ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , 0 , neglab ) ; expand_float ( out , in , 0 ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( inmode , AND , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i0 = expand_simple_binop ( inmode , IOR , i0 , i1 , i0 , 1 , OPTAB_DIRECT ) ; expand_float ( f0 , i0 , 0 ) ; emit_insn ( gen_rtx_SET ( out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode/SImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


"%Klane index must be a constant immediate"

"%Ktotal size and element size must be a non-zero constant immediate"

Expand an AArch64 AdvSIMD builtin ( intrinsic ) .


<s>
const
char
*
emit_fusion_gpr_load
(
rtx
target
,
rtx
mem
)
{
rtx
addis_value
;
rtx
addr
;
rtx
load_offset
;
const
char
*
load_str
=
;
const
char
*
mode_name
=
;
machine_mode
mode
;
if
(
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
mem
=
XEXP
(
mem
,
0
)
;
gcc_assert
(
REG_P
(
target
)
&&
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
addis_value
,
&
load_offset
)
;
mode
=
GET_MODE
(
mem
)
;
switch
(
mode
)
{
case
QImode
:
mode_name
=
"char"
;
load_str
=
"lbz"
;
break
;
case
HImode
:
mode_name
=
"short"
;
load_str
=
"lhz"
;
break
;
case
SImode
:
case
SFmode
:
mode_name
=
(
mode
==
SFmode
)
"float"
:
"int"
;
load_str
=
"lwz"
;
break
;
case
DImode
:
case
DFmode
:
gcc_assert
(
TARGET_POWERPC64
)
;
mode_name
=
(
mode
==
DFmode
)
"double"
:
"long"
;
load_str
=
"ld"
;
break
;
default
:
fatal_insn
(
"Bad GPR fusion"
,
gen_rtx_SET
(
target
,
mem
)
)
;
}
emit_fusion_addis
(
target
,
addis_value
,
"gpr load fusion"
,
mode_name
)
;
emit_fusion_load_store
(
target
,
target
,
load_offset
,
load_str
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a gpr load to the same register that we loaded up the addis instruction . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

rs6000
0
0
"char"
"lbz"
"short"
"lhz"
"float"
"int"
"lwz"
"double"
"long"
"ld"
"Bad GPR fusion"
"gpr load fusion"
""


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MMI
=
&
getAnalysis
<
MachineModuleInfo
>
(
)
;
MCE
.
setModuleInfo
(
MMI
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
MCInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
++
NumEmitted
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static void rs6000_set_default_type_attributes ( tree type ) { if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( "longcall" ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ; } </s>

Set longcall attributes on all functions declared when rs6000_default_long_calls is true .


<s> rtx rs6000_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode ; unsigned int regno ; if ( rs6000_darwin64_abi && TYPE_MODE ( valtype ) == BLKmode && TREE_CODE ( valtype ) == RECORD_TYPE && int_size_in_bytes ( valtype ) > 0 ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , 1 , true ) ; if ( valret ) return valret ; } if ( TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE ( valtype ) == DImode ) { return gen_rtx_PARALLEL ( DImode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 1 ) , GEN_INT ( 4 ) ) ) ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE ( valtype ) == DCmode ) { return gen_rtx_PARALLEL ( DCmode , gen_rtvec ( 4 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 1 ) , GEN_INT ( 4 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 2 ) , GEN_INT ( 8 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + 3 ) , GEN_INT ( 12 ) ) ) ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; else mode = TYPE_MODE ( valtype ) ; if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TREE_CODE ( valtype ) == VECTOR_TYPE && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s>
void
ARMAsmPrinter
::
emitMachineConstantPoolValue
(
MachineConstantPoolValue
*
MCPV
)
{
const
DataLayout
&
DL
=
getDataLayout
(
)
;
int
Size
=
DL
.
getTypeAllocSize
(
MCPV
->
getType
(
)
)
;
ARMConstantPoolValue
*
ACPV
=
static_cast
<
ARMConstantPoolValue
*
>
(
MCPV
)
;
if
(
ACPV
->
isPromotedGlobal
(
)
)
{
auto
*
ACPC
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
;
for
(
const
auto
*
GV
:
ACPC
->
promotedGlobals
(
)
)
{
if
(
!
EmittedPromotedGlobalLabels
.
count
(
GV
)
)
{
MCSymbol
*
GVSym
=
getSymbol
(
GV
)
;
OutStreamer
->
emitLabel
(
GVSym
)
;
EmittedPromotedGlobalLabels
.
insert
(
GV
)
;
}
}
return
emitGlobalConstant
(
DL
,
ACPC
->
getPromotedGlobalInit
(
)
)
;
}
MCSymbol
*
MCSym
;
if
(
ACPV
->
isLSDA
(
)
)
{
MCSym
=
getMBBExceptionSym
(
MF
->
front
(
)
)
;
}
else
if
(
ACPV
->
isBlockAddress
(
)
)
{
const
BlockAddress
*
BA
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getBlockAddress
(
)
;
MCSym
=
GetBlockAddressSymbol
(
BA
)
;
}
else
if
(
ACPV
->
isGlobalValue
(
)
)
{
const
GlobalValue
*
GV
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getGV
(
)
;
unsigned
char
TF
=
Subtarget
->
isTargetMachO
(
)
ARMII
::
MO_NONLAZY
:
0
;
MCSym
=
GetARMGVSymbol
(
GV
,
TF
)
;
}
else
if
(
ACPV
->
isMachineBasicBlock
(
)
)
{
const
MachineBasicBlock
*
MBB
=
cast
<
ARMConstantPoolMBB
>
(
ACPV
)
->
getMBB
(
)
;
MCSym
=
MBB
->
getSymbol
(
)
;
}
else
{
assert
(
ACPV
->
isExtSymbol
(
)
&&
"unrecognized constant pool value"
)
;
auto
Sym
=
cast
<
ARMConstantPoolSymbol
>
(
ACPV
)
->
getSymbol
(
)
;
MCSym
=
GetExternalSymbolSymbol
(
Sym
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
MCSym
,
getModifierVariantKind
(
ACPV
->
getModifier
(
)
)
,
OutContext
)
;
if
(
ACPV
->
getPCAdjustment
(
)
)
{
MCSymbol
*
PCLabel
=
getPICLabel
(
DL
.
getPrivateGlobalPrefix
(
)
,
getFunctionNumber
(
)
,
ACPV
->
getLabelId
(
)
,
OutContext
)
;
const
MCExpr
*
PCRelExpr
=
MCSymbolRefExpr
::
create
(
PCLabel
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createAdd
(
PCRelExpr
,
MCConstantExpr
::
create
(
ACPV
->
getPCAdjustment
(
)
,
OutContext
)
,
OutContext
)
;
if
(
ACPV
->
mustAddCurrentAddress
(
)
)
{
MCSymbol
*
DotSym
=
OutContext
.
createTempSymbol
(
)
;
OutStreamer
->
emitLabel
(
DotSym
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
create
(
DotSym
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createSub
(
PCRelExpr
,
DotExpr
,
OutContext
)
;
}
Expr
=
MCBinaryExpr
::
createSub
(
Expr
,
PCRelExpr
,
OutContext
)
;
}
OutStreamer
->
emitValue
(
Expr
,
Size
)
;
}
</s>

EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file .

ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARMII::MO_NONLAZY
0
ARM
ARM
"unrecognized constant pool value"
ARM


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
return
Res
;
}
</s>


<s> void Cpu0InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> StringRef getPassName ( ) const override { return "MipsPostLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
bool
ARMConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
isThumb
4
:
8
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination BB#"
<<
DestBB
->
getNumber
(
)
<<
" from BB#"
<<
MI
->
getParent
(
)
->
getNumber
(
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

ARM
ARM
4
8
"Branch of destination BB#"
" from BB#"
" max delta="
" from "
" to "
" offset "
"\t"


<s> bool Cpu0SEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const Cpu0Subtarget & > ( MF . getSubtarget ( ) ) ; return Cpu0DAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> aarch64_svpattern aarch64_svpattern_for_vl ( machine_mode pred_mode , int vl ) { if ( vl < 0 ) return AARCH64_SV_ALL ; if ( maybe_gt ( vl , GET_MODE_NUNITS ( pred_mode ) ) ) return AARCH64_NUM_SVPATTERNS ; if ( vl >= 1 && vl <= 8 ) return aarch64_svpattern ( AARCH64_SV_VL1 + ( vl - 1 ) ) ; if ( vl >= 16 && vl <= 256 && pow2p_hwi ( vl ) ) return aarch64_svpattern ( AARCH64_SV_VL16 + ( exact_log2 ( vl ) - 4 ) ) ; int max_vl ; if ( GET_MODE_NUNITS ( pred_mode ) . is_constant ( & max_vl ) ) { if ( vl == ( max_vl / 3 ) * 3 ) return AARCH64_SV_MUL3 ; if ( vl == ( max_vl & - 4 ) ) return AARCH64_SV_MUL4 ; if ( vl == ( 1 << floor_log2 ( max_vl ) ) ) return AARCH64_SV_POW2 ; if ( vl == max_vl ) return AARCH64_SV_ALL ; } return AARCH64_NUM_SVPATTERNS ; } </s>

See if there is an svpattern that encodes an SVE predicate of mode PRED_MODE in which the first VL bits are set and the rest are clear . Return the pattern if so , otherwise return AARCH64_NUM_SVPATTERNS . A VL of -1 indicates an all-true vector .


"%qs attribute only applies to functions"

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


"Memory locations not expected for call return"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static unsigned int compute_vrsave_mask ( ) { unsigned int i , mask = 0 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( regs_ever_live [ i ] ) mask |= ALTIVEC_REG_BIT ( i ) ; if ( mask == 0 ) return mask ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( call_used_regs [ i ] ) mask |= ALTIVEC_REG_BIT ( i ) ; for ( i = cfun -> args_info . vregno ; i >= ALTIVEC_ARG_MIN_REG ; -- i ) mask &= ~ ALTIVEC_REG_BIT ( i ) ; { bool yes = false ; diddle_return_value ( is_altivec_return_reg , & yes ) ; if ( yes ) mask &= ~ ALTIVEC_REG_BIT ( ALTIVEC_ARG_RETURN ) ; } return mask ; } </s>

Return a 32-bit mask of the AltiVec registers we need to set in VRSAVE . Bit n of the return value is 1 if Vn is live . The MSB in the 32-bit word is 0 .


<s> enum direction pa_function_arg_padding ( machine_mode mode , const_tree type ) { if ( mode == BLKmode || ( TARGET_64BIT && type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( int_size_in_bytes ( type ) * BITS_PER_UNIT ) % PARM_BOUNDARY == 0 ) return none ; if ( TARGET_64BIT ) return upward ; else return downward ; } if ( GET_MODE_BITSIZE ( mode ) < PARM_BOUNDARY ) return downward ; else return none ; } </s>


<s> bool ARMAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a00000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & 1 ) OW -> Write8 ( 0 ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % 4 ) { default : break ; case 1 : OW -> Write8 ( 0 ) ; break ; case 2 : OW -> Write16 ( 0 ) ; break ; case 3 : OW -> Write16 ( 0 ) ; OW -> Write8 ( 0xa0 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> rtx function_expander :: expand ( ) { unsigned int nargs = call_expr_nargs ( call_expr ) ; args . reserve ( nargs ) ; for ( unsigned int i = 0 ; i < nargs ; ++ i ) args . quick_push ( expand_normal ( CALL_EXPR_ARG ( call_expr , i ) ) ) ; return base -> expand ( * this ) ; } </s>


<s>
static
unsigned
getHashValue
(
const
MemOpKey
&
Val
)
{
assert
(
Val
.
Disp
!=
PtrInfo
::
getEmptyKey
(
)
&&
"Cannot hash the empty key"
)
;
assert
(
Val
.
Disp
!=
PtrInfo
::
getTombstoneKey
(
)
&&
"Cannot hash the tombstone key"
)
;
hash_code
Hash
=
hash_combine
(
*
Val
.
Operands
[
0
]
,
*
Val
.
Operands
[
1
]
,
*
Val
.
Operands
[
2
]
,
*
Val
.
Operands
[
3
]
)
;
switch
(
Val
.
Disp
->
getType
(
)
)
{
case
MachineOperand
::
MO_Immediate
:
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getIndex
(
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getSymbolName
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getGlobal
(
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getBlockAddress
(
)
)
;
break
;
case
MachineOperand
::
MO_MCSymbol
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getMCSymbol
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
Hash
=
hash_combine
(
Hash
,
Val
.
Disp
->
getMBB
(
)
)
;
break
;
default
:
llvm_unreachable
(
"Invalid address displacement operand"
)
;
}
return
(
unsigned
)
Hash
;
}
</s>

Using name and line to get hash value . It should already be mostly unique .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize ; } </s>

Return the maximum size of a call frame that must be allocated for an outgoing function call .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( AFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> const LEGInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createExecutionDependencyFixPass ( & X86 :: VR128XRegClass ) ) ; if ( UseVZeroUpper ) addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
STI
.
getSchedModel
(
)
,
&
STI
,
TII
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
.
begin
(
)
,
MLI
.
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool ARMPassConfig :: addInstSelector ( ) { addPass ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getTargetTriple ( ) . isOSBinFormatELF ( ) && TM -> Options . EnableFastISel ) addPass ( createARMGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> bool X86DAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { if ( OptLevel == CodeGenOpt :: None ) return false ; if ( ! N . hasOneUse ( ) ) return false ; if ( N . getOpcode ( ) != ISD :: LOAD ) return true ; if ( U == Root ) { switch ( U -> getOpcode ( ) ) { default : break ; case X86ISD :: ADD : case X86ISD :: SUB : case X86ISD :: AND : case X86ISD :: XOR : case X86ISD :: OR : case ISD :: ADD : case ISD :: ADDC : case ISD :: ADDE : case ISD :: AND : case ISD :: OR : case ISD :: XOR : { SDValue Op1 = U -> getOperand ( 1 ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( Imm -> getAPIntValue ( ) . isSignedIntN ( 8 ) ) return false ; if ( Op1 . getOpcode ( ) == X86ISD :: Wrapper ) { SDValue Val = Op1 . getOperand ( 0 ) ; if ( Val . getOpcode ( ) == ISD :: TargetGlobalTLSAddress ) return false ; } } } } return true ; } </s>

IsProfitableToFold - Returns true if it 's profitable to fold the specific operand node N of U during instruction selection that starts at Root .


<s> static bool canonicalize_vector_int_perm ( const struct expand_vec_perm_d * d , struct expand_vec_perm_d * nd ) { int i ; enum machine_mode mode = VOIDmode ; switch ( d -> vmode ) { case V16QImode : mode = V8HImode ; break ; case V32QImode : mode = V16HImode ; break ; case V64QImode : mode = V32HImode ; break ; case V8HImode : mode = V4SImode ; break ; case V16HImode : mode = V8SImode ; break ; case V32HImode : mode = V16SImode ; break ; case V4SImode : mode = V2DImode ; break ; case V8SImode : mode = V4DImode ; break ; case V16SImode : mode = V8DImode ; break ; default : return false ; } for ( i = 0 ; i < d -> nelt ; i += 2 ) if ( ( d -> perm [ i ] & 1 ) || d -> perm [ i + 1 ] != d -> perm [ i ] + 1 ) return false ; nd -> vmode = mode ; nd -> nelt = d -> nelt / 2 ; for ( i = 0 ; i < nd -> nelt ; i ++ ) nd -> perm [ i ] = d -> perm [ 2 * i ] / 2 ; if ( GET_MODE_INNER ( mode ) != DImode ) canonicalize_vector_int_perm ( nd , nd ) ; if ( nd != d ) { nd -> one_operand_p = d -> one_operand_p ; nd -> testing_p = d -> testing_p ; if ( d -> op0 == d -> op1 ) nd -> op0 = nd -> op1 = gen_lowpart ( nd -> vmode , d -> op0 ) ; else { nd -> op0 = gen_lowpart ( nd -> vmode , d -> op0 ) ; nd -> op1 = gen_lowpart ( nd -> vmode , d -> op1 ) ; } if ( d -> testing_p ) nd -> target = gen_raw_REG ( nd -> vmode , LAST_VIRTUAL_REGISTER + 1 ) ; else nd -> target = gen_reg_rtx ( nd -> vmode ) ; } return true ; } </s>

For V * [ QHS ] Imode permutations , check if the same permutation ca n't be performed in a 2x , 4x or 8x wider inner mode .


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , enum machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; enum machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case V2DFmode : case V2DImode : case V2SFmode : case V2SImode : return false ; case V4SFmode : case V4SImode : case V8HImode : case V4HImode : break ; case V16QImode : wmode = V8HImode ; goto widen ; case V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( INTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


<s> static rtx gen_frame_mem_offset ( machine_mode mode , rtx reg , int offset ) { return gen_frame_mem ( mode , gen_rtx_PLUS ( Pmode , reg , GEN_INT ( offset ) ) ) ; } </s>

Emit an offset memory reference suitable for a frame store , while converting to a valid addressing mode .


"Caller should have checked for a comparison"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & Fn . getSubtarget < AArch64Subtarget > ( ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegUnits . init ( * TRI ) ; UsedRegUnits . init ( * TRI ) ; DefinedInBB . init ( * TRI ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) { auto M = optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; Modified |= M ; } return Modified ; } </s>


<s> unsigned PPCTargetLowering :: getJumpTableEncoding ( ) const { if ( isJumpTableRelative ( ) ) return MachineJumpTableInfo :: EK_LabelDifference32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool X86FixupSetCCPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 4 > ToErase ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) != X86 :: SETCCr ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( 0 ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == X86 :: MOVZX32rr8 ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ; if ( ! FlagsDefMI ) continue ; if ( impUsesFlags ( FlagsDefMI ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ? & X86 :: GR32RegClass : & X86 :: GR32_ABCDRegClass ; unsigned ZeroReg = MRI -> createVirtualRegister ( RC ) ; unsigned InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( X86 :: MOV32r0 ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( X86 :: INSERT_SUBREG ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) ) . addImm ( X86 :: sub_8bit ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( 0 ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; } } for ( auto & I : ToErase ) I -> eraseFromParent ( ) ; return Changed ; } </s>


<s> static void mep_reload_pointer ( int regno , const char * symbol ) { rtx reg , sym ; if ( ! df_regs_ever_live_p ( regno ) && crtl -> is_leaf ) return ; reg = gen_rtx_REG ( SImode , regno ) ; sym = gen_rtx_SYMBOL_REF ( SImode , symbol ) ; emit_insn ( gen_movsi_topsym_s ( reg , sym ) ) ; emit_insn ( gen_movsi_botsym_s ( reg , reg , sym ) ) ; } </s>

Used for interrupt functions , which ca n't assume that $ tp and $ gp contain the correct pointers .


<s> int iq2000_adjust_insn_length ( rtx insn , int length ) { if ( simplejump_p ( insn ) || ( ( GET_CODE ( insn ) == JUMP_INSN || GET_CODE ( insn ) == CALL_INSN ) ) ) length += 4 ; return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file .


<s> long rs6000_const_f32_to_i32 ( rtx operand ) { long value ; const struct real_value * rv = CONST_DOUBLE_REAL_VALUE ( operand ) ; gcc_assert ( GET_MODE ( operand ) == SFmode ) ; REAL_VALUE_TO_TARGET_SINGLE ( * rv , value ) ; return value ; } </s>

Convert a SFmode constant to the integer bit pattern .


<s> bool aarch64_operands_ok_for_ldpstp ( rtx * operands , bool load , enum machine_mode mode ) { HOST_WIDE_INT offval_1 , offval_2 , msize ; enum reg_class rclass_1 , rclass_2 ; rtx mem_1 , mem_2 , reg_1 , reg_2 , base_1 , base_2 , offset_1 , offset_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; reg_1 = operands [ 0 ] ; reg_2 = operands [ 2 ] ; gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) ) return false ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; reg_1 = operands [ 1 ] ; reg_2 = operands [ 3 ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ; } if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO ( reg_2 ) ) ) rclass_2 = FP_REGS ; else rclass_2 = GENERAL_REGS ; if ( rclass_1 != rclass_2 ) return false ; return true ; } </s>

Given OPERANDS of consecutive load/store , check if we can merge them into ldp/stp . LOAD is true if they are load instructions . MODE is the mode of memory operands .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
||
STI
.
isTargetDarwin
(
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
for
(
size_t
R
=
0
;
R
<
ARM
::
GPRRegClass
.
getNumRegs
(
)
;
++
R
)
{
if
(
STI
.
isGPRegisterReserved
(
R
)
)
{
markSuperRegs
(
Reserved
,
ARM
::
R0
+
R
)
;
}
}
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
markSuperRegs
(
Reserved
,
ARM
::
ZR
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> DecodeStatus OR1KDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableOR1K32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> enum rtx_code ix86_reverse_condition ( enum rtx_code code , machine_mode mode ) { return ( mode == CCFPmode ? reverse_condition_maybe_unordered ( code ) : reverse_condition ( code ) ) ; } </s>


<s> static void sh_override_options_after_change ( void ) { if ( flag_align_loops && ! str_align_loops ) str_align_loops = optimize_size ? "2" : "4" ; parse_alignment_opts ( ) ; if ( flag_align_jumps && ! str_align_jumps ) str_align_jumps = "2" ; else if ( align_jumps . levels [ 0 ] . get_value ( ) < 2 ) str_align_jumps = "2" ; if ( flag_align_functions && ! str_align_functions ) str_align_functions = optimize_size ? "2" : "4" ; if ( TARGET_RELAX ) { parse_alignment_opts ( ) ; int min_align = MAX ( align_loops . levels [ 0 ] . get_value ( ) , align_jumps . levels [ 0 ] . get_value ( ) ) ; if ( min_align < 4 ) min_align = 4 ; if ( align_functions . levels [ 0 ] . get_value ( ) < min_align ) { char * r = XNEWVEC ( char , 16 ) ; sprintf ( r , "%d" , min_align ) ; str_align_functions = r ; } } } </s>


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool AArch64TargetLowering :: isReassocProfitable ( SelectionDAG & DAG , SDValue N0 , SDValue N1 ) const { if ( ! N0 . hasOneUse ( ) ) return false ; unsigned IID = getIntrinsicID ( N1 . getNode ( ) ) ; if ( IID == Intrinsic :: aarch64_neon_umull || N1 . getOpcode ( ) == AArch64ISD :: UMULL || IID == Intrinsic :: aarch64_neon_smull || N1 . getOpcode ( ) == AArch64ISD :: SMULL ) return N0 . getOpcode ( ) != ISD :: ADD ; return true ; } </s>

Control the following reassociation of operands : ( op ( op x , c1 ) , y ) - > ( op ( op x , y ) , c1 ) where N0 is ( op x , c1 ) and N1 is y .


<s> bool X86RegisterInfo :: isArgumentRegister ( const MachineFunction & MF , MCRegister Reg ) const { const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; const TargetRegisterInfo & TRI = * ST . getRegisterInfo ( ) ; auto IsSubReg = [ & ] ( MCRegister RegA , MCRegister RegB ) { return TRI . isSuperOrSubRegisterEq ( RegA , RegB ) ; } ; if ( ! ST . is64Bit ( ) ) return llvm :: any_of ( SmallVector < MCRegister > { X86 :: EAX , X86 :: ECX , X86 :: EDX } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) || ( ST . hasMMX ( ) && X86 :: VR64RegClass . contains ( Reg ) ) ; CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; if ( CC == CallingConv :: X86_64_SysV && IsSubReg ( X86 :: RAX , Reg ) ) return true ; if ( llvm :: any_of ( SmallVector < MCRegister > { X86 :: RDX , X86 :: RCX , X86 :: R8 , X86 :: R9 } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; if ( CC != CallingConv :: Win64 && llvm :: any_of ( SmallVector < MCRegister > { X86 :: RDI , X86 :: RSI } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; if ( ST . hasSSE1 ( ) && llvm :: any_of ( SmallVector < MCRegister > { X86 :: XMM0 , X86 :: XMM1 , X86 :: XMM2 , X86 :: XMM3 , X86 :: XMM4 , X86 :: XMM5 , X86 :: XMM6 , X86 :: XMM7 } , [ & ] ( MCRegister & RegA ) { return IsSubReg ( RegA , Reg ) ; } ) ) return true ; return false ; } </s>

isArgumentReg - Returns true if Reg can be used as an argument to a function .


<s> bool umips_save_restore_pattern_p ( bool save_p , rtx pattern ) { int n ; unsigned int i ; HOST_WIDE_INT first_offset = 0 ; rtx first_base = 0 ; unsigned int regmask = 0 ; for ( n = 0 ; n < XVECLEN ( pattern , 0 ) ; n ++ ) { rtx set , reg , mem , this_base ; HOST_WIDE_INT this_offset ; set = XVECEXP ( pattern , 0 , n ) ; if ( GET_CODE ( set ) != SET ) return false ; mem = save_p ? SET_DEST ( set ) : SET_SRC ( set ) ; if ( ! MEM_P ( mem ) || MEM_VOLATILE_P ( mem ) ) return false ; mips_split_plus ( XEXP ( mem , 0 ) , & this_base , & this_offset ) ; if ( ! REG_P ( this_base ) ) return false ; if ( n == 0 ) { if ( ! UMIPS_12BIT_OFFSET_P ( this_offset ) ) return false ; first_base = this_base ; first_offset = this_offset ; } else { if ( REGNO ( this_base ) != REGNO ( first_base ) || this_offset != first_offset + UNITS_PER_WORD * n ) return false ; } reg = save_p ? SET_SRC ( set ) : SET_DEST ( set ) ; if ( ! REG_P ( reg ) ) return false ; regmask |= 1 << REGNO ( reg ) ; } for ( i = 0 ; i < ARRAY_SIZE ( umips_swm_mask ) ; i ++ ) if ( regmask == umips_swm_mask [ i ] ) return true ; return false ; } </s>

Return true if PATTERN matches the kind of instruction generated by umips_build_save_restore . SAVE_P is true for store .


<s> static rtx gen_movdi_x ( rtx dest , rtx src , rtx offset ATTRIBUTE_UNUSED ) { return gen_movdi ( dest , src ) ; } </s>

Wrapper functions that discards the CONST_INT spill offset . These exist so that we can give gr_spill/gr_fill the offset they need and use a consistant function interface .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && MF . needsFrameMoves ( ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( isDestroy && InternalAmt && ! blockEndIsUnreachable ( MBB , I ) ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool ix86_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int flags ) { struct gcc_options func_options , func_options_set ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , "default" ) == 0 ) return true ; if ( ( DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) == target_attribute_cache [ 1 ] || DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) == NULL_TREE ) && ( DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) == target_attribute_cache [ 2 ] || DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) == NULL_TREE ) && simple_cst_list_equal ( args , target_attribute_cache [ 0 ] ) ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = target_attribute_cache [ 1 ] ; DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = target_attribute_cache [ 2 ] ; return true ; } tree old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , 0 , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; tree old_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( old_target == NULL_TREE ) old_target = target_option_default_node ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( old_target ) ) ; new_target = ix86_valid_target_attribute_tree ( fndecl , args , & func_options , & func_options_set , flags == 1 ) ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; if ( new_target == error_mark_node ) ret = false ; else if ( new_target ) { if ( DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) == NULL_TREE && DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) == NULL_TREE ) { target_attribute_cache [ 0 ] = copy_list ( args ) ; target_attribute_cache [ 1 ] = new_target ; target_attribute_cache [ 2 ] = old_optimize != new_optimize ? new_optimize : NULL_TREE ; } DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> virtual const ARMFrameInfo * getFrameInfo ( ) const { return FrameInfo . get ( ) ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s>
void
PPCInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLWINM
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
MB
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
bool
useSubstituteMnemonic
=
false
;
if
(
SH
<=
31
&&
MB
==
0
&&
ME
==
(
31
SH
)
)
{
O
<<
"\tslwi "
;
useSubstituteMnemonic
=
true
;
}
if
(
SH
<=
31
&&
MB
==
(
32
SH
)
&&
ME
==
31
)
{
O
<<
"\tsrwi "
;
useSubstituteMnemonic
=
true
;
SH
=
32
SH
;
}
if
(
useSubstituteMnemonic
)
{
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
}
if
(
(
MI
->
getOpcode
(
)
==
PPC
::
OR
||
MI
->
getOpcode
(
)
==
PPC
::
OR8
)
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
O
<<
"\tmr "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLDICR
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
63
SH
==
ME
)
{
O
<<
"\tsldi "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
}
if
(
MI
->
getOpcode
(
)
==
TargetOpcode
::
COPY_TO_REGCLASS
)
return
;
printInstruction
(
MI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


getTargetNodeName - This method returns the name of a target specific


<s> Register VEInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { VEMachineFunctionInfo * VEFI = MF -> getInfo < VEMachineFunctionInfo > ( ) ; Register GlobalBaseReg = VEFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; GlobalBaseReg = VE :: SX15 ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( VE :: GETGOT ) , GlobalBaseReg ) ; VEFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

VE VE VE VE VE VE 0 VE::SX15 VE::GETGOT VE


<s> void function_builder :: add_unique_function ( const function_instance & instance , tree return_type , vec < tree > & argument_types , uint64_t required_extensions , bool force_direct_overloads ) { char * name = get_name ( instance , false ) ; tree fntype = build_function_type_array ( return_type , argument_types . length ( ) , argument_types . address ( ) ) ; tree attrs = get_attributes ( instance ) ; registered_function & rfn = add_function ( instance , name , fntype , attrs , required_extensions , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! * rfn_slot ) ; * rfn_slot = & rfn ; if ( m_direct_overloads || force_direct_overloads ) { char * overload_name = get_name ( instance , true ) ; if ( strcmp ( name , overload_name ) != 0 ) { tree attrs = get_attributes ( instance ) ; add_function ( instance , overload_name , fntype , attrs , required_extensions , false ) ; } } obstack_free ( & m_string_obstack , name ) ; } </s>

Add a built-in function for INSTANCE , with the argument types given by ARGUMENT_TYPES and the return type given by RETURN_TYPE . NAME is the `` full '' name for C function . OVERLOAD_NAME is the `` short '' name for C++ overloaded function . OVERLOAD_NAME can be nullptr because some instance does n't have C++ overloaded function .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


"LVI load hardening is only supported on 64-bit"

runOnMachineFunction - Emit the function body .


<s> bool forceScalarizeMaskedScatter ( VectorType * VTy , Align Alignment ) { return forceScalarizeMaskedGather ( VTy , Alignment ) ; } </s>

Return true if the target forces scalarizing of llvm.masked.scatter intrinsics .


<s> unsigned ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 32 ) return 4 ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void X86AsmPrinter :: emitBasicBlockEnd ( const MachineBasicBlock & MBB ) { if ( Subtarget -> hardenSlsRet ( ) || Subtarget -> hardenSlsIJmp ( ) ) { auto I = MBB . getLastNonDebugInstr ( ) ; if ( I != MBB . end ( ) ) { if ( ( Subtarget -> hardenSlsRet ( ) && isSimpleReturn ( * I ) ) || ( Subtarget -> hardenSlsIJmp ( ) && isIndirectBranchOrTailCall ( * I ) ) ) { MCInst TmpInst ; TmpInst . setOpcode ( X86 :: INT3 ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } } } AsmPrinter :: emitBasicBlockEnd ( MBB ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; } </s>

Targets can override this to emit stuff at the end of a basic block .


"the default AIX Altivec ABI is not yet "


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & ARM :: tGPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget . is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> void OR1KInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>


<s> void PPCHazardRecognizer970 :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugInstr ( ) ) return ; unsigned Opcode = MI -> getOpcode ( ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; PPCII :: PPC970_Unit InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == PPCII :: PPC970_Pseudo ) return ; if ( Opcode == PPC :: MTCTR || Opcode == PPC :: MTCTR8 ) HasCTRSet = true ; if ( isStore && NumStores < 4 && ! MI -> memoperands_empty ( ) ) { MachineMemOperand * MO = * MI -> memoperands_begin ( ) ; StoreSize [ NumStores ] = MO -> getSize ( ) ; StoreOffset [ NumStores ] = MO -> getOffset ( ) ; StoreValue [ NumStores ] = MO -> getValue ( ) ; ++ NumStores ; } if ( InstrType == PPCII :: PPC970_BRU || isSingle ) NumIssued = 4 ; ++ NumIssued ; if ( isCracked ) ++ NumIssued ; if ( NumIssued == 5 ) EndDispatchGroup ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> HOST_WIDE_INT ix86_convert_const_vector_to_integer ( rtx op , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) gcc_unreachable ( ) ; int nunits = GET_MODE_NUNITS ( mode ) ; wide_int val = wi :: zero ( GET_MODE_BITSIZE ( mode ) ) ; machine_mode innermode = GET_MODE_INNER ( mode ) ; unsigned int innermode_bits = GET_MODE_BITSIZE ( innermode ) ; switch ( mode ) { case E_V2QImode : case E_V4QImode : case E_V2HImode : case E_V8QImode : case E_V4HImode : case E_V2SImode : for ( int i = 0 ; i < nunits ; ++ i ) { int v = INTVAL ( XVECEXP ( op , 0 , i ) ) ; wide_int wv = wi :: shwi ( v , innermode_bits ) ; val = wi :: insert ( val , wv , innermode_bits * i , innermode_bits ) ; } break ; case E_V2HFmode : case E_V2BFmode : case E_V4HFmode : case E_V4BFmode : case E_V2SFmode : for ( int i = 0 ; i < nunits ; ++ i ) { rtx x = XVECEXP ( op , 0 , i ) ; int v = real_to_target ( NULL , CONST_DOUBLE_REAL_VALUE ( x ) , REAL_MODE_FORMAT ( innermode ) ) ; wide_int wv = wi :: shwi ( v , innermode_bits ) ; val = wi :: insert ( val , wv , innermode_bits * i , innermode_bits ) ; } break ; default : gcc_unreachable ( ) ; } return val . to_shwi ( ) ; } </s>

Return HOST_WIDE_INT for const vector OP in MODE .


<s> const MCPhysReg * MMIXRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> bool X86WinAllocaExpander :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasWinAlloca ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; STI = & MF . getSubtarget < X86Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; StackPtr = TRI -> getStackRegister ( ) ; SlotSize = TRI -> getSlotSize ( ) ; StackProbeSize = 4096 ; if ( MF . getFunction ( ) . hasFnAttribute ( "stack-probe-size" ) ) { MF . getFunction ( ) . getFnAttribute ( "stack-probe-size" ) . getValueAsString ( ) . getAsInteger ( 0 , StackProbeSize ) ; } LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ; return true ; } </s>


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , 0 ) , false ) ) return true ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasQPX ( false ) , HasFSQRT ( false ) , HasFRE ( false ) , HasFRES ( false ) , HasFRSQRTE ( false ) , HasFRSQRTES ( false ) , HasRecipPrec ( false ) , HasSTFIWX ( false ) , HasLFIWAX ( false ) , HasFPRND ( false ) , HasFPCVT ( false ) , HasISEL ( false ) , HasPOPCNTD ( false ) , HasLDBRX ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = "+64bit," + FullFS ; else FullFS = "+64bit" ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) ) StackAlignment = 32 ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool ComplexPatternFuncMutatesDAG ( ) const override { return true ; } </s>

Return true if complex patterns for this target can mutate the DAG .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>


<s> static bool arm_return_in_msb ( const_tree valtype ) { return ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || FIXED_POINT_TYPE_P ( valtype ) ) ) ; } </s>

Values which must be returned in the most-significant end of the return register .


<s> void AArch64InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s> bool csky_simple_addr_operand_p ( rtx op ) { struct csky_address addr ; if ( ! decompose_csky_address ( op , & addr ) ) return false ; if ( addr . disp && GET_CODE ( addr . disp ) == UNSPEC ) return false ; if ( ! addr . index && ! addr . symbol ) return true ; return false ; } </s>

Helper function for the csky_simple_mem_operand predicate . Returns true if OP is an address of the form reg + displacement .


<s> static enum rtx_code ix86_prepare_fp_compare_args ( enum rtx_code code , rtx * pop0 , rtx * pop1 ) { bool unordered_compare = ix86_unordered_fp_compare ( code ) ; rtx op0 = * pop0 , op1 = * pop1 ; machine_mode op_mode = GET_MODE ( op0 ) ; bool is_sse = SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( op_mode ) ; if ( ! is_sse && ( unordered_compare || ( op_mode == XFmode && ! ( standard_80387_constant_p ( op0 ) == 1 || standard_80387_constant_p ( op1 ) == 1 ) && GET_CODE ( op1 ) != FLOAT ) || ix86_fp_comparison_strategy ( code ) == IX86_FPCMP_COMI ) ) { op0 = force_reg ( op_mode , op0 ) ; op1 = force_reg ( op_mode , op1 ) ; } else { if ( standard_80387_constant_p ( op0 ) == 0 || ( MEM_P ( op0 ) && ! ( standard_80387_constant_p ( op1 ) == 0 || MEM_P ( op1 ) ) ) ) { enum rtx_code new_code = ix86_fp_swap_condition ( code ) ; if ( new_code != UNKNOWN ) { std :: swap ( op0 , op1 ) ; code = new_code ; } } if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == 0 ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == 1 ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( REG_P ( op1 ) || can_create_pseudo_p ( ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; } * pop0 = op0 ; * pop1 = op1 ; return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to a fp comparison . The operands are updated in place ; the new comparsion code is returned .


<s> unsigned SystemZTTIImpl :: getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( ! Vector ) return 14 ; if ( ST -> hasVector ( ) ) return 32 ; return 0 ; } </s>


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func -> hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool aarch64_prepare_sve_int_fma ( rtx * operands , rtx_code code ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( rtx shifts = aarch64_convert_mult_to_shift ( operands [ 2 ] , code ) ) { rtx product = expand_binop ( mode , vashl_optab , operands [ 1 ] , shifts , NULL_RTX , true , OPTAB_DIRECT ) ; force_expand_binop ( mode , code == PLUS ? add_optab : sub_optab , operands [ 3 ] , product , operands [ 0 ] , true , OPTAB_DIRECT ) ; return true ; } operands [ 2 ] = force_reg ( mode , operands [ 2 ] ) ; return false ; } </s>

Prepare for an integer SVE multiply-add or multiply-subtract pattern ; CODE is PLUS for the former and MINUS for the latter . OPERANDS is the operands array , in the same order as for fma_optab . Return true if the function emitted all the necessary instructions , false if the caller should generate the pattern normally with the new OPERANDS array .


<s> StackOffset VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( ! hasFP ( MF ) ) { FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } if ( RegInfo -> hasStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = VE :: SX17 ; else FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } </s>


<s> bool Thumb1FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_PORTABLE_RUNTIME ) return false ; if ( TARGET_ELF32 ) return ( decl != NULL_TREE ) ; if ( TARGET_64BIT ) return false ; return ( decl && ! TREE_PUBLIC ( decl ) ) ; } </s>

Only direct calls to static functions are allowed to be sibling ( tail ) call optimized . This restriction is necessary because some linker generated stubs will store return pointers into rp ' in some cases which might clobber a live value already in rp ' . In a sibcall the current function and the target function share stack space . Thus if the path to the current function and the path to the target function save a value in rp ' , they save the value into the same stack slot , which has undesirable consequences . Because of the deferred binding nature of shared libraries any function with external scope could be in a different load module and thus require rp ' to be saved when calling that function . So sibcall optimizations can only be safe for static function . Note that GCC never needs return value relocations , so we do n't have to worry about static calls with return value relocations ( which require saving rp ' ) . It is safe to perform a sibcall optimization when the target function will never return .


Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


<s> static int arm_effective_regno ( rtx op , bool strict ) { gcc_assert ( REG_P ( op ) ) ; if ( ! strict || REGNO ( op ) < FIRST_PSEUDO_REGISTER || ! reg_renumber || reg_renumber [ REGNO ( op ) ] < 0 ) return REGNO ( op ) ; return reg_renumber [ REGNO ( op ) ] ; } </s>

In non-STRICT mode , return the register number ; in STRICT mode return the hard regno or the replacement if it wo n't be a mem . Otherwise , return the original pseudo number .


<s> int X86InstrInfo :: getSPAdjust ( const MachineInstr & MI ) const { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( MI . getOpcode ( ) == getCallFrameSetupOpcode ( ) || MI . getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { unsigned StackAlign = TFI -> getStackAlignment ( ) ; int SPAdj = ( MI . getOperand ( 0 ) . getImm ( ) + StackAlign - 1 ) / StackAlign * StackAlign ; SPAdj -= MI . getOperand ( 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == getCallFrameSetupOpcode ( ) ) return SPAdj ; else return - SPAdj ; } if ( MI . isCall ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return 0 ; return - ( I -> getOperand ( 1 ) . getImm ( ) ) ; } switch ( MI . getOpcode ( ) ) { default : return 0 ; case X86 :: PUSH32i8 : case X86 :: PUSH32r : case X86 :: PUSH32rmm : case X86 :: PUSH32rmr : case X86 :: PUSHi32 : return 4 ; case X86 :: PUSH64i8 : case X86 :: PUSH64r : case X86 :: PUSH64rmm : case X86 :: PUSH64rmr : case X86 :: PUSH64i32 : return 8 ; } } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


<s>
static
void
x86_print_call_or_nop
(
FILE
*
file
,
const
char
*
target
)
{
if
(
flag_nop_mcount
||
!
strcmp
(
target
,
"nop"
)
)
fprintf
(
file
,
"1:"
ASM_BYTE
"0x0f, 0x1f, 0x44, 0x00, 0x00\n"
)
;
else
fprintf
(
file
,
"1:\tcall\t%s\n"
,
target
)
;
}
</s>


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
llvm
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> void ia64_emit_cond_move ( rtx op0 , rtx op1 , rtx cond ) { rtx_insn * insn , * first = get_last_insn ( ) ; emit_move_insn ( op0 , op1 ) ; for ( insn = get_last_insn ( ) ; insn != first ; insn = PREV_INSN ( insn ) ) if ( INSN_P ( insn ) ) PATTERN ( insn ) = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , PATTERN ( insn ) ) ; } </s>

Split a move from OP1 to OP0 conditional on COND .


"Virtual function multiversioning not supported"

Generate the dispatching code body to dispatch multi-versioned function DECL . The target hook is called to process the `` target '' attributes and provide the code to dispatch the right function at run-time . NODE points to the dispatcher decl whose body will be created .


<s> int aarch64_vec_fpconst_pow_of_2 ( rtx x ) { int nelts ; if ( GET_CODE ( x ) != CONST_VECTOR || ! CONST_VECTOR_NUNITS ( x ) . is_constant ( & nelts ) ) return - 1 ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) != MODE_VECTOR_FLOAT ) return - 1 ; int firstval = aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , 0 ) ) ; if ( firstval <= 0 ) return - 1 ; for ( int i = 1 ; i < nelts ; i ++ ) if ( aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , i ) ) != firstval ) return - 1 ; return firstval ; } </s>

If X is a vector of equal CONST_DOUBLE values and that value is Y , return the aarch64_fpconst_pow_of_2 of Y . Otherwise return -1 .


<s>
const
char
*
nds32_output_casesi_pc_relative
(
rtx
*
operands
)
{
machine_mode
mode
;
rtx
diff_vec
;
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
1
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
output_asm_insn
(
"la\t$ta, %l1"
,
operands
)
;
mode
=
GET_MODE
(
diff_vec
)
;
switch
(
mode
)
{
case
QImode
:
output_asm_insn
(
"lb\t%2, [$ta + %0 << 0]"
,
operands
)
;
break
;
case
HImode
:
output_asm_insn
(
"lh\t%2, [$ta + %0 << 1]"
,
operands
)
;
break
;
case
SImode
:
output_asm_insn
(
"lw\t%2, [$ta + %0 << 2]"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
output_asm_insn
(
"add\t$ta, %2, $ta"
,
operands
)
;
if
(
TARGET_16_BIT
)
return
"jr5\t$ta"
;
else
return
"jr\t$ta"
;
}
</s>

Function to generate PC relative jump table . Refer to nds32.md for more details . The following is the sample for the case that diff value can be presented in '.short ' size . addi $ r1 , $ r1 , - ( case_lower_bound ) slti $ ta , $ r1 , ( case_number ) beqz $ ta , .L_skip_label la $ ta , .L35 ! get jump table address lh $ r1 , [ $ ta + $ r1 < < 1 ] ! load symbol diff from jump table entry addi $ ta , $ r1 , $ ta jr5 $ ta ! jump table entry L35 : .short .L25-.L35 .short .L26-.L35 .short .L27-.L35 .short .L28-.L35 .short .L29-.L35 .short .L30-.L35 .short .L31-.L35 .short .L32-.L35 .short .L33-.L35 .short .L34-.L35


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) { emit_insn ( gen_aarch64_load_exclusive ( mode , rval , mem , model_rtx ) ) ; } </s>