<s> bool AArch64_MC :: isFpOrNEON ( const MCInst & MI , const MCInstrInfo * MCII ) { const auto & FPR128 = AArch64MCRegisterClasses [ AArch64 :: FPR128RegClassID ] ; const auto & FPR64 = AArch64MCRegisterClasses [ AArch64 :: FPR64RegClassID ] ; const auto & FPR32 = AArch64MCRegisterClasses [ AArch64 :: FPR32RegClassID ] ; const auto & FPR16 = AArch64MCRegisterClasses [ AArch64 :: FPR16RegClassID ] ; const auto & FPR8 = AArch64MCRegisterClasses [ AArch64 :: FPR8RegClassID ] ; auto IsFPR = [ & ] ( const MCOperand & Op ) { if ( ! Op . isReg ( ) ) return false ; auto Reg = Op . getReg ( ) ; return FPR128 . contains ( Reg ) || FPR64 . contains ( Reg ) || FPR32 . contains ( Reg ) || FPR16 . contains ( Reg ) || FPR8 . contains ( Reg ) ; } ; return llvm :: any_of ( MI , IsFPR ) ; } </s>

Returns whether the instruction is FP or NEON .


<s> rtx legitimize_tls_address ( rtx x , rtx reg ) { rtx dest , tp , label , labelno , sum , insns , ret , eqv , addend ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; } return dest ; case TLS_MODEL_LOCAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? 8 : 4 ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; reg = force_reg ( SImode , gen_rtx_CONST ( SImode , reg ) ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; default : abort ( ) ; } } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> static int ix86_register_move_cost ( machine_mode mode , reg_class_t class1_i , reg_class_t class2_i ) { enum reg_class class1 = ( enum reg_class ) class1_i ; enum reg_class class2 = ( enum reg_class ) class2_i ; if ( inline_secondary_memory_needed ( class1 , class2 , mode , 0 ) ) { int cost = 1 ; cost += inline_memory_move_cost ( mode , class1 , 2 ) ; cost += inline_memory_move_cost ( mode , class2 , 2 ) ; if ( targetm . class_max_nregs ( class1 , mode ) > targetm . class_max_nregs ( class2 , mode ) ) cost += 20 ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += 20 ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) || SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return MAX ( 8 , ix86_cost -> mmxsse_to_integer ) ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> fp_move ; if ( MAYBE_SSE_CLASS_P ( class1 ) ) return ix86_cost -> sse_move ; if ( MAYBE_MMX_CLASS_P ( class1 ) ) return ix86_cost -> mmx_move ; return 2 ; } </s>

Return the cost of moving data from a register in class CLASS1 to one in class CLASS2 . It is not required that the cost always equal 2 when FROM is the same as TO ; on some machines it is expensive to move between registers if they are not general registers .


<s> TargetTransformInfo AArch64TargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( AArch64TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> static bool loongarch_in_small_data_p ( const_tree decl ) { int size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( VAR_P ( decl ) && DECL_SECTION_NAME ( decl ) != 0 ) { const char * name ; name = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( name , ".sdata" ) != 0 && strcmp ( name , ".sbss" ) != 0 ) return false ; if ( ! DECL_EXTERNAL ( decl ) ) return true ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return size > 0 && size <= g_switch_value ; } </s>


<s> static bool nds32_sp_base_or_plus_load_store_p ( rtx_insn * insn ) { rtx mem_src = NULL_RTX ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : mem_src = SET_SRC ( PATTERN ( insn ) ) ; break ; case TYPE_STORE : mem_src = SET_DEST ( PATTERN ( insn ) ) ; break ; default : break ; } if ( mem_src != NULL_RTX ) { if ( ( GET_CODE ( mem_src ) == ZERO_EXTEND ) || ( GET_CODE ( mem_src ) == SIGN_EXTEND ) ) mem_src = XEXP ( mem_src , 0 ) ; if ( ( GET_CODE ( XEXP ( mem_src , 0 ) ) == PLUS ) ) mem_src = XEXP ( mem_src , 0 ) ; if ( REG_P ( XEXP ( mem_src , 0 ) ) && ( ( frame_pointer_needed && REGNO ( XEXP ( mem_src , 0 ) ) == FP_REGNUM ) || REGNO ( XEXP ( mem_src , 0 ) ) == SP_REGNUM ) ) return true ; } return false ; } </s>

Return true if insn is a sp/fp base or sp/fp plus load-store instruction .


Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts.\ The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM and then branches to the specified routine . This code template is copied from text segment to stack location and then patched with pa_trampoline_init to contain valid values , and then entered as a subroutine . It is best to keep this as small as possible to avoid having to flush multiple lines in the cache .


<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> perm . length ( ) ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev64v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev32v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev32v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev64v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev64v4hi ; break ; case E_V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case E_V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev16v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev16v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev32v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev32v4hi ; break ; case E_V4SImode : gen = gen_neon_vrev64v4si ; break ; case E_V2SImode : gen = gen_neon_vrev64v2si ; break ; case E_V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case E_V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s>
void
MipsRegisterBankInfo
::
applyMappingImpl
(
const
OperandsMapper
&
OpdMapper
)
const
{
MachineInstr
&
MI
=
OpdMapper
.
getMI
(
)
;
InstListTy
NewInstrs
;
MachineIRBuilder
B
(
MI
)
;
MachineFunction
*
MF
=
MI
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
OpdMapper
.
getMRI
(
)
;
InstManager
NewInstrObserver
(
NewInstrs
)
;
GISelObserverWrapper
WrapperObserver
(
&
NewInstrObserver
)
;
LegalizerHelper
Helper
(
*
MF
,
WrapperObserver
,
B
)
;
LegalizationArtifactCombiner
ArtCombiner
(
B
,
MF
->
getRegInfo
(
)
,
*
MF
->
getSubtarget
(
)
.
getLegalizerInfo
(
)
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
case
TargetOpcode
::
G_PHI
:
case
TargetOpcode
::
G_SELECT
:
{
Helper
.
narrowScalar
(
MI
,
0
,
LLT
::
scalar
(
32
)
)
;
while
(
!
NewInstrs
.
empty
(
)
)
{
MachineInstr
*
NewMI
=
NewInstrs
.
pop_back_val
(
)
;
if
(
NewMI
->
getOpcode
(
)
==
TargetOpcode
::
G_UNMERGE_VALUES
)
{
SmallVector
<
MachineInstr
*
,
2
>
DeadInstrs
;
ArtCombiner
.
tryCombineMerges
(
*
NewMI
,
DeadInstrs
)
;
for
(
MachineInstr
*
DeadMI
:
DeadInstrs
)
DeadMI
->
eraseFromParent
(
)
;
}
else
if
(
NewMI
->
getOpcode
(
)
==
TargetOpcode
::
G_MERGE_VALUES
)
continue
;
else
for
(
auto
Op
:
NewMI
->
operands
(
)
)
{
if
(
Op
.
isReg
(
)
)
{
assert
(
MRI
.
getType
(
Op
.
getReg
(
)
)
.
getSizeInBits
(
)
==
32
&&
"Only 32 bit gprb is handled here.\n"
)
;
MRI
.
setRegBank
(
Op
.
getReg
(
)
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
}
}
}
return
;
}
case
TargetOpcode
::
G_UNMERGE_VALUES
:
{
SmallVector
<
MachineInstr
*
,
2
>
DeadInstrs
;
ArtCombiner
.
tryCombineMerges
(
MI
,
DeadInstrs
)
;
for
(
MachineInstr
*
DeadMI
:
DeadInstrs
)
DeadMI
->
eraseFromParent
(
)
;
return
;
}
default
:
break
;
}
return
applyDefaultMapping
(
OpdMapper
)
;
}
</s>


<s> StringRef ARM64NamedImmMapper :: toString ( uint32_t Value , bool & Valid ) const { for ( unsigned i = 0 ; i < NumPairs ; ++ i ) { if ( Pairs [ i ] . Value == Value ) { Valid = true ; return Pairs [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createARMWinCOFFObjectWriter ( OS , false ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void arm_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { enum memmodel model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; rtx_code_label * label ; rtx x ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( model ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_release ( model ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_acquire ( model ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , 0 ) ; arm_emit_load_exclusive ( mode , old_out , mem , use_acquire ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } case PLUS : if ( mode == DImode ) { emit_move_insn ( new_out , old_out ) ; if ( code == PLUS ) x = gen_adddi3 ( new_out , new_out , value ) ; else x = gen_subdi3 ( new_out , new_out , value ) ; emit_insn ( x ) ; break ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; } arm_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , use_release ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , cond , const0_rtx , label ) ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( model ) ; } </s>

Split an atomic operation pattern . Operation is given by CODE and is one of PLUS , MINUS , IOR , XOR , SET ( for an exchange operation ) or NOT ( for a nand operation ) . Operation is performed on the content at MEM and on VALUE following the memory model MODEL_RTX . The content at MEM before and after the operation is returned in OLD_OUT and NEW_OUT respectively while the success of the operation is returned in COND . Using a scratch register or an operand register for these determines what result is returned for that pattern .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( doMergeWithPrevious && PI != MBB . begin ( ) && PI -> isCFIInstruction ( ) ) PI = std :: prev ( PI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = PI -> getOperand ( 2 ) . getImm ( ) ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset = PI -> getOperand ( 4 ) . getImm ( ) ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = - PI -> getOperand ( 2 ) . getImm ( ) ; } else return 0 ; PI = MBB . erase ( PI ) ; if ( PI != MBB . end ( ) && PI -> isCFIInstruction ( ) ) { auto CIs = MBB . getParent ( ) -> getFrameInstructions ( ) ; MCCFIInstruction CI = CIs [ PI -> getOperand ( 0 ) . getCFIIndex ( ) ] ; if ( CI . getOperation ( ) == MCCFIInstruction :: OpDefCfaOffset ) PI = MBB . erase ( PI ) ; } if ( ! doMergeWithPrevious ) MBBI = skipDebugInstructionsForward ( PI , MBB . end ( ) ) ; return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> static unsigned int aarch64_autovectorize_vector_sizes ( void ) { return ( 16 | 8 ) ; } </s>

Return a list of possible vector sizes for the vectorizer to iterate over .


<s> Optional < Value * > AArch64TTIImpl :: simplifyDemandedVectorEltsIntrinsic ( InstCombiner & IC , IntrinsicInst & II , APInt OrigDemandedElts , APInt & UndefElts , APInt & UndefElts2 , APInt & UndefElts3 , std :: function < void ( Instruction * , unsigned , APInt , APInt & ) > SimplifyAndSetOp ) const { switch ( II . getIntrinsicID ( ) ) { default : break ; case Intrinsic :: aarch64_neon_fcvtxn : case Intrinsic :: aarch64_neon_rshrn : case Intrinsic :: aarch64_neon_sqrshrn : case Intrinsic :: aarch64_neon_sqrshrun : case Intrinsic :: aarch64_neon_sqshrn : case Intrinsic :: aarch64_neon_sqshrun : case Intrinsic :: aarch64_neon_sqxtn : case Intrinsic :: aarch64_neon_sqxtun : case Intrinsic :: aarch64_neon_uqrshrn : case Intrinsic :: aarch64_neon_uqshrn : case Intrinsic :: aarch64_neon_uqxtn : SimplifyAndSetOp ( & II , 0 , OrigDemandedElts , UndefElts ) ; break ; } return None ; } </s>

Can be used to implement target-specific instruction combining .


Function that may creates more instructions for large value on adjusting stack pointer . In nds32 target , 'addi ' can be used for stack pointer adjustment in prologue/epilogue stage . However , sometimes there are too many local variables so that the adjustment value is not able to be fit in the 'addi ' instruction . One solution is to move value into a register and then use 'add ' instruction . In practice , we use TA_REGNUM ( $ r15 ) to accomplish this purpose . Also , we need to return zero for sp adjustment so that proglogue/epilogue knows there is no need to create 'addi ' instruction .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP , Mips :: FP , Mips :: RA } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 , Mips :: FP_64 , Mips :: RA_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegisterClass -> begin ( ) ; Reg != Mips :: AFGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegisterClass -> begin ( ) ; Reg != Mips :: CPU64RegsRegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegisterClass -> begin ( ) ; Reg != Mips :: FGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegFixed ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool isFPImm ( ) const { return Kind == k_FPImmediate ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> bool X86InstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI . getOpcode ( ) ) ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .


<s> static void ia64_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == 4 || size == 8 ) ; if ( size == 4 ) fputs ( "\tdata4.ua\t@dtprel(" , file ) ; else fputs ( "\tdata8.ua\t@dtprel(" , file ) ; output_addr_const ( file , x ) ; fputs ( ")" , file ) ; } </s>

This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> bool check ( function_checker & c ) const OVERRIDE { return c . require_immediate_range ( 2 , 0 , 7 ) ; } </s>

Perform semantic checks on the call . Return true if the call is valid , otherwise report a suitable error .


"getBranchTargetOpValue is not implemented yet"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


Implement the TARGET_CPU_CPP_BUILTINS macro


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


<s>
bool
aarch64_process_target_attr
(
tree
args
,
const
char
*
pragma_or_attr
)
{
if
(
TREE_CODE
(
args
)
==
TREE_LIST
)
{
do
{
tree
head
=
TREE_VALUE
(
args
)
;
if
(
head
)
{
if
(
!
aarch64_process_target_attr
(
head
,
pragma_or_attr
)
)
return
false
;
}
args
=
TREE_CHAIN
(
args
)
;
}
while
(
args
)
;
return
true
;
}
gcc_assert
(
TREE_CODE
(
args
)
==
STRING_CST
)
;
size_t
len
=
strlen
(
TREE_STRING_POINTER
(
args
)
)
;
char
*
str_to_check
=
(
char
*
)
alloca
(
len
+
1
)
;
strcpy
(
str_to_check
,
TREE_STRING_POINTER
(
args
)
)
;
if
(
len
==
0
)
{
error
(
"malformed target %s value"
,
pragma_or_attr
)
;
return
false
;
}
unsigned
int
num_commas
=
num_occurences_in_str
(
','
,
str_to_check
)
;
char
*
token
=
strtok
(
str_to_check
,
","
)
;
unsigned
int
num_attrs
=
0
;
while
(
token
)
{
num_attrs
++
;
if
(
!
aarch64_process_one_target_attr
(
token
,
pragma_or_attr
)
)
{
error
(
"target %s %qs is invalid"
,
pragma_or_attr
,
token
)
;
return
false
;
}
token
=
strtok
(
,
","
)
;
}
if
(
num_attrs
!=
num_commas
+
1
)
{
error
(
"malformed target %s list %qs"
,
pragma_or_attr
,
TREE_STRING_POINTER
(
args
)
)
;
return
false
;
}
return
true
;
}
</s>

Parse the tree in ARGS that contains the target attribute information and update the global target options space . PRAGMA_OR_ATTR is a string to be used in error messages , specifying whether this is processing a target attribute or a target pragma .


<s> static bool has_dispatch ( rtx_insn * insn , int action ) { if ( ( TARGET_BDVER1 || TARGET_BDVER2 || TARGET_BDVER3 || TARGET_BDVER4 || TARGET_ZNVER1 ) && flag_dispatch_scheduler ) switch ( action ) { default : return false ; case IS_DISPATCH_ON : return true ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ; } return false ; } </s>

Return TRUE if Dispatch Scheduling is supported .


<s> bool VERegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { switch ( PhysReg ) { case VE :: VM0 : case VE :: VMP0 : return true ; default : return false ; } } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F , PromotionCacheTy & PromotionCache ) { SmallVector < UpdateRecord , 64 > Updates ; for ( Instruction & I : instructions ( & F ) ) { for ( Use & U : I . operands ( ) ) { Constant * Cst = dyn_cast < Constant > ( U ) ; if ( ! Cst || isa < GlobalValue > ( Cst ) || ! containsOnlyConstantData ( Cst ) ) continue ; if ( ! shouldConvert ( * Cst , PromotionCache ) ) continue ; unsigned OpNo = & U - I . op_begin ( ) ; if ( ! shouldConvertUse ( Cst , & I , OpNo ) ) continue ; Updates . emplace_back ( Cst , & I , OpNo ) ; } } if ( Updates . empty ( ) ) return false ; promoteConstants ( F , Updates , PromotionCache ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static void mips_arg_info ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named , struct mips_arg_info * info ) { bool doubleword_aligned_p ; unsigned int num_bytes , num_words , max_regs ; num_bytes = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; num_words = ( num_bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; switch ( mips_abi ) { case ABI_EABI : info -> fpr_p = ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_32 : case ABI_O64 : info -> fpr_p = ( ! cum -> gp_reg_found && cum -> arg_number < 2 && ( type == 0 || SCALAR_FLOAT_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_N32 : case ABI_64 : info -> fpr_p = ( named && ( type == 0 || FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; if ( info -> fpr_p && GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_UNIT_SIZE ( mode ) < UNITS_PER_FPVALUE ) { if ( cum -> num_gprs >= MAX_ARGS_IN_REGISTERS - 1 ) info -> fpr_p = false ; else num_words = 2 ; } break ; default : gcc_unreachable ( ) ; } doubleword_aligned_p = FUNCTION_ARG_BOUNDARY ( mode , type ) > BITS_PER_WORD ; info -> reg_offset = ( mips_abi == ABI_EABI && info -> fpr_p ? cum -> num_fprs : cum -> num_gprs ) ; if ( doubleword_aligned_p ) info -> reg_offset += info -> reg_offset & 1 ; info -> stack_offset = cum -> stack_words ; if ( doubleword_aligned_p ) info -> stack_offset += info -> stack_offset & 1 ; max_regs = MAX_ARGS_IN_REGISTERS - info -> reg_offset ; info -> reg_words = MIN ( num_words , max_regs ) ; info -> stack_words = num_words - info -> reg_words ; } </s>

Fill INFO with information about a single argument . CUM is the cumulative state for earlier arguments . MODE is the mode of this argument and TYPE is its type ( if known ) . NAMED is true if this is a named ( fixed ) argument rather than a variable one .


<s> static void fold_compare_helper ( gimple_stmt_iterator * gsi , tree_code code , gimple * stmt ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree cmp = fold_build_vec_cmp ( code , TREE_TYPE ( lhs ) , arg0 , arg1 , gsi ) ; gimple * g = gimple_build_assign ( lhs , cmp ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the in-between steps for the vector compare built-ins .


Add the named attribute to a class and its vtable and rtti .


<s> static rtx sparc_builtin_setjmp_frame_value ( void ) { return hard_frame_pointer_rtx ; } </s>

Return the hard frame pointer directly to bypass the stack bias .


<s> bool AArch64InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( getMaddPatterns ( Root , Patterns ) ) return true ; if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns , DoRegPressureReduce ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { unsigned Opc = Orig -> getOpcode ( ) ; if ( Opc == X86 :: MOV32r0 && ! isSafeToClobberEFLAGS ( MBB , I ) ) { DebugLoc DL = Orig -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( X86 :: MOV32ri ) ) . addOperand ( Orig -> getOperand ( 0 ) ) . addImm ( 0 ) ; } else { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } MachineInstr * NewMI = std :: prev ( I ) ; NewMI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveX86CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } setMachineOutliner ( true ) ; setSupportsDebugEntryValues ( true ) ; initAsmInfo ( ) ; } </s>


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ; DataSection . setAlignment ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ; BSSSection . setAlignment ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . EmitCodeAlignment ( Alignment , Alignment ) ; else OS . EmitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( EFlags & ELF :: EF_MIPS_CPIC && getABI ( ) . IsN64 ( ) ) EFlags |= ELF :: EF_MIPS_PIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; bool EHPadIBTNeeded = MBB . isEHPad ( ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; if ( EHPadIBTNeeded && I -> isEHLabel ( ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; EHPadIBTNeeded = false ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
RegisterBankInfo
*
AArch64Subtarget
::
getRegBankInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getRegBankInfo
(
)
;
}
</s>

If the information for the register banks is available , return it .


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
if
(
skipFunction
(
*
mf
.
getFunction
(
)
)
)
return
false
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
mf
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
&
*
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>


<s> int const_ok_for_arm ( HOST_WIDE_INT i ) { int lowbit ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != 0 && ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != ( ( ~ ( unsigned HOST_WIDE_INT ) 0 ) & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) ) ) return FALSE ; i &= ( unsigned HOST_WIDE_INT ) 0xffffffff ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xff ) == 0 ) return TRUE ; lowbit = ffs ( ( int ) i ) - 1 ; if ( TARGET_ARM ) lowbit &= ~ 1 ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) 0xff ) << lowbit ) ) == 0 ) return TRUE ; if ( TARGET_ARM ) { if ( lowbit <= 4 && ( ( i & ~ 0xc000003f ) == 0 || ( i & ~ 0xf000000f ) == 0 || ( i & ~ 0xfc000003 ) == 0 ) ) return TRUE ; } else { HOST_WIDE_INT v ; v = i & 0xff ; v |= v << 16 ; if ( i == v || i == ( v | ( v << 8 ) ) ) return TRUE ; v = i & 0xff00 ; v |= v << 16 ; if ( i == v ) return TRUE ; } return FALSE ; } </s>

Return TRUE if int I is a valid immediate ARM constant .


"-m64 requires PowerPC64 architecture, enabling"

The Darwin version of SUBTARGET_OVERRIDE_OPTIONS .


<s> bool AZPRAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return ! ( I -> isBarrier ( ) || ( I -> getOpcode ( ) == AZPR :: BE && I -> getOperand ( 0 ) . getReg ( ) == I -> getOperand ( 1 ) . getReg ( ) ) ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s>
MipsSubtarget
&
MipsSubtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
,
const
TargetMachine
&
TM
)
{
std
::
string
CPUName
=
MIPS_MC
::
selectMipsCPU
(
TM
.
getTargetTriple
(
)
,
CPU
)
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
InMips16Mode
&&
!
IsSoftFloat
)
InMips16HardFloat
=
true
;
if
(
StackAlignOverride
)
stackAlignment
=
StackAlignOverride
;
else
if
(
isABI_N32
(
)
||
isABI_N64
(
)
)
stackAlignment
=
16
;
else
{
assert
(
isABI_O32
(
)
&&
"Unknown ABI for stack alignment!"
)
;
stackAlignment
=
8
;
}
return
*
this
;
}
</s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

Mips
Mips
Mips
MIPS_MC::selectMipsCPU
Mips
Mips
16
"Unknown ABI for stack alignment!"
8


<s> ScheduleHazardRecognizer :: HazardType PPCScoreboardHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { return ScoreboardHazardRecognizer :: getHazardType ( SU , Stalls ) ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> static tree pa_d_handle_target_float_abi ( void ) { const char * abi ; if ( TARGET_SOFT_FLOAT ) abi = "soft" ; else abi = "hard" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> static void ix86_maybe_switch_abi ( void ) { if ( TARGET_64BIT && call_used_regs [ SI_REG ] == ( cfun -> machine -> call_abi == MS_ABI ) ) reinit_regs ( ) ; } </s>

64-bit MS and SYSV ABI have different set of call used registers . Avoid expensive re-initialization of init_regs each time we switch function context since this is needed only during RTL expansion .


<s> static bool is_nonpipeline_insn ( rtx_insn * insn ) { enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; type = get_attr_type ( insn ) ; if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT || type == TYPE_DSQRT || type == TYPE_MFCR || type == TYPE_MFCRF || type == TYPE_MFJMPR ) { return true ; } return false ; } </s>

Return true if the instruction is nonpipelined on the Cell .


<s> void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


Emit unwind opcodes for .vsave directives .


<s> bool MipsFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
const
char
*
mmix_data_section_asm_op
(
void
)
{
return
"\t.data ! mmixal:= 8H LOC 9B"
;
}
</s>


<s> inline tree tuple_type_field ( tree type ) { for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) return field ; gcc_unreachable ( ) ; } </s>

Return the single field in tuple type TYPE .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> static int pa_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { unsigned int max_arg_words = 8 ; unsigned int offset = 0 ; if ( ! TARGET_64BIT ) return 0 ; if ( FUNCTION_ARG_SIZE ( mode , type ) > 1 && ( cum -> words & 1 ) ) offset = 1 ; if ( cum -> words + offset + FUNCTION_ARG_SIZE ( mode , type ) <= max_arg_words ) return 0 ; else if ( cum -> words + offset >= max_arg_words ) return 0 ; else return ( max_arg_words - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

If this arg would be passed totally in registers or totally on the stack , then this routine should return zero .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR64RegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
GPR32RegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
GPR64RegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
LORegsRegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
LORegs64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case HFmode : if ( ! TARGET_VFP_FP16INST ) break ; mode = SFmode ; * op1 = convert_to_mode ( mode , * op1 , 1 ) ; * op2 = convert_to_mode ( mode , * op2 , 1 ) ; case SFmode : case DFmode : if ( ! vfp_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! vfp_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . isSVR4ABI ( ) && PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { FrameIdx = MF . getInfo < PPCFunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .

PowerPC PPC PPC PPC PPC::CR2 PPC::CR4 PPC


<s> MCObjectWriter * SICAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createSICELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> static int sh_round_reg ( const CUMULATIVE_ARGS & cum , machine_mode mode ) { return ( ( ( TARGET_ALIGN_DOUBLE || ( TARGET_FPU_DOUBLE && ( mode == DFmode || mode == DCmode ) && cum . arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( mode ) ) ) && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_WORD ) ? ( cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] + ( cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] & 1 ) ) : cum . arg_count [ ( int ) get_sh_arg_class ( mode ) ] ) ; } </s>

Round a register number up to a proper boundary for an arg of mode MODE . The SH does n't care about double alignment , so we only round doubles to even regs when asked to explicitly .


"%qE attribute only applies to functions"

"FP registers might be clobbered despite %qE attribute: compile with %<-mgeneral-regs-only%>"

Handle an `` interrupt '' or `` isr '' attribute ; arguments as in struct attribute_spec.handler .


Do whatever processing is required at the end of a file .


<s> int xstormy16_carry_plus_operand ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( x , 1 ) ) < - 4 || INTVAL ( XEXP ( x , 1 ) ) > 4 ) ) ; } </s>

Recognize a PLUS that needs the carry register .


<s> void override_options ( void ) { target_flags &= ~ MASK_GPOPT ; iq2000_isa = IQ2000_ISA_DEFAULT ; iq2000_print_operand_punct [ '?' ] = 1 ; iq2000_print_operand_punct [ '#' ] = 1 ; iq2000_print_operand_punct [ '&' ] = 1 ; iq2000_print_operand_punct [ '!' ] = 1 ; iq2000_print_operand_punct [ '*' ] = 1 ; iq2000_print_operand_punct [ '@' ] = 1 ; iq2000_print_operand_punct [ '.' ] = 1 ; iq2000_print_operand_punct [ '(' ] = 1 ; iq2000_print_operand_punct [ ')' ] = 1 ; iq2000_print_operand_punct [ '[' ] = 1 ; iq2000_print_operand_punct [ ']' ] = 1 ; iq2000_print_operand_punct [ '<' ] = 1 ; iq2000_print_operand_punct [ '>' ] = 1 ; iq2000_print_operand_punct [ '{' ] = 1 ; iq2000_print_operand_punct [ '}' ] = 1 ; iq2000_print_operand_punct [ '^' ] = 1 ; iq2000_print_operand_punct [ '$' ] = 1 ; iq2000_print_operand_punct [ '+' ] = 1 ; iq2000_print_operand_punct [ '~' ] = 1 ; gpr_mode = SImode ; init_machine_status = iq2000_init_machine_status ; } </s>

Set global variables as needed for the options enabled .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
static
void
complete_vector_type
(
typeinfo
*
typeptr
,
char
*
buf
,
int
*
bufi
)
{
if
(
typeptr
->
isbool
)
buf
[
(
*
bufi
)
++
]
=
'b'
;
buf
[
(
*
bufi
)
++
]
=
'v'
;
if
(
typeptr
->
ispixel
)
{
memcpy
(
&
buf
[
*
bufi
]
,
"p8hi"
,
4
)
;
*
bufi
+=
4
;
return
;
}
switch
(
typeptr
->
base
)
{
case
BT_CHAR
:
memcpy
(
&
buf
[
*
bufi
]
,
"16qi"
,
4
)
;
*
bufi
+=
4
;
break
;
case
BT_SHORT
:
memcpy
(
&
buf
[
*
bufi
]
,
"8hi"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_INT
:
memcpy
(
&
buf
[
*
bufi
]
,
"4si"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_LONGLONG
:
memcpy
(
&
buf
[
*
bufi
]
,
"2di"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_FLOAT
:
memcpy
(
&
buf
[
*
bufi
]
,
"4sf"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_DOUBLE
:
memcpy
(
&
buf
[
*
bufi
]
,
"2df"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_INT128
:
memcpy
(
&
buf
[
*
bufi
]
,
"1ti"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_FLOAT128
:
memcpy
(
&
buf
[
*
bufi
]
,
"1tf"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_VPAIR
:
memcpy
(
&
buf
[
*
bufi
]
,
"1poi"
,
4
)
;
*
bufi
+=
4
;
break
;
case
BT_VQUAD
:
memcpy
(
&
buf
[
*
bufi
]
,
"1pxi"
,
4
)
;
*
bufi
+=
4
;
break
;
default
:
diag
(
pos
,
"unhandled basetype %d.\n"
,
typeptr
->
base
)
;
exit
(
1
)
;
}
}
</s>

Convert a vector type into a mode string .


<s> EVT PPCTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return PPCSubTarget . useCRBits ( ) ? MVT :: i1 : MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static unsigned int mips_arg_regno ( const struct mips_arg_info * info , bool hard_float_p ) { if ( ! info -> fpr_p || ! hard_float_p ) return GP_ARG_FIRST + info -> reg_offset ; else if ( mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info -> reg_offset > 0 ) return FP_ARG_FIRST + 2 ; else return FP_ARG_FIRST + info -> reg_offset ; } </s>

INFO describes a register argument that has the normal format for the argument 's mode . Return the register it uses , assuming that FPRs are available if HARD_FLOAT_P .


"CFProtection used on invalid architecture!"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool X86TargetLowering :: isCommutativeBinOp ( unsigned Opcode ) const { switch ( Opcode ) { case X86ISD :: AVG : case X86ISD :: PCMPEQ : case X86ISD :: PMULDQ : case X86ISD :: PMULUDQ : case X86ISD :: FMAXC : case X86ISD :: FMINC : case X86ISD :: FAND : case X86ISD :: FOR : case X86ISD :: FXOR : return true ; } return TargetLoweringBase :: isCommutativeBinOp ( Opcode ) ; } </s>

Returns true if the opcode is a commutative binary operation .


"Branch-taken block should post-dominate first candidate"

"Error in code produced by branch coalescing"

runOnMachineFunction - Emit the function body .


<s> unsigned PPCMCCodeEmitter :: getInstSizeInBytes ( const MCInst & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; return Desc . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
SystemZOperand
::
print
(
raw_ostream
&
OS
)
const
{
llvm_unreachable
(
"Not implemented"
)
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static rtx mep_convert_regnum ( const struct cgen_regnum_operand * regnum , rtx arg ) { if ( regnum -> count == 0 ) return arg ; if ( GET_CODE ( arg ) != CONST_INT || INTVAL ( arg ) < 0 || INTVAL ( arg ) >= regnum -> count ) return 0 ; return gen_rtx_REG ( SImode , INTVAL ( arg ) + regnum -> base ) ; } </s>

Apply regnum conversions to ARG using the description given by REGNUM . Return the new argument on success and null on failure .


<s> int pru_get_ctable_exact_base_index ( unsigned HOST_WIDE_INT caddr ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( pru_ctable ) ; i ++ ) { if ( pru_ctable [ i ] . valid && pru_ctable [ i ] . base == caddr ) return i ; } return - 1 ; } </s>

Recognize a CTABLE base address . Return CTABLE entry index , or -1 if base was not found in the pragma-filled pru_ctable .


<s> static rtx loongarch_unspec_address_offset ( rtx base , rtx offset , enum loongarch_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , base ) , UNSPEC_ADDRESS_FIRST + symbol_type ) ; if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ; return gen_rtx_CONST ( Pmode , base ) ; } </s>

Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE , then add CONST_INT OFFSET to the result .


"getJumpTargetOpValue expects only expressions or an immediate"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> bool AArch64PassConfig :: addInstSelector ( ) { addPass ( createAArch64ISelDag ( getAArch64TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getSubtarget < AArch64Subtarget > ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64CleanupLocalDynamicTLSPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void altivec_expand_lvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx load = gen_rtx_SET ( VOIDmode , tmp , op1 ) ; rtx lvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , load , lvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , tmp , tmp , sel ) , UNSPEC_VPERM ) ; gcc_assert ( REG_P ( op0 ) ) ; emit_insn ( par ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , vperm ) ) ; } </s>

Generate code for an `` lvx '' , `` lvxl '' , or `` lve * x '' built-in for a little endian target with -maltivec=be specified . Issue the load followed by an element-reversing permute .


<s> Register getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>


<s> int shadd_constant_p ( int val ) { if ( val == 2 || val == 4 || val == 8 ) return 1 ; else return 0 ; } </s>

Return 1 if the given constant is 2 , 4 , or 8 . These are the valid constants for shadd instructions .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"::LowerOperation"
;
Op
->
print
(
dbgs
(
)
)
;
)
;
unsigned
Opcode
=
Op
.
getOpcode
(
)
;
switch
(
Opcode
)
{
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_SWAP
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_LONGJMP
:
return
lowerEH_SJLJ_LONGJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETJMP
:
return
lowerEH_SJLJ_SETJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETUP_DISPATCH
:
return
lowerEH_SJLJ_SETUP_DISPATCH
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
lowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
INSERT_VECTOR_ELT
:
return
lowerINSERT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
lowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"::LowerOperation_VVP"
;
Op
->
print
(
dbgs
(
)
)
;
)
;
if
(
ISD
::
isVPOpcode
(
Opcode
)
)
return
lowerToVVP
(
Op
,
DAG
)
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
VEISD
::
VEC_BROADCAST
:
if
(
getAnnotatedNodeAVL
(
Op
)
.
second
)
return
Op
;
return
legalizeInternalVectorOp
(
Op
,
DAG
)
;
case
ISD
::
MLOAD
:
case
ISD
::
MSTORE
:
if
(
isMaskArithmetic
(
Op
)
&&
isPackedVectorType
(
Op
.
getValueType
(
)
)
)
return
splitMaskArithmetic
(
Op
,
DAG
)
;
return
lowerToVVP
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> inline hashval_t mips_lo_sum_offset_hasher :: hash ( const mips_lo_sum_offset * entry ) { return mips_hash_base ( entry -> base ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONMoveFixPass ( ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , Align ( AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool isConditionalBranch ( unsigned Opc ) { switch ( Opc ) { default : return false ; case AArch64 :: TBZW : case AArch64 :: TBNZW : case AArch64 :: TBZX : case AArch64 :: TBNZX : case AArch64 :: CBZW : case AArch64 :: CBNZW : case AArch64 :: CBZX : case AArch64 :: CBNZX : case AArch64 :: Bcc : return true ; } } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> unsigned int ix86_minimum_alignment ( tree exp , machine_mode mode , unsigned int align ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64 ) return align ; if ( ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) return 32 ; return align ; } </s>

Compute the minimum required alignment for dynamic stack realignment purposes for a local variable , parameter or a stack slot . EXP is the data type or decl itself , MODE is its mode and ALIGN is the alignment that the object would ordinarily have .


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * this , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void mmix_encode_section_info ( tree decl , rtx rtl , int first ) { if ( ( TREE_CODE ( decl ) == VAR_DECL && ( DECL_EXTERNAL ( decl ) || TREE_PUBLIC ( decl ) ) ) || ( TREE_CODE ( decl ) == FUNCTION_DECL && TREE_PUBLIC ( decl ) ) ) ; else if ( first && DECL_P ( decl ) ) { const char * str = XSTR ( XEXP ( rtl , 0 ) , 0 ) ; int len = strlen ( str ) ; char * newstr ; newstr = ( char * ) ggc_alloc_string ( "" , len + 1 ) ; strcpy ( newstr + 1 , str ) ; * newstr = '@' ; XSTR ( XEXP ( rtl , 0 ) , 0 ) = newstr ; } if ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CONSTANT ( decl ) || ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , 0 ) ) = 1 ; } </s>


<s>
static
void
vax_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
function
)
{
fprintf
(
file
,
"\t.word 0x0ffc\n\taddl2 $"
HOST_WIDE_INT_PRINT_DEC
,
delta
)
;
asm_fprintf
(
file
,
",4(%Rap)\n"
)
;
fprintf
(
file
,
"\tjmp "
)
;
assemble_name
(
file
,
XSTR
(
XEXP
(
DECL_RTL
(
function
)
,
0
)
,
0
)
)
;
fprintf
(
file
,
"+2\n"
)
;
}
</s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance . .mask ^m < r2 , r3 , r4 , r5 , r6 , r7 , r8 , r9 , r10 , r11 > # conservative entry mask addl2 $ DELTA , 4 ( ap ) # adjust first argument jmp FUNCTION+2 # jump beyond FUNCTION 's entry mask


<s> void rs6000_emit_swdiv ( rtx dst , rtx n , rtx d , bool note_p ) { machine_mode mode = GET_MODE ( dst ) ; rtx one , x0 , e0 , x1 , xprev , eprev , xnext , enext , u , v ; int i ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; one = rs6000_load_constant_and_splat ( mode , dconst1 ) ; x0 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , d ) , UNSPEC_FRES ) ) ) ; if ( passes > 1 ) { e0 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( e0 , d , x0 , one ) ; x1 = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( x1 , e0 , x0 , x0 ) ; for ( i = 0 , xprev = x1 , eprev = e0 ; i < passes - 2 ; ++ i , xprev = xnext , eprev = enext ) { enext = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( enext , eprev , eprev ) ) ; xnext = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( xnext , enext , xprev , xprev ) ; } } else xprev = x0 ; u = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , n , xprev ) ) ; v = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( v , d , u , n ) ; rs6000_emit_madd ( dst , v , xprev , u ) ; if ( note_p ) add_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_DIV ( mode , n , d ) ) ; } </s>

Newton-Raphson approximation of floating point divide DST = N/D . If NOTE_P , add a reg_note saying that this was a division . Support both scalar and vector divide . Assumes no trapping math and finite arguments .


"  r%d def in insn %d isn't convertible\n"

"  r%d use in insn %d isn't convertible\n"

Check REF 's chain to add new insns into a queue and find registers requiring conversion . Return true if OK , false if the analysis was aborted .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: X86_FastCall ) ; F -> addParamAttr ( 0 , Attribute :: AttrKind :: InReg ) ; } return ; } StringRef GuardMode = M . getStackProtectorGuard ( ) ; if ( ( GuardMode == "tls" || GuardMode . empty ( ) ) && hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> void sh_init_cumulative_args ( CUMULATIVE_ARGS * pcum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl , signed int n_named_args , enum machine_mode mode ) { pcum -> arg_count [ ( int ) SH_ARG_FLOAT ] = 0 ; pcum -> free_single_fp_reg = 0 ; pcum -> stack_regs = 0 ; pcum -> byref_regs = 0 ; pcum -> byref = 0 ; pcum -> outgoing = ( n_named_args == - 1 ) ? 0 : 1 ; pcum -> renesas_abi = sh_attr_renesas_p ( fntype ) ? 1 : 0 ; if ( fntype ) { pcum -> force_mem = ( ( TARGET_HITACHI || pcum -> renesas_abi ) && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ) ; pcum -> prototype_p = TYPE_ARG_TYPES ( fntype ) ? TRUE : FALSE ; pcum -> arg_count [ ( int ) SH_ARG_INT ] = TARGET_SH5 && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ; pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && pcum -> arg_count [ ( int ) SH_ARG_INT ] == 0 && ( TYPE_MODE ( TREE_TYPE ( fntype ) ) == BLKmode ? int_size_in_bytes ( TREE_TYPE ( fntype ) ) : GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) ) > 4 && ( BASE_RETURN_VALUE_REG ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) == FIRST_RET_REG ) ) ; } else { pcum -> arg_count [ ( int ) SH_ARG_INT ] = 0 ; pcum -> prototype_p = FALSE ; if ( mode != VOIDmode ) { pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && GET_MODE_SIZE ( mode ) > 4 && BASE_RETURN_VALUE_REG ( mode ) == FIRST_RET_REG ) ; pcum -> force_mem = ( TARGET_DEFAULT & MASK_HITACHI ) && ( mode == BLKmode || ( GET_MODE_SIZE ( mode ) > 4 && ! ( mode == DFmode && TARGET_FPU_DOUBLE ) ) ) ; } else { pcum -> call_cookie = 0 ; pcum -> force_mem = FALSE ; } } } </s>

Initialize the CUMULATIVE_ARGS structure .


<s> static void pop ( int rn ) { rtx x , sp_reg , reg ; if ( rn == FPUL_REG ) x = gen_pop_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_pop_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return ; x = gen_pop_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_pop_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , 0 , 0 ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( SImode , sp_reg , plus_constant ( SImode , sp_reg , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; } </s>

Output RTL to pop register RN from the stack .


<s> TargetStackID :: Value AArch64FrameLowering :: getStackIDForScalableVectors ( ) const { return TargetStackID :: SVEVector ; } </s>

Returns the StackID that scalable vectors should be associated with .


<s> bool SICInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case SIC :: RetLR : expandRetLR ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> SDValue Cpu0SETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { return Cpu0TargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> void ELFAArch64AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { if ( isByteSwappedFixup ( Fixup . getValue ( ) ) ) Value = ByteSwap_32 ( unsigned ( Value ) ) ; } AArch64AsmBackend :: applyFixup ( Fixup , Data , DataSize , Value , IsPCRel ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void ARMTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { ARMELFStreamer & Streamer = getStreamer ( ) ; if ( ! Streamer . IsThumb ) return ; Streamer . getAssembler ( ) . registerSymbol ( * Symbol ) ; unsigned Type = cast < MCSymbolELF > ( Symbol ) -> getType ( ) ; if ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) Streamer . emitThumbFunc ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> static rtx ix86_expand_sse_compare_mask ( enum rtx_code code , rtx op0 , rtx op1 , bool swap_operands ) { rtx ( * insn ) ( rtx , rtx , rtx , rtx ) ; machine_mode mode = GET_MODE ( op0 ) ; rtx mask = gen_reg_rtx ( mode ) ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; insn = mode == DFmode ? gen_setcc_df_sse : gen_setcc_sf_sse ; emit_insn ( insn ( mask , op0 , op1 , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ) ) ; return mask ; } </s>

Expand a mask generating SSE comparison instruction comparing OP0 with OP1 using comparison code CODE . Operands are swapped for the comparison if SWAP_OPERANDS is true . Returns a rtx for the generated mask .


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s> SDValue TOYTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BR_CC : return LowerBR_CC ( Op , DAG ) ; } } </s>


<s> unsigned VEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: LDrii || MI . getOpcode ( ) == VE :: LDLSXrii || MI . getOpcode ( ) == VE :: LDUrii || MI . getOpcode ( ) == VE :: LDQrii ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> unsigned MipsAsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) . getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> int barrier_align ( rtx barrier_or_label ) { rtx next = next_real_insn ( barrier_or_label ) , pat , prev ; int slot , credit , jump_to_next = 0 ; if ( ! next ) return 0 ; pat = PATTERN ( next ) ; if ( GET_CODE ( pat ) == ADDR_DIFF_VEC ) return 2 ; if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , 1 ) == UNSPECV_ALIGN ) return 0 ; prev = prev_real_insn ( barrier_or_label ) ; if ( GET_CODE ( PATTERN ( prev ) ) == ADDR_DIFF_VEC ) { pat = PATTERN ( prev ) ; return ( ( TARGET_SMALLCODE || ( ( unsigned ) XVECLEN ( pat , 1 ) * GET_MODE_SIZE ( GET_MODE ( pat ) ) <= ( unsigned ) 1 << ( CACHE_LOG - 2 ) ) ) ? 1 << TARGET_SHMEDIA : align_jumps_log ) ; } if ( TARGET_SMALLCODE ) return 0 ; if ( ! TARGET_SH2 || ! optimize ) return align_jumps_log ; if ( mdep_reorg_phase > SH_FIXUP_PCLOAD ) { prev = prev_real_insn ( prev ) ; for ( slot = 2 , credit = ( 1 << ( CACHE_LOG - 2 ) ) + 2 ; credit >= 0 && prev && GET_CODE ( prev ) == INSN ; prev = prev_real_insn ( prev ) ) { jump_to_next = 0 ; if ( GET_CODE ( PATTERN ( prev ) ) == USE || GET_CODE ( PATTERN ( prev ) ) == CLOBBER ) continue ; if ( GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) { prev = XVECEXP ( PATTERN ( prev ) , 0 , 1 ) ; if ( INSN_UID ( prev ) == INSN_UID ( next ) ) { jump_to_next = 1 ; continue ; } } if ( slot && get_attr_in_delay_slot ( prev ) == IN_DELAY_SLOT_YES ) slot = 0 ; credit -= get_attr_length ( prev ) ; } if ( prev && GET_CODE ( prev ) == JUMP_INSN && JUMP_LABEL ( prev ) ) { rtx x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN ( prev ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( credit - slot >= ( GET_CODE ( SET_SRC ( pat ) ) == PC ? 2 : 0 ) ) return 0 ; } } } return align_jumps_log ; } </s>

BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following a barrier . Return the base 2 logarithm of the desired alignment .


<s> void rs6000_expand_interleave ( rtx target , rtx op0 , rtx op1 , bool highp ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; rtx perm [ 16 ] ; high = ( highp ? 0 : nelt / 2 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { perm [ i * 2 ] = GEN_INT ( i + high ) ; perm [ i * 2 + 1 ] = GEN_INT ( i + nelt + high ) ; } rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , nelt , perm ) ; } </s>


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : case ARM :: VSTR_P0_off : case ARM :: MVE_VSTRWU32 : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64 : case ARM :: VST1d64TPseudo : case ARM :: VST1d64QPseudo : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: MQQPRStore : case ARM :: MQQQQPRStore : if ( MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
void
SystemZInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32mr
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Pmr
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128mr
;
}
else
llvm_unreachable
(
"Unsupported regclass to store"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool IA64TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createIA64DAGToDAGInstructionSelector ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"getJumpTargetOpValue is not implemented yet"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s>
void
neon_const_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
)
{
bounds_check
(
operand
,
low
,
high
,
"constant out of range"
)
;
}
</s>


<s> static bool aarch64_reads_global_state_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode ) ; if ( flags & FLAG_READ_FPCR ) return true ; return flags & FLAG_READ_MEMORY ; } </s>

Return true if calls to the function could read some form of global state .


<s> const MCExpr * PPCTargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( ! Subtarget . isPPC64 ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Default : case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; default : return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s>
void
PPCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
PPC
::
GPRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR
;
else
if
(
PPC
::
G8RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR8
;
else
if
(
PPC
::
F4RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
FMR
;
else
if
(
PPC
::
CRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
MCRF
;
else
if
(
PPC
::
VRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
VOR
;
else
if
(
PPC
::
CRBITRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
CROR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
const
TargetInstrDesc
&
TID
=
get
(
Opc
)
;
if
(
TID
.
getNumOperands
(
)
==
3
)
BuildMI
(
MBB
,
I
,
DL
,
TID
,
DestReg
)
.
addReg
(
SrcReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
TID
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

PowerPC
PPC
PPC::GPRCRegClass
PPC::OR
PPC::G8RCRegClass
PPC::OR8
PPC::F4RCRegClass
PPC::FMR
PPC::CRRCRegClass
PPC::MCRF
PPC::VRRCRegClass
PPC::VOR
PPC::CRBITRCRegClass
PPC::CROR
"Impossible reg-to-reg copy"
3


<s> static machine_mode sparc_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VIS ) switch ( mode ) { case E_SImode : return V2SImode ; case E_HImode : return V4HImode ; case E_QImode : return V8QImode ; default : ; } return word_mode ; } </s>

Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> SDValue LanaiSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & , const SDLoc & , SDValue , SDValue , SDValue , SDValue Size , unsigned , bool , bool , MachinePointerInfo , MachinePointerInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> DecodeStatus LanaiDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableLanai32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> unsigned SystemZInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , SystemZII :: SimpleBDXLoad ) ; } </s>


<s> int nds32_can_use_return_insn ( void ) { if ( ! reload_completed ) return 0 ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size == 0 ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> bool Mips16InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA16 : ExpandRetRA16 ( MBB , MI , Mips :: JrcRa16 ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> const char * getPassName ( ) const override { return AARCH64_DEAD_REG_DEF_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static unsigned int ix86_compat_function_arg_boundary ( machine_mode mode , const_tree type , unsigned int align ) { if ( ! TARGET_64BIT && mode != TDmode && mode != TFmode ) { if ( ! type ) { if ( ! ( TARGET_SSE && SSE_REG_MODE_P ( mode ) ) ) align = PARM_BOUNDARY ; } else { if ( ! ix86_compat_aligned_value_p ( type ) ) align = PARM_BOUNDARY ; } } if ( align > BIGGEST_ALIGNMENT ) align = BIGGEST_ALIGNMENT ; return align ; } </s>

Return the alignment boundary for MODE and TYPE with alignment ALIGN . XXX : This function is obsolete and is only used for checking psABI compatibility with previous versions of GCC .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s> unsigned int mips_hard_regno_nregs ( int regno , enum machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ) ; else if ( ! FP_REG_P ( regno ) ) return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; else return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ) ; } </s>


"Can't break virtual register dependencies."

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s>
MachineBasicBlock
*
MipsTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
*
TII
=
getTargetMachine
(
)
.
getInstrInfo
(
)
;
bool
isFPCmp
=
false
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
case
Mips
::
Select_FCC
:
case
Mips
::
Select_FCC_S32
:
case
Mips
::
Select_FCC_D32
:
isFPCmp
=
true
;
case
Mips
::
Select_CC
:
case
Mips
::
Select_CC_S32
:
case
Mips
::
Select_CC_D32
:
{
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
if
(
isFPCmp
)
{
Mips
::
CondCode
CC
=
(
Mips
::
CondCode
)
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
Opc
=
FPBranchCodeToOpc
(
GetFPBranchCodeFromCond
(
CC
)
)
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
Opc
)
)
.
addMBB
(
sinkMBB
)
;
}
else
BuildMI
(
BB
,
dl
,
TII
->
get
(
Mips
::
BNE
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addReg
(
Mips
::
ZERO
)
.
addMBB
(
sinkMBB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
i
=
BB
->
succ_begin
(
)
,
e
=
BB
->
succ_end
(
)
;
i
!=
e
;
++
i
)
sinkMBB
->
addSuccessor
(
*
i
)
;
while
(
!
BB
->
succ_empty
(
)
)
BB
->
removeSuccessor
(
BB
->
succ_begin
(
)
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
Mips
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> MVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned Align , bool isSrcConst , bool isSrcStr ) const { if ( ! NoImplicitFloat && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE2 ( ) && Size >= 16 ) return MVT :: v4i32 ; if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE1 ( ) && Size >= 16 ) return MVT :: v4f32 ; } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


"Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> inline machine_mode function_instance :: gp_mode ( unsigned int i ) const { return aarch64_sve_pred_mode ( type_suffix ( i ) . element_bytes ) . require ( ) ; } </s>

Return the mode of the governing predicate to use when operating on type suffix I .


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; int FrameIdx ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlignment ( * RC ) ) ; FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; if ( hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) && Reg == AArch64 :: FP ) { FrameIdx = MFI . CreateStackObject ( 8 , Alignment , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static rtx pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style , bool set_cfa ) { struct machine_function * m = cfun -> machine ; rtx addend = offset ; rtx insn ; bool add_frame_related_expr = false ; if ( ! x86_64_immediate_operand ( offset , Pmode ) ) { if ( style ) addend = gen_rtx_REG ( Pmode , R11_REG ) ; else { gcc_assert ( src != hard_frame_pointer_rtx && dest != hard_frame_pointer_rtx ) ; addend = hard_frame_pointer_rtx ; } emit_insn ( gen_rtx_SET ( addend , offset ) ) ; if ( style < 0 ) add_frame_related_expr = true ; } insn = emit_insn ( gen_pro_epilogue_adjust_stack_add ( Pmode , dest , src , addend ) ) ; if ( style >= 0 ) ix86_add_queued_cfa_restore_notes ( insn ) ; if ( set_cfa ) { rtx r ; gcc_assert ( m -> fs . cfa_reg == src ) ; m -> fs . cfa_offset += INTVAL ( offset ) ; m -> fs . cfa_reg = dest ; r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , r ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else if ( style < 0 ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( add_frame_related_expr ) { rtx r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , r ) ; } } if ( dest == stack_pointer_rtx ) { HOST_WIDE_INT ooffset = m -> fs . sp_offset ; bool valid = m -> fs . sp_valid ; bool realigned = m -> fs . sp_realigned ; if ( src == hard_frame_pointer_rtx ) { valid = m -> fs . fp_valid ; realigned = false ; ooffset = m -> fs . fp_offset ; } else if ( src == crtl -> drap_reg ) { valid = m -> fs . drap_valid ; realigned = false ; ooffset = 0 ; } else { gcc_checking_assert ( src == stack_pointer_rtx || offset == const0_rtx ) ; } m -> fs . sp_offset = ooffset - INTVAL ( offset ) ; m -> fs . sp_valid = valid ; m -> fs . sp_realigned = realigned ; } return insn ; } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


<s> void LEGInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LEG :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const uint16_t RegList [ ] = { MD :: R0 , MD :: R1 , MD :: R2 , MD :: R3 } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; if ( State . isVarArg ( ) ) { AnalyzeVarArgs ( State , Args ) ; return ; } SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 2 , 2 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList , NbRegs ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } } else { UseStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 4 , 4 , ArgFlags ) ; continue ; } if ( LocVT == MVT :: i32 || LocVT == MVT :: f32 ) { unsigned Offset1 = State . AllocateStack ( 4 , 4 ) ; State . addLoc ( CCValAssign :: getMem ( ValNo ++ , ArgVT , Offset1 , LocVT , LocInfo ) ) ; continue ; } } } } } </s>

The function will invoke AnalyzeCallOperands .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void function_builder :: append_name ( const char * name ) { obstack_grow ( & m_string_obstack , name , strlen ( name ) ) ; } </s>

Add NAME to the end of the function name being built .


<s> StringRef getPassName ( ) const override { return ARM_PREALLOC_LOAD_STORE_OPT_NAME ; } </s>


<s>
bool
PPCTargetLowering
::
isFPExtFree
(
EVT
DestVT
,
EVT
SrcVT
)
const
{
assert
(
DestVT
.
isFloatingPoint
(
)
&&
SrcVT
.
isFloatingPoint
(
)
&&
"invalid fpext types"
)
;
if
(
DestVT
==
MVT
::
f128
)
return
false
;
return
true
;
}
</s>

Return true if an fpext operation is free ( for instance , because single-precision floating-point numbers are implicitly extended to double-precision ) .

PowerPC
PPC
"invalid fpext types"
MVT::f128