<s> void PPCAIXAsmPrinter :: emitTTypeReference ( const GlobalValue * GV , unsigned Encoding ) { if ( GV ) { MCSymbol * TypeInfoSym = TM . getSymbol ( GV ) ; MCSymbol * TOCEntry = lookUpOrCreateTOCEntry ( TypeInfoSym ) ; const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ; auto & Ctx = OutStreamer -> getContext ( ) ; const MCExpr * Exp = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCEntry , Ctx ) , MCSymbolRefExpr :: create ( TOCBaseSym , Ctx ) , Ctx ) ; OutStreamer -> emitValue ( Exp , GetSizeOfEncodedValue ( Encoding ) ) ; } else OutStreamer -> emitIntValue ( 0 , GetSizeOfEncodedValue ( Encoding ) ) ; } </s>

Emit reference to a ttype global with a specified encoding .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
default
:
break
;
}
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
bool
IsNaCl
=
Subtarget
.
isTargetNaCl
(
)
;
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
IsNaCl
)
{
if
(
CallsEHReturn
)
return
CSR_NaCl64EHRet_SaveList
;
return
CSR_NaCl64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> opt_machine_mode aarch64_ptrue_all_mode ( rtx x ) { gcc_assert ( GET_MODE ( x ) == VNx16BImode ) ; if ( GET_CODE ( x ) != CONST_VECTOR || ! CONST_VECTOR_DUPLICATE_P ( x ) || ! CONST_INT_P ( CONST_VECTOR_ENCODED_ELT ( x , 0 ) ) || INTVAL ( CONST_VECTOR_ENCODED_ELT ( x , 0 ) ) == 0 ) return opt_machine_mode ( ) ; unsigned int nelts = const_vector_encoded_nelts ( x ) ; for ( unsigned int i = 1 ; i < nelts ; ++ i ) if ( CONST_VECTOR_ENCODED_ELT ( x , i ) != const0_rtx ) return opt_machine_mode ( ) ; return aarch64_sve_pred_mode ( nelts ) ; } </s>

If VNx16BImode rtx X is a canonical PTRUE for a predicate mode , return that predicate mode , otherwise return opt_machine_mode ( ) .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
static
void
initialize_aarch64_code_model
(
struct
gcc_options
*
opts
)
{
if
(
opts
->
x_flag_pic
)
{
switch
(
opts
->
x_aarch64_cmodel_var
)
{
case
AARCH64_CMODEL_TINY
:
aarch64_cmodel
=
AARCH64_CMODEL_TINY_PIC
;
break
;
case
AARCH64_CMODEL_SMALL
:
aarch64_cmodel
=
(
flag_pic
==
2
AARCH64_CMODEL_SMALL_PIC
:
AARCH64_CMODEL_SMALL_SPIC
)
;
aarch64_cmodel
=
AARCH64_CMODEL_SMALL_PIC
;
break
;
case
AARCH64_CMODEL_LARGE
:
sorry
(
"code model %qs with %<-f%s%>"
,
"large"
,
opts
->
x_flag_pic
>
1
"PIC"
:
"pic"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
aarch64_cmodel
=
opts
->
x_aarch64_cmodel_var
;
}
</s>

A checking mechanism for the implementation of the various code models .


<s> static int loongarch_move_from_gpr_cost ( reg_class_t to ) { switch ( to ) { case GENERAL_REGS : return 2 ; case FP_REGS : return 4 ; default : return 0 ; } } </s>

Return the cost of moving a value from a GPR to a register of class TO . Return 0 for classes that are unions of other classes handled by this function .


<s> static rtx sh_function_arg ( cumulative_args_t ca_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; machine_mode mode = arg . mode ; if ( arg . end_marker_p ( ) ) return ca -> renesas_abi ? const1_rtx : const0_rtx ; if ( sh_pass_in_reg_p ( * ca , mode , arg . type ) && ( arg . named || ! ( TARGET_HITACHI || ca -> renesas_abi ) ) ) { int regno ; if ( mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ( ! FUNCTION_ARG_SCmode_WART || ( sh_round_reg ( * ca , mode ) & 1 ) ) ) { rtx r1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( sh_round_reg ( * ca , mode ) ^ 1 ) ) , const0_rtx ) ; rtx r2 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ( sh_round_reg ( * ca , mode ) + 1 ) ^ 1 ) ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( SCmode , gen_rtvec ( 2 , r1 , r2 ) ) ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && ca -> free_single_fp_reg && mode == SFmode ) return gen_rtx_REG ( mode , ca -> free_single_fp_reg ) ; regno = ( BASE_ARG_REG ( mode ) + sh_round_reg ( * ca , mode ) ) ^ ( mode == SFmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ! TARGET_HITACHI && ! ca -> renesas_abi ) ; return gen_rtx_REG ( mode , regno ) ; } return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On SH the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { gcc_assert ( mode == SImode ) ; emit_insn ( gen_load_locked_si ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s>
void
CSKYInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
CSKYMachineFunctionInfo
*
CFI
=
MF
.
getInfo
<
CSKYMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
unsigned
Opcode
=
0
;
if
(
CSKY
::
GPRRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
LD32W
;
}
else
if
(
CSKY
::
CARRYRegClass
.
hasSubClassEq
(
RC
)
)
{
Opcode
=
CSKY
::
RESTORE_CARRY
;
CFI
->
setSpillsCR
(
)
;
}
else
if
(
v2sf
&&
CSKY
::
sFPR32RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
FLD_S
;
else
if
(
v2df
&&
CSKY
::
sFPR64RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
FLD_D
;
else
if
(
v3sf
&&
CSKY
::
FPR32RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
f2FLD_S
;
else
if
(
v3df
&&
CSKY
::
FPR64RegClass
.
hasSubClassEq
(
RC
)
)
Opcode
=
CSKY
::
f2FLD_D
;
else
{
llvm_unreachable
(
"Unknown RegisterClass"
)
;
}
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> SDValue PPCTargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool & isTailCall , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg ISD::InputArg PPC PPC PPC


<s> const char * i386_pe_strip_name_encoding_full ( const char * str ) { const char * p ; const char * name = i386_pe_strip_name_encoding ( str ) ; if ( * name == '@' ) name ++ ; p = strchr ( name , '@' ) ; if ( p ) return ggc_alloc_string ( name , p - name ) ; return name ; } </s>

Also strip the fastcall prefix and stdcall suffix .


"MIPS DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> int64_t getFrameAdjustment ( const MachineInstr & I ) const { assert ( isFrameInstr ( I ) ) ; if ( isFrameSetup ( I ) ) return I . getOperand ( 2 ) . getImm ( ) ; return I . getOperand ( 1 ) . getImm ( ) ; } </s>

Returns the stack pointer adjustment that happens inside the frame setup .. destroy sequence ( e.g .


<s> yaml :: MachineFunctionInfo * AArch64TargetMachine :: convertFuncInfoToYAML ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < AArch64FunctionInfo > ( ) ; return new yaml :: AArch64FunctionInfo ( * MFI ) ; } </s>

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
unsigned
X86TTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
)
const
{
std
::
pair
<
unsigned
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
Ty
)
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
static
const
X86CostTblEntry
AVX1CostTable
[
]
=
{
{
ISD
::
MUL
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v8i32
,
4
}
,
{
ISD
::
MUL
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
SUB
,
MVT
::
v4i64
,
4
}
,
{
ISD
::
ADD
,
MVT
::
v4i64
,
4
}
,
}
;
if
(
ST
->
hasAVX
(
)
)
{
int
Idx
=
FindInTable
(
AVX1CostTable
,
array_lengthof
(
AVX1CostTable
)
,
ISD
,
LT
.
second
)
;
if
(
Idx
!=
1
)
return
LT
.
first
*
AVX1CostTable
[
Idx
]
.
Cost
;
}
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) { setPICStyle ( PICStyles :: GOT ) ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0
ARMCC::AL


<s> BitVector DCPU16RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( DCPU16 :: EX ) ; Reserved . set ( DCPU16 :: SP ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( DCPU16 :: J ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips OptimizePICCall"
;
}
</s>


<s> static bool mips_no_speculation_in_delay_slots_p ( ) { return TARGET_CB_MAYBE ; } </s>


<s> bool n8_consumed_by_addr_in_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_BRANCH : use_rtx = extract_branch_target_rtx ( consumer ) ; break ; case TYPE_LOAD : if ( load_single_p ( consumer ) ) use_rtx = extract_mem_rtx ( consumer ) ; else use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE : if ( store_single_p ( consumer ) && ( ! post_update_insn_p ( consumer ) || immed_offset_p ( extract_mem_rtx ( consumer ) ) ) ) use_rtx = extract_mem_rtx ( consumer ) ; else use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; default : gcc_unreachable ( ) ; } return reg_overlap_p ( def_reg , use_rtx ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at AG ( II ) .


<s> static bool rs6000_lra_p ( void ) { return TARGET_LRA ; } </s>

Return true if we use LRA instead of reload pass .


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s> void AArch64BranchTargets :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue PPCTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { EVT VT = N -> getValueType ( 0 ) ; if ( VT == MVT :: i64 && ! Subtarget . isPPC64 ( ) ) return SDValue ( ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; bool IsNegPow2 = Divisor . isNegatedPowerOf2 ( ) ; unsigned Lg2 = ( IsNegPow2 ? - Divisor : Divisor ) . countTrailingZeros ( ) ; SDValue ShiftAmt = DAG . getConstant ( Lg2 , DL , VT ) ; SDValue Op = DAG . getNode ( PPCISD :: SRA_ADDZE , DL , VT , N0 , ShiftAmt ) ; Created . push_back ( Op . getNode ( ) ) ; if ( IsNegPow2 ) { Op = DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , Op ) ; Created . push_back ( Op . getNode ( ) ) ; } return Op ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> static const char * arm_identify_fpu_from_isa ( sbitmap isa ) { auto_sbitmap fpubits ( isa_num_bits ) ; auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return "softvfp" ; for ( unsigned int i = 0 ; i < ARRAY_SIZE ( all_fpus ) ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ; if ( bitmap_equal_p ( fpubits , cand_fpubits ) ) return all_fpus [ i ] . name ; } gcc_unreachable ( ) ; } </s>

Match an ISA feature bitmap to a named FPU . We always use the first entry that exactly matches the feature set , so that we effectively canonicalize the FPU name for the assembler .


<s> bool arm_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) { if ( TARGET_ARM ) return arm_legitimate_address_outer_p ( mode , x , SET , strict_p ) ; else if ( TARGET_THUMB2 ) return thumb2_legitimate_address_p ( mode , x , strict_p ) ; else return thumb1_legitimate_address_p ( mode , x , strict_p ) ; } </s>

Return nonzero if X is a valid ARM state address operand .


Do anything needed before RTL is emitted for each function .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_store : case vector_stmt : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case scalar_load : case vector_load : return 2 ; case vec_perm : if ( TARGET_VSX && rs6000_tune == PROCESSOR_POWER7 ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX && rs6000_tune == PROCESSOR_POWER7 ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : case vector_gather_load : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 2 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 || elements == 1 ) return 4 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 4 ; case - 1 : case 4 : case 12 : return 33 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 4 ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 || elements == 1 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return 5 ; else if ( INTEGRAL_TYPE_P ( elem_type ) ) { if ( TARGET_P9_VECTOR ) return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 2 ; else return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 5 ; } else return 2 ; default : gcc_unreachable ( ) ; } } </s>


<s> static rtx ix86_expand_sse_round ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op1 , op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; if ( optimize || target == 0 || GET_MODE ( target ) != tmode || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; op1 = GEN_INT ( d -> comparison ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutines of ix86_expand_args_builtin to take care of round insns .


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { if ( ST -> getCPUDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , SE , UP , ORE ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static machine_mode sparc_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree fntype ATTRIBUTE_UNUSED , int for_return ATTRIBUTE_UNUSED ) { if ( type != NULL_TREE && POINTER_TYPE_P ( type ) ) { * punsignedp = POINTERS_EXTEND_UNSIGNED ; return Pmode ; } if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) return word_mode ; return mode ; } </s>

Handle promotion of pointer and integer arguments .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function & F = MF -> getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F . hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F . getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


<s> static void add_to_dispatch_window ( rtx_insn * insn ) { int byte_len ; dispatch_windows * window_list ; dispatch_windows * next_list ; dispatch_windows * window0_list ; enum insn_path path ; enum dispatch_group insn_group ; bool insn_fits ; int num_insn ; int num_uops ; int window_num ; int insn_num_uops ; int sum ; if ( INSN_CODE ( insn ) < 0 ) return ; byte_len = min_insn_size ( insn ) ; window_list = dispatch_window_list ; next_list = window_list -> next ; path = get_insn_path ( insn ) ; insn_group = get_insn_group ( insn ) ; if ( next_list ) window_list = dispatch_window_list -> next ; if ( path == path_single ) insn_num_uops = 1 ; else if ( path == path_double ) insn_num_uops = 2 ; else insn_num_uops = ( int ) path ; num_insn = window_list -> num_insn ; num_uops = window_list -> num_uops ; window_num = window_list -> window_num ; insn_fits = fits_dispatch_window ( insn ) ; if ( num_insn >= MAX_INSN || num_uops + insn_num_uops > MAX_INSN || ! ( insn_fits ) ) { window_num = ~ window_num & 1 ; window_list = allocate_next_window ( window_num ) ; } if ( window_num == 0 ) { add_insn_window ( insn , window_list , insn_num_uops ) ; if ( window_list -> num_insn >= MAX_INSN && insn_group == disp_branch ) { process_end_window ( ) ; return ; } } else if ( window_num == 1 ) { window0_list = window_list -> prev ; sum = window0_list -> window_size + window_list -> window_size ; if ( sum == 32 || ( byte_len + sum ) >= 48 ) { process_end_window ( ) ; window_list = dispatch_window_list ; } add_insn_window ( insn , window_list , insn_num_uops ) ; } else gcc_unreachable ( ) ; if ( is_end_basic_block ( insn_group ) ) { process_end_window ( ) ; return ; } } </s>

Adds a scheduled instruction , INSN , to the current dispatch window . If the total bytes of instructions or the number of instructions in the window exceed allowable , it allocates a new window .


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; ArgInfo ArgRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( DL , ArgRetInfo , 0 , RetInfos , OrigArgIndices ) ; SmallVector < ISD :: OutputArg , 8 > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> unsigned DLXMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; if ( MCOp . isReg ( ) || MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , static_cast < MCFixupKind > ( DLX :: FIXUP_DLX_25 ) ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned AArch64AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { AArch64Operand & Op = static_cast < AArch64Operand & > ( AsmOp ) ; int64_t ExpectedVal ; switch ( Kind ) { default : return Match_InvalidOperand ; case MCK__HASH_0 : ExpectedVal = 0 ; break ; case MCK__HASH_1 : ExpectedVal = 1 ; break ; case MCK__HASH_12 : ExpectedVal = 12 ; break ; case MCK__HASH_16 : ExpectedVal = 16 ; break ; case MCK__HASH_2 : ExpectedVal = 2 ; break ; case MCK__HASH_24 : ExpectedVal = 24 ; break ; case MCK__HASH_3 : ExpectedVal = 3 ; break ; case MCK__HASH_32 : ExpectedVal = 32 ; break ; case MCK__HASH_4 : ExpectedVal = 4 ; break ; case MCK__HASH_48 : ExpectedVal = 48 ; break ; case MCK__HASH_6 : ExpectedVal = 6 ; break ; case MCK__HASH_64 : ExpectedVal = 64 ; break ; case MCK__HASH_8 : ExpectedVal = 8 ; break ; case MCK_MPR : if ( Op . isTokenEqual ( "za" ) ) return Match_Success ; return Match_InvalidOperand ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void aarch64_expand_mov_immediate ( rtx dest , rtx imm ) { machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( mode == SImode || mode == DImode ) ; if ( GET_CODE ( imm ) == SYMBOL_REF || GET_CODE ( imm ) == LABEL_REF || GET_CODE ( imm ) == CONST ) { rtx mem , base , offset ; enum aarch64_symbol_type sty ; split_const ( imm , & base , & offset ) ; sty = aarch64_classify_symbol ( base , offset , SYMBOL_CONTEXT_ADR ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( offset != const0_rtx && targetm . cannot_force_const_mem ( mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_GOTTPREL : case SYMBOL_SMALL_GOT : case SYMBOL_TINY_GOT : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_TPREL : case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_CODE ( imm ) == HIGH ) emit_insn ( gen_rtx_SET ( VOIDmode , dest , imm ) ) ; else { rtx mem = force_const_mem ( mode , imm ) ; gcc_assert ( mem ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , mem ) ) ; } return ; } aarch64_internal_mov_immediate ( dest , imm , true , GET_MODE ( dest ) ) ; } </s>

Set DEST to immediate IMM . For SVE vector modes , GEN_VEC_DUPLICATE is a pattern that can be used to set DEST to a replicated scalar element .


<s> static void aarch64_emit_post_barrier ( enum memmodel model ) { const enum memmodel base_model = memmodel_base ( model ) ; if ( is_mm_sync ( model ) && ( base_model == MEMMODEL_ACQUIRE || base_model == MEMMODEL_ACQ_REL || base_model == MEMMODEL_SEQ_CST ) ) { emit_insn ( gen_mem_thread_fence ( GEN_INT ( MEMMODEL_SEQ_CST ) ) ) ; } } </s>

Emit a barrier , that is appropriate for memory model MODEL , at the end of a sequence implementing an atomic operation .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { fixIMPLICITDEF ( MF ) ; fixNoReturn ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MipsInstrInfo :: SafeInLoadDelaySlot ( const MachineInstr & MIInSlot , const MachineInstr & LoadMI ) const { if ( MIInSlot . isInlineAsm ( ) ) return false ; return ! llvm :: any_of ( LoadMI . defs ( ) , [ & ] ( const MachineOperand & Op ) { return Op . isReg ( ) && MIInSlot . readsRegister ( Op . getReg ( ) ) ; } ) ; } </s>

Predicate to determine if an instruction can go in a load delay slot .


<s> static void pru_function_arg_regi_mark_slot ( int regi , cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT param_size = pru_function_arg_size ( mode , type ) ; gcc_assert ( named ) ; while ( param_size -- ) { gcc_assert ( regi >= FIRST_ARG_REGNUM && regi <= LAST_ARG_REGNUM ) ; gcc_assert ( ! cum -> regs_used [ regi - FIRST_ARG_REGNUM ] ) ; cum -> regs_used [ regi - FIRST_ARG_REGNUM ] = true ; regi ++ ; } } </s>

Mark CUM_V that a function argument will occupy HW register slot starting at REGI . The number of consecutive 8-bit HW registers marked as occupied depends on the MODE and TYPE of the argument .


<s>
static
void
ix86_avoid_jump_mispredicts
(
void
)
{
rtx_insn
*
insn
,
*
start
=
get_insns
(
)
;
int
nbytes
=
0
,
njumps
=
0
;
bool
isjump
=
false
;
for
(
insn
=
start
;
insn
;
insn
=
NEXT_INSN
(
insn
)
)
{
int
min_size
;
if
(
LABEL_P
(
insn
)
)
{
align_flags
alignment
=
label_to_alignment
(
insn
)
;
int
align
=
alignment
.
levels
[
0
]
.
log
;
int
max_skip
=
alignment
.
levels
[
0
]
.
maxskip
;
if
(
max_skip
>
15
)
max_skip
=
15
;
if
(
align
<=
0
||
(
align
<=
3
&&
max_skip
!=
(
1
<<
align
)
1
)
)
max_skip
=
0
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Label %i with max_skip %i\n"
,
INSN_UID
(
insn
)
,
max_skip
)
;
if
(
max_skip
)
{
while
(
nbytes
+
max_skip
>=
16
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
JUMP_P
(
start
)
&&
asm_noperands
(
PATTERN
(
start
)
)
<
0
)
||
CALL_P
(
start
)
)
njumps
,
isjump
=
true
;
else
isjump
=
false
;
nbytes
-=
ix86_min_insn_size
(
start
)
;
}
}
continue
;
}
min_size
=
ix86_min_insn_size
(
insn
)
;
nbytes
+=
min_size
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Insn %i estimated to %i bytes\n"
,
INSN_UID
(
insn
)
,
min_size
)
;
if
(
(
JUMP_P
(
insn
)
&&
asm_noperands
(
PATTERN
(
insn
)
)
<
0
)
||
CALL_P
(
insn
)
)
njumps
++
;
else
continue
;
while
(
njumps
>
3
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
JUMP_P
(
start
)
&&
asm_noperands
(
PATTERN
(
start
)
)
<
0
)
||
CALL_P
(
start
)
)
njumps
,
isjump
=
true
;
else
isjump
=
false
;
nbytes
-=
ix86_min_insn_size
(
start
)
;
}
gcc_assert
(
njumps
>=
0
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Interval %i to %i has %i bytes\n"
,
INSN_UID
(
start
)
,
INSN_UID
(
insn
)
,
nbytes
)
;
if
(
njumps
==
3
&&
isjump
&&
nbytes
<
16
)
{
int
padsize
=
15
nbytes
+
ix86_min_insn_size
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Padding insn %i by %i bytes!\n"
,
INSN_UID
(
insn
)
,
padsize
)
;
emit_insn_before
(
gen_pad
(
GEN_INT
(
padsize
)
)
,
insn
)
;
}
}
}
</s>

AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte window .


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
(
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
||
pattern_is_rotate64
(
body
)
)
&&
MEM_P
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
auto_vec
<
rtx_insn
*
>
and_insns
;
auto_vec
<
rtx
>
and_ops
;
bool
is_any_def_and
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insns
,
&
and_ops
)
;
if
(
is_any_def_and
)
{
gcc_assert
(
and_insns
.
length
(
)
==
and_ops
.
length
(
)
)
;
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
new_reg
=
0
;
rtx
and_mask
=
0
;
for
(
unsigned
i
=
0
;
i
<
and_insns
.
length
(
)
;
i
++
)
{
rtx_insn
*
and_insn
=
and_insns
[
i
]
;
rtx
and_op
=
and_ops
[
i
]
;
rtx
and_base
=
XEXP
(
and_op
,
0
)
;
if
(
!
new_reg
)
{
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
and_mask
=
XEXP
(
and_op
,
1
)
;
}
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
}
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
new_reg
)
,
new_reg
,
and_mask
)
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> static bool mips16e_collect_argument_save_p ( rtx dest , rtx src , rtx * reg_values , unsigned int * regno_ptr ) { unsigned int argno , regno ; HOST_WIDE_INT offset , required_offset ; rtx addr , base ; if ( ! MEM_P ( dest ) || ! REG_P ( src ) || GET_MODE ( dest ) != word_mode ) return false ; regno = REGNO ( src ) ; if ( ! IN_RANGE ( regno , GP_ARG_FIRST , GP_ARG_LAST ) || reg_values [ regno ] ) return false ; argno = regno - GP_ARG_FIRST ; addr = mips16e_collect_propagate_value ( XEXP ( dest , 0 ) , reg_values ) ; mips_split_plus ( addr , & base , & offset ) ; required_offset = cfun -> machine -> frame . total_size + argno * UNITS_PER_WORD ; if ( base == hard_frame_pointer_rtx ) required_offset -= cfun -> machine -> frame . hard_frame_pointer_offset ; else if ( base != stack_pointer_rtx ) return false ; if ( offset != required_offset ) return false ; * regno_ptr = regno ; return true ; } </s>

Return true if ( set DEST SRC ) stores an argument register into its caller-allocated save slot , storing the number of that argument register in * REGNO_PTR if so . REG_VALUES is as for mips16e_collect_propagate_value .


<s> static bool mflip_mips16_use_mips16_p ( tree decl ) { const char * name ; bool base_is_mips16 = ( mips_base_compression_flags & MASK_MIPS16 ) != 0 ; if ( ! DECL_NAME ( decl ) ) return ! base_is_mips16 ; if ( ! mflip_mips16_htab ) mflip_mips16_htab = hash_map < const char * , bool , mips16_flip_traits > :: create_ggc ( 37 ) ; name = IDENTIFIER_POINTER ( DECL_NAME ( decl ) ) ; bool existed ; bool * slot = & mflip_mips16_htab -> get_or_insert ( name , & existed ) ; if ( ! existed ) { mips16_flipper = ! mips16_flipper ; * slot = mips16_flipper ? ! base_is_mips16 : base_is_mips16 ; } return * slot ; } </s>

DECL is a function that needs a default `` mips16 '' or `` nomips16 '' attribute for -mflip-mips16 . Return true if it should use `` mips16 '' and false if it should use `` nomips16 '' .


<s> static tree rs6000_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { HOST_WIDE_INT fnmask ; if ( code >= RS6000_BUILTIN_COUNT ) return error_mark_node ; fnmask = rs6000_builtin_info [ code ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) { rs6000_invalid_builtin ( ( enum rs6000_builtins ) code ) ; return error_mark_node ; } return rs6000_builtin_decls [ code ] ; } </s>

Returns the rs6000 builtin decl for CODE .


<s> void SystemZELFFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: ELFCallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; } if ( MF . front ( ) . isLiveIn ( SystemZ :: R6D ) && ZFI -> getRestoreGPRRegs ( ) . LowGPR != SystemZ :: R6D ) for ( auto & MO : MRI -> use_nodbg_operands ( SystemZ :: R6D ) ) MO . setIsKill ( false ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"passing %qT to argument %d of %qE, which"

" when using a vector of base addresses"

"passing %qT to argument %d of %qE, but %qT is not"

" expects a pointer to 32-bit or 64-bit elements"

Require argument ARGNO to be a pointer to a scalar type that has a corresponding type suffix . Return that type suffix on success , otherwise report an error and return NUM_TYPE_SUFFIXES . GATHER_SCATTER_P is true if the function is a gather/scatter operation , and so requires a pointer to 32-bit or 64-bit data .


Store the specified register of the given register class to the specified stack frame index .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"fixupNeedsRelaxation() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool umips_build_save_restore ( mips_save_restore_fn fn , unsigned * mask , HOST_WIDE_INT * offset ) { int nregs ; unsigned int i , j ; rtx pattern , set , reg , mem ; HOST_WIDE_INT this_offset ; rtx this_base ; for ( i = 0 ; i < ARRAY_SIZE ( umips_swm_mask ) ; i ++ ) if ( ( * mask & 0xffff0000 ) == umips_swm_mask [ i ] ) break ; if ( i == ARRAY_SIZE ( umips_swm_mask ) ) return false ; nregs = ( umips_swm_encoding [ i ] & 0xf ) + ( umips_swm_encoding [ i ] >> 4 ) ; this_offset = * offset - UNITS_PER_WORD * ( nregs - 1 ) ; if ( ! UMIPS_12BIT_OFFSET_P ( this_offset ) ) return false ; pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs ) ) ; this_base = stack_pointer_rtx ; for ( j = 0 ; j < ( umips_swm_encoding [ i ] & 0xf ) ; j ++ ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; unsigned int regno = ( j != 8 ) ? 16 + j : 30 ; * mask &= ~ ( 1 << regno ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , 0 , j ) = set ; } if ( umips_swm_encoding [ i ] >> 4 ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; * mask &= ~ ( 1 << 31 ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; reg = gen_rtx_REG ( SImode , 31 ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , 0 , j ) = set ; } pattern = emit_insn ( pattern ) ; if ( fn == mips_save_reg ) RTX_FRAME_RELATED_P ( pattern ) = 1 ; * offset -= UNITS_PER_WORD * nregs ; return true ; } </s>

Try to use a microMIPS LWM or SWM instruction to save or restore as many GPRs in * MASK as possible . * OFFSET is the offset from the stack pointer of the topmost save slot . Remove from * MASK all registers that were handled using LWM and SWM . Update * OFFSET so that it points to the first unused save slot .


<s> machine_mode mips_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , NULL ) ; else return mode ; } </s>


<s>
void
ARMAsmPrinter
::
PrintSymbolOperand
(
const
MachineOperand
&
MO
,
raw_ostream
&
O
)
{
assert
(
MO
.
isGlobal
(
)
&&
"caller should check MO.isGlobal"
)
;
unsigned
TF
=
MO
.
getTargetFlags
(
)
;
if
(
TF
&
ARMII
::
MO_LO16
)
O
<<
":lower16:"
;
else
if
(
TF
&
ARMII
::
MO_HI16
)
O
<<
":upper16:"
;
GetARMGVSymbol
(
MO
.
getGlobal
(
)
,
TF
)
->
print
(
O
,
MAI
)
;
printOffset
(
MO
.
getOffset
(
)
,
O
)
;
}
</s>


"MMIX Internal: %s is not a shiftable int"

Print the presumed shiftable wyde argument shifted into place ( to be output with an operand ) .


<s> static void aarch64_emit_unspec_cond ( rtx target , rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) { rtx unspec = aarch64_gen_unspec_cond ( code , pred_mode , pred , op0 , op1 ) ; emit_set_insn ( target , unspec ) ; } </s>

Emit an instruction : ( set TARGET ( unspec : PRED_MODE [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) ) where < X > is the operation associated with comparison CODE .


<s> static int power6_sched_reorder2 ( rtx_insn * * ready , int lastpos ) { int pos ; rtx load_mem , str_mem ; if ( is_store_insn ( last_scheduled_insn , & str_mem ) ) load_store_pendulum -- ; else if ( is_load_insn ( last_scheduled_insn , & load_mem ) ) load_store_pendulum ++ ; else return cached_can_issue_more ; if ( ( load_store_pendulum == 0 ) || ( lastpos <= 0 ) ) return cached_can_issue_more ; if ( load_store_pendulum == 1 ) { pos = lastpos ; while ( pos >= 0 ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) ) { move_to_end_of_ready ( ready , pos , lastpos ) ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ lastpos ] ) ) INSN_PRIORITY ( ready [ lastpos ] ) ++ ; break ; } pos -- ; } } else if ( load_store_pendulum == - 2 ) { pos = lastpos ; while ( pos >= 0 ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum -- ; break ; } pos -- ; } } else if ( load_store_pendulum == - 1 ) { int first_store_pos = - 1 ; pos = lastpos ; while ( pos >= 0 ) { if ( is_store_insn ( ready [ pos ] , & str_mem ) ) { rtx str_mem2 ; if ( first_store_pos == - 1 ) first_store_pos = pos ; if ( is_store_insn ( last_scheduled_insn , & str_mem2 ) && adjacent_mem_locations ( str_mem , str_mem2 ) ) { move_to_end_of_ready ( ready , pos , lastpos ) ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ lastpos ] ) ) INSN_PRIORITY ( ready [ lastpos ] ) ++ ; first_store_pos = - 1 ; break ; } ; } pos -- ; } if ( first_store_pos >= 0 ) { move_to_end_of_ready ( ready , first_store_pos , lastpos ) ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ lastpos ] ) ) INSN_PRIORITY ( ready [ lastpos ] ) ++ ; } } else if ( load_store_pendulum == 2 ) { pos = lastpos ; while ( pos >= 0 ) { if ( is_store_insn ( ready [ pos ] , & str_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum ++ ; break ; } pos -- ; } } return cached_can_issue_more ; } </s>

Do Power6 specific sched_reorder2 reordering of ready list .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; } tocrel_base = op ; tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


<s> static void arm_unwind_emit ( FILE * asm_out_file , rtx insn ) { rtx pat ; if ( ! ARM_EABI_UNWIND_TABLES ) return ; if ( GET_CODE ( insn ) == NOTE || ! RTX_FRAME_RELATED_P ( insn ) ) return ; pat = find_reg_note ( insn , REG_FRAME_RELATED_EXPR , NULL_RTX ) ; if ( pat ) pat = XEXP ( pat , 0 ) ; else pat = PATTERN ( insn ) ; switch ( GET_CODE ( pat ) ) { case SET : arm_unwind_emit_set ( asm_out_file , pat ) ; break ; case SEQUENCE : arm_unwind_emit_stm ( asm_out_file , pat ) ; break ; default : abort ( ) ; } } </s>

Emit unwind directives for the given insn .


<s> void ia64_expand_widen_sum ( rtx operands [ 3 ] , bool unsignedp ) { machine_mode wmode ; rtx l , h , t , sign ; sign = ia64_unpack_sign ( operands [ 1 ] , unsignedp ) ; wmode = GET_MODE ( operands [ 0 ] ) ; l = gen_reg_rtx ( wmode ) ; h = gen_reg_rtx ( wmode ) ; ia64_unpack_assemble ( l , operands [ 1 ] , sign , false ) ; ia64_unpack_assemble ( h , operands [ 1 ] , sign , true ) ; t = expand_binop ( wmode , add_optab , l , operands [ 2 ] , NULL , 0 , OPTAB_DIRECT ) ; t = expand_binop ( wmode , add_optab , h , t , operands [ 0 ] , 0 , OPTAB_DIRECT ) ; if ( t != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , t ) ; } </s>

Emit an integral vector widening sum operations .


<s> static void def_or_undef_macro ( struct cpp_reader * pfile , const char * name , bool def_p ) { if ( def_p ) cpp_define ( pfile , name ) ; else cpp_undef ( pfile , name ) ; } </s>

Define or undefine macros based on the current target . If the user does # pragma GCC target , we need to adjust the macros dynamically .


<s> const char * X86TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget -> hasSSE2 ( ) ) return "Y" ; if ( Subtarget -> hasSSE1 ( ) ) return "x" ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s>
unsigned
ARMTTIImpl
::
getGatherScatterOpCost
(
unsigned
Opcode
,
Type
*
DataTy
,
Value
*
Ptr
,
bool
VariableMask
,
unsigned
Alignment
)
{
if
(
!
ST
->
hasMVEIntegerOps
(
)
||
!
EnableMaskedGatherScatters
)
return
BaseT
::
getGatherScatterOpCost
(
Opcode
,
DataTy
,
Ptr
,
VariableMask
,
Alignment
)
;
assert
(
DataTy
->
isVectorTy
(
)
&&
"Can't do gather/scatters on scalar!"
)
;
VectorType
*
VTy
=
cast
<
VectorType
>
(
DataTy
)
;
unsigned
NumElems
=
VTy
->
getNumElements
(
)
;
unsigned
EltSize
=
VTy
->
getScalarSizeInBits
(
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
DataTy
)
;
unsigned
VectorCost
=
NumElems
*
LT
.
first
;
unsigned
ScalarCost
=
NumElems
*
LT
.
first
+
BaseT
::
getScalarizationOverhead
(
DataTy
,
{
}
)
;
if
(
EltSize
*
NumElems
!=
128
||
NumElems
<
4
)
return
ScalarCost
;
if
(
Alignment
<
EltSize
/
8
)
return
ScalarCost
;
if
(
EltSize
==
32
)
return
VectorCost
;
if
(
EltSize
!=
8
&&
EltSize
!=
16
)
return
ScalarCost
;
if
(
auto
BC
=
dyn_cast
<
BitCastInst
>
(
Ptr
)
)
Ptr
=
BC
->
getOperand
(
0
)
;
if
(
auto
*
GEP
=
dyn_cast
<
GetElementPtrInst
>
(
Ptr
)
)
{
if
(
GEP
->
getNumOperands
(
)
!=
2
)
return
ScalarCost
;
unsigned
Scale
=
DL
.
getTypeAllocSize
(
GEP
->
getResultElementType
(
)
)
;
if
(
Scale
!=
1
&&
Scale
*
8
!=
EltSize
)
return
ScalarCost
;
if
(
auto
ZExt
=
dyn_cast
<
ZExtInst
>
(
GEP
->
getOperand
(
1
)
)
)
if
(
ZExt
->
getOperand
(
0
)
->
getType
(
)
->
getScalarSizeInBits
(
)
<=
EltSize
)
return
VectorCost
;
return
ScalarCost
;
}
return
ScalarCost
;
}
</s>

Calculate the cost of Gather / Scatter operation .


<s>
bool
ARMAsmParser
::
ParseInstruction
(
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
StringRef
Head
=
Name
.
slice
(
Start
,
Next
)
;
unsigned
PredicationCode
;
unsigned
ProcessorIMod
;
bool
CarrySetting
;
Head
=
SplitMnemonic
(
Head
,
PredicationCode
,
CarrySetting
,
ProcessorIMod
)
;
Operands
.
push_back
(
ARMOperand
::
CreateToken
(
Head
,
NameLoc
)
)
;
bool
CanAcceptCarrySet
,
CanAcceptPredicationCode
;
GetMnemonicAcceptInfo
(
Head
,
CanAcceptCarrySet
,
CanAcceptPredicationCode
)
;
if
(
CanAcceptCarrySet
)
{
Operands
.
push_back
(
ARMOperand
::
CreateCCOut
(
CarrySetting
ARM
::
CPSR
:
0
,
NameLoc
)
)
;
}
else
{
}
if
(
CanAcceptPredicationCode
)
{
Operands
.
push_back
(
ARMOperand
::
CreateCondCode
(
ARMCC
::
CondCodes
(
PredicationCode
)
,
NameLoc
)
)
;
}
else
{
}
if
(
ProcessorIMod
)
{
Operands
.
push_back
(
ARMOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
ProcessorIMod
,
getContext
(
)
)
,
NameLoc
,
NameLoc
)
)
;
}
else
{
}
while
(
Next
!=
StringRef
::
npos
)
{
Start
=
Next
;
Next
=
Name
.
find
(
'.'
,
Start
+
1
)
;
StringRef
ExtraToken
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
ARMOperand
::
CreateToken
(
ExtraToken
,
NameLoc
)
)
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Head
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Head
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
true
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
EatToEndOfStatement
(
)
;
return
TokError
(
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

ARM
ARM
0
ARM
ARM
ARM::CPSR
0
ARM
ARMCC::CondCodes
ARM
1
ARM
"unexpected token in argument list"


Output assembly language to define a symbol as COMMON from a DECL , possibly with visibility .


<s> bool ARMFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned CFSize = MFI . getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; if ( VT . isSimple ( ) ) { MVT VVT = VT . getSimpleVT ( ) ; const unsigned NumElts = VVT . getVectorNumElements ( ) ; MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget . hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget . hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) return MVT :: getVectorVT ( MVT :: i1 , NumElts ) ; if ( ! isTypeLegal ( VT ) && getTypeAction ( Context , VT ) == TypePromoteInteger ) { EVT LegalVT = getTypeToTransformTo ( Context , VT ) ; EltVT = LegalVT . getVectorElementType ( ) . getSimpleVT ( ) ; } if ( Subtarget . hasVLX ( ) && EltVT . getSizeInBits ( ) >= 32 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
->
optForSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LiveRegs
.
init
(
&
TII
->
getRegisterInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool X86AsmParser :: processInstruction ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Ops ) { switch ( Inst . getOpcode ( ) ) { default : return false ; case X86 :: AND16i16 : return convert16i16to16ri8 ( Inst , X86 :: AND16ri8 ) ; case X86 :: AND32i32 : return convert32i32to32ri8 ( Inst , X86 :: AND32ri8 ) ; case X86 :: AND64i32 : return convert64i32to64ri8 ( Inst , X86 :: AND64ri8 ) ; case X86 :: XOR16i16 : return convert16i16to16ri8 ( Inst , X86 :: XOR16ri8 ) ; case X86 :: XOR32i32 : return convert32i32to32ri8 ( Inst , X86 :: XOR32ri8 ) ; case X86 :: XOR64i32 : return convert64i32to64ri8 ( Inst , X86 :: XOR64ri8 ) ; case X86 :: OR16i16 : return convert16i16to16ri8 ( Inst , X86 :: OR16ri8 ) ; case X86 :: OR32i32 : return convert32i32to32ri8 ( Inst , X86 :: OR32ri8 ) ; case X86 :: OR64i32 : return convert64i32to64ri8 ( Inst , X86 :: OR64ri8 ) ; case X86 :: CMP16i16 : return convert16i16to16ri8 ( Inst , X86 :: CMP16ri8 , true ) ; case X86 :: CMP32i32 : return convert32i32to32ri8 ( Inst , X86 :: CMP32ri8 , true ) ; case X86 :: CMP64i32 : return convert64i32to64ri8 ( Inst , X86 :: CMP64ri8 , true ) ; case X86 :: ADD16i16 : return convert16i16to16ri8 ( Inst , X86 :: ADD16ri8 ) ; case X86 :: ADD32i32 : return convert32i32to32ri8 ( Inst , X86 :: ADD32ri8 ) ; case X86 :: ADD64i32 : return convert64i32to64ri8 ( Inst , X86 :: ADD64ri8 ) ; case X86 :: SUB16i16 : return convert16i16to16ri8 ( Inst , X86 :: SUB16ri8 ) ; case X86 :: SUB32i32 : return convert32i32to32ri8 ( Inst , X86 :: SUB32ri8 ) ; case X86 :: SUB64i32 : return convert64i32to64ri8 ( Inst , X86 :: SUB64ri8 ) ; case X86 :: ADC16i16 : return convert16i16to16ri8 ( Inst , X86 :: ADC16ri8 ) ; case X86 :: ADC32i32 : return convert32i32to32ri8 ( Inst , X86 :: ADC32ri8 ) ; case X86 :: ADC64i32 : return convert64i32to64ri8 ( Inst , X86 :: ADC64ri8 ) ; case X86 :: SBB16i16 : return convert16i16to16ri8 ( Inst , X86 :: SBB16ri8 ) ; case X86 :: SBB32i32 : return convert32i32to32ri8 ( Inst , X86 :: SBB32ri8 ) ; case X86 :: SBB64i32 : return convert64i32to64ri8 ( Inst , X86 :: SBB64ri8 ) ; } } </s>

Process a single instruction and collect debug info anchors .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_ROUNDEVEN : case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function entry .


<s> int arm_hard_regno_mode_ok ( unsigned int regno , enum machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && TARGET_VFP && regno == VFPCC_REGNUM ) ) ; if ( TARGET_THUMB ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && TARGET_MAVERICK && IS_CIRRUS_REGNUM ( regno ) ) return ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) || ( mode == DImode ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return TRUE ; if ( mode == DFmode ) return ( ( regno - FIRST_VFP_REGNUM ) & 1 ) == 0 ; return FALSE ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return ( TARGET_HARD_FLOAT && TARGET_FPA && GET_MODE_CLASS ( mode ) == MODE_FLOAT && regno >= FIRST_FPA_REGNUM && regno <= LAST_FPA_REGNUM ) ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> static rtx sparc_function_value_1 ( const_tree type , machine_mode mode , bool outgoing ) { int regbase = ( outgoing ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 32 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_record_value ( type , mode , 0 , 1 , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } else if ( TARGET_ARCH32 && ! ( type && AGGREGATE_TYPE_P ( type ) ) && mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle TARGET_FUNCTION_VALUE , and TARGET_LIBCALL_VALUE target hook . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel" "ppc-got"


<s>
static
bool
rs6000_declare_alias
(
struct
symtab_node
*
n
,
void
*
d
)
{
struct
declare_alias_data
*
data
=
(
struct
declare_alias_data
*
)
d
;
if
(
!
n
->
alias
||
n
->
weakref
)
return
false
;
if
(
lookup_attribute
(
"ifunc"
,
DECL_ATTRIBUTES
(
n
->
decl
)
)
)
return
false
;
TREE_ASM_WRITTEN
(
n
->
decl
)
=
true
;
const
char
*
name
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
n
->
decl
)
)
;
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
2
)
;
char
*
p
;
int
dollar_inside
=
0
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
n
->
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
n
->
decl
)
)
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
else
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
fputs
(
"\t.globl ."
,
data
->
file
)
;
else
fputs
(
"\t.globl "
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
else
if
(
DECL_WEAK
(
n
->
decl
)
&&
!
data
->
function_descriptor
)
ASM_WEAKEN_DECL
(
data
->
file
,
n
->
decl
,
name
,
)
;
}
else
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
else
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
fputs
(
"\t.lglobl ."
,
data
->
file
)
;
else
fputs
(
"\t.lglobl "
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
if
(
data
->
function_descriptor
)
fputs
(
"."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
fputs
(
":\n"
,
data
->
file
)
;
return
false
;
}
</s>

Declare alias N. A helper function for for_node_and_aliases .


<s> bool SystemZPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && getSystemZTargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int64_t Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) + Subtarget . getStackPointerBias ( ) ; SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; unsigned FramePtr = SP :: I6 ; if ( FuncInfo -> isLeafProc ( ) ) { FramePtr = SP :: O6 ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; Offset += ( stackSize ) ? Subtarget . getAdjustedFrameSize ( stackSize ) : 0 ; } if ( Offset >= - 4096 && Offset <= 4095 ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FramePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } else { const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; unsigned OffHi = ( unsigned ) Offset >> 10U ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: ADDrr ) , SP :: G1 ) . addReg ( SP :: G1 ) . addReg ( FramePtr ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( SP :: G1 , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset & ( ( 1 << 10 ) - 1 ) ) ; } } </s>


<s> FastISel * AArch64 :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { return new AArch64FastISel ( FuncInfo , LibInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s>
InstructionCost
AArch64TTIImpl
::
getMinMaxReductionCost
(
VectorType
*
Ty
,
VectorType
*
CondTy
,
bool
IsUnsigned
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
!
isa
<
ScalableVectorType
>
(
Ty
)
)
return
BaseT
::
getMinMaxReductionCost
(
Ty
,
CondTy
,
IsUnsigned
,
CostKind
)
;
assert
(
(
isa
<
ScalableVectorType
>
(
Ty
)
&&
isa
<
ScalableVectorType
>
(
CondTy
)
)
&&
"Both vector needs to be scalable"
)
;
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
Ty
)
;
InstructionCost
LegalizationCost
=
0
;
if
(
LT
.
first
>
1
)
{
Type
*
LegalVTy
=
EVT
(
LT
.
second
)
.
getTypeForEVT
(
Ty
->
getContext
(
)
)
;
unsigned
CmpOpcode
=
Ty
->
isFPOrFPVectorTy
(
)
Instruction
::
FCmp
:
Instruction
::
ICmp
;
LegalizationCost
=
getCmpSelInstrCost
(
CmpOpcode
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
+
getCmpSelInstrCost
(
Instruction
::
Select
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
;
LegalizationCost
*=
LT
.
first
1
;
}
return
LegalizationCost
+
2
;
}
</s>

Try to calculate op costs for min/max reduction operations .


<s> static rtx ix86_expand_aligntest ( rtx variable , int value ) { rtx label = gen_label_rtx ( ) ; rtx tmpcount = gen_reg_rtx ( GET_MODE ( variable ) ) ; if ( GET_MODE ( variable ) == DImode ) emit_insn ( gen_anddi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; else emit_insn ( gen_andsi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; emit_cmp_and_jump_insns ( tmpcount , const0_rtx , EQ , 0 , GET_MODE ( variable ) , 1 , label ) ; return label ; } </s>

Helper function for the string operations below . Dest VARIABLE whether it is aligned to VALUE bytes . If true , jump to the label .


<s> int sh_media_register_for_return ( void ) { int regno ; int tr0_used ; if ( ! crtl -> is_leaf ) return - 1 ; if ( lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( current_function_decl ) ) ) return - 1 ; if ( sh_cfun_interrupt_handler_p ( ) ) return - 1 ; tr0_used = flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ; for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_really_used_regs [ regno ] && ! df_regs_ever_live_p ( regno ) ) return regno ; return - 1 ; } </s>

Choose a call-clobbered target-branch register that remains unchanged along the whole function . We set it up as the return value in the prologue .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool ARMSubtarget :: useDFAforSMS ( ) const { return false ; } </s>

Default to DFA for resource management , return false when target will use ProcResource in InstrSchedModel instead .


<s> static void emit_and_preserve ( rtx seq , rtx reg , rtx reg2 ) { HOST_WIDE_INT offset = 16 * UNITS_PER_WORD ; HOST_WIDE_INT size = SPARC_STACK_ALIGN ( offset + 2 * UNITS_PER_WORD ) ; rtx slot = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , stack_pointer_rtx , SPARC_STACK_BIAS + offset ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - size ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , slot , reg ) ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( VOIDmode , adjust_address ( slot , word_mode , UNITS_PER_WORD ) , reg2 ) ) ; emit_insn ( seq ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( VOIDmode , reg2 , adjust_address ( slot , word_mode , UNITS_PER_WORD ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , slot ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; } </s>

Emit the sequence of insns SEQ while preserving the registers .


<s> const MCPhysReg * VERegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; bool CanImplicitFloat = ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = IsMemset && Size < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , 16 ) ) return MVT :: v2i64 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , 16 ) ) return MVT :: f128 ; if ( Size >= 8 && AlignmentIsAcceptable ( MVT :: i64 , 8 ) ) return MVT :: i64 ; if ( Size >= 4 && AlignmentIsAcceptable ( MVT :: i32 , 4 ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> MachineBasicBlock :: iterator Cpu0FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = Cpu0 :: SP ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Cpu0 :: ADJCALLSTACKDOWN ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
for
(
MachineInstr
&
MI
:
MBB
)
{
if
(
!
MI
.
isFullCopy
(
)
)
continue
;
MachineOperand
&
DstMO
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
SrcMO
=
MI
.
getOperand
(
1
)
;
if
(
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
!
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
SrcRC
=
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown source for a VSX copy"
)
;
Register
NewVReg
=
MRI
.
createVirtualRegister
(
SrcRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
SUBREG_TO_REG
)
,
NewVReg
)
.
addImm
(
1
)
.
add
(
SrcMO
)
.
addImm
(
PPC
::
sub_64
)
;
SrcMO
.
setReg
(
NewVReg
)
;
}
else
if
(
!
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
DstRC
=
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
DstMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown destination for a VSX copy"
)
;
Register
NewVReg
=
MRI
.
createVirtualRegister
(
DstRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
NewVReg
)
.
add
(
SrcMO
)
;
SrcMO
.
setReg
(
NewVReg
)
;
SrcMO
.
setSubReg
(
PPC
::
sub_64
)
;
}
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> bool rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; machine_mode mode = GET_MODE ( dest ) ; enum rtx_code cond_code ; rtx ( * isel_func ) ( rtx , rtx , rtx , rtx , rtx ) ; bool signedp ; if ( mode != SImode && ( ! TARGET_POWERPC64 || mode != DImode ) ) return false ; if ( GET_MODE_CLASS ( GET_MODE ( XEXP ( op , 0 ) ) ) == MODE_CC ) return false ; condition_rtx = rs6000_generate_compare ( op , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; cr = XEXP ( condition_rtx , 0 ) ; signedp = GET_MODE ( cr ) == CCmode ; isel_func = ( mode == SImode ? ( signedp ? gen_isel_cc_si : gen_isel_ccuns_si ) : ( signedp ? gen_isel_cc_di : gen_isel_ccuns_di ) ) ; switch ( cond_code ) { case LT : case GT : case LTU : case GTU : case EQ : break ; default : { std :: swap ( false_cond , true_cond ) ; PUT_CODE ( condition_rtx , reverse_condition ( cond_code ) ) ; } break ; } false_cond = force_reg ( mode , false_cond ) ; if ( true_cond != const0_rtx ) true_cond = force_reg ( mode , true_cond ) ; emit_insn ( isel_func ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return true ; } </s>


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; if ( GET_CODE ( addr ) == CONST ) { poly_int64 addend ; rtx sym = strip_offset ( addr , & addend ) ; if ( GET_CODE ( sym ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( sym ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s>
SDValue
AArch64TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
CCAssignFn
*
RetCC
=
CallConv
==
CallingConv
::
WebKit_JS
RetCC_AArch64_WebKit_JS
:
RetCC_AArch64_AAPCS
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
realRVLocIdx
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
,
++
realRVLocIdx
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
realRVLocIdx
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
if
(
Outs
[
i
]
.
ArgVT
==
MVT
::
i1
)
{
Arg
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
MVT
::
i1
,
Arg
)
;
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
Arg
)
;
}
break
;
case
CCValAssign
::
BCvt
:
Arg
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
AArch64ISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned getBasePointerSaveOffset ( ) const { return BasePointerSaveOffset ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


<s> bool ARMInstrInfo :: PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: B || Opc == ARM :: tB ) { MI -> setDesc ( get ( Opc == ARM :: B ? ARM :: Bcc : ARM :: tBcc ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ 0 ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ 1 ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setImm ( Pred [ 0 ] . getImm ( ) ) ; MI -> getOperand ( PIdx + 1 ) . setReg ( Pred [ 1 ] . getReg ( ) ) ; return true ; } return false ; } </s>

Convert the instruction into a predicated instruction .


<s> BitVector VERegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const Register ReservedRegs [ ] = { VE :: SX8 , VE :: SX9 , VE :: SX10 , VE :: SX11 , VE :: SX12 , VE :: SX13 , VE :: SX14 , VE :: SX15 , VE :: SX16 , VE :: SX17 , } ; for ( auto R : ReservedRegs ) for ( MCRegAliasIterator ItAlias ( R , this , true ) ; ItAlias . isValid ( ) ; ++ ItAlias ) Reserved . set ( * ItAlias ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> int iq2000_can_use_return_insn ( void ) { if ( ! reload_completed ) return 0 ; if ( regs_ever_live [ 31 ] || profile_flag ) return 0 ; if ( cfun -> machine -> initialized ) return cfun -> machine -> total_size == 0 ; return compute_frame_size ( get_frame_size ( ) ) == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ( ! SYMBOL_REF_LOCAL_P ( x ) || ( SYMBOL_REF_DECL ( x ) ? DECL_WEAK ( SYMBOL_REF_DECL ( x ) ) : 0 ) ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , as_a < scalar_float_mode > ( GET_MODE_INNER ( mode ) ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
KindReg
&&
"Not a register"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> MCSymbol * AArch64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; } </s>

Return the symbol for the specified constant pool entry .


"multiple save reg attributes to function %qD"

"multiple nested types attributes to function %qD"

"multiple interrupt attributes to function %qD"

Function for nds32_merge_decl_attributes ( ) and nds32_insert_attributes ( ) to check if there are any conflict isr-specific attributes being set . We need to check : 1 . Only 'save_all ' or 'partial_save ' in the attributes . 2 . Only 'nested ' , 'not_nested ' , or 'nested_ready ' in the attributes . 3 . Only 'interrupt ' , 'exception ' , or 'reset ' in the attributes .


<s> virtual const IA64InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


"AltiVec argument passed to unprototyped function"

Target hook for invalid_arg_for_unprototyped_fn .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = getMipsRegisterNumbering ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; Mips :: Fixups FixupKind = Mips :: Fixups ( 0 ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { case MCSymbolRefExpr :: VK_Mips_GPREL : FixupKind = Mips :: fixup_Mips_GPREL16 ; break ; case MCSymbolRefExpr :: VK_Mips_GOT_CALL : FixupKind = Mips :: fixup_Mips_CALL16 ; break ; case MCSymbolRefExpr :: VK_Mips_GOT16 : FixupKind = Mips :: fixup_Mips_GOT_Global ; break ; case MCSymbolRefExpr :: VK_Mips_GOT : FixupKind = Mips :: fixup_Mips_GOT_Local ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_HI : FixupKind = Mips :: fixup_Mips_HI16 ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_LO : FixupKind = Mips :: fixup_Mips_LO16 ; break ; case MCSymbolRefExpr :: VK_Mips_TLSGD : FixupKind = Mips :: fixup_Mips_TLSGD ; break ; case MCSymbolRefExpr :: VK_Mips_TLSLDM : FixupKind = Mips :: fixup_Mips_TLSLDM ; break ; case MCSymbolRefExpr :: VK_Mips_DTPREL_HI : FixupKind = Mips :: fixup_Mips_DTPREL_HI ; break ; case MCSymbolRefExpr :: VK_Mips_DTPREL_LO : FixupKind = Mips :: fixup_Mips_DTPREL_LO ; break ; case MCSymbolRefExpr :: VK_Mips_GOTTPREL : FixupKind = Mips :: fixup_Mips_GOTTPREL ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_HI : FixupKind = Mips :: fixup_Mips_TPREL_HI ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_LO : FixupKind = Mips :: fixup_Mips_TPREL_LO ; break ; default : break ; } Fixups . push_back ( MCFixup :: Create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> void ARM64InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


"********** AArch64 Conditional Compares **********\n"

runOnMachineFunction - Emit the function body .


<s>
void
maybe_unlink
(
const
char
*
file
)
{
if
(
debug
)
notice
(
"[Leaving %s]\n"
,
file
)
;
else
unlink_if_ordinary
(
file
)
;
}
</s>

Unlink a temporary file unless requested otherwise .


<s> MVT IA64TargetLowering :: getSetCCResultType ( MVT VT ) const { return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void rs6000_expand_extract_even ( rtx target , rtx op0 , rtx op1 ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) perm . quick_push ( i * 2 ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , perm ) ; } </s>


<s> bool ARMFrameInfo :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void pru_register_pragmas ( void ) { c_register_pragma ( NULL , "ctable_entry" , pru_pragma_ctable_entry ) ; c_register_pragma ( NULL , "CTABLE_ENTRY" , pru_pragma_ctable_entry ) ; c_register_addr_space ( "__regio_symbol" , ADDR_SPACE_REGIO ) ; } </s>


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( N ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == ISD :: ADD && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::ADD ISD::POST_INC ISD::POST_DEC


<s> bool isStackIdSafeForLocalArea ( unsigned StackId ) const override { return StackId != TargetStackID :: SVEVector ; } </s>

This method returns whether or not it is safe for an object with the given stack id to be bundled into the local area .


<s> static rtx expand_set_or_cpymem_constant_prologue ( rtx dst , rtx * srcp , rtx destreg , rtx srcreg , rtx value , rtx vec_value , int desired_align , int align_bytes , bool issetmem ) { rtx src = NULL ; rtx orig_dst = dst ; rtx orig_src = NULL ; int piece_size = 1 ; int copied_bytes = 0 ; if ( ! issetmem ) { gcc_assert ( srcp != NULL ) ; src = * srcp ; orig_src = src ; } for ( piece_size = 1 ; piece_size <= desired_align && copied_bytes < align_bytes ; piece_size <<= 1 ) { if ( align_bytes & piece_size ) { if ( issetmem ) { if ( vec_value && piece_size > GET_MODE_SIZE ( GET_MODE ( value ) ) ) dst = emit_memset ( dst , destreg , vec_value , piece_size ) ; else dst = emit_memset ( dst , destreg , value , piece_size ) ; } else dst = emit_memmov ( dst , & src , destreg , srcreg , piece_size ) ; copied_bytes += piece_size ; } } if ( MEM_ALIGN ( dst ) < ( unsigned int ) desired_align * BITS_PER_UNIT ) set_mem_align ( dst , desired_align * BITS_PER_UNIT ) ; if ( MEM_SIZE_KNOWN_P ( orig_dst ) ) set_mem_size ( dst , MEM_SIZE ( orig_dst ) - align_bytes ) ; if ( ! issetmem ) { int src_align_bytes = get_mem_align_offset ( src , desired_align * BITS_PER_UNIT ) ; if ( src_align_bytes >= 0 ) src_align_bytes = desired_align - src_align_bytes ; if ( src_align_bytes >= 0 ) { unsigned int src_align ; for ( src_align = desired_align ; src_align >= 2 ; src_align >>= 1 ) { if ( ( src_align_bytes & ( src_align - 1 ) ) == ( align_bytes & ( src_align - 1 ) ) ) break ; } if ( src_align > ( unsigned int ) desired_align ) src_align = desired_align ; if ( MEM_ALIGN ( src ) < src_align * BITS_PER_UNIT ) set_mem_align ( src , src_align * BITS_PER_UNIT ) ; } if ( MEM_SIZE_KNOWN_P ( orig_src ) ) set_mem_size ( src , MEM_SIZE ( orig_src ) - align_bytes ) ; * srcp = src ; } return dst ; } </s>

This function is like the previous one , except here we know how many bytes need to be copied . That allows us to update alignment not only of DST , which is returned , but also of SRC , which is passed as a pointer for that reason .


<s> void ARMTargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s>
static
const
char
*
ia64_invalid_binary_op
(
int
op
ATTRIBUTE_UNUSED
,
const_tree
type1
,
const_tree
type2
)
{
if
(
TYPE_MODE
(
type1
)
==
RFmode
||
TYPE_MODE
(
type2
)
==
RFmode
)
return
N_
(
"invalid operation on %<__fpreg%>"
)
;
return
;
}
</s>

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"Unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
0
"Unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> bool X86PassConfig :: addILPOpts ( ) { if ( X86EarlyIfConv && getX86Subtarget ( ) . hasCMov ( ) ) { addPass ( & EarlyIfConverterID ) ; return true ; } return false ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s>
bool
X86RegisterInfo
::
getRegAllocationHints
(
Register
VirtReg
,
ArrayRef
<
MCPhysReg
>
Order
,
SmallVectorImpl
<
MCPhysReg
>
&
Hints
,
const
MachineFunction
&
MF
,
const
VirtRegMap
*
VRM
,
const
LiveRegMatrix
*
Matrix
)
const
{
const
MachineRegisterInfo
*
MRI
=
&
MF
.
getRegInfo
(
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
->
getRegClass
(
VirtReg
)
;
bool
BaseImplRetVal
=
TargetRegisterInfo
::
getRegAllocationHints
(
VirtReg
,
Order
,
Hints
,
MF
,
VRM
,
Matrix
)
;
if
(
RC
.
getID
(
)
!=
X86
::
TILERegClassID
)
return
BaseImplRetVal
;
ShapeT
VirtShape
=
getTileShape
(
VirtReg
,
const_cast
<
VirtRegMap
*
>
(
VRM
)
,
MRI
)
;
auto
AddHint
=
[
&
]
(
MCPhysReg
PhysReg
)
{
Register
VReg
=
Matrix
->
getOneVReg
(
PhysReg
)
;
if
(
VReg
==
MCRegister
::
NoRegister
)
{
Hints
.
push_back
(
PhysReg
)
;
return
;
}
ShapeT
PhysShape
=
getTileShape
(
VReg
,
const_cast
<
VirtRegMap
*
>
(
VRM
)
,
MRI
)
;
if
(
PhysShape
==
VirtShape
)
Hints
.
push_back
(
PhysReg
)
;
}
;
SmallSet
<
MCPhysReg
,
4
>
CopyHints
;
CopyHints
.
insert
(
Hints
.
begin
(
)
,
Hints
.
end
(
)
)
;
Hints
.
clear
(
)
;
for
(
auto
Hint
:
CopyHints
)
{
if
(
RC
.
contains
(
Hint
)
&&
!
MRI
->
isReserved
(
Hint
)
)
AddHint
(
Hint
)
;
}
for
(
MCPhysReg
PhysReg
:
Order
)
{
if
(
!
CopyHints
.
count
(
PhysReg
)
&&
RC
.
contains
(
PhysReg
)
&&
!
MRI
->
isReserved
(
PhysReg
)
)
AddHint
(
PhysReg
)
;
}
LLVM_DEBUG
(
{
dbgs
(
)
<<
"Hints for virtual register "
<<
format_hex
(
VirtReg
,
8
)
<<
"\n"
;
for
(
auto
Hint
:
Hints
)
{
dbgs
(
)
<<
"tmm"
<<
Hint
<<
","
;
}
dbgs
(
)
<<
"\n"
;
}
</s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> unsigned AArch64TargetLowering :: getVaListSizeInBits ( const DataLayout & DL ) const { if ( Subtarget -> isTargetDarwin ( ) ) return getPointerTy ( DL ) . getSizeInBits ( ) ; return 3 * getPointerTy ( DL ) . getSizeInBits ( ) + 2 * 32 ; } </s>

Returns the size of the platform 's va_list object .


<s>
static
void
mmix_file_start
(
void
)
{
default_file_start
(
)
;
fputs
(
"! mmixal:= 8H LOC Data_Section\n"
,
asm_out_file
)
;
text_section
(
)
;
}
</s>

TARGET_ASM_FILE_START . We just emit a little comment for the time being .


<s> bool PPCLoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; MadeChange |= runOnLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void AArch64RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const AArch64InstrInfo * TII = MF . getSubtarget < AArch64Subtarget > ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( AArch64 :: ADDXri ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , 0 , this , MF ) ) ; unsigned Shifter = AArch64_AM :: getShifterImm ( AArch64_AM :: LSL , 0 ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> void print_operand_address ( FILE * file , rtx x ) { struct mips_address_info addr ; if ( mips_classify_address ( & addr , x , word_mode , true ) ) switch ( addr . type ) { case ADDRESS_REG : print_operand ( file , addr . offset , 0 ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_LO_SUM : print_operand ( file , addr . offset , 'R' ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_CONST_INT : output_addr_const ( file , x ) ; fprintf ( file , "(%s)" , reg_names [ 0 ] ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , x ) ; return ; } gcc_unreachable ( ) ; } </s>

Print the operand address represented by the rtx addr