<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
OS
<<
Mem
.
Base
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_Register
:
OS
<<
"Register<"
<<
Reg
.
RegNum
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool AArch64TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: arm_neon_vld1 : case Intrinsic :: arm_neon_vld2 : case Intrinsic :: arm_neon_vld3 : case Intrinsic :: arm_neon_vld4 : case Intrinsic :: aarch64_neon_vld1x2 : case Intrinsic :: aarch64_neon_vld1x3 : case Intrinsic :: aarch64_neon_vld1x4 : case Intrinsic :: arm_neon_vld2lane : case Intrinsic :: arm_neon_vld3lane : case Intrinsic :: arm_neon_vld4lane : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; uint64_t NumElts = getDataLayout ( ) -> getTypeAllocSize ( I . getType ( ) ) / 8 ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case Intrinsic :: arm_neon_vst1 : case Intrinsic :: arm_neon_vst2 : case Intrinsic :: arm_neon_vst3 : case Intrinsic :: arm_neon_vst4 : case Intrinsic :: aarch64_neon_vst1x2 : case Intrinsic :: aarch64_neon_vst1x3 : case Intrinsic :: aarch64_neon_vst1x4 : case Intrinsic :: arm_neon_vst2lane : case Intrinsic :: arm_neon_vst3lane : case Intrinsic :: arm_neon_vst4lane : { Info . opc = ISD :: INTRINSIC_VOID ; unsigned NumElts = 0 ; for ( unsigned ArgI = 1 , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) / 8 ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , MVT :: i64 , NumElts ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - 1 ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_type_node ) return "U6__booll" ; if ( TARGET_FLOAT128_TYPE ) { if ( type == ieee128_float_type_node ) return "U10__float128" ; if ( type == ibm128_float_type_node ) return "g" ; if ( type == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return ( TARGET_IEEEQUAD ) ? "U10__float128" : "g" ; } if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_ELF && TARGET_LONG_DOUBLE_128 && ! TARGET_IEEEQUAD ) return "g" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


<s> int v9_regcmp_p ( enum rtx_code code ) { return ( code == EQ || code == NE || code == GE || code == LT || code == LE || code == GT ) ; } </s>

Nonzero if CODE , a comparison , is suitable for use in v9 conditional move or branch on register contents instructions .


<s> virtual bool requiresRegisterScavenging ( const MachineFunction & MF ) const LLVM_OVERRIDE { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


"COPY with other register classes is not supported"


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
if
(
RPI
.
IsGPR
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
!
MRI
.
isReserved
(
Reg1
)
)
MBB
.
addLiveIn
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
{
if
(
!
MRI
.
isReserved
(
Reg2
)
)
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
8
,
8
)
)
;
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void AArch64AsmPrinter :: emitStartOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "@feat.00" ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> emitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> emitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = 0 ; if ( M . getModuleFlag ( "cfguard" ) ) { Feat00Flags |= 0x800 ; } if ( M . getModuleFlag ( "ehcontguard" ) ) { Feat00Flags |= 0x4000 ; } OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> emitAssignment ( S , MCConstantExpr :: create ( Feat00Flags , MMI -> getContext ( ) ) ) ; } if ( ! TT . isOSBinFormatELF ( ) ) return ; unsigned Flags = 0 ; if ( const auto * BTE = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "branch-target-enforcement" ) ) ) if ( BTE -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ; if ( const auto * Sign = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "sign-return-address" ) ) ) if ( Sign -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_PAC ; if ( Flags == 0 ) return ; if ( auto * TS = static_cast < AArch64TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) TS -> emitNoteSection ( Flags ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> static bool iq2000_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return ( REGNO_REG_CLASS ( regno ) == GR_REGS ? ( regno & 1 ) == 0 || GET_MODE_SIZE ( mode ) <= 4 : ( regno & 1 ) == 0 || GET_MODE_SIZE ( mode ) == 4 ) ; } </s>


<s> void PPCRegisterInfo :: lowerACCSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; bool IsKilled = MI . getOperand ( 0 ) . isKill ( ) ; bool IsPrimed = PPC :: ACCRCRegClass . contains ( SrcReg ) ; Register Reg = PPC :: VSRp0 + ( SrcReg - ( IsPrimed ? PPC :: ACC0 : PPC :: UACC0 ) ) * 2 ; bool IsLittleEndian = Subtarget . isLittleEndian ( ) ; emitAccSpillRestoreInfo ( MBB , IsPrimed , false ) ; if ( IsPrimed ) BuildMI ( MBB , II , DL , TII . get ( PPC :: XXMFACC ) , SrcReg ) . addReg ( SrcReg ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( PPC :: STXVP ) ) . addReg ( Reg , getKillRegState ( IsKilled ) ) , FrameIndex , IsLittleEndian ? 32 : 0 ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( PPC :: STXVP ) ) . addReg ( Reg + 1 , getKillRegState ( IsKilled ) ) , FrameIndex , IsLittleEndian ? 0 : 32 ) ; if ( IsPrimed && ! IsKilled ) BuildMI ( MBB , II , DL , TII . get ( PPC :: XXMTACC ) , SrcReg ) . addReg ( SrcReg ) ; MBB . erase ( II ) ; } </s>

lowerACCSpilling - Generate the code for spilling the accumulator register .


<s> const char * getSymbol ( ) const { return S ; } </s>

Get the target address and flags for the named symbol .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> SDValue LanaiSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> int ix86_data_alignment ( tree type , int align , bool opt ) { int max_align_compat = MIN ( 256 , MAX_OFILE_ALIGNMENT ) ; int max_align = MIN ( ( unsigned ) ix86_tune_cost -> prefetch_block * 8 , MAX_OFILE_ALIGNMENT ) ; if ( max_align < BITS_PER_WORD ) max_align = BITS_PER_WORD ; switch ( ix86_align_data_type ) { case ix86_align_data_type_abi : opt = false ; break ; case ix86_align_data_type_compat : max_align = BITS_PER_WORD ; break ; case ix86_align_data_type_cacheline : break ; } if ( TARGET_IAMCU ) align = iamcu_alignment ( type , align ) ; if ( opt && AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) { if ( wi :: geu_p ( TYPE_SIZE ( type ) , max_align_compat ) && align < max_align_compat ) align = max_align_compat ; if ( wi :: geu_p ( TYPE_SIZE ( type ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , 128 ) && align < 128 ) return 128 ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a static variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( MCID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( MCID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: Latency ; return Sched :: RegPressure ; } </s>


<s> const AArch64MCExpr * AArch64MCExpr :: Create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) AArch64MCExpr ( Expr , Kind ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> SDValue getMergeValues ( ArrayRef < SDValue > Values ) const { return DAG . getMergeValues ( Values , DL ) ; } </s>


<s> SDValue MipsSETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: SMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Mult , true , true , DAG ) ; case ISD :: UMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Multu , true , true , DAG ) ; case ISD :: MULHS : return lowerMulDiv ( Op , MipsISD :: Mult , false , true , DAG ) ; case ISD :: MULHU : return lowerMulDiv ( Op , MipsISD :: Multu , false , true , DAG ) ; case ISD :: MUL : return lowerMulDiv ( Op , MipsISD :: Mult , true , false , DAG ) ; case ISD :: SDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRem , true , true , DAG ) ; case ISD :: UDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRemU , true , true , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_VOID : return lowerINTRINSIC_VOID ( Op , DAG ) ; case ISD :: EXTRACT_VECTOR_ELT : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case ISD :: BUILD_VECTOR : return lowerBUILD_VECTOR ( Op , DAG ) ; case ISD :: VECTOR_SHUFFLE : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; } return MipsTargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::LOAD ISD::STORE ISD::SMUL_LOHI MipsISD::Mult ISD::UMUL_LOHI MipsISD::Multu ISD::MULHS MipsISD::Mult ISD::MULHU MipsISD::Multu ISD::MUL MipsISD::Mult ISD::SDIVREM MipsISD::DivRem ISD::UDIVREM MipsISD::DivRemU ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_VOID ISD::EXTRACT_VECTOR_ELT ISD::BUILD_VECTOR ISD::VECTOR_SHUFFLE Mips


<s> static inline int mov_insn_alignment_mask ( machine_mode mode , bool consider_sh2a ) { const int mov_insn_sz = mov_insn_size ( mode , consider_sh2a ) ; return mov_insn_sz > 0 ? ( mov_insn_sz - 1 ) : 0 ; } </s>

Determine the alignment mask for a move insn of the specified mode .


<s>
unsigned
char
X86Subtarget
::
ClassifyGlobalReference
(
const
GlobalValue
*
GV
,
const
TargetMachine
&
TM
)
const
{
if
(
GV
->
hasDLLImportLinkage
(
)
)
return
X86II
::
MO_DLLIMPORT
;
bool
isDecl
=
GV
->
hasAvailableExternallyLinkage
(
)
;
if
(
GV
->
isDeclaration
(
)
&&
!
GV
->
isMaterializable
(
)
)
isDecl
=
true
;
if
(
isPICStyleRIPRel
(
)
)
{
if
(
TM
.
getCodeModel
(
)
==
CodeModel
::
Large
)
return
X86II
::
MO_NO_FLAG
;
if
(
isTargetDarwin
(
)
)
{
if
(
GV
->
hasDefaultVisibility
(
)
&&
(
isDecl
||
GV
->
isWeakForLinker
(
)
)
)
return
X86II
::
MO_GOTPCREL
;
}
else
if
(
!
isTargetWin64
(
)
)
{
assert
(
isTargetELF
(
)
&&
"Unknown rip-relative target"
)
;
if
(
!
GV
->
hasLocalLinkage
(
)
&&
GV
->
hasDefaultVisibility
(
)
)
return
X86II
::
MO_GOTPCREL
;
}
return
X86II
::
MO_NO_FLAG
;
}
if
(
isPICStyleGOT
(
)
)
{
if
(
GV
->
hasLocalLinkage
(
)
||
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_GOTOFF
;
return
X86II
::
MO_GOT
;
}
if
(
isPICStyleStubPIC
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_PIC_BASE_OFFSET
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
;
if
(
isDecl
||
GV
->
hasCommonLinkage
(
)
)
{
return
X86II
::
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE
;
}
return
X86II
::
MO_PIC_BASE_OFFSET
;
}
if
(
isPICStyleStubNoDynamic
(
)
)
{
if
(
!
isDecl
&&
!
GV
->
isWeakForLinker
(
)
)
return
X86II
::
MO_NO_FLAG
;
if
(
!
GV
->
hasHiddenVisibility
(
)
)
return
X86II
::
MO_DARWIN_NONLAZY
;
return
X86II
::
MO_NO_FLAG
;
}
return
X86II
::
MO_NO_FLAG
;
}
</s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s>
unsigned
X86InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
X86
::
JMP_1
&&
X86
::
getCondFromBranch
(
*
I
)
==
X86
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , MVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , PPCTargetMachine & TM , CodeGenOpt :: Level OptLevel ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , DL ( getDataLayoutString ( TargetTriple ) ) , IsPPC64 ( TargetTriple . getArch ( ) == Triple :: ppc64 || TargetTriple . getArch ( ) == Triple :: ppc64le ) , OptLevel ( OptLevel ) , TargetABI ( PPC_ABI_UNKNOWN ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( * this ) , TLInfo ( TM ) , TSInfo ( & DL ) { } </s>

This constructor initializes the data members to match that of the specified triple .


"Branch-taken block should post-dominate first candidate"

"Error in code produced by branch coalescing"

runOnMachineFunction - Emit the function body .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( 4 - i - 1 ) * 8 ) ) & 0xff ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : return 32 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static int ix86_mode_needed ( int entity , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_needed ( insn ) ; case AVX_U128 : return ix86_avx_u128_mode_needed ( insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : return ix86_i387_mode_needed ( entity , insn ) ; default : gcc_unreachable ( ) ; } return 0 ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s>
void
DarwinARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; FixCallImmediates = false ; IgnoreZeroFlag = false ; InsertNOPDoublePrecision = false ; FixFSMULD = false ; ReplaceFMULS = false ; PreventRoundChange = false ; FixAllFDIVSQRT = false ; InsertNOPLoad = false ; FlushCacheLineSWAP = false ; InsertNOPsLoadStore = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> Type * getType ( ) const { return Root -> getType ( ) ; } </s>

Overload to return most specific vector type .


"passing %wd to argument %d of %qE, which expects"

Report that LOCATION has a call to FNDECL in which argument ARGNO has the value ACTUAL , whereas the function requires a valid value of enum type ENUMTYPE . ARGNO counts from zero .


<s> bool SystemZInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned LowReg = 0 , HighReg = 0 , StartOffset = - 1U , EndOffset = 0 ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass != & SystemZ :: FP64RegClass ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += 8 ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64mr : SystemZ :: MOV64mrm ) ) ) ; MIB . addReg ( SystemZ :: R15D ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & SystemZ :: FP64RegClass ) { MBB . addLiveIn ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"rs6000_can_change_mode_class, return %s, from = %s, "

Debug version of rs6000_can_change_mode_class .


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo ; } </s>

getRegInfo - Return information about the registers currently in use .


<s>
const
char
*
pa_output_64bit_and
(
rtx
*
operands
)
{
if
(
GET_CODE
(
operands
[
2
]
)
==
CONST_INT
&&
INTVAL
(
operands
[
2
]
)
!=
0
)
{
unsigned
HOST_WIDE_INT
mask
=
INTVAL
(
operands
[
2
]
)
;
int
ls0
,
ls1
,
ms0
,
p
,
len
;
for
(
ls0
=
0
;
ls0
<
HOST_BITS_PER_WIDE_INT
;
ls0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ls0
)
)
==
0
)
break
;
for
(
ls1
=
ls0
;
ls1
<
HOST_BITS_PER_WIDE_INT
;
ls1
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ls1
)
)
!=
0
)
break
;
for
(
ms0
=
ls1
;
ms0
<
HOST_BITS_PER_WIDE_INT
;
ms0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
ms0
)
)
==
0
)
break
;
gcc_assert
(
ms0
==
HOST_BITS_PER_WIDE_INT
)
;
if
(
ls1
==
HOST_BITS_PER_WIDE_INT
)
{
len
=
ls0
;
gcc_assert
(
len
)
;
operands
[
2
]
=
GEN_INT
(
len
)
;
return
"extrd,u %1,63,%2,%0"
;
}
else
{
p
=
63
ls0
;
len
=
ls1
ls0
;
operands
[
2
]
=
GEN_INT
(
p
)
;
operands
[
3
]
=
GEN_INT
(
len
)
;
return
"depdi 0,%2,%3,%0"
;
}
}
else
return
"and %1,%2,%0"
;
}
</s>

Return a string to perform a bitwise-and of operands [ 1 ] with operands [ 2 ] storing the result in operands [ 0 ] .


<s> static void flow_dependent_p_1 ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_referenced_p ( x , * pinsn ) ) * pinsn = NULL_RTX ; } </s>

A helper function for flow_dependent_p called through note_stores .


<s> bool X86TTIImpl :: isLegalMaskedStore ( Type * DataType , int Consecutive ) { return isLegalMaskedLoad ( DataType , Consecutive ) ; } </s>

Return true if the target supports masked store .


<s> static rtx arm_gen_multiple_op ( bool is_load , int * regs , int count , rtx basereg , bool write_back , rtx basemem , HOST_WIDE_INT * offsetp ) { rtx mems [ MAX_LDM_STM_OPS ] ; HOST_WIDE_INT offset = * offsetp ; int i ; gcc_assert ( count <= MAX_LDM_STM_OPS ) ; if ( GET_CODE ( basereg ) == PLUS ) basereg = XEXP ( basereg , 0 ) ; for ( i = 0 ; i < count ; i ++ ) { rtx addr = plus_constant ( Pmode , basereg , i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( basemem , SImode , addr , offset ) ; offset += 4 ; } if ( write_back ) * offsetp = offset ; if ( is_load ) return arm_gen_load_multiple_1 ( count , regs , mems , basereg , write_back ? 4 * count : 0 ) ; else return arm_gen_store_multiple_1 ( count , regs , mems , basereg , write_back ? 4 * count : 0 ) ; } </s>

Generate either a load-multiple or a store-multiple instruction . This function can be used in situations where we can start with a single MEM rtx and adjust its address upwards . COUNT is the number of operations in the instruction , not counting a possible update of the base register . REGS is an array containing the register operands . BASEREG is the base register to be used in addressing the memory operands , which are constructed from BASEMEM . WRITE_BACK specifies whether the generated instruction should include an update of the base register . OFFSETP is used to pass an offset to and from this function ; this offset is not used when constructing the address ( instead BASEMEM should have an appropriate offset in its address ) , it is used only for setting MEM_OFFSET . It is updated only if WRITE_BACK is true .


<s> void AArch64AsmPrinter :: emitStartOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "@feat.00" ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = 0 ; if ( M . getModuleFlag ( "cfguard" ) ) { Feat00Flags |= 0x800 ; } if ( M . getModuleFlag ( "ehcontguard" ) ) { Feat00Flags |= 0x4000 ; } OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> emitAssignment ( S , MCConstantExpr :: create ( Feat00Flags , MMI -> getContext ( ) ) ) ; } if ( ! TT . isOSBinFormatELF ( ) ) return ; unsigned Flags = 0 ; if ( const auto * BTE = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "branch-target-enforcement" ) ) ) if ( BTE -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ; if ( const auto * Sign = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "sign-return-address" ) ) ) if ( Sign -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_PAC ; if ( Flags == 0 ) return ; if ( auto * TS = static_cast < AArch64TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) TS -> emitNoteSection ( Flags ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { EmitDataMappingSymbol ( ) ; MCObjectStreamer :: emitFill ( NumBytes , FillValue , Loc ) ; } </s>

Emit Size bytes worth of the value specified by FillValue .


<s> bool AArch64TargetMachine :: parseMachineFunctionInfo ( const yaml :: MachineFunctionInfo & MFI , PerFunctionMIParsingState & PFS , SMDiagnostic & Error , SMRange & SourceRange ) const { const auto & YamlMFI = reinterpret_cast < const yaml :: AArch64FunctionInfo & > ( MFI ) ; MachineFunction & MF = PFS . MF ; MF . getInfo < AArch64FunctionInfo > ( ) -> initializeBaseYamlFields ( YamlMFI ) ; return false ; } </s>

Parse out the target 's MachineFunctionInfo from the YAML reprsentation .


<s> unsigned ARM64TTI :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , OperandValueKind Opd1Info , OperandValueKind Opd2Info ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool MipsTargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget . hasMips32 ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> void ix86_emit_i387_log1p ( rtx op0 , rtx op1 ) { rtx_code_label * label1 = gen_label_rtx ( ) ; rtx_code_label * label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx res = gen_reg_rtx ( XFmode ) ; rtx cst , cstln2 , cst1 ; rtx_insn * insn ; do_pending_stack_adjust ( ) ; cst = const_double_from_real_value ( REAL_VALUE_ATOF ( "0.29289321881345247561810596348408353" , XFmode ) , XFmode ) ; cstln2 = force_reg ( XFmode , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; cst = force_reg ( XFmode , cst ) ; ix86_expand_branch ( GE , tmp , cst , label1 ) ; predict_jump ( REG_BR_PROB_BASE * 10 / 100 ) ; insn = get_last_insn ( ) ; JUMP_LABEL ( insn ) = label1 ; emit_insn ( gen_fyl2xp1xf3_i387 ( res , op1 , cstln2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; LABEL_NUSES ( label1 ) = 1 ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_PLUS ( XFmode , op1 , cst1 ) ) ) ; emit_insn ( gen_fyl2xxf3_i387 ( res , tmp , cstln2 ) ) ; emit_label ( label2 ) ; LABEL_NUSES ( label2 ) = 1 ; emit_move_insn ( op0 , res ) ; } </s>

Output code to perform a log1p XFmode calculation .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MipsTargetMachine
&
Target
=
static_cast
<
MipsTargetMachine
&
>
(
const_cast
<
TargetMachine
&
>
(
MF
.
getTarget
(
)
)
)
;
JTI
=
Target
.
getJITInfo
(
)
;
II
=
Target
.
getInstrInfo
(
)
;
TD
=
Target
.
getDataLayout
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
nullptr
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
,
Subtarget
->
isLittle
(
)
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
)
emitInstruction
(
*
I
++
,
*
MBB
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
"JITTing function '"
"'\n"


<s> bool hasLowDefLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx ) const override { return false ; } </s>

Compute operand latency of a def of 'Reg ' .


<s> bool LanaiAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << LanaiInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned int call_properties ( const function_instance & ) const OVERRIDE { return CP_WRITE_MEMORY ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC


<s> static int ix86_dirflag_mode_needed ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) { if ( cfun -> machine -> func_type == TYPE_NORMAL ) return X86_DIRFLAG_ANY ; else return TARGET_CLD ? X86_DIRFLAG_ANY : X86_DIRFLAG_RESET ; } if ( recog_memoized ( insn ) < 0 ) return X86_DIRFLAG_ANY ; if ( get_attr_type ( insn ) == TYPE_STR ) { if ( cfun -> machine -> func_type == TYPE_NORMAL ) return TARGET_CLD ? X86_DIRFLAG_RESET : X86_DIRFLAG_ANY ; else return X86_DIRFLAG_RESET ; } return X86_DIRFLAG_ANY ; } </s>

Return needed mode for entity in optimize_mode_switching pass .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; HasPWRPSR = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> SDNode * Cpu0DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < Cpu0FunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ATOMIC_FENCE
:
return
lowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_SWAP
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_LONGJMP
:
return
lowerEH_SJLJ_LONGJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETJMP
:
return
lowerEH_SJLJ_SETJMP
(
Op
,
DAG
)
;
case
ISD
::
EH_SJLJ_SETUP_DISPATCH
:
return
lowerEH_SJLJ_SETUP_DISPATCH
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
lowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
lowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
,
*
this
,
Subtarget
)
;
case
ISD
::
BUILD_VECTOR
:
return
lowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
lowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
lowerVAARG
(
Op
,
DAG
)
;
return
lowerToVVP
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
NumEmitted
++
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
static
void
rs6000_debug_reg_print
(
int
first_regno
,
int
last_regno
,
const
char
*
reg_name
)
{
int
r
,
m
;
for
(
r
=
first_regno
;
r
<=
last_regno
;
++
r
)
{
const
char
*
comma
=
""
;
int
len
;
if
(
first_regno
==
last_regno
)
fprintf
(
stderr
,
"%s:\t"
,
reg_name
)
;
else
fprintf
(
stderr
,
"%s%d:\t"
,
reg_name
,
r
first_regno
)
;
len
=
8
;
for
(
m
=
0
;
m
<
NUM_MACHINE_MODES
;
++
m
)
if
(
rs6000_hard_regno_mode_ok_p
[
m
]
[
r
]
&&
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
if
(
rs6000_hard_regno_nregs
[
m
]
[
r
]
>
1
)
len
+=
fprintf
(
stderr
,
"%s%s/%d"
,
comma
,
GET_MODE_NAME
(
m
)
,
rs6000_hard_regno_nregs
[
m
]
[
r
]
)
;
else
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
GET_MODE_NAME
(
m
)
)
;
comma
=
", "
;
}
if
(
call_used_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"call-used"
)
;
comma
=
", "
;
}
if
(
fixed_regs
[
r
]
)
{
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
len
=
8
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%s%s"
,
comma
,
"fixed"
)
;
comma
=
", "
;
}
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
len
+=
fprintf
(
stderr
,
"%sreg-class = %s"
,
comma
,
reg_class_names
[
(
int
)
rs6000_regno_regclass
[
r
]
]
)
;
comma
=
", "
;
if
(
len
>
70
)
{
fprintf
(
stderr
,
",\n\t"
)
;
comma
=
""
;
}
fprintf
(
stderr
,
"%sregno = %d\n"
,
comma
,
r
)
;
}
}
</s>

Print interesting facts about registers .


<s> static reg_class_t ix86_preferred_output_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) return MAYBE_SSE_CLASS_P ( regclass ) ? ALL_SSE_REGS : NO_REGS ; if ( IS_STACK_MODE ( mode ) ) return FLOAT_CLASS_P ( regclass ) ? regclass : NO_REGS ; return regclass ; } </s>

Discourage putting floating-point values in SSE registers unless SSE math is being used , and likewise for the 387 registers .


<s> rtx mips_subword ( rtx op , int high_p ) { unsigned int byte ; enum machine_mode mode ; mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = DImode ; if ( TARGET_BIG_ENDIAN ? ! high_p : high_p ) byte = UNITS_PER_WORD ; else byte = 0 ; if ( REG_P ( op ) ) { if ( FP_REG_P ( REGNO ( op ) ) ) return gen_rtx_REG ( word_mode , high_p ? REGNO ( op ) + 1 : REGNO ( op ) ) ; if ( ACC_HI_REG_P ( REGNO ( op ) ) ) return gen_rtx_REG ( word_mode , high_p ? REGNO ( op ) : REGNO ( op ) + 1 ) ; } if ( MEM_P ( op ) ) return mips_rewrite_small_data ( adjust_address ( op , word_mode , byte ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ; } </s>

Return one word of double-word value OP , taking into account the fixed endianness of certain registers . HIGH_P is true to select the high part , false to select the low part .


<s> void AArch64TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , SE , UP ) ; if ( L -> getLoopDepth ( ) > 1 ) UP . PartialThreshold *= 2 ; UP . PartialOptSizeThreshold = 0 ; if ( ST -> getProcFamily ( ) == AArch64Subtarget :: Falkor && EnableFalkorHWPFUnrollFix ) getFalkorUnrollingPreferences ( L , SE , UP ) ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } } } if ( ST -> getProcFamily ( ) != AArch64Subtarget :: Others && ! ST -> getSchedModel ( ) . isOutOfOrder ( ) ) { UP . Runtime = true ; UP . Partial = true ; UP . UpperBound = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = 4 ; UP . UnrollAndJam = true ; UP . UnrollAndJamInnerLoopThreshold = 60 ; } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static bool ix86_flags_dependent ( rtx_insn * insn , rtx_insn * dep_insn , enum attr_type insn_type ) { rtx set , set2 ; if ( insn_type != TYPE_SETCC && insn_type != TYPE_ICMOV && insn_type != TYPE_FCMOV && insn_type != TYPE_IBR ) return false ; if ( ( set = single_set ( dep_insn ) ) != 0 ) { set = SET_DEST ( set ) ; set2 = NULL_RTX ; } else if ( GET_CODE ( PATTERN ( dep_insn ) ) == PARALLEL && XVECLEN ( PATTERN ( dep_insn ) , 0 ) == 2 && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) == SET && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 1 ) ) == SET ) { set = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) ; set2 = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) ; } else return false ; if ( ! REG_P ( set ) || REGNO ( set ) != FLAGS_REG ) return false ; if ( ! reg_overlap_mentioned_p ( set , PATTERN ( insn ) ) ) return false ; if ( set2 && reg_overlap_mentioned_p ( set2 , PATTERN ( insn ) ) ) return false ; return true ; } </s>

A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set by DEP_INSN and nothing set by DEP_INSN .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 DynAlloca Expander"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int loongarch_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & generic_arg ) { struct loongarch_arg_info arg ; loongarch_get_arg_info ( & arg , get_cumulative_args ( cum ) , generic_arg . mode , generic_arg . type , generic_arg . named , false ) ; return arg . stack_p ? arg . num_gprs * UNITS_PER_WORD : 0 ; } </s>


<s> bool SparcRegisterInfo :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; if ( REG_P ( addr ) || GET_CODE ( addr ) == SYMBOL_REF ) { * base = addr ; * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && ( REG_P ( XEXP ( addr , 0 ) ) || GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF ) && CONST_INT_P ( XEXP ( addr , 1 ) ) ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return true ; } return false ; } </s>

If MEM is in the form of `` base+offset '' , extract the two parts of address and set to BASE and OFFSET , otherwise return false after clearing BASE and OFFSET .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const RegisterBankInfo * ARMSubtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> bool isLegalMaskedScatter ( Type * DataType ) { return ST -> hasSVE ( ) ; } </s>

Return true if the target supports masked scatter .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".hword" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".word" ) return ParseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".xword" ) return ParseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".tlsdesccall" ) return ParseDirectiveTLSDescCall ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( C ) ) return PPCMaterializeInt ( CI , VT , VT != MVT :: i1 ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: VAARG : return lowerVAARG ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return lowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: EH_DWARF_CFA : return lowerEH_DWARF_CFA ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::VAARG ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::EH_DWARF_CFA ISD::FP_TO_SINT


<s> static void pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style , bool set_cfa ) { struct machine_function * m = cfun -> machine ; rtx insn ; bool add_frame_related_expr = false ; if ( Pmode == SImode ) insn = gen_pro_epilogue_adjust_stack_si_add ( dest , src , offset ) ; else if ( x86_64_immediate_operand ( offset , DImode ) ) insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , offset ) ; else { rtx tmp ; if ( style ) tmp = gen_rtx_REG ( DImode , R11_REG ) ; else { gcc_assert ( src != hard_frame_pointer_rtx && dest != hard_frame_pointer_rtx ) ; tmp = hard_frame_pointer_rtx ; } insn = emit_insn ( gen_rtx_SET ( DImode , tmp , offset ) ) ; if ( style < 0 ) add_frame_related_expr = true ; insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , tmp ) ; } insn = emit_insn ( insn ) ; if ( style >= 0 ) ix86_add_queued_cfa_restore_notes ( insn ) ; if ( set_cfa ) { rtx r ; gcc_assert ( m -> fs . cfa_reg == src ) ; m -> fs . cfa_offset += INTVAL ( offset ) ; m -> fs . cfa_reg = dest ; r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( VOIDmode , dest , r ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , r ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else if ( style < 0 ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( add_frame_related_expr ) { rtx r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( VOIDmode , dest , r ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , r ) ; } } if ( dest == stack_pointer_rtx ) { HOST_WIDE_INT ooffset = m -> fs . sp_offset ; bool valid = m -> fs . sp_valid ; if ( src == hard_frame_pointer_rtx ) { valid = m -> fs . fp_valid ; ooffset = m -> fs . fp_offset ; } else if ( src == crtl -> drap_reg ) { valid = m -> fs . drap_valid ; ooffset = 0 ; } else { gcc_checking_assert ( src == stack_pointer_rtx || offset == const0_rtx ) ; } m -> fs . sp_offset = ooffset - INTVAL ( offset ) ; m -> fs . sp_valid = valid ; } } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"LC3 Assembly Printer"
;
}
</s>


<s> static void aarch64_process_components ( sbitmap components , bool prologue_p ) { rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; unsigned last_regno = SBITMAP_SIZE ( components ) ; unsigned regno = aarch64_get_next_set_bit ( components , R0_REGNUM ) ; rtx_insn * insn = NULL ; while ( regno != last_regno ) { machine_mode mode = GP_REGNUM_P ( regno ) ? DImode : DFmode ; rtx reg = gen_rtx_REG ( mode , regno ) ; HOST_WIDE_INT offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr = plus_constant ( Pmode , ptr_reg , offset ) ; rtx mem = gen_frame_mem ( mode , addr ) ; rtx set = prologue_p ? gen_rtx_SET ( mem , reg ) : gen_rtx_SET ( reg , mem ) ; unsigned regno2 = aarch64_get_next_set_bit ( components , regno + 1 ) ; if ( regno2 == last_regno ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; break ; } HOST_WIDE_INT offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) != GET_MODE_SIZE ( mode ) ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; regno = regno2 ; continue ; } rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( ! frame_pointer_needed ) offset2 += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem ( mode , addr2 ) ; rtx set2 = prologue_p ? gen_rtx_SET ( mem2 , reg2 ) : gen_rtx_SET ( reg2 , mem2 ) ; if ( prologue_p ) insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; else insn = emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) { add_reg_note ( insn , REG_CFA_OFFSET , set ) ; add_reg_note ( insn , REG_CFA_OFFSET , set2 ) ; } else { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg2 ) ; } regno = aarch64_get_next_set_bit ( components , regno2 + 1 ) ; } } </s>

Do the work for aarch64_emit_prologue_components and aarch64_emit_epilogue_components . COMPONENTS is the bitmap of registers to save/restore , PROLOGUE_P indicates whether to emit the prologue sequence for these components or the epilogue sequence . That is , it determines whether we should emit stores or loads and what kind of CFA notes to attach to the insns . Otherwise the logic for the two sequences is very similar .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( "\t.frame\t$" + StringRef ( MipsInstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + "," + Twine ( stackSize ) + ",$" + StringRef ( MipsInstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ; } </s>

Mips Mips "\t.frame\t$" Mips "," ",$" Mips


<s> static rtx sh_allocate_initial_value ( rtx hard_reg ) { if ( REGNO ( hard_reg ) == PR_REG ) { if ( crtl -> is_leaf && ! sh_pr_n_sets ( ) ) return hard_reg ; else return gen_frame_mem ( Pmode , return_address_pointer_rtx ) ; } return NULL_RTX ; } </s>

Return where to allocate pseudo for a given hard register initial value .


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) { if ( TARGET_POWERPC64 ) { if ( size == 8 ) return true ; if ( size == 16 && TARGET_P9_VECTOR && mode != TDmode ) return true ; } if ( TARGET_VSX_SMALL_INTEGER ) { if ( mode == SImode ) return true ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return true ; } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> unsigned SystemZTTIImpl :: getNumberOfRegisters ( bool Vector ) { if ( ! Vector ) return 14 ; if ( ST -> hasVector ( ) ) return 32 ; return 0 ; } </s>


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
false
;
for
(
const
MachineOperand
&
MO
:
Orig
.
operands
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
MO
.
getReg
(
)
==
X86
::
EFLAGS
)
{
ClobbersEFLAGS
=
true
;
break
;
}
}
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
addOperand
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
*
NewMI
=
std
::
prev
(
I
)
;
NewMI
->
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) ) ) if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 1 , FrameIndex ) ) return MI . getOperand ( 0 ) . getReg ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
.
bitcastToAPInt
(
)
.
getZExtValue
(
)
;
if
(
!
getFPImmIsExact
(
)
)
OS
<<
" (inexact)"
;
OS
<<
">"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_BTIHint
:
OS
<<
getBTIHintName
(
)
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
if
(
!
getShiftExtendAmount
(
)
&&
!
hasShiftExtendAmount
(
)
)
break
;
LLVM_FALLTHROUGH
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
" (inexact)"
">"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<register "
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> static inline MemOpKey getEmptyKey ( ) { return MemOpKey ( PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) ) ; } </s>

Empty key : no key should be generated that has no DILocalVariable .


<s> static bool mips_cannot_force_const_mem ( machine_mode mode , rtx x ) { enum mips_symbol_type type ; rtx base , offset ; if ( GET_CODE ( x ) == HIGH ) return true ; if ( ( CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && mips_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( mips_symbolic_constant_p ( base , SYMBOL_CONTEXT_LEA , & type ) ) { if ( mips_use_pcrel_pool_p [ ( int ) type ] ) return false ; if ( SMALL_INT ( offset ) && mips_symbol_insns ( type , MAX_MACHINE_MODE ) > 0 ) return true ; if ( TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p ( type ) ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>

Return true if X can not be forced into a constant pool .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( GET_CODE ( x ) == SYMBOL_REF && ( CONSTANT_POOL_ADDRESS_P ( x ) || SYMBOL_REF_LOCAL_P ( x ) ) ) fputs ( "(GOTOFF)" , asm_out_file ) ; else if ( GET_CODE ( x ) == LABEL_REF ) fputs ( "(GOTOFF)" , asm_out_file ) ; else fputs ( "(GOT)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } if ( arm_vector_mode_supported_p ( GET_MODE ( x ) ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; switch ( GET_MODE ( x ) ) { case V2SImode : size = 4 ; break ; case V4HImode : size = 2 ; break ; case V8QImode : size = 1 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < units ; i ++ ) { rtx elt ; elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> static bool sparc_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return to == HARD_FRAME_POINTER_REGNUM || ! sparc_frame_pointer_required ( ) ; } </s>

The way this is structured , we ca n't eliminate SFP in favor of SP if the frame pointer is required : we want to use the SFP- > HFP elimination in that case . But the test in update_eliminables does n't know we are assuming below that we only do the former elimination .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s> bool ARMBaseInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned TCycles , unsigned TExtra , MachineBasicBlock & FMBB , unsigned FCycles , unsigned FExtra , float Probability , float Confidence ) const { if ( ! TCycles || ! FCycles ) return false ; float UnpredCost = Probability * TCycles + ( 1.0 - Probability ) * FCycles ; UnpredCost += 1.0 ; UnpredCost += ( 1.0 - Confidence ) * Subtarget . getMispredictionPenalty ( ) ; return ( float ) ( TCycles + FCycles + TExtra + FExtra ) < UnpredCost ; } </s>


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { if ( DirectiveID . getString ( ) == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".end" ) { Parser . Lex ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".frame" ) { Parser . EatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".set" ) { return parseDirectiveSet ( ) ; } if ( DirectiveID . getString ( ) == ".fmask" ) { Parser . EatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".mask" ) { Parser . EatToEndOfStatement ( ) ; return false ; } if ( DirectiveID . getString ( ) == ".gpword" ) { Parser . EatToEndOfStatement ( ) ; return false ; } return true ; } </s>


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicCmpXchgIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicCmpXchgInst
*
CI
,
Value
*
AlignedAddr
,
Value
*
CmpVal
,
Value
*
NewVal
,
Value
*
Mask
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
cast
<
PointerType
>
(
AlignedAddr
->
getType
(
)
)
->
getElementType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
IntCmpXchg
=
Intrinsic
::
getDeclaration
(
M
,
Intrinsic
::
ppc_cmpxchg_i128
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
CmpLo
=
Builder
.
CreateTrunc
(
CmpVal
,
Int64Ty
,
"cmp_lo"
)
;
Value
*
CmpHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
CmpVal
,
64
)
,
Int64Ty
,
"cmp_hi"
)
;
Value
*
NewLo
=
Builder
.
CreateTrunc
(
NewVal
,
Int64Ty
,
"new_lo"
)
;
Value
*
NewHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
NewVal
,
64
)
,
Int64Ty
,
"new_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
emitLeadingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
IntCmpXchg
,
{
Addr
,
CmpLo
,
CmpHi
,
NewLo
,
NewHi
}
)
;
emitTrailingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; bool hasAVX2 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX2 ( ) ; uint16_t validDomains = 0 ; if ( domain && lookup ( MI -> getOpcode ( ) , domain ) ) validDomains = 0xe ; else if ( domain && lookupAVX2 ( MI -> getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? 0xe : 0x6 ; return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> bool isLegalNTStore ( Type * DataType , Align Alignment ) { if ( isa < VectorType > ( DataType ) ) { unsigned NumElements = DataType -> getVectorNumElements ( ) ; unsigned EltSize = DataType -> getVectorElementType ( ) -> getScalarSizeInBits ( ) ; return NumElements > 1 && isPowerOf2_64 ( NumElements ) && EltSize >= 8 && EltSize <= 128 && isPowerOf2_64 ( EltSize ) ; } return BaseT :: isLegalNTStore ( DataType , Alignment ) ; } </s>

Return true if the target supports nontemporal store .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static int pru_function_arg_regi ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; size_t argsize = pru_function_arg_size ( mode , type ) ; size_t i , bi ; int regi = - 1 ; if ( ! pru_arg_in_reg_bysize ( argsize ) ) return - 1 ; if ( ! named ) return - 1 ; for ( i = 0 ; regi < 0 && i < ARRAY_SIZE ( cum -> regs_used ) ; i ++ ) { gcc_assert ( argsize == 1 || argsize == 2 || argsize == 3 || argsize == 4 || argsize == 8 ) ; if ( ( argsize >= 4 ) && ( i % 4 ) != 0 ) continue ; if ( argsize == 3 && ( i % 4 ) != 0 ) continue ; if ( argsize == 2 && ( i % 4 ) == 3 ) continue ; for ( bi = 0 ; bi < argsize && ( bi + i ) < ARRAY_SIZE ( cum -> regs_used ) ; bi ++ ) { if ( cum -> regs_used [ bi + i ] ) break ; } if ( bi == argsize ) regi = FIRST_ARG_REGNUM + i ; } return regi ; } </s>

Helper function to get the starting storage HW register for an argument , or -1 if it must be passed on stack . The cum_v state is not changed .


<s>
unsigned
ARM64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM64
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool ARMBaseInstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; if ( MF . getInfo < ARMFunctionInfo > ( ) -> isThumb1OnlyFunction ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> const MCExpr * MipsTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; return MipsMCExpr :: create ( MipsMCExpr :: MEK_DTPREL , Expr , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
bool
isAligned
=
(
RI
.
getStackAlignment
(
)
>=
16
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
TM
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void real_line_pos ( int diagpos , int * real_line , int * real_pos ) { * real_line = line - lastline ; * real_pos = diagpos ; for ( int i = 0 ; i < MAXLINES ; i ++ ) { int len = strlen ( lines [ i ] ) ; if ( * real_pos <= len ) break ; ( * real_line ) ++ ; * real_pos -= len - 2 ; } ( * real_pos ) ++ ; } </s>

From a possibly extended line with a virtual position , calculate the current line and character position .


<s> static void mips_promote_ready ( rtx_insn * * ready , int lower , int higher ) { rtx_insn * new_head ; int i ; new_head = ready [ lower ] ; for ( i = lower ; i < higher ; i ++ ) ready [ i ] = ready [ i + 1 ] ; ready [ i ] = new_head ; } </s>

Remove the instruction at index LOWER from ready queue READY and reinsert it in front of the instruction at index HIGHER . LOWER must be < = HIGHER .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( TM . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( TFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( PPC :: X2 ) ; else Reserved . reset ( PPC :: R2 ) ; } } if ( TFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"\nrs6000_address_cost, return = %d, speed = %s, x:\n"

Debug form of ADDRESS_COST that is selected if -mdebug=cost .


<s>
void
X86AvoidSFBPass
::
buildCopy
(
MachineInstr
*
LoadInst
,
unsigned
NLoadOpcode
,
int64_t
LoadDisp
,
MachineInstr
*
StoreInst
,
unsigned
NStoreOpcode
,
int64_t
StoreDisp
,
unsigned
Size
,
int64_t
LMMOffset
,
int64_t
SMMOffset
)
{
MachineOperand
&
LoadBase
=
getBaseOperand
(
LoadInst
)
;
MachineOperand
&
StoreBase
=
getBaseOperand
(
StoreInst
)
;
MachineBasicBlock
*
MBB
=
LoadInst
->
getParent
(
)
;
MachineMemOperand
*
LMMO
=
*
LoadInst
->
memoperands_begin
(
)
;
MachineMemOperand
*
SMMO
=
*
StoreInst
->
memoperands_begin
(
)
;
unsigned
Reg1
=
MRI
->
createVirtualRegister
(
TII
->
getRegClass
(
TII
->
get
(
NLoadOpcode
)
,
0
,
TRI
,
*
(
MBB
->
getParent
(
)
)
)
)
;
MachineInstr
*
NewLoad
=
BuildMI
(
*
MBB
,
LoadInst
,
LoadInst
->
getDebugLoc
(
)
,
TII
->
get
(
NLoadOpcode
)
,
Reg1
)
.
add
(
LoadBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
LoadDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
LMMO
,
LMMOffset
,
Size
)
)
;
if
(
LoadBase
.
isReg
(
)
)
getBaseOperand
(
NewLoad
)
.
setIsKill
(
false
)
;
LLVM_DEBUG
(
NewLoad
->
dump
(
)
)
;
MachineInstr
*
StInst
=
StoreInst
;
if
(
StoreInst
->
getPrevNode
(
)
==
LoadInst
)
StInst
=
LoadInst
;
MachineInstr
*
NewStore
=
BuildMI
(
*
MBB
,
StInst
,
StInst
->
getDebugLoc
(
)
,
TII
->
get
(
NStoreOpcode
)
)
.
add
(
StoreBase
)
.
addImm
(
1
)
.
addReg
(
X86
::
NoRegister
)
.
addImm
(
StoreDisp
)
.
addReg
(
X86
::
NoRegister
)
.
addReg
(
Reg1
)
.
addMemOperand
(
MBB
->
getParent
(
)
->
getMachineMemOperand
(
SMMO
,
SMMOffset
,
Size
)
)
;
if
(
StoreBase
.
isReg
(
)
)
getBaseOperand
(
NewStore
)
.
setIsKill
(
false
)
;
MachineOperand
&
StoreSrcVReg
=
StoreInst
->
getOperand
(
X86
::
AddrNumOperands
)
;
assert
(
StoreSrcVReg
.
isReg
(
)
&&
"Expected virtual register"
)
;
NewStore
->
getOperand
(
X86
::
AddrNumOperands
)
.
setIsKill
(
StoreSrcVReg
.
isKill
(
)
)
;
LLVM_DEBUG
(
NewStore
->
dump
(
)
)
;
}
</s>


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
MI
.
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s>
void
ix86_file_end
(
void
)
{
rtx
xops
[
2
]
;
int
regno
;
for
(
regno
=
0
;
regno
<
8
;
++
regno
)
{
char
name
[
32
]
;
if
(
!
(
(
pic_labels_used
>>
regno
)
&
1
)
)
continue
;
get_pc_thunk_name
(
name
,
regno
)
;
if
(
USE_HIDDEN_LINKONCE
)
{
tree
decl
;
decl
=
build_decl
(
FUNCTION_DECL
,
get_identifier
(
name
)
,
error_mark_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
DECL_ONE_ONLY
(
decl
)
=
1
;
(
*
targetm
.
asm_out
.
unique_section
)
(
decl
,
0
)
;
named_section
(
decl
,
,
0
)
;
(
*
targetm
.
asm_out
.
globalize_label
)
(
asm_out_file
,
name
)
;
fputs
(
"\t.hidden\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_DECLARE_FUNCTION_NAME
(
asm_out_file
,
name
,
decl
)
;
}
else
{
text_section
(
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
}
xops
[
0
]
=
gen_rtx_REG
(
SImode
,
regno
)
;
xops
[
1
]
=
gen_rtx_MEM
(
SImode
,
stack_pointer_rtx
)
;
output_asm_insn
(
"mov{l}\t{%1, %0|%0, %1}"
,
xops
)
;
output_asm_insn
(
"ret"
,
xops
)
;
}
if
(
NEED_INDICATE_EXEC_STACK
)
file_end_indicate_exec_stack
(
)
;
}
</s>

This function generates code for -fpic that loads % ebx with the return address of the caller and then returns .


<s> static bool mips_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return mips_hard_regno_mode_ok_p [ mode ] [ regno ] ; } </s>


<s> bool isCheapToSpeculateCttz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_KNM : case PROCESSOR_INTEL : case PROCESSOR_K6 : case PROCESSOR_BTVER2 : case PROCESSOR_PENTIUM4 : case PROCESSOR_NOCONA : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_BTVER1 : return 3 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_ZNVER2 : case PROCESSOR_ZNVER3 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_TREMONT : case PROCESSOR_ALDERLAKE : case PROCESSOR_GENERIC : return 4 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s> unsigned TOYInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case TOY :: LOADrr : if ( MI -> getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void vr4130_align_insns ( void ) { struct mips_sim state ; rtx_insn * insn , * subinsn , * last , * last2 , * next ; bool aligned_p ; dfa_start ( ) ; last = 0 ; last2 = 0 ; aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; length = get_attr_length ( insn ) ; if ( length > 0 && USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn ) ; length = get_attr_length ( insn ) ; if ( length > 0 ) { if ( NONJUMP_INSN_P ( SEQ_BEGIN ( insn ) ) && ( recog_memoized ( insn ) < 0 || length >= 8 ) ) { next = emit_insn_after ( gen_align ( GEN_INT ( 3 ) ) , insn ) ; next = NEXT_INSN ( next ) ; mips_sim_next_cycle ( & state ) ; aligned_p = true ; } else if ( length & 4 ) aligned_p = ! aligned_p ; last2 = last ; last = insn ; } if ( LABEL_P ( insn ) && label_to_alignment ( insn ) . levels [ 0 ] . log >= 3 ) aligned_p = true ; } dfa_finish ( ) ; } </s>

Implement -mvr4130-align . Go through each basic block and simulate the processor pipeline . If we find that a pair of instructions could execute in parallel , and the first of those instruction is not 8-byte aligned , insert a nop to make it aligned .


<s> static machine_mode ix86_split_reduction ( machine_mode mode ) { switch ( mode ) { case E_V8DImode : case E_V4DImode : return V2DImode ; case E_V16SImode : case E_V8SImode : return V4SImode ; case E_V32HImode : case E_V16HImode : return V8HImode ; case E_V64QImode : case E_V32QImode : return V16QImode ; case E_V16SFmode : case E_V8SFmode : return V4SFmode ; case E_V8DFmode : case E_V4DFmode : return V2DFmode ; default : return mode ; } } </s>

All CPUs prefer to avoid cross-lane operations so perform reductions upper against lower halves up to SSE reg size .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static bool aarch64_evpc_sel ( struct expand_vec_perm_d * d ) { machine_mode vmode = d -> vmode ; int unit_size = GET_MODE_UNIT_SIZE ( vmode ) ; if ( d -> vec_flags != VEC_SVE_DATA || unit_size > 8 ) return false ; int n_patterns = d -> perm . encoding ( ) . npatterns ( ) ; poly_int64 vec_len = d -> perm . length ( ) ; for ( int i = 0 ; i < n_patterns ; ++ i ) if ( ! known_eq ( d -> perm [ i ] , i ) && ! known_eq ( d -> perm [ i ] , vec_len + i ) ) return false ; for ( int i = n_patterns ; i < n_patterns * 2 ; i ++ ) if ( ! d -> perm . series_p ( i , n_patterns , i , n_patterns ) && ! d -> perm . series_p ( i , n_patterns , vec_len + i , n_patterns ) ) return false ; if ( d -> testing_p ) return true ; machine_mode pred_mode = aarch64_sve_pred_mode ( vmode ) ; rtx_vector_builder builder ( pred_mode , n_patterns , 2 ) ; for ( int i = 0 ; i < n_patterns * 2 ; i ++ ) { rtx elem = known_eq ( d -> perm [ i ] , i ) ? CONST1_RTX ( BImode ) : CONST0_RTX ( BImode ) ; builder . quick_push ( elem ) ; } rtx const_vec = builder . build ( ) ; rtx pred = force_reg ( pred_mode , const_vec ) ; emit_insn ( gen_vcond_mask ( vmode , vmode , d -> target , d -> op0 , d -> op1 , pred ) ) ; return true ; } </s>

Try to implement D using SVE SEL instruction .


<s> rtx pure_scalable_type_info :: get_rtx ( machine_mode mode , unsigned int first_zr , unsigned int first_pr ) const { if ( mode == pieces [ 0 ] . mode ) { gcc_assert ( pieces . length ( ) == 1 ) ; return pieces [ 0 ] . get_rtx ( first_zr , first_pr ) ; } rtvec rtxes = rtvec_alloc ( pieces . length ( ) ) ; for ( unsigned int i = 0 ; i < pieces . length ( ) ; ++ i ) { rtx reg = pieces [ i ] . get_rtx ( first_zr , first_pr ) ; rtx offset = gen_int_mode ( pieces [ i ] . offset , Pmode ) ; RTVEC_ELT ( rtxes , i ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , offset ) ; first_zr += pieces [ i ] . num_zr ; first_pr += pieces [ i ] . num_pr ; } return gen_rtx_PARALLEL ( mode , rtxes ) ; } </s>

Return the location of a PST that is known to be passed or returned in registers . FIRST_ZR is the first unused vector argument register and FIRST_PR is the first unused predicate argument register .


"%<-mcall-ms2sysv-xlogues%> is not compatible with %s"

Emits a warning for unsupported msabi to sysv pro/epilogues .


<s> machine_mode aarch64_hard_regno_caller_save_mode ( unsigned regno , unsigned nregs , machine_mode mode ) { if ( nregs == 1 && GET_MODE_SIZE ( mode ) <= 16 ) { if ( GET_MODE_SIZE ( mode ) >= 4 ) return mode ; else return SImode ; } else return choose_hard_reg_mode ( regno , nregs , false ) ; } </s>


<s> static rtx ia64_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; machine_mode hfa_mode ; int unsignedp ; const_tree func = fn_decl_or_type ; if ( fn_decl_or_type && ! DECL_P ( fn_decl_or_type ) ) func = NULL ; mode = TYPE_MODE ( valtype ) ; hfa_mode = hfa_element_mode ( valtype , 0 ) ; if ( hfa_mode != VOIDmode ) { rtx loc [ 8 ] ; int i ; int hfa_size ; int byte_size ; int offset ; hfa_size = GET_MODE_SIZE ( hfa_mode ) ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( valtype ) : GET_MODE_SIZE ( mode ) ) ; offset = 0 ; for ( i = 0 ; offset < byte_size ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( hfa_mode , FR_ARG_FIRST + i ) , GEN_INT ( offset ) ) ; offset += hfa_size ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } else if ( FLOAT_TYPE_P ( valtype ) && mode != TFmode && mode != TCmode ) return gen_rtx_REG ( mode , FR_ARG_FIRST ) ; else { bool need_parallel = false ; if ( BYTES_BIG_ENDIAN && ( mode == BLKmode || ( valtype && AGGREGATE_TYPE_P ( valtype ) ) ) ) need_parallel = true ; else if ( mode == XFmode || mode == XCmode || mode == RFmode ) need_parallel = true ; if ( need_parallel ) { rtx loc [ 8 ] ; int offset ; int bytesize ; int i ; offset = 0 ; bytesize = int_size_in_bytes ( valtype ) ; if ( bytesize == 0 ) return gen_rtx_REG ( mode , GR_RET_FIRST ) ; for ( i = 0 ; offset < bytesize ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , GR_RET_FIRST + i ) , GEN_INT ( offset ) ) ; offset += UNITS_PER_WORD ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } mode = promote_function_mode ( valtype , mode , & unsignedp , func ? TREE_TYPE ( func ) : NULL_TREE , true ) ; return gen_rtx_REG ( mode , GR_RET_FIRST ) ; } } </s>

Return rtx for register that holds the function return value .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> std :: unique_ptr < CSEConfigBase > ARMPassConfig :: getCSEConfig ( ) const { return getStandardCSEConfigForOpt ( TM -> getOptLevel ( ) ) ; } </s>

Returns the CSEConfig object to use for the current optimization level .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::READCYCLECOUNTER


<s>
const
char
*
aarch64_output_probe_sve_stack_clash
(
rtx
base
,
rtx
adjustment
,
rtx
min_probe_threshold
,
rtx
guard_size
)
{
gcc_assert
(
flag_stack_clash_protection
)
;
gcc_assert
(
CONST_INT_P
(
min_probe_threshold
)
&&
CONST_INT_P
(
guard_size
)
)
;
gcc_assert
(
INTVAL
(
guard_size
)
>
INTVAL
(
min_probe_threshold
)
)
;
HOST_WIDE_INT
residual_probe_guard
=
INTVAL
(
min_probe_threshold
)
;
residual_probe_guard
=
aarch64_clamp_to_uimm12_shift
(
residual_probe_guard
)
;
rtx
probe_offset_value_rtx
=
gen_int_mode
(
residual_probe_guard
,
Pmode
)
;
gcc_assert
(
INTVAL
(
min_probe_threshold
)
>=
residual_probe_guard
)
;
gcc_assert
(
aarch64_uimm12_shift
(
residual_probe_guard
)
)
;
static
int
labelno
=
0
;
char
loop_start_lab
[
32
]
;
char
loop_end_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_start_lab
,
"SVLPSPL"
,
labelno
)
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_end_lab
,
"SVLPEND"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_start_lab
)
;
xops
[
0
]
=
adjustment
;
xops
[
1
]
=
probe_offset_value_rtx
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tb.lt\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_end_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
0
]
=
base
;
xops
[
1
]
=
probe_offset_value_rtx
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
xops
[
1
]
=
const0_rtx
;
output_asm_insn
(
"str\txzr, [%0, %1]"
,
xops
)
;
xops
[
0
]
=
adjustment
;
xops
[
1
]
=
probe_offset_value_rtx
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
fputs
(
"\tb\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_start_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_end_lab
)
;
xops
[
0
]
=
base
;
xops
[
1
]
=
adjustment
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
return
""
;
}
</s>

Emit the probe loop for doing stack clash probes and stack adjustments for SVE . This emits probes from BASE to BASE - ADJUSTMENT based on a guard size of GUARD_SIZE . When a probe is emitted it is done at most MIN_PROBE_THRESHOLD bytes from the current BASE at an interval of at most MIN_PROBE_THRESHOLD . By the end of this function BASE = BASE - ADJUSTMENT .


<s> void aarch64_expand_call ( rtx result , rtx mem , rtx callee_abi , bool sibcall ) { rtx call , callee , tmp ; rtvec vec ; machine_mode mode ; gcc_assert ( MEM_P ( mem ) ) ; callee = XEXP ( mem , 0 ) ; mode = GET_MODE ( callee ) ; gcc_assert ( mode == Pmode ) ; if ( SYMBOL_REF_P ( callee ) ? ( aarch64_is_long_call_p ( callee ) || aarch64_is_noplt_call_p ( callee ) ) : ! REG_P ( callee ) ) XEXP ( mem , 0 ) = force_reg ( mode , callee ) ; call = gen_rtx_CALL ( VOIDmode , mem , const0_rtx ) ; if ( result != NULL_RTX ) call = gen_rtx_SET ( result , call ) ; if ( sibcall ) tmp = ret_rtx ; else tmp = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; gcc_assert ( CONST_INT_P ( callee_abi ) ) ; callee_abi = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 1 , callee_abi ) , UNSPEC_CALLEE_ABI ) ; vec = gen_rtvec ( 3 , call , callee_abi , tmp ) ; call = gen_rtx_PARALLEL ( VOIDmode , vec ) ; aarch64_emit_call_insn ( call ) ; } </s>

This function is used by the call expanders of the machine description . RESULT is the register in which the result is returned . It 's NULL for `` call '' and `` sibcall '' . MEM is the location of the function call . SIBCALL indicates whether this function call is normal call or sibling call . It will generate different pattern accordingly .


<s> void ix86_emit_i387_atanh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx half = const_double_from_real_value ( dconsthalf , XFmode ) ; rtx cst1 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , op1 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e1 , e2 , cst1 ) ) ; emit_insn ( gen_addxf3 ( e2 , e2 , e2 ) ) ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_insn ( gen_divxf3 ( e1 , e2 , e1 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; half = force_reg ( XFmode , half ) ; emit_insn ( gen_mulxf3 ( op0 , e2 , half ) ) ; } </s>

Output code to perform an atanh XFmode calculation .