<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLD1q64Pseudo : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
unsigned
ARMBaseInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
getLastNonDebugInstr
(
)
;
if
(
I
==
MBB
.
end
(
)
)
return
0
;
if
(
!
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> static int rs6000_issue_rate ( ) { switch ( rs6000_cpu_attr ) { case CPU_RIOS1 : case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : return 2 ; case CPU_RIOS2 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & ARM :: CCRRegClass ) return 0 ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> static void mips_macc_chains_record ( rtx_insn * insn ) { if ( get_attr_may_clobber_hilo ( insn ) ) mips_macc_chains_last_hilo = insn ; } </s>

A TUNE_MACC_CHAINS helper function . Record that instruction INSN has been scheduled , updating mips_macc_chains_last_hilo appropriately .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool PPCInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case PPC :: EXTSW : case PPC :: EXTSW_32_64 : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = PPC :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s>
unsigned
IA64RegisterInfo
::
getRARegister
(
)
const
{
assert
(
0
&&
"What is the return address register"
)
;
return
0
;
}
</s>

This method should return the register where the return address can be found .


<s> static void do_isel ( rtx dest , rtx cmp , rtx src_t , rtx src_f , rtx cr ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_isel_signed_di ( dest , cmp , src_t , src_f , cr ) ) ; else emit_insn ( gen_isel_signed_si ( dest , cmp , src_t , src_f , cr ) ) ; } </s>

Emit an isel of the proper mode for DEST . DEST is the isel destination register . SRC1 is the isel source if CR is true . SRC2 is the isel source if CR is false . CR is the condition for the isel .


<s> void ARM64_ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> unsigned MipsTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) return std :: max ( ( ( unsigned ) VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? 32 : 64 ) ) , 1U ) ; return MipsTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> const OR1KInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> static bool insn_uses_reg_p ( rtx_insn * insn , unsigned int reg ) { extract_insn ( insn ) ; return ( ( REG_P ( recog_data . operand [ 1 ] ) && REGNO ( recog_data . operand [ 1 ] ) == reg ) || ( recog_data . n_operands == 3 && REG_P ( recog_data . operand [ 2 ] ) && REGNO ( recog_data . operand [ 2 ] ) == reg ) ) ; } </s>

True if any of INSN 's source register ( s ) is REG .


<s>
Sparc
::
Fixups
SparcMCExpr
::
getFixupKind
(
SparcMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
assert
(
0
&&
"Unhandled SparcMCExpr::VariantKind"
)
;
case
VK_Sparc_LO
:
return
Sparc
::
fixup_sparc_lo10
;
case
VK_Sparc_HI
:
return
Sparc
::
fixup_sparc_hi22
;
case
VK_Sparc_H44
:
return
Sparc
::
fixup_sparc_h44
;
case
VK_Sparc_M44
:
return
Sparc
::
fixup_sparc_m44
;
case
VK_Sparc_L44
:
return
Sparc
::
fixup_sparc_l44
;
case
VK_Sparc_HH
:
return
Sparc
::
fixup_sparc_hh
;
case
VK_Sparc_HM
:
return
Sparc
::
fixup_sparc_hm
;
case
VK_Sparc_PC22
:
return
Sparc
::
fixup_sparc_pc22
;
case
VK_Sparc_PC10
:
return
Sparc
::
fixup_sparc_pc10
;
case
VK_Sparc_GOT22
:
return
Sparc
::
fixup_sparc_got22
;
case
VK_Sparc_GOT10
:
return
Sparc
::
fixup_sparc_got10
;
case
VK_Sparc_WPLT30
:
return
Sparc
::
fixup_sparc_wplt30
;
case
VK_Sparc_TLS_GD_HI22
:
return
Sparc
::
fixup_sparc_tls_gd_hi22
;
case
VK_Sparc_TLS_GD_LO10
:
return
Sparc
::
fixup_sparc_tls_gd_lo10
;
case
VK_Sparc_TLS_GD_ADD
:
return
Sparc
::
fixup_sparc_tls_gd_add
;
case
VK_Sparc_TLS_GD_CALL
:
return
Sparc
::
fixup_sparc_tls_gd_call
;
case
VK_Sparc_TLS_LDM_HI22
:
return
Sparc
::
fixup_sparc_tls_ldm_hi22
;
case
VK_Sparc_TLS_LDM_LO10
:
return
Sparc
::
fixup_sparc_tls_ldm_lo10
;
case
VK_Sparc_TLS_LDM_ADD
:
return
Sparc
::
fixup_sparc_tls_ldm_add
;
case
VK_Sparc_TLS_LDM_CALL
:
return
Sparc
::
fixup_sparc_tls_ldm_call
;
case
VK_Sparc_TLS_LDO_HIX22
:
return
Sparc
::
fixup_sparc_tls_ldo_hix22
;
case
VK_Sparc_TLS_LDO_LOX10
:
return
Sparc
::
fixup_sparc_tls_ldo_lox10
;
case
VK_Sparc_TLS_LDO_ADD
:
return
Sparc
::
fixup_sparc_tls_ldo_add
;
case
VK_Sparc_TLS_IE_HI22
:
return
Sparc
::
fixup_sparc_tls_ie_hi22
;
case
VK_Sparc_TLS_IE_LO10
:
return
Sparc
::
fixup_sparc_tls_ie_lo10
;
case
VK_Sparc_TLS_IE_LD
:
return
Sparc
::
fixup_sparc_tls_ie_ld
;
case
VK_Sparc_TLS_IE_LDX
:
return
Sparc
::
fixup_sparc_tls_ie_ldx
;
case
VK_Sparc_TLS_IE_ADD
:
return
Sparc
::
fixup_sparc_tls_ie_add
;
case
VK_Sparc_TLS_LE_HIX22
:
return
Sparc
::
fixup_sparc_tls_le_hix22
;
case
VK_Sparc_TLS_LE_LOX10
:
return
Sparc
::
fixup_sparc_tls_le_lox10
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> MCELFStreamer & VETargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const bool Uses64BitStackPtr = STI . isTarget64BitLP64 ( ) || STI . isTargetNaCl64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Uses64BitStackPtr , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( Uses64BitStackPtr , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( Uses64BitStackPtr , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
bool
ARMBaseInstrInfo
::
getInsertSubregLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
RegSubRegPair
&
BaseReg
,
RegSubRegPairAndIdx
&
InsertedReg
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isInsertSubregLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VSETLNi32
:
const
MachineOperand
&
MOBaseReg
=
MI
.
getOperand
(
1
)
;
const
MachineOperand
&
MOInsertedReg
=
MI
.
getOperand
(
2
)
;
if
(
MOInsertedReg
.
isUndef
(
)
)
return
false
;
const
MachineOperand
&
MOIndex
=
MI
.
getOperand
(
3
)
;
BaseReg
.
Reg
=
MOBaseReg
.
getReg
(
)
;
BaseReg
.
SubReg
=
MOBaseReg
.
getSubReg
(
)
;
InsertedReg
.
Reg
=
MOInsertedReg
.
getReg
(
)
;
InsertedReg
.
SubReg
=
MOInsertedReg
.
getSubReg
(
)
;
InsertedReg
.
SubIdx
=
MOIndex
.
getImm
(
)
==
0
ARM
::
ssub_0
:
ARM
::
ssub_1
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getInsertSubregInputs .


<s>
void
mmix_override_options
(
)
{
if
(
flag_pic
)
{
warning
(
"-f%s not supported: ignored"
,
(
flag_pic
>
1
)
"PIC"
:
"pic"
)
;
flag_pic
=
0
;
}
ggc_add_rtx_root
(
&
mmix_compare_op0
,
1
)
;
ggc_add_rtx_root
(
&
mmix_compare_op1
,
1
)
;
}
</s>


<s> static unsigned int find_drap_reg ( void ) { tree decl = cfun -> decl ; if ( TARGET_64BIT ) { if ( DECL_STATIC_CHAIN ( decl ) || crtl -> tail_call_emit ) return R13_REG ; return R10_REG ; } else { if ( DECL_STATIC_CHAIN ( decl ) || crtl -> tail_call_emit ) return DI_REG ; if ( ix86_function_regparm ( TREE_TYPE ( decl ) , decl ) <= 2 ) { unsigned int ccvt = ix86_get_callcvt ( TREE_TYPE ( decl ) ) ; if ( ( ccvt & ( IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) == 0 ) return CX_REG ; } return DI_REG ; } } </s>

Find an available register to be used as dynamic realign argument pointer regsiter . Such a register will be written in prologue and used in begin of body , so it must not be 1. parameter passing register . 2 . GOT pointer . We reuse static-chain register if it is available . Otherwise , we use DI for i386 and R13 for x86-64 . We chose R13 since it has shorter encoding . Return : the regno of chosen register .


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } emitA64MappingSymbol ( ) ; MCELFStreamer :: emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( CPU == "geode" ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } const uint64_t OptimalCount = ( Count < 16 ) ? Count : 15 ; const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10 ; for ( uint64_t i = 0 , e = Prefixes ; i != e ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint64_t Rest = OptimalCount - Prefixes ; for ( uint64_t i = 0 , e = Rest ; i != e ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; for ( uint64_t i = OptimalCount , e = Count ; i != e ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> unsigned getNumFixupKinds ( ) const override { return SystemZ :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static bool expand_vec_perm_pblendv ( struct expand_vec_perm_d * d ) { unsigned i , which , nelt = d -> nelt ; struct expand_vec_perm_d dcopy , dcopy1 ; machine_mode vmode = d -> vmode ; bool ok ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( vmode ) == 32 ) ; else if ( TARGET_AVX && ( vmode == V4DFmode || vmode == V8SFmode ) ) ; else if ( TARGET_SSE4_1 && ( GET_MODE_SIZE ( vmode ) == 4 || GET_MODE_SIZE ( vmode ) == 8 || GET_MODE_SIZE ( vmode ) == 16 ) ) ; else return false ; for ( i = 0 , which = 0 ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e != i ) which |= ( e < nelt ? 1 : 2 ) ; } if ( which != 1 && which != 2 ) return false ; if ( d -> testing_p && GET_MODE_SIZE ( vmode ) == 16 ) return true ; dcopy = * d ; if ( which == 2 ) dcopy . op0 = dcopy . op1 = d -> op1 ; else dcopy . op0 = dcopy . op1 = d -> op0 ; if ( ! d -> testing_p ) dcopy . target = gen_reg_rtx ( vmode ) ; dcopy . one_operand_p = true ; for ( i = 0 ; i < nelt ; ++ i ) dcopy . perm [ i ] = d -> perm [ i ] & ( nelt - 1 ) ; ok = expand_vec_perm_1 ( & dcopy ) ; if ( GET_MODE_SIZE ( vmode ) != 16 && ! ok ) return false ; else gcc_assert ( ok ) ; if ( d -> testing_p ) return true ; dcopy1 = * d ; if ( which == 2 ) dcopy1 . op1 = dcopy . target ; else dcopy1 . op0 = dcopy . target ; for ( i = 0 ; i < nelt ; ++ i ) dcopy1 . perm [ i ] = ( ( d -> perm [ i ] >= nelt ) ? ( nelt + i ) : i ) ; ok = expand_vec_perm_blend ( & dcopy1 ) ; gcc_assert ( ok ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_const_1 . Try to simplify the permutation using the SSE4_1 pblendv instruction . Potentially reduces permutation from 2 pshufb and or to 1 pshufb and pblendv .


<s> static bool aarch64_gimple_fold_builtin ( gimple_stmt_iterator * gsi ) { gcall * stmt = as_a < gcall * > ( gsi_stmt ( * gsi ) ) ; tree fndecl = gimple_call_fndecl ( stmt ) ; unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; gimple * new_stmt = NULL ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : new_stmt = aarch64_general_gimple_fold_builtin ( subcode , stmt ) ; break ; case AARCH64_BUILTIN_SVE : new_stmt = aarch64_sve :: gimple_fold_builtin ( subcode , gsi , stmt ) ; break ; } if ( ! new_stmt ) return false ; gsi_replace ( gsi , new_stmt , true ) ; return true ; } </s>


<s> static bool aarch64_needs_frame_chain ( void ) { if ( frame_pointer_needed || crtl -> calls_eh_return ) return true ; bool is_leaf = crtl -> is_leaf && ! df_regs_ever_live_p ( LR_REGNUM ) ; if ( flag_omit_leaf_frame_pointer && is_leaf ) return false ; return aarch64_use_frame_pointer ; } </s>

Determine whether a frame chain needs to be generated .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool AArch64InstrInfo :: isExtendLikelyToBeFolded ( MachineInstr & ExtMI , MachineRegisterInfo & MRI ) const { assert ( ExtMI . getOpcode ( ) == TargetOpcode :: G_SEXT || ExtMI . getOpcode ( ) == TargetOpcode :: G_ZEXT || ExtMI . getOpcode ( ) == TargetOpcode :: G_ANYEXT ) ; if ( ExtMI . getOpcode ( ) == TargetOpcode :: G_ANYEXT ) return true ; Register DefReg = ExtMI . getOperand ( 0 ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( DefReg ) ) return false ; auto * UserMI = & * MRI . use_instr_nodbg_begin ( DefReg ) ; return UserMI -> getOpcode ( ) == TargetOpcode :: G_PTR_ADD ; } </s>

Given the generic extension instruction ExtMI , returns true if this extension is a likely candidate for being folded into an another instruction .


<s> bool PPCInstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { int AltOpc = PPC :: getAltVSXFMAOpcode ( MI -> getOpcode ( ) ) ; if ( AltOpc == - 1 ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 2 , 3 ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> PPCSubtarget :: PPCSubtarget ( const TargetMachine & tm , const Module & M , const std :: string & FS , bool is64Bit ) : TM ( tm ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , DarwinVers ( 0 ) { std :: string CPU = "generic" ; CPU = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( FS , CPU ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; const std :: string & TT = M . getTargetTriple ( ) ; if ( TT . length ( ) > 7 ) { size_t DarwinPos = TT . find ( "-darwin" ) ; if ( DarwinPos != std :: string :: npos ) { if ( isdigit ( TT [ DarwinPos + 7 ] ) ) DarwinVers = atoi ( & TT [ DarwinPos + 7 ] ) ; else DarwinVers = 8 ; } } else if ( TT . empty ( ) ) { DarwinVers = 9 ; DarwinVers = 8 ; } if ( isDarwin ( ) ) { HasLazyResolverStubs = true ; AsmFlavor = NewMnemonic ; } else { AsmFlavor = OldMnemonic ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static inline bool offset_4bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , - 8 , 7 ) ) ; } </s>

Return true if OFFSET is a signed 4-bit value multiplied by the size of MODE .


<s> bool PPCTTIImpl :: isHardwareLoopProfitable ( Loop * L , ScalarEvolution & SE , AssumptionCache & AC , TargetLibraryInfo * LibInfo , HardwareLoopInfo & HWLoopInfo ) { const PPCTargetMachine & TM = ST -> getTargetMachine ( ) ; TargetSchedModel SchedModel ; SchedModel . init ( ST ) ; unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , 32 > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( 6 * SchedModel . getIssueWidth ( ) ) ) return false ; } SmallPtrSet < const Value * , 4 > Visited ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo , Visited ) ) return false ; SmallVector < BasicBlock * , 4 > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = 0 , FalseWeight = 0 ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( 0 ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . isPPC64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , 1 ) ; return true ; } </s>

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> bool MipsAbiFlags :: merge ( const Input & pInput , MipsAbiFlags & oldFlags , const MipsAbiFlags & newFlags ) { if ( oldFlags . m_IsaLevel == 0 ) { oldFlags = newFlags ; return true ; } if ( newFlags . m_IsaLevel > oldFlags . m_IsaLevel ) oldFlags . m_IsaLevel = newFlags . m_IsaLevel ; oldFlags . m_IsaRev = std :: max ( oldFlags . m_IsaRev , newFlags . m_IsaRev ) ; oldFlags . m_GprSize = std :: max ( oldFlags . m_GprSize , newFlags . m_GprSize ) ; oldFlags . m_Cpr1Size = std :: max ( oldFlags . m_Cpr1Size , newFlags . m_Cpr1Size ) ; oldFlags . m_Cpr2Size = std :: max ( oldFlags . m_Cpr2Size , newFlags . m_Cpr2Size ) ; oldFlags . m_Ases |= newFlags . m_Ases ; oldFlags . m_Flags1 |= newFlags . m_Flags1 ; if ( oldFlags . m_FpAbi == newFlags . m_FpAbi ) return true ; if ( isFpGreater ( newFlags . m_FpAbi , oldFlags . m_FpAbi ) ) { oldFlags . m_FpAbi = newFlags . m_FpAbi ; return true ; } if ( isFpGreater ( oldFlags . m_FpAbi , newFlags . m_FpAbi ) ) return true ; llvm :: StringRef oldAbiName = getFpAbiName ( oldFlags . m_FpAbi ) ; llvm :: StringRef newAbiName = getFpAbiName ( newFlags . m_FpAbi ) ; warning ( diag :: warn_Mips_fp_abi_incompatible ) << oldAbiName << newAbiName << pInput . name ( ) ; return false ; } </s>


<s> bool X86IndirectThunks :: doInitialization ( Module & M ) { initTIs ( M , TIs ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ; } </s>

True if the stack can be realigned for the target .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR && MBB . succ_empty ( ) ) { if ( isVarArg ) continue ; if ( STI . hasV4TOps ( ) && ! STI . hasV5TOps ( ) ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; if ( MI != MBB . end ( ) ) MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool ARMSubtarget :: enableMachineScheduler ( ) const { return getSchedModel ( ) . isOutOfOrder ( ) && isSwift ( ) ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : if ( ! selectBinaryOp ( I , ISD :: MUL ) ) return selectMul ( I ) ; return true ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : if ( ! selectCast ( I , ISD :: ZERO_EXTEND ) ) return selectIntExt ( I ) ; return true ; case Instruction :: SExt : if ( ! selectCast ( I , ISD :: SIGN_EXTEND ) ) return selectIntExt ( I ) ; return true ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; ( void ) & CC_AArch64_DarwinPCS_VarArg ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printMemReference ( MI , OpNo , "no-rip" ) ; return false ; } } printMemReference ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> machine_mode mips_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , false ) ; else return mode ; } </s>


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
ExpandVectorExtension
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
ATOMIC_STORE
:
case
ISD
::
ATOMIC_LOAD
:
case
ISD
::
ATOMIC_LOAD_ADD
:
case
ISD
::
ATOMIC_LOAD_AND
:
case
ISD
::
ATOMIC_LOAD_NAND
:
case
ISD
::
ATOMIC_LOAD_OR
:
case
ISD
::
ATOMIC_LOAD_SUB
:
case
ISD
::
ATOMIC_LOAD_XOR
:
case
ISD
::
ATOMIC_SWAP
:
case
ISD
::
ATOMIC_CMP_SWAP
:
case
ISD
::
ATOMIC_LOAD_MIN
:
case
ISD
::
ATOMIC_LOAD_UMIN
:
case
ISD
::
ATOMIC_LOAD_MAX
:
case
ISD
::
ATOMIC_LOAD_UMAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> void sparc_flat_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size - get_stack_check_protect ( ) ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == 0 ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_frame_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7 ) ; } } if ( frame_pointer_needed ) { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the GOT register if needed .


<s> bool X86FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) && ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> MachineBasicBlock :: iterator TOYFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == TOY :: ADJCALLSTACKUP || I -> getOpcode ( ) == TOY :: ADJCALLSTACKDOWN ) { return MBB . erase ( I ) ; } return MBB . end ( ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

TOY TOY TOY::ADJCALLSTACKUP TOY::ADJCALLSTACKDOWN


<s> static void pa_hpux_file_end ( void ) { unsigned int i ; extern_symbol * p ; if ( ! NO_DEFERRED_PROFILE_COUNTERS ) output_deferred_profile_counters ( ) ; output_deferred_plabels ( ) ; for ( i = 0 ; VEC_iterate ( extern_symbol , extern_symbols , i , p ) ; i ++ ) { tree decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , 0 ) ) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ; } VEC_free ( extern_symbol , gc , extern_symbols ) ; } </s>

Output text required at the end of an assembler file . This includes deferred plabels and .import directives for all external symbols that were actually referenced .


<s> virtual const InstrItineraryData getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static int arm_needs_doubleword_align ( machine_mode mode , const_tree type ) { if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; int ret = 0 ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) { if ( TREE_CODE ( field ) == FIELD_DECL ) return 1 ; else ret = - 1 ; } return ret ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


"iwmmxt requires an AAPCS compatible ABI for proper operation"

"iwmmxt abi requires an iwmmxt capable cpu"

"target CPU does not support interworking"

"AAPCS does not support -mcaller-super-interworking"

"AAPCS does not support -mcallee-super-interworking"

"target CPU does not support ARMv8-M Security Extensions"

"ARMv8-M Security Extensions incompatible with selected FPU"

"-mfloat-abi=hard: selected processor lacks an FPU"

Perform some validation between the desired architecture and the rest of the options .


<s> static rtx aarch64_expand_sve_const_pred_trn ( rtx target , rtx_vector_builder & builder , unsigned int elt_size , unsigned int permute_size ) { unsigned int a_elt_size = GET_MODE_SIZE ( DImode ) ; unsigned int b_elt_size = GET_MODE_SIZE ( DImode ) ; for ( unsigned int i = 0 ; i < builder . encoded_nelts ( ) ; i += elt_size ) if ( INTVAL ( builder . elt ( i ) ) != 0 ) { if ( i & permute_size ) b_elt_size |= i - permute_size ; else a_elt_size |= i ; } a_elt_size &= - a_elt_size ; b_elt_size &= - b_elt_size ; rtx_vector_builder a_builder ( VNx16BImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; rtx_vector_builder b_builder ( VNx16BImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; unsigned int nelts = builder . encoded_nelts ( ) ; for ( unsigned int i = 0 ; i < nelts ; ++ i ) if ( i & ( elt_size - 1 ) ) { a_builder . quick_push ( const0_rtx ) ; b_builder . quick_push ( const0_rtx ) ; } else if ( ( i & permute_size ) == 0 ) { a_builder . quick_push ( builder . elt ( i ) ) ; b_builder . quick_push ( builder . elt ( i + permute_size ) ) ; } else { if ( a_elt_size > permute_size ) a_builder . quick_push ( const0_rtx ) ; else a_builder . quick_push ( a_builder . elt ( i - a_elt_size ) ) ; if ( b_elt_size > permute_size ) b_builder . quick_push ( const0_rtx ) ; else b_builder . quick_push ( b_builder . elt ( i - b_elt_size ) ) ; } a_builder . finalize ( ) ; b_builder . finalize ( ) ; rtx_insn * last = get_last_insn ( ) ; rtx a = aarch64_expand_sve_const_pred_1 ( NULL_RTX , a_builder , false ) ; if ( ! a ) return NULL_RTX ; rtx b = a ; if ( a_builder != b_builder ) { b = aarch64_expand_sve_const_pred_1 ( NULL_RTX , b_builder , false ) ; if ( ! b ) { delete_insns_since ( last ) ; return NULL_RTX ; } } machine_mode mode = aarch64_sve_pred_mode ( permute_size ) . require ( ) ; target = aarch64_target_reg ( target , mode ) ; emit_insn ( gen_aarch64_sve ( UNSPEC_TRN1 , mode , target , gen_lowpart ( mode , a ) , gen_lowpart ( mode , b ) ) ) ; return target ; } </s>

BUILDER is a constant predicate in which the index of every set bit is a multiple of ELT_SIZE ( which is < = 8 ) . Try to load the constant using a TRN1 of size PERMUTE_SIZE , which is > = ELT_SIZE . Return the register on success , otherwise return null . Use TARGET as the register if nonnull and convenient .


<s> int direct_return ( ) { if ( reload_completed ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( info -> first_gp_reg_save == 32 && info -> first_fp_reg_save == 64 && info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 && ! info -> lr_save_p && ! info -> cr_save_p && info -> vrsave_mask == 0 && ! info -> push_p ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> bool sh_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( sh_cfun_interrupt_handler_p ( ) && ! df_regs_ever_live_p ( new_reg ) ) return false ; return true ; } </s>

Return nonzero if register old_reg can be renamed to register new_reg .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + 1 , DL , F ) ; LLT Ty = MRI . getType ( VRegs [ Idx ] ) ; unsigned Dst = VRegs [ Idx ] ; bool Split = false ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ Idx ] ) MIRBuilder . buildCopy ( VRegs [ Idx ] , Dst ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> DecodeStatus SystemZDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 0 ; if ( Bytes . size ( ) < 2 ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ 0 ] < 0x40 ) { Size = 2 ; Table = DecoderTable16 ; } else if ( Bytes [ 0 ] < 0xc0 ) { Size = 4 ; Table = DecoderTable32 ; } else { Size = 6 ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) return MCDisassembler :: Fail ; uint64_t Inst = 0 ; for ( uint64_t I = 0 ; I < Size ; ++ I ) Inst = ( Inst << 8 ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> const MCRegister ARMElfTargetObjectFile :: getStaticBase ( ) const { return ARM :: R9 ; } </s>

Returns the register used as static base in RWPI variants .


<s> StringRef getPassName ( ) const override { return AARCH64_VECTOR_BY_ELEMENT_OPT_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
isDarwinABI
=
Subtarget
.
isDarwinABI
(
)
;
if
(
(
isPPC64
&&
VT
!=
MVT
::
i64
&&
VT
!=
MVT
::
i32
)
||
(
!
isPPC64
&&
VT
!=
MVT
::
i32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
MVT
::
i64
;
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
isDarwinABI
0
:
(
is64Bit
PPC
::
X2
:
PPC
::
R2
)
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
isDarwinABI
)
0
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
SDValue
VETargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ( ! regs_ever_live [ regno ] || call_used_regs [ regno ] ) && ( ! regs_ever_live [ regno + 1 ] || call_used_regs [ regno + 1 ] ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 + 4 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 + 4 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


<s>
bool
ARMBaseInstrInfo
::
analyzeSelect
(
const
MachineInstr
&
MI
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
unsigned
&
TrueOp
,
unsigned
&
FalseOp
,
bool
&
Optimizable
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
TrueOp
=
1
;
FalseOp
=
2
;
Cond
.
push_back
(
MI
.
getOperand
(
3
)
)
;
Cond
.
push_back
(
MI
.
getOperand
(
4
)
)
;
Optimizable
=
true
;
return
false
;
}
</s>

Analyze the given select instruction , returning true if it can not be understood .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARM64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & ARM64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & ARM64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & ARM64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & ARM64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & ARM64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & ARM64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM64 :: CPSR ) , & ARM64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ 2 ] , & Constraint [ Size - 1 ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= 0 && RegNo <= 31 ) { Res . first = ARM64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & ARM64 :: FPR128RegClass ; } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> int symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return 1 ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return 1 ; } return 0 ; } </s>

Return true if OP contains a symbol reference


"JIT does not support pseudo instruction GETPCX yet!"

Targets should implement this to emit instructions .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return combineVECTOR_SHUFFLE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: STRICT_FP_ROUND : case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: STRICT_FP_EXTEND : case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return combineINT_TO_FP ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool X86AsmBackend :: allowAutoPadding ( ) const { return ( AlignBoundary != Align :: None ( ) && AlignBranchType != X86 :: AlignBranchNone ) ; } </s>

Return true if this target might automatically pad instructions and thus need to emit padding enable/disable directives around sensative code .


"LoongArch DAG->DAG Pattern Instruction Selection"


<s> void MMIXInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V4HFmode : gen = gen_neon_vextv4hf ; break ; case V8HFmode : gen = gen_neon_vextv8hf ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx aarch64_expand_builtin ( tree exp , rtx target , rtx , machine_mode , int ignore ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return aarch64_general_expand_builtin ( subcode , exp , target , ignore ) ; case AARCH64_BUILTIN_SVE : return aarch64_sve :: expand_builtin ( subcode , exp , target ) ; } gcc_unreachable ( ) ; } </s>


<s> unsigned stackAlignment ( ) const { return hasMips64 ( ) ? 16 : 8 ; } </s>

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function .


<s> int pru_can_use_return_insn ( void ) { if ( ! reload_completed || crtl -> profile ) return 0 ; return cfun -> machine -> total_size == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> static int arm_barrier_cost ( rtx insn ) { int base_cost = 50 ; rtx next = next_nonnote_insn ( insn ) ; if ( next != NULL && GET_CODE ( next ) == CODE_LABEL ) base_cost -= 20 ; switch ( GET_CODE ( insn ) ) { case CODE_LABEL : return 50 ; case INSN : case CALL_INSN : return base_cost ; case JUMP_INSN : return base_cost - 10 ; default : return base_cost + 10 ; } } </s>

Return the cost of forcibly inserting a barrier after INSN .


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , DL ( isTargetMachO ( ) ? "e-m:o-i64:64-i128:128-n32:64-S128" : ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( & DL ) , TLInfo ( TM ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> size_t THMToARMStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> enum machine_mode mmix_select_cc_mode ( RTX_CODE op , rtx x , rtx y ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { if ( op == ORDERED || op == UNORDERED || op == UNGE || op == UNGT || op == UNLE || op == UNLT ) return CC_FUNmode ; if ( op == EQ || op == NE ) return CC_FPEQmode ; return CC_FPmode ; } if ( op == GTU || op == LTU || op == GEU || op == LEU ) return CC_UNSmode ; return CCmode ; } </s>


<s> bool mep_vliw_jmp_match ( rtx tgt ) { bool src_vliw = mep_vliw_function_p ( cfun -> decl ) ; bool tgt_vliw = INTVAL ( tgt ) ; if ( mep_section_tag ( DECL_RTL ( cfun -> decl ) ) == 'f' ) return false ; return src_vliw == tgt_vliw ; } </s>

Like the above , but also test for near/far mismatches .


<s> const uint32_t * AArch64RegisterInfo :: getWindowsStackProbePreservedMask ( ) const { return CSR_AArch64_StackProbe_Windows_RegMask ; } </s>

Stack probing calls preserve different CSRs to the normal CC .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalign"
)
return
parseDirectiveFPOStackAlign
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>


"getBranchTarget26OpValueMM expects only expressions or immediates"

getBranchTarget26OpValueMM - Return binary encoding of the branch target operand .


<s> static void mep_make_parallel ( rtx_insn * insn1 , rtx_insn * insn2 ) { rtx expr ; if ( RTX_FRAME_RELATED_P ( insn2 ) ) { expr = mep_frame_expr ( insn2 ) ; if ( RTX_FRAME_RELATED_P ( insn1 ) ) expr = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec ( 2 , mep_frame_expr ( insn1 ) , expr ) ) ; set_unique_reg_note ( insn1 , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( insn1 ) = 1 ; } PATTERN ( insn1 ) = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , PATTERN ( insn1 ) , PATTERN ( insn2 ) ) ) ; INSN_CODE ( insn1 ) = - 1 ; } </s>

Merge instructions INSN1 and INSN2 using a PARALLEL . Store the new pattern in INSN1 ; INSN2 will be deleted by the caller .


<s> unsigned SystemZInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case SystemZ :: MOV32rm : case SystemZ :: MOV32rmy : case SystemZ :: MOV64rm : case SystemZ :: MOVSX32rm8 : case SystemZ :: MOVSX32rm16y : case SystemZ :: MOVSX64rm8 : case SystemZ :: MOVSX64rm16 : case SystemZ :: MOVSX64rm32 : case SystemZ :: MOVZX32rm8 : case SystemZ :: MOVZX32rm16 : case SystemZ :: MOVZX64rm8 : case SystemZ :: MOVZX64rm16 : case SystemZ :: MOVZX64rm32 : case SystemZ :: FMOV32rm : case SystemZ :: FMOV32rmy : case SystemZ :: FMOV64rm : case SystemZ :: FMOV64rmy : case SystemZ :: MOV64Prm : case SystemZ :: MOV64Prmy : case SystemZ :: MOV128rm : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 && MI -> getOperand ( 3 ) . getReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> TargetLowering :: ConstraintWeight SparcTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; } break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static unsigned int aarch64_function_arg_alignment ( machine_mode mode , const_tree type ) { if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) ; if ( integer_zerop ( TYPE_SIZE ( type ) ) ) return 0 ; gcc_assert ( TYPE_MODE ( type ) == mode ) ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) ; unsigned int alignment = 0 ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ; return alignment ; } </s>

Given MODE and TYPE of a function argument , return the alignment in bits . The idea is to suppress any stronger alignment requested by the user and opt for the natural alignment ( specified in AAPCS64 \S 4.1 ) . This is a helper function for local use only .


<s> const X86TargetMachine & getTargetMachine ( ) const { return static_cast < const X86TargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
Imm
.
Val
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
Mem
.
Off
->
print
(
OS
)
;
OS
<<
">"
;
break
;
case
k_PhysRegister
:
OS
<<
"PhysReg<"
<<
PhysReg
.
Num
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool X86TargetLowering :: isTruncateFree ( const Type * Ty1 , const Type * Ty2 ) const { if ( ! Ty1 -> isIntegerTy ( ) || ! Ty2 -> isIntegerTy ( ) ) return false ; unsigned NumBits1 = Ty1 -> getPrimitiveSizeInBits ( ) ; unsigned NumBits2 = Ty2 -> getPrimitiveSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return true ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
Value
*
AArch64TargetLowering
::
emitStoreConditional
(
IRBuilderBase
&
Builder
,
Value
*
Val
,
Value
*
Addr
,
AtomicOrdering
Ord
)
const
{
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
bool
IsRelease
=
isReleaseOrStronger
(
Ord
)
;
if
(
Val
->
getType
(
)
->
getPrimitiveSizeInBits
(
)
==
128
)
{
Intrinsic
::
ID
Int
=
IsRelease
Intrinsic
::
aarch64_stlxp
:
Intrinsic
::
aarch64_stxp
;
Function
*
Stxr
=
Intrinsic
::
getDeclaration
(
M
,
Int
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
Lo
=
Builder
.
CreateTrunc
(
Val
,
Int64Ty
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Val
,
64
)
,
Int64Ty
,
"hi"
)
;
Addr
=
Builder
.
CreateBitCast
(
Addr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
return
Builder
.
CreateCall
(
Stxr
,
{
Lo
,
Hi
,
Addr
}
)
;
}
Intrinsic
::
ID
Int
=
IsRelease
Intrinsic
::
aarch64_stlxr
:
Intrinsic
::
aarch64_stxr
;
const
DataLayout
&
DL
=
M
->
getDataLayout
(
)
;
IntegerType
*
IntValTy
=
Builder
.
getIntNTy
(
DL
.
getTypeSizeInBits
(
Val
->
getType
(
)
)
)
;
if
(
Val
->
getType
(
)
->
isPointerTy
(
)
)
Addr
=
Builder
.
CreatePointerCast
(
Addr
,
IntValTy
->
getPointerTo
(
Addr
->
getType
(
)
->
getPointerAddressSpace
(
)
)
)
;
Type
*
Tys
[
]
=
{
Addr
->
getType
(
)
}
;
Function
*
Stxr
=
Intrinsic
::
getDeclaration
(
M
,
Int
,
Tys
)
;
assert
(
!
DL
.
isFatPointer
(
Val
->
getType
(
)
)
&&
"Should not be handled here!"
)
;
if
(
Val
->
getType
(
)
->
isPointerTy
(
)
)
Val
=
Builder
.
CreatePtrToInt
(
Val
,
IntValTy
)
;
else
Val
=
Builder
.
CreateBitCast
(
Val
,
IntValTy
)
;
return
Builder
.
CreateCall
(
Stxr
,
{
Builder
.
CreateZExtOrBitCast
(
Val
,
Stxr
->
getFunctionType
(
)
->
getParamType
(
0
)
)
,
Addr
}
)
;
}
</s>

Perform a store-conditional operation to Addr .


<s> MCObjectWriter * LanaiAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createLanaiELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool aarch64_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { return FP_REGNUM_P ( regno ) && maybe_gt ( GET_MODE_SIZE ( mode ) , 8 ) ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The callee only saves the lower 64 bits of a 128-bit register . Tell the compiler the callee clobbers the top 64 bits when restoring the bottom 64 bits .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LW
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
{
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
isMips1
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LDC1
)
,
DestReg
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
MBB
.
getParent
(
)
->
getTarget
(
)
.
getRegisterInfo
(
)
;
const
unsigned
*
SubSet
=
TRI
->
getSubRegisters
(
DestReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
0
]
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
LWC1
)
,
SubSet
[
1
]
)
.
addImm
(
4
)
.
addFrameIndex
(
FI
)
;
}
}
else
llvm_unreachable
(
"Register class not handled!"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case SCmode : case DCmode : case TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || FLOAT128_VECTOR_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> unsigned DLXInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return 1 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> unsigned SystemZTTIImpl :: getMinPrefetchStride ( unsigned NumMemAccesses , unsigned NumStridedMemAccesses , unsigned NumPrefetches , bool HasCall ) const { if ( NumPrefetches > 16 ) return UINT_MAX ; if ( NumStridedMemAccesses > 32 && NumStridedMemAccesses == NumMemAccesses && ! HasCall ) return 1 ; return ST -> hasMiscellaneousExtensions3 ( ) ? 8192 : 2048 ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s>
SDValue
LoongArchTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
CCInfo
,
Outs
,
CC_LoongArch
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
LoongArchISD
::
RET
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void rs6000_emit_le_vsx_load ( rtx dest , rtx source , machine_mode mode ) { if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , 0 ) ; } rtx tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; rs6000_emit_le_vsx_permute ( tmp , source , mode ) ; rs6000_emit_le_vsx_permute ( dest , tmp , mode ) ; } </s>

Emit a little-endian load from vector memory location SOURCE to VSX register DEST in mode MODE . The load is done with two permuting insn 's that represent an lxvd2x and xxpermdi .


<s>
static
std
::
string
getEdgeAttributes
(
NodeRef
,
ChildIteratorType
E
,
GraphType
*
)
{
int
EdgeVal
=
(
*
E
.
getCurrent
(
)
)
.
getValue
(
)
;
return
EdgeVal
>=
0
"label = "
+
std
::
to_string
(
EdgeVal
)
:
"color = red, style = \"dashed\""
;
}
</s>

If you want to override the dot attributes printed for a particular edge , override this method .


<s> static rtx aarch64_gen_storewb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case DImode : return gen_storewb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; case DFmode : return gen_storewb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return an instruction to store the pair of registers REG and REG2 of mode MODE to location BASE with write-back adjusting the stack location BASE by ADJUSTMENT .


"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s> bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ) { tree fntype ; if ( CALL_EXPR_STATIC_CHAIN ( exp ) ) return false ; if ( decl ) fntype = TREE_TYPE ( decl ) ; else fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE && ! ( decl && decl == current_function_decl ) ) { function_args_iterator args_iter ; tree type ; int nvreg = 0 ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > 0 ) return false ; } if ( rs6000_decl_ok_for_sibcall ( decl ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> static bool expand_vec_perm_pshuflw_pshufhw ( struct expand_vec_perm_d * d ) { unsigned char perm2 [ MAX_VECT_LEN ] ; unsigned i ; bool ok ; if ( d -> vmode != V8HImode || ! d -> one_operand_p ) return false ; for ( i = 0 ; i < 4 ; ++ i ) if ( d -> perm [ i ] >= 4 ) return false ; for ( i = 4 ; i < 8 ; ++ i ) if ( d -> perm [ i ] < 4 ) return false ; if ( d -> testing_p ) return true ; memcpy ( perm2 , d -> perm , 4 ) ; for ( i = 4 ; i < 8 ; ++ i ) perm2 [ i ] = i ; ok = expand_vselect ( d -> target , d -> op0 , perm2 , 8 , d -> testing_p ) ; gcc_assert ( ok ) ; memcpy ( perm2 + 4 , d -> perm + 4 , 4 ) ; for ( i = 0 ; i < 4 ; ++ i ) perm2 [ i ] = i ; ok = expand_vselect ( d -> target , d -> target , perm2 , 8 , d -> testing_p ) ; gcc_assert ( ok ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement D in terms of a pair of pshuflw + pshufhw instructions .


<s> machine_mode aarch64_sve_int_mode ( machine_mode mode ) { scalar_int_mode int_mode = aarch64_sve_element_int_mode ( mode ) ; return aarch64_sve_data_mode ( int_mode , GET_MODE_NUNITS ( mode ) ) . require ( ) ; } </s>

Return the integer vector mode associated with SVE mode MODE . Unlike related_int_vector_mode , this can handle the case in which MODE is a predicate ( and thus has a different total size ) .


<s> void LEGFrameLowering :: emitPrologue ( MachineFunction & MF ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = LEG :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: SUBrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: SUBri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool arm_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ; } return false ; } </s>

Return TRUE if X contains any TLS symbol references .


<s>
unsigned
PPCInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
&
PreHeader
,
MachineInstr
*
IndVar
,
MachineInstr
&
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isBDNZ
(
Cmp
.
getOpcode
(
)
)
&&
"Expecting a CTR loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
.
getDebugLoc
(
)
;
MachineInstr
*
Loop
=
findLoopInstr
(
PreHeader
)
;
if
(
!
Loop
)
return
0
;
Register
LoopCountReg
=
Loop
->
getOperand
(
0
)
.
getReg
(
)
;
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MachineInstr
*
LoopCount
=
MRI
.
getUniqueVRegDef
(
LoopCountReg
)
;
if
(
!
LoopCount
)
return
0
;
if
(
LoopCount
->
getOpcode
(
)
==
PPC
::
LI8
||
LoopCount
->
getOpcode
(
)
==
PPC
::
LI
)
{
int64_t
Offset
=
LoopCount
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
{
LoopCount
->
eraseFromParent
(
)
;
Loop
->
eraseFromParent
(
)
;
return
0
;
}
LoopCount
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
0
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateReg
(
Subtarget
.
isPPC64
(
)
PPC
::
CTR8
:
PPC
::
CTR
,
true
)
)
;
return
LoopCountReg
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s> void PPCELFStreamer :: emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { PPCMCCodeEmitter * Emitter = static_cast < PPCMCCodeEmitter * > ( getAssembler ( ) . getEmitterPtr ( ) ) ; Optional < bool > IsPartOfGOTToPCRelPair = isPartOfGOTToPCRelPair ( Inst , STI ) ; if ( IsPartOfGOTToPCRelPair . hasValue ( ) && ! IsPartOfGOTToPCRelPair . getValue ( ) ) emitGOTToPCRelReloc ( Inst ) ; if ( ! Emitter -> isPrefixedInstruction ( Inst ) ) { MCELFStreamer :: emitInstruction ( Inst , STI ) ; return ; } emitPrefixedInstruction ( Inst , STI ) ; if ( IsPartOfGOTToPCRelPair . hasValue ( ) && IsPartOfGOTToPCRelPair . getValue ( ) ) emitGOTToPCRelLabel ( Inst ) ; } </s>

Targets should implement this to emit instructions .


<s> const Cpu0AnalyzeImmediate :: InstSeq & Cpu0AnalyzeImmediate :: Analyze ( uint64_t Imm , unsigned Size , bool LastInstrIsADDiu ) { this -> Size = Size ; ADDiu = Cpu0 :: ADDiu ; ORi = Cpu0 :: ORi ; SHL = Cpu0 :: SHL ; LUi = Cpu0 :: LUi ; InstSeqLs SeqLs ; if ( LastInstrIsADDiu | ! Imm ) GetInstSeqLsADDiu ( Imm , Size , SeqLs ) ; else GetInstSeqLs ( Imm , Size , SeqLs ) ; GetShortestSeq ( SeqLs , Insts ) ; return Insts ; } </s>

Analyze - Get an instruction sequence to load immediate Imm .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a ( possibly variable ) scalar , using EXPECTED as the name of its expected type . Return true if the argument has the right form , otherwise report an appropriate error .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned MaxCallSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; unsigned FrameSizeMinusRBP = RoundUpToAlignment ( CSSize + MaxCallSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> static void mips_dfa_post_advance_cycle ( void ) { if ( TUNE_LOONGSON_2EF ) mips_ls2_dfa_post_advance_cycle ( curr_state ) ; } </s>

Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE . This hook is being called at the start of each cycle .


<s> int ix86_issue_rate ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_KNM : case PROCESSOR_INTEL : case PROCESSOR_K6 : case PROCESSOR_BTVER2 : case PROCESSOR_PENTIUM4 : case PROCESSOR_NOCONA : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_ATHLON : case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_BTVER1 : return 3 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_GENERIC : return 4 ; default : return 1 ; } } </s>

Return the maximum number of instructions a cpu can issue .


<s> const MCExpr * PPC64LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_DTPREL , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> static void create_bif_order ( void ) { bif_order = ( int * ) malloc ( ( curr_bif + 1 ) * sizeof ( int ) ) ; rbt_inorder_callback ( & bifo_rbt , bifo_rbt . rbt_root , set_bif_order ) ; } </s>

Create a mapping from function IDs in their final order to the order they appear in the built-in function file .


<s> static void do_load_for_compare ( rtx reg , rtx mem , machine_mode mode ) { switch ( GET_MODE ( reg ) ) { case E_V16QImode : switch ( mode ) { case E_V16QImode : if ( ! BYTES_BIG_ENDIAN ) { if ( TARGET_P9_VECTOR ) emit_insn ( gen_vsx_ld_elemrev_v16qi_internal ( reg , mem ) ) ; else { rtx reg_v2di = simplify_gen_subreg ( V2DImode , reg , V16QImode , 0 ) ; gcc_assert ( MEM_P ( mem ) ) ; rtx addr = XEXP ( mem , 0 ) ; rtx mem_v2di = gen_rtx_MEM ( V2DImode , addr ) ; MEM_COPY_ATTRIBUTES ( mem_v2di , mem ) ; set_mem_size ( mem , GET_MODE_SIZE ( V2DImode ) ) ; emit_insn ( gen_vsx_ld_elemrev_v2di ( reg_v2di , mem_v2di ) ) ; } } else emit_insn ( gen_vsx_movv2di_64bit ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_DImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case E_SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case E_DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_SImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case E_SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case E_DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_QImode : gcc_assert ( mode == E_QImode ) ; emit_move_insn ( reg , mem ) ; break ; default : gcc_unreachable ( ) ; break ; } } </s>

Figure out the correct instructions to generate to load data for block compare . MODE is used for the read from memory , and data is zero extended if REG is wider than MODE . If LE code is being generated , bswap loads are used . REG is the destination register to move the data into . MEM is the memory block being read . MODE is the mode of memory to use for the read .


<s> bool ARMSubtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) && ( ! isThumb ( ) || hasV8MBaselineOps ( ) ) ; } </s>

True if the subtarget should run the atomic expansion pass .


<s> void LanaiAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getArchName ( ) != "arm64e" && TT . getEnvironment ( ) != Triple :: GNUILP32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> bool ARMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) { } </s>


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> MCInst PPCInstrInfo :: getNop ( ) const { MCInst Nop ; Nop . setOpcode ( PPC :: NOP ) ; return Nop ; } </s>

Return the noop instruction to use for a noop .


<s> static void csky_reorg ( void ) { if ( TARGET_CONSTANT_POOL ) csky_emit_constant_pools ( ) ; } </s>

Implement TARGET_MACHINE_DEPENDENT_REORG . This handles -mconstpool output .


"emitting conditional microcode insn %s\t[%s] #%d"

Define FINAL_PRESCAN_INSN if some processing needs to be done before outputting the assembler code . On the PowerPC , we remember if the current insn is a prefixed insn where we need to emit a ' p ' before the insn . In addition , if the insn is part of a PC-relative reference to an external label optimization , this is recorded also .


<s> bool AArch64RegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const { return PhysReg == AArch64 :: WZR || PhysReg == AArch64 :: XZR ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> void MipsOutgoingValueHandler :: assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; uint64_t LocMemOffset = VA . getLocMemOffset ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , MemTy , commonAlignment ( STI . getStackAlignment ( ) , LocMemOffset ) ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = ( regno1 <= R30_REGNUM ) ? E_DImode : E_DFmode ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 2 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push registers numbered REGNO1 and REGNO2 to the stack , adjusting the stack pointer by ADJUSTMENT .


<s> static bool aarch64_sched_can_speculate_insn ( rtx_insn * insn ) { switch ( get_attr_type ( insn ) ) { case TYPE_SDIV : case TYPE_UDIV : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_FSQRTS : case TYPE_FSQRTD : case TYPE_NEON_FP_SQRT_S : case TYPE_NEON_FP_SQRT_D : case TYPE_NEON_FP_SQRT_S_Q : case TYPE_NEON_FP_SQRT_D_Q : case TYPE_NEON_FP_DIV_S : case TYPE_NEON_FP_DIV_D : case TYPE_NEON_FP_DIV_S_Q : case TYPE_NEON_FP_DIV_D_Q : return false ; default : return true ; } } </s>

Implement TARGET_SCHED_CAN_SPECULATE_INSN . Return true if INSN can be scheduled for speculative execution . Reject the long-running division and square-root instructions .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentInstruction ( Inst , Operands , getContext ( ) , MII , Out ) ; Out . EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void SystemZInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( LoadOpcode ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool X86TargetLowering :: isLegalStoreImmediate ( int64_t Imm ) const { return isInt < 32 > ( Imm ) ; } </s>

Return true if the specified immediate is legal for the value input of a store instruction .


<s> static bool mips_expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt ) { machine_mode v2mode ; rtx x ; v2mode = GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) ; x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return mips_expand_vselect ( target , x , perm , nelt ) ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s>
SDValue
LanaiTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
MUL
:
return
LowerMUL
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
LowerSHL_PARTS
(
Op
,
DAG
)
;
case
ISD
::
SRL_PARTS
:
return
LowerSRL_PARTS
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Lanai
Lanai
ISD::MUL
ISD::BR_CC
ISD::ConstantPool
ISD::GlobalAddress
ISD::BlockAddress
ISD::JumpTable
ISD::SELECT_CC
ISD::SETCC
ISD::SHL_PARTS
ISD::SRL_PARTS
ISD::VASTART
ISD::DYNAMIC_STACKALLOC
ISD::RETURNADDR
ISD::FRAMEADDR
"unimplemented operand"