<s> void MMIXFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( MMIX :: r253 ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static void iq2000_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { unsigned int iq2000_off = ! cum -> last_arg_fp ; unsigned int iq2000_fp_off = cum -> last_arg_fp ; if ( ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) ) { int iq2000_save_gp_regs = MAX_ARGS_IN_REGISTERS - cum -> arg_words - iq2000_off ; int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum -> fp_arg_words - iq2000_fp_off ) ; if ( iq2000_save_gp_regs < 0 ) iq2000_save_gp_regs = 0 ; if ( iq2000_save_fp_regs < 0 ) iq2000_save_fp_regs = 0 ; * pretend_size = ( ( iq2000_save_gp_regs * UNITS_PER_WORD ) + ( iq2000_save_fp_regs * UNITS_PER_FPREG ) ) ; if ( ! ( no_rtl ) ) { if ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , - ( iq2000_save_gp_regs * UNITS_PER_WORD ) ) ; mem = gen_rtx_MEM ( BLKmode , ptr ) ; move_block_from_reg ( cum -> arg_words + GP_ARG_FIRST + iq2000_off , mem , iq2000_save_gp_regs ) ; } } } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> static bool use_toc_relative_ref ( rtx sym ) { return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) ) || ( TARGET_CMODEL == CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) ) ) ; } </s>

Return true iff the given SYMBOL_REF refers to a constant pool entry that we have put in the TOC , or for cmodel=medium , if the SYMBOL_REF can be addressed relative to the toc pointer .


<s> const char * output_387_reg_move ( rtx insn , rtx * operands ) { if ( REG_P ( operands [ 0 ] ) ) { if ( REG_P ( operands [ 1 ] ) && find_regno_note ( insn , REG_DEAD , REGNO ( operands [ 1 ] ) ) ) { if ( REGNO ( operands [ 0 ] ) == FIRST_STACK_REG ) return output_387_ffreep ( operands , 0 ) ; return "fstp\t%y0" ; } if ( STACK_TOP_P ( operands [ 0 ] ) ) return "fld%Z1\t%y1" ; return "fst\t%y0" ; } else if ( MEM_P ( operands [ 0 ] ) ) { gcc_assert ( REG_P ( operands [ 1 ] ) ) ; if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ 1 ] ) ) ) return "fstp%Z0\t%y0" ; else { if ( GET_MODE ( operands [ 0 ] ) == XFmode ) return "fstp%Z0\t%y0\n\tfld%Z0\t%y0" ; else return "fst%Z0\t%y0" ; } } else gcc_unreachable ( ) ; } </s>

Output code to perform an x87 FP register move , from OPERANDS [ 1 ] to OPERANDS [ 0 ] .


<s> bool isLegalMaskedStore ( Type * DataTy ) { return isLegalMaskedLoad ( DataTy ) ; } </s>

Return true if the target supports masked store .


"rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n"

A C expressions returning the cost of moving data of MODE from a register to or from memory .


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const TargetFrameLowering * TFI = STI . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return getFramePointerReg ( STI ) ; return ARM :: SP ; } </s>


<s> bool SparcAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> getDesc ( ) . isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> getDesc ( ) . isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> static enum reg_class rs6000_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx in ) { int regno ; if ( TARGET_ELF || ( DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT ) ) { if ( rclass != BASE_REGS && ( GET_CODE ( in ) == SYMBOL_REF || GET_CODE ( in ) == HIGH || GET_CODE ( in ) == LABEL_REF || GET_CODE ( in ) == CONST ) ) return BASE_REGS ; } if ( GET_CODE ( in ) == REG ) { regno = REGNO ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } } else if ( GET_CODE ( in ) == SUBREG ) { regno = true_regnum ( in ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = - 1 ; } else regno = - 1 ; if ( TARGET_VSX && GET_MODE_SIZE ( mode ) < 16 && ! mode_supports_vmx_dform ( mode ) && ( ( ( rclass == GENERAL_REGS || rclass == BASE_REGS ) && ( regno >= 0 && ALTIVEC_REGNO_P ( regno ) ) ) || ( ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( regno >= 0 && INT_REGNO_P ( regno ) ) ) ) ) return FLOAT_REGS ; if ( rclass == GENERAL_REGS || rclass == BASE_REGS || ( regno >= 0 && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( rclass == VSX_REGS && ( regno == - 1 || VSX_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - 1 || FP_REGNO_P ( regno ) ) && ( rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS ) ) return ( mode != SDmode || lra_in_progress ) ? NO_REGS : GENERAL_REGS ; if ( ( regno == - 1 || ALTIVEC_REGNO_P ( regno ) ) && rclass == ALTIVEC_REGS ) return NO_REGS ; if ( ( rclass == CR_REGS || rclass == CR0_REGS ) && regno >= 0 && CR_REGNO_P ( regno ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return the register class of a scratch register needed to copy IN into or out of a register in RCLASS in MODE . If it can be done directly , NO_REGS is returned .


"%<gp_offset%> (%ld) or %<end_offset%> (%ld) is less than zero"

Save or restore instructions based on whether this is the prologue or epilogue . prologue is 1 for the prologue .


<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { if ( Inst . getFlags ( ) & X86 :: EXTRA_DO_NOT_RELAX ) return false ; if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - 1 ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , unsigned EncodingAlignment ) const { int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( hasSPE ( ) && SelectAddressEVXRegReg ( N , Base , Index , DAG ) ) return true ; if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( 1 ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


"Switch should handle all register classes"


<s>
static
void
seh_cfa_adjust_cfa
(
FILE
*
f
,
struct
seh_frame_state
*
seh
,
rtx
pat
)
{
rtx
dest
,
src
;
HOST_WIDE_INT
reg_offset
=
0
;
unsigned
int
dest_regno
;
dest
=
SET_DEST
(
pat
)
;
src
=
SET_SRC
(
pat
)
;
if
(
GET_CODE
(
src
)
==
PLUS
)
{
reg_offset
=
INTVAL
(
XEXP
(
src
,
1
)
)
;
src
=
XEXP
(
src
,
0
)
;
}
else
if
(
GET_CODE
(
src
)
==
MINUS
)
{
reg_offset
=
INTVAL
(
XEXP
(
src
,
1
)
)
;
src
=
XEXP
(
src
,
0
)
;
}
gcc_assert
(
src
==
stack_pointer_rtx
)
;
gcc_assert
(
seh
->
cfa_reg
==
stack_pointer_rtx
)
;
dest_regno
=
REGNO
(
dest
)
;
if
(
dest_regno
==
STACK_POINTER_REGNUM
)
seh_emit_stackalloc
(
f
,
seh
,
reg_offset
)
;
else
if
(
dest_regno
==
HARD_FRAME_POINTER_REGNUM
)
{
HOST_WIDE_INT
offset
;
seh
->
cfa_reg
=
dest
;
seh
->
cfa_offset
-=
reg_offset
;
offset
=
seh
->
sp_offset
seh
->
cfa_offset
;
gcc_assert
(
(
offset
&
15
)
==
0
)
;
gcc_assert
(
IN_RANGE
(
offset
,
0
,
240
)
)
;
fputs
(
"\t.seh_setframe\t"
,
f
)
;
print_reg
(
seh
->
cfa_reg
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
else
gcc_unreachable
(
)
;
}
</s>


<s> void ia64_expand_atomic_op ( enum rtx_code code , rtx mem , rtx val , rtx old_dst , rtx new_dst ) { enum machine_mode mode = GET_MODE ( mem ) ; rtx old_reg , new_reg , cmp_reg , ar_ccv , label ; enum insn_code icode ; if ( ( mode == SImode || mode == DImode ) && ( code == PLUS || code == MINUS ) && fetchadd_operand ( val , mode ) ) { if ( code == MINUS ) val = GEN_INT ( - INTVAL ( val ) ) ; if ( ! old_dst ) old_dst = gen_reg_rtx ( mode ) ; emit_insn ( gen_memory_barrier ( ) ) ; if ( mode == SImode ) icode = CODE_FOR_fetchadd_acq_si ; else icode = CODE_FOR_fetchadd_acq_di ; emit_insn ( GEN_FCN ( icode ) ( old_dst , mem , val ) ) ; if ( new_dst ) { new_reg = expand_simple_binop ( mode , PLUS , old_dst , val , new_dst , true , OPTAB_WIDEN ) ; if ( new_reg != new_dst ) emit_move_insn ( new_dst , new_reg ) ; } return ; } gcc_assert ( MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , 0 ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , 1 ) ) ; } else emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; ar_ccv = gen_rtx_REG ( DImode , AR_CCV_REGNUM ) ; emit_move_insn ( old_reg , cmp_reg ) ; emit_move_insn ( ar_ccv , cmp_reg ) ; if ( old_dst ) emit_move_insn ( old_dst , gen_lowpart ( mode , cmp_reg ) ) ; new_reg = cmp_reg ; if ( code == NOT ) { new_reg = expand_simple_unop ( DImode , NOT , new_reg , NULL_RTX , true ) ; code = AND ; } new_reg = expand_simple_binop ( DImode , code , new_reg , val , NULL_RTX , true , OPTAB_DIRECT ) ; if ( mode != DImode ) new_reg = gen_lowpart ( mode , new_reg ) ; if ( new_dst ) emit_move_insn ( new_dst , new_reg ) ; switch ( mode ) { case QImode : icode = CODE_FOR_cmpxchg_rel_qi ; break ; case HImode : icode = CODE_FOR_cmpxchg_rel_hi ; break ; case SImode : icode = CODE_FOR_cmpxchg_rel_si ; break ; case DImode : icode = CODE_FOR_cmpxchg_rel_di ; break ; default : gcc_unreachable ( ) ; } emit_insn ( GEN_FCN ( icode ) ( cmp_reg , mem , ar_ccv , new_reg ) ) ; emit_cmp_and_jump_insns ( cmp_reg , old_reg , NE , NULL , DImode , true , label ) ; } </s>

Expand an atomic operation . We want to perform MEM < CODE > = VAL atomically . This differs from the generic code in that we know about the zero-extending properties of cmpxchg , and the zero-extending requirements of ar.ccv . We also know that ld.acq+cmpxchg.rel equals a full barrier . The loop we want to generate looks like cmp_reg = mem ; label : old_reg = cmp_reg ; new_reg = cmp_reg op val ; cmp_reg = compare-and-swap ( mem , old_reg , new_reg ) if ( cmp_reg ! = old_reg ) goto label ; Note that we only do the plain load from memory once . Subsequent iterations use the value loaded by the compare-and-swap pattern .


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , unsigned Depth ) const { if ( Op . getOpcode ( ) == X86ISD :: SETCC_CARRY ) return Op . getValueType ( ) . getScalarType ( ) . getSizeInBits ( ) ; return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; switch ( IntrData -> Type ) { case LOADA : case LOADU : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = ( IntrData -> Type == LOADA ? Info . memVT . getSizeInBits ( ) / 8 : 1 ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void LanaiFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const LanaiRegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; Align StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI . getMaxAlign ( ) : getStackAlign ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"expression value must be representiable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void sparc_expand_prologue ( void ) { rtx insn ; int i ; sparc_leaf_function_p = optimize > 0 && leaf_function_p ( ) && only_leaf_regs_used ( ) ; actual_fsize = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; sparc_prologue_data_valid_p = true ; if ( sparc_leaf_function_p ) { frame_base_reg = stack_pointer_rtx ; frame_base_offset = actual_fsize + SPARC_STACK_BIAS ; } else { frame_base_reg = hard_frame_pointer_rtx ; frame_base_offset = SPARC_STACK_BIAS ; } if ( actual_fsize == 0 ) ; else if ( sparc_leaf_function_p ) { if ( actual_fsize <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - actual_fsize ) ) ) ; else if ( actual_fsize <= 8192 ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - actual_fsize ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( - actual_fsize ) ) ; insn = emit_insn ( gen_stack_pointer_inc ( reg ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( GEN_INT ( - actual_fsize ) ) , REG_NOTES ( insn ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } else { if ( actual_fsize <= 4096 ) insn = emit_insn ( gen_save_register_window ( GEN_INT ( - actual_fsize ) ) ) ; else if ( actual_fsize <= 8192 ) { insn = emit_insn ( gen_save_register_window ( GEN_INT ( - 4096 ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - actual_fsize ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( - actual_fsize ) ) ; insn = emit_insn ( gen_save_register_window ( reg ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , i ) ) = 1 ; } if ( num_gfregs ) emit_save_or_restore_regs ( SORR_SAVE ) ; if ( flag_pic && current_function_uses_pic_offset_table ) load_pic_register ( false ) ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the PIC register if needed .


<s> void PPCTTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { if ( ST -> getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Lanai Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_SPE ) ? RS6000_BTM_SPE : 0 ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


<s> static rtx function_arg_union_value ( int size , machine_mode mode , int slotno , int regno ) { int nwords = ROUND_ADVANCE ( size ) , i ; rtx regs ; if ( nwords == 0 ) return gen_rtx_REG ( mode , regno ) ; if ( slotno == SPARC_INT_ARG_MAX - 1 ) nwords = 1 ; regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( i = 0 ; i < nwords ; i ++ ) { XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , GEN_INT ( UNITS_PER_WORD * i ) ) ; regno ++ ; } return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions of the 64-bit ABI for passing and returning unions . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the union . MODE is the argument 's machine mode . REGNO is the hard register the union will be passed in .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static rtx ix86_expand_vec_set_builtin ( tree exp ) { machine_mode tmode , mode1 ; tree arg0 , arg1 , arg2 ; int elt ; rtx op0 , op1 , target ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; arg2 = CALL_EXPR_ARG ( exp , 2 ) ; tmode = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; mode1 = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , tmode , EXPAND_NORMAL ) ; op1 = expand_expr ( arg1 , NULL_RTX , mode1 , EXPAND_NORMAL ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg2 ) ; if ( GET_MODE ( op1 ) != mode1 && GET_MODE ( op1 ) != VOIDmode ) op1 = convert_modes ( mode1 , GET_MODE ( op1 ) , op1 , true ) ; op0 = force_reg ( tmode , op0 ) ; op1 = force_reg ( mode1 , op1 ) ; target = gen_reg_rtx ( tmode ) ; emit_move_insn ( target , op0 ) ; ix86_expand_vector_set ( true , target , op1 , elt ) ; return target ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_set . They would be redundant ( for non-MMX ) if we had a language-level syntax for referencing vector elements .


<s> int neon_vector_mem_operand ( rtx op , int type , bool strict ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return ! strict ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( ( type != 1 && GET_CODE ( ind ) == POST_INC ) || ( type == 0 && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( type == 2 && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , 1 ) , 1 ) ) ) return true ; if ( type == 0 && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , 0 ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , 1 ) ) && INTVAL ( XEXP ( ind , 1 ) ) > - 1024 && ( INTVAL ( XEXP ( ind , 1 ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? 1016 : 1024 ) ) && ( INTVAL ( XEXP ( ind , 1 ) ) & 3 ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a memory operand which we can load or store a vector to/from . TYPE is one of the following values : 0 - Vector load/stor ( vldr ) 1 - Core registers ( ldm ) 2 - Element/structure loads ( vld1 )


<s> bool csky_minipool_load_p ( rtx_insn * insn ) { rtx op1 , addr ; extract_insn_cached ( insn ) ; op1 = recog_data . operand [ 1 ] ; if ( CONSTANT_P ( op1 ) ) return true ; if ( GET_CODE ( op1 ) == ZERO_EXTEND || GET_CODE ( op1 ) == SIGN_EXTEND ) op1 = XEXP ( op1 , 0 ) ; if ( GET_CODE ( op1 ) != MEM ) return false ; addr = XEXP ( op1 , 0 ) ; if ( GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; return GET_CODE ( addr ) == LABEL_REF ; } </s>

Return true if INSN is a minipool load or instruction that will be converted to one . It is assumed that INSN has type attribute `` load '' .


<s> static rtx altivec_expand_ld_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 ; machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_load_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_load_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_vector_altivec_load_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_load_v4sf ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2df : icode = CODE_FOR_vector_altivec_load_v2df ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2di : icode = CODE_FOR_vector_altivec_load_v2di ; case ALTIVEC_BUILTIN_LD_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_load_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ 0 ] . mode ; mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> static bool rs6000_const_not_ok_for_debug_p ( rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) { rtx c = get_pool_constant ( x ) ; machine_mode cmode = get_pool_mode ( x ) ; if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( c , cmode ) ) return true ; } return false ; } </s>

Return true if X should n't be emitted into the debug info . The linker does n't like .toc section references from .debug_ * sections , so reject .toc section symbols .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool nds32_expand_cpymemsi_loop_unknown_size ( rtx dstmem , rtx srcmem , rtx size , rtx alignment ) { rtx dst_base_reg , src_base_reg ; rtx dst_itr , src_itr ; rtx dstmem_m , srcmem_m , dst_itr_m , src_itr_m ; rtx dst_end ; rtx size_least_3_bit ; rtx double_word_end ; rtx double_word_mode_loop , byte_mode_entry , byte_mode_loop , end_label ; rtx tmp ; rtx mask_least_3_bit ; int start_regno ; bool align_to_4_bytes = ( INTVAL ( alignment ) & 3 ) == 0 ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return 0 ; if ( TARGET_REDUCED_REGS ) start_regno = 2 ; else start_regno = 16 ; dst_itr = gen_reg_rtx ( Pmode ) ; src_itr = gen_reg_rtx ( Pmode ) ; dst_end = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( QImode ) ; mask_least_3_bit = GEN_INT ( ~ 7 ) ; double_word_mode_loop = gen_label_rtx ( ) ; byte_mode_entry = gen_label_rtx ( ) ; byte_mode_loop = gen_label_rtx ( ) ; end_label = gen_label_rtx ( ) ; dst_base_reg = copy_to_mode_reg ( Pmode , XEXP ( dstmem , 0 ) ) ; src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , 0 ) ) ; size_least_3_bit = expand_binop ( SImode , and_optab , size , mask_least_3_bit , NULL_RTX , 0 , OPTAB_WIDEN ) ; dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_cmp_and_jump_insns ( size_least_3_bit , const0_rtx , EQ , NULL , SImode , 1 , byte_mode_entry ) ; double_word_end = expand_binop ( Pmode , add_optab , dst_base_reg , size_least_3_bit , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_label ( double_word_mode_loop ) ; src_itr_m = src_itr ; dst_itr_m = dst_itr ; srcmem_m = srcmem ; dstmem_m = dstmem ; nds32_emit_mem_move_block ( start_regno , 2 , & dst_itr_m , & dstmem_m , & src_itr_m , & srcmem_m , true ) ; emit_move_insn ( dst_itr , dst_itr_m ) ; emit_move_insn ( src_itr , src_itr_m ) ; emit_cmp_and_jump_insns ( double_word_end , dst_itr , NE , NULL , Pmode , 1 , double_word_mode_loop ) ; emit_label ( byte_mode_entry ) ; emit_cmp_and_jump_insns ( dst_itr , dst_end , EQ , NULL , Pmode , 1 , end_label ) ; emit_label ( byte_mode_loop ) ; nds32_emit_post_inc_load_store ( tmp , src_itr , QImode , true ) ; nds32_emit_post_inc_load_store ( tmp , dst_itr , QImode , false ) ; emit_cmp_and_jump_insns ( dst_itr , dst_end , NE , NULL , SImode , 1 , byte_mode_loop ) ; emit_label ( end_label ) ; return true ; } </s>

Auxiliary function for expand cpymem pattern .


<s> static void csky_function_arg_advance ( cumulative_args_t pcum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int param_size = csky_num_arg_regs ( mode , type ) ; if ( * pcum + param_size > CSKY_NPARM_REGS ) * pcum = CSKY_NPARM_REGS ; else * pcum += param_size ; } </s>


<s> void SHUXIInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( SHUXI :: POP ) ) . addReg ( DestReg , getDefRegState ( true ) ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI -> getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI -> getObjectAlignment ( Obj ) ; int ObjectSize = MFI -> getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI -> getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> const X86TargetMachine & getTargetMachine ( ) { return static_cast < const X86TargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
MIB
.
addUse
(
PhysReg
,
RegState
::
Implicit
)
;
Register
ExtReg
;
unsigned
PhysRegSize
=
MRI
.
getTargetRegisterInfo
(
)
->
getRegSizeInBits
(
PhysReg
,
MRI
)
;
unsigned
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
unsigned
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
if
(
PhysRegSize
>
ValSize
&&
LocSize
==
ValSize
)
{
assert
(
(
PhysRegSize
==
128
||
PhysRegSize
==
80
)
&&
"We expect that to be 128 bit"
)
;
auto
MIB
=
MIRBuilder
.
buildAnyExt
(
LLT
::
scalar
(
PhysRegSize
)
,
ValVReg
)
;
ExtReg
=
MIB
.
getReg
(
0
)
;
}
else
ExtReg
=
extendRegister
(
ValVReg
,
VA
)
;
MIRBuilder
.
buildCopy
(
PhysReg
,
ExtReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SystemZ Long Branch"
;
}
</s>


<s> static bool aarch64_could_trap_p ( aarch64_simd_builtin_datum * d ) { unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY | FLAG_WRITE_MEMORY ) ) return true ; return false ; } </s>

Return true if calls to the function could raise a signal .


<s>
SDValue
DCPU16TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
ROTL
:
return
LowerROT
(
Op
,
DAG
,
true
)
;
case
ISD
::
ROTR
:
return
LowerROT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerMUL_LOHI
(
Op
,
DAG
,
true
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerMUL_LOHI
(
Op
,
DAG
,
false
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void mips_init_libfuncs ( void ) { if ( TARGET_FIX_VR4120 ) { set_optab_libfunc ( sdiv_optab , SImode , "__vr4120_divsi3" ) ; set_optab_libfunc ( smod_optab , SImode , "__vr4120_modsi3" ) ; } if ( TARGET_MIPS16 && mips16_hard_float ) { set_optab_libfunc ( add_optab , SFmode , "__mips16_addsf3" ) ; set_optab_libfunc ( sub_optab , SFmode , "__mips16_subsf3" ) ; set_optab_libfunc ( smul_optab , SFmode , "__mips16_mulsf3" ) ; set_optab_libfunc ( sdiv_optab , SFmode , "__mips16_divsf3" ) ; set_optab_libfunc ( eq_optab , SFmode , "__mips16_eqsf2" ) ; set_optab_libfunc ( ne_optab , SFmode , "__mips16_nesf2" ) ; set_optab_libfunc ( gt_optab , SFmode , "__mips16_gtsf2" ) ; set_optab_libfunc ( ge_optab , SFmode , "__mips16_gesf2" ) ; set_optab_libfunc ( lt_optab , SFmode , "__mips16_ltsf2" ) ; set_optab_libfunc ( le_optab , SFmode , "__mips16_lesf2" ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , "__mips16_fix_truncsfsi" ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , "__mips16_floatsisf" ) ; if ( TARGET_DOUBLE_FLOAT ) { set_optab_libfunc ( add_optab , DFmode , "__mips16_adddf3" ) ; set_optab_libfunc ( sub_optab , DFmode , "__mips16_subdf3" ) ; set_optab_libfunc ( smul_optab , DFmode , "__mips16_muldf3" ) ; set_optab_libfunc ( sdiv_optab , DFmode , "__mips16_divdf3" ) ; set_optab_libfunc ( eq_optab , DFmode , "__mips16_eqdf2" ) ; set_optab_libfunc ( ne_optab , DFmode , "__mips16_nedf2" ) ; set_optab_libfunc ( gt_optab , DFmode , "__mips16_gtdf2" ) ; set_optab_libfunc ( ge_optab , DFmode , "__mips16_gedf2" ) ; set_optab_libfunc ( lt_optab , DFmode , "__mips16_ltdf2" ) ; set_optab_libfunc ( le_optab , DFmode , "__mips16_ledf2" ) ; set_conv_libfunc ( sext_optab , DFmode , SFmode , "__mips16_extendsfdf2" ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , "__mips16_truncdfsf2" ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , "__mips16_fix_truncdfsi" ) ; set_conv_libfunc ( sfloat_optab , DFmode , SImode , "__mips16_floatsidf" ) ; } } else gofast_maybe_init_libfuncs ( ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool NEONPreAllocPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= PreAllocNEONRegisters ( MBB ) ; } return Modified ; } </s>


<s> static rtx_insn * rs6000_emit_savres_rtx ( rs6000_stack_t * info , rtx frame_reg_rtx , int save_area_offset , int lr_offset , machine_mode reg_mode , int sel ) { int i ; int offset , start_reg , end_reg , n_regs , use_reg ; int reg_size = GET_MODE_SIZE ( reg_mode ) ; rtx sym ; rtvec p ; rtx par ; rtx_insn * insn ; offset = 0 ; start_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save : - 1 ) ; end_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? 32 : ( sel & SAVRES_REG ) == SAVRES_FPR ? 64 : ( sel & SAVRES_REG ) == SAVRES_VR ? LAST_ALTIVEC_REGNO + 1 : - 1 ) ; n_regs = end_reg - start_reg ; p = rtvec_alloc ( 3 + ( ( sel & SAVRES_LR ) ? 1 : 0 ) + ( ( sel & SAVRES_REG ) == SAVRES_VR ? 1 : 0 ) + n_regs ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , offset ++ ) = ret_rtx ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , 0 ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = 0 ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != 0 ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , 0 ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) { insn = emit_jump_insn ( par ) ; JUMP_LABEL ( insn ) = ret_rtx ; } else insn = emit_insn ( par ) ; return insn ; } </s>

Construct a parallel rtx describing the effect of a call to an out-of-line register save/restore routine , and emit the insn or jump_insn as appropriate .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s>
static
int
getMemScale
(
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
STRBBui
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
STRHHui
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s> hashval_t toc_hasher :: hash ( toc_hash_struct * thc ) { return rs6000_hash_constant ( thc -> key ) ^ thc -> key_mode ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static rtx rs6000_darwin64_record_arg ( CUMULATIVE_ARGS * orig_cum , tree type , int named , bool retval ) { rtx rvec [ FIRST_PSEUDO_REGISTER ] ; int k = 1 , kbase = 1 ; HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; CUMULATIVE_ARGS copy_cum = * orig_cum ; CUMULATIVE_ARGS * cum = & copy_cum ; if ( ! retval && TYPE_ALIGN ( type ) >= 2 * BITS_PER_WORD && ( cum -> words % 2 ) != 0 ) cum -> words ++ ; cum -> intoffset = 0 ; cum -> use_stack = 0 ; cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , 0 , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = 0 ; rvec [ 0 ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } if ( k > 1 || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( k - kbase , & rvec [ kbase ] ) ) ; else return NULL_RTX ; } </s>

For the darwin64 ABI , we want to construct a PARALLEL consisting of the register ( s ) to be used for each field and subfield of a struct being passed by value , along with the offset of where the register 's value may be found in the block . FP fields go in FP register , vector fields go in vector registers , and everything else goes in int registers , packed as in memory . This code is also used for function return values . RETVAL indicates whether this is the case . Much of this is taken from the SPARC V9 port , which has a similar calling convention .


<s> bool X86PassConfig :: addPreRegAlloc ( ) { PM . add ( createX86MaxStackAlignmentHeuristicPass ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
void
CAHPAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
if
(
!
Value
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
return
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void ix86_emit_i387_asinh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx cst1 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_mulxf3 ( e1 , op1 , op1 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , cst1 ) ) ; emit_insn ( gen_sqrtxf2 ( e2 , e2 ) ) ; emit_insn ( gen_addxf3 ( e2 , e2 , cst1 ) ) ; emit_insn ( gen_divxf3 ( e1 , e1 , e2 ) ) ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , op1 ) ) ; emit_insn ( gen_addxf3 ( e1 , e1 , e2 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; emit_move_insn ( op0 , e2 ) ; } </s>

Output code to perform an asinh XFmode calculation .


<s> bool ARMPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Constant Islands"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86FastPreTileConfig :: runOnMachineFunction ( MachineFunction & MFunc ) { MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; ST = & MFunc . getSubtarget < X86Subtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; X86FI = MFunc . getInfo < X86MachineFunctionInfo > ( ) ; MFI = & MFunc . getFrameInfo ( ) ; TRI = ST -> getRegisterInfo ( ) ; CfgSS = - 1 ; unsigned NumVirtRegs = MRI -> getNumVirtRegs ( ) ; bool HasVirtTileReg = false ; for ( unsigned I = 0 , E = NumVirtRegs ; I != E ; ++ I ) { Register VirtReg = Register :: index2VirtReg ( I ) ; if ( MRI -> getRegClass ( VirtReg ) -> getID ( ) == X86 :: TILERegClassID ) { HasVirtTileReg = true ; break ; } } if ( ! HasVirtTileReg ) return false ; StackSlotForVirtReg . resize ( NumVirtRegs ) ; MayLiveAcrossBlocks . clear ( ) ; MayLiveAcrossBlocks . resize ( NumVirtRegs * 3 ) ; bool Change = false ; assert ( MRI -> isSSA ( ) ) ; for ( MachineBasicBlock & MBB : MFunc ) canonicalizePHIs ( MBB ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( MF ) ; for ( MachineBasicBlock * MBB : RPOT ) { convertPHIs ( * MBB ) ; Change |= configBasicBlock ( * MBB ) ; } if ( Change ) InitializeTileConfigStackSpace ( ) ; StackSlotForVirtReg . clear ( ) ; return Change ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx ix86_broadcast_from_constant ( machine_mode mode , rtx op ) { int nunits = GET_MODE_NUNITS ( mode ) ; if ( nunits < 2 ) return nullptr ; if ( ! TARGET_INTER_UNIT_MOVES_TO_VEC && INTEGRAL_MODE_P ( mode ) ) return nullptr ; if ( ! ( TARGET_AVX2 || ( TARGET_AVX && ( GET_MODE_INNER ( mode ) == SImode || GET_MODE_INNER ( mode ) == DImode ) ) || FLOAT_MODE_P ( mode ) ) || standard_sse_constant_p ( op , mode ) ) return nullptr ; if ( GET_MODE_INNER ( mode ) == DImode && ! TARGET_64BIT && ( ! TARGET_AVX512F || ( GET_MODE_SIZE ( mode ) < 64 && ! TARGET_AVX512VL ) ) ) return nullptr ; if ( GET_MODE_INNER ( mode ) == TImode ) return nullptr ; rtx constant = get_pool_constant ( XEXP ( op , 0 ) ) ; if ( GET_CODE ( constant ) != CONST_VECTOR ) return nullptr ; if ( GET_MODE ( constant ) != mode ) { constant = simplify_subreg ( mode , constant , GET_MODE ( constant ) , 0 ) ; if ( constant == nullptr || GET_CODE ( constant ) != CONST_VECTOR ) return nullptr ; } rtx first = XVECEXP ( constant , 0 , 0 ) ; for ( int i = 1 ; i < nunits ; ++ i ) { rtx tmp = XVECEXP ( constant , 0 , i ) ; if ( ! rtx_equal_p ( tmp , first ) ) return nullptr ; } return first ; } </s>

OP is a memref of CONST_VECTOR , return scalar constant mem if CONST_VECTOR is a vec_duplicate , else return NULL .


<s> virtual const SparcSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"invalid feature modifier in %<-mcpu=%s%>"

Validate a command-line -mcpu option . Parse the cpu and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results if they are valid in RES and ISA_FLAGS . Return whether the option is valid .


<s>
static
bool
symbian_class_needs_attribute_p
(
tree
ctype
,
const
char
*
attribute_name
)
{
VEC
(
tree
,
gc
)
*
method_vec
;
method_vec
=
CLASSTYPE_METHOD_VEC
(
ctype
)
;
if
(
TYPE_POLYMORPHIC_P
(
ctype
)
&&
method_vec
&&
lookup_attribute
(
attribute_name
,
DECL_ATTRIBUTES
(
VEC_index
(
tree
,
method_vec
,
0
)
)
)
)
return
true
;
if
(
TREE_CODE
(
ctype
)
==
RECORD_TYPE
)
{
unsigned
int
len
;
len
=
method_vec
VEC_length
(
tree
,
method_vec
)
:
0
;
for
(
;
len
;
)
{
tree
member
=
VEC_index
(
tree
,
method_vec
,
len
)
;
if
(
!
member
)
continue
;
for
(
member
=
OVL_CURRENT
(
member
)
;
member
;
member
=
OVL_NEXT
(
member
)
)
{
if
(
TREE_CODE
(
member
)
!=
FUNCTION_DECL
)
continue
;
if
(
DECL_PURE_VIRTUAL_P
(
member
)
)
continue
;
if
(
!
DECL_VIRTUAL_P
(
member
)
)
continue
;
if
(
lookup_attribute
(
attribute_name
,
DECL_ATTRIBUTES
(
member
)
)
)
{
print_node_brief
(
stderr
,
""
,
ctype
,
0
)
;
fprintf
(
stderr
,
" inherits %s because"
,
attribute_name
)
;
print_node_brief
(
stderr
,
""
,
member
,
0
)
;
fprintf
(
stderr
,
" has it.\n"
)
;
return
true
;
}
}
}
}
print_node_brief
(
stderr
,
""
,
ctype
,
0
)
;
fprintf
(
stderr
,
" does not inherit %s\n"
,
attribute_name
)
;
return
false
;
}
</s>

Decide if a class needs to have an attribute because one of its member functions has the attribute .


<s> MCSection * DLXTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void ix86_expand_trunc ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xi , TWO52 , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xi = gen_reg_rtx ( int_mode_for_mode ( mode ) . require ( ) ) ; expand_fix ( xi , res , 0 ) ; expand_float ( xa , xi , 0 ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; emit_move_insn ( res , xa ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing trunc from OPERAND1 storing into OPERAND0 .


<s> unsigned AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { unsigned Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1


The label list for the current page freed by linking the list onto the free label element chain .


<s> static rtx add_constant ( rtx x , enum machine_mode mode , rtx last_value ) { int i ; rtx lab , new , ref , newref ; for ( i = 0 ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , 3 ) != XINT ( pool_vector [ i ] . value , 3 ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new = 0 ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - 1 ] . value ) ) { new = gen_label_rtx ( ) ; LABEL_REFS ( new ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new ; } if ( lab && pool_window_label ) { newref = gen_rtx_LABEL_REF ( VOIDmode , pool_window_label ) ; ref = pool_vector [ pool_window_last ] . wend ; LABEL_NEXTREF ( newref ) = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new ) pool_window_label = new ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - 1 ] . value ) ) { lab = 0 ; pool_vector [ pool_size - 1 ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL_RTX ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == 0 ) ; if ( lab && pool_window_label ) { newref = gen_rtx_LABEL_REF ( VOIDmode , pool_window_label ) ; ref = pool_vector [ pool_window_last ] . wend ; LABEL_NEXTREF ( newref ) = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size ; pool_size ++ ; return lab ; } </s>

Add a constant to the pool and return its label .


<s> void SICInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDR = SIC :: ADD ; unsigned SUBR = SIC :: SUB ; unsigned LDi = SIC :: LDi ; unsigned LDi4 = SIC :: LDi4 ; unsigned LDiL = SIC :: LDiL ; unsigned T = SIC :: T ; if ( isUInt < 20 > ( Amount ) ) { if ( isUInt < 12 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( LDi ) , T ) . addImm ( Amount ) ; } else { BuildMI ( MBB , I , DL , get ( LDi4 ) , T ) . addImm ( Amount ) ; } BuildMI ( MBB , I , DL , get ( ADDR ) , SP ) . addReg ( SP ) . addReg ( T ) ; } else if ( isUInt < 20 > ( - Amount ) ) { if ( isUInt < 12 > ( - Amount ) ) { BuildMI ( MBB , I , DL , get ( LDi ) , T ) . addImm ( - Amount ) ; } else { BuildMI ( MBB , I , DL , get ( LDi4 ) , T ) . addImm ( - Amount ) ; } BuildMI ( MBB , I , DL , get ( SUBR ) , SP ) . addReg ( SP ) . addReg ( T ) ; } else { BuildMI ( MBB , I , DL , get ( LDiL ) , T ) . addImm ( Amount ) ; BuildMI ( MBB , I , DL , get ( ADDR ) , SP ) . addReg ( SP ) . addReg ( T ) ; } } </s>


<s> bool AArch64FastISel :: optimizeSelect ( const SelectInst * SI ) { if ( ! SI -> getType ( ) -> isIntegerTy ( 1 ) ) return false ; const Value * Src1Val , * Src2Val ; unsigned Opc = 0 ; bool NeedExtraOp = false ; if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getTrueValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getFalseValue ( ) ; Opc = AArch64 :: ORRWrr ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getFalseValue ( ) ; Src2Val = SI -> getCondition ( ) ; Opc = AArch64 :: BICWrr ; } } else if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getFalseValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ORRWrr ; NeedExtraOp = true ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ANDWrr ; } } if ( ! Opc ) return false ; unsigned Src1Reg = getRegForValue ( Src1Val ) ; if ( ! Src1Reg ) return false ; unsigned Src2Reg = getRegForValue ( Src2Val ) ; if ( ! Src2Reg ) return false ; if ( NeedExtraOp ) Src1Reg = emitLogicalOp_ri ( ISD :: XOR , MVT :: i32 , Src1Reg , 1 ) ; unsigned ResultReg = fastEmitInst_rr ( Opc , & AArch64 :: GPR32RegClass , Src1Reg , Src2Reg ) ; updateValueMap ( SI , ResultReg ) ; return true ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> bool supportSwiftError ( ) const override { return true ; } </s>

Return true if the target supports swifterror attribute .


"preferPredicateOverEpilogue: not a single block "

"preferPredicateOverEpilogue: hardware-loop is not "

Query the target whether it would be prefered to create a predicated vector loop , which can avoid the need to emit a scalar epilogue loop .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAArch64WinCOFFObjectWriter ( OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool X86TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == MVT :: f32 ) return X86ScalarSSEf32 ; else if ( VT == MVT :: f64 ) return X86ScalarSSEf64 ; return true ; } </s>

Returns true if it 's safe to use load / store of the specified type to expand memcpy / memset inline .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MMI
=
&
getAnalysis
<
MachineModuleInfo
>
(
)
;
MCE
.
setModuleInfo
(
MMI
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
NumEmitted
++
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>


<s> Relocator :: Result unsupported ( Relocation & pReloc , AArch64Relocator & pParent ) { return Relocator :: Unsupported ; } </s>


<s> static int loongarch_symbol_insns ( enum loongarch_symbol_type type , machine_mode mode ) { switch ( type ) { case SYMBOL_GOT_DISP : if ( mode != MAX_MACHINE_MODE ) return 0 ; return 3 ; case SYMBOL_TLSGD : case SYMBOL_TLSLDM : return 1 ; case SYMBOL_TLS : return 0 ; } gcc_unreachable ( ) ; } </s>

Returns the number of instructions necessary to reference a symbol .


<s> bool ThumbRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { if ( MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ) { return false ; } return true ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> static rtx pa_trampoline_adjust_address ( rtx addr ) { if ( ! TARGET_64BIT ) addr = memory_address ( Pmode , plus_constant ( Pmode , addr , 46 ) ) ; return addr ; } </s>

Perform any machine-specific adjustment in the address of the trampoline . ADDR contains the address that was passed to pa_trampoline_init . Adjust the trampoline address to point to the plabel at offset 44 .


<s> void X86TTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { if ( ! UsePartialUnrolling ) return ; unsigned MaxOps ; if ( PartialUnrollingThreshold . getNumOccurrences ( ) > 0 ) { MaxOps = PartialUnrollingThreshold ; } else if ( ST -> isAtom ( ) ) { MaxOps = 10 ; } else if ( ST -> hasFSGSBase ( ) && ST -> hasXOP ( ) ) { MaxOps = 40 ; } else if ( ST -> hasFMA4 ( ) ) { return ; } else if ( ST -> hasAVX ( ) || ST -> hasSSE42 ( ) ) { MaxOps = 28 ; } else if ( ST -> hasSSSE3 ( ) ) { MaxOps = 18 ; } else { return ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , E = L -> block_end ( ) ; I != E ; ++ I ) { BasicBlock * BB = * I ; for ( BasicBlock :: iterator J = BB -> begin ( ) , JE = BB -> end ( ) ; J != JE ; ++ J ) if ( isa < CallInst > ( J ) || isa < InvokeInst > ( J ) ) { ImmutableCallSite CS ( J ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } } UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP . PartialOptSizeThreshold = MaxOps ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static section * pa_select_section ( tree exp , int reloc , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( TREE_CODE ( exp ) == VAR_DECL && TREE_READONLY ( exp ) && ! TREE_THIS_VOLATILE ( exp ) && DECL_INITIAL ( exp ) && ( DECL_INITIAL ( exp ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( exp ) ) ) && ! ( reloc & pa_reloc_rw_mask ( ) ) ) { if ( TARGET_SOM && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) return som_one_only_readonly_data_section ; else return readonly_data_section ; } else if ( CONSTANT_CLASS_P ( exp ) && ! ( reloc & pa_reloc_rw_mask ( ) ) ) return readonly_data_section ; else if ( TARGET_SOM && TREE_CODE ( exp ) == VAR_DECL && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) return som_one_only_data_section ; else return data_section ; } </s>

On hpux10 , the linker will give an error if we have a reference in the read-only data section to a symbol defined in a shared library . Therefore , expressions that might require a reloc can not be placed in the read-only data section .


<s> InstructionCost AArch64TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( 1 ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; MemOpCost *= getSVEGatherScatterOverhead ( Opcode ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF ) ; } </s>

Calculate the cost of Gather / Scatter operation .


"Virtual function multiversioning not supported"

Generate the dispatching code body to dispatch multi-versioned function DECL . The target hook is called to process the `` target '' attributes and provide the code to dispatch the right function at run-time . NODE points to the dispatcher decl whose body will be created .


<s> const ARMBaseRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> uint32_t generateCompactUnwindEncoding ( ArrayRef < MCCFIInstruction > Instrs ) const override { return generateCompactUnwindEncodingImpl ( Instrs ) ; } </s>

Generate compact unwind encoding for the function based on the CFI instructions .


<s> static bool aarch64_fold_builtin_lane_check ( tree arg0 , tree arg1 , tree arg2 ) { if ( TREE_CODE ( arg0 ) != INTEGER_CST ) return false ; if ( TREE_CODE ( arg1 ) != INTEGER_CST ) return false ; if ( TREE_CODE ( arg2 ) != INTEGER_CST ) return false ; auto totalsize = wi :: to_widest ( arg0 ) ; auto elementsize = wi :: to_widest ( arg1 ) ; if ( totalsize == 0 || elementsize == 0 ) return false ; auto lane = wi :: to_widest ( arg2 ) ; auto high = wi :: udiv_trunc ( totalsize , elementsize ) ; return wi :: ltu_p ( lane , high ) ; } </s>

Return true if the lane check can be removed as there is no error going to be emitted .


<s> void x86_elf_aligned_common ( FILE * file , const char * name , unsigned HOST_WIDE_INT size , int align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) fputs ( "\t.largecomm\t" , file ) ; else fputs ( COMMON_ASM_OP , file ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

This says how to output assembler code to declare an uninitialized external linkage data object . For medium model x86-64 we need to use .largecomm opcode for large objects .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; if ( Changed ) F . getRegInfo ( ) . invalidateLiveness ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool ix86_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_WIDE_INT : case CONST_DOUBLE : case CONST_VECTOR : return false ; default : break ; } return ! ix86_legitimate_constant_p ( mode , x ) ; } </s>

Determine if it 's legal to put X into the constant pool . This is not possible for the address of thread-local symbols , which is checked above .


<s> void PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = Subtarget . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> static const char * mips_sync_insn2_template ( enum attr_sync_insn2 type ) { switch ( type ) { case SYNC_INSN2_NOP : gcc_unreachable ( ) ; case SYNC_INSN2_AND : return "and\t%0,%1,%z2" ; case SYNC_INSN2_XOR : return "xor\t%0,%1,%z2" ; case SYNC_INSN2_NOT : return "nor\t%0,%1,%." ; } gcc_unreachable ( ) ; } </s>

Return the asm template associated with sync_insn2 value TYPE .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static bool has_inlined_assembly ( function * fn ) { basic_block bb ; gimple_stmt_iterator gsi ; if ( fn -> cfg == NULL ) return true ; FOR_EACH_BB_FN ( bb , fn ) for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) if ( gimple_code ( gsi_stmt ( gsi ) ) == GIMPLE_ASM ) return true ; return false ; } </s>

Return true if this function has inline assembly code or if we can not be certain that it does not . False if we know that there is no inline assembly .


<s> unsigned F2003fRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return F2003f :: F5 ; } </s>


<s> unsigned DLXInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TrueBlock , MachineBasicBlock * FalseBlock , ArrayRef < MachineOperand > Condition , const DebugLoc & DL , int * BytesAdded ) const { return 1 ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> static rtx safe_vector_operand ( rtx x , enum machine_mode mode ) { if ( x == const0_rtx ) x = CONST0_RTX ( mode ) ; return x ; } </s>

Errors in the source file can cause expand_expr to return const0_rtx where we expect a vector . To avoid crashing , use one of the vector clear instructions .


<s> static void sparc_init_pic_reg ( void ) { edge entry_edge ; rtx_insn * seq ; if ( ! crtl -> uses_pic_offset_table ) return ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , global_offset_table_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } </s>


<s> void XNCMRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { llvm_unreachable ( 0 ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
)
const
{
unsigned
NumBytes
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
TargetSize
/
8
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static int aarch64_sched_adjust_priority ( rtx_insn * insn , int priority ) { rtx x = PATTERN ( insn ) ; if ( GET_CODE ( x ) == SET ) { x = SET_SRC ( x ) ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_SHA1H ) return priority + 10 ; } return priority ; } </s>

Implement the TARGET_SCHED_ADJUST_PRIORITY hook . Adjust priority of sha1h instructions so they are scheduled before other SHA1 instructions .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>


<s> bool AArch64TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { if ( Immed < 0 ) Immed *= - 1 ; return isLegalAddImmediate ( Immed ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


"PPC pre-emit peephole: erasing instruction: "


<s> enum reg_class aarch64_regno_regclass ( unsigned regno ) { if ( GP_REGNUM_P ( regno ) ) return GENERAL_REGS ; if ( regno == SP_REGNUM ) return STACK_REG ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return ( FP_LO8_REGNUM_P ( regno ) ? FP_LO8_REGS : FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ) ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno ) ? PR_LO_REGS : PR_HI_REGS ; if ( regno == FFR_REGNUM || regno == FFRT_REGNUM ) return FFR_REGS ; return NO_REGS ; } </s>


<s> bool X86InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; unsigned SlotSize = is64Bit ? 8 : 4 ; MachineFunction & MF = * MBB . getParent ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FI -> setCalleeSavedFrameSize ( CSI . size ( ) * SlotSize ) ; unsigned Opc = is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , false , false , true ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static rtx sparc_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx orig_x = x ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 1 ) , force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , force_operand ( XEXP ( x , 1 ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , force_operand ( XEXP ( x , 0 ) , NULL_RTX ) , XEXP ( x , 1 ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , force_operand ( XEXP ( x , 1 ) , NULL_RTX ) ) ; if ( x != orig_x && sparc_legitimate_address_p ( mode , x , FALSE ) ) return x ; if ( sparc_tls_referenced_p ( x ) ) x = sparc_legitimize_tls_address ( x ) ; else if ( flag_pic ) x = sparc_legitimize_pic_address ( x , NULL_RTX ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 1 ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , copy_to_mode_reg ( Pmode , XEXP ( x , 1 ) ) ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , 0 ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , 1 ) , copy_to_mode_reg ( Pmode , XEXP ( x , 0 ) ) ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) x = copy_to_suggested_reg ( x , NULL_RTX , Pmode ) ; return x ; } </s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X . On SPARC , change REG+N into REG+REG , and REG+ ( X * Y ) into REG+REG .


<s> static unsigned int mips_build_lower ( struct mips_integer_op * codes , unsigned HOST_WIDE_INT value ) { unsigned HOST_WIDE_INT high ; unsigned int i ; high = value & ~ ( unsigned HOST_WIDE_INT ) 0xffff ; if ( ! LUI_OPERAND ( high ) && ( value & 0x18000 ) == 0x18000 ) { i = mips_build_integer ( codes , CONST_HIGH_PART ( value ) ) ; codes [ i ] . code = PLUS ; codes [ i ] . value = CONST_LOW_PART ( value ) ; } else { i = mips_build_integer ( codes , high ) ; codes [ i ] . code = IOR ; codes [ i ] . value = value & 0xffff ; } return i + 1 ; } </s>

As for mips_build_shift , but assume that the final action will be an IOR or PLUS operation .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( ( TSFlags & X86II :: NOTRACK ) || ( Flags & X86 :: IP_HAS_NOTRACK ) ) OS << "\tnotrack\t" ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
static
void
copy_fp_args
(
rtx
insn
)
{
rtx
link
;
rtx
xoperands
[
2
]
;
for
(
link
=
CALL_INSN_FUNCTION_USAGE
(
insn
)
;
link
;
link
=
XEXP
(
link
,
1
)
)
{
int
arg_mode
,
regno
;
rtx
use
=
XEXP
(
link
,
0
)
;
if
(
!
(
GET_CODE
(
use
)
==
USE
&&
GET_CODE
(
XEXP
(
use
,
0
)
)
==
REG
&&
FUNCTION_ARG_REGNO_P
(
REGNO
(
XEXP
(
use
,
0
)
)
)
)
)
continue
;
arg_mode
=
GET_MODE
(
XEXP
(
use
,
0
)
)
;
regno
=
REGNO
(
XEXP
(
use
,
0
)
)
;
if
(
regno
>=
32
&&
regno
<=
39
)
{
if
(
arg_mode
==
SFmode
)
{
xoperands
[
0
]
=
XEXP
(
use
,
0
)
;
xoperands
[
1
]
=
gen_rtx_REG
(
SImode
,
26
(
regno
32
)
/
2
)
;
output_asm_insn
(
"{fstws|fstw} %0,-16(%%sr0,%%r30)"
,
xoperands
)
;
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
)
;
}
else
{
xoperands
[
0
]
=
XEXP
(
use
,
0
)
;
xoperands
[
1
]
=
gen_rtx_REG
(
DImode
,
25
(
regno
34
)
/
2
)
;
output_asm_insn
(
"{fstds|fstd} %0,-16(%%sr0,%%r30)"
,
xoperands
)
;
output_asm_insn
(
"ldw -12(%%sr0,%%r30),%R1"
,
xoperands
)
;
output_asm_insn
(
"ldw -16(%%sr0,%%r30),%1"
,
xoperands
)
;
}
}
}
}
</s>

Copy any FP arguments in INSN into integer registers .


<s> MachineBasicBlock :: iterator X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : 0 ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( isDestroy && blockEndIsUnreachable ( MBB , I ) ) return I ; if ( ! reserveCallFrame ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && MF . needsFrameMoves ( ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return I ; } if ( InternalAmt ) { MachineBasicBlock :: iterator CI = I ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( CI != B && ! std :: prev ( CI ) -> isCall ( ) ) -- CI ; BuildStackAdjustment ( MBB , CI , DL , - InternalAmt , false ) ; } return I ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> CSKYSubtarget & CSKYSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPUName , StringRef TuneCPUName , StringRef FS ) { if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; UseHardFloat = false ; UseHardFloatABI = false ; HasFPUv2SingleFloat = false ; HasFPUv2DoubleFloat = false ; HasFPUv3HalfWord = false ; HasFPUv3HalfFloat = false ; HasFPUv3SingleFloat = false ; HasFPUv3DoubleFloat = false ; HasFdivdu = false ; HasFLOATE1 = false ; HasFLOAT1E2 = false ; HasFLOAT1E3 = false ; HasFLOAT3E4 = false ; HasFLOAT7E60 = false ; HasExtendLrw = false ; HasBTST16 = false ; HasTrust = false ; HasJAVA = false ; HasCache = false ; HasNVIC = false ; HasDSP = false ; HasDSP1E2 = false ; HasDSPE60 = false ; HasDSPV2 = false ; HasDSP_Silan = false ; HasDoloop = false ; HasHardwareDivide = false ; HasHighRegisters = false ; HasVDSPV2 = false ; HasVDSP2E3 = false ; HasVDSP2E60F = false ; ReadTPHard = false ; HasVDSPV1_128 = false ; UseCCRT = false ; DumpConstPool = false ; EnableInterruptAttribute = false ; HasPushPop = false ; HasSTM = false ; SmartMode = false ; EnableStackSize = false ; HasE1 = false ; HasE2 = false ; Has2E3 = false ; HasMP = false ; Has3E3r1 = false ; Has3r1E3r2 = false ; Has3r2E3r3 = false ; Has3E7 = false ; HasMP1E2 = false ; Has7E10 = false ; Has10E60 = false ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned AArch64FrameLowering :: getWinEHParentFrameOffset ( const MachineFunction & MF ) const { return 0 ; } </s>

The parent frame offset ( aka dispFrame ) is only used on X86_64 to retrieve the parent 's frame pointer .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>


<s> HOST_WIDE_INT const_vector_elt_as_int ( rtx op , unsigned int elt ) { rtx tmp ; gcc_assert ( GET_MODE ( op ) != V2DImode && GET_MODE ( op ) != V2DFmode ) ; tmp = CONST_VECTOR_ELT ( op , elt ) ; if ( GET_MODE ( op ) == V4SFmode ) tmp = gen_lowpart ( SImode , tmp ) ; return INTVAL ( tmp ) ; } </s>

Interpret element ELT of the CONST_VECTOR OP as an integer value . If the mode of OP is MODE_VECTOR_INT , this simply returns the corresponding element of the vector , but for V4SFmode , the corresponding `` float '' is interpreted as an SImode integer .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>


<s> bool ix86_bd_has_dispatch ( rtx_insn * insn , int action ) { if ( ( TARGET_CPU_P ( BDVER1 ) || TARGET_CPU_P ( BDVER2 ) || TARGET_CPU_P ( BDVER3 ) || TARGET_CPU_P ( BDVER4 ) ) && flag_dispatch_scheduler ) switch ( action ) { default : return false ; case IS_DISPATCH_ON : return true ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ; } return false ; } </s>

Return TRUE if Dispatch Scheduling is supported .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const ARMSubtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < ARMSubtarget > ( ) ; if ( ! Subtarget . isAAPCS_ABI ( ) || Subtarget . isTargetMachO ( ) || Subtarget . isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * Subtarget . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> static void assign_csky_minipool_offsets ( Mfix * barrier ) { HOST_WIDE_INT offset = 0 ; Mnode * mp ; minipool_barrier = barrier ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { mp -> offset = offset ; if ( mp -> refcount > 0 ) offset += mp -> fix_size ; } } </s>

Fill in the offsets for minipool entries .


<s> bool ARMFrameInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> rtx standard_80387_constant_rtx ( int idx ) { int i ; if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; switch ( idx ) { case 3 : case 4 : case 5 : case 6 : case 7 : i = idx - 3 ; break ; default : gcc_unreachable ( ) ; } return CONST_DOUBLE_FROM_REAL_VALUE ( ext_80387_constants_table [ i ] , XFmode ) ; } </s>

Return the CONST_DOUBLE representing the 80387 constant that is loaded by the specified special instruction . The argument IDX matches the return value from standard_80387_constant_p .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> unsigned AArch64InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: STRWui : case AArch64 :: STRXui : case AArch64 :: STRBui : case AArch64 :: STRHui : case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static bool rs6000_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == PTImode || mode1 == OOmode || mode1 == XOmode || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode ) return mode1 == mode2 ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode1 ) ) return ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ; if ( GET_MODE_CLASS ( mode1 ) == MODE_CC ) return GET_MODE_CLASS ( mode2 ) == MODE_CC ; if ( GET_MODE_CLASS ( mode2 ) == MODE_CC ) return false ; return true ; } </s>

Implement TARGET_MODES_TIEABLE_P . PTImode can not tie with other modes because PTImode is restricted to even GPR registers , and TImode can go in any GPR as well as VSX registers ( PR 57744 ) . Similarly , do n't allow OOmode ( vector pair , restricted to even VSX registers ) or XOmode ( vector quad , restricted to FPR registers divisible by 4 ) to tie with other modes . Altivec/VSX vector tests were moved ahead of scalar float mode , so that IEEE 128-bit floating point on VSX systems ties with other vectors .


<s> virtual const Cpu0RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool runOnModule ( Module & M ) override { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; if ( skipModule ( M ) ) return false ; bool Changed = false ; PromotionCacheTy PromotionCache ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF , PromotionCache ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static int mips_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ) { struct mips_arg_info info ; mips_arg_info ( cum , mode , type , named , & info ) ; return info . stack_words > 0 ? info . reg_words * UNITS_PER_WORD : 0 ; } </s>


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; unsigned FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextMap CallSeqMap ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext & Context = CallSeqMap [ I ] ; collectCallInfo ( MF , * BB , I , Context ) ; } if ( ! isProfitable ( MF , CallSeqMap ) ) return false ; for ( auto CC : CallSeqMap ) if ( CC . second . UsePush ) Changed |= adjustCallSequence ( MF , CC . first , CC . second ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


"use_as_extended_reg: converting non-extending mem load in "

"use_as_extended_reg: dest reg %d of extending insn %d is "

Given a reg that is known to be sign or zero extended at some insn , take the appropriate measures so that the extended value can be used as a reg at the specified insn and return the resulting reg rtx .


<s> int aarch64_simd_attr_length_rglist ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) . to_constant ( ) / UNITS_PER_VREG ) * 4 ; } </s>

Compute and return the length of aarch64_simd_reglist < mode > , where < mode > is one of VSTRUCT modes : OI , CI , EI , or XI .


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = KnownOne . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; break ; case ARMISD :: CMOV : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero , KnownOne , Depth + 1 ) ; if ( KnownZero == 0 && KnownOne == 0 ) return ; APInt KnownZeroRHS , KnownOneRHS ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZeroRHS , KnownOneRHS , Depth + 1 ) ; KnownZero &= KnownZeroRHS ; KnownOne &= KnownOneRHS ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarType ( ) . getSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
assert
(
MFI
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
if
(
RC
->
getID
(
)
==
X86
::
TILERegClassID
)
{
unsigned
Opc
=
X86
::
TILESTORED
;
MachineRegisterInfo
&
RegInfo
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
Register
VirtReg
=
RegInfo
.
createVirtualRegister
(
&
X86
::
GR64_NOSPRegClass
)
;
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
X86
::
MOV64ri
)
,
VirtReg
)
.
addImm
(
64
)
;
MachineInstr
*
NewMI
=
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
MachineOperand
&
MO
=
NewMI
->
getOperand
(
2
)
;
MO
.
setReg
(
VirtReg
)
;
MO
.
setIsKill
(
true
)
;
}
else
{
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlign
(
)
>=
Alignment
)
||
(
RI
.
canRealignStack
(
MF
)
&&
!
MFI
.
isFixedObjectIndex
(
FrameIdx
)
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static unsigned feature_count ( const arm_feature_set * set ) { return ( bit_count ( ARM_FSET_CPU1 ( * set ) ) + bit_count ( ARM_FSET_CPU2 ( * set ) ) ) ; } </s>

Return the number of features in feature-set SET .