<s> int X86FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) FrameReg = RegInfo -> getStackRegister ( ) ; else FrameReg = RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF , FI ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( const MipsTargetMachine & TM , const MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return createMips16TargetLowering ( TM , STI ) ; return createMipsSETargetLowering ( TM , STI ) ; } </s>


<s> void nds32_spilt_doubleword ( rtx * operands , bool load_p ) { int reg = load_p ? 0 : 1 ; int mem = load_p ? 1 : 0 ; rtx reg_rtx = load_p ? operands [ 0 ] : operands [ 1 ] ; rtx mem_rtx = load_p ? operands [ 1 ] : operands [ 0 ] ; rtx low_part [ 2 ] , high_part [ 2 ] ; rtx sub_mem = XEXP ( mem_rtx , 0 ) ; low_part [ reg ] = simplify_gen_subreg ( SImode , reg_rtx , GET_MODE ( reg_rtx ) , 0 ) ; high_part [ reg ] = simplify_gen_subreg ( SImode , reg_rtx , GET_MODE ( reg_rtx ) , 4 ) ; if ( GET_CODE ( sub_mem ) == POST_DEC ) { sub_mem = XEXP ( sub_mem , 0 ) ; low_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_MODIFY ( Pmode , sub_mem , gen_rtx_PLUS ( Pmode , sub_mem , GEN_INT ( 4 ) ) ) ) ; high_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_MODIFY ( Pmode , sub_mem , gen_rtx_PLUS ( Pmode , sub_mem , GEN_INT ( - 12 ) ) ) ) ; } else if ( GET_CODE ( sub_mem ) == POST_INC ) { sub_mem = XEXP ( sub_mem , 0 ) ; low_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( Pmode , sub_mem ) ) ; high_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( Pmode , sub_mem ) ) ; } else if ( GET_CODE ( sub_mem ) == POST_MODIFY ) { rtx post_mem = XEXP ( sub_mem , 0 ) ; rtx plus_op = XEXP ( sub_mem , 1 ) ; rtx post_val = XEXP ( plus_op , 1 ) ; low_part [ mem ] = gen_rtx_MEM ( SImode , gen_rtx_POST_MODIFY ( Pmode , post_mem , gen_rtx_PLUS ( Pmode , post_mem , post_val ) ) ) ; high_part [ mem ] = gen_rtx_MEM ( SImode , plus_constant ( Pmode , post_mem , 4 ) ) ; } else { low_part [ mem ] = adjust_address ( mem_rtx , SImode , 0 ) ; high_part [ mem ] = adjust_address ( mem_rtx , SImode , 4 ) ; } if ( ( load_p && reg_overlap_mentioned_p ( low_part [ 0 ] , high_part [ 1 ] ) ) || GET_CODE ( sub_mem ) == POST_MODIFY ) { operands [ 2 ] = high_part [ 0 ] ; operands [ 3 ] = high_part [ 1 ] ; operands [ 4 ] = low_part [ 0 ] ; operands [ 5 ] = low_part [ 1 ] ; } else { operands [ 2 ] = low_part [ 0 ] ; operands [ 3 ] = low_part [ 1 ] ; operands [ 4 ] = high_part [ 0 ] ; operands [ 5 ] = high_part [ 1 ] ; } } </s>

Spilt a doubleword instrucion to two single word instructions .


<s> bool OR1KPassConfig :: addPreEmitPass ( ) { addPass ( createOR1KDelaySlotFillerPass ( getOR1KTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> void arm_emit_fp16_const ( rtx c ) { REAL_VALUE_TYPE r ; long bits ; REAL_VALUE_FROM_CONST_DOUBLE ( r , c ) ; bits = real_to_target ( NULL , & r , HFmode ) ; if ( WORDS_BIG_ENDIAN ) assemble_zeros ( 2 ) ; assemble_integer ( GEN_INT ( bits ) , 2 , BITS_PER_WORD , 1 ) ; if ( ! WORDS_BIG_ENDIAN ) assemble_zeros ( 2 ) ; } </s>

Emit a fp16 constant appropriately padded to occupy a 4-byte word . HFmode constant pool entries are actually loaded with ldr .


<s> void MipsRegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { MachineInstr & MI = OpdMapper . getMI ( ) ; InstListTy NewInstrs ; MachineIRBuilder B ( MI ) ; MachineFunction * MF = MI . getMF ( ) ; MachineRegisterInfo & MRI = OpdMapper . getMRI ( ) ; const LegalizerInfo & LegInfo = * MF -> getSubtarget ( ) . getLegalizerInfo ( ) ; InstManager NewInstrObserver ( NewInstrs ) ; GISelObserverWrapper WrapperObserver ( & NewInstrObserver ) ; LegalizerHelper Helper ( * MF , WrapperObserver , B ) ; LegalizationArtifactCombiner ArtCombiner ( B , MF -> getRegInfo ( ) , LegInfo ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_PHI : case TargetOpcode :: G_SELECT : case TargetOpcode :: G_IMPLICIT_DEF : { Helper . narrowScalar ( MI , 0 , LLT :: scalar ( 32 ) ) ; while ( ! NewInstrs . empty ( ) ) { MachineInstr * NewMI = NewInstrs . pop_back_val ( ) ; if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES ) combineAwayG_UNMERGE_VALUES ( ArtCombiner , * NewMI ) ; else if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) continue ; else setRegBank ( * NewMI , MRI ) ; } return ; } case TargetOpcode :: G_UNMERGE_VALUES : combineAwayG_UNMERGE_VALUES ( ArtCombiner , MI ) ; return ; default : break ; } return applyDefaultMapping ( OpdMapper ) ; } </s>


<s> static unsigned int aarch64_sve_container_bits ( machine_mode mode ) { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; poly_uint64 vector_bits = ( vec_flags & ( VEC_PARTIAL | VEC_SVE_PRED ) ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ; return vector_element_size ( vector_bits , GET_MODE_NUNITS ( mode ) ) ; } </s>

MODE is some form of SVE vector mode . For data modes , return the number of vector register bits that each element of MODE occupies , such as 64 for both VNx2DImode and VNx2SImode ( where each 32-bit value is stored in a 64-bit container ) . For predicate modes , return the number of data bits controlled by each significant predicate bit .


<s> static bool arm_cxx_use_aeabi_atexit ( void ) { return TARGET_AAPCS_BASED ; } </s>

The EABI says __aeabi_atexit should be used to register static destructors .


<s> MachineBasicBlock :: iterator UPTFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == UPT :: ADJCALLSTACKUP || I -> getOpcode ( ) == UPT :: ADJCALLSTACKDOWN ) { return MBB . erase ( I ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

UPT UPT UPT::ADJCALLSTACKUP UPT::ADJCALLSTACKDOWN


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static void aarch64_destroy_cost_data ( void * data ) { delete static_cast < aarch64_vector_costs * > ( data ) ; } </s>


<s> static rtx altivec_expand_vec_ext_builtin ( tree exp , rtx target ) { machine_mode tmode , mode0 ; tree arg0 , arg1 ; rtx op0 ; rtx op1 ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; if ( TREE_CODE ( arg1 ) == INTEGER_CST ) ( void ) get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_extract ( target , op0 , op1 ) ; return target ; } </s>


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDR_P0_off : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return ARM :: P0 ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d8TPseudo : case ARM :: VLD1d16TPseudo : case ARM :: VLD1d32TPseudo : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d8QPseudo : case ARM :: VLD1d16QPseudo : case ARM :: VLD1d32QPseudo : case ARM :: VLD1d64QPseudo : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"MachineModuleInfo should always be available"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
const
MCExpr
*
SystemZMCInstLower
::
getExpr
(
const
MachineOperand
&
MO
,
MCSymbolRefExpr
::
VariantKind
Kind
)
const
{
const
MCSymbol
*
Symbol
;
bool
HasOffset
=
true
;
switch
(
MO
.
getType
(
)
)
{
case
MachineOperand
::
MO_MachineBasicBlock
:
Symbol
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
HasOffset
=
false
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
Symbol
=
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
Symbol
=
AsmPrinter
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
Symbol
=
AsmPrinter
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
;
HasOffset
=
false
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
Symbol
=
AsmPrinter
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
Symbol
=
AsmPrinter
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
break
;
default
:
llvm_unreachable
(
"unknown operand type"
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
Create
(
Symbol
,
Kind
,
Ctx
)
;
if
(
HasOffset
)
if
(
int64_t
Offset
=
MO
.
getOffset
(
)
)
{
const
MCExpr
*
OffsetExpr
=
MCConstantExpr
::
Create
(
Offset
,
Ctx
)
;
Expr
=
MCBinaryExpr
::
CreateAdd
(
Expr
,
OffsetExpr
,
Ctx
)
;
}
return
Expr
;
}
</s>

Implementation of the SCEVPredicate interface .


<s> void aarch64_sls_emit_blr_function_thunks ( FILE * out_file ) { if ( ! aarch64_harden_sls_blr_p ( ) ) return ; bool any_functions_emitted = false ; section * save_text_section = in_section ; switch_to_section ( function_section ( current_function_decl ) ) ; for ( int regnum = 0 ; regnum < 30 ; ++ regnum ) { rtx specu_label = cfun -> machine -> call_via [ regnum ] ; if ( specu_label == NULL ) continue ; targetm . asm_out . print_operand ( out_file , specu_label , 0 ) ; asm_fprintf ( out_file , ":\n" ) ; aarch64_sls_emit_function_stub ( out_file , regnum ) ; any_functions_emitted = true ; } if ( any_functions_emitted ) asm_fprintf ( out_file , "\t%s\n" , aarch64_sls_barrier ( true ) ) ; switch_to_section ( save_text_section ) ; } </s>

Emit all BLR stubs for this particular function . Here we emit all the BLR stubs needed for the current function . Since we emit these stubs in a consecutive block we know there will be no speculation gadgets between each stub , and hence we only emit a speculation barrier at the end of the stub sequences . This is called in the TARGET_ASM_FUNCTION_EPILOGUE hook .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


"InsertBranch must not be told to insert a fallthrough"

"CAHP branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( NeedsWinCFI ) std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; int FrameIdx ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlignment ( * RC ) ) ; FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; if ( hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) && Reg == AArch64 :: FP ) { FrameIdx = MFI . CreateStackObject ( 8 , Alignment , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel" "ppc-got" "ppc-opt-pcrel" "ppc-tlsgd" "ppc-tlsld" "ppc-tprel" "ppc-tlsgdm" "ppc-got-tlsgd-pcrel" "ppc-got-tlsld-pcrel" "ppc-got-tprel-pcrel"


<s> static section * mips_function_rodata_section ( tree decl , bool ) { if ( ! TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD ) return default_function_rodata_section ( decl , false ) ; if ( decl && DECL_SECTION_NAME ( decl ) ) { const char * name = DECL_SECTION_NAME ( decl ) ; if ( DECL_COMDAT_GROUP ( decl ) && strncmp ( name , ".gnu.linkonce.t." , 16 ) == 0 ) { char * rname = ASTRDUP ( name ) ; rname [ 14 ] = 'd' ; return get_section ( rname , SECTION_LINKONCE | SECTION_WRITE , decl ) ; } else if ( flag_function_sections && flag_data_sections && strncmp ( name , ".text." , 6 ) == 0 ) { char * rname = ASTRDUP ( name ) ; memcpy ( rname + 1 , "data" , 4 ) ; return get_section ( rname , SECTION_WRITE , decl ) ; } } return data_section ; } </s>

Implement TARGET_ASM_FUNCTION_RODATA_SECTION . The complication here is that , with the combination TARGET_ABICALLS & & ! TARGET_GPWORD , jump tables will use absolute addresses , and should therefore not be included in the read-only part of a DSO . Handle such cases by selecting a normal data section instead of a read-only one . The logic apes that in default_function_rodata_section .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) || ! Subtarget -> hasVFP2 ( ) ) return false ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + 1 , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static void emit_save_or_restore_local_in_regs ( rtx base , int offset , sorr_act_t action ) { if ( offset < - 4096 || offset + 16 * UNITS_PER_WORD > 4095 ) { base = emit_adjust_base_to_offset ( base , offset ) ; offset = 0 ; } emit_save_or_restore_regs ( 16 , 32 , base , offset , sparc_leaf_function_p , save_local_or_in_reg_p , action , SORR_ADVANCE ) ; } </s>

Emit code to save/restore call-saved local and in registers .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; auto IsFoldableRMW = [ ] ( SDValue Load , SDValue Op ) { if ( ! Op . hasOneUse ( ) ) return false ; SDNode * User = * Op -> use_begin ( ) ; if ( ! ISD :: isNormalStore ( User ) ) return false ; auto * Ld = cast < LoadSDNode > ( Load ) ; auto * St = cast < StoreSDNode > ( User ) ; return Ld -> getBasePtr ( ) == St -> getBasePtr ( ) ; } ; auto IsFoldableAtomicRMW = [ ] ( SDValue Load , SDValue Op ) { if ( ! Load . hasOneUse ( ) || Load . getOpcode ( ) != ISD :: ATOMIC_LOAD ) return false ; if ( ! Op . hasOneUse ( ) ) return false ; SDNode * User = * Op -> use_begin ( ) ; if ( User -> getOpcode ( ) != ISD :: ATOMIC_STORE ) return false ; auto * Ld = cast < AtomicSDNode > ( Load ) ; auto * St = cast < AtomicSDNode > ( User ) ; return Ld -> getBasePtr ( ) == St -> getBasePtr ( ) ; } ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : return false ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && IsFoldableRMW ( N0 , Op ) ) return false ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; LLVM_FALLTHROUGH ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( MayFoldLoad ( N1 ) && ( ! Commute || ! isa < ConstantSDNode > ( N0 ) || ( Op . getOpcode ( ) != ISD :: MUL && IsFoldableRMW ( N1 , Op ) ) ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ( Commute && ! isa < ConstantSDNode > ( N1 ) ) || ( Op . getOpcode ( ) != ISD :: MUL && IsFoldableRMW ( N0 , Op ) ) ) ) return false ; if ( IsFoldableAtomicRMW ( N0 , Op ) || ( Commute && IsFoldableAtomicRMW ( N1 , Op ) ) ) return false ; } } PVT = MVT :: i32 ; return true ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s>
bool
AArch64FrameLowering
::
hasFP
(
const
MachineFunction
&
MF
)
const
{
const
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterInfo
*
RegInfo
=
MF
.
getTarget
(
)
.
getRegisterInfo
(
)
;
assert
(
!
RegInfo
->
needsStackRealignment
(
MF
)
&&
"No stack realignment on AArch64!"
)
;
return
(
MFI
->
hasCalls
(
)
||
MFI
->
hasVarSizedObjects
(
)
||
MFI
->
isFrameAddressTaken
(
)
)
;
}
</s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void tryAddingPcLoadReferenceComment ( uint64_t Address , uint64_t Value , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; Dis -> tryAddingPcLoadReferenceComment ( Value , Address ) ; } </s>

Try to add a comment on the PC-relative load .


<s> tree aarch64_fold_builtin ( tree fndecl , int n_args ATTRIBUTE_UNUSED , tree * args , bool ignore ATTRIBUTE_UNUSED ) { int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; switch ( fcode ) { BUILTIN_VDQF ( UNOP , abs , 2 ) return fold_build1 ( ABS_EXPR , type , args [ 0 ] ) ; break ; VAR1 ( UNOP , floatv2si , 2 , v2sf ) VAR1 ( UNOP , floatv4si , 2 , v4sf ) VAR1 ( UNOP , floatv2di , 2 , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ 0 ] ) ; default : break ; } return NULL_TREE ; } </s>


<s> static bool arm_output_ttype ( rtx x ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( ! CONST_INT_P ( x ) ) fputs ( "(TARGET2)" , asm_out_file ) ; fputc ( '\n' , asm_out_file ) ; return TRUE ; } </s>

Output a reference from a function exception table to the type_info object X . The EABI specifies that the symbol should be relocated by an R_ARM_TARGET2 relocation .


<s> static char * find_target_compiler ( const char * name ) { bool found = false ; char * * paths = NULL ; unsigned n_paths , i ; char * target_compiler ; const char * collect_gcc = getenv ( "COLLECT_GCC" ) ; const char * gcc_path = dirname ( ASTRDUP ( collect_gcc ) ) ; const char * gcc_exec = basename ( ASTRDUP ( collect_gcc ) ) ; if ( strcmp ( gcc_exec , collect_gcc ) == 0 ) { target_compiler = XDUPVEC ( char , name , strlen ( name ) + 1 ) ; found = true ; goto out ; } target_compiler = concat ( gcc_path , "/" , name , NULL ) ; if ( access_check ( target_compiler , X_OK ) == 0 ) { found = true ; goto out ; } n_paths = parse_env_var ( getenv ( "COMPILER_PATH" ) , & paths ) ; for ( i = 0 ; i < n_paths ; i ++ ) { size_t len = strlen ( paths [ i ] ) + 1 + strlen ( name ) + 1 ; target_compiler = XRESIZEVEC ( char , target_compiler , len ) ; sprintf ( target_compiler , "%s/%s" , paths [ i ] , name ) ; if ( access_check ( target_compiler , X_OK ) == 0 ) { found = true ; break ; } } out : free_array_of_ptrs ( ( void * * ) paths , n_paths ) ; return found ? target_compiler : NULL ; } </s>

Find target compiler using a path from COLLECT_GCC or COMPILER_PATH .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg , i } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < AArch64FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; AArch64IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Assigner . StackOffset , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_neon_fmaxnm : case Intrinsic :: aarch64_neon_fminnm : return instCombineMaxMinNM ( IC , II ) ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_fadd : return instCombineSVEVectorFAdd ( IC , II ) ; case Intrinsic :: aarch64_sve_fsub : return instCombineSVEVectorBinOp ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1_gather_index : return instCombineLD1GatherIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_st1_scatter_index : return instCombineST1ScatterIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1 : return instCombineSVELD1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_st1 : return instCombineSVEST1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_sdiv : return instCombineSVESDIV ( IC , II ) ; case Intrinsic :: aarch64_sve_sel : return instCombineSVESel ( IC , II ) ; case Intrinsic :: aarch64_sve_srshl : return instCombineSVESrshl ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty ) const { if ( PPCSubTarget . isDarwin ( ) ) return 4 ; unsigned Align = PPCSubTarget . isPPC64 ( ) ? 8 : 4 ; if ( PPCSubTarget . hasAltivec ( ) || PPCSubTarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , PPCSubTarget . hasQPX ( ) ? 32 : 16 ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Um
:
case
InlineAsm
::
Constraint_Un
:
case
InlineAsm
::
Constraint_Uq
:
case
InlineAsm
::
Constraint_Us
:
case
InlineAsm
::
Constraint_Ut
:
case
InlineAsm
::
Constraint_Uv
:
case
InlineAsm
::
Constraint_Uy
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"Unexpected asm memory constraint"


<s> Register ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDframe : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; Register BaseReg = MRI . createVirtualRegister ( & ARM :: GPRRegClass ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) . add ( condCodeOp ( ) ) ; return BaseReg ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDframe ARM::t2ADDri ARM::GPRRegClass 0 ARMCC::AL


<s> int mt_legitimate_address_p ( enum machine_mode mode , rtx xinsn , int strict ) { if ( mt_legitimate_simple_address_p ( mode , xinsn , strict ) ) return 1 ; if ( ( mode ) == SImode && GET_CODE ( xinsn ) == AND && GET_CODE ( XEXP ( xinsn , 1 ) ) == CONST_INT && INTVAL ( XEXP ( xinsn , 1 ) ) == - 3 ) return mt_legitimate_simple_address_p ( mode , XEXP ( xinsn , 0 ) , strict ) ; else return 0 ; } </s>

Helper function of GO_IF_LEGITIMATE_ADDRESS . Return non-zero if XINSN is a legitimate address on MT .


<s> static int rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; if ( GET_MODE ( rs6000_compare_op0 ) != SImode ) return 0 ; condition_rtx = rs6000_generate_compare ( GET_CODE ( op ) ) ; cr = XEXP ( condition_rtx , 0 ) ; if ( GET_MODE ( cr ) == CCmode ) emit_insn ( gen_isel_signed ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; else emit_insn ( gen_isel_unsigned ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return 1 ; } </s>


<s> unsigned int rs6000_special_adjust_field_align ( tree type , unsigned int computed ) { if ( computed <= 32 || TYPE_PACKED ( type ) ) return computed ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; while ( AGGREGATE_TYPE_P ( type ) ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return computed ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node && ( TYPE_MODE ( type ) == DFmode || TYPE_MODE ( type ) == DCmode ) ) computed = MIN ( computed , 32 ) ; return computed ; } </s>

AIX word-aligns FP doubles but doubleword-aligns 64-bit ints .


<s> bool AArch64PassConfig :: addPreSched2 ( ) { addPass ( createAArch64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static bool contains_core_p ( unsigned * arr , unsigned core ) { if ( arr [ 0 ] != INVALID_CORE ) { if ( arr [ 0 ] == core ) return true ; if ( arr [ 1 ] != INVALID_CORE ) return arr [ 1 ] == core ; } return false ; } </s>

Return true iff ARR contains CORE , in either of the two elements .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Asm
,
Fixup
,
Target
,
Value
,
IsPCRel
,
Ctx
,
IsLittleEndian
,
true
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
.
isDarwin
(
)
)
RegName
=
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"invalid feature modifier in %<-march=%s%>"

Validate a command-line -march option . Parse the arch and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results , if they are valid , in RES and ISA_FLAGS . Return whether the option is valid .


<s> static struct mips_multi_member * mips_multi_add ( void ) { mips_multi_member empty ; memset ( & empty , 0 , sizeof ( empty ) ) ; return mips_multi_members . safe_push ( empty ) ; } </s>

Add a new , uninitialized member to the current multi-insn sequence .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; Subtarget = & MF . getSubtarget < PPCSubtarget > ( ) ; PPCLowering = Subtarget -> getTargetLowering ( ) ; if ( Subtarget -> hasROPProtect ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; const int Result = MFI . CreateStackObject ( 8 , Align ( 8 ) , false ) ; FI -> setROPProtectionHashSaveIndex ( Result ) ; } SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> enum aarch64_symbol_type aarch64_classify_symbolic_expression ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , INTVAL ( offset ) ) ; } </s>

Classify the base of symbolic expression X , given that X appears in context CONTEXT .


<s> void addLOHDirective ( MCLOHType Kind , const MILOHArgs & Args ) { LOHContainerSet . push_back ( MILOHDirective ( Kind , Args ) ) ; LOHRelated . insert ( Args . begin ( ) , Args . end ( ) ) ; } </s>

Add a LOH directive of this Kind and this Args .


<s> bool X86InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load1 , SDNode * Load2 , int64_t Offset1 , int64_t Offset2 , unsigned NumLoads ) const { assert ( Offset2 > Offset1 ) ; if ( ( Offset2 - Offset1 ) / 8 > 64 ) return false ; unsigned Opc1 = Load1 -> getMachineOpcode ( ) ; unsigned Opc2 = Load2 -> getMachineOpcode ( ) ; if ( Opc1 != Opc2 ) return false ; switch ( Opc1 ) { default : break ; case X86 :: LD_Fp32m : case X86 :: LD_Fp64m : case X86 :: LD_Fp80m : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : return false ; } EVT VT = Load1 -> getValueType ( 0 ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : if ( TM . getSubtargetImpl ( ) -> is64Bit ( ) ) { if ( NumLoads >= 3 ) return false ; } else if ( NumLoads ) { return false ; } break ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : case MVT :: f32 : case MVT :: f64 : if ( NumLoads ) return false ; break ; } return true ; } </s>

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s>
void
VEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
IsAliasOfSX
(
SrcReg
)
&&
IsAliasOfSX
(
DestReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
ORri
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
else
if
(
VE
::
F128RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
unsigned
SubRegIdx
[
]
=
{
VE
::
sub_even
,
VE
::
sub_odd
}
;
unsigned
int
NumSubRegs
=
2
;
copyPhysSubRegs
(
MBB
,
I
,
DL
,
DestReg
,
SrcReg
,
KillSrc
,
get
(
VE
::
ORri
)
,
NumSubRegs
,
SubRegIdx
,
&
getRegisterInfo
(
)
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
dbgs
(
)
<<
"Impossible reg-to-reg copy from "
<<
printReg
(
SrcReg
,
TRI
)
<<
" to "
<<
printReg
(
DestReg
,
TRI
)
<<
"\n"
;
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>


<s> void DLXAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool , const MCSubtargetInfo * ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>


<s> static void mips_push_asm_switch_1 ( struct mips_asm_switch * asm_switch , const char * prefix , const char * suffix ) { if ( asm_switch -> nesting_level == 0 ) fprintf ( asm_out_file , "%s.set\tno%s%s" , prefix , asm_switch -> name , suffix ) ; asm_switch -> nesting_level ++ ; } </s>

Start a new block with the given asm switch enabled . If we need to print a directive , emit PREFIX before it and SUFFIX after it .


<s> bool rs6000_is_valid_insert_mask ( rtx mask , rtx shift , machine_mode mode ) { int nb , ne ; if ( ! rs6000_is_valid_mask ( mask , & nb , & ne , mode ) ) return false ; int n = GET_MODE_PRECISION ( mode ) ; int sh = INTVAL ( XEXP ( shift , 1 ) ) ; if ( sh < 0 || sh >= n ) return false ; rtx_code code = GET_CODE ( shift ) ; if ( sh == 0 ) code = ROTATE ; if ( code == ROTATE && sh >= 0 && nb >= ne && ne >= sh ) code = ASHIFT ; if ( code == ROTATE && sh >= 0 && nb >= ne && nb < sh ) { code = LSHIFTRT ; sh = n - sh ; } if ( mode == DImode && code == ROTATE ) return ( ne == sh ) ; if ( mode == SImode && code == ROTATE ) return ( nb < 32 && ne < 32 && sh < 32 ) ; if ( ne > nb ) return false ; if ( code == ASHIFT && ne < sh ) return false ; if ( nb < 32 && ne < 32 && sh < 32 && ! ( code == LSHIFTRT && nb >= 32 - sh ) ) return true ; if ( code == LSHIFTRT ) sh = 64 - sh ; if ( ne == sh ) return ! ( code == LSHIFTRT && nb >= sh ) ; return false ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwimi or rldimi instruction , to implement an insert with shift SHIFT ( a ROTATE , ASHIFT , or LSHIFTRT ) in mode MODE .


"alignment (%u) for %s exceeds maximum alignment "

Both the HP and GNU assemblers under HP-UX provide a .comm directive that does n't allow the alignment of global common storage to be directly specified . The SOM linker aligns common storage based on the rounded value of the NUM_BYTES parameter in the .comm directive . It 's not possible to use the .align directive as it does n't affect the alignment of the label associated with a .comm directive .


"PPC branch conditions have two components!"

"Cannot insert select on target without ISEL support"

"TrueReg and FalseReg must have overlapping register classes"

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> void sparc_split_reg_reg ( rtx dest , rtx src , machine_mode mode ) { rtx dest1 = gen_highpart ( mode , dest ) ; rtx dest2 = gen_lowpart ( mode , dest ) ; rtx src1 = gen_highpart ( mode , src ) ; rtx src2 = gen_lowpart ( mode , src ) ; if ( reg_overlap_mentioned_p ( dest1 , src2 ) ) { emit_move_insn_1 ( dest2 , src2 ) ; emit_move_insn_1 ( dest1 , src1 ) ; } else { emit_move_insn_1 ( dest1 , src1 ) ; emit_move_insn_1 ( dest2 , src2 ) ; } } </s>

Split a REG < -- > REG move into a pair of moves in MODE .


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Opc = MI . getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LD ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LDC1 ) || ( Opc == Mips :: LDC164 ) ) { if ( ( MI . getOperand ( 1 ) . isFI ( ) ) && ( MI . getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( 2 ) ) ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void mep_reorg_noframe ( rtx_insn * insns ) { rtx_insn * start_frame_insn ; rtx_insn * end_frame_insn = 0 ; int sp_adjust , sp2 ; rtx sp ; while ( insns && ! INSN_P ( insns ) ) insns = NEXT_INSN ( insns ) ; if ( ! insns ) return ; sp_adjust = add_sp_insn_p ( insns ) ; if ( sp_adjust == 0 ) return ; start_frame_insn = insns ; sp = SET_DEST ( PATTERN ( start_frame_insn ) ) ; insns = next_real_insn ( insns ) ; while ( insns ) { rtx_insn * next = next_real_insn ( insns ) ; if ( ! next ) break ; sp2 = add_sp_insn_p ( insns ) ; if ( sp2 ) { if ( end_frame_insn ) return ; end_frame_insn = insns ; if ( sp2 != - sp_adjust ) return ; } else if ( mep_mentioned_p ( insns , sp , 0 ) ) return ; else if ( CALL_P ( insns ) ) return ; insns = next ; } if ( end_frame_insn ) { delete_insn ( start_frame_insn ) ; delete_insn ( end_frame_insn ) ; } } </s>

Check for trivial functions that set up an unneeded stack frame .


<s>
static
void
adjust_xxpermdi
(
rtx_insn
*
insn
)
{
rtx
set
=
PATTERN
(
insn
)
;
rtx
select
=
XEXP
(
set
,
1
)
;
rtx
concat
=
XEXP
(
select
,
0
)
;
rtx
src0
=
XEXP
(
concat
,
0
)
;
XEXP
(
concat
,
0
)
=
XEXP
(
concat
,
1
)
;
XEXP
(
concat
,
1
)
=
src0
;
rtx
parallel
=
XEXP
(
select
,
1
)
;
int
lane0
=
INTVAL
(
XVECEXP
(
parallel
,
0
,
0
)
)
;
int
lane1
=
INTVAL
(
XVECEXP
(
parallel
,
0
,
1
)
)
;
int
new_lane0
=
3
lane1
;
int
new_lane1
=
3
lane0
;
XVECEXP
(
parallel
,
0
,
0
)
=
GEN_INT
(
new_lane0
)
;
XVECEXP
(
parallel
,
0
,
1
)
=
GEN_INT
(
new_lane1
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lanes for xxpermdi %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains an XXPERMDI operation ( that is not a doubleword swap ) , reverse the order of the source operands and adjust the indices of the source lanes to account for doubleword reversal .


"you cannot take the address of a nested function if you use "

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> static void sh_setup_incoming_varargs ( CUMULATIVE_ARGS * ca , enum machine_mode mode , tree type , int * pretend_arg_size , int second_time ATTRIBUTE_UNUSED ) { gcc_assert ( current_function_stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs , anon_parm_regs ; named_parm_regs = ( ROUND_REG ( * ca , mode ) + ( mode == BLKmode ? ROUND_ADVANCE ( int_size_in_bytes ( type ) ) : ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > 0 ) * pretend_arg_size = anon_parm_regs * 4 ; } } </s>

We actually emit the code in sh_expand_prologue . We used to use a static variable to flag that we need to emit this code , but that does n't when inlining , when functions are deferred and then emitted later . Fortunately , we already have two flags that are part of struct function that tell if a function uses varargs or stdarg .


<s> bool CSKYPassConfig :: addInstSelector ( ) { addPass ( createCSKYISelDag ( getCSKYTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool legitimate_constant_p ( rtx x ) { rtx inner ; switch ( GET_CODE ( x ) ) { case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; break ; case CONST : inner = XEXP ( x , 0 ) ; if ( GET_CODE ( inner ) == PLUS && SPARC_SYMBOL_REF_TLS_P ( XEXP ( inner , 0 ) ) ) return false ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode ) return true ; if ( TARGET_VIS && SCALAR_FLOAT_MODE_P ( GET_MODE ( x ) ) && const_zero_operand ( x , GET_MODE ( x ) ) ) return true ; return false ; case CONST_VECTOR : if ( TARGET_VIS && const_zero_operand ( x , GET_MODE ( x ) ) ) return true ; return false ; default : break ; } return true ; } </s>

Nonzero if the constant value X is a legitimate general operand . It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , RegKind Kind , SMLoc S , SMLoc E , MCContext & Ctx , RegConstraintEqualityTy EqTy = RegConstraintEqualityTy :: EqualsReg , AArch64_AM :: ShiftExtendType ExtTy = AArch64_AM :: LSL , unsigned ShiftAmount = 0 , unsigned HasExplicitAmount = false ) { auto Op = make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = Kind ; Op -> Reg . ElementWidth = 0 ; Op -> Reg . EqualityTy = EqTy ; Op -> Reg . ShiftExtend . Type = ExtTy ; Op -> Reg . ShiftExtend . Amount = ShiftAmount ; Op -> Reg . ShiftExtend . HasExplicitAmount = HasExplicitAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static rtx aarch64_gen_load_pair ( machine_mode mode , rtx reg1 , rtx mem1 , rtx reg2 , rtx mem2 ) { switch ( mode ) { case E_DImode : return gen_load_pairdi ( reg1 , mem1 , reg2 , mem2 ) ; case E_DFmode : return gen_load_pairdf ( reg1 , mem1 , reg2 , mem2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and regurn a load pair isntruction of mode MODE to load register REG1 from MEM1 and register REG2 from MEM2 .


<s> DecodeStatus SparcDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { uint32_t Insn ; bool isLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , isLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( STI . getFeatureBits ( ) [ Sparc :: FeatureV9 ] ) { Result = decodeInstruction ( DecoderTableSparcV932 , Instr , Insn , Address , this , STI ) ; } else { Result = decodeInstruction ( DecoderTableSparcV832 , Instr , Insn , Address , this , STI ) ; } if ( Result != MCDisassembler :: Fail ) return Result ; Result = decodeInstruction ( DecoderTableSparc32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .

Sparc Sparc Sparc::FeatureV9 Sparc Sparc Sparc 4


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
ResValue
=
OutVals
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
AExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
ResValue
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static struct machine_function * iq2000_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const TargetInstrInfo & TII = * MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_type_node ) return "U6__booll" ; if ( TARGET_FLOAT128_TYPE ) { if ( type == ieee128_float_type_node ) return "U10__float128" ; if ( type == ibm128_float_type_node ) return "g" ; if ( type == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return ( TARGET_IEEEQUAD ) ? "U10__float128" : "g" ; } if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_ELF && TARGET_LONG_DOUBLE_128 && ! TARGET_IEEEQUAD ) return "g" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


<s> static int arm_legitimate_index_p ( enum machine_mode mode , rtx index , RTX_CODE outer , int strict_p ) { HOST_WIDE_INT range ; enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( TARGET_FPA || TARGET_MAVERICK ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || ( TARGET_MAVERICK && mode == DImode ) ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return val > - 256 && val < 256 ; else return val > - 4096 && val < 4092 ; } return TARGET_LDRD && arm_address_register_rtx_p ( index , strict_p ) ; } if ( GET_MODE_SIZE ( mode ) <= 4 && ! ( arm_arch4 && ( mode == HImode || ( mode == QImode && outer == SIGN_EXTEND ) ) ) ) { if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && power_of_two_operand ( xiop1 , SImode ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && power_of_two_operand ( xiop0 , SImode ) ) ) ; } else if ( code == LSHIFTRT || code == ASHIFTRT || code == ASHIFT || code == ROTATERT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && GET_CODE ( op ) == CONST_INT && INTVAL ( op ) > 0 && INTVAL ( op ) <= 31 ) ; } } if ( arm_arch4 ) { if ( mode == HImode || ( outer == SIGN_EXTEND && mode == QImode ) ) range = 256 ; else range = 4096 ; } else range = ( mode == HImode ) ? 4095 : 4096 ; return ( code == CONST_INT && INTVAL ( index ) < range && INTVAL ( index ) > - range ) ; } </s>

Return nonzero if INDEX is valid for an address index operand in ARM state .


<s>
ScheduleHazardRecognizer
::
HazardType
PPCHazardRecognizer970
::
getHazardType
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
NoHazard
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
NumIssued
!=
0
&&
(
isFirst
||
isSingle
)
)
return
Hazard
;
if
(
isCracked
&&
NumIssued
>
2
)
return
Hazard
;
switch
(
InstrType
)
{
default
:
llvm_unreachable
(
"Unknown instruction type!"
)
;
case
PPCII
::
PPC970_FXU
:
case
PPCII
::
PPC970_LSU
:
case
PPCII
::
PPC970_FPU
:
case
PPCII
::
PPC970_VALU
:
case
PPCII
::
PPC970_VPERM
:
if
(
NumIssued
==
4
)
return
Hazard
;
break
;
case
PPCII
::
PPC970_CRU
:
if
(
NumIssued
>=
2
)
return
Hazard
;
break
;
case
PPCII
::
PPC970_BRU
:
break
;
}
if
(
HasCTRSet
&&
(
Opcode
==
PPC
::
BCTRL_Darwin
||
Opcode
==
PPC
::
BCTRL_SVR4
)
)
return
NoopHazard
;
if
(
isLoad
&&
NumStores
)
{
unsigned
LoadSize
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown load!"
)
;
case
PPC
::
LBZ
:
case
PPC
::
LBZU
:
case
PPC
::
LBZX
:
case
PPC
::
LBZ8
:
case
PPC
::
LBZU8
:
case
PPC
::
LBZX8
:
case
PPC
::
LVEBX
:
LoadSize
=
1
;
break
;
case
PPC
::
LHA
:
case
PPC
::
LHAU
:
case
PPC
::
LHAX
:
case
PPC
::
LHZ
:
case
PPC
::
LHZU
:
case
PPC
::
LHZX
:
case
PPC
::
LVEHX
:
case
PPC
::
LHBRX
:
case
PPC
::
LHA8
:
case
PPC
::
LHAU8
:
case
PPC
::
LHAX8
:
case
PPC
::
LHZ8
:
case
PPC
::
LHZU8
:
case
PPC
::
LHZX8
:
LoadSize
=
2
;
break
;
case
PPC
::
LFS
:
case
PPC
::
LFSU
:
case
PPC
::
LFSX
:
case
PPC
::
LWZ
:
case
PPC
::
LWZU
:
case
PPC
::
LWZX
:
case
PPC
::
LWA
:
case
PPC
::
LWAX
:
case
PPC
::
LVEWX
:
case
PPC
::
LWBRX
:
case
PPC
::
LWZ8
:
case
PPC
::
LWZX8
:
LoadSize
=
4
;
break
;
case
PPC
::
LFD
:
case
PPC
::
LFDU
:
case
PPC
::
LFDX
:
case
PPC
::
LD
:
case
PPC
::
LDU
:
case
PPC
::
LDX
:
LoadSize
=
8
;
break
;
case
PPC
::
LVX
:
case
PPC
::
LVXL
:
LoadSize
=
16
;
break
;
}
if
(
isLoadOfStoredAddress
(
LoadSize
,
Node
->
getOperand
(
0
)
,
Node
->
getOperand
(
1
)
)
)
return
NoopHazard
;
}
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .


"Unexpected instruction type for reassociation"

"Must have dead EFLAGS operand in reassociable instruction"

"Unexpected operand in reassociable instruction"

This is an architecture-specific helper function of reassociateOps .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ; if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; if ( ! OutStreamer . hasRawTextSupport ( ) ) { switch ( TmpInst0 . getOpcode ( ) ) { case Mips :: DSLL : case Mips :: DSRL : case Mips :: DSRA : Mips :: LowerLargeShift ( TmpInst0 ) ; break ; case Mips :: DEXT : case Mips :: DINS : Mips :: LowerDextDins ( TmpInst0 ) ; } } OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Mips Mips 128 Mips::DSLL Mips::DSRL Mips::DSRA Mips::LowerLargeShift Mips::DEXT Mips::DINS Mips::LowerDextDins


<s> const DLXInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static bool rs6000_lra_p ( void ) { return rs6000_lra_flag ; } </s>

Return true if we use LRA instead of reload pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"optimise barriers pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const std :: vector < SDValue > & BVOps , MVT EVT , SelectionDAG & DAG ) const { unsigned NumElts = BVOps . size ( ) ; if ( EVT . getSizeInBits ( ) * NumElts == 64 ) return false ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 ) { return ( isMOVLMask ( & BVOps [ 0 ] , 4 ) || isCommutedMOVL ( & BVOps [ 0 ] , 4 , true ) || isSHUFPMask ( & BVOps [ 0 ] , 4 ) || isCommutedSHUFP ( & BVOps [ 0 ] , 4 ) ) ; } return false ; } </s>


<s> machreg_t inet_makeaddr ( machreg_t net , machreg_t lna ) { return _inet_makeaddr ( net , lna ) >> SHIFT_BITS ; } </s>

< arpa/inet.h > has struct in_addr inet_makeaddr ( int , int ) ; ( IRIX 6.2 ) struct in_addr inet_makeaddr ( in_addr_t , in_addr_t ) ; ( IRIX 6.5 )


<s> static bool mips_valid_pointer_mode ( enum machine_mode mode ) { return ( mode == SImode || ( TARGET_64BIT && mode == DImode ) ) ; } </s>


<s> static void mips_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved , fp_saved ; local_cum = * cum ; FUNCTION_ARG_ADVANCE ( local_cum , mode , type , 1 ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; fp_saved = ( EABI_FLOAT_VARARGS_P ? MAX_ARGS_IN_REGISTERS - local_cum . num_fprs : 0 ) ; if ( ! no_rtl ) { if ( gp_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_rtx_MEM ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { enum machine_mode mode ; int off , i ; off = - gp_saved * UNITS_PER_WORD ; off &= ~ ( UNITS_PER_FPVALUE - 1 ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += FP_INC ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , off ) ; mem = gen_rtx_MEM ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; emit_move_insn ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE ; } } } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = ( gp_saved * UNITS_PER_WORD + fp_saved * UNITS_PER_FPREG ) ; } </s>


"getBranchTargetOpValueMM expects only expressions or immediates"

getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> DecodeStatus AArch64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { CommentStream = & CS ; Size = 0 ; if ( Bytes . size ( ) < 4 ) return Fail ; Size = 4 ; uint32_t Insn = ( Bytes [ 3 ] << 24 ) | ( Bytes [ 2 ] << 16 ) | ( Bytes [ 1 ] << 8 ) | ( Bytes [ 0 ] << 0 ) ; return decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; } </s>


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> bool function_checker :: require_immediate ( unsigned int argno , HOST_WIDE_INT & value_out ) { gcc_assert ( argno < m_nargs ) ; tree arg = m_args [ argno ] ; if ( ! tree_fits_uhwi_p ( arg ) ) { report_non_ice ( location , fndecl , argno ) ; return false ; } value_out = tree_to_uhwi ( arg ) ; return true ; } </s>

Check that argument ARGNO is an integer constant expression and store its value in VALUE_OUT if so . The caller should first check that argument ARGNO exists .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool MipsTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . hasMips3 ( ) && Subtarget . abiUsesSoftFloat ( ) ) { if ( Type == MVT :: i32 ) return true ; } return IsSigned ; } </s>

Returns true if arguments should be sign-extended in lib calls .


<s>
MachineBasicBlock
*
SystemZTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
SystemZInstrInfo
&
TII
=
*
TM
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
SystemZ
::
Select32
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF32
||
MI
->
getOpcode
(
)
==
SystemZ
::
Select64
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF64
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
SystemZCC
::
CondCodes
CC
=
(
SystemZCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
BuildMI
(
BB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
copy1MBB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SystemZ
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; AArch64PreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx expand_set_or_cpymem_prologue ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx vec_value , rtx count , int align , int desired_alignment , bool issetmem ) { int i ; for ( i = 1 ; i < desired_alignment ; i <<= 1 ) { if ( align <= i ) { rtx_code_label * label = ix86_expand_aligntest ( destptr , i , false ) ; if ( issetmem ) { if ( vec_value && i > GET_MODE_SIZE ( GET_MODE ( value ) ) ) destmem = emit_memset ( destmem , destptr , vec_value , i ) ; else destmem = emit_memset ( destmem , destptr , value , i ) ; } else destmem = emit_memmov ( destmem , & srcmem , destptr , srcptr , i ) ; ix86_adjust_counter ( count , i ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; set_mem_align ( destmem , i * 2 * BITS_PER_UNIT ) ; } } return destmem ; } </s>

Depending on ISSETMEM , copy enough from SRCMEM to DESTMEM or set enough to DESTMEM to align it to DESIRED_ALIGNMENT . Original alignment is ALIGN . Depending on ISSETMEM , either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are ignored . Return value is updated DESTMEM .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> std :: pair < unsigned , const TargetRegisterClass * > MipsTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , Mips :: CPURegsRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , Mips :: FGR32RegisterClass ) ; if ( VT == MVT :: f64 ) if ( ( ! Subtarget -> isSingleFloat ( ) ) && ( ! Subtarget -> isFP64bit ( ) ) ) return std :: make_pair ( 0U , Mips :: AFGR64RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; if ( ! AFI || AFI -> hasRedZone ( ) . getValueOr ( true ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> static rtx arm_trampoline_adjust_address ( rtx addr ) { if ( TARGET_THUMB ) addr = expand_simple_binop ( Pmode , IOR , addr , const1_rtx , NULL , 0 , OPTAB_LIB_WIDEN ) ; return addr ; } </s>

Thumb trampolines should be entered in thumb mode , so set the bottom bit of the address .


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> const TargetRegisterClass * SparcRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return Subtarget . is64Bit ( ) ? & SP :: I64RegsRegClass : & SP :: IntRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

Sparc Sparc SP::I64RegsRegClass SP::IntRegsRegClass


<s> bool X86TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == 8 ) return false ; if ( Subtarget . hasXOP ( ) && ( Bits == 8 || Bits == 16 || Bits == 32 || Bits == 64 ) ) return false ; if ( Subtarget . hasAVX2 ( ) && ( Bits == 32 || Bits == 64 ) ) return false ; if ( Subtarget . hasBWI ( ) && Bits == 16 ) return false ; return true ; } </s>

This is used to enable splatted operand transforms for vector shifts and vector funnel shifts .


<s> bool mips_const_vector_same_val_p ( rtx op , machine_mode mode ) { int i , nunits = GET_MODE_NUNITS ( mode ) ; rtx first ; if ( GET_CODE ( op ) != CONST_VECTOR || GET_MODE ( op ) != mode ) return false ; first = CONST_VECTOR_ELT ( op , 0 ) ; for ( i = 1 ; i < nunits ; i ++ ) if ( ! rtx_equal_p ( first , CONST_VECTOR_ELT ( op , i ) ) ) return false ; return true ; } </s>

Return true if OP is a constant vector with the number of units in MODE , and each unit has the same value .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
mf
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> const uint16_t * TOYRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { TOY :: R4 , TOY :: R5 , TOY :: R6 , TOY :: R7 , TOY :: R8 , TOY :: R9 , 0 } ; return CalleeSavedRegs ; } </s>


<s> static rtx mep_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == VOIDmode ) return GEN_INT ( cum -> vliw ) ; if ( cum -> nregs < 4 ) { if ( type && TARGET_IVC2 && VECTOR_TYPE_P ( type ) ) return gen_rtx_REG ( mode , cum -> nregs + 49 ) ; else return gen_rtx_REG ( mode , cum -> nregs + 1 ) ; } return NULL_RTX ; } </s>

The ABI is thus : Arguments are in $ 1 , $ 2 , $ 3 , $ 4 , stack . Arguments larger than 4 bytes are passed indirectly . Return value in 0 , unless bigger than 4 bytes , then the caller passes a pointer as the first arg . For varargs , we copy $ 1 .. $ 4 to the stack .


<s> static void vax_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum += ( arg . promoted_size_in_bytes ( ) + 3 ) & ~ 3 ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> unsigned AArch64TTIImpl :: getMaxPrefetchIterationsAhead ( ) { return ST -> getMaxPrefetchIterationsAhead ( ) ; } </s>

Return the maximum prefetch distance in terms of loop iterations .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned Align , bool isSrcConst , bool isSrcStr , SelectionDAG & DAG ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM::tSpill
0


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s> static tree rs6000_builtin_vectorized_libmass ( combined_fn fn , tree type_out , tree type_in ) { char name [ 32 ] ; const char * suffix = NULL ; tree fntype , new_fndecl , bdecl = NULL_TREE ; int n_args = 1 ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations || ! TARGET_VSX ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_ATAN2 : CASE_CFN_HYPOT : CASE_CFN_POW : n_args = 2 ; gcc_fallthrough ( ) ; CASE_CFN_ACOS : CASE_CFN_ACOSH : CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == 2 ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = "d2" ; } else if ( el_mode == SFmode && n == 4 ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = "4" ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( "__builtin_" ) - 1 ) ; strcat ( name , suffix ) ; if ( n_args == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == 2 ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for the Mathematical Acceleration Subsystem ( mass ) interface to a library with vectorized intrinsics .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } else if ( Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSFRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && Subtarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>


<s> static bool ia64_cannot_force_const_mem ( machine_mode mode , rtx x ) { if ( mode == RFmode ) return true ; return tls_symbolic_operand_type ( x ) != 0 ; } </s>

Do n't allow TLS addresses to get spilled to memory .


<s> void X86DynAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { const DebugLoc & DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getDynAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; bool Is64BitAlloca = MI -> getOpcode ( ) == X86 :: DYN_ALLOCA_64 ; assert ( SlotSize == 4 || SlotSize == 8 ) ; switch ( L ) { case TouchAndSub : { assert ( Amount >= SlotSize ) ; unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; } case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64BitAlloca , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64BitAlloca ? X86 :: SUB64rr : X86 :: SUB32rr ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; } break ; } Register AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; if ( MRI -> use_empty ( AmountReg ) ) if ( MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ) AmountDef -> eraseFromParent ( ) ; } </s>


Helper function of mt_legitimate_address_p . Return true if XINSN is a simple address , otherwise false .


"Multiply operation with an immediate and a register!"

"Divide operation with an immediate and a register!"

Produce a widened version of the select instruction .


<s> static void nds32_group_tls_insn ( rtx insn ) { rtx pat = PATTERN ( insn ) ; rtx unspec_relax_group = XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ; int group_id = nds32_alloc_relax_group_id ( ) ; while ( GET_CODE ( pat ) != SET && GET_CODE ( pat ) == PARALLEL ) { pat = XVECEXP ( pat , 0 , 0 ) ; } if ( GET_CODE ( unspec_relax_group ) == UNSPEC && XINT ( unspec_relax_group , 1 ) == UNSPEC_VOLATILE_RELAX_GROUP ) { XVECEXP ( unspec_relax_group , 0 , 0 ) = GEN_INT ( group_id ) ; } } </s>


"Unexpected Kind in getPointerRegClass!"


<s> static void ix86_simd_clone_adjust ( struct cgraph_node * node ) { const char * str = NULL ; gcc_assert ( node -> decl == cfun -> decl ) ; switch ( node -> simdclone -> vecsize_mangle ) { case 'b' : if ( ! TARGET_SSE2 ) str = "sse2" ; break ; case 'c' : if ( ! TARGET_AVX ) str = "avx" ; break ; case 'd' : if ( ! TARGET_AVX2 ) str = "avx2" ; break ; case 'e' : if ( ! TARGET_AVX512F ) str = "avx512f" ; break ; default : gcc_unreachable ( ) ; } if ( str == NULL ) return ; push_cfun ( NULL ) ; tree args = build_tree_list ( NULL_TREE , build_string ( strlen ( str ) , str ) ) ; bool ok = ix86_valid_target_attribute_p ( node -> decl , NULL , args , 0 ) ; gcc_assert ( ok ) ; pop_cfun ( ) ; ix86_reset_previous_fndecl ( ) ; ix86_set_current_function ( node -> decl ) ; } </s>

Add target attribute to SIMD clone NODE if needed .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; const Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> llvm :: FastISel * X86 :: createFastISel ( MachineFunction & mf , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < const Instruction * , 8 > & cil ) { return new X86FastISel ( mf , vm , bm , am , cil ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static rtx csky_function_arg ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int reg = pcum -> reg ; machine_mode mode = arg . mode ; if ( FUNCTION_VARG_MODE_P ( mode ) && ! pcum -> is_stdarg ) { reg = pcum -> freg ; if ( reg < CSKY_NPARM_FREGS ) return gen_rtx_REG ( mode , CSKY_FIRST_VFP_REGNUM + reg ) ; else return NULL_RTX ; } if ( reg < CSKY_NPARM_REGS ) return gen_rtx_REG ( mode , CSKY_FIRST_PARM_REGNUM + reg ) ; return NULL_RTX ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasOptNone ( ) ) OptimizationGoal = 6 ; else if ( F . hasMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . hasOptSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; emitAlignment ( Align ( 2 ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> emitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCInstrInfo :: isBDNZ ( unsigned Opcode ) const { return ( Opcode == ( Subtarget . isPPC64 ( ) ? PPC :: BDNZ8 : PPC :: BDNZ ) ) ; } </s>

Check Opcode is BDNZ ( Decrement CTR and branch if it is still nonzero ) .


<s> SDValue X86SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , bool , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= 256 || SrcPtrInfo . getAddrSpace ( ) >= 256 ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: ECX , X86 :: ESI , X86 :: EDI } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; const X86Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < X86Subtarget > ( ) ; if ( UseFSRMForMemcpy && Subtarget . hasFSRM ( ) ) return emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , Size , MVT :: i8 ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static void ix86_pad_returns ( void ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR -> preds ) { basic_block bb = e -> src ; rtx ret = BB_END ( bb ) ; rtx prev ; bool replace = false ; if ( GET_CODE ( ret ) != JUMP_INSN || GET_CODE ( PATTERN ( ret ) ) != RETURN || ! maybe_hot_bb_p ( bb ) ) continue ; for ( prev = PREV_INSN ( ret ) ; prev ; prev = PREV_INSN ( prev ) ) if ( active_insn_p ( prev ) || GET_CODE ( prev ) == CODE_LABEL ) break ; if ( prev && GET_CODE ( prev ) == CODE_LABEL ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( EDGE_FREQUENCY ( e ) && e -> src -> index >= 0 && ! ( e -> flags & EDGE_FALLTHRU ) ) replace = true ; } if ( ! replace ) { prev = prev_active_insn ( ret ) ; if ( prev && ( ( GET_CODE ( prev ) == JUMP_INSN && any_condjump_p ( prev ) ) || GET_CODE ( prev ) == CALL_INSN ) ) replace = true ; if ( ! prev && cfun -> function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED ) replace = true ; } if ( replace ) { emit_insn_before ( gen_return_internal_long ( ) , ret ) ; delete_insn ( ret ) ; } } } </s>

AMD Athlon works faster when RET is not destination of conditional jump or directly preceded by other jump instruction . We avoid the penalty by inserting NOP just before the RET instructions in such cases .


<s> InstructionCost getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( BitSize > 64 ) return TTI :: TCC_Free ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 21 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getSExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> unsigned getInstSizeInBytes ( const MachineInstr & MI ) const override { return 4U ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , SP :: IntRegsRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .