<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; bool genExecuteOnly = ARM_TM . getMCSubtargetInfo ( ) -> hasFeature ( ARM :: FeatureExecuteOnly ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_ARM_PURECODE ; TextSection = Ctx . getELFSection ( ".text" , Type , Flags , 0 , "" , false , 0U , nullptr ) ; } } </s>

This method must be called before any actual lowering is done .

ARM ARM ARM ARM ARM ARM ARM ARMABI::ARM_ABI_AAPCS ARM ARM::FeatureExecuteOnly ARM ".text" 0 "" 0U


<s>
bool
ARMAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
assert
(
0
&&
"unknown operand type"
)
;
return
false
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
&&
MO
.
getReg
(
)
!=
ARM
::
CPSR
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
GetSymbolRef
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

ARM
ARM
0
"unknown operand type"
ARM::CPSR
"Subregs should be eliminated!"


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE && TREE_CODE ( type ) != OPAQUE_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_long_type_node ) return "U6__boolx" ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return "g" ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return "u9__ieee128" ; if ( type == vector_pair_type_node ) return "u13__vector_pair" ; if ( type == vector_quad_type_node ) return "u13__vector_quad" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


"Can only insert epilogue into returning blocks"

"Expected to see callee-save register restore code"


<s> static size_t mingw32_gt_pch_alloc_granularity ( void ) { SYSTEM_INFO si ; GetSystemInfo ( & si ) ; va_granularity = ( size_t ) si . dwAllocationGranularity ; return va_granularity ; } </s>

Granularity for reserving address space .


<s> int sh_media_register_for_return ( void ) { int regno ; int tr0_used ; if ( ! current_function_is_leaf ) return - 1 ; if ( lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( current_function_decl ) ) ) return - 1 ; if ( sh_cfun_interrupt_handler_p ( ) ) return - 1 ; tr0_used = flag_pic && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ; for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_really_used_regs [ regno ] && ! regs_ever_live [ regno ] ) return regno ; return - 1 ; } </s>

Choose a call-clobbered target-branch register that remains unchanged along the whole function . We set it up as the return value in the prologue .


<s> void rs6000_split_logical ( rtx operands [ 3 ] , enum rtx_code code , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; machine_mode sub_mode ; rtx op0 , op1 , op2 ; int sub_size , regno0 , regno1 , nregs , i ; if ( mode == DImode && ! TARGET_POWERPC64 ) { rs6000_split_logical_di ( operands , code , complement_final_p , complement_op1_p , complement_op2_p ) ; return ; } op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; op2 = ( code == NOT ) ? NULL_RTX : operands [ 2 ] ; sub_mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; sub_size = GET_MODE_SIZE ( sub_mode ) ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; gcc_assert ( reload_completed ) ; gcc_assert ( IN_RANGE ( regno0 , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; gcc_assert ( IN_RANGE ( regno1 , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; nregs = rs6000_hard_regno_nregs [ ( int ) mode ] [ regno0 ] ; gcc_assert ( nregs > 1 ) ; if ( op2 && REG_P ( op2 ) ) gcc_assert ( IN_RANGE ( REGNO ( op2 ) , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; for ( i = 0 ; i < nregs ; i ++ ) { int offset = i * sub_size ; rtx sub_op0 = simplify_subreg ( sub_mode , op0 , mode , offset ) ; rtx sub_op1 = simplify_subreg ( sub_mode , op1 , mode , offset ) ; rtx sub_op2 = ( ( code == NOT ) ? NULL_RTX : simplify_subreg ( sub_mode , op2 , mode , offset ) ) ; rs6000_split_logical_inner ( sub_op0 , sub_op1 , sub_op2 , code , sub_mode , complement_final_p , complement_op1_p , complement_op2_p ) ; } return ; } </s>

Split the insns that make up boolean operations operating on multiple GPR registers . The boolean MD patterns ensure that the inputs either are exactly the same as the output registers , or there is no overlap . OPERANDS is an array containing the destination and two input operands . CODE is the base operation ( AND , IOR , XOR , NOT ) . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


"dynamic alloca in the static alloca map?"

Emit an alloca address in a register using target-specific logic .


<s> static int unspec_cdot ( int rot ) { switch ( rot ) { case 0 : return UNSPEC_CDOT ; case 90 : return UNSPEC_CDOT90 ; case 180 : return UNSPEC_CDOT180 ; case 270 : return UNSPEC_CDOT270 ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_CDOT * unspec for rotation amount ROT .


<s> static SDValue matchBinOpReduction ( SDNode * Extract , ISD :: NodeType BinOp ) { if ( ( Extract -> getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) || ! isNullConstant ( Extract -> getOperand ( 1 ) ) ) return SDValue ( ) ; unsigned Stages = Log2_32 ( Extract -> getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Op = Extract -> getOperand ( 0 ) ; for ( unsigned i = 0 ; i < Stages ; ++ i ) { if ( Op . getOpcode ( ) != BinOp ) return SDValue ( ) ; ShuffleVectorSDNode * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( 0 ) . getNode ( ) ) ; if ( Shuffle ) { Op = Op . getOperand ( 1 ) ; } else { Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( 1 ) . getNode ( ) ) ; Op = Op . getOperand ( 0 ) ; } if ( ! Shuffle || ( Shuffle -> getOperand ( 0 ) != Op ) ) return SDValue ( ) ; for ( int Index = 0 , MaskEnd = 1 << i ; Index < MaskEnd ; ++ Index ) if ( Shuffle -> getMaskElt ( Index ) != MaskEnd + Index ) return SDValue ( ) ; } return Op ; } </s>

Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract .


<s> static bool isThumb ( const MCSubtargetInfo & STI ) { return STI . getFeatureBits ( ) [ ARM :: ModeThumb ] ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> registered_function & function_builder :: add_function ( const function_instance & instance , const char * name , tree fntype , tree attrs , aarch64_feature_flags required_extensions , bool overloaded_p , bool placeholder_p ) { unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_SVE ; tree decl = placeholder_p ? integer_zero_node : simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function > ( ) ; rfn . instance = instance ; rfn . decl = decl ; rfn . required_extensions = required_extensions ; rfn . overloaded_p = overloaded_p ; vec_safe_push ( registered_functions , & rfn ) ; return rfn ; } </s>

Add a function called NAME with type FNTYPE and attributes ATTRS . INSTANCE describes what the function does .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static rtx rs6000_complex_function_value ( machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_UNIT_SIZE ( mode ) ; if ( TARGET_FLOAT128_TYPE && ( mode == KCmode || ( mode == TCmode && TARGET_IEEEQUAD ) ) ) regno = ALTIVEC_ARG_RETURN ; else if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= 4 ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= 8 ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + 1 ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } </s>

Return an RTX representing where to find the function value of a function returning MODE .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue X86SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= 256 || SrcPtrInfo . getAddrSpace ( ) >= 256 ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: ECX , X86 :: ESI , X86 :: EDI } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; const X86Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < X86Subtarget > ( ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno , unsigned int format ) { if ( ( format == 0 && write_symbols != DWARF2_DEBUG ) || format == 2 ) return regno ; if ( regno <= 63 ) return regno ; if ( regno == LR_REGNO ) return 108 ; if ( regno == CTR_REGNO ) return 109 ; if ( format == 1 && regno == CR2_REGNO ) return 64 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 86 ; if ( regno == CA_REGNO ) return 101 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 1124 ; if ( regno == VRSAVE_REGNO ) return 356 ; if ( regno == VSCR_REGNO ) return 67 ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s> rtx aarch64_pfalse_reg ( machine_mode mode ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) ; rtx reg = force_reg ( VNx16BImode , CONST0_RTX ( VNx16BImode ) ) ; return gen_lowpart ( mode , reg ) ; } </s>

Return an all-false predicate register of mode MODE .


<s> static void init_float128_ibm ( machine_mode mode ) { if ( ! TARGET_XL_COMPAT ) { set_optab_libfunc ( add_optab , mode , "__gcc_qadd" ) ; set_optab_libfunc ( sub_optab , mode , "__gcc_qsub" ) ; set_optab_libfunc ( smul_optab , mode , "__gcc_qmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "__gcc_qdiv" ) ; if ( ! TARGET_HARD_FLOAT ) { set_optab_libfunc ( neg_optab , mode , "__gcc_qneg" ) ; set_optab_libfunc ( eq_optab , mode , "__gcc_qeq" ) ; set_optab_libfunc ( ne_optab , mode , "__gcc_qne" ) ; set_optab_libfunc ( gt_optab , mode , "__gcc_qgt" ) ; set_optab_libfunc ( ge_optab , mode , "__gcc_qge" ) ; set_optab_libfunc ( lt_optab , mode , "__gcc_qlt" ) ; set_optab_libfunc ( le_optab , mode , "__gcc_qle" ) ; set_optab_libfunc ( unord_optab , mode , "__gcc_qunord" ) ; set_conv_libfunc ( sext_optab , mode , SFmode , "__gcc_stoq" ) ; set_conv_libfunc ( sext_optab , mode , DFmode , "__gcc_dtoq" ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , "__gcc_qtos" ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , "__gcc_qtod" ) ; set_conv_libfunc ( sfix_optab , SImode , mode , "__gcc_qtoi" ) ; set_conv_libfunc ( ufix_optab , SImode , mode , "__gcc_qtou" ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , "__gcc_itoq" ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , "__gcc_utoq" ) ; } } else { set_optab_libfunc ( add_optab , mode , "_xlqadd" ) ; set_optab_libfunc ( sub_optab , mode , "_xlqsub" ) ; set_optab_libfunc ( smul_optab , mode , "_xlqmul" ) ; set_optab_libfunc ( sdiv_optab , mode , "_xlqdiv" ) ; } if ( mode == IFmode ) { set_conv_libfunc ( sext_optab , mode , SDmode , "__dpd_extendsdtf" ) ; set_conv_libfunc ( sext_optab , mode , DDmode , "__dpd_extendddtf" ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , "__dpd_trunctdtf" ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , "__dpd_trunctfsd" ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , "__dpd_trunctfdd" ) ; set_conv_libfunc ( sext_optab , TDmode , mode , "__dpd_extendtftd" ) ; set_conv_libfunc ( sfix_optab , DImode , mode , "__fixtfdi" ) ; set_conv_libfunc ( ufix_optab , DImode , mode , "__fixunstfdi" ) ; set_conv_libfunc ( sfloat_optab , mode , DImode , "__floatditf" ) ; set_conv_libfunc ( ufloat_optab , mode , DImode , "__floatunditf" ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , "__fixtfti" ) ; set_conv_libfunc ( ufix_optab , TImode , mode , "__fixunstfti" ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , "__floattitf" ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , "__floatuntitf" ) ; } } } </s>

Set up AIX/Darwin/64-bit Linux quad floating point routines .


<s> void ARMTargetStreamer :: reset ( ) { } </s>

Reset an existing scalar value for Def and a given Instance .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { const bool SrcIsCheri = isCheriPointer ( SrcAS , nullptr ) ; const bool DestIsCheri = isCheriPointer ( DestAS , nullptr ) ; if ( ( SrcIsCheri || DestIsCheri ) && ( SrcIsCheri != DestIsCheri ) ) return false ; return SrcAS < 256 && DestAS < 256 ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> isPredicable ( ) ) return false ; if ( ! isEligibleForITBlock ( MI ) ) return false ; ARMFunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { assert ( 0 ) ; } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>


<s> bool legitimate_constant_pool_address_p ( const_rtx x , machine_mode mode , bool strict ) { return ( toc_relative_expr_p ( x , strict ) && ( TARGET_CMODEL != CMODEL_MEDIUM || constant_pool_expr_p ( XVECEXP ( tocrel_base , 0 , 0 ) ) || mode == QImode || offsettable_ok_by_alignment ( XVECEXP ( tocrel_base , 0 , 0 ) , INTVAL ( tocrel_offset ) , mode ) ) ) ; } </s>

Return true if X is a constant pool address , and also for cmodel=medium if X is a toc-relative address known to be offsettable within MODE .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < AArch64FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static inline tree compound_expr ( tree t1 , tree t2 ) { return build2 ( COMPOUND_EXPR , void_type_node , t1 , t2 ) ; } </s>

Return the compound expression made of T1 and T2 .


<s>
const
char
*
output_fp_compare
(
rtx
insn
,
rtx
*
operands
,
int
eflags_p
,
int
unordered_p
)
{
int
stack_top_dies
;
rtx
cmp_op0
,
cmp_op1
;
int
is_sse
=
SSE_REG_P
(
operands
[
0
]
)
||
SSE_REG_P
(
operands
[
1
]
)
;
if
(
eflags_p
)
{
cmp_op0
=
operands
[
0
]
;
cmp_op1
=
operands
[
1
]
;
}
else
{
cmp_op0
=
operands
[
1
]
;
cmp_op1
=
operands
[
2
]
;
}
if
(
is_sse
)
{
if
(
GET_MODE
(
operands
[
0
]
)
==
SFmode
)
if
(
unordered_p
)
return
"ucomiss\t{%1, %0|%0, %1}"
;
else
return
"comiss\t{%1, %0|%0, %1}"
;
else
if
(
unordered_p
)
return
"ucomisd\t{%1, %0|%0, %1}"
;
else
return
"comisd\t{%1, %0|%0, %1}"
;
}
gcc_assert
(
STACK_TOP_P
(
cmp_op0
)
)
;
stack_top_dies
=
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
)
!=
0
;
if
(
cmp_op1
==
CONST0_RTX
(
GET_MODE
(
cmp_op1
)
)
)
{
if
(
stack_top_dies
)
{
output_asm_insn
(
"ftst\n\tfnstsw\t%0"
,
operands
)
;
return
TARGET_USE_FFREEP
"ffreep\t%y1"
:
"fstp\t%y1"
;
}
else
return
"ftst\n\tfnstsw\t%0"
;
}
if
(
STACK_REG_P
(
cmp_op1
)
&&
stack_top_dies
&&
find_regno_note
(
insn
,
REG_DEAD
,
REGNO
(
cmp_op1
)
)
&&
REGNO
(
cmp_op1
)
!=
FIRST_STACK_REG
)
{
if
(
eflags_p
)
{
if
(
unordered_p
)
output_asm_insn
(
"fucomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
else
output_asm_insn
(
"fcomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
return
TARGET_USE_FFREEP
"ffreep\t%y0"
:
"fstp\t%y0"
;
}
else
{
if
(
unordered_p
)
return
"fucompp\n\tfnstsw\t%0"
;
else
return
"fcompp\n\tfnstsw\t%0"
;
}
}
else
{
static
const
char
*
const
alt
[
16
]
=
{
"fcom%z2\t%y2\n\tfnstsw\t%0"
,
"fcomp%z2\t%y2\n\tfnstsw\t%0"
,
"fucom%z2\t%y2\n\tfnstsw\t%0"
,
"fucomp%z2\t%y2\n\tfnstsw\t%0"
,
"ficom%z2\t%y2\n\tfnstsw\t%0"
,
"ficomp%z2\t%y2\n\tfnstsw\t%0"
,
,
,
"fcomi\t{%y1, %0|%0, %y1}"
,
"fcomip\t{%y1, %0|%0, %y1}"
,
"fucomi\t{%y1, %0|%0, %y1}"
,
"fucomip\t{%y1, %0|%0, %y1}"
,
,
,
,
}
;
int
mask
;
const
char
*
ret
;
mask
=
eflags_p
<<
3
;
mask
|=
(
GET_MODE_CLASS
(
GET_MODE
(
cmp_op1
)
)
==
MODE_INT
)
<<
2
;
mask
|=
unordered_p
<<
1
;
mask
|=
stack_top_dies
;
gcc_assert
(
mask
<
16
)
;
ret
=
alt
[
mask
]
;
gcc_assert
(
ret
)
;
return
ret
;
}
}
</s>

Output code for INSN to compare OPERANDS . EFLAGS_P is 1 when fcomi should be used and 2 when fnstsw should be used . UNORDERED_P is true when fucom should be used .


<s>
const
MCExpr
*
SystemZMCInstLower
::
getExpr
(
const
MachineOperand
&
MO
,
MCSymbolRefExpr
::
VariantKind
Kind
)
const
{
const
MCSymbol
*
Symbol
;
bool
HasOffset
=
true
;
switch
(
MO
.
getType
(
)
)
{
case
MachineOperand
::
MO_MachineBasicBlock
:
Symbol
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
HasOffset
=
false
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
Symbol
=
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
Symbol
=
AsmPrinter
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
Symbol
=
AsmPrinter
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
;
HasOffset
=
false
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
Symbol
=
AsmPrinter
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
Symbol
=
AsmPrinter
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
break
;
default
:
llvm_unreachable
(
"unknown operand type"
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
Create
(
Symbol
,
Kind
,
Ctx
)
;
if
(
HasOffset
)
if
(
int64_t
Offset
=
MO
.
getOffset
(
)
)
{
const
MCExpr
*
OffsetExpr
=
MCConstantExpr
::
Create
(
Offset
,
Ctx
)
;
Expr
=
MCBinaryExpr
::
CreateAdd
(
Expr
,
OffsetExpr
,
Ctx
)
;
}
return
Expr
;
}
</s>

Implementation of the SCEVPredicate interface .


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; ARMGISelActualAccessor * GISel = new ARMGISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new ARMCallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new ARMLegalizerInfo ( * I ) ) ; auto * RBI = new ARMRegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( createARMInstructionSelector ( * this , * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" ARM ARM ARM ARM ARM ARM ARM


<s> int arm_mac_accumulator_is_result ( rtx producer , rtx consumer ) { rtx result ; rtx op0 , op1 , acc ; producer = PATTERN ( producer ) ; consumer = PATTERN ( consumer ) ; if ( GET_CODE ( producer ) == COND_EXEC ) producer = COND_EXEC_CODE ( producer ) ; if ( GET_CODE ( consumer ) == COND_EXEC ) consumer = COND_EXEC_CODE ( consumer ) ; if ( GET_CODE ( producer ) != SET ) return 0 ; result = XEXP ( producer , 0 ) ; if ( GET_CODE ( consumer ) != SET ) return 0 ; if ( GET_CODE ( XEXP ( consumer , 1 ) ) == PLUS ) { if ( GET_CODE ( XEXP ( XEXP ( consumer , 1 ) , 0 ) ) != MULT ) return 0 ; op0 = XEXP ( XEXP ( XEXP ( consumer , 1 ) , 0 ) , 0 ) ; op1 = XEXP ( XEXP ( XEXP ( consumer , 1 ) , 0 ) , 1 ) ; acc = XEXP ( XEXP ( consumer , 1 ) , 1 ) ; } else if ( GET_CODE ( XEXP ( consumer , 1 ) ) == MINUS ) { if ( GET_CODE ( XEXP ( XEXP ( consumer , 1 ) , 1 ) ) != MULT ) return 0 ; op0 = XEXP ( XEXP ( XEXP ( consumer , 1 ) , 1 ) , 0 ) ; op1 = XEXP ( XEXP ( XEXP ( consumer , 1 ) , 1 ) , 1 ) ; acc = XEXP ( XEXP ( consumer , 1 ) , 0 ) ; } else return 0 ; return ( reg_overlap_mentioned_p ( result , acc ) && ! reg_overlap_mentioned_p ( result , op0 ) && ! reg_overlap_mentioned_p ( result , op1 ) ) ; } </s>

Return non-zero iff the consumer ( a multiply-accumulate or a multiple-subtract instruction ) has an accumulator dependency on the result of the producer and no other dependency on that result . It does not check if the producer is multiply-accumulate instruction .


<s> BitVector Cpu0RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Cpu0 :: ZERO , Cpu0 :: AT , Cpu0 :: SP , Cpu0 :: LR , Cpu0 :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; const Cpu0MachineFunctionInfo * Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; if ( Cpu0FI -> globalBaseRegFixed ( ) ) Reserved . set ( Cpu0 :: GP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: tLDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s>
void
addInst
(
MachineInstr
*
MI
,
SetVector
<
MachineInstr
*
>
&
Preds
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops: Adding predicated MI: "
<<
*
MI
)
;
if
(
!
Divergent
&&
!
set_difference
(
Preds
,
VPST
->
Predicates
)
.
empty
(
)
)
{
Divergent
=
&
Insts
.
back
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" - has divergent predicate: "
<<
*
Divergent
->
MI
)
;
}
Insts
.
emplace_back
(
MI
,
Preds
)
;
assert
(
Insts
.
size
(
)
<=
4
&&
"Too many instructions in VPT block!"
)
;
}
</s>

ARM
"ARM Loops: Adding predicated MI: "
" - has divergent predicate: "
4
"Too many instructions in VPT block!"


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; const TargetRegisterClass * RC = Subtarget . isPPC64 ( ) ? G8RC : GPRC ; unsigned Reg = findScratchRegister ( II , RS , RC , SPAdj ) ; if ( ! MI . getOperand ( 0 ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCR ) , Reg ) ; else BuildMI ( MBB , II , dl , TII . get ( PPC :: MFCR ) , Reg ) . addReg ( MI . getOperand ( 0 ) . getReg ( ) , RegState :: ImplicitKill ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( PPC :: RLWINM ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( PPCRegisterInfo :: getRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( PPC :: STW ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( 1 ) . getImm ( ) ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> const ARMBaseRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void LEGAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void arm_emit_vfp_multi_reg_pop ( int first_reg , int num_regs , rtx base_reg ) { int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; gcc_assert ( num_regs && num_regs <= 32 ) ; if ( num_regs == 2 && ! arm_arch6 ) { if ( first_reg == 15 ) first_reg -- ; num_regs ++ ; } if ( num_regs > 16 ) { arm_emit_vfp_multi_reg_pop ( first_reg , 16 , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + 16 , num_regs - 16 , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; tmp = gen_rtx_SET ( base_reg , plus_constant ( Pmode , base_reg , 8 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 0 ) = tmp ; for ( j = 0 , i = first_reg ; j < num_regs ; i += 2 ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , 8 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + 1 ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( TARGET_VFP && REGNO ( base_reg ) == IP_REGNUM ) { RTX_FRAME_RELATED_P ( par ) = 1 ; add_reg_note ( par , REG_CFA_DEF_CFA , hard_frame_pointer_rtx ) ; } else arm_add_cfa_adjust_cfa_note ( par , 2 * UNITS_PER_WORD * num_regs , base_reg , base_reg ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi of NUM_REGS consecutive VFP regs , starting at FIRST_REG . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> bool X86TargetLowering :: shouldScalarizeBinop ( SDValue VecOp ) const { EVT VecVT = VecOp . getValueType ( ) ; if ( ! isOperationLegalOrCustomOrPromote ( VecOp . getOpcode ( ) , VecVT ) ) return true ; EVT ScalarVT = VecVT . getScalarType ( ) ; return isOperationLegalOrCustomOrPromote ( VecOp . getOpcode ( ) , ScalarVT ) ; } </s>

Scalar ops always have equal or better analysis/performance/power than the vector equivalent , so this always makes sense if the scalar op is supported .


<s> static void aarch64_restore_callee_saves ( machine_mode mode , poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { rtx base_rtx = stack_pointer_rtx ; unsigned regno ; unsigned regno2 ; poly_int64 offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else emit_move_insn ( reg , mem ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfi_ops ) ; } } </s>

Emit code to restore the callee registers of mode MODE from register number START up to and including LIMIT . Restore from the stack offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true . Write the appropriate REG_CFA_RESTORE notes into CFI_OPS .


"OffsetRegShifted must imply OffsetIsReg!"

"Offset must exists unless register offset is used!"

"Cannot have shift amount without shifted register offset!"

"Cannot have expression offset and register offset!"


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_cpu_attr ) { case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return 2 ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return 5 ; case CPU_POWER8 : return 7 ; case CPU_POWER9 : return 6 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s>
void
LanaiFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
LanaiInstrInfo
&
LII
=
*
static_cast
<
const
LanaiInstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
;
determineFrameLayout
(
MF
)
;
unsigned
StackSize
=
MFI
->
getStackSize
(
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
SW_RI
)
)
.
addReg
(
Lanai
::
FP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
4
)
.
addImm
(
LPAC
::
makePreOp
(
LPAC
::
ADD
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
ADD_I_LO
)
,
Lanai
::
FP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
if
(
StackSize
!=
0
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
SUB_I_LO
)
,
Lanai
::
SP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
StackSize
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
if
(
MFI
->
hasVarSizedObjects
(
)
)
replaceAdjDynAllocPseudo
(
MF
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> extern bool arm_is_constant_pool_ref ( rtx x ) { return ( MEM_P ( x ) && GET_CODE ( XEXP ( x , 0 ) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( x , 0 ) ) ) ; } </s>

return TRUE if x is a reference to a value in a constant pool


<s> void ARM64BranchRelaxation :: verify ( ) { unsigned PrevNum = MF -> begin ( ) -> getNumber ( ) ; for ( MachineBasicBlock & MBB : * MF ) { unsigned Align = MBB . getAlignment ( ) ; unsigned Num = MBB . getNumber ( ) ; assert ( BlockInfo [ Num ] . Offset % ( 1u << Align ) == 0 ) ; assert ( ! Num || BlockInfo [ PrevNum ] . postOffset ( ) <= BlockInfo [ Num ] . Offset ) ; PrevNum = Num ; } } </s>


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , Align ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static bool mips_can_inline_p ( tree caller , tree callee ) { if ( mips_get_compress_mode ( callee ) != mips_get_compress_mode ( caller ) ) return false ; return default_target_can_inline_p ( caller , callee ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; ForCodeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) || FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned long thumb1_compute_save_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( frame_pointer_needed ) mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function .


"execute-only should not generate constant pools"

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } if ( InConstantPool && MI -> getOpcode ( ) != Mips :: CONSTPOOL_ENTRY ) { OutStreamer . EmitDataRegion ( MCDR_DataRegionEnd ) ; InConstantPool = false ; } if ( MI -> getOpcode ( ) == Mips :: CONSTPOOL_ENTRY ) { unsigned LabelId = ( unsigned ) MI -> getOperand ( 0 ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( 1 ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer . EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; } OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( OutStreamer , & * I ) ) continue ; MCInst TmpInst0 ; MCInstLowering . Lower ( I , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>


<s> static inline SlotWithTag getTombstoneKey ( ) { return { - 3 , - 3 ; } </s>

Difference in tombstone is that the Optional is meaningful .


<s> bool LEGInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { bool HasCondBranch = false ; TBB = nullptr ; FBB = nullptr ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == LEG :: B ) { MachineBasicBlock * TargetBB = MI . getOperand ( 0 ) . getMBB ( ) ; if ( HasCondBranch ) { FBB = TargetBB ; } else { TBB = TargetBB ; } } else if ( MI . getOpcode ( ) == LEG :: Bcc ) { MachineBasicBlock * TargetBB = MI . getOperand ( 1 ) . getMBB ( ) ; TBB = TargetBB ; Cond . push_back ( MI . getOperand ( 0 ) ) ; HasCondBranch = true ; } } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; if ( first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != 0 ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) && df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM ; if ( flag_pic && crtl -> uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


"Unexpected fixup kind in fixupNeedsRelaxation()!"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static rtx mips_call_tls_get_addr ( rtx sym , enum mips_symbol_type type , rtx v0 ) { rtx insn , loc , a0 ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Return an instruction sequence that calls __tls_get_addr . SYM is the TLS symbol we are referencing and TYPE is the symbol type to use ( either global dynamic or local dynamic ) . V0 is an RTX for the return value location .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const Thumb1RegisterInfo & MRI , int NumBytes ) { emitThumbRegPlusImmediate ( MBB , MBBI , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , dl ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s>
void
fma_forest
::
dispatch
(
)
{
this
->
m_target_parity
=
this
->
m_roots
->
front
(
)
->
get_parity
(
)
;
int
fpu_balance
=
this
->
m_globals
->
get_fpu_balance
(
)
;
if
(
fpu_balance
!=
0
)
this
->
m_target_parity
=
(
fpu_balance
<
0
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Target parity for forest #%d: %s\n"
,
this
->
m_id
,
this
->
m_target_parity
"odd"
:
"even"
)
;
}
</s>

Dispatch forest to the least utilized pipeline .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SPISD :: NodeType ) Opcode ) { case SPISD :: FIRST_NUMBER : break ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static rtx sh_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , BASE_RETURN_VALUE_REG ( mode ) ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


"Unknown fence ordering in emitLeadingFence"


<s> static void ia64_override_options_after_change ( void ) { if ( optimize >= 3 && ! OPTION_SET_P ( flag_selective_scheduling ) && ! OPTION_SET_P ( flag_selective_scheduling2 ) ) { flag_selective_scheduling2 = 1 ; flag_sel_sched_pipelining = 1 ; } if ( mflag_sched_control_spec == 2 ) { mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0 ; } if ( flag_sel_sched_pipelining && flag_auto_inc_dec ) { flag_auto_inc_dec = 0 ; } } </s>


<s> static bool sparc_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_VECTOR : return false ; case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return sparc_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) || sparc_cannot_force_const_mem ( mode , XEXP ( x , 1 ) ) ; case UNSPEC : return true ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> unsigned VETargetLowering :: getJumpTableEncoding ( ) const { if ( isPositionIndependent ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; const bool isPPC64 = MBB . getParent ( ) -> getSubtarget < PPCSubtarget > ( ) . isPPC64 ( ) ; const unsigned TOCReg = isPPC64 ? PPC :: X2 : PPC :: R2 ; for ( auto & MI : MBB ) { if ( ! hasTOCLoReloc ( MI ) ) continue ; MI . addOperand ( MachineOperand :: CreateReg ( TOCReg , false , true ) ) ; Changed = true ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


Return a function that will generate a check for speculation TS with mode MODE_NO . If simple check is needed , pass true for SIMPLE_CHECK_P . If clearing check is needed , pass true for CLEARING_CHECK_P .


<s> static void ix86_expand_ashl_const ( rtx operand , int count , machine_mode mode ) { if ( count == 1 || ( count * ix86_cost -> add <= ix86_cost -> shift_const && ! optimize_insn_for_size_p ( ) ) ) { while ( count -- > 0 ) emit_insn ( gen_add2_insn ( operand , operand ) ) ; } else { rtx ( * insn ) ( rtx , rtx , rtx ) ; insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3 ; emit_insn ( insn ( operand , operand , GEN_INT ( count ) ) ) ; } } </s>

Helper function of ix86_split_ashl used to generate an SImode/DImode left shift by a constant , either using a single shift or a sequence of add instructions .


<s> static rtx mips_call_tls_get_addr ( rtx sym , enum mips_symbol_type type , rtx v0 ) { rtx insn , loc , tga , a0 ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( Pmode , a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; tga = gen_rtx_MEM ( Pmode , mips_tls_symbol ) ; insn = emit_call_insn ( gen_call_value ( v0 , tga , const0_rtx , const0_rtx ) ) ; CONST_OR_PURE_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , v0 ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>


"this definition requires the MVE ISA extension"

Implement # pragma GCC arm `` arm_mve_types.h '' .


<s> bool EquivSubstPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; if ( ! RNG ) RNG . reset ( Fn . getFunction ( ) -> getParent ( ) -> createRNG ( this ) ) ; bool Changed = false ; std :: vector < const EquivInsnFilter * > Candidates ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ) { ++ PreEquivSubstInstructionCount ; Candidates . clear ( ) ; for ( size_t i = 0 ; i < array_lengthof ( Filters ) ; i ++ ) if ( Filters [ i ] -> check ( * BB , * I ) ) Candidates . push_back ( Filters [ i ] ) ; if ( Candidates . empty ( ) ) { ++ I ; continue ; } unsigned int Roll = RNG -> Random ( 100 ) ; ++ EquivSubstCandidates ; if ( Roll >= multicompiler :: EquivSubstPercentage ) { ++ I ; continue ; } unsigned int Pick = RNG -> Random ( Candidates . size ( ) ) ; MachineBasicBlock :: iterator J = I ; ++ I ; Candidates [ Pick ] -> subst ( * BB , TII , J ) ; Changed = true ; ++ EquivSubstituted ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
unsigned
MipsCodeEmitter
::
getBranchTarget21OpValue
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
llvm_unreachable
(
"Unimplemented function."
)
;
return
0
;
}
</s>

getBranchTarget21OpValue - Return binary encoding of the branch target operand .


"llvm does not support 'Q', 'R', and 'H' modifiers!"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const MCPhysReg * Comet2RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 Intel-Style Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned AArch64TargetLowering :: getByValTypeAlignment ( Type * Ty ) const { return 4 ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> void xstormy16_split_cbranch ( machine_mode mode , rtx label , rtx comparison , rtx dest ) { rtx op0 = XEXP ( comparison , 0 ) ; rtx op1 = XEXP ( comparison , 1 ) ; rtx_insn * seq , * last_insn ; rtx compare ; start_sequence ( ) ; xstormy16_expand_arith ( mode , COMPARE , dest , op0 , op1 ) ; seq = get_insns ( ) ; end_sequence ( ) ; gcc_assert ( INSN_P ( seq ) ) ; last_insn = seq ; while ( NEXT_INSN ( last_insn ) != NULL_RTX ) last_insn = NEXT_INSN ( last_insn ) ; compare = SET_SRC ( XVECEXP ( PATTERN ( last_insn ) , 0 , 0 ) ) ; PUT_CODE ( XEXP ( compare , 0 ) , GET_CODE ( comparison ) ) ; XEXP ( compare , 1 ) = gen_rtx_LABEL_REF ( VOIDmode , label ) ; emit_insn ( seq ) ; } </s>

Take a SImode conditional branch , one of GT/LE/GTU/LEU , and split the arithmetic operation . Most of the work is done by xstormy16_expand_arith .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return nullptr ; } </s>

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER


<s> void X86ATTInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '%' << getRegisterName ( RegNo ) ; } </s>


"FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD "

"instructions with NOPs and floating-point store"


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return PPCMaterializeInt ( C , VT , VT != MVT :: i1 ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static bool mips_orphaned_high_part_p ( mips_offset_table * htab , rtx_insn * insn ) { enum mips_symbol_type type ; rtx x , set ; set = single_set ( insn ) ; if ( set ) { x = SET_SRC ( set ) ; if ( GET_CODE ( x ) == HIGH && absolute_symbolic_operand ( XEXP ( x , 0 ) , VOIDmode ) ) return ! mips_lo_sum_offset_lookup ( htab , XEXP ( x , 0 ) , NO_INSERT ) ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_LOAD_GOT && mips_symbolic_constant_p ( XVECEXP ( x , 0 , 1 ) , SYMBOL_CONTEXT_LEA , & type ) && type == SYMBOL_GOTOFF_PAGE ) return ! mips_lo_sum_offset_lookup ( htab , XVECEXP ( x , 0 , 1 ) , NO_INSERT ) ; } return false ; } </s>

Return true if INSN is a SET of an orphaned high-part relocation . HTAB is a hash table of mips_lo_sum_offsets that describes all the LO_SUMs in the current function .


<s> bool isThumb ( ) const { return STI . getFeatureBits ( ) [ ARM :: ModeThumb ] ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> static void mips_ls2_init_dfa_post_cycle_insn ( void ) { start_sequence ( ) ; emit_insn ( gen_ls2_alu1_turn_enabled_insn ( ) ) ; mips_ls2 . alu1_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_alu2_turn_enabled_insn ( ) ) ; mips_ls2 . alu2_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_falu1_turn_enabled_insn ( ) ) ; mips_ls2 . falu1_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; emit_insn ( gen_ls2_falu2_turn_enabled_insn ( ) ) ; mips_ls2 . falu2_turn_enabled_insn = get_insns ( ) ; end_sequence ( ) ; mips_ls2 . alu1_core_unit_code = get_cpu_unit_code ( "ls2_alu1_core" ) ; mips_ls2 . alu2_core_unit_code = get_cpu_unit_code ( "ls2_alu2_core" ) ; mips_ls2 . falu1_core_unit_code = get_cpu_unit_code ( "ls2_falu1_core" ) ; mips_ls2 . falu2_core_unit_code = get_cpu_unit_code ( "ls2_falu2_core" ) ; } </s>

Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2 .


<s> char * function_builder :: finish_name ( ) { obstack_1grow ( & m_string_obstack , 0 ) ; return ( char * ) obstack_finish ( & m_string_obstack ) ; } </s>

Zero-terminate and complete the function name being built .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned opc = N -> getOpcode ( ) ; switch ( opc ) { default : break ; case ISD :: ADDE : return PerformADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SDIVREM : case ISD :: UDIVREM : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SETCC : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return PerformANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::SDIVREM ISD::UDIVREM ISD::SETCC ISD::AND ISD::OR


<s> static void i386_pe_seh_fini ( FILE * f ) { if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; fputs ( "\t.seh_endproc\n" , f ) ; } </s>

Emit an assembler directive for the end of the function .


<s> static void ATTRIBUTE_UNUSED x86_64_elf_unique_section ( tree decl , int reloc ) { if ( ix86_in_large_data_p ( decl ) ) { const char * prefix = NULL ; bool one_only = DECL_COMDAT_GROUP ( decl ) && ! HAVE_COMDAT_GROUP ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_DATA : case SECCAT_DATA_REL : case SECCAT_DATA_REL_LOCAL : case SECCAT_DATA_REL_RO : case SECCAT_DATA_REL_RO_LOCAL : prefix = one_only ? ".ld" : ".ldata" ; break ; case SECCAT_BSS : prefix = one_only ? ".lb" : ".lbss" ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : prefix = one_only ? ".lr" : ".lrodata" ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( prefix ) { const char * name , * linkonce ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; linkonce = one_only ? ".gnu.linkonce" : "" ; string = ACONCAT ( ( linkonce , prefix , "." , name , NULL ) ) ; set_decl_section_name ( decl , string ) ; return ; } } default_unique_section ( decl , reloc ) ; } </s>

Build up a unique section name , expressed as a STRING_CST node , and assign it to DECL_SECTION_NAME ( decl ) . RELOC indicates whether the initial value of EXP requires link-time relocations .


<s>
unsigned
SparcInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
SP
::
BA
&&
I
->
getOpcode
(
)
!=
SP
::
BCOND
&&
I
->
getOpcode
(
)
!=
SP
::
FBCOND
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

Sparc
Sparc
"code size not handled"
0
SP::BA
SP::BCOND
SP::FBCOND


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MipsMCInstLower MCInstLowering ( Mang , * MF , * this ) ; unsigned Opc = MI -> getOpcode ( ) ; MCInst TmpInst0 ; SmallVector < MCInst , 4 > MCInsts ; MCInstLowering . Lower ( MI , TmpInst0 ) ; if ( ! OutStreamer . hasRawTextSupport ( ) && isDirective ( Opc ) ) return ; if ( isUnalignedLoadStore ( Opc ) ) { if ( OutStreamer . hasRawTextSupport ( ) ) { MCInst Directive ; Directive . setOpcode ( Mips :: MACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; Directive . setOpcode ( Mips :: NOMACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; } else { MCInstLowering . LowerUnalignedLoadStore ( MI , MCInsts ) ; for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; } return ; } if ( ! OutStreamer . hasRawTextSupport ( ) ) { if ( Opc == Mips :: CPLOAD ) MCInstLowering . LowerCPLOAD ( MI , MCInsts ) ; else if ( Opc == Mips :: CPRESTORE ) MCInstLowering . LowerCPRESTORE ( MI , MCInsts ) ; if ( ! MCInsts . empty ( ) ) { for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; return ; } } if ( Opc == Mips :: SETGP01 ) { MCInstLowering . LowerSETGP01 ( MI , MCInsts ) ; for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; return ; } OutStreamer . EmitInstruction ( TmpInst0 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
void
final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
opvec
ATTRIBUTE_UNUSED
,
int
noperands
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_DUMPISIZE
)
fprintf
(
asm_out_file
,
"\n! at %04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
TARGET_RELAX
)
{
rtx
note
;
note
=
find_reg_note
(
insn
,
REG_LABEL_OPERAND
,
NULL_RTX
)
;
if
(
note
)
{
rtx
pattern
;
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
switch
(
GET_CODE
(
pattern
)
)
{
case
SET
:
if
(
GET_CODE
(
SET_SRC
(
pattern
)
)
!=
CALL
&&
get_attr_type
(
insn
)
!=
TYPE_SFUNC
)
{
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
}
case
CALL
:
asm_fprintf
(
asm_out_file
,
"\t.uses %LL%d\n"
,
CODE_LABEL_NUMBER
(
XEXP
(
note
,
0
)
)
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
}
}
</s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s> static bool chain_contains_only_swaps ( swap_web_entry * insn_entry , struct df_link * link , enum chain_purpose purpose ) { if ( ! link ) return false ; for ( ; link ; link = link -> next ) { if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( DF_REF_REG ( link -> ref ) ) ) ) continue ; if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx reached_insn = DF_REF_INSN ( link -> ref ) ; unsigned uid = INSN_UID ( reached_insn ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( reached_insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load || insn_entry [ uid ] . is_store ) return false ; if ( purpose == FOR_LOADS ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( use ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_def_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || ! insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } else if ( purpose == FOR_STORES ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( def ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_use_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_use_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } } return true ; } </s>

Return true if the UD or DU chain headed by LINK is non-empty , and every entry on the chain references an insn that is a register swap . Furthermore , if PURPOSE is FOR_LOADS , each such register swap must have only permuting loads as reaching defs . If PURPOSE is FOR_STORES , each such register swap must have only register swaps or permuting stores as reached uses .


<s> rtx sh_find_equiv_gbr_addr ( rtx_insn * insn , rtx mem ) { if ( ! MEM_P ( mem ) || gbr_address_mem ( mem , GET_MODE ( mem ) ) ) return NULL_RTX ; if ( side_effects_p ( XEXP ( mem , 0 ) ) ) return NULL_RTX ; if ( df == NULL ) return NULL_RTX ; base_reg_disp gbr_disp = sh_find_base_reg_disp ( insn , XEXP ( mem , 0 ) ) ; if ( gbr_disp . is_reg ( ) && REGNO ( gbr_disp . reg ( ) ) == GBR_REG ) { for ( df_ref d = DF_REG_DEF_CHAIN ( GBR_REG ) ; d != NULL ; d = DF_REF_NEXT_REG ( d ) ) { if ( CALL_P ( DF_REF_INSN ( d ) ) ) { if ( REGNO_REG_SET_P ( regs_invalidated_by_call_regset , GBR_REG ) ) return NULL_RTX ; else continue ; } else return NULL_RTX ; } rtx disp = GEN_INT ( gbr_disp . disp ( ) ) ; if ( gbr_displacement ( disp , GET_MODE ( mem ) ) ) return gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , GBR_REG ) , disp ) ; } return NULL_RTX ; } </s>

Given an insn and a memory operand , try to find an equivalent GBR based memory address and return the corresponding new memory address . Return NULL_RTX if not found .


<s> void TeeRISCFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; TeeRISCMachineFunctionInfo * TFI = MF . getInfo < TeeRISCMachineFunctionInfo > ( ) ; const TeeRISCInstrInfo & TII = * static_cast < const TeeRISCInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = TFI -> getFPStackOffset ( ) ; int RAOffset = TFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( TeeRISC :: ADD ) , TeeRISC :: SP ) . addReg ( TeeRISC :: FP ) . addReg ( TeeRISC :: ZERO ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TeeRISC :: LD ) , TeeRISC :: FP ) . addReg ( TeeRISC :: SP ) . addImm ( FPOffset ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( TeeRISC :: LD ) , TeeRISC :: LR ) . addReg ( TeeRISC :: SP ) . addImm ( RAOffset ) ; } int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII . get ( TeeRISC :: ADD_IMM ) , TeeRISC :: SP ) . addReg ( TeeRISC :: SP ) . addImm ( StackSize ) ; } } </s>

TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC::ADD TeeRISC::SP TeeRISC::FP TeeRISC::ZERO TeeRISC::LD TeeRISC::FP TeeRISC::SP TeeRISC::LD TeeRISC::LR TeeRISC::SP TeeRISC::ADD_IMM TeeRISC::SP TeeRISC::SP


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createX86MachObjectWriter ( OS , true , MachO :: CPU_TYPE_X86_64 , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
", "
<<
StringRef
(
RegIdx
.
Tok
.
Data
,
RegIdx
.
Tok
.
Length
)
<<
">"
;
break
;
case
k_Token
:
OS
<<
getToken
(
)
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
case
k_RegPair
:
OS
<<
"RegPair<"
<<
RegIdx
.
Index
<<
","
<<
RegIdx
.
Index
+
1
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
BITCAST
:
ReplaceBITCASTResults
(
N
,
Results
,
DAG
)
;
return
;
case
AArch64ISD
::
SADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
SADDV
)
;
return
;
case
AArch64ISD
::
UADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
UADDV
)
;
return
;
case
AArch64ISD
::
SMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMIN
,
AArch64ISD
::
SMINV
)
;
return
;
case
AArch64ISD
::
UMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMIN
,
AArch64ISD
::
UMINV
)
;
return
;
case
AArch64ISD
::
SMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMAX
,
AArch64ISD
::
SMAXV
)
;
return
;
case
AArch64ISD
::
UMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMAX
,
AArch64ISD
::
UMAXV
)
;
return
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_128Results
(
N
,
Results
,
DAG
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static const char * csky_mangle_type ( const_tree type ) { if ( TYPE_NAME ( type ) && TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL && DECL_NAME ( TYPE_NAME ( type ) ) && ! strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( TYPE_NAME ( type ) ) ) , "__fp16" ) ) return "__fp16" ; return NULL ; } </s>


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( TT . isOSDarwin ( ) || ReserveX18 ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
char
*
output_cbranch
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
rtx
cc_reg
=
XEXP
(
op
,
0
)
;
machine_mode
mode
=
GET_MODE
(
cc_reg
)
;
int
cc_regno
=
REGNO
(
cc_reg
)
CR0_REGNO
;
int
need_longbranch
=
label
!=
&&
get_attr_length
(
insn
)
==
8
;
int
really_reversed
=
reversed
^
need_longbranch
;
char
*
s
=
string
;
const
char
*
ccode
;
const
char
*
pred
;
rtx
note
;
validate_condition_mode
(
code
,
mode
)
;
if
(
really_reversed
)
{
if
(
mode
==
CCFPmode
)
code
=
reverse_condition_maybe_unordered
(
code
)
;
else
code
=
reverse_condition
(
code
)
;
}
if
(
(
!
TARGET_FPRS
&&
TARGET_HARD_FLOAT
)
&&
mode
==
CCFPmode
)
{
switch
(
code
)
{
case
EQ
:
code
=
GT
;
break
;
case
NE
:
code
=
UNLE
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
switch
(
code
)
{
case
NE
:
case
LTGT
:
ccode
=
"ne"
;
break
;
case
EQ
:
case
UNEQ
:
ccode
=
"eq"
;
break
;
case
GE
:
case
GEU
:
ccode
=
"ge"
;
break
;
case
GT
:
case
GTU
:
case
UNGT
:
ccode
=
"gt"
;
break
;
case
LE
:
case
LEU
:
ccode
=
"le"
;
break
;
case
LT
:
case
LTU
:
case
UNLT
:
ccode
=
"lt"
;
break
;
case
UNORDERED
:
ccode
=
"un"
;
break
;
case
ORDERED
:
ccode
=
"nu"
;
break
;
case
UNGE
:
ccode
=
"nl"
;
break
;
case
UNLE
:
ccode
=
"ng"
;
break
;
default
:
gcc_unreachable
(
)
;
}
pred
=
""
;
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
;
if
(
note
!=
NULL_RTX
)
{
int
prob
=
XINT
(
note
,
0
)
REG_BR_PROB_BASE
/
2
;
if
(
rs6000_always_hint
||
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
100
*
48
&&
br_prob_note_reliable_p
(
note
)
)
)
{
if
(
abs
(
prob
)
>
REG_BR_PROB_BASE
/
20
&&
(
(
prob
>
0
)
^
need_longbranch
)
)
pred
=
"+"
;
else
pred
=
"-"
;
}
}
if
(
label
==
)
s
+=
sprintf
(
s
,
"b%slr%s "
,
ccode
,
pred
)
;
else
s
+=
sprintf
(
s
,
"b%s%s "
,
ccode
,
pred
)
;
if
(
reg_names
[
cc_regno
+
CR0_REGNO
]
[
0
]
==
'%'
)
*
s
++
=
'%'
;
s
+=
sprintf
(
s
,
"%s"
,
reg_names
[
cc_regno
+
CR0_REGNO
]
)
;
if
(
label
!=
)
{
if
(
need_longbranch
)
s
+=
sprintf
(
s
,
",$+8\n\tb %s"
,
label
)
;
else
s
+=
sprintf
(
s
,
",%s"
,
label
)
;
}
return
string
;
}
</s>

Output a conditional branch to LABEL . CODE is the comparison code . CC_MODE is the mode of the CC register . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the instruction .


<s>
bool
ARMAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

ARM
ARM
0
"unexpected inline asm memory operand"
"["
"]"


<s> static section * mips_function_rodata_section ( tree decl ) { if ( ! TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD ) return default_function_rodata_section ( decl ) ; if ( decl && DECL_SECTION_NAME ( decl ) ) { const char * name = DECL_SECTION_NAME ( decl ) ; if ( DECL_COMDAT_GROUP ( decl ) && strncmp ( name , ".gnu.linkonce.t." , 16 ) == 0 ) { char * rname = ASTRDUP ( name ) ; rname [ 14 ] = 'd' ; return get_section ( rname , SECTION_LINKONCE | SECTION_WRITE , decl ) ; } else if ( flag_function_sections && flag_data_sections && strncmp ( name , ".text." , 6 ) == 0 ) { char * rname = ASTRDUP ( name ) ; memcpy ( rname + 1 , "data" , 4 ) ; return get_section ( rname , SECTION_WRITE , decl ) ; } } return data_section ; } </s>

Implement TARGET_ASM_FUNCTION_RODATA_SECTION . The complication here is that , with the combination TARGET_ABICALLS & & ! TARGET_GPWORD , jump tables will use absolute addresses , and should therefore not be included in the read-only part of a DSO . Handle such cases by selecting a normal data section instead of a read-only one . The logic apes that in default_function_rodata_section .


"invalid conversion from type %<bfloat16_t%>"

"invalid conversion to type %<bfloat16_t%>"

Return the diagnostic message string if conversion from FROMTYPE to TOTYPE is not allowed , NULL otherwise .


"relaxInstruction() should not be called"

Relax the instruction in the given fragment to the next wider instruction .


<s> bool isReg ( ) const override { return Kind == Register ; } </s>


<s> rtx scalar_chain :: convert_compare ( rtx op1 , rtx op2 , rtx_insn * insn ) { rtx src , tmp ; if ( op2 != const0_rtx ) { convert_op ( & op1 , insn ) ; convert_op ( & op2 , insn ) ; if ( MEM_P ( op1 ) && MEM_P ( op2 ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , op1 ) , insn ) ; src = tmp ; } else src = op1 ; src = gen_rtx_XOR ( vmode , src , op2 ) ; } else if ( GET_CODE ( op1 ) == AND && GET_CODE ( XEXP ( op1 , 0 ) ) == NOT ) { rtx op11 = XEXP ( XEXP ( op1 , 0 ) , 0 ) ; rtx op12 = XEXP ( op1 , 1 ) ; convert_op ( & op11 , insn ) ; convert_op ( & op12 , insn ) ; if ( ! REG_P ( op11 ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , op11 ) , insn ) ; op11 = tmp ; } src = gen_rtx_AND ( vmode , gen_rtx_NOT ( vmode , op11 ) , op12 ) ; } else if ( GET_CODE ( op1 ) == AND ) { rtx op11 = XEXP ( op1 , 0 ) ; rtx op12 = XEXP ( op1 , 1 ) ; convert_op ( & op11 , insn ) ; convert_op ( & op12 , insn ) ; if ( ! REG_P ( op11 ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , op11 ) , insn ) ; op11 = tmp ; } return gen_rtx_UNSPEC ( CCmode , gen_rtvec ( 2 , op11 , op12 ) , UNSPEC_PTEST ) ; } else { convert_op ( & op1 , insn ) ; src = op1 ; } if ( ! REG_P ( src ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , src ) , insn ) ; src = tmp ; } if ( vmode == V2DImode ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_vec_interleave_lowv2di ( tmp , src , src ) , insn ) ; src = tmp ; } else if ( vmode == V4SImode ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_sse2_pshufd ( tmp , src , const0_rtx ) , insn ) ; src = tmp ; } return gen_rtx_UNSPEC ( CCmode , gen_rtvec ( 2 , src , src ) , UNSPEC_PTEST ) ; } </s>


<s> const ARMRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getNewValOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( shouldInlineQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AI ) ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> bool ia64_expand_vecint_minmax ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx xops [ 6 ] ; if ( mode == V8QImode && ( code == UMIN || code == UMAX ) ) return false ; if ( mode == V4HImode && ( code == SMIN || code == SMAX ) ) return false ; if ( mode == V4HImode && code == UMAX ) { rtx x , tmp = gen_reg_rtx ( mode ) ; x = gen_rtx_US_MINUS ( mode , operands [ 1 ] , operands [ 2 ] ) ; emit_insn ( gen_rtx_SET ( tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ 0 ] , tmp , operands [ 2 ] ) ) ; return true ; } xops [ 0 ] = operands [ 0 ] ; xops [ 4 ] = xops [ 1 ] = operands [ 1 ] ; xops [ 5 ] = xops [ 2 ] = operands [ 2 ] ; switch ( code ) { case UMIN : code = LTU ; break ; case UMAX : code = GTU ; break ; case SMIN : code = LT ; break ; case SMAX : code = GT ; break ; default : gcc_unreachable ( ) ; } xops [ 3 ] = gen_rtx_fmt_ee ( code , VOIDmode , operands [ 1 ] , operands [ 2 ] ) ; ia64_expand_vecint_cmov ( xops ) ; return true ; } </s>

Emit an integral vector min or max operation . Return true if all done .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; return std :: make_pair ( domain , domain && lookup ( MI -> getOpcode ( ) , domain ) ? 0xe : 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> static void ix86_emit_mode_set ( int entity , int mode , int prev_mode ATTRIBUTE_UNUSED , HARD_REG_SET regs_live ) { switch ( entity ) { case X86_DIRFLAG : if ( mode == X86_DIRFLAG_RESET ) emit_insn ( gen_cld ( ) ) ; break ; case AVX_U128 : if ( mode == AVX_U128_CLEAN ) ix86_avx_emit_vzeroupper ( regs_live ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Generate one or more insns to set ENTITY to MODE . HARD_REG_LIVE is the set of hard registers live at the point where the insn ( s ) are to be inserted .


<s> rtx pa_return_addr_rtx ( int count , rtx frameaddr ) { rtx label ; rtx rp ; rtx saved_rp ; rtx ins ; HOST_WIDE_INT insns [ 4 ] ; int i , len ; if ( count != 0 ) return NULL_RTX ; rp = get_hard_reg_initial_val ( Pmode , 2 ) ; if ( TARGET_64BIT || TARGET_NO_SPACE_REGS ) return rp ; saved_rp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( saved_rp , rp ) ; ins = copy_to_reg ( gen_rtx_AND ( Pmode , rp , MASK_RETURN_ADDR ) ) ; label = gen_label_rtx ( ) ; if ( TARGET_PA_20 ) { insns [ 0 ] = 0x4bc23fd1 ; insns [ 1 ] = - 398405630 ; len = 2 ; } else { insns [ 0 ] = 0x4bc23fd1 ; insns [ 1 ] = 0x004010a1 ; insns [ 2 ] = 0x00011820 ; insns [ 3 ] = - 532676606 ; len = 4 ; } for ( i = 0 ; i < len ; i ++ ) { rtx op0 = gen_rtx_MEM ( SImode , plus_constant ( Pmode , ins , i * 4 ) ) ; rtx op1 = GEN_INT ( insns [ i ] ) ; emit_cmp_and_jump_insns ( op0 , op1 , NE , NULL , SImode , 0 , label ) ; } emit_move_insn ( saved_rp , gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant ( Pmode , frameaddr , - 24 ) ) ) ) ; emit_label ( label ) ; return saved_rp ; } </s>

Fetch the return address for the frame COUNT steps up from the current frame , after the prologue . FRAMEADDR is the frame pointer of the COUNT frame . We want to ignore any export stub remnants here . To handle this , we examine the code at the return address , and if it is an export stub , we return a memory rtx for the stub return address stored at frame-24 . The value returned is used in two different ways : 1 . To find a function 's caller . 2 . To change the return address for a function . This function handles most instances of case 1 ; however , it will fail if there are two levels of stubs to execute on the return path . The only way I believe that can happen is if the return value needs a parameter relocation , which never happens for C code . This function handles most instances of case 2 ; however , it will fail if we did not originally have stub code on the return path but will need stub code on the new return path . This can happen if the caller & callee are both in the main program , but the new return location is in a shared library .


"%qs is only valid for the cell processor"

"%qs requires ISA 3.0 IEEE 128-bit floating point"

"%qs requires the %qs (or newer), and %qs or %qs options"

"%qs is not supported with the current options"

Raise an error message for a builtin function that is called without the appropriate target options being set .


<s> bool Warning ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Warning ( L , Msg , Ranges ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> static void mips_sim_next_cycle ( struct mips_sim * state ) { state -> time ++ ; state -> insns_left = state -> issue_rate ; state_transition ( state -> dfa_state , 0 ) ; } </s>


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , ( MCFixupKind ) Mips :: fixup_Mips_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static tree aarch64_get_attributes ( unsigned int f , machine_mode mode ) { tree attrs = NULL_TREE ; if ( ! aarch64_modifies_global_state_p ( f , mode ) ) { if ( aarch64_reads_global_state_p ( f , mode ) ) attrs = aarch64_add_attribute ( "pure" , attrs ) ; else attrs = aarch64_add_attribute ( "const" , attrs ) ; } if ( ! flag_non_call_exceptions || ! aarch64_could_trap_p ( f , mode ) ) attrs = aarch64_add_attribute ( "nothrow" , attrs ) ; return aarch64_add_attribute ( "leaf" , attrs ) ; } </s>

Return the appropriate function attributes .


<s> bool rs6000_overloaded_builtin_p ( enum rs6000_builtins fncode ) { return ( rs6000_builtin_info [ ( int ) fncode ] . attr & RS6000_BTC_OVERLOADED ) != 0 ; } </s>

Return true if a builtin function is overloaded .


<s> void ia64_emit_cond_move ( rtx op0 , rtx op1 , rtx cond ) { rtx insn , first = get_last_insn ( ) ; emit_move_insn ( op0 , op1 ) ; for ( insn = get_last_insn ( ) ; insn != first ; insn = PREV_INSN ( insn ) ) if ( INSN_P ( insn ) ) PATTERN ( insn ) = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , PATTERN ( insn ) ) ; } </s>

Split a move from OP1 to OP0 conditional on COND .


<s> static bool arm_scalar_mode_supported_p ( scalar_mode mode ) { if ( mode == HFmode ) return ( arm_fp16_format != ARM_FP16_FORMAT_NONE ) ; else if ( ALL_FIXED_POINT_MODE_P ( mode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Implement TARGET_SCALAR_MODE_SUPPORTED_P . This simply adds HFmode as a supported mode ; even though we do n't implement arithmetic on this type directly , it 's supported by optabs conversions , much the way the double-word arithmetic is special-cased in the default hook .


<s> bool MipsSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( isGP64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> static bool rs6000_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( DEFAULT_ABI == ABI_AIX || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if TYPE must be passed on the stack and not in registers .


<s> bool splitFramePushPop ( ) const { return isTargetMachO ( ) ; } </s>

Returns true if the frame setup is split into two separate pushes ( first r0-r7 , lr then r8-r11 ) , principally so that the frame pointer is adjacent to lr .


<s> SDValue ARM64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case ARM64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> int MipsAsmParser :: tryParseRegister ( StringRef Mnemonic ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; else return RegNum ; if ( isMips64 ( ) && RegNum == Mips :: ZERO_64 ) { if ( Mnemonic . find ( "ddiv" ) != StringRef :: npos ) RegNum = Mips :: ZERO ; } return RegNum ; } </s>

tryParseRegister - parse one register if possible

Mips Mips 1 Mips Mips::ZERO_64 "ddiv" Mips::ZERO


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( createX86NaClRewritePass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> rtx ix86_build_const_vector ( machine_mode mode , bool vect , rtx value ) { int i , n_elt ; rtvec v ; machine_mode scalar_mode ; switch ( mode ) { case E_V64QImode : case E_V32QImode : case E_V16QImode : case E_V32HImode : case E_V16HImode : case E_V8HImode : case E_V16SImode : case E_V8SImode : case E_V4SImode : case E_V2SImode : case E_V8DImode : case E_V4DImode : case E_V2DImode : gcc_assert ( vect ) ; case E_V8HFmode : case E_V16HFmode : case E_V32HFmode : case E_V16SFmode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : n_elt = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( n_elt ) ; scalar_mode = GET_MODE_INNER ( mode ) ; RTVEC_ELT ( v , 0 ) = value ; for ( i = 1 ; i < n_elt ; ++ i ) RTVEC_ELT ( v , i ) = vect ? value : CONST0_RTX ( scalar_mode ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; default : gcc_unreachable ( ) ; } } </s>

A subroutine of ix86_build_signbit_mask . If VECT is true , then replicate the value for all elements of the vector register .


<s> TargetLowering :: ConstraintWeight SparcTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; } break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


Returns the index for the immediate for a given instruction .


Change register usage conditional on target flags .


<s> static AArch64Operand * CreateReg ( unsigned RegNum , bool isVector , SMLoc S , SMLoc E , MCContext & Ctx ) { AArch64Operand * Op = new AArch64Operand ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . isVector = isVector ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { Register PredReg ; ARMCC :: CondCodes CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return nullptr ; MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ; CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return CommutedMI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

ARM ARM ARM::MOVCCr ARM::t2MOVCCr ARMCC::CondCodes ARMCC::AL ARM::CPSR ARMCC::getOppositeCondition


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BEQ_MM
:
return
Mips
::
BNE_MM
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BNE_MM
:
return
Mips
::
BEQ_MM
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
case
Mips
::
BEQZC_MM
:
return
Mips
::
BNEZC_MM
;
case
Mips
::
BNEZC_MM
:
return
Mips
::
BEQZC_MM
;
case
Mips
::
BEQZC
:
return
Mips
::
BNEZC
;
case
Mips
::
BNEZC
:
return
Mips
::
BEQZC
;
case
Mips
::
BEQC
:
return
Mips
::
BNEC
;
case
Mips
::
BNEC
:
return
Mips
::
BEQC
;
case
Mips
::
BGTZC
:
return
Mips
::
BLEZC
;
case
Mips
::
BGEZC
:
return
Mips
::
BLTZC
;
case
Mips
::
BLTZC
:
return
Mips
::
BGEZC
;
case
Mips
::
BLEZC
:
return
Mips
::
BGTZC
;
case
Mips
::
BEQZC64
:
return
Mips
::
BNEZC64
;
case
Mips
::
BNEZC64
:
return
Mips
::
BEQZC64
;
case
Mips
::
BEQC64
:
return
Mips
::
BNEC64
;
case
Mips
::
BNEC64
:
return
Mips
::
BEQC64
;
case
Mips
::
BGEC64
:
return
Mips
::
BLTC64
;
case
Mips
::
BGEUC64
:
return
Mips
::
BLTUC64
;
case
Mips
::
BLTC64
:
return
Mips
::
BGEC64
;
case
Mips
::
BLTUC64
:
return
Mips
::
BGEUC64
;
case
Mips
::
BGTZC64
:
return
Mips
::
BLEZC64
;
case
Mips
::
BGEZC64
:
return
Mips
::
BLTZC64
;
case
Mips
::
BLTZC64
:
return
Mips
::
BGEZC64
;
case
Mips
::
BLEZC64
:
return
Mips
::
BGTZC64
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > RetInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; ArgInfo ArgRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( DL , ArgRetInfo , 0 , RetInfos , OrigArgIndices ) ; SmallVector < ISD :: OutputArg , 8 > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; MipsOutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> Optional < ParamLoadedValue > ARMBaseInstrInfo :: describeLoadedValue ( const MachineInstr & MI , Register Reg ) const { if ( auto DstSrcPair = isCopyInstrImpl ( MI ) ) { Register DstReg = DstSrcPair -> Destination -> getReg ( ) ; if ( DstReg != Reg ) return None ; } return TargetInstrInfo :: describeLoadedValue ( MI , Reg ) ; } </s>

Produce the expression describing the MI loading a value into the physical register Reg .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
TM
=
&
Func
.
getTarget
(
)
;
const
X86Subtarget
&
ST
=
TM
->
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
static_cast
<
const
X86InstrInfo
*
>
(
TM
->
getSubtargetImpl
(
)
->
getInstrInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .