<s> MipsInstrInfo :: BranchType MipsInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify , SmallVectorImpl < MachineInstr * > & BranchInstrs ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugValue ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return BT_NoBranch ; } MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; if ( ++ I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_CondUncond ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static bool sparc_cannot_force_const_mem ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_VECTOR : return false ; case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return sparc_cannot_force_const_mem ( XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( XEXP ( x , 0 ) ) || sparc_cannot_force_const_mem ( XEXP ( x , 1 ) ) ; case UNSPEC : return true ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> unsigned int vectors_per_tuple ( ) const override { return m_vectors_per_tuple ; } </s>

If the function operates on tuples of vectors , return the number of vectors in the tuples , otherwise return 1 .


<s> bool ix86_function_arg_regno_p ( int regno ) { int i ; enum calling_abi call_abi ; const int * parm_regs ; if ( TARGET_MPX && BND_REGNO_P ( regno ) ) return true ; if ( ! TARGET_64BIT ) { if ( TARGET_MACHO ) return ( regno < REGPARM_MAX || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ! fixed_regs [ regno ] ) ) ; else return ( regno < REGPARM_MAX || ( TARGET_MMX && MMX_REGNO_P ( regno ) && ( regno < FIRST_MMX_REG + MMX_REGPARM_MAX ) ) || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) ) ; } if ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) return true ; call_abi = ix86_cfun_abi ( ) ; if ( call_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( call_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; for ( i = 0 ; i < ( call_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX ) ; i ++ ) if ( regno == parm_regs [ i ] ) return true ; return false ; } </s>

Return true when register may be used to pass function parameters .


<s> void ix86_expand_push ( enum machine_mode mode , rtx x ) { rtx tmp ; tmp = expand_simple_binop ( Pmode , PLUS , stack_pointer_rtx , GEN_INT ( - GET_MODE_SIZE ( mode ) ) , stack_pointer_rtx , 1 , OPTAB_DIRECT ) ; if ( tmp != stack_pointer_rtx ) emit_move_insn ( stack_pointer_rtx , tmp ) ; tmp = gen_rtx_MEM ( mode , stack_pointer_rtx ) ; emit_move_insn ( tmp , x ) ; } </s>

Expand a push in MODE . This is some mode for which we do not support proper push instructions , at least from the registers that we expect the value to live in .


<s> static bool mips_expand_vpc_loongson_pshufh ( struct expand_vec_perm_d * d ) { unsigned i , mask ; rtx rmask ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( d -> vmode != V4HImode ) return false ; if ( d -> testing_p ) return true ; for ( i = mask = 0 ; i < 4 ; i ++ ) mask |= ( d -> perm [ i ] & 3 ) << ( i * 2 ) ; rmask = force_reg ( SImode , GEN_INT ( mask ) ) ; if ( d -> one_vector_p ) emit_insn ( gen_loongson_pshufh ( d -> target , d -> op0 , rmask ) ) ; else { rtx t0 , t1 , x , merge , rmerge [ 4 ] ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , d -> op1 , rmask ) ) ; emit_insn ( gen_loongson_pshufh ( t0 , d -> op0 , rmask ) ) ; for ( i = 0 ; i < 4 ; ++ i ) rmerge [ i ] = ( d -> perm [ i ] & 4 ? constm1_rtx : const0_rtx ) ; merge = gen_rtx_CONST_VECTOR ( V4HImode , gen_rtvec_v ( 4 , rmerge ) ) ; merge = force_reg ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , merge , t1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t1 , x ) ) ; x = gen_rtx_NOT ( V4HImode , merge ) ; x = gen_rtx_AND ( V4HImode , x , t0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t0 , x ) ) ; x = gen_rtx_IOR ( V4HImode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , d -> target , x ) ) ; } return true ; } </s>

Recognize patterns for the Loongson PSHUFH instruction .


<s> static unsigned int increase_distance ( rtx_insn * prev , rtx_insn * next , unsigned int distance ) { df_ref def , use ; if ( ! prev || ! next ) return distance + ( distance & 1 ) + 2 ; if ( ! DF_INSN_USES ( next ) || ! DF_INSN_DEFS ( prev ) ) return distance + 1 ; FOR_EACH_INSN_USE ( use , next ) FOR_EACH_INSN_DEF ( def , prev ) if ( ! DF_REF_IS_ARTIFICIAL ( def ) && DF_REF_REGNO ( use ) == DF_REF_REGNO ( def ) ) return distance + ( distance & 1 ) + 2 ; return distance + 1 ; } </s>

Increase given DISTANCE in half-cycles according to dependencies between PREV and NEXT instructions . Add 1 half-cycle if there is no dependency and go to next cycle if there is some dependecy .


"%qE attribute only applies to functions"

Handle a `` force_align_arg_pointer '' attribute .


<s> void X86DAGToDAGISel :: PostprocessISelDAG ( ) { if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_end ( ) ; bool MadeChange = false ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; if ( tryOptimizeRem8Extend ( N ) ) { MadeChange = true ; continue ; } if ( N -> getMachineOpcode ( ) != TargetOpcode :: SUBREG_TO_REG ) continue ; unsigned SubRegIdx = N -> getConstantOperandVal ( 2 ) ; if ( SubRegIdx != X86 :: sub_xmm && SubRegIdx != X86 :: sub_ymm ) continue ; SDValue Move = N -> getOperand ( 1 ) ; if ( ! Move . isMachineOpcode ( ) ) continue ; switch ( Move . getMachineOpcode ( ) ) { default : continue ; case X86 :: VMOVAPDrr : case X86 :: VMOVUPDrr : case X86 :: VMOVAPSrr : case X86 :: VMOVUPSrr : case X86 :: VMOVDQArr : case X86 :: VMOVDQUrr : case X86 :: VMOVAPDYrr : case X86 :: VMOVUPDYrr : case X86 :: VMOVAPSYrr : case X86 :: VMOVUPSYrr : case X86 :: VMOVDQAYrr : case X86 :: VMOVDQUYrr : case X86 :: VMOVAPDZ128rr : case X86 :: VMOVUPDZ128rr : case X86 :: VMOVAPSZ128rr : case X86 :: VMOVUPSZ128rr : case X86 :: VMOVDQA32Z128rr : case X86 :: VMOVDQU32Z128rr : case X86 :: VMOVDQA64Z128rr : case X86 :: VMOVDQU64Z128rr : case X86 :: VMOVAPDZ256rr : case X86 :: VMOVUPDZ256rr : case X86 :: VMOVAPSZ256rr : case X86 :: VMOVUPSZ256rr : case X86 :: VMOVDQA32Z256rr : case X86 :: VMOVDQU32Z256rr : case X86 :: VMOVDQA64Z256rr : case X86 :: VMOVDQU64Z256rr : break ; } SDValue In = Move . getOperand ( 0 ) ; if ( ! In . isMachineOpcode ( ) || In . getMachineOpcode ( ) <= TargetOpcode :: GENERIC_OP_END ) continue ; uint64_t TSFlags = getInstrInfo ( ) -> get ( In . getMachineOpcode ( ) ) . TSFlags ; if ( ( TSFlags & X86II :: EncodingMask ) != X86II :: VEX && ( TSFlags & X86II :: EncodingMask ) != X86II :: EVEX && ( TSFlags & X86II :: EncodingMask ) != X86II :: XOP ) continue ; CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , In , N -> getOperand ( 2 ) ) ; MadeChange = true ; } if ( MadeChange ) CurDAG -> RemoveDeadNodes ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> const char * X86_64Relocator :: getName ( Relocation :: Type pType ) const { return X86_64ApplyFunctions [ pType ] . name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static rtx get_thread_pointer ( int to_reg ) { rtx tp , reg , insn ; tp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TP ) ; if ( ! to_reg ) return tp ; reg = gen_reg_rtx ( Pmode ) ; insn = gen_rtx_SET ( VOIDmode , reg , tp ) ; insn = emit_insn ( insn ) ; return reg ; } </s>

Load the thread pointer . If TO_REG is true , force it into a register .


<s> const SparcMCExpr * SparcMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) SparcMCExpr ( Kind , Expr ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> SDValue AArch64TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && Subtarget -> useRSqrt ( ) ) ) if ( SDValue Estimate = getEstimate ( Subtarget , AArch64ISD :: FRSQRTE , Operand , DAG , ExtraSteps ) ) { SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; SDNodeFlags Flags ; Flags . setAllowReassociation ( true ) ; for ( int i = ExtraSteps ; i > 0 ; -- i ) { SDValue Step = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Estimate , Flags ) ; Step = DAG . getNode ( AArch64ISD :: FRSQRTS , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( 0.0 , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , ISD :: SETEQ ) ; Estimate = DAG . getNode ( ISD :: FMUL , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? ISD :: VSELECT : ISD :: SELECT , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps = 0 ; return Estimate ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s>
SDValue
LC3TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_LC3
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
LC3ISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"without AVX512F enabled changes the ABI"

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


<s> static rtx arm_libcall_value ( machine_mode mode , const_rtx libcall ) { if ( TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( arm_libcall_uses_aapcs_base ( libcall ) ) return gen_rtx_REG ( mode , ARG_REGISTER ( 1 ) ) ; } return arm_libcall_value_1 ( mode ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> int fma_node :: get_parity ( ) { return this -> m_head -> regno % 2 ; } </s>

Return the parity of the destination register of the instruction represented by this node .


<s> bool ia64_expand_vecint_minmax ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { rtx xops [ 6 ] ; if ( mode == V8QImode && ( code == UMIN || code == UMAX ) ) return false ; if ( mode == V4HImode && ( code == SMIN || code == SMAX ) ) return false ; if ( mode == V4HImode && code == UMAX ) { rtx x , tmp = gen_reg_rtx ( mode ) ; x = gen_rtx_US_MINUS ( mode , operands [ 1 ] , operands [ 2 ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ 0 ] , tmp , operands [ 2 ] ) ) ; return true ; } xops [ 0 ] = operands [ 0 ] ; xops [ 4 ] = xops [ 1 ] = operands [ 1 ] ; xops [ 5 ] = xops [ 2 ] = operands [ 2 ] ; switch ( code ) { case UMIN : code = LTU ; break ; case UMAX : code = GTU ; break ; case SMIN : code = LT ; break ; case SMAX : code = GT ; break ; default : gcc_unreachable ( ) ; } xops [ 3 ] = gen_rtx_fmt_ee ( code , VOIDmode , operands [ 1 ] , operands [ 2 ] ) ; ia64_expand_vecint_cmov ( xops ) ; return true ; } </s>

Emit an integral vector min or max operation . Return true if all done .


<s> pad_direction rs6000_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! AGGREGATE_PADDING_FIXED ) { if ( BYTES_BIG_ENDIAN ) { HOST_WIDE_INT size = 0 ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == 1 || size == 2 || size == 4 ) return PAD_DOWNWARD ; } return PAD_UPWARD ; } if ( AGGREGATES_PAD_UPWARD_ALWAYS ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return PAD_UPWARD ; } return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . For the AIX ABI structs are always stored left shifted in their argument slot .


<s>
const
AArch64GOT
&
AArch64GNULDBackend
::
getGOT
(
)
const
{
assert
(
m_pGOT
!=
&&
"GOT section not exist"
)
;
return
*
m_pGOT
;
}
</s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { EVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } break ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> const MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( Kind . isReadOnly ( ) ) { if ( C ) { Type * Ty = C -> getType ( ) ; SmallString < 32 > COMDATSymName ; if ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) { COMDATSymName = "__real@" ; COMDATSymName += scalarConstantToHexString ( C ) ; } else if ( const auto * VTy = dyn_cast < VectorType > ( Ty ) ) { uint64_t NumBits = VTy -> getBitWidth ( ) ; if ( NumBits == 128 || NumBits == 256 ) { COMDATSymName = NumBits == 128 ? "__xmm@" : "__ymm@" ; for ( int I = VTy -> getNumElements ( ) - 1 , E = - 1 ; I != E ; -- I ) COMDATSymName += scalarConstantToHexString ( C -> getAggregateElement ( I ) ) ; } } if ( ! COMDATSymName . empty ( ) ) { unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; return getContext ( ) . getCOFFSection ( ".rdata" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } } } return TargetLoweringObjectFile :: getSectionForConstant ( Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( llvm :: any_of ( CSI , [ ] ( const CalleeSavedInfo & C ) { return C . getReg ( ) == ARM :: FPCXTNS ; } ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( ARM :: VSTR_FPCXTNS_pre ) , ARM :: SP ) . addReg ( ARM :: SP ) . addImm ( - 4 ) . add ( predOps ( ARMCC :: AL ) ) ; } emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"insertBranch must not be told to insert a fallthrough"

"CSKY branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> static void ready_reorder ( rtx * ready , int nready ) { SCHED_REORDER ( ready , nready ) ; } </s>

Sort the ready list READY by ascending priority , using the SCHED_REORDER macro .


<s> bool X86InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; switch ( MI -> getOpcode ( ) ) { case X86 :: V_SET0 : return Expand2AddrUndef ( MI , get ( HasAVX ? X86 :: VXORPSrr : X86 :: XORPSrr ) ) ; case X86 :: TEST8ri_NOREX : MI -> setDesc ( get ( X86 :: TEST8ri ) ) ; return true ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool function_resolver :: require_integer_immediate ( unsigned int argno ) { if ( ! scalar_argument_p ( argno ) ) { report_non_ice ( location , fndecl , argno ) ; return false ; } return true ; } </s>

Require argument ARGNO to be suitable for an integer constant expression . Return true if it is , otherwise report an appropriate error . function_checker checks whether the argument is actually constant and has a suitable range . The reason for distinguishing immediate arguments here is because it provides more consistent error messages than require_scalar_type would .


<s> static rtx rs6000_emit_stack_reset ( rs6000_stack_t * info , rtx frame_reg_rtx , HOST_WIDE_INT frame_off , unsigned updt_regno ) { if ( frame_off == 0 && REGNO ( frame_reg_rtx ) == updt_regno ) return NULL_RTX ; rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 || ( TARGET_SPE_ABI && info -> spe_64bit_regs_used != 0 && info -> first_gp_reg_save != 32 ) ) return emit_insn ( gen_stack_restore_tie ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; if ( frame_off != 0 ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else return emit_move_insn ( updt_reg_rtx , frame_reg_rtx ) ; return NULL_RTX ; } </s>

Emit a sequence of insns , including a stack tie if needed , for resetting the stack pointer . If UPDT_REGNO is not 1 , then do n't reset the stack pointer , but move the base of the frame into reg UPDT_REGNO for use by out-of-line register restore routines .


<s>
void
crx_print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
enum
crx_addrtype
addrtype
;
struct
crx_address
address
;
int
offset
;
addrtype
=
crx_decompose_address
(
addr
,
&
address
)
;
if
(
address
.
disp
)
offset
=
INTVAL
(
address
.
disp
)
;
else
offset
=
0
;
switch
(
addrtype
)
{
case
CRX_REG_REL
:
fprintf
(
file
,
"%d(%s)"
,
offset
,
reg_names
[
REGNO
(
address
.
base
)
]
)
;
return
;
case
CRX_POST_INC
:
switch
(
GET_CODE
(
address
.
side_effect
)
)
{
case
PLUS
:
break
;
case
MINUS
:
offset
=
offset
;
break
;
case
POST_INC
:
offset
=
GET_MODE_SIZE
(
output_memory_reference_mode
)
;
break
;
case
POST_DEC
:
offset
=
GET_MODE_SIZE
(
output_memory_reference_mode
)
;
break
;
default
:
abort
(
)
;
}
fprintf
(
file
,
"%d(%s)+"
,
offset
,
reg_names
[
REGNO
(
address
.
base
)
]
)
;
return
;
case
CRX_SCALED_INDX
:
fprintf
(
file
,
"%d(%s, %s, %d)"
,
offset
,
reg_names
[
REGNO
(
address
.
base
)
]
,
reg_names
[
REGNO
(
address
.
index
)
]
,
address
.
scale
)
;
return
;
case
CRX_ABSOLUTE
:
output_addr_const
(
file
,
address
.
disp
)
;
return
;
default
:
abort
(
)
;
}
}
</s>

Implements the macro PRINT_OPERAND_ADDRESS defined in crx.h .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( const MachineFunction & MF , bool UseEstimate , unsigned * NewMaxCallFrameSize ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( NewMaxCallFrameSize ) * NewMaxCallFrameSize = maxCallFrameSize ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; Register FIReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildFrameIndex ( FIReg , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg ; } if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( p0 , Register ( AArch64 :: SP ) ) . getReg ( 0 ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> void LC3InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s> void LC3MCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s>
void
relaxInstruction
(
const
MCInst
&
,
llvm
::
MCInst
&
)
const
override
{
llvm_unreachable
(
"Cannot relax instructions"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


"Blocked load and store instructions: \n"

runOnMachineFunction - Emit the function body .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
,
false
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOCAL_ESCAPE
)
{
MachineOperand
&
FI
=
MI
.
getOperand
(
FIOperandNum
)
;
Offset
=
TFI
->
getNonLocalFrameIndexReference
(
MF
,
FrameIndex
)
;
FI
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
AArch64
::
TAGPstack
)
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64FunctionInfo
*
AFI
=
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
FrameReg
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
Offset
=
MFI
.
getObjectOffset
(
FrameIndex
)
+
AFI
->
getTaggedBasePointerOffset
(
)
;
}
else
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
false
,
true
)
;
}
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool isMem ( ) const override { return isMemImm ( ) || isMemRegImm ( ) || isMemRegReg ( ) ; } </s>


<s> rtx rx_maybe_pidify_operand ( rtx op , int copy_to_reg ) { if ( rx_pid_data_operand ( op ) == PID_UNENCODED ) { if ( GET_CODE ( op ) == MEM ) { rtx a = gen_pid_addr ( gen_rtx_REG ( SImode , rx_pid_base_regnum ( ) ) , XEXP ( op , 0 ) ) ; op = replace_equiv_address ( op , a ) ; } else { op = gen_pid_addr ( gen_rtx_REG ( SImode , rx_pid_base_regnum ( ) ) , op ) ; } if ( copy_to_reg ) op = copy_to_mode_reg ( GET_MODE ( op ) , op ) ; } return op ; } </s>

Maybe convert an operand into its PID format .


<s> const MCExpr * AArch64_MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . createTempSymbol ( ) ; Streamer . EmitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: createSub ( Res , PC , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

ARM ARM ARM::SP ARM::PC ARM::FPSCR ARM::R9


<s> bool SparcAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; addPass ( createAArch64ExpandHardenedPseudosPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const X86InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
static
void
recombine_lvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
&&
GET_CODE
(
XEXP
(
SET_SRC
(
body
)
,
0
)
)
==
MEM
)
;
rtx
mem
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
rtx
and_operation
=
find_alignment_op
(
insn
,
base_reg
)
;
if
(
and_operation
!=
0
)
{
df_ref
def
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_DEF
(
def
,
insn_info
)
{
struct
df_link
*
link
=
DF_REF_CHAIN
(
def
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
XEXP
(
mem
,
0
)
=
and_operation
;
SET_SRC
(
body
)
=
mem
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"lvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the load for an lvx pattern , put it in canonical form .


<s> static machine_mode aarch64_simd_container_mode ( scalar_mode mode , poly_int64 width ) { if ( TARGET_SVE && maybe_ne ( width , 128 ) && known_eq ( width , BITS_PER_SVE_VECTOR ) ) return aarch64_full_sve_mode ( mode ) . else_mode ( word_mode ) ; gcc_assert ( known_eq ( width , 64 ) || known_eq ( width , 128 ) ) ; if ( TARGET_SIMD ) { if ( known_eq ( width , 128 ) ) return aarch64_vq_mode ( mode ) . else_mode ( word_mode ) ; else switch ( mode ) { case E_SFmode : return V2SFmode ; case E_HFmode : return V4HFmode ; case E_BFmode : return V4BFmode ; case E_SImode : return V2SImode ; case E_HImode : return V4HImode ; case E_QImode : return V8QImode ; default : break ; } } return word_mode ; } </s>

Return appropriate SIMD container for MODE within a vector of WIDTH bits .


<s> static void mips16_load_branch_target ( rtx dest , rtx src ) { if ( TARGET_ABICALLS && ! TARGET_ABSOLUTE_ABICALLS ) { rtx page , low ; if ( mips_cfun_has_cprestore_slot_p ( ) ) mips_emit_move ( dest , mips_cprestore_slot ( dest , true ) ) ; else mips_emit_move ( dest , pic_offset_table_rtx ) ; page = mips_unspec_address ( src , SYMBOL_GOTOFF_PAGE ) ; low = mips_unspec_address ( src , SYMBOL_GOT_PAGE_OFST ) ; emit_insn ( gen_rtx_SET ( dest , PMODE_INSN ( gen_unspec_got , ( dest , page ) ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_LO_SUM ( Pmode , dest , low ) ) ) ; } else { src = mips_unspec_address ( src , SYMBOL_ABSOLUTE ) ; mips_emit_move ( dest , src ) ; } } </s>

Emit code to load LABEL_REF SRC into MIPS16 register DEST . This is called very late in mips_reorg , but the caller is required to run mips16_lay_out_constants on the result .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT ISD::AND ISD::OR ISD::ADD


<s> static bool isUnconditionalBranch ( unsigned int Opcode ) { switch ( Opcode ) { default : return false ; case Mips :: Bimm16 : case Mips :: BimmX16 : case Mips :: JalB16 : return true ; } } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s> Register CSKYInstrInfo :: getGlobalBaseReg ( MachineFunction & MF ) const { CSKYMachineFunctionInfo * CFI = MF . getInfo < CSKYMachineFunctionInfo > ( ) ; MachineConstantPool * MCP = MF . getConstantPool ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register GlobalBaseReg = CFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL ; CSKYConstantPoolValue * CPV = CSKYConstantPoolSymbol :: Create ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , "_GLOBAL_OFFSET_TABLE_" , 0 , CSKYCP :: ADDR ) ; unsigned CPI = MCP -> getConstantPoolIndex ( CPV , Align ( 4 ) ) ; MachineMemOperand * MO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , 4 , Align ( 4 ) ) ; BuildMI ( FirstMBB , MBBI , DL , get ( CSKY :: LRW32 ) , CSKY :: R28 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( MO ) ; GlobalBaseReg = MRI . createVirtualRegister ( & CSKY :: GPRRegClass ) ; BuildMI ( FirstMBB , MBBI , DL , get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( CSKY :: R28 ) ; CFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool sh_can_follow_jump ( const rtx_insn * branch1 , const rtx_insn * branch2 ) { if ( flag_reorder_blocks_and_partition && simplejump_p ( branch2 ) && CROSSING_JUMP_P ( branch2 ) ) return false ; if ( flag_expensive_optimizations && simplejump_p ( branch2 ) ) { rtx dest = XEXP ( SET_SRC ( single_set ( branch2 ) ) , 0 ) ; rtx_insn * insn ; int distance ; for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = PREV_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = NEXT_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } } return false ; } </s>

Return true if it 's possible to redirect BRANCH1 to the destination of an unconditional jump BRANCH2 . We only want to do this if the resulting branch will have a short displacement .


<s> bool AArch64TargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( 1 ) ) ; if ( ! Mask ) return false ; return Mask -> getUniqueInteger ( ) . isPowerOf2 ( ) ; } </s>

Return if the target supports combining a chain like :


<s> static rtx sh_legitimize_address ( rtx x , rtx oldx , machine_mode mode ) { if ( flag_pic ) x = legitimize_pic_address ( oldx , mode , NULL_RTX ) ; if ( TARGET_SHMEDIA ) return x ; if ( ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return x ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && BASE_REGISTER_RTX_P ( XEXP ( x , 0 ) ) ) { struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( XEXP ( x , 1 ) ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = expand_binop ( Pmode , add_optab , XEXP ( x , 0 ) , adj . offset_adjust , NULL_RTX , 0 , OPTAB_LIB_WIDEN ) ; return gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; } } return x ; } </s>

Try to modify an illegitimate address and make it legitimate . If we find one , return the new , valid address . Otherwise , return the original address .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return MCInstLowering . lowerOperand ( MO , MCOp ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool fixupNeedsRelaxation ( const MCFixup & , uint64_t , const MCRelaxableFragment * , const MCAsmLayout & ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

Mips
Intrinsic::ID
Intrinsic::cheri_cap_bounds_set
Intrinsic::getDeclaration
0
"Replacing "
"  with "


Return an array that contains the bitmask target flag values and their names .


<s> static int mep_insn_dependent_p ( rtx x , rtx y ) { rtx tmp ; gcc_assert ( INSN_P ( x ) ) ; gcc_assert ( INSN_P ( y ) ) ; tmp = PATTERN ( y ) ; note_stores ( PATTERN ( x ) , mep_insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX ) return 1 ; tmp = PATTERN ( x ) ; note_stores ( PATTERN ( y ) , mep_insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX ) return 1 ; return 0 ; } </s>

Return true if anything in insn X is ( anti , output , true ) dependent on anything in insn Y .


<s> TargetLowering :: AtomicExpansionKind PPCTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getPointerOperand ( ) -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) ; if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == 128 ) return AtomicExpansionKind :: MaskedIntrinsic ; return TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AI ) ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; const auto & DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> virtual bool mayNeedRelaxation ( const MCInst & Inst ) const LLVM_OVERRIDE { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool sparc_function_value_regno_p ( const unsigned int regno ) { return ( regno == 8 || ( TARGET_FPU && regno == 32 ) ) ; } </s>

Handle FUNCTION_VALUE_REGNO_P . On the SPARC , the first `` output '' reg is used for integer values , and the first floating point register is used for floating point values .


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { emitDataMappingSymbol ( ) ; MCObjectStreamer :: emitFill ( NumBytes , FillValue , Loc ) ; } </s>

Emit Size bytes worth of the value specified by FillValue .


<s> static void ix86_emit_support_tinfos ( emit_support_tinfos_callback callback ) { extern tree ix86_float16_type_node ; extern tree ix86_bf16_type_node ; if ( ! TARGET_SSE2 ) { gcc_checking_assert ( ! float16_type_node && ! bfloat16_type_node ) ; float16_type_node = ix86_float16_type_node ; bfloat16_type_node = ix86_bf16_type_node ; callback ( float16_type_node ) ; callback ( bfloat16_type_node ) ; float16_type_node = NULL_TREE ; bfloat16_type_node = NULL_TREE ; } } </s>

Create C++ tinfo symbols for only conditionally available fundamental types .


PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-nlp" "ppc-nlp-hidden"


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> void d30v_expand_prologue ( ) { rtx sp = stack_pointer_rtx ; d30v_stack_t * info = d30v_stack_info ( ) ; int i ; rtx mem_di = NULL_RTX ; rtx mem_si = NULL_RTX ; int num_memrefs = ( info -> memrefs_2words + info -> memrefs_1word + info -> memrefs_varargs ) ; if ( TARGET_DEBUG_STACK ) debug_stack_info ( info ) ; if ( info -> total_size ) emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( - info -> total_size ) ) ) ; if ( num_memrefs > 1 ) { rtx save_tmp = gen_rtx ( REG , Pmode , GPR_STACK_TMP ) ; rtx post_inc = gen_rtx ( POST_INC , Pmode , save_tmp ) ; mem_di = gen_rtx ( MEM , DImode , post_inc ) ; mem_si = gen_rtx ( MEM , SImode , post_inc ) ; emit_insn ( gen_addsi3 ( save_tmp , sp , GEN_INT ( info -> save_offset ) ) ) ; } else if ( num_memrefs == 1 ) { rtx addr = plus_constant ( sp , info -> save_offset ) ; mem_di = gen_rtx ( MEM , DImode , addr ) ; mem_si = gen_rtx ( MEM , SImode , addr ) ; } for ( i = ACCUM_FIRST ; i <= ACCUM_LAST ; i ++ ) if ( info -> save_p [ i ] ) { rtx acc_tmp = gen_rtx ( REG , DImode , GPR_ATMP_FIRST ) ; emit_insn ( gen_movdi ( acc_tmp , gen_rtx ( REG , DImode , i ) ) ) ; emit_insn ( gen_movdi ( mem_di , acc_tmp ) ) ; } for ( i = GPR_FIRST ; i <= GPR_LAST ; i += 2 ) if ( info -> save_p [ i ] == 2 ) emit_insn ( gen_movdi ( mem_di , gen_rtx ( REG , DImode , i ) ) ) ; for ( i = GPR_FIRST ; i <= GPR_LAST ; i ++ ) if ( info -> save_p [ i ] == 1 ) emit_insn ( gen_movsi ( mem_si , gen_rtx ( REG , SImode , i ) ) ) ; if ( info -> varargs_p ) { if ( ( info -> memrefs_1word & 1 ) != 0 ) { rtx save_tmp = XEXP ( XEXP ( mem_si , 0 ) , 0 ) ; emit_insn ( gen_addsi3 ( save_tmp , save_tmp , GEN_INT ( UNITS_PER_WORD ) ) ) ; } for ( i = GPR_ARG_FIRST ; i <= GPR_ARG_LAST ; i += 2 ) emit_insn ( gen_movdi ( mem_di , gen_rtx ( REG , DImode , i ) ) ) ; } if ( frame_pointer_needed ) emit_move_insn ( frame_pointer_rtx , sp ) ; emit_insn ( gen_blockage ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in output_function_prologue ( ) , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; Target = Addr + Imm + 4 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isAtLeastRelease ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> machine_mode rs6000_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree , int for_return ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < ( TARGET_32BIT ? 4 : 8 ) ) mode = TARGET_32BIT ? SImode : DImode ; return mode ; } </s>

On rs6000 , function arguments are promoted , as are function return values .


<s> bool X86TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . hasXMMInt ( ) ) { PM . add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool hasStandaloneRem ( EVT VT ) const override { return HasStandaloneRem ; } </s>

Return true if the target can handle a standalone remainder operation .


<s> bool AArch64TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , ISD :: LoadExtType ExtTy , EVT NewVT ) const { if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( Load , ExtTy , NewVT ) ) return false ; if ( ExtTy != ISD :: NON_EXTLOAD ) return true ; MemSDNode * Mem = dyn_cast < MemSDNode > ( Load ) ; assert ( Mem ) ; const SDValue & Base = Mem -> getBasePtr ( ) ; if ( Base . getOpcode ( ) == ISD :: ADD && Base . getOperand ( 1 ) . getOpcode ( ) == ISD :: SHL && Base . getOperand ( 1 ) . hasOneUse ( ) && Base . getOperand ( 1 ) . getOperand ( 1 ) . getOpcode ( ) == ISD :: Constant ) { if ( Mem -> getMemoryVT ( ) . isScalableVector ( ) ) return false ; uint64_t ShiftAmount = Base . getOperand ( 1 ) . getConstantOperandVal ( 1 ) ; uint64_t LoadBytes = Mem -> getMemoryVT ( ) . getSizeInBits ( ) / 8 ; if ( ShiftAmount == Log2_32 ( LoadBytes ) ) return false ; } return true ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static const char * ix86_mangle_fundamental_type ( tree type ) { switch ( TYPE_MODE ( type ) ) { case TFmode : return "g" ; case XFmode : return "e" ; default : return NULL ; } } </s>

Return the mangling of TYPE if it is an extended fundamental type .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s> void AArch64Subtarget :: mirFileLoaded ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) ) MFI . computeMaxCallFrameSize ( MF ) ; } </s>

This is called after a .mir file was loaded .


<s> bool ARMTargetLowering :: isExtractSubvectorCheap ( EVT ResVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> int pa_attr_length_call ( rtx_insn * insn , int sibcall ) { int local_call ; rtx call , call_dest ; tree call_decl ; int length = 0 ; rtx pat = PATTERN ( insn ) ; unsigned long distance = - 1 ; gcc_assert ( CALL_P ( insn ) ) ; if ( INSN_ADDRESSES_SET_P ( ) ) { unsigned long total ; total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; call = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; gcc_assert ( GET_CODE ( call ) == CALL ) ; call_dest = XEXP ( XEXP ( call , 0 ) , 0 ) ; call_decl = SYMBOL_REF_DECL ( call_dest ) ; local_call = call_decl && targetm . binds_local_p ( call_decl ) ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! sibcall && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) length += 8 ; else if ( TARGET_64BIT && ! local_call ) length += sibcall ? 28 : 24 ; else if ( ( TARGET_LONG_ABS_CALL || local_call ) && ! flag_pic ) length += 12 ; else if ( TARGET_LONG_PIC_SDIFF_CALL || ( TARGET_GAS && ! TARGET_SOM && local_call ) ) { length += 20 ; if ( ! TARGET_PA_20 && ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += 8 ; } else { length += 32 ; if ( TARGET_SOM ) length += length_fp_args ( insn ) ; if ( flag_pic ) length += 4 ; if ( ! TARGET_PA_20 ) { if ( ! sibcall ) length += 8 ; if ( ! TARGET_NO_SPACE_REGS && ( ! local_call || flag_pic ) ) length += 8 ; } } return length ; } </s>

Return the attribute length of the call instruction INSN . The SIBCALL flag indicates whether INSN is a regular call or a sibling call . The length returned must be longer than the code actually generated by pa_output_call . Since branch shortening is done before delay branch sequencing , there is no way to determine whether or not the delay slot will be filled during branch shortening . Even when the delay slot is filled , we may have to add a nop if the delay slot contains a branch that ca n't reach its target . Thus , we always have to include the delay slot in the length estimate . This used to be done in pa_adjust_insn_length but we do it here now as some sequences always fill the delay slot and we can save four bytes in the estimate for these sequences .


"definition of static data member %q+D of "

Return true if DECL should be a dllimport 'd object .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
AArch64MCExpr
::
VariantKind
RefKind
=
static_cast
<
AArch64MCExpr
::
VariantKind
>
(
Target
.
getRefKind
(
)
)
;
if
(
RefKind
&
AArch64MCExpr
::
VK_SABS
)
{
if
(
SignedValue
<
0
)
Data
[
Offset
+
3
]
&=
~
(
1
<<
6
)
;
else
Data
[
Offset
+
3
]
|=
(
1
<<
6
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
SystemZOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
KindToken
:
OS
<<
"Token:"
<<
getToken
(
)
;
break
;
case
KindReg
:
OS
<<
"Reg:"
<<
SystemZInstPrinter
::
getRegisterName
(
getReg
(
)
)
;
break
;
case
KindImm
:
OS
<<
"Imm:"
;
printMCExpr
(
getImm
(
)
,
OS
)
;
break
;
case
KindImmTLS
:
OS
<<
"ImmTLS:"
;
printMCExpr
(
getImmTLS
(
)
.
Imm
,
OS
)
;
if
(
getImmTLS
(
)
.
Sym
)
{
OS
<<
", "
;
printMCExpr
(
getImmTLS
(
)
.
Sym
,
OS
)
;
}
break
;
case
KindMem
:
{
const
MemOp
&
Op
=
getMem
(
)
;
OS
<<
"Mem:"
<<
*
cast
<
MCConstantExpr
>
(
Op
.
Disp
)
;
if
(
Op
.
Base
)
{
OS
<<
"("
;
if
(
Op
.
MemKind
==
BDLMem
)
OS
<<
*
cast
<
MCConstantExpr
>
(
Op
.
Length
.
Imm
)
<<
","
;
else
if
(
Op
.
MemKind
==
BDRMem
)
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Length
.
Reg
)
<<
","
;
if
(
Op
.
Index
)
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Index
)
<<
","
;
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Base
)
;
OS
<<
")"
;
}
break
;
}
case
KindInvalid
:
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

SystemZ
SystemZ
"Token:"
"Reg:"
SystemZ
"Imm:"
"ImmTLS:"
", "
"Mem:"
"("
","
SystemZ
","
SystemZ
","
SystemZ
")"


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new X86MCAsmInfoDarwin ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: MinGW64 : case Triple :: Cygwin : case Triple :: Win32 : return new X86MCAsmInfoCOFF ( TheTriple ) ; default : return new X86ELFMCAsmInfo ( TheTriple ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
XOR32rr
)
)
;
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
KSET0B
:
case
X86
::
KSET0W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORWrr
)
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORWrr
)
)
;
case
TargetOpcode
::
LOAD_STACK_GUARD
:
expandLoadStackGuard
(
MIB
,
*
this
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static ARMOperand CreateMem ( unsigned BaseRegNum , bool OffsetIsReg , const MCExpr * Offset , unsigned OffsetRegNum , bool OffsetRegShifted , enum ShiftType ShiftType , const MCExpr * ShiftAmount , bool Preindexed , bool Postindexed , bool Negative , bool Writeback ) { ARMOperand Res ; Res . Kind = Memory ; Res . Mem . BaseRegNum = BaseRegNum ; Res . Mem . OffsetIsReg = OffsetIsReg ; Res . Mem . Offset = Offset ; Res . Mem . OffsetRegNum = OffsetRegNum ; Res . Mem . OffsetRegShifted = OffsetRegShifted ; Res . Mem . ShiftType = ShiftType ; Res . Mem . ShiftAmount = ShiftAmount ; Res . Mem . Preindexed = Preindexed ; Res . Mem . Postindexed = Postindexed ; Res . Mem . Negative = Negative ; Res . Mem . Writeback = Writeback ; return Res ; } </s>


<s> static bool is_lfs_stfs_insn ( rtx_insn * insn ) { rtx pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL ) return false ; if ( XVECLEN ( pattern , 0 ) != 2 ) return false ; rtx set = XVECEXP ( pattern , 0 , 0 ) ; if ( GET_CODE ( set ) != SET ) return false ; rtx clobber = XVECEXP ( pattern , 0 , 1 ) ; if ( GET_CODE ( clobber ) != CLOBBER ) return false ; rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; rtx scratch = SET_DEST ( clobber ) ; if ( GET_CODE ( src ) != UNSPEC ) return false ; if ( XINT ( src , 1 ) == UNSPEC_SI_FROM_SF && GET_CODE ( dest ) == MEM && GET_MODE ( dest ) == SImode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == V4SFmode ) return true ; if ( XINT ( src , 1 ) == UNSPEC_SF_FROM_SI && GET_CODE ( dest ) == REG && GET_MODE ( dest ) == SFmode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == DImode ) return true ; return false ; } </s>

Helper function to see if we 're potentially looking at lfs/stfs . - PARALLEL containing a SET and a CLOBBER - stfs : - SET is from UNSPEC_SI_FROM_SF to MEM : SI - CLOBBER is a V4SF - lfs : - SET is from UNSPEC_SF_FROM_SI to REG : SF - CLOBBER is a DI


"missing %<target%> attribute for multi-versioned %D"

This function returns true if FN1 and FN2 are versions of the same function , that is , the target strings of the function decls are different . This assumes that FN1 and FN2 have the same signature .


<s> bool ARMBaseInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int64_t CmpMask , CmpValue ; bool IsThumb1 ; if ( Next != MI . getParent ( ) -> end ( ) && analyzeCompare ( * Next , SrcReg , SrcReg2 , CmpMask , CmpValue ) && isRedundantFlagInstr ( & * Next , SrcReg , SrcReg2 , CmpValue , & MI , IsThumb1 ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( Subtarget . hasStandardEncoding ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( Subtarget . inMips16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> bool ARMCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallingConv :: ID CallConv , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const auto & TLI = * getTLI < ARMTargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( MF . getSubtarget < ARMSubtarget > ( ) . genLongCalls ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( ARM :: ADJCALLSTACKDOWN ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( ARM :: BLX ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , 8 > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; splitToValueTypes ( Arg , ArgInfos , DL , MRI ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( OrigRet , ArgInfos , DL , MRI ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ; } CallSeqStart . addImm ( ArgHandler . StackSize ) . add ( predOps ( ARMCC :: AL ) ) ; MIRBuilder . buildInstr ( ARM :: ADJCALLSTACKUP ) . addImm ( ArgHandler . StackSize ) . addImm ( 0 ) . add ( predOps ( ARMCC :: AL ) ) ; return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .

ARM ARM ARM ARM ARM::ADJCALLSTACKDOWN ARM::BLX 8 ARMCC::AL ARM::ADJCALLSTACKUP 0 ARMCC::AL


<s>
void
SystemZPostRASchedStrategy
::
enterMBB
(
MachineBasicBlock
*
NextMBB
)
{
assert
(
(
SchedStates
.
find
(
NextMBB
)
==
SchedStates
.
end
(
)
)
&&
"Entering MBB twice?"
)
;
DEBUG
(
dbgs
(
)
<<
"+++ Entering MBB#"
<<
NextMBB
->
getNumber
(
)
)
;
MBB
=
NextMBB
;
HazardRec
=
SchedStates
[
MBB
]
=
new
SystemZHazardRecognizer
(
TII
,
&
SchedModel
)
;
DEBUG
(
const
MachineLoop
*
Loop
=
MLI
->
getLoopFor
(
MBB
)
;
if
(
Loop
&&
Loop
->
getHeader
(
)
==
MBB
)
dbgs
(
)
<<
" (Loop header)"
;
dbgs
(
)
<<
":\n"
;
)
;
MachineBasicBlock
*
SinglePredMBB
=
getSingleSchedPred
(
MBB
,
MLI
->
getLoopFor
(
MBB
)
)
;
if
(
SinglePredMBB
==
nullptr
||
SchedStates
.
find
(
SinglePredMBB
)
==
SchedStates
.
end
(
)
)
return
;
DEBUG
(
dbgs
(
)
<<
"+++ Continued scheduling from MBB#"
<<
SinglePredMBB
->
getNumber
(
)
<<
"\n"
;
)
;
HazardRec
->
copyState
(
SchedStates
[
SinglePredMBB
]
)
;
for
(
MachineBasicBlock
::
iterator
I
=
SinglePredMBB
->
getFirstTerminator
(
)
;
I
!=
SinglePredMBB
->
end
(
)
;
I
++
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Emitting incoming branch: "
;
I
->
dump
(
)
;
)
;
bool
TakenBranch
=
(
I
->
isBranch
(
)
&&
(
TII
->
getBranchInfo
(
*
I
)
.
Target
->
isReg
(
)
||
TII
->
getBranchInfo
(
*
I
)
.
Target
->
getMBB
(
)
==
MBB
)
)
;
HazardRec
->
emitInstruction
(
&
*
I
,
TakenBranch
)
;
if
(
TakenBranch
)
break
;
}
}
</s>

Tell the strategy that MBB is about to be processed .

SystemZ
SystemZ
"Entering MBB twice?"
"+++ Entering MBB#"
SystemZ
" (Loop header)"
":\n"
"+++ Continued scheduling from MBB#"
"\n"
"+++ Emitting incoming branch: "


"AArch64 FastISel doesn't support types larger than i64"

This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the given getelementptr index value .


<s> bool DLXInstrInfo :: analyzeSelect ( const MachineInstr & MI , SmallVectorImpl < MachineOperand > & Cond , unsigned & TrueOp , unsigned & FalseOp , bool & Optimizable ) const { return false ; } </s>

Analyze the given select instruction , returning true if it can not be understood .


<s> static machine_mode ia64_c_mode_for_suffix ( char suffix ) { if ( suffix == 'q' ) return TFmode ; if ( suffix == 'w' ) return XFmode ; return VOIDmode ; } </s>


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool MandarinFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool isLittleEndian ( ) const { return isLittle ; } </s>

Tests whether the target triple is little endian .


<s> bool X86InstrInfo :: isHighLatencyDef ( int opc ) const { switch ( opc ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDr : case X86 :: SQRTPSm : case X86 :: SQRTPSr : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : case X86 :: VDIVSDrm : case X86 :: VDIVSDrm_Int : case X86 :: VDIVSDrr : case X86 :: VDIVSDrr_Int : case X86 :: VDIVSSrm : case X86 :: VDIVSSrm_Int : case X86 :: VDIVSSrr : case X86 :: VDIVSSrr_Int : case X86 :: VSQRTPDm : case X86 :: VSQRTPDr : case X86 :: VSQRTPSm : case X86 :: VSQRTPSr : case X86 :: VSQRTSDm : case X86 :: VSQRTSDm_Int : case X86 :: VSQRTSDr : case X86 :: VSQRTSSm : case X86 :: VSQRTSSm_Int : case X86 :: VSQRTSSr : case X86 :: VSQRTPDZrm : case X86 :: VSQRTPDZrr : case X86 :: VSQRTPSZrm : case X86 :: VSQRTPSZrr : case X86 :: VSQRTSDZm : case X86 :: VSQRTSDZm_Int : case X86 :: VSQRTSDZr : case X86 :: VSQRTSSZm_Int : case X86 :: VSQRTSSZr : case X86 :: VSQRTSSZm : case X86 :: VDIVSDZrm : case X86 :: VDIVSDZrr : case X86 :: VDIVSSZrm : case X86 :: VDIVSSZrr : case X86 :: VGATHERQPSZrm : case X86 :: VGATHERQPDZrm : case X86 :: VGATHERDPDZrm : case X86 :: VGATHERDPSZrm : case X86 :: VPGATHERQDZrm : case X86 :: VPGATHERQQZrm : case X86 :: VPGATHERDDZrm : case X86 :: VPGATHERDQZrm : case X86 :: VSCATTERQPDZmr : case X86 :: VSCATTERQPSZmr : case X86 :: VSCATTERDPDZmr : case X86 :: VSCATTERDPSZmr : case X86 :: VPSCATTERQDZmr : case X86 :: VPSCATTERQQZmr : case X86 :: VPSCATTERDDZmr : case X86 :: VPSCATTERDQZmr : return true ; } } </s>

Return true if this opcode has high latency to its result .


<s> FastISel * X86 :: createFastISel ( FunctionLoweringInfo & funcInfo ) { return new X86FastISel ( funcInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> uint64_t getStackSize ( ) { return StackSize ; } </s>

Return the number of bytes that must be allocated to hold all of the fixed size frame objects .


<s> void ix86_emit_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src ) { rtx op , clob ; op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , dst , src ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } </s>

Emit x86 binary operand CODE in mode MODE , where the first operand matches destination . RTX includes clobber of FLAGS_REG .


<s> void MipsDAGToDAGISel :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved < StackProtector > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
Register
VETargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"sp"
,
VE
::
SX11
)
.
Case
(
"fp"
,
VE
::
SX9
)
.
Case
(
"sl"
,
VE
::
SX8
)
.
Case
(
"lr"
,
VE
::
SX10
)
.
Case
(
"tp"
,
VE
::
SX14
)
.
Case
(
"outer"
,
VE
::
SX12
)
.
Case
(
"info"
,
VE
::
SX17
)
.
Case
(
"got"
,
VE
::
SX15
)
.
Case
(
"plt"
,
VE
::
SX16
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> static bool is_fusable_store ( rtx_insn * insn , rtx * str_mem ) { if ( is_store_insn ( insn , str_mem ) && get_attr_prefixed ( insn ) == PREFIXED_NO && get_attr_update ( insn ) == UPDATE_NO && get_attr_indexed ( insn ) == INDEXED_NO ) { if ( ! MEM_SIZE_KNOWN_P ( * str_mem ) ) return false ; machine_mode mode = GET_MODE ( * str_mem ) ; HOST_WIDE_INT size = MEM_SIZE ( * str_mem ) ; if ( INTEGRAL_MODE_P ( mode ) ) return ( size == 4 || size == 8 ) ; else if ( FLOAT_MODE_P ( mode ) ) return ( size == 8 ) ; } return false ; } </s>

Determine if INSN is a store to memory that can be fused with a similar adjacent store .


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && std :: find ( Order . begin ( ) , Order . end ( ) , PairedPhys ) != Order . end ( ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = 0 , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> static void rs6000_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.long\t" , file ) ; break ; case 8 : fputs ( DOUBLE_INT_ASM_OP , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; if ( TARGET_ELF ) fputs ( "@dtprel+0x8000" , file ) ; } </s>

This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s>
const
TargetRegisterClass
*
ARMBaseRegisterInfo
::
getMatchingSuperRegClass
(
const
TargetRegisterClass
*
A
,
const
TargetRegisterClass
*
B
,
unsigned
SubIdx
)
const
{
switch
(
SubIdx
)
{
default
:
return
0
;
case
1
:
case
2
:
case
3
:
case
4
:
if
(
A
->
getSize
(
)
==
8
)
{
if
(
B
==
&
ARM
::
SPR_8RegClass
)
return
&
ARM
::
DPR_8RegClass
;
assert
(
B
==
&
ARM
::
SPRRegClass
&&
"Expecting SPR register class!"
)
;
if
(
A
==
&
ARM
::
DPR_8RegClass
)
return
A
;
return
&
ARM
::
DPR_VFP2RegClass
;
}
assert
(
A
->
getSize
(
)
==
16
&&
"Expecting a Q register class!"
)
;
if
(
B
==
&
ARM
::
SPR_8RegClass
)
return
&
ARM
::
QPR_8RegClass
;
return
&
ARM
::
QPR_VFP2RegClass
;
case
5
:
case
6
:
if
(
B
==
&
ARM
::
DPR_VFP2RegClass
)
return
&
ARM
::
QPR_VFP2RegClass
;
if
(
B
==
&
ARM
::
DPR_8RegClass
)
return
&
ARM
::
QPR_8RegClass
;
return
A
;
}
return
0
;
}
</s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; uint64_t MaxReach = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize * 2 ) ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> BitVector ARMRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void mips_function_rodata_section ( tree decl ) { if ( ! TARGET_ABICALLS || TARGET_GPWORD ) default_function_rodata_section ( decl ) ; else if ( decl && DECL_SECTION_NAME ( decl ) ) { const char * name = TREE_STRING_POINTER ( DECL_SECTION_NAME ( decl ) ) ; if ( DECL_ONE_ONLY ( decl ) && strncmp ( name , ".gnu.linkonce.t." , 16 ) == 0 ) { char * rname = ASTRDUP ( name ) ; rname [ 14 ] = 'd' ; named_section_real ( rname , SECTION_LINKONCE | SECTION_WRITE , decl ) ; } else if ( flag_function_sections && flag_data_sections && strncmp ( name , ".text." , 6 ) == 0 ) { char * rname = ASTRDUP ( name ) ; memcpy ( rname + 1 , "data" , 4 ) ; named_section_flags ( rname , SECTION_WRITE ) ; } else data_section ( ) ; } else data_section ( ) ; } </s>

Implement TARGET_ASM_FUNCTION_RODATA_SECTION . The complication here is that , with the combination TARGET_ABICALLS & & ! TARGET_GPWORD , jump tables will use absolute addresses , and should therefore not be included in the read-only part of a DSO . Handle such cases by selecting a normal data section instead of a read-only one . The logic apes that in default_function_rodata_section .


<s> bool MipsInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { return true ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; int Offset = getTargetMachine ( ) . Options . StackProtectorGuardOffset ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; const auto & GuardReg = getTargetMachine ( ) . Options . StackProtectorGuardReg ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> static void nds32_emit_stack_v3pop ( rtx Rb , rtx Re , rtx En4 ATTRIBUTE_UNUSED , rtx imm8u ) { int regno ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx pop_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; rtx dwarf = NULL_RTX ; num_use_regs = REGNO ( Re ) - REGNO ( Rb ) + 1 + 3 ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = 0 ; for ( regno = REGNO ( Rb ) ; regno <= ( int ) REGNO ( Re ) ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset + INTVAL ( imm8u ) ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , copy_rtx ( adjust_sp_rtx ) , dwarf ) ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; REG_NOTES ( parallel_insn ) = dwarf ; } </s>

Function to create a parallel rtx pattern which presents stack v3pop behavior . The overall concept are : `` pop registers from memory '' , `` adjust stack pointer '' .


<s> void FISCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == FISC :: ADJCALLSTACKUP || I -> getOpcode ( ) == FISC :: ADJCALLSTACKDOWN ) MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

FISC FISC FISC::ADJCALLSTACKUP FISC::ADJCALLSTACKDOWN


<s> bool aarch64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( TARGET_SIMD && aarch64_vector_mode_p ( mode1 ) && aarch64_vector_mode_p ( mode2 ) ) return true ; return false ; } </s>

Implement MODES_TIEABLE_P . In principle we should always return true . However due to issues with register allocation it is preferable to avoid tieing integer scalar and FP scalar modes . Executing integer operations in general registers is better than treating them as scalar vector operations . This reduces latency and avoids redundant int < - > FP moves . So tie modes if they are either the same class , or vector modes with other vector modes , vector structs or any scalar mode .


<s>
void
X86AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
X86MCInstLower
MCInstLowering
(
Mang
,
*
MF
,
*
this
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
TargetOpcode
::
DBG_VALUE
:
if
(
isVerbose
(
)
&&
OutStreamer
.
hasRawTextSupport
(
)
)
{
std
::
string
TmpStr
;
raw_string_ostream
OS
(
TmpStr
)
;
PrintDebugValueComment
(
MI
,
OS
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
OS
.
str
(
)
)
)
;
}
return
;
case
X86
::
Int_MemBarrier
:
if
(
OutStreamer
.
hasRawTextSupport
(
)
)
OutStreamer
.
EmitRawText
(
StringRef
(
"\t#MEMBARRIER"
)
)
;
return
;
case
X86
::
EH_RETURN
:
case
X86
::
EH_RETURN64
:
{
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
OutStreamer
.
AddComment
(
StringRef
(
"eh_return, addr: %"
)
+
X86ATTInstPrinter
::
getRegisterName
(
Reg
)
)
;
break
;
}
case
X86
::
TAILJMPr
:
case
X86
::
TAILJMPd
:
case
X86
::
TAILJMPd64
:
OutStreamer
.
AddComment
(
"TAILCALL"
)
;
break
;
case
X86
::
TLS_addr32
:
case
X86
::
TLS_addr64
:
case
X86
::
TLS_base_addr32
:
case
X86
::
TLS_base_addr64
:
return
LowerTlsAddr
(
OutStreamer
,
MCInstLowering
,
*
MI
)
;
case
X86
::
MOVPC32r
:
{
MCSymbol
*
PICBase
=
MF
->
getPICBaseSymbol
(
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
CALLpcrel32
)
.
addExpr
(
MCSymbolRefExpr
::
Create
(
PICBase
,
OutContext
)
)
)
;
OutStreamer
.
EmitLabel
(
PICBase
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
POP32r
)
.
addReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
return
;
}
case
X86
::
ADD32ri
:
{
if
(
MI
->
getOperand
(
2
)
.
getTargetFlags
(
)
!=
X86II
::
MO_GOT_ABSOLUTE_ADDRESS
)
break
;
MCSymbol
*
DotSym
=
OutContext
.
CreateTempSymbol
(
)
;
OutStreamer
.
EmitLabel
(
DotSym
)
;
MCSymbol
*
OpSym
=
MCInstLowering
.
GetSymbolFromOperand
(
MI
->
getOperand
(
2
)
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
Create
(
DotSym
,
OutContext
)
;
const
MCExpr
*
PICBase
=
MCSymbolRefExpr
::
Create
(
MF
->
getPICBaseSymbol
(
)
,
OutContext
)
;
DotExpr
=
MCBinaryExpr
::
CreateSub
(
DotExpr
,
PICBase
,
OutContext
)
;
DotExpr
=
MCBinaryExpr
::
CreateAdd
(
MCSymbolRefExpr
::
Create
(
OpSym
,
OutContext
)
,
DotExpr
,
OutContext
)
;
OutStreamer
.
EmitInstruction
(
MCInstBuilder
(
X86
::
ADD32ri
)
.
addReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addExpr
(
DotExpr
)
)
;
return
;
}
}
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned X86FastISel :: fastMaterializeFloatZero ( const ConstantFP * CF ) { MVT VT ; if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return 0 ; bool HasAVX512 = Subtarget -> hasAVX512 ( ) ; unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : return 0 ; case MVT :: f32 : if ( X86ScalarSSEf32 ) Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SS : X86 :: FsFLD0SS ; else Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( X86ScalarSSEf64 ) Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SD : X86 :: FsFLD0SD ; else Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : return 0 ; } unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } </s>

Emit the floating-point constant +0.0 in a register using target- specific logic .


<s> static bool moxie_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 2 * UNITS_PER_WORD ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> static enum aarch64_parse_opt_result aarch64_parse_cpu ( const char * to_parse , const struct processor * * res , unsigned long * isa_flags , std :: string * invalid_extension ) { const char * ext ; const struct processor * cpu ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , to_parse , len ) == 0 ) { unsigned long isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the result tuning in RES and the architecture flags in ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> rtx gen_easy_altivec_constant ( rtx op ) { enum machine_mode mode = GET_MODE ( op ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtx last = CONST_VECTOR_ELT ( op , nunits - 1 ) ; unsigned step = nunits / 4 ; unsigned copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , last ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V8HImode , gen_lowpart ( HImode , last ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V16QImode , gen_lowpart ( QImode , last ) ) ; gcc_unreachable ( ) ; } </s>

Generate a VEC_DUPLICATE representing a vspltis [ bhw ] instruction whose result is OP . Abort if it is not possible .


"instructions, but the target does not support ARM mode execution."

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool SystemZInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Pred , unsigned DstReg , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! STI . hasLoadStoreOnCond ( ) ) return false ; if ( Pred . size ( ) != 2 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && SystemZ :: GRX32BitRegClass . hasSubClassEq ( RC ) ) || SystemZ :: GR32BitRegClass . hasSubClassEq ( RC ) || SystemZ :: GR64BitRegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


Return 1 if br.ret can do all the work required to return from a function .


<s> bool ARMBaseInstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Subtarget . isCortexA8 ( ) && ( DDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainVFP ) ) return true ; unsigned Latency = SchedModel . computeOperandLatency ( DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency <= 3 ) return false ; return DDomain == ARMII :: DomainVFP || DDomain == ARMII :: DomainNEON || UDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainNEON ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .

ARM ARM ARMII::DomainMask ARMII::DomainMask ARMII::DomainVFP ARMII::DomainVFP 3 ARMII::DomainVFP ARMII::DomainNEON ARMII::DomainVFP ARMII::DomainNEON


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Native Client Rewrite Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> bool loongarch_signed_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = 0 ) { x += 1 << ( bits + shift - 1 ) ; return loongarch_unsigned_immediate_p ( x , bits , shift ) ; } </s>

Return true if X fits within a signed field of BITS bits that is shifted left SHIFT bits before being used .


<s> TargetPassConfig * SICTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SICPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void SystemZHazardRecognizer :: copyState ( SystemZHazardRecognizer * Incoming ) { CurrGroupSize = Incoming -> CurrGroupSize ; DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming -> LastFPdOpCycleIdx ; GrpCount = Incoming -> GrpCount ; } </s>

Copy counters from end of single predecessor .


<s> DecodeStatus LoongArchDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { uint32_t Insn ; DecodeStatus Result ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } Insn = support :: endian :: read32le ( Bytes . data ( ) ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = 4 ; return Result ; } </s>

Returns the disassembly of a single instruction .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
getARMRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
MCID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = Endian == support :: little ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"LVI load hardening is only supported on 64-bit"

runOnMachineFunction - Emit the function body .


"Relocation required in an instruction that we cannot encode!"