<s> static bool rs6000_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p ) { static int recurse = 0 ; if ( TARGET_RELOCATABLE && in_section != toc_section && ! recurse && ! CONST_SCALAR_INT_P ( x ) && CONSTANT_P ( x ) ) { char buf [ 256 ] ; recurse = 1 ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LCP" , fixuplabelno ) ; fixuplabelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\t.long\t(" ) ; output_addr_const ( asm_out_file , x ) ; fprintf ( asm_out_file , ")@fixup\n" ) ; fprintf ( asm_out_file , "\t.section\t\".fixup\",\"aw\"\n" ) ; ASM_OUTPUT_ALIGN ( asm_out_file , 2 ) ; fprintf ( asm_out_file , "\t.long\t" ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , "\n\t.previous\n" ) ; recurse = 0 ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , 0 ) [ 0 ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , 0 ) ; while ( * name == '.' ) name ++ ; fprintf ( asm_out_file , "\t.long\t%s\n" , name ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The powerpc version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined . It also needs to handle DI-mode objects on 64-bit targets .


"\n========== quad_load_store, return %s\n"

Return true if this is a load or store quad operation . This function does not handle the atomic quad memory instructions .


<s> SDValue Cpu0TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned opc = N -> getOpcode ( ) ; switch ( opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> unsigned AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { unsigned Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1


<s> bool nds32_e8_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return e8_consumed_by_addr_in_p ( consumer , def_reg ) ; } </s>


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) , XEXP ( rem , 0 ) , Pmode ) ; * quot_p = quot ; * rem_p = rem ; } </s>


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return AArch64 :: X1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 Promote Constant"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Cannot align scalable vectors more than 16 bytes"

"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"Arch64 does not support GOT PC rel with extra offset"

Get the target specific PC relative GOT entry relocation .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s> void ix86_expand_xorsign ( rtx operands [ ] ) { rtx ( * xorsign_insn ) ( rtx , rtx , rtx , rtx ) ; machine_mode mode , vmode ; rtx dest , op0 , op1 , mask ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; if ( mode == SFmode ) { xorsign_insn = gen_xorsignsf3_1 ; vmode = V4SFmode ; } else if ( mode == DFmode ) { xorsign_insn = gen_xorsigndf3_1 ; vmode = V2DFmode ; } else gcc_unreachable ( ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; emit_insn ( xorsign_insn ( dest , op0 , op1 , mask ) ) ; } </s>


<s> static enum machine_mode type_natural_mode ( tree type ) { enum machine_mode mode = TYPE_MODE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE && ! VECTOR_MODE_P ( mode ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( ( size == 8 || size == 16 ) && TYPE_VECTOR_SUBPARTS ( type ) > 1 ) { enum machine_mode innermode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) mode = MIN_MODE_VECTOR_FLOAT ; else mode = MIN_MODE_VECTOR_INT ; for ( ; mode != VOIDmode ; mode = GET_MODE_WIDER_MODE ( mode ) ) if ( GET_MODE_NUNITS ( mode ) == TYPE_VECTOR_SUBPARTS ( type ) && GET_MODE_INNER ( mode ) == innermode ) return mode ; gcc_unreachable ( ) ; } } return mode ; } </s>

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


<s> static bool sparc_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( flag_pic && GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; if ( op0 == pic_offset_table_rtx && symbolic_operand ( op1 , VOIDmode ) ) return true ; } return false ; } </s>

Return true if ADDR ( a legitimate address expression ) has an effect that depends on the machine mode it is used for . In PIC mode , ( mem : HI [ % l7+a ] ) is not equivalent to ( mem : QI [ % l7+a ] ) ( mem : QI [ % l7+a+1 ] ) because [ % l7+a+1 ] is interpreted as the address of ( a+1 ) .


<s> static tree resolve_vec_mul ( resolution * res , tree * args , tree * types , location_t loc ) { if ( TREE_CODE ( types [ 0 ] ) != VECTOR_TYPE || ! lang_hooks . types_compatible_p ( types [ 0 ] , types [ 1 ] ) ) { * res = resolved_bad ; return error_mark_node ; } switch ( TYPE_MODE ( TREE_TYPE ( types [ 0 ] ) ) ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : * res = resolved ; return fold_build2_loc ( loc , MULT_EXPR , types [ 0 ] , args [ 0 ] , fold_convert ( types [ 0 ] , args [ 1 ] ) ) ; case E_SFmode : { * res = resolved ; tree call = rs6000_builtin_decls [ RS6000_BIF_XVMULSP ] ; return build_call_expr ( call , 2 , args [ 0 ] , args [ 1 ] ) ; } case E_DFmode : { * res = resolved ; tree call = rs6000_builtin_decls [ RS6000_BIF_XVMULDP ] ; return build_call_expr ( call , 2 , args [ 0 ] , args [ 1 ] ) ; } default : * res = resolved_bad ; return error_mark_node ; } } </s>

Resolve an overloaded vec_mul call and return a tree expression for the resolved call if successful . ARGS contains the arguments to the call . TYPES contains their types . RES must be set to indicate the status of the resolution attempt . LOC contains statement location information .


<s> bool Cpu0SEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Cpu0 :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


runOnMachineFunction - Emit the function body .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
*
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
false
;
for
(
const
MachineOperand
&
MO
:
Orig
->
operands
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
MO
.
getReg
(
)
==
X86
::
EFLAGS
)
{
ClobbersEFLAGS
=
true
;
break
;
}
}
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
->
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
addOperand
(
Orig
->
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
*
NewMI
=
std
::
prev
(
I
)
;
NewMI
->
substituteRegister
(
Orig
->
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return C_RegisterClass ; case 'I' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCInst LoweredMI ; switch ( MI -> getOpcode ( ) ) { case SystemZ :: Return : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R14D ) ; break ; case SystemZ :: CallBRASL : LoweredMI = MCInstBuilder ( SystemZ :: BRASL ) . addReg ( SystemZ :: R14D ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBASR : LoweredMI = MCInstBuilder ( SystemZ :: BASR ) . addReg ( SystemZ :: R14D ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; break ; case SystemZ :: CallJG : LoweredMI = MCInstBuilder ( SystemZ :: JG ) . addExpr ( Lower . getExpr ( MI -> getOperand ( 0 ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case SystemZ :: CallBR : LoweredMI = MCInstBuilder ( SystemZ :: BR ) . addReg ( SystemZ :: R1D ) ; break ; case SystemZ :: IILF64 : LoweredMI = MCInstBuilder ( SystemZ :: IILF ) . addReg ( SystemZMC :: getRegAsGR32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: IIHF64 : LoweredMI = MCInstBuilder ( SystemZ :: IIHF ) . addReg ( SystemZMC :: getRegAsGRH32 ( MI -> getOperand ( 0 ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( 2 ) . getImm ( ) ) ; break ; case SystemZ :: RISBHH : case SystemZ :: RISBHL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBHG ) ; break ; case SystemZ :: RISBLH : case SystemZ :: RISBLL : LoweredMI = lowerRIEfLow ( MI , SystemZ :: RISBLG ) ; break ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRILow ( MI , SystemZ :: NAME ) ; break LOWER_LOW ( IILL ) ; LOWER_LOW ( IILH ) ; LOWER_LOW ( TMLL ) ; LOWER_LOW ( TMLH ) ; LOWER_LOW ( NILL ) ; LOWER_LOW ( NILH ) ; LOWER_LOW ( NILF ) ; LOWER_LOW ( OILL ) ; LOWER_LOW ( OILH ) ; LOWER_LOW ( OILF ) ; LOWER_LOW ( XILF ) ; case SystemZ :: NAME ## 64 : LoweredMI = lowerRIHigh ( MI , SystemZ :: NAME ) ; break LOWER_HIGH ( IIHL ) ; LOWER_HIGH ( IIHH ) ; LOWER_HIGH ( TMHL ) ; LOWER_HIGH ( TMHH ) ; LOWER_HIGH ( NIHL ) ; LOWER_HIGH ( NIHH ) ; LOWER_HIGH ( NIHF ) ; LOWER_HIGH ( OIHL ) ; LOWER_HIGH ( OIHH ) ; LOWER_HIGH ( OIHF ) ; LOWER_HIGH ( XIHF ) ; default : Lower . lower ( MI , LoweredMI ) ; break ; } OutStreamer . EmitInstruction ( LoweredMI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( 0 ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> int eligible_for_return_delay ( rtx trial ) { rtx pat ; if ( GET_CODE ( trial ) != INSN || GET_CODE ( PATTERN ( trial ) ) != SET ) return 0 ; if ( get_attr_length ( trial ) != 1 ) return 0 ; if ( num_gfregs ) return 0 ; if ( current_function_calls_eh_return ) return 0 ; if ( sparc_leaf_function_p ) return get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ; pat = PATTERN ( trial ) ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= 8 && REGNO ( SET_DEST ( pat ) ) < 24 ) ) return 0 ; if ( REGNO ( SET_DEST ( pat ) ) >= 32 ) return ( TARGET_V9 && ! epilogue_renumber ( & pat , 1 ) && ( get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ) ) ; return eligible_for_restore_insn ( trial , true ) ; } </s>

Return nonzero if TRIAL can go into the function return 's delay slot .


<s> static inline TOCKey getTombstoneKey ( ) { return { nullptr , MCSymbolRefExpr :: VariantKind :: VK_Invalid } ; } </s>

Difference in tombstone is that the Optional is meaningful .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Fixup Store Forward Block"
;
}
</s>


<s> static void ix86_set_current_function ( tree fndecl ) { if ( fndecl == ix86_previous_fndecl ) return ; tree old_tree ; if ( ix86_previous_fndecl == NULL_TREE ) old_tree = target_option_current_node ; else if ( DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ; else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> static bool ix86_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case asin_optab : case acos_optab : case log1p_optab : case exp_optab : case exp10_optab : case exp2_optab : case expm1_optab : case ldexp_optab : case scalb_optab : case round_optab : case lround_optab : return opt_type == OPTIMIZE_FOR_SPEED ; case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_SSE4_1 && mode1 != HFmode ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( ( ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && TARGET_SSE4_1 ) || mode1 == HFmode ) && ! flag_trapping_math ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( mode1 ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s>
bool
RegDefsUses
::
update
(
const
MachineInstr
&
MI
,
unsigned
Begin
,
unsigned
End
)
{
BitVector
NewDefs
(
TRI
.
getNumRegs
(
)
)
,
NewUses
(
TRI
.
getNumRegs
(
)
)
;
bool
HasHazard
=
false
;
for
(
unsigned
I
=
Begin
;
I
!=
End
;
++
I
)
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
I
)
;
if
(
MO
.
isReg
(
)
&&
MO
.
getReg
(
)
)
{
if
(
checkRegDefsUses
(
NewDefs
,
NewUses
,
MO
.
getReg
(
)
,
MO
.
isDef
(
)
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
DEBUG_TYPE
": found register hazard for operand "
<<
I
<<
": "
;
MO
.
dump
(
)
)
;
HasHazard
=
true
;
}
}
}
Defs
|=
NewDefs
;
Uses
|=
NewUses
;
return
HasHazard
;
}
</s>

Mips
": found register hazard for operand "
": "


<s> static short find_insn_regmode_weight ( rtx insn , enum machine_mode mode ) { short reg_weight = 0 ; rtx x ; x = PATTERN ( insn ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; if ( GET_CODE ( x ) == PARALLEL ) { int j ; for ( j = XVECLEN ( x , 0 ) - 1 ; j >= 0 ; j -- ) { x = XVECEXP ( PATTERN ( insn ) , 0 , j ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; } } for ( x = REG_NOTES ( insn ) ; x ; x = XEXP ( x , 1 ) ) { if ( REG_NOTE_KIND ( x ) == REG_DEAD || REG_NOTE_KIND ( x ) == REG_UNUSED ) { rtx note = XEXP ( x , 0 ) ; if ( GET_CODE ( note ) == REG && GET_MODE ( note ) == mode ) reg_weight -- ; } } return reg_weight ; } </s>


<s> bool MipsTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_MipsO32 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> const SICTargetLowering * SICTargetLowering :: create ( const SICTargetMachine & TM , const SICSubtarget & STI ) { return new SICTargetLowering ( TM , STI ) ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"MIPS Os16 Optimization"
;
}
</s>

getPassName - Return a nice clean name for a pass .


Return the probing interval for -fstack-clash-protection .


Return TRUE if the type , as described by TYPE and MODE , is a short vector type as described in AAPCS64 \S 4.1.2 . See the comment above aarch64_composite_type_p for the notes on MODE .


<s> bool LC2200PassConfig :: addInstSelector ( ) { addPass ( createLC2200ISelDag ( getLC2200TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static tree aarch64_builtin_reciprocal ( tree fndecl ) { machine_mode mode = TYPE_MODE ( TREE_TYPE ( fndecl ) ) ; if ( ! use_rsqrt_p ( mode ) ) return NULL_TREE ; return aarch64_builtin_rsqrt ( DECL_FUNCTION_CODE ( fndecl ) ) ; } </s>

Function to decide when to use the approximate reciprocal square root builtin .


<s> void altivec_expand_stvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx store = gen_rtx_SET ( op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( par ) ; } </s>

Generate code for a `` stvx '' or `` stvxl '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s> void sparc_profile_hook ( int labelno ) { char buf [ 32 ] ; rtx lab , fun ; fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_FUNCTION ) ; if ( NO_PROFILE_COUNTERS ) { emit_library_call ( fun , LCT_NORMAL , VOIDmode ) ; } else { ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; lab = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; emit_library_call ( fun , LCT_NORMAL , VOIDmode , lab , Pmode ) ; } } </s>

Output rtl to increment the profiler label LABELNO for profiling a function entry .


<s> class LLVM_LIBRARY_VISIBILITY SystemZMCInstLower { Mangler * Mang ; MCContext & Ctx ; SystemZAsmPrinter & AsmPrinter ; public : SystemZMCInstLower ( Mangler * mang , MCContext & ctx , SystemZAsmPrinter & asmPrinter ) ; void lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerOperand ( const MachineOperand & MO ) const ; const MCExpr * getExpr ( const MachineOperand & MO , MCSymbolRefExpr :: VariantKind Kind ) const ; } </s>

Implementation of the SCEVPredicate interface .


<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static int pad_groups ( FILE * dump , int sched_verbose , rtx prev_head_insn , rtx tail ) { rtx insn , next_insn ; rtx nop ; int issue_rate ; int can_issue_more ; int group_end ; int group_count = 0 ; issue_rate = rs6000_issue_rate ( ) ; can_issue_more = issue_rate ; insn = get_next_active_insn ( prev_head_insn , tail ) ; next_insn = get_next_active_insn ( insn , tail ) ; while ( insn != NULL_RTX ) { can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; group_end = ( next_insn == NULL_RTX || GET_MODE ( next_insn ) == TImode ) ; if ( next_insn == NULL_RTX ) break ; if ( group_end ) { if ( can_issue_more && ( rs6000_sched_insert_nops == sched_finish_pad_groups ) && ! insn_terminates_group_p ( insn , current_group ) && ! insn_terminates_group_p ( next_insn , previous_group ) ) { if ( ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; while ( can_issue_more ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } } can_issue_more = issue_rate ; group_count ++ ; } insn = next_insn ; next_insn = get_next_active_insn ( insn , tail ) ; } return group_count ; } </s>

Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the dispatch group boundaries that the scheduler had marked . Pad with nops any dispatch groups which have vacant issue slots , in order to force the scheduler 's grouping on the processor dispatcher . The function returns the number of dispatch groups found .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
false
;
for
(
const
MachineOperand
&
MO
:
Orig
.
operands
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
MO
.
getReg
(
)
==
X86
::
EFLAGS
)
{
ClobbersEFLAGS
=
true
;
break
;
}
}
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
add
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; AArch64BranchTargetAligner BTA ; unsigned Opcode = Inst . getOpcode ( ) ; if ( BTA . needsSpecialAlignment ( STI . getCPU ( ) , Opcode ) ) { unsigned BA = BTA . getBranchTargetAlignment ( Inst ) ; if ( BA ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitCodeAlignment ( BA ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> MachineInstr * Thumb2InstrInfo :: optimizeSelect ( MachineInstr & MI , SmallPtrSetImpl < MachineInstr * > & SeenMIs , bool PreferFalse ) const { MachineInstr * RV = ARMBaseInstrInfo :: optimizeSelect ( MI , SeenMIs , PreferFalse ) ; if ( ! RV && getSubtarget ( ) . hasV8_1MMainlineOps ( ) && ! PreferNoCSEL ) { Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( ! DestReg . isVirtual ( ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( ARM :: t2CSEL ) , DestReg ) . add ( MI . getOperand ( 2 ) ) . add ( MI . getOperand ( 1 ) ) . add ( MI . getOperand ( 3 ) ) ; SeenMIs . insert ( NewMI ) ; return NewMI ; } return RV ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool mips_expand_vec_perm_const ( rtx operands [ 4 ] ) { struct expand_vec_perm_d d ; int i , nelt , which ; unsigned char orig_perm [ MAX_VECT_LEN ] ; rtx sel ; bool ok ; d . target = operands [ 0 ] ; d . op0 = operands [ 1 ] ; d . op1 = operands [ 2 ] ; sel = operands [ 3 ] ; d . vmode = GET_MODE ( d . target ) ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = false ; memset ( orig_perm , 0 , MAX_VECT_LEN ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { rtx e = XVECEXP ( sel , 0 , i ) ; int ei = INTVAL ( e ) & ( 2 * nelt - 1 ) ; which |= ( ei < nelt ? 1 : 2 ) ; orig_perm [ i ] = ei ; } memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; switch ( which ) { default : gcc_unreachable ( ) ; case 3 : d . one_vector_p = false ; if ( ! rtx_equal_p ( d . op0 , d . op1 ) ) break ; case 2 : for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] &= nelt - 1 ; d . op0 = d . op1 ; d . one_vector_p = true ; break ; case 1 : d . op1 = d . op0 ; d . one_vector_p = true ; break ; } ok = mips_expand_vec_perm_const_1 ( & d ) ; if ( ! ok && which == 3 ) { d . op0 = operands [ 1 ] ; d . op1 = operands [ 2 ] ; d . one_vector_p = false ; memcpy ( d . perm , orig_perm , MAX_VECT_LEN ) ; ok = mips_expand_vec_perm_const_1 ( & d ) ; } return ok ; } </s>


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_PREL_G3
:
return
":prel_g3:"
;
case
VK_PREL_G2
:
return
":prel_g2:"
;
case
VK_PREL_G2_NC
:
return
":prel_g2_nc:"
;
case
VK_PREL_G1
:
return
":prel_g1:"
;
case
VK_PREL_G1_NC
:
return
":prel_g1_nc:"
;
case
VK_PREL_G0
:
return
":prel_g0:"
;
case
VK_PREL_G0_NC
:
return
":prel_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT
:
return
":got:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_PAGE_LO15
:
return
":gotpage_lo15:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL
:
return
":gottprel:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s>
unsigned
LC2200InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
reverse_iterator
I
=
MBB
.
rbegin
(
)
,
REnd
=
MBB
.
rend
(
)
;
unsigned
removed
=
0
;
while
(
I
!=
REnd
&&
removed
<
2
)
{
if
(
I
->
isDebugInstr
(
)
)
{
++
I
;
continue
;
}
if
(
!
getAnalyzableBrOpc
(
I
->
getOpcode
(
)
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
rbegin
(
)
;
++
removed
;
}
return
removed
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT . isPS4 ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getCPUDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> static tree find_sole_member ( tree type ) { tree field , member = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_SIZE ( field ) ) return NULL_TREE ; if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( member ) return NULL_TREE ; member = field ; } return member ; } </s>

TYPE is a RECORD_TYPE . If there is only a single non-zero-sized member , return it .


<s>
const
CallLowering
*
ARMSubtarget
::
getCallLowering
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getCallLowering
(
)
;
}
</s>

ARM
ARM
"Access to GlobalISel APIs not set"


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
XOR32rr
)
)
;
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
KSET0B
:
case
X86
::
KSET0W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORWrr
)
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORWrr
)
)
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
void
ARMConstantIslands
::
verify
(
MachineFunction
&
MF
)
{
assert
(
BBOffsets
.
size
(
)
==
BBSizes
.
size
(
)
)
;
for
(
unsigned
i
=
1
,
e
=
BBOffsets
.
size
(
)
;
i
!=
e
;
++
i
)
assert
(
BBOffsets
[
i
1
]
+
BBSizes
[
i
1
]
==
BBOffsets
[
i
]
)
;
if
(
!
isThumb
)
return
;
for
(
MachineFunction
::
iterator
MBBI
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBBI
!=
E
;
++
MBBI
)
{
MachineBasicBlock
*
MBB
=
MBBI
;
if
(
!
MBB
->
empty
(
)
&&
MBB
->
begin
(
)
->
getOpcode
(
)
==
ARM
::
CONSTPOOL_ENTRY
)
{
unsigned
MBBId
=
MBB
->
getNumber
(
)
;
assert
(
HasInlineAsm
||
(
BBOffsets
[
MBBId
]
%
4
==
0
&&
BBSizes
[
MBBId
]
%
4
==
0
)
||
(
BBOffsets
[
MBBId
]
%
4
!=
0
&&
BBSizes
[
MBBId
]
%
4
!=
0
)
)
;
}
}
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
GetOffsetOf
(
U
.
MI
)
+
(
isThumb
4
:
8
)
;
unsigned
CPEOffset
=
GetOffsetOf
(
U
.
CPEMI
)
;
unsigned
Disp
=
UserOffset
<
CPEOffset
CPEOffset
UserOffset
:
UserOffset
CPEOffset
;
assert
(
Disp
<=
U
.
MaxDisp
||
"Constant pool entry out of range!"
)
;
}
}
</s>


<s> static void rs6000_live_on_entry ( bitmap regs ) { if ( flag_split_stack ) bitmap_set_bit ( regs , 12 ) ; } </s>

We may have to tell the dataflow pass that the split stack prologue is initializing a register .


<s> void order_regs_for_local_alloc ( ) { static int last_order_nonleaf = 1 ; if ( regs_ever_live [ 15 ] != last_order_nonleaf ) { last_order_nonleaf = ! last_order_nonleaf ; memcpy ( ( char * ) reg_alloc_order , ( const char * ) reg_alloc_orders [ last_order_nonleaf ] , FIRST_PSEUDO_REGISTER * sizeof ( int ) ) ; } } </s>

Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override { uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0x60000000 , Endian ) ; OS . write_zeros ( Count % 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void expand_fusion_gpr_load ( rtx * operands ) { rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == ZERO_EXTEND || ( TARGET_P8_FUSION_SIGN && GET_CODE ( orig_mem ) == SIGN_EXTEND ) ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( ZERO_EXTEND , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_GPR ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , new_mem ) ) ; if ( extend == SIGN_EXTEND ) { int sub_off = ( ( BYTES_BIG_ENDIAN ) ? GET_MODE_SIZE ( extend_mode ) - GET_MODE_SIZE ( target_mode ) : 0 ) ; rtx sign_reg = simplify_subreg ( target_mode , target , extend_mode , sub_off ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_SIGN_EXTEND ( extend_mode , sign_reg ) ) ) ; } return ; } </s>

During the peephole2 pass , adjust and expand the insns for a load fusion sequence . We adjust the addis register to use the target register . If the load sign extends , we adjust the code to do the zero extending load , and an explicit sign extension later since the fusion only covers zero extending loads . The operands are : operands [ 0 ] register set with addis ( to be replaced with target ) operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LW_P8
:
Mips
::
LW
;
else
if
(
Mips
::
CPU64RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LD_P8
:
Mips
::
LD
;
else
if
(
Mips
::
FGR32RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LWC1_P8
:
Mips
::
LWC1
;
else
if
(
Mips
::
AFGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
LDC1
;
else
if
(
Mips
::
FGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
LDC164_P8
:
Mips
::
LDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static void sh_va_start ( tree valist , rtx nextarg ) { tree f_next_o , f_next_o_limit , f_next_fp , f_next_fp_limit , f_next_stack ; tree next_o , next_o_limit , next_fp , next_fp_limit , next_stack ; tree t , u ; int nfp , nint ; if ( TARGET_SH5 ) { expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist , nextarg ) ; return ; } if ( ( ! TARGET_SH2E && ! TARGET_SH4 ) || TARGET_HITACHI || sh_cfun_attr_renesas_p ( ) ) { std_expand_builtin_va_start ( valist , nextarg ) ; return ; } f_next_o = TYPE_FIELDS ( va_list_type_node ) ; f_next_o_limit = DECL_CHAIN ( f_next_o ) ; f_next_fp = DECL_CHAIN ( f_next_o_limit ) ; f_next_fp_limit = DECL_CHAIN ( f_next_fp ) ; f_next_stack = DECL_CHAIN ( f_next_fp_limit ) ; next_o = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_o ) , valist , f_next_o , NULL_TREE ) ; next_o_limit = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_o_limit ) , valist , f_next_o_limit , NULL_TREE ) ; next_fp = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_fp ) , valist , f_next_fp , NULL_TREE ) ; next_fp_limit = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_fp_limit ) , valist , f_next_fp_limit , NULL_TREE ) ; next_stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_stack ) , valist , f_next_stack , NULL_TREE ) ; u = make_tree ( sizetype , expand_builtin_saveregs ( ) ) ; u = fold_convert ( ptr_type_node , u ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_fp , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nfp = crtl -> args . info . arg_count [ SH_ARG_FLOAT ] ; if ( nfp < 8 ) nfp = 8 - nfp ; else nfp = 0 ; u = fold_build_pointer_plus_hwi ( u , UNITS_PER_WORD * nfp ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_fp_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_o , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nint = crtl -> args . info . arg_count [ SH_ARG_INT ] ; if ( nint < 4 ) nint = 4 - nint ; else nint = 0 ; u = fold_build_pointer_plus_hwi ( u , UNITS_PER_WORD * nint ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_o_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , nextarg ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_stack , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s> static bool aarch64_decl_is_long_call_p ( const_tree decl ATTRIBUTE_UNUSED ) { return false ; } </s>

Return true if calls to DECL should be treated as long-calls ( ie called via a register ) .


<s> const MCExpr * ARMTargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr , SMLoc Loc ) { return ConstantPools -> addEntry ( Streamer , Expr , 4 , Loc ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s> void AnalyzeReturn ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( Outs ) ; CCState :: AnalyzeReturn ( Outs , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeReturn - Analyze the returned values of a return , incorporating info about the result values into this state .


<s>
bool
LVLGen
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** Begin LVLGen **********\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** Function: "
<<
F
.
getName
(
)
<<
'\n'
)
;
LLVM_DEBUG
(
F
.
dump
(
)
)
;
bool
Changed
=
false
;
const
VESubtarget
&
Subtarget
=
F
.
getSubtarget
<
VESubtarget
>
(
)
;
TII
=
Subtarget
.
getInstrInfo
(
)
;
TRI
=
Subtarget
.
getRegisterInfo
(
)
;
for
(
MachineBasicBlock
&
MBB
:
F
)
Changed
|=
runOnMachineBasicBlock
(
MBB
)
;
if
(
Changed
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
F
.
dump
(
)
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"********** End LVLGen **********\n"
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool aarch64_sve_pred_dominates_p ( rtx * pred1 , rtx pred2 ) { machine_mode mode = GET_MODE ( pred2 ) ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && mode == GET_MODE ( pred1 [ 0 ] ) && aarch64_sve_gp_strictness ( pred1 [ 1 ] , SImode ) ) ; return ( pred1 [ 0 ] == CONSTM1_RTX ( mode ) || INTVAL ( pred1 [ 1 ] ) == SVE_RELAXED_GP || rtx_equal_p ( pred1 [ 0 ] , pred2 ) ) ; } </s>

Return true if predicate PRED1 [ 0 ] is true whenever predicate PRED2 is true , or alternatively if we know that the operation predicated by PRED1 [ 0 ] is safe to perform whenever PRED2 is true . PRED1 [ 1 ] is a aarch64_sve_gp_strictness operand that describes the operation predicated by PRED1 [ 0 ] .


<s> static bool abi_v4_pass_in_fpr ( machine_mode mode , bool named ) { if ( ! TARGET_HARD_FLOAT ) return false ; if ( TARGET_DOUBLE_FLOAT && mode == DFmode ) return true ; if ( TARGET_SINGLE_FLOAT && mode == SFmode && named ) return true ; if ( is_complex_IBM_long_double ( mode ) ) return false ; if ( FLOAT128_2REG_P ( mode ) ) return true ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return true ; return false ; } </s>

Whether ABI_V4 passes MODE args to a function in floating point registers .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . EmitCodeAlignment ( Alignment , Alignment ) ; else OS . EmitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void x86_output_aligned_bss ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) switch_to_section ( get_named_section ( decl , ".lbss" , 0 ) ) ; else switch_to_section ( bss_section ) ; ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ; ASM_OUTPUT_LABEL ( file , name ) ; ASM_OUTPUT_SKIP ( file , size ? size : 1 ) ; } </s>

Utility function for targets to use in implementing ASM_OUTPUT_ALIGNED_BSS .


Find a spare low register to use during the prolog of a function .


<s> int MipsAsmParser :: tryParseRegister ( StringRef Mnemonic ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; else return RegNum ; if ( isMips64 ( ) && RegNum == Mips :: ZERO_64 ) { if ( Mnemonic . find ( "ddiv" ) != StringRef :: npos ) RegNum = Mips :: ZERO ; } return RegNum ; } </s>

tryParseRegister - parse one register if possible

Mips Mips 1 Mips Mips::ZERO_64 "ddiv" Mips::ZERO


<s>
StringRef
getPassName
(
)
const
override
{
return
"MIPS16 Hard Float Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


Change register usage conditional on target flags .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


"64-bit code requested on a subtarget that doesn't support it!"


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
(
Divisor
)
.
isPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasCMov
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
APInt
Lg2Mask
=
APInt
::
getLowBitsSet
(
VT
.
getSizeInBits
(
)
,
Lg2
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
Lg2Mask
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i64
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
bool
hasHardQuad
=
Subtarget
->
hasHardQuad
(
)
;
bool
is64Bit
=
Subtarget
->
is64Bit
(
)
;
bool
isV9
=
Subtarget
->
isV9
(
)
;
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
,
*
this
,
hasHardQuad
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
,
*
this
,
hasHardQuad
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
,
*
this
,
hasHardQuad
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
,
*
this
,
hasHardQuad
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerF128Load
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerF128Store
(
Op
,
DAG
)
;
case
ISD
::
FADD
:
return
LowerF128Op
(
Op
,
DAG
,
getLibcallName
(
RTLIB
::
ADD_F128
)
,
2
)
;
case
ISD
::
FSUB
:
return
LowerF128Op
(
Op
,
DAG
,
getLibcallName
(
RTLIB
::
SUB_F128
)
,
2
)
;
case
ISD
::
FMUL
:
return
LowerF128Op
(
Op
,
DAG
,
getLibcallName
(
RTLIB
::
MUL_F128
)
,
2
)
;
case
ISD
::
FDIV
:
return
LowerF128Op
(
Op
,
DAG
,
getLibcallName
(
RTLIB
::
DIV_F128
)
,
2
)
;
case
ISD
::
FSQRT
:
return
LowerF128Op
(
Op
,
DAG
,
getLibcallName
(
RTLIB
::
SQRT_F128
)
,
1
)
;
case
ISD
::
FNEG
:
return
LowerFNEG
(
Op
,
DAG
,
*
this
,
is64Bit
)
;
case
ISD
::
FABS
:
return
LowerFABS
(
Op
,
DAG
,
isV9
)
;
case
ISD
::
FP_EXTEND
:
return
LowerF128_FPEXTEND
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
FP_ROUND
:
return
LowerF128_FPROUND
(
Op
,
DAG
,
*
this
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
FISC
::
NumTargetFixupKinds
]
=
{
{
"fixup_fisc_mov_q1_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_mov_q2_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_mov_q3_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_mov_q4_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_call26_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_call19_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_9bit_address"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_6bit_shamt"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_12bit_imm"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_movrz_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
void
X86IntelInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> bool MicroMipsSizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> inMicroMipsMode ( ) || ! Subtarget -> hasMips32r2 ( ) ) return false ; MipsII = static_cast < const MipsInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; bool Modified = false ; MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; for ( ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>


"Expected VPT block to start with a VPST or VPT!"

Returns true if this iterator is still pointing at a valid entry .


<s> const Cpu0RegisterInfo & Cpu0SEInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool rs6000_global_entry_point_needed_p ( void ) { if ( DEFAULT_ABI != ABI_ELFv2 ) return false ; if ( TARGET_SINGLE_PIC_BASE ) return false ; if ( cfun -> is_thunk ) return true ; return cfun -> machine -> r2_setup_needed ; } </s>

Return whether we need to emit an ELFv2 global entry point prologue .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> void FISCFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) return ; unsigned StackReg = FISC :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( FISC :: ADDrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( FISC :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

FISC FISC FISC::SP FISC::ADDrr FISC::ADDri


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; bool BranchWithZeroOperand = ( I -> isBranch ( ) && ! I -> isPseudo ( ) && I -> getOperand ( 1 ) . isReg ( ) && ( I -> getOperand ( 1 ) . getReg ( ) == Mips :: ZERO || I -> getOperand ( 1 ) . getReg ( ) == Mips :: ZERO_64 ) ) ; if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; } else if ( BranchWithZeroOperand ) { MIB . addOperand ( I -> getOperand ( 0 ) ) ; for ( unsigned J = 2 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> static unsigned int aarch64_detect_vector_stmt_subtype ( vec_info * vinfo , vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , enum vect_cost_model_location where , unsigned int stmt_cost ) { const simd_vec_cost * simd_costs = aarch64_simd_vec_costs ( vectype ) ; const sve_vec_cost * sve_costs = nullptr ; if ( aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) ) sve_costs = aarch64_tune_params . vec_costs -> sve ; if ( is_a < gphi * > ( stmt_info -> stmt ) ) return 0 ; if ( kind == vec_to_scalar && STMT_VINFO_DATA_REF ( stmt_info ) && DR_IS_WRITE ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) return simd_costs -> store_elt_extra_cost ; if ( kind == scalar_store && sve_costs && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_GATHER_SCATTER ) return sve_costs -> scatter_store_elt_cost ; if ( kind == vec_to_scalar && where == vect_body && sve_costs ) { unsigned int latency = aarch64_sve_in_loop_reduction_latency ( vinfo , stmt_info , vectype , sve_costs ) ; if ( latency ) return latency ; } if ( kind == vec_to_scalar && where == vect_epilogue && aarch64_is_reduction ( stmt_info ) ) switch ( GET_MODE_INNER ( TYPE_MODE ( vectype ) ) ) { case E_QImode : return simd_costs -> reduc_i8_cost ; case E_HImode : return simd_costs -> reduc_i16_cost ; case E_SImode : return simd_costs -> reduc_i32_cost ; case E_DImode : return simd_costs -> reduc_i64_cost ; case E_HFmode : case E_BFmode : return simd_costs -> reduc_f16_cost ; case E_SFmode : return simd_costs -> reduc_f32_cost ; case E_DFmode : return simd_costs -> reduc_f64_cost ; default : break ; } return stmt_cost ; } </s>

STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost for the vectorized form of STMT_INFO , which has cost kind KIND and which when vectorized would operate on vector type VECTYPE . Try to subdivide the target-independent categorization provided by KIND to get a more accurate cost . WHERE specifies where the cost associated with KIND occurs .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> static bool ix86_function_ok_for_sibcall ( tree decl , tree exp ) { tree func ; rtx a , b ; if ( ! TARGET_64BIT && flag_pic && ( ! decl || TREE_PUBLIC ( decl ) ) ) return false ; if ( decl ) func = decl ; else { func = TREE_TYPE ( TREE_OPERAND ( exp , 0 ) ) ; if ( POINTER_TYPE_P ( func ) ) func = TREE_TYPE ( func ) ; } a = ix86_function_value ( TREE_TYPE ( exp ) , func , false ) ; b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( ! decl && ! TARGET_64BIT ) { tree type ; type = TREE_OPERAND ( exp , 0 ) ; type = TREE_TYPE ( type ) ; type = TREE_TYPE ( type ) ; if ( ix86_function_regparm ( type , NULL ) >= 3 ) { return false ; } } if ( decl && DECL_DLLIMPORT_P ( decl ) && ix86_function_regparm ( TREE_TYPE ( decl ) , NULL ) >= 3 ) return false ; if ( cfun -> machine -> force_align_arg_pointer ) return false ; return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s>
bool
X86DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Op0
,
Op1
,
Op2
,
Op3
,
Op4
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_v
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_X
:
if
(
!
selectAddr
(
nullptr
,
Op
,
Op0
,
Op1
,
Op2
,
Op3
,
Op4
)
)
return
true
;
break
;
}
OutOps
.
push_back
(
Op0
)
;
OutOps
.
push_back
(
Op1
)
;
OutOps
.
push_back
(
Op2
)
;
OutOps
.
push_back
(
Op3
)
;
OutOps
.
push_back
(
Op4
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool X86TTIImpl :: canMacroFuseCmp ( ) { return ST -> hasMacroFusion ( ) ; } </s>

Return true if the target can fuse a compare and branch .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : case ISD :: ROTL : return combineSHIFTROT ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool PPCTargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


"C++ constructor pointer had zero size!"

"C++ constructor pointer was not a GlobalValue!"

Targets can override this to change how global constants that are part of a C++ static/global constructor list are emitted .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int
OffsetA
=
0
,
OffsetB
=
0
;
int
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
&&
(
MIa
->
mayLoad
(
)
||
MIa
->
mayStore
(
)
)
&&
"MIa must be a store or a load"
)
;
assert
(
MIb
&&
(
MIb
->
mayLoad
(
)
||
MIb
->
mayStore
(
)
)
&&
"MIb must be a store or a load"
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getLdStBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getLdStBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool loongarch_expand_block_move ( rtx dest , rtx src , rtx length ) { int max_move_bytes = LARCH_MAX_MOVE_BYTES_STRAIGHT ; if ( CONST_INT_P ( length ) && INTVAL ( length ) <= loongarch_max_inline_memcpy_size ) { if ( INTVAL ( length ) <= max_move_bytes ) { loongarch_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { loongarch_block_move_loop ( dest , src , INTVAL ( length ) , LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } } return false ; } </s>

Expand a cpymemsi instruction , which copies LENGTH bytes from memory reference SRC to memory reference DEST .


<s> static void ix86_emit_restore_regs_using_pop ( void ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , false ) ) ix86_emit_restore_reg_using_pop ( gen_rtx_REG ( word_mode , regno ) ) ; } </s>

Emit code to restore saved registers using POP insns .


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMLxExpansionPass ( ) ) ; if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void ARMTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { ARMELFStreamer & Streamer = getStreamer ( ) ; if ( ! Streamer . IsThumb ) return ; const MCSymbolData & SD = Streamer . getOrCreateSymbolData ( Symbol ) ; if ( MCELF :: GetType ( SD ) & ( ELF :: STT_FUNC << ELF_STT_Shift ) ) Streamer . EmitThumbFunc ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
X86
::
NumTargetFixupKinds
]
=
{
{
"reloc_riprel_4byte"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_riprel_4byte_movq_load"
,
0
,
4
*
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"reloc_signed_4byte"
,
0
,
4
*
8
,
0
}
,
{
"reloc_global_offset_table"
,
0
,
4
*
8
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
TargetAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Flag || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( TID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: Latency ; return Sched :: RegPressure ; } </s>


<s> void setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; processPHIs ( MF ) ; } </s>


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool hasDomain ( unsigned domain ) const { return AvailableDomains & ( 1u << domain ) ; } </s>


<s> const char * iq2000_fill_delay_slot ( const char * ret , enum delay_type type , rtx operands [ ] , rtx cur_insn ) { rtx set_reg ; enum machine_mode mode ; rtx next_insn = cur_insn ? NEXT_INSN ( cur_insn ) : NULL_RTX ; int num_nops ; if ( type == DELAY_LOAD || type == DELAY_FCMP ) num_nops = 1 ; else num_nops = 0 ; next_insn = NEXT_INSN ( cur_insn ) ; while ( next_insn != 0 && ( GET_CODE ( next_insn ) == NOTE || GET_CODE ( next_insn ) == CODE_LABEL ) ) next_insn = NEXT_INSN ( next_insn ) ; dslots_load_total += num_nops ; if ( TARGET_DEBUG_C_MODE || type == DELAY_NONE || operands == 0 || cur_insn == 0 || next_insn == 0 || GET_CODE ( next_insn ) == CODE_LABEL || ( set_reg = operands [ 0 ] ) == 0 ) { dslots_number_nops = 0 ; iq2000_load_reg = 0 ; iq2000_load_reg2 = 0 ; iq2000_load_reg3 = 0 ; iq2000_load_reg4 = 0 ; return ret ; } set_reg = operands [ 0 ] ; if ( set_reg == 0 ) return ret ; while ( GET_CODE ( set_reg ) == SUBREG ) set_reg = SUBREG_REG ( set_reg ) ; mode = GET_MODE ( set_reg ) ; dslots_number_nops = num_nops ; iq2000_load_reg = set_reg ; if ( GET_MODE_SIZE ( mode ) > ( unsigned ) ( UNITS_PER_WORD ) ) iq2000_load_reg2 = gen_rtx_REG ( SImode , REGNO ( set_reg ) + 1 ) ; else iq2000_load_reg2 = 0 ; return ret ; } </s>

Returns an operand string for the given instruction 's delay slot , after updating filled delay slot statistics . We assume that operands [ 0 ] is the target register that is set . In order to check the next insn , most of this functionality is moved to FINAL_PRESCAN_INSN , and we just set the global variables that it needs .


<s> rsqrts_type get_rsqrts_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrts_df3 ; case SFmode : return gen_aarch64_rsqrts_sf3 ; case V2DFmode : return gen_aarch64_rsqrts_v2df3 ; case V2SFmode : return gen_aarch64_rsqrts_v2sf3 ; case V4SFmode : return gen_aarch64_rsqrts_v4sf3 ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root series step insn depending on machine mode .


<s> bool AArch64Subtarget :: supportsAddressTopByteIgnored ( ) const { if ( ! UseAddressTopByteIgnored ) return false ; if ( TargetTriple . isiOS ( ) ) { unsigned Major , Minor , Micro ; TargetTriple . getiOSVersion ( Major , Minor , Micro ) ; return Major >= 8 ; } return false ; } </s>

CPU has TBI ( top byte of addresses is ignored during HW address translation ) and OS enables it .


<s> static void rx_get_stack_layout ( unsigned int * lowest , unsigned int * highest , unsigned int * register_mask , unsigned int * frame_size , unsigned int * stack_size ) { unsigned int reg ; unsigned int low ; unsigned int high ; unsigned int fixed_reg = 0 ; unsigned int save_mask ; unsigned int pushed_mask ; unsigned int unneeded_pushes ; if ( is_naked_func ( NULL_TREE ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = 0 ; * frame_size = 0 ; * stack_size = 0 ; return ; } for ( save_mask = high = low = 0 , reg = 1 ; reg < CC_REGNUM ; reg ++ ) { if ( ( df_regs_ever_live_p ( reg ) || ( call_used_or_fixed_reg_p ( reg ) && is_interrupt_func ( NULL_TREE ) && ! crtl -> is_leaf ) ) && ( ! call_used_or_fixed_reg_p ( reg ) || is_interrupt_func ( NULL_TREE ) || ( is_fast_interrupt_func ( NULL_TREE ) && ! IN_RANGE ( reg , 10 , 13 ) ) ) ) { if ( low == 0 ) low = reg ; high = reg ; save_mask |= 1 << reg ; } if ( low != 0 && fixed_reg == 0 && fixed_regs [ reg ] ) fixed_reg = reg ; } if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < 2 ) { save_mask |= ( 1 << 13 ) | ( 1 << 14 ) ; if ( low == 0 ) low = 13 ; if ( high == 0 || low == high ) high = low + 1 ; } pushed_mask = ( HOST_WIDE_INT_M1U << low ) & ~ ( HOST_WIDE_INT_M1U << ( high + 1 ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = 0 ; * highest = 0 ; * register_mask = save_mask ; } else { * lowest = low ; * highest = high ; * register_mask = 0 ; } * frame_size = rx_round_up ( get_frame_size ( ) , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( crtl -> args . size > 0 ) * frame_size += rx_round_up ( crtl -> args . size , STACK_BOUNDARY / BITS_PER_UNIT ) ; * stack_size = rx_round_up ( crtl -> outgoing_args_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>

Returns either the lowest numbered and highest numbered registers that occupy the call-saved area of the stack frame , if the registers are stored as a contiguous block , or else a bitmask of the individual registers if they are stored piecemeal . Also computes the size of the frame and the size of the outgoing arguments block ( in bytes ) .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static bool exact_dependency_1 ( rtx addr , rtx insn ) { enum rtx_code code ; const char * format_ptr ; int i , j ; code = GET_CODE ( insn ) ; switch ( code ) { case MEM : if ( rtx_equal_p ( addr , insn ) ) return true ; break ; case REG : CASE_CONST_ANY : case SYMBOL_REF : case CODE_LABEL : case PC : case CC0 : case EXPR_LIST : return false ; default : break ; } format_ptr = GET_RTX_FORMAT ( code ) ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; i ++ ) { switch ( * format_ptr ++ ) { case 'e' : if ( exact_dependency_1 ( addr , XEXP ( insn , i ) ) ) return true ; break ; case 'E' : for ( j = 0 ; j < XVECLEN ( insn , i ) ; j ++ ) if ( exact_dependency_1 ( addr , XVECEXP ( insn , i , j ) ) ) return true ; break ; } } return false ; } </s>

Helper function for exact_store_load_dependency . Return true if addr is found in insn .


<s> int rx_initial_elimination_offset ( int from , int to ) { unsigned int low ; unsigned int high ; unsigned int frame_size ; unsigned int stack_size ; unsigned int mask ; rx_get_stack_layout ( & low , & high , & mask , & frame_size , & stack_size ) ; if ( from == ARG_POINTER_REGNUM ) { if ( low ) frame_size += ( ( high - low ) + 1 ) * UNITS_PER_WORD ; else frame_size += bit_count ( mask ) * UNITS_PER_WORD ; frame_size += 1 * UNITS_PER_WORD ; if ( to == FRAME_POINTER_REGNUM ) return frame_size ; gcc_assert ( to == STACK_POINTER_REGNUM ) ; return frame_size + stack_size ; } gcc_assert ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) ; return stack_size ; } </s>

Compute the offset ( in words ) between FROM ( arg pointer or frame pointer ) and TO ( frame pointer or stack pointer ) . See ASCII art comment at the start of rx_expand_prologue for more information .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 || ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG && UI -> getOpcode ( ) != X86ISD :: CPS_RET ) return false ; if ( UI -> getNumOperands ( ) > 4 ) return false ; if ( UI -> getNumOperands ( ) == 4 && UI -> getOperand ( UI -> getNumOperands ( ) - 1 ) . getValueType ( ) != MVT :: Glue ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


"stack frame not a multiple of octabyte: %wd"

Expands the function epilogue into RTX .


<s>
SDNode
*
OR1KDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
SDValue
imm
=
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
OR1K
::
ADDI
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
,
imm
)
;
return
CurDAG
->
getMachineNode
(
Opc
,
dl
,
VT
,
TFI
,
imm
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static void ATTRIBUTE_UNUSED mips_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.dtprelword\t" , file ) ; break ; case 8 : fputs ( "\t.dtpreldword\t" , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; fputs ( "+0x8000" , file ) ; } </s>


<s> void rs6000_output_function_entry ( FILE * file , const char * fname ) { if ( fname [ 0 ] != '.' ) { switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , "L." ) ; break ; case ABI_ELFv2 : case ABI_V4 : case ABI_DARWIN : break ; } } RS6000_OUTPUT_BASENAME ( file , fname ) ; } </s>


<s> bool PPCInstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case PPC :: FADD : case PPC :: FADDS : case PPC :: FMUL : case PPC :: FMULS : case PPC :: VADDFP : case PPC :: XSADDDP : case PPC :: XVADDDP : case PPC :: XVADDSP : case PPC :: XSADDSP : case PPC :: XSMULDP : case PPC :: XVMULDP : case PPC :: XVMULSP : case PPC :: XSMULSP : case PPC :: QVFADD : case PPC :: QVFADDS : case PPC :: QVFADDSs : case PPC :: QVFMUL : case PPC :: QVFMULS : case PPC :: QVFMULSs : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .

PowerPC PPC PPC::FADD PPC::FADDS PPC::FMUL PPC::FMULS PPC::VADDFP PPC::XSADDDP PPC::XVADDDP PPC::XVADDSP PPC::XSADDSP PPC::XSMULDP PPC::XVMULDP PPC::XVMULSP PPC::XSMULSP PPC::QVFADD PPC::QVFADDS PPC::QVFADDSs PPC::QVFMUL PPC::QVFMULS PPC::QVFMULSs


<s> bool SystemZRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const MipsSubtarget & ST = MF . getTarget ( ) . getSubtarget < MipsSubtarget > ( ) ; const TargetRegisterClass * RC = ST . isABI_N64 ( ) ? ( const TargetRegisterClass * ) & Mips :: CPU64RegsRegClass : ( const TargetRegisterClass * ) & Mips :: CPURegsRegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Mips Mips Mips Mips Mips::CPU64RegsRegClass Mips::CPURegsRegClass


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> static bool aarch64_expand_sve_widened_duplicate ( rtx dest , scalar_int_mode src_mode , rtx src ) { if ( src_mode != TImode ) { poly_uint64 count = exact_div ( GET_MODE_SIZE ( GET_MODE ( dest ) ) , GET_MODE_SIZE ( src_mode ) ) ; machine_mode dup_mode = mode_for_vector ( src_mode , count ) . require ( ) ; emit_move_insn ( gen_lowpart ( dup_mode , dest ) , gen_const_vec_duplicate ( dup_mode , src ) ) ; return true ; } src = force_const_mem ( src_mode , src ) ; if ( ! src ) return false ; if ( ! aarch64_sve_ld1r_operand_p ( src ) ) { rtx addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; src = replace_equiv_address ( src , addr ) ; } machine_mode mode = GET_MODE ( dest ) ; unsigned int elem_bytes = GET_MODE_UNIT_SIZE ( mode ) ; machine_mode pred_mode = aarch64_sve_pred_mode ( elem_bytes ) . require ( ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; src = gen_rtx_UNSPEC ( mode , gen_rtvec ( 2 , ptrue , src ) , UNSPEC_LD1RQ ) ; emit_insn ( gen_rtx_SET ( dest , src ) ) ; return true ; } </s>

Try to duplicate SRC into SVE register DEST , given that SRC is an integer of mode INT_MODE . Return true on success .


<s> void VEAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerVEMachineInstrToMCInst ( & * I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) <= 32 ) return std :: make_pair ( 0U , & AArch64 :: GPR32RegClass ) ; else if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64RegClass ) ; break ; case 'w' : if ( VT == MVT :: f16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; else if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; else if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; else if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: VPR64RegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; else if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: VPR128RegClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
static
void
rs6000_xcoff_file_end
(
void
)
{
switch_to_section
(
text_section
)
;
fputs
(
"_section_.text:\n"
,
asm_out_file
)
;
switch_to_section
(
data_section
)
;
fputs
(
TARGET_32BIT
"\t.long _section_.text\n"
:
"\t.llong _section_.text\n"
,
asm_out_file
)
;
}
</s>

Output at end of assembler file . On the RS/6000 , referencing data should automatically pull in text .

powerpcspe
"_section_.text:\n"
"\t.long _section_.text\n"
"\t.llong _section_.text\n"


"parameter passing for argument of type "

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


"PPC branch conditions have two components!"

"Cannot insert select on target without ISEL support"

"TrueReg and FalseReg must have overlapping register classes"

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> static void ix86_test_loading_call_insn ( ) { if ( ! TARGET_SSE ) return ; rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( "x86_64/call-insn.rtl" ) ) ; rtx_insn * insn = get_insns ( ) ; ASSERT_EQ ( CALL_INSN , GET_CODE ( insn ) ) ; ASSERT_TRUE ( RTX_FLAG ( insn , jump ) ) ; rtx pat = PATTERN ( insn ) ; ASSERT_EQ ( CALL , GET_CODE ( SET_SRC ( pat ) ) ) ; { ASSERT_EQ ( EXPR_LIST , GET_CODE ( REG_NOTES ( insn ) ) ) ; rtx_expr_list * note0 = as_a < rtx_expr_list * > ( REG_NOTES ( insn ) ) ; ASSERT_EQ ( REG_CALL_DECL , REG_NOTE_KIND ( note0 ) ) ; rtx_expr_list * note1 = note0 -> next ( ) ; ASSERT_EQ ( REG_EH_REGION , REG_NOTE_KIND ( note1 ) ) ; ASSERT_EQ ( NULL , note1 -> next ( ) ) ; } { rtx_expr_list * usage = as_a < rtx_expr_list * > ( CALL_INSN_FUNCTION_USAGE ( insn ) ) ; ASSERT_EQ ( EXPR_LIST , GET_CODE ( usage ) ) ; ASSERT_EQ ( DFmode , GET_MODE ( usage ) ) ; ASSERT_EQ ( USE , GET_CODE ( usage -> element ( ) ) ) ; ASSERT_EQ ( NULL , usage -> next ( ) ) ; } } </s>

Verify that the RTL loader copes with a call_insn dump . This test is target-specific since the dump contains a target-specific hard reg name .


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool split_stack_arg_pointer_used_p ( void ) { if ( cfun -> machine -> split_stack_arg_pointer != NULL_RTX && ( ! REG_P ( cfun -> machine -> split_stack_arg_pointer ) || ( REGNO ( cfun -> machine -> split_stack_arg_pointer ) < FIRST_PSEUDO_REGISTER ) ) ) return true ; rtx_insn * insn ; basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) return false ; df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { rtx x = DF_REF_REG ( use ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return true ; } df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) { rtx x = DF_REF_REG ( def ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return false ; } } return bitmap_bit_p ( DF_LR_OUT ( bb ) , 12 ) ; } </s>

Return whether the split-stack arg pointer ( r12 ) is used .


<s>
void
LC2200DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
XLenVT
=
MVT
::
i32
;
SDLoc
DL
(
Node
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
{
auto
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
VT
==
XLenVT
&&
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
LC2200
::
zero
,
XLenVT
)
;
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
return
;
}
int64_t
Imm
=
ConstNode
->
getSExtValue
(
)
;
if
(
XLenVT
==
MVT
::
i32
)
{
ReplaceNode
(
Node
,
selectImm
(
CurDAG
,
SDLoc
(
Node
)
,
Imm
,
XLenVT
)
)
;
return
;
}
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
XLenVT
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
LC2200
::
ADDI
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>


<s> virtual bool runOnFunction ( Function & Fn ) { GlobalBaseReg = 0 ; return SelectionDAGISel :: runOnFunction ( Fn ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static inline void desc_epilogue ( unw_word t , unw_word ecount , struct unw_state_record * sr ) { sr -> epilogue_start = sr -> region_start + sr -> region_len - 1 - t ; sr -> epilogue_count = ecount + 1 ; } </s>


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ? 2 : 4 ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / ShVal ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 2 4 16 4 0


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) { if ( ! VECTOR_MODE_P ( mode ) ) return cost ; if ( GET_MODE_BITSIZE ( mode ) == 128 && TARGET_SSE_SPLIT_REGS ) return cost * 2 ; if ( GET_MODE_BITSIZE ( mode ) > 128 && TARGET_AVX128_OPTIMAL ) return cost * GET_MODE_BITSIZE ( mode ) / 128 ; return cost ; } </s>

Return cost of vector operation in MODE given that scalar version has COST . If PARALLEL is true assume that CPU has more than one unit performing the operation .


"Can only put epilog before 'retl' instruction!"


<s> enum reg_class crx_regno_reg_class ( int regno ) { if ( regno >= 0 && regno < SP_REGNUM ) return NOSP_REGS ; if ( regno == SP_REGNUM ) return GENERAL_REGS ; if ( regno == LO_REGNUM ) return LO_REGS ; if ( regno == HI_REGNUM ) return HI_REGS ; return NO_REGS ; } </s>

Return the class number of the smallest class containing reg number REGNO . * This could be a conditional expression or could index an array .


<s> const SystemZSubtarget * getSubtargetImpl ( ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool PPCInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , Register & SrcReg , Register & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = PPC :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> bool X86InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .