<s> bool AArch64InstrInfo :: analyzeBranchPredicate ( MachineBasicBlock & MBB , MachineBranchPredicate & MBP , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return true ; if ( I -> getOpcode ( ) == AArch64 :: SpeculationBarrierISBDSBEndBB || I -> getOpcode ( ) == AArch64 :: SpeculationBarrierSBEndBB ) { -- I ; } if ( ! isUnpredicatedTerminator ( * I ) ) return true ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( ! isCondBranchOpcode ( LastOpc ) ) return true ; switch ( LastOpc ) { default : return true ; case AArch64 :: CBZW : case AArch64 :: CBZX : case AArch64 :: CBNZW : case AArch64 :: CBNZX : break ; } ; MBP . TrueDest = LastInst -> getOperand ( 1 ) . getMBB ( ) ; assert ( MBP . TrueDest && "expected!" ) ; MBP . FalseDest = MBB . getNextNode ( ) ; MBP . ConditionDef = nullptr ; MBP . SingleUseCondition = false ; MBP . LHS = LastInst -> getOperand ( 0 ) ; MBP . RHS = MachineOperand :: CreateImm ( 0 ) ; MBP . Predicate = LastOpc == AArch64 :: CBNZX ? MachineBranchPredicate :: PRED_NE : MachineBranchPredicate :: PRED_EQ ; return false ; } </s>

Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible .


<s> unsigned MipsAsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> static bool sh_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( 1 && ( ! TARGET_SHCOMPACT || current_function_args_info . stack_regs == 0 ) && ! sh_cfun_interrupt_handler_p ( ) && ( ! flag_pic || ( decl && ! TREE_PUBLIC ( decl ) ) || ( decl && DECL_VISIBILITY ( decl ) != VISIBILITY_DEFAULT ) ) ) ; } </s>

If PIC , we can not make sibling calls to global functions because the PLT requires r12 to be live .


<s> static rtx_code_label * add_constant ( rtx x , machine_mode mode , rtx last_value ) { int i ; rtx_code_label * lab , * new_rtx ; label_ref_list_t ref , newref ; for ( i = 0 ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , 3 ) != XINT ( pool_vector [ i ] . value , 3 ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new_rtx = 0 ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - 1 ] . value ) ) { new_rtx = gen_label_rtx ( ) ; LABEL_REFS ( new_rtx ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new_rtx ; } if ( lab && pool_window_label ) { newref = ( label_ref_list_t ) pool_alloc ( label_ref_list_pool ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new_rtx ) pool_window_label = new_rtx ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - 1 ] . value ) ) { lab = 0 ; pool_vector [ pool_size - 1 ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == 0 ) ; if ( lab && pool_window_label ) { newref = ( label_ref_list_t ) pool_alloc ( label_ref_list_pool ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size ; pool_size ++ ; return lab ; } </s>

Add a constant to the pool and return its label .


<s> static void push_regs ( HARD_REG_SET * mask , bool interrupt_handler ) { bool skip_fpscr = false ; for ( int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_reg_set_intersect_p ( * mask , reg_class_contents [ DF_REGS ] ) ) { push ( FPSCR_REG ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , ~ * mask ) ; skip_fpscr = true ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = 0 ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + 1 ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = emit_frame_insn ( x ) ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * 4 ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - 32 ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; } else for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) && ! sh_cfun_resbank_handler_p ( ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 LEA Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool PPCInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . getOpcode ( ) == PPC :: MFFS || MI . getOpcode ( ) == PPC :: MTFSF ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static tree fold_build_vec_cmp ( tree_code code , tree type , tree arg0 , tree arg1 ) { tree cmp_type = build_same_sized_truth_vector_type ( type ) ; tree zero_vec = build_zero_cst ( type ) ; tree minus_one_vec = build_minus_one_cst ( type ) ; tree cmp = fold_build2 ( code , cmp_type , arg0 , arg1 ) ; return fold_build3 ( VEC_COND_EXPR , type , cmp , minus_one_vec , zero_vec ) ; } </s>

Helper function to handle the gimple folding of a vector compare operation . This sets up true/false vectors , and uses the VEC_COND_EXPR operation . CODE indicates which comparison is to be made . ( EQ , GT , ... ) . TYPE indicates the type of the result .


<s> unsigned SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( MI . getOpcode ( ) == SystemZ :: PATCHPOINT ) return PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ; else if ( MI . getOpcode ( ) == SystemZ :: STACKMAP ) return MI . getOperand ( 1 ) . getImm ( ) ; else if ( MI . getOpcode ( ) == SystemZ :: FENTRY_CALL ) return 6 ; return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; if ( CPUName == "generic" ) CPUName = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

PowerPC PPC PPC PPC 16 PPC::DIR_NONE PPC "generic" "generic"


<s> bool mmix_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x , bool strict_checking ) { ( ( strict_checking \ && ( REGNO ( X ) <= MMIX_LAST_GENERAL_REGISTER \ || ( reg_renumber [ REGNO ( X ) ] > 0 \ && reg_renumber [ REGNO ( X ) ] <= MMIX_LAST_GENERAL_REGISTER ) ) ) \ || ( ! strict_checking \ && ( REGNO ( X ) <= MMIX_LAST_GENERAL_REGISTER \ || REGNO ( X ) >= FIRST_PSEUDO_REGISTER \ || REGNO ( X ) == ARG_POINTER_REGNUM ) ) ) if ( REG_P ( x ) && MMIX_REG_OK ( x ) ) return 1 ; if ( GET_CODE ( x ) == PLUS ) { rtx x1 = XEXP ( x , 0 ) ; rtx x2 = XEXP ( x , 1 ) ; if ( ! REG_P ( x1 ) ) { rtx tem = x1 ; x1 = x2 ; x2 = tem ; } if ( ! REG_P ( x1 ) || ! MMIX_REG_OK ( x1 ) ) return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; if ( REG_P ( x2 ) && MMIX_REG_OK ( x2 ) ) return 1 ; if ( satisfies_constraint_I ( x2 ) ) return 1 ; return 0 ; } return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; } </s>

Return 1 if the address is OK , otherwise 0 .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; if ( STI . hasMOPS ( ) ) { return EmitMOPS ( AArch64ISD :: MOPS_MEMMOVE , DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memmove .


<s> void SystemZInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static int mips_set_reg_reg_piece_cost ( machine_mode mode , unsigned int units ) { return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) + units - 1 ) / units ) ; } </s>

Return the cost of moving between two registers of mode MODE , assuming that the move will be in pieces of at most UNITS bytes .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static rtx nds32_delegitimize_address ( rtx x ) { x = delegitimize_mem_from_attrs ( x ) ; if ( GET_CODE ( x ) == CONST ) { rtx inner = XEXP ( x , 0 ) ; if ( GET_CODE ( inner ) == PLUS ) inner = XEXP ( inner , 0 ) ; if ( GET_CODE ( inner ) == UNSPEC ) { switch ( XINT ( inner , 1 ) ) { case UNSPEC_GOTINIT : case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLT : case UNSPEC_TLSGD : case UNSPEC_TLSLD : case UNSPEC_TLSIE : case UNSPEC_TLSLE : case UNSPEC_ICT : x = XVECEXP ( inner , 0 , 0 ) ; break ; default : break ; } } } return x ; } </s>

Reorgnize the UNSPEC CONST and return its direct symbol .


<s>
void
ARMConstantIslands
::
verify
(
)
{
for
(
MachineFunction
::
iterator
MBBI
=
MF
->
begin
(
)
,
E
=
MF
->
end
(
)
;
MBBI
!=
E
;
++
MBBI
)
{
MachineBasicBlock
*
MBB
=
MBBI
;
unsigned
MBBId
=
MBB
->
getNumber
(
)
;
assert
(
!
MBBId
||
BBInfo
[
MBBId
1
]
.
postOffset
(
)
<=
BBInfo
[
MBBId
]
.
Offset
)
;
}
DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
1
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> rtx nds32_expand_load_multiple ( int base_regno , int count , rtx base_addr , rtx basemem ) { int par_index ; int offset ; rtx result ; rtx new_addr , mem , reg ; result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; for ( par_index = 0 ; par_index < count ; par_index ++ ) { offset = par_index * 4 ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , 0 , par_index ) = gen_rtx_SET ( VOIDmode , reg , mem ) ; } return result ; } </s>

Functions to expand load_multiple and store_multiple . They are auxiliary extern functions to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> bool constant_address_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case LABEL_REF : case CONST_INT : case HIGH : return true ; case CONST : if ( flag_pic && pic_address_needs_scratch ( x ) ) return false ; return sparc_legitimate_constant_p ( Pmode , x ) ; case SYMBOL_REF : return ! flag_pic && sparc_legitimate_constant_p ( Pmode , x ) ; default : return false ; } } </s>

Determine if a given RTX is a valid constant address .


<s> TargetLowering :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { Type * MemType = LI -> getType ( ) ; bool NoImplicitFloatOps = LI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && Subtarget . hasSSE2 ( ) ) return AtomicExpansionKind :: None ; return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> static unsigned int rs6000_parm_start ( enum machine_mode mode , tree type , unsigned int nwords ) { unsigned int align ; unsigned int parm_offset ; align = function_arg_boundary ( mode , type ) / PARM_BOUNDARY - 1 ; parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6 ; return nwords + ( - ( parm_offset + nwords ) & align ) ; } </s>

For a function parm of MODE and TYPE , return the starting word in the parameter area . NWORDS of the parameter area are already used .


<s> bool enableIndirectBrExpand ( ) const override { return useRetpolineIndirectBranches ( ) ; } </s>

If we are using indirect thunks , we need to expand indirectbr to avoid it lowering to an actual indirect jump .


<s> bool ix86_expand_strlen ( rtx out , rtx src , rtx eoschar , rtx align ) { rtx addr , scratch1 , scratch2 , scratch3 , scratch4 ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! TARGET_INLINE_ALL_STRINGOPS && ! optimize_insn_for_size_p ( ) && ( ! CONST_INT_P ( align ) || INTVAL ( align ) < 4 ) ) return false ; addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; scratch1 = gen_reg_rtx ( Pmode ) ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! optimize_insn_for_size_p ( ) ) { emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; emit_insn ( ix86_gen_sub3 ( out , out , addr ) ) ; } else { rtx unspec ; if ( fixed_regs [ AX_REG ] || fixed_regs [ CX_REG ] || fixed_regs [ DI_REG ] ) return false ; scratch2 = gen_reg_rtx ( Pmode ) ; scratch3 = gen_reg_rtx ( Pmode ) ; scratch4 = force_reg ( Pmode , constm1_rtx ) ; emit_move_insn ( scratch3 , addr ) ; eoschar = force_reg ( QImode , eoschar ) ; src = replace_equiv_address_nv ( src , scratch3 ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , src , eoschar , align , scratch4 ) , UNSPEC_SCAS ) ; emit_insn ( gen_strlenqi_1 ( scratch1 , scratch3 , unspec ) ) ; emit_insn ( ix86_gen_one_cmpl2 ( scratch2 , scratch1 ) ) ; emit_insn ( ix86_gen_add3 ( out , scratch2 , constm1_rtx ) ) ; } return true ; } </s>


<s> static machine_mode pa_c_mode_for_suffix ( char suffix ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { if ( suffix == 'q' ) return TFmode ; } return VOIDmode ; } </s>


<s> static rtx function_arg_vector_value ( int size , int slotno , bool named , int regno ) { const int mult = ( named ? 2 : 1 ) ; unsigned int nwords ; if ( slotno == ( named ? SPARC_FP_ARG_MAX : SPARC_INT_ARG_MAX ) - 1 ) nwords = 1 ; else nwords = CEIL_NWORDS ( size ) ; rtx regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nwords ) ) ; if ( size < UNITS_PER_WORD ) XVECEXP ( regs , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , regno ) , const0_rtx ) ; else for ( unsigned int i = 0 ; i < nwords ; i ++ ) XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno + i * mult ) , GEN_INT ( i * UNITS_PER_WORD ) ) ; return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions for passing and returning BLKmode vectors . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the vector . REGNO is the FP hard register the vector will be passed in .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , usingPBQP ( false ) { initAsmInfo ( ) ; if ( EnablePBQP && Subtarget . isCortexA57 ( ) && OL != CodeGenOpt :: None ) { usingPBQP = true ; RegisterRegAlloc :: setDefault ( createAArch64A57PBQPRegAlloc ) ; } } </s>


<s> bool MicroMipsSizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget -> inMicroMipsMode ( ) || ! Subtarget -> hasMips32r2 ( ) || Subtarget -> hasMips32r6 ( ) ) return false ; MipsII = static_cast < const MipsInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; bool Modified = false ; MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; for ( ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool EnqueueExitsPass :: runOnMachineFunction ( MachineFunction & Func ) { Func . enqueueExitBlock ( ) ; return true ; } </s>


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeCopy ( & MBB ) ; return Changed ; } </s>


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == 0 ) return base_align ; return min ( base_align , offset & - offset ) ; } </s>

Compute the alignment of pointer+OFFSET where the original alignment of pointer was BASE_ALIGN .


<s> bool sh_dynamicalize_shift_p ( rtx count ) { gcc_assert ( CONST_INT_P ( count ) ) ; const int shift_amount_i = std :: abs ( INTVAL ( count ) ) & 31 ; int insn_count ; if ( shift_amount_i == 31 ) insn_count = 2 ; else insn_count = ashl_lshr_seq [ shift_amount_i ] . insn_count ; return TARGET_DYNSHIFT && ( insn_count > 1 + SH_DYNAMIC_SHIFT_COST ) ; } </s>

Return true if it is potentially beneficial to use a dynamic shift instruction ( shad / shar ) instead of a combination of 1/2/8/16 shift instructions for the specified shift count . If dynamic shifts are not available , always return false .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


<s> static void mips_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; if ( ! ISA_HAS_LWL_LWR ) bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; else { if ( MEM_ALIGN ( src ) == BITS_PER_WORD / 2 && MEM_ALIGN ( dest ) == BITS_PER_WORD / 2 ) bits = BITS_PER_WORD / 2 ; else bits = BITS_PER_WORD ; } mode = mode_for_size ( bits , MODE_INT , 0 ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , 0 , 0 ) ) gcc_unreachable ( ) ; } } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , 0 ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s> bool AArch64FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ! ( hasFP ( MF ) && MFI -> hasVarSizedObjects ( ) ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"warning: some functions compiled with BTI and some compiled "

"warning: not setting BTI in feature flags\n"

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> static void mmix_reorg ( void ) { int regno ; for ( regno = MMIX_LAST_STACK_REGISTER_REGNUM ; regno >= 0 ; regno -- ) if ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || ( regno == MMIX_FRAME_POINTER_REGNUM && frame_pointer_needed ) ) break ; if ( ! TARGET_ABI_GNU && regno < crtl -> args . info . regs - 1 ) { regno = crtl -> args . info . regs - 1 ; if ( regno > MMIX_RETURN_VALUE_REGNUM - 1 ) regno = MMIX_RETURN_VALUE_REGNUM - 1 ; } cfun -> machine -> highest_saved_stack_register = regno ; } </s>

Implement TARGET_MACHINE_DEPENDENT_REORG . No actual rearrangements done here ; just virtually by calculating the highest saved stack register number used to modify the register numbers at output time .


<s> TargetPassConfig * F2003fTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new F2003fPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static void note_invalid_constants ( rtx_insn * insn , HOST_WIDE_INT address , int do_pushes ) { int opno ; extract_constrain_insn ( insn ) ; if ( recog_data . n_alternatives == 0 ) return ; preprocess_constraints ( insn ) ; const operand_alternative * op_alt = which_op_alt ( ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] != OP_IN ) continue ; if ( op_alt [ opno ] . memory_ok ) { rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , op ) ; } else if ( MEM_P ( op ) && GET_CODE ( XEXP ( op , 0 ) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( op , 0 ) ) ) { if ( do_pushes ) { rtx cop = avoid_constant_pool_reference ( op ) ; if ( op == cop ) cop = get_pool_constant ( XEXP ( op , 0 ) ) ; push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , cop ) ; } } } } return ; } </s>

Scan INSN and note any of its operands that need fixing . If DO_PUSHES is false we do not actually push any of the fixups needed . The function returns TRUE if any fixups were needed/pushed . This is used by arm_memory_load_p ( ) which needs to know about loads of constants that will be converted into minipool loads .


<s> void Mips16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MipsFunctionInfo * FuncInfo = MF . getInfo < MipsFunctionInfo > ( ) ; const char * Mips16HelperFunction = 0 ; bool NeedMips16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Subtarget -> inMips16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { Mips16IntrinsicHelperType IntrinsicFind = { S -> getSymbol ( ) , "" } ; if ( std :: binary_search ( Mips16IntrinsicHelper , array_endof ( Mips16IntrinsicHelper ) , IntrinsicFind ) ) { const Mips16IntrinsicHelperType * h = ( std :: find ( Mips16IntrinsicHelper , array_endof ( Mips16IntrinsicHelper ) , IntrinsicFind ) ) ; Mips16HelperFunction = h -> Helper ; NeedMips16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { Mips16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) Mips16HelperFunction = getMips16HelperFunction ( CLI . RetTy , CLI . Args , NeedMips16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = Mips :: V0 ; if ( NeedMips16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( Mips16HelperFunction , getPointerTy ( ) ) ; ExternalSymbolSDNode * S = cast < ExternalSymbolSDNode > ( JumpTarget ) ; JumpTarget = getAddrGlobal ( S , JumpTarget . getValueType ( ) , DAG , MipsII :: MO_GOT , Chain , FuncInfo -> callPtrInfo ( S -> getSymbol ( ) ) ) ; } else RegsToPass . push_front ( std :: make_pair ( ( unsigned ) Mips :: T9 , Callee ) ) ; } Ops . push_back ( JumpTarget ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .

Mips Mips Mips Mips Mips 0 Mips Mips Mips Mips "" Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips::V0 Mips Mips MipsII::MO_GOT Mips::T9 Mips


<s> bool aarch64_sve_ptrue_svpattern_p ( rtx x , struct simd_immediate_info * info ) { if ( GET_CODE ( x ) != CONST ) return false ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) != UNSPEC || XINT ( x , 1 ) != UNSPEC_PTRUE ) return false ; if ( info ) { aarch64_svpattern pattern = ( aarch64_svpattern ) INTVAL ( XVECEXP ( x , 0 , 0 ) ) ; machine_mode pred_mode = GET_MODE ( XVECEXP ( x , 0 , 1 ) ) ; scalar_int_mode int_mode = aarch64_sve_element_int_mode ( pred_mode ) ; * info = simd_immediate_info ( int_mode , pattern ) ; } return true ; } </s>

Return true if X is an UNSPEC_PTRUE constant of the form : ( const ( unspec [ PATTERN ZERO ] UNSPEC_PTRUE ) ) where PATTERN is the svpattern as a CONST_INT and where ZERO is a zero constant of the required PTRUE mode ( which can have fewer elements than X 's mode , if zero bits are significant ) . If so , and if INFO is nonnull , describe the immediate in INFO .


<s> static int stackSlotSize ( ) { return 8 ; } </s>


<s> bool ix86_hardreg_mov_ok ( rtx dst , rtx src ) { if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ! REG_P ( src ) && ! MEM_P ( src ) && ! x86_64_immediate_operand ( src , GET_MODE ( dst ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) && ! reload_completed ) return false ; return true ; } </s>

Return true if a set of DST by the expression SRC should be allowed . This prevents complex sets of likely_spilled hard regs before reload .


<s> static int aarch64_simd_clone_usable ( struct cgraph_node * node ) { switch ( node -> simdclone -> vecsize_mangle ) { case 'n' : if ( ! TARGET_SIMD ) return - 1 ; return 0 ; default : gcc_unreachable ( ) ; } } </s>


<s> static void avoid_func_arg_motion ( rtx_insn * first_arg , rtx_insn * insn ) { rtx set ; rtx tmp ; if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PARALLEL && GET_CODE ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 1 ) == UNSPEC_BNDSTX ) { add_dependence ( first_arg , insn , REG_DEP_ANTI ) ; return ; } set = single_set ( insn ) ; if ( ! set ) return ; tmp = SET_DEST ( set ) ; if ( REG_P ( tmp ) ) { add_dependence ( first_arg , insn , REG_DEP_OUTPUT ) ; return ; } add_dependence ( first_arg , insn , REG_DEP_ANTI ) ; } </s>

Add output or anti dependency from insn to first_arg to restrict its code motion .


<s>
unsigned
assignCustomValue
(
const
ARMCallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
override
{
CCValAssign
VA
=
VAs
[
0
]
;
assert
(
VA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
CCValAssign
NextVA
=
VAs
[
1
]
;
assert
(
NextVA
.
needsCustom
(
)
&&
"Value doesn't need custom handling"
)
;
assert
(
NextVA
.
getValVT
(
)
==
MVT
::
f64
&&
"Unsupported type"
)
;
assert
(
VA
.
getValNo
(
)
==
NextVA
.
getValNo
(
)
&&
"Values belong to different arguments"
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
assert
(
NextVA
.
isRegLoc
(
)
&&
"Value should be in reg"
)
;
unsigned
NewRegs
[
]
=
{
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
,
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
32
)
)
}
;
assignValueToReg
(
NewRegs
[
0
]
,
VA
.
getLocReg
(
)
,
VA
)
;
assignValueToReg
(
NewRegs
[
1
]
,
NextVA
.
getLocReg
(
)
,
NextVA
)
;
bool
IsLittle
=
MIRBuilder
.
getMF
(
)
.
getSubtarget
<
ARMSubtarget
>
(
)
.
isLittle
(
)
;
if
(
!
IsLittle
)
std
::
swap
(
NewRegs
[
0
]
,
NewRegs
[
1
]
)
;
MIRBuilder
.
buildSequence
(
Arg
.
Reg
,
NewRegs
,
{
0
,
32
}
)
;
return
1
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> const MINA32MCExpr * MINA32MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) MINA32MCExpr ( Kind , Expr ) ; } </s>


<s>
static
void
rs6000_xcoff_file_start
(
void
)
{
rs6000_gen_section_name
(
&
xcoff_bss_section_name
,
main_input_filename
,
".bss_"
)
;
rs6000_gen_section_name
(
&
xcoff_private_data_section_name
,
main_input_filename
,
".rw_"
)
;
rs6000_gen_section_name
(
&
xcoff_read_only_section_name
,
main_input_filename
,
".ro_"
)
;
fputs
(
"\t.file\t"
,
asm_out_file
)
;
output_quoted_string
(
asm_out_file
,
main_input_filename
)
;
fputc
(
'\n'
,
asm_out_file
)
;
if
(
write_symbols
!=
NO_DEBUG
)
private_data_section
(
)
;
text_section
(
)
;
if
(
profile_flag
)
fprintf
(
asm_out_file
,
"\t.extern %s\n"
,
RS6000_MCOUNT
)
;
rs6000_file_start
(
)
;
}
</s>

Output at beginning of assembler file . Initialize the section names for the RS/6000 at this point . Specify filename , including full path , to assembler . We want to go into the TOC section so at least one .toc will be emitted . Also , in order to output proper .bs/.es pairs , we need at least one static [ RW ] section emitted . Finally , declare mcount when profiling to make the assembler happy .


<s> int mips_idiv_insns ( void ) { int count ; count = 1 ; if ( TARGET_CHECK_ZERO_DIV ) { if ( GENERATE_DIVIDE_TRAPS ) count ++ ; else count += 2 ; } if ( TARGET_FIX_R4000 || TARGET_FIX_R4400 ) count ++ ; return count ; } </s>

Return the number of instructions needed for an integer division .


<s> void split_double_mode ( machine_mode mode , rtx operands [ ] , int num , rtx lo_half [ ] , rtx hi_half [ ] ) { machine_mode half_mode ; unsigned int byte ; rtx mem_op = NULL_RTX ; int mem_num = 0 ; switch ( mode ) { case E_TImode : half_mode = DImode ; break ; case E_DImode : half_mode = SImode ; break ; case E_P2HImode : half_mode = HImode ; break ; case E_P2QImode : half_mode = QImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { if ( mem_op && rtx_equal_p ( op , mem_op ) ) { lo_half [ num ] = lo_half [ mem_num ] ; hi_half [ num ] = hi_half [ mem_num ] ; } else { mem_op = op ; mem_num = num ; lo_half [ num ] = adjust_address ( op , half_mode , 0 ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; } } else { lo_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , 0 ) ; hi_half [ num ] = simplify_gen_subreg ( half_mode , op , GET_MODE ( op ) == VOIDmode ? mode : GET_MODE ( op ) , byte ) ; } } } </s>

Split one or more double-mode RTL references into pairs of half-mode references . The RTL can be REG , offsettable MEM , integer constant , or CONST_DOUBLE . `` operands '' is a pointer to an array of double-mode RTLs to split and `` num '' is its length . lo_half and hi_half are output arrays that parallel `` operands '' .


<s>
bool
AArch64TargetLowering
::
isLegalAddImmediate
(
int64_t
Immed
)
const
{
if
(
Immed
==
std
::
numeric_limits
<
int64_t
>
::
min
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Illegal add imm "
<<
Immed
<<
": avoid UB for INT64_MIN\n"
)
;
return
false
;
}
Immed
=
std
::
abs
(
Immed
)
;
bool
IsLegal
=
(
(
Immed
>>
12
)
==
0
||
(
(
Immed
&
0xfff
)
==
0
&&
Immed
>>
24
==
0
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Is "
<<
Immed
<<
" legal add imm: "
<<
(
IsLegal
"yes"
:
"no"
)
<<
"\n"
)
;
return
IsLegal
;
}
</s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> static bool mips_canonicalize_comparison ( enum rtx_code * code , rtx * cmp1 , enum machine_mode mode ) { HOST_WIDE_INT original , plus_one ; if ( GET_CODE ( * cmp1 ) != CONST_INT ) return false ; original = INTVAL ( * cmp1 ) ; plus_one = trunc_int_for_mode ( ( unsigned HOST_WIDE_INT ) original + 1 , mode ) ; switch ( * code ) { case LE : if ( original < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; case LEU : if ( plus_one != 0 ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; default : return false ; } return false ; } </s>

Canonicalize LE or LEU comparisons into LT comparisons when possible to avoid extra instructions or inverting the comparison .


<s> static void ix86_emit_save_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to save registers using MOV insns . First register is restored from POINTER + OFFSET .


<s>
static
void
ix86_output_indirect_branch_via_reg
(
rtx
call_op
,
bool
sibcall_p
)
{
char
thunk_name_buf
[
32
]
;
char
*
thunk_name
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
int
regno
=
REGNO
(
call_op
)
;
if
(
cfun
->
machine
->
indirect_branch_type
!=
indirect_branch_thunk_inline
)
{
if
(
cfun
->
machine
->
indirect_branch_type
==
indirect_branch_thunk
)
{
int
i
=
regno
;
if
(
i
>=
FIRST_REX_INT_REG
)
i
-=
(
FIRST_REX_INT_REG
LAST_INT_REG
1
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
indirect_thunks_bnd_used
|=
1
<<
i
;
else
indirect_thunks_used
|=
1
<<
i
;
}
indirect_thunk_name
(
thunk_name_buf
,
regno
,
need_prefix
,
false
)
;
thunk_name
=
thunk_name_buf
;
}
else
thunk_name
=
;
if
(
sibcall_p
)
{
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
}
else
{
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd call\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tcall\t%s\n"
,
thunk_name
)
;
return
;
}
char
indirectlabel1
[
32
]
;
char
indirectlabel2
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel1
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel2
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd jmp\t"
,
asm_out_file
)
;
else
fputs
(
"\tjmp\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel2
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel1
)
;
if
(
thunk_name
!=
)
{
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
else
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
else
output_indirect_thunk
(
need_prefix
,
regno
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel2
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd call\t"
,
asm_out_file
)
;
else
fputs
(
"\tcall\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel1
)
;
fputc
(
'\n'
,
asm_out_file
)
;
}
}
</s>

Output indirect branch via a call and return thunk . CALL_OP is a register which contains the branch target . XASM is the assembly template for CALL_OP . Branch is a tail call if SIBCALL_P is true . A normal call is converted to : call __x86_indirect_thunk_reg and a tail call is converted to : jmp __x86_indirect_thunk_reg


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
TM
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
"Unable to encode MachineOperand!"
0


<s> rtx gen_push ( rtx arg ) { struct machine_function * m = cfun -> machine ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) m -> fs . cfa_offset += UNITS_PER_WORD ; m -> fs . sp_offset += UNITS_PER_WORD ; if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( gen_rtx_MEM ( word_mode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , arg ) ; } </s>

Code to generate prologue and epilogue sequences


<s> const uint16_t * OpenRISCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; return ( TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ) ; } </s>


<s> bool MipsAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { OS . write_zeros ( Count ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Atom LEA Fixup"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0x60000000 , Endian ) ; OS . write_zeros ( Count % 4 ) ; return true ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 FP Stackifier"
;
}
</s>


<s> bool ARMFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasMinSize ( ) ) return false ; return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> static void do_and3 ( rtx dest , rtx src1 , rtx src2 ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_anddi3 ( dest , src1 , src2 ) ) ; else emit_insn ( gen_andsi3 ( dest , src1 , src2 ) ) ; } </s>

Emit an and of the proper mode for DEST . DEST is the destination register for the and . SRC1 is the first and input . SRC2 is the second and input . Computes DEST = SRC1 & SRC2 .


<s> bool ARM64TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,15]"

"immediate operand must be in the range [0,239]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void function_builder :: add_unique_function ( const function_instance & instance , tree return_type , vec < tree > & argument_types , uint64_t required_extensions , bool force_direct_overloads ) { char * name = get_name ( instance , false ) ; tree fntype = build_function_type_array ( return_type , argument_types . length ( ) , argument_types . address ( ) ) ; tree attrs = get_attributes ( instance ) ; registered_function & rfn = add_function ( instance , name , fntype , attrs , required_extensions , false , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! * rfn_slot ) ; * rfn_slot = & rfn ; char * overload_name = get_name ( instance , true ) ; if ( strcmp ( name , overload_name ) != 0 ) { tree attrs = get_attributes ( instance ) ; bool placeholder_p = ! ( m_direct_overloads || force_direct_overloads ) ; add_function ( instance , overload_name , fntype , attrs , required_extensions , false , placeholder_p ) ; } obstack_free ( & m_string_obstack , name ) ; } </s>

Add a built-in function for INSTANCE , with the argument types given by ARGUMENT_TYPES and the return type given by RETURN_TYPE . NAME is the `` full '' name for C function . OVERLOAD_NAME is the `` short '' name for C++ overloaded function . OVERLOAD_NAME can be nullptr because some instance does n't have C++ overloaded function .


<s> void LanaiPassConfig :: addPreEmitPass ( ) { addPass ( createLanaiDelaySlotFillerPass ( getLanaiTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void emitAssignment ( MCSymbol * S , const MCExpr * Value ) override { auto * Symbol = cast < MCSymbolELF > ( S ) ; if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const auto & RhsSym = cast < MCSymbolELF > ( static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ) ; unsigned Other = Symbol -> getOther ( ) ; Other &= ~ ELF :: STO_PPC64_LOCAL_MASK ; Other |= RhsSym . getOther ( ) & ELF :: STO_PPC64_LOCAL_MASK ; Symbol -> setOther ( Other ) ; } </s>


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool rx_reg_dead_or_unused_after_insn ( const rtx_insn * i , int regno ) { return find_regno_note ( i , REG_DEAD , regno ) != NULL || find_regno_note ( i , REG_UNUSED , regno ) != NULL ; } </s>

Given an insn and a reg number , tell whether the reg dies or is unused after the insn .


<s> static unsigned int insn_is_swap_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET ) return 0 ; rtx rhs = SET_SRC ( body ) ; if ( GET_CODE ( rhs ) != VEC_SELECT ) return 0 ; rtx parallel = XEXP ( rhs , 1 ) ; if ( GET_CODE ( parallel ) != PARALLEL ) return 0 ; unsigned int len = XVECLEN ( parallel , 0 ) ; if ( len != 2 && len != 4 && len != 8 && len != 16 ) return 0 ; for ( unsigned int i = 0 ; i < len / 2 ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( GET_CODE ( op ) != CONST_INT || INTVAL ( op ) != len / 2 + i ) return 0 ; } for ( unsigned int i = len / 2 ; i < len ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( GET_CODE ( op ) != CONST_INT || INTVAL ( op ) != i - len / 2 ) return 0 ; } return 1 ; } </s>

Return 1 iff INSN swaps doublewords . This may be a reg-reg swap , a permuting load , or a permuting store .


<s> static machine_mode arm_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_NEON ) switch ( mode ) { case SFmode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode ; case SImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode ; case HImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode ; case QImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode ; case DImode : if ( ! TARGET_NEON_VECTORIZE_DOUBLE ) return V2DImode ; break ; default : ; } if ( TARGET_REALLY_IWMMXT ) switch ( mode ) { case SImode : return V2SImode ; case HImode : return V4HImode ; case QImode : return V8QImode ; default : ; } return word_mode ; } </s>

Use the option -mvectorize-with-neon-double to override the use of quardword registers when autovectorizing for Neon , at least until multiple vector widths are supported properly by the middle-end .


<s> tree ix86_veclibabi_acml ( combined_fn fn , tree type_out , tree type_in ) { char name [ 20 ] = "__vr.._" ; tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! TARGET_64BIT || ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_SIN : CASE_CFN_COS : CASE_CFN_EXP : CASE_CFN_LOG : CASE_CFN_LOG2 : CASE_CFN_LOG10 : if ( el_mode == DFmode && n == 2 ) { name [ 4 ] = 'd' ; name [ 5 ] = '2' ; } else if ( el_mode == SFmode && n == 4 ) { name [ 4 ] = 's' ; name [ 5 ] = '4' ; } else return NULL_TREE ; break ; default : return NULL_TREE ; } tree fndecl = mathfn_built_in ( el_mode == DFmode ? double_type_node : float_type_node , fn ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; sprintf ( name + 7 , "%s" , bname + 10 ) ; arity = 0 ; for ( args = DECL_ARGUMENTS ( fndecl ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for an ACML-style interface to a library with vectorized intrinsics .


<s> const char * thumb1_output_casesi ( rtx * operands ) { rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ 0 ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; switch ( GET_MODE ( diff_vec ) ) { case QImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi" ) ; case HImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi" ) ; case SImode : return "bl\t%___gnu_thumb1_case_si" ; default : gcc_unreachable ( ) ; } } </s>

Output a Thumb-1 casesi dispatch sequence .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; } </s>


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) ; Offset += MI . getOperand ( FIOperandNum + 2 ) . getImm ( ) ; if ( MI . getOpcode ( ) == VE :: STQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 3 ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , VE :: sub_even ) ; Register SrcLoReg = getSubReg ( SrcReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: STrii ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( SrcLoReg ) ; replaceFI ( MF , II , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: STrii ) ) ; MI . getOperand ( 3 ) . setReg ( SrcHiReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == VE :: LDQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , VE :: sub_even ) ; Register DestLoReg = getSubReg ( DestReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: LDrii ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) ; replaceFI ( MF , II , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: LDrii ) ) ; MI . getOperand ( 0 ) . setReg ( DestHiReg ) ; Offset += 8 ; } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : return 32 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { APInt KnownZero2 , KnownOne2 ; KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZero , KnownOne , Depth + 1 ) ; DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero2 , KnownOne2 , Depth + 1 ) ; KnownOne &= KnownOne2 ; KnownZero &= KnownZero2 ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & LoongArch :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static bool ix86_rop_should_change_byte_p ( int t ) { return t == 0xc2 || t == 0xc3 || t == 0xca || t == 0xcb ; } </s>

Return true if T is one of the bytes we should avoid with -mmitigate-rop .


"Byval argument's alignment should be a multiple of RegSizeInBytes."

Target-specific cleanup for formal ByVal parameters .


"Unexpected operand in reassociable instruction"

Return true when \P Inst has reassociable operands in the same \P MBB .


<s> int insn_refs_are_delayed ( rtx insn ) { return ( ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) != SEQUENCE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && get_attr_type ( insn ) == TYPE_MILLI ) ) ; } </s>

Return nonzero if references for INSN are delayed . Millicode insns are actually function calls with some special constraints on arguments and register usage . Millicode calls always expect their arguments in the integer argument registers , and always return their result in % r29 ( ret1 ) . They are expected to clobber their arguments , % r1 , % r29 , and the return pointer which is % r31 on 32-bit and % r2 on 64-bit , and nothing else . This function tells reorg that the references to arguments and millicode calls do not appear to happen until after the millicode call . This allows reorg to put insns which set the argument registers into the delay slot of the millicode call -- thus they act more like traditional CALL_INSNs . Note we can not consider side effects of the insn to be delayed because the branch and link insn will clobber the return pointer . If we happened to use the return pointer in the delay slot of the call , then we lose . get_attr_type will try to recognize the given insn , so make sure to filter out things it will not accept -- SEQUENCE , USE and CLOBBER insns in particular .


<s> virtual const Dcpu16RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void ARM64RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII -> get ( ARM64 :: ADDXri ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , 0 , this , MF ) ) ; unsigned Shifter = ARM64_AM :: getShifterImm ( ARM64_AM :: LSL , 0 ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> bool PPCTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Intrn = MF . getFunction ( ) -> hasInternalLinkage ( ) ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


"Flag output operand is of invalid type"


<s> unsigned int arm_dbx_register_number ( unsigned int regno ) { if ( regno < 16 ) return regno ; if ( IS_FPA_REGNUM ( regno ) ) return ( TARGET_AAPCS_BASED ? 96 : 16 ) + regno - FIRST_FPA_REGNUM ; if ( IS_VFP_REGNUM ( regno ) ) return 64 + regno - FIRST_VFP_REGNUM ; if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return 104 + regno - FIRST_IWMMXT_GR_REGNUM ; if ( IS_IWMMXT_REGNUM ( regno ) ) return 112 + regno - FIRST_IWMMXT_REGNUM ; gcc_unreachable ( ) ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s>
void
SystemZInstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Pred
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
unsigned
Opc
;
if
(
SystemZ
::
GRX32BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasLoadStoreOnCond2
(
)
)
Opc
=
SystemZ
::
LOCRMux
;
else
{
Opc
=
SystemZ
::
LOCR
;
MRI
.
constrainRegClass
(
DstReg
,
&
SystemZ
::
GR32BitRegClass
)
;
}
}
else
if
(
SystemZ
::
GR64BitRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
SystemZ
::
LOCGR
;
else
llvm_unreachable
(
"Invalid register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> int aarch64_vec_fpconst_pow_of_2 ( rtx x ) { if ( GET_CODE ( x ) != CONST_VECTOR ) return - 1 ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) != MODE_VECTOR_FLOAT ) return - 1 ; int firstval = aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , 0 ) ) ; if ( firstval <= 0 ) return - 1 ; for ( int i = 1 ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) if ( aarch64_fpconst_pow_of_2 ( CONST_VECTOR_ELT ( x , i ) ) != firstval ) return - 1 ; return firstval ; } </s>

If X is a vector of equal CONST_DOUBLE values and that value is Y , return the aarch64_fpconst_pow_of_2 of Y . Otherwise return -1 .


<s> static bool r10k_uncached_address_p ( unsigned HOST_WIDE_INT address ) { unsigned HOST_WIDE_INT upper ; if ( address + 0x60000000 < 0x20000000 ) return true ; if ( Pmode == DImode ) { upper = ( address >> 40 ) & 0xf9ffff ; if ( upper == 0x900000 || upper == 0xb80000 ) return true ; } return false ; } </s>

Return true if ADDRESS is known to be an uncached address on R10K systems .


<s> bool sh_can_use_simple_return_p ( void ) { HARD_REG_SET live_regs_mask ; int d ; if ( TARGET_SHMEDIA || ( TARGET_SHCOMPACT && ( crtl -> args . info . call_cookie & CALL_COOKIE_RET_TRAMP ( 1 ) ) ) ) return false ; if ( ! reload_completed || frame_pointer_needed ) return false ; if ( optimize_function_for_size_p ( cfun ) ) return false ; d = calc_live_regs ( & live_regs_mask ) ; if ( rounded_frame_size ( d ) > 4 ) return false ; return true ; } </s>

Return true if it is appropriate to emit ` ret ' instructions in the body of a function .


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode ) ; } } </s>

Emit a sequence representing a little-endian VSX load or store , moving data from SOURCE to DEST in mode MODE . This is done separately from rs6000_emit_move to ensure it is called only during expand . LE VSX loads and stores introduced later are handled with a split . The expand-time RTL generation allows us to optimize away redundant pairs of register-permutes .


<s> rtx aarch64_expand_sve_dupq ( rtx target , machine_mode mode , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; gcc_assert ( GET_MODE_INNER ( mode ) == GET_MODE_INNER ( src_mode ) ) ; insn_code icode = ( BYTES_BIG_ENDIAN ? code_for_aarch64_vec_duplicate_vq_be ( mode ) : code_for_aarch64_vec_duplicate_vq_le ( mode ) ) ; unsigned int i = 0 ; expand_operand ops [ 3 ] ; create_output_operand ( & ops [ i ++ ] , target , mode ) ; create_output_operand ( & ops [ i ++ ] , src , src_mode ) ; if ( BYTES_BIG_ENDIAN ) { unsigned int nelts_per_vq = 128 / GET_MODE_UNIT_BITSIZE ( mode ) ; rtx sel = aarch64_gen_stepped_int_parallel ( nelts_per_vq , nelts_per_vq - 1 , - 1 ) ; create_fixed_operand ( & ops [ i ++ ] , sel ) ; } expand_insn ( icode , i , ops ) ; return ops [ 0 ] . value ; } </s>

Duplicate 128-bit Advanced SIMD vector SRC so that it fills an SVE register of mode MODE . Use TARGET for the result if it 's nonnull and convenient . The two vector modes must have the same element mode . The behavior is to duplicate architectural lane N of SRC into architectural lanes N + I * STEP of the result . On big-endian targets , architectural lane 0 of an Advanced SIMD vector is the last element of the vector in memory layout , so for big-endian targets this operation has the effect of reversing SRC before duplicating it . Callers need to account for this .


<s> unsigned int rs6000_data_alignment ( tree type , unsigned int align , enum data_align how ) { if ( how != align_opt ) { if ( TREE_CODE ( type ) == VECTOR_TYPE && align < 128 ) align = 128 ; } if ( how != align_abi ) { if ( TREE_CODE ( type ) == ARRAY_TYPE && TYPE_MODE ( TREE_TYPE ( type ) ) == QImode ) { if ( align < BITS_PER_WORD ) align = BITS_PER_WORD ; } } return align ; } </s>

Return alignment of TYPE . Existing alignment is ALIGN . HOW selects whether the alignment is abi mandated , optional , or both abi and optional alignment .


<s> bool loongarch_can_use_return_insn ( void ) { return reload_completed && cfun -> machine -> frame . total_size == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> bool aarch64_simd_check_vect_par_cnst_half ( rtx op , machine_mode mode , bool high ) { rtx ideal = aarch64_simd_vect_par_cnst_half ( mode , high ) ; HOST_WIDE_INT count_op = XVECLEN ( op , 0 ) ; HOST_WIDE_INT count_ideal = XVECLEN ( ideal , 0 ) ; int i = 0 ; if ( ! VECTOR_MODE_P ( mode ) ) return false ; if ( count_op != count_ideal ) return false ; for ( i = 0 ; i < count_ideal ; i ++ ) { rtx elt_op = XVECEXP ( op , 0 , i ) ; rtx elt_ideal = XVECEXP ( ideal , 0 , i ) ; if ( ! CONST_INT_P ( elt_op ) || INTVAL ( elt_ideal ) != INTVAL ( elt_op ) ) return false ; } return true ; } </s>

Check OP for validity as a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low lanes , from the perspective of the architecture . See the diagram above aarch64_simd_vect_par_cnst_half for more details .


<s> virtual const DCPU16InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> unsigned int rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( field != NULL && field != type ) { type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( type != error_mark_node && TYPE_MODE ( type ) == DFmode ) align = MAX ( align , 64 ) ; } return align ; } </s>

Darwin , AIX increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned .


<s> void vax_notice_update_cc ( rtx exp , rtx insn ATTRIBUTE_UNUSED ) { if ( GET_CODE ( exp ) == SET ) { if ( GET_CODE ( SET_SRC ( exp ) ) == CALL ) CC_STATUS_INIT ; else if ( GET_CODE ( SET_DEST ( exp ) ) != ZERO_EXTRACT && GET_CODE ( SET_DEST ( exp ) ) != PC ) { cc_status . flags = 0 ; switch ( GET_CODE ( SET_SRC ( exp ) ) ) { case NEG : if ( GET_MODE_CLASS ( GET_MODE ( exp ) ) == MODE_FLOAT ) break ; case AND : case IOR : case XOR : case NOT : case MEM : case REG : cc_status . flags = CC_NO_OVERFLOW ; break ; default : break ; } cc_status . value1 = SET_DEST ( exp ) ; cc_status . value2 = SET_SRC ( exp ) ; } } else if ( GET_CODE ( exp ) == PARALLEL && GET_CODE ( XVECEXP ( exp , 0 , 0 ) ) == SET ) { if ( GET_CODE ( SET_SRC ( XVECEXP ( exp , 0 , 0 ) ) ) == CALL ) CC_STATUS_INIT ; else if ( GET_CODE ( SET_DEST ( XVECEXP ( exp , 0 , 0 ) ) ) != PC ) { cc_status . flags = 0 ; cc_status . value1 = SET_DEST ( XVECEXP ( exp , 0 , 0 ) ) ; cc_status . value2 = SET_SRC ( XVECEXP ( exp , 0 , 0 ) ) ; } else CC_STATUS_INIT ; } else CC_STATUS_INIT ; if ( cc_status . value1 && REG_P ( cc_status . value1 ) && cc_status . value2 && reg_overlap_mentioned_p ( cc_status . value1 , cc_status . value2 ) ) cc_status . value2 = 0 ; if ( cc_status . value1 && MEM_P ( cc_status . value1 ) && cc_status . value2 && MEM_P ( cc_status . value2 ) ) cc_status . value2 = 0 ; } </s>


<s> bool n9_2r1w_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_PBSAD : case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : use_rtx = PATTERN ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_STORE : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ Stack Align: May be called with mis-aligned SP.\n"

"\t%@ Non-secure entry function: called from non-secure code.\n"

"\t%@ args = %d, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


Return an array that contains the direct target flag values and their names .


<s> const PPCMCExpr * PPCMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool isDarwin , MCContext & Ctx ) { return new ( Ctx ) PPCMCExpr ( Kind , Expr , isDarwin ) ; } </s>


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( * MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) -> optForSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>


<s>
const
uint16_t
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
bool
HasAVX512
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX512
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
default
:
break
;
}
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> void ix86_split_copysign_const ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = simplify_gen_subreg ( vmode , dest , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is known to be a constant , and so has already been expanded into a vector constant .


<s> int arm_no_early_alu_shift_value_dep ( rtx producer , rtx consumer ) { rtx value = PATTERN ( producer ) ; rtx op = PATTERN ( consumer ) ; rtx early_op ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , 0 , 0 ) ; value = XEXP ( value , 0 ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , 0 , 0 ) ; op = XEXP ( op , 1 ) ; early_op = XEXP ( op , 0 ) ; if ( GET_CODE ( early_op ) != REG ) early_op = XEXP ( early_op , 0 ) ; return ! reg_overlap_mentioned_p ( value , early_op ) ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value dependency on the result of PRODUCER .


<s> bool OR1KAsmParser :: ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { size_t dotLoc = Name . find ( '.' ) ; Operands . push_back ( OR1KOperand :: CreateToken ( Name . substr ( 0 , dotLoc ) , NameLoc ) ) ; if ( dotLoc < Name . size ( ) ) { size_t dotLoc2 = Name . rfind ( '.' ) ; if ( dotLoc == dotLoc2 ) Operands . push_back ( OR1KOperand :: CreateToken ( Name . substr ( dotLoc ) , NameLoc ) ) ; else { Operands . push_back ( OR1KOperand :: CreateToken ( Name . substr ( dotLoc , dotLoc2 - dotLoc ) , NameLoc ) ) ; Operands . push_back ( OR1KOperand :: CreateToken ( Name . substr ( dotLoc2 ) , NameLoc ) ) ; } } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>


<s>
void
handle_arm_sve_h
(
)
{
if
(
function_table
)
{
error
(
"duplicate definition of %qs"
,
"arm_sve.h"
)
;
return
;
}
sve_switcher
sve
;
for
(
unsigned
int
type_i
=
0
;
type_i
<
NUM_VECTOR_TYPES
;
++
type_i
)
{
vector_type_index
type
=
vector_type_index
(
type_i
)
;
register_vector_type
(
type
)
;
if
(
type
!=
VECTOR_TYPE_svbool_t
)
for
(
unsigned
int
count
=
2
;
count
<=
MAX_TUPLE_SIZE
;
++
count
)
register_tuple_type
(
count
,
type
)
;
}
register_svpattern
(
)
;
register_svprfop
(
)
;
function_table
=
new
hash_table
<
registered_function_hasher
>
(
1023
)
;
function_builder
builder
;
for
(
unsigned
int
i
=
0
;
i
<
ARRAY_SIZE
(
function_groups
)
;
++
i
)
builder
.
register_function_group
(
function_groups
[
i
]
)
;
}
</s>

Implement # pragma GCC aarch64 `` arm_sve.h '' .


<s> bool PPCMCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } </s>

Evaluates the fixup as a constant value .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( Subtarget -> isTargetNaCl ( ) || ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> const PPCMCExpr * PPCMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool IsDarwin , MCContext & Ctx ) { return new ( Ctx ) PPCMCExpr ( Kind , Expr , IsDarwin ) ; } </s>


<s> bool PPCInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = PPC :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


"Legal fp imm: materialize 0 using the zero register\n"

Returns true if the target can instruction select the specified FP immediate natively .


<s> rtx loongarch_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNUM ) ; } </s>

Implement RETURN_ADDR_RTX . We do not support moving back to a previous frame .


<s> static int rs6000_use_sched_lookahead ( void ) { switch ( rs6000_cpu_attr ) { case CPU_PPC8540 : case CPU_PPC8548 : return 4 ; case CPU_CELL : return ( reload_completed ? 8 : 0 ) ; default : return 0 ; } } </s>

Return how many instructions to look ahead for better insn scheduling .


<s> rtx rs6000_force_indexed_or_indirect_mem ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; gcc_assert ( MEM_P ( x ) ) ; if ( can_create_pseudo_p ( ) && ! indexed_or_indirect_operand ( x , mode ) ) { rtx addr = XEXP ( x , 0 ) ; if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; op0 = force_reg ( Pmode , op0 ) ; op1 = force_reg ( Pmode , op1 ) ; x = replace_equiv_address ( x , gen_rtx_PLUS ( Pmode , op0 , op1 ) ) ; } else x = replace_equiv_address ( x , force_reg ( Pmode , addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX and LDBRX that only take reg+reg addressing .


<s> static enum unwind_info_type ia64_debug_unwind_info ( void ) { return UI_TARGET ; } </s>


<s> static void rs6000_free_sched_context ( void * _sc ) { gcc_assert ( _sc != NULL ) ; free ( _sc ) ; } </s>


<s> static machine_mode ix86_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { if ( m1 == m2 ) return m1 ; if ( GET_MODE_CLASS ( m1 ) != MODE_CC || GET_MODE_CLASS ( m2 ) != MODE_CC ) return VOIDmode ; if ( ( m1 == CCGCmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCGCmode ) ) return CCGCmode ; if ( ( m1 == CCNOmode && m2 == CCGOCmode ) || ( m1 == CCGOCmode && m2 == CCNOmode ) ) return CCNOmode ; if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode || m2 == CCNOmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode || m1 == CCNOmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case E_CCmode : case E_CCGCmode : case E_CCGOCmode : case E_CCNOmode : case E_CCAmode : case E_CCCmode : case E_CCOmode : case E_CCPmode : case E_CCSmode : case E_CCZmode : switch ( m2 ) { default : return VOIDmode ; case E_CCmode : case E_CCGCmode : case E_CCGOCmode : case E_CCNOmode : case E_CCAmode : case E_CCCmode : case E_CCOmode : case E_CCPmode : case E_CCSmode : case E_CCZmode : return CCmode ; } case E_CCFPmode : return VOIDmode ; } } </s>

If two condition code modes are compatible , return a condition code mode which is compatible with both . Otherwise , return VOIDmode .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool MipsTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { PM . add ( createMipsDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


Return the opcode of the special instruction to be used to load the constant X .


<s> static parse_codes parse_ovld ( void ) { parse_codes result = PC_OK ; diag = & ovld_diag ; if ( ! advance_line ( ovld_file ) ) return PC_OK ; while ( result == PC_OK ) result = parse_ovld_stanza ( ) ; if ( result == PC_EOFILE ) return PC_OK ; return result ; } </s>


<s>
const
char
*
getPassName
(
)
const
{
return
"Dead register definitions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void restore_non_core_regs ( phase1_vrs * vrs ) { if ( ( vrs -> demand_save_flags & DEMAND_SAVE_VFP ) == 0 ) __gnu_Unwind_Restore_VFP ( & vrs -> vfp ) ; } </s>

Restore coprocessor state after phase1 unwinding .


<s> void LanaiFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const LanaiRegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI -> getMaxAlignment ( ) : getStackAlignment ( ) ; unsigned MaxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool AArch64_MC :: isQForm ( const MCInst & MI , const MCInstrInfo * MCII ) { const auto & FPR128 = AArch64MCRegisterClasses [ AArch64 :: FPR128RegClassID ] ; return llvm :: any_of ( MI , [ & ] ( const MCOperand & Op ) { return Op . isReg ( ) && FPR128 . contains ( Op . getReg ( ) ) ; } ) ; } </s>

Returns whether the instruction is in Q form ( 128 bit operands )


<s> unsigned X86InstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI . getOpcode ( ) ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> static int mips_symbol_insns ( enum mips_symbol_type type , machine_mode mode ) { return mips_symbol_insns_1 ( type , mode ) * ( TARGET_MIPS16 ? 2 : 1 ) ; } </s>

Return the number of instructions needed to load a symbol of the given type into a register . If valid in an address , the same number of instructions are needed for loads and stores . Treat extended mips16 instructions as two instructions .


<s> unsigned ARMFastISel :: fastEmitInst_rrr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill , unsigned Op2 , bool Op2IsKill ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; Op2 = constrainOperandRegClass ( II , Op1 , 3 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with three register operands and a result register in the given register class .


<s> static void dump_tree_root_info ( fma_forest * forest , fma_root_node * node ) { node -> dump_info ( forest ) ; } </s>

Wrapper around fma_root_node : :dump_info for use as parameter of function pointer type in func_fma_steering : :dfs .


<s> void ix86_expand_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx set , dst , src ; bool use_sse = false ; bool vector_mode = VECTOR_MODE_P ( mode ) ; machine_mode vmode = mode ; rtvec par ; if ( vector_mode || mode == TFmode ) use_sse = true ; else if ( TARGET_SSE_MATH ) { use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; } dst = operands [ 0 ] ; src = operands [ 1 ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( dst , set ) ; if ( use_sse ) { rtx mask , use , clob ; mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode || mode == TFmode ) par = gen_rtvec ( 2 , set , use ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 3 , set , use , clob ) ; } } else { rtx clob ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 2 , set , clob ) ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } </s>

Generate code for floating point ABS or NEG .


<s> static unsigned int aarch64_function_arg_alignment ( machine_mode mode , const_tree type , unsigned int * abi_break ) { * abi_break = 0 ; if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) ; if ( integer_zerop ( TYPE_SIZE ( type ) ) ) return 0 ; gcc_assert ( TYPE_MODE ( type ) == mode ) ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) ; unsigned int alignment = 0 ; unsigned int bitfield_alignment = 0 ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) { alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ; if ( DECL_BIT_FIELD_TYPE ( field ) ) bitfield_alignment = std :: max ( bitfield_alignment , TYPE_ALIGN ( DECL_BIT_FIELD_TYPE ( field ) ) ) ; } if ( bitfield_alignment > alignment ) { * abi_break = alignment ; return bitfield_alignment ; } return alignment ; } </s>

Given MODE and TYPE of a function argument , return the alignment in bits . The idea is to suppress any stronger alignment requested by the user and opt for the natural alignment ( specified in AAPCS64 \S 4.1 ) . This is a helper function for local use only .


<s> const char * output_branch ( int logic , rtx insn , rtx * operands ) { switch ( get_attr_length ( insn ) ) { case 6 : if ( ! TARGET_RELAX ) { int label = lf ++ ; rtx op0 = operands [ 0 ] ; if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , 0 , 0 ) ) && get_attr_length ( XVECEXP ( final_sequence , 0 , 1 ) ) ) { asm_fprintf ( asm_out_file , "\tb%s%ss\t%LLF%d\n" , logic ? "f" : "t" , ASSEMBLER_DIALECT ? "/" : "." , label ) ; print_slot ( final_sequence ) ; } else asm_fprintf ( asm_out_file , "\tb%s\t%LLF%d\n" , logic ? "f" : "t" , label ) ; output_asm_insn ( "bra\t%l0" , & op0 ) ; fprintf ( asm_out_file , "\tnop\n" ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "LF" , label ) ; return "" ; } case 2 : return logic ? "bt%.\t%l0" : "bf%.\t%l0" ; case 8 : if ( ! TARGET_RELAX ) { int label = lf ++ ; gcc_assert ( ! final_sequence || ! ( INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , 0 , 0 ) ) ) ) ; asm_fprintf ( asm_out_file , "b%s%ss\t%LLF%d\n" , logic ? "f" : "t" , ASSEMBLER_DIALECT ? "/" : "." , label ) ; fprintf ( asm_out_file , "\tnop\n" ) ; output_asm_insn ( "bra\t%l0" , operands ) ; fprintf ( asm_out_file , "\tnop\n" ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "LF" , label ) ; return "" ; } case 4 : { char buffer [ 10 ] ; sprintf ( buffer , "b%s%ss\t%%l0" , logic ? "t" : "f" , ASSEMBLER_DIALECT ? "/" : "." ) ; output_asm_insn ( buffer , & operands [ 0 ] ) ; return "nop" ; } default : gcc_unreachable ( ) ; } } </s>

Output a conditional/unconditional branch to LABEL . COND is the string condition . INSN is the instruction .


<s> unsigned PPCTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return Subtarget . isPPC64 ( ) ? PPC :: X3 : PPC :: R3 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


"\nrs6000_secondary_reload_class, return %s, rclass = %s, "

Debug version of rs6000_secondary_reload_class .


<s> bool AArch64TargetLowering :: shouldExtendGSIndex ( EVT VT , EVT & EltTy ) const { if ( VT . getVectorElementType ( ) == MVT :: i8 || VT . getVectorElementType ( ) == MVT :: i16 ) { EltTy = MVT :: i32 ; return true ; } return false ; } </s>

Returns true if the index type for a masked gather/scatter requires extending .


<s> int sh_contains_memref_p ( rtx insn ) { return for_each_rtx ( & PATTERN ( insn ) , & sh_contains_memref_p_1 , NULL ) ; } </s>

Return nonzero iff INSN contains a MEM .


<s> void ARMConstantPoolValue :: print ( raw_ostream & O ) const { if ( GV ) O << GV -> getName ( ) ; else O << S ; if ( Modifier ) O << "(" << Modifier << ")" ; if ( PCAdjust != 0 ) { O << "-(LPC" << LabelId << "+" << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << "-." ; O << ")" ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool PPCInstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned OpC = MI -> getOpcode ( ) ; switch ( OpC ) { default : return false ; case PPC :: B : case PPC :: BLR : case PPC :: BCTR : case PPC :: BCTR8 : case PPC :: BCTRL : case PPC :: BCTRL8 : return true ; } } </s>

Return true if the specified instruction can be predicated .

PowerPC PPC PPC::B PPC::BLR PPC::BCTR PPC::BCTR8 PPC::BCTRL PPC::BCTRL8


<s> static rtx mips_force_unary ( machine_mode mode , enum rtx_code code , rtx op0 ) { rtx reg ; reg = gen_reg_rtx ( mode ) ; mips_emit_unary ( code , reg , op0 ) ; return reg ; } </s>

Compute ( CODE OP0 ) and store the result in a new register of mode MODE . Return that new register .


"\nrs6000_legitimate_address_p: return = %s, mode = %s, "

Debug version of rs6000_legitimate_address_p .


<s> void ARMAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( EnableMCInst ) { printInstructionThroughMCStreamer ( MI ) ; } else { int Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: CONSTPOOL_ENTRY ) EmitAlignment ( 2 ) ; printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned ARMFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .