<s> static const char * detect_processor_freebsd ( void ) { return "powerpc" ; } </s>


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMMOVE ) ; } </s>

Emit target-specific code that performs a memmove .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createAArch64ELFObjectWriter ( OS , OSABI , IsLittle ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool TOYPassConfig :: addPreRegAlloc ( ) { addPass ( createTOYPreRegAlloc ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


"SSE vector return without SSE enabled "

"MMX vector return without MMX enabled "

When returning SSE vector types , we have a choice of either ( 1 ) being abi incompatible with a -march switch , or ( 2 ) generating an error . Given no good solution , I think the safest thing is one warning . The user wo n't be able to use -Werror , but .... Choose the STRUCT_VALUE_RTX hook because that 's ( at present ) only called in response to actually generating a caller or callee that uses such a type . As opposed to RETURN_IN_MEMORY , which is called via aggregate_value_p for general type probing from tree-ssa .


<s> const FISCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool MipsHazardSchedule :: runOnMachineFunction ( MachineFunction & MF ) { const MipsSubtarget * STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! STI -> hasMips32r6 ( ) || STI -> inMicroMipsMode ( ) ) return false ; bool Changed = false ; const MipsInstrInfo * TII = STI -> getInstrInfo ( ) ; for ( MachineFunction :: iterator FI = MF . begin ( ) ; FI != MF . end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; Iter Inst ; bool LastInstInFunction = std :: next ( I ) == FI -> end ( ) && std :: next ( FI ) == MF . end ( ) ; if ( ! LastInstInFunction ) { std :: pair < Iter , bool > Res = getNextMachineInstr ( std :: next ( I ) , & * FI ) ; LastInstInFunction |= Res . second ; Inst = Res . first ; } if ( LastInstInFunction || ! TII -> SafeInForbiddenSlot ( * Inst ) ) { Changed = true ; MIBundleBuilder ( & * I ) . append ( BuildMI ( MF , I -> getDebugLoc ( ) , TII -> get ( Mips :: NOP ) ) ) ; NumInsertedNops ++ ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips::NOP


<s> virtual unsigned int execute ( function * ) { return frame_header_opt ( ) ; } </s>


<s>
bool
ARMAsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
DW
=
getAnalysisIfAvailable
<
DwarfWriter
>
(
)
;
if
(
Subtarget
->
isThumb
(
)
)
O
<<
"\t.syntax unified\n"
;
if
(
Subtarget
->
isTargetELF
(
)
)
{
std
::
string
CPUString
=
Subtarget
->
getCPUString
(
)
;
if
(
CPUString
!=
"generic"
)
O
<<
"\t.cpu "
<<
CPUString
<<
'\n'
;
if
(
Subtarget
->
hasVFP2
(
)
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
VFP_arch
<<
", 2\n"
;
if
(
!
UnsafeFPMath
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_denormal
<<
", 1\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_exceptions
<<
", 1\n"
;
if
(
FiniteOnlyFPMath
(
)
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_number_model
<<
", 1\n"
;
else
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_number_model
<<
", 3\n"
;
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_align8_needed
<<
", 1\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_align8_preserved
<<
", 1\n"
;
if
(
Subtarget
->
isAAPCS_ABI
(
)
&&
FloatABIType
==
FloatABI
::
Hard
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_HardFP_use
<<
", 3\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_VFP_args
<<
", 1\n"
;
}
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

ARM
ARM
"\t.syntax unified\n"
"generic"
"\t.cpu "
"\t.eabi_attribute "
ARMBuildAttrs::VFP_arch
", 2\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_denormal
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_exceptions
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_number_model
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_number_model
", 3\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_align8_needed
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_align8_preserved
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_HardFP_use
", 3\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_VFP_args
", 1\n"


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( F . hasAvailableExternallyLinkage ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCastsSafe ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ) { unsigned long func_type ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) ) return false ; return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


<s> SDValue SHUXITargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == 128 ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> int mmix_initial_elimination_offset ( int fromreg , int toreg ) { int regno ; int fp_sp_offset = ( get_frame_size ( ) + current_function_outgoing_args_size + 7 ) & ~ 7 ; if ( fromreg == MMIX_ARG_POINTER_REGNUM && toreg == MMIX_FRAME_POINTER_REGNUM ) return 0 ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <= 255 ; regno ++ ) if ( ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) fp_sp_offset += 8 ; return fp_sp_offset + ( MMIX_CFUN_HAS_LANDING_PAD ? 16 : ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? 8 : 0 ) ) + ( fromreg == MMIX_ARG_POINTER_REGNUM ? 0 : 8 ) ; } </s>

The difference between the ( imaginary ) frame pointer and the stack pointer . Used to eliminate the frame pointer .


<s> void xstormy16_initialize_trampoline ( rtx addr , rtx fnaddr , rtx static_chain ) { rtx reg_addr = gen_reg_rtx ( Pmode ) ; rtx temp = gen_reg_rtx ( HImode ) ; rtx reg_fnaddr = gen_reg_rtx ( HImode ) ; rtx reg_addr_mem ; reg_addr_mem = gen_rtx_MEM ( HImode , reg_addr ) ; emit_move_insn ( reg_addr , addr ) ; emit_move_insn ( temp , GEN_INT ( 0x3130 | STATIC_CHAIN_REGNUM ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; emit_move_insn ( temp , static_chain ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; emit_move_insn ( reg_fnaddr , fnaddr ) ; emit_move_insn ( temp , reg_fnaddr ) ; emit_insn ( gen_andhi3 ( temp , temp , GEN_INT ( 0xFF ) ) ) ; emit_insn ( gen_iorhi3 ( temp , temp , GEN_INT ( 0x0200 ) ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; emit_insn ( gen_lshrhi3 ( reg_fnaddr , reg_fnaddr , GEN_INT ( 8 ) ) ) ; emit_move_insn ( reg_addr_mem , reg_fnaddr ) ; } </s>

Initialize the variable parts of a trampoline . ADDR is an RTX for the address of the trampoline ; FNADDR is an RTX for the address of the nested function ; STATIC_CHAIN is an RTX for the static chain value that should be passed to the function when it is called .


"Unexpected operand for inline assembly"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 avoid trailing call pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void MipsInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( Mips :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> bool insn_defines_reg ( unsigned int regno1 , unsigned int regno2 , rtx_insn * insn ) { df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) if ( DF_REF_REG_DEF_P ( def ) && ! DF_REF_IS_ARTIFICIAL ( def ) && ( regno1 == DF_REF_REGNO ( def ) || regno2 == DF_REF_REGNO ( def ) ) ) return true ; return false ; } </s>

Function checks if instruction INSN defines register number REGNO1 or REGNO2 .


<s> bool sh_cannot_change_mode_class ( enum machine_mode from , enum machine_mode to , enum reg_class class ) { if ( to == SFmode && VECTOR_MODE_P ( from ) && GET_MODE_INNER ( from ) == SFmode ) return ( reg_classes_intersect_p ( GENERAL_REGS , class ) ) ; if ( GET_MODE_SIZE ( from ) != GET_MODE_SIZE ( to ) ) { if ( TARGET_LITTLE_ENDIAN ) { if ( GET_MODE_SIZE ( to ) < 8 || GET_MODE_SIZE ( from ) < 8 ) return reg_classes_intersect_p ( DF_REGS , class ) ; } else { if ( GET_MODE_SIZE ( from ) < 8 ) return reg_classes_intersect_p ( DF_HI_REGS , class ) ; } } return 0 ; } </s>

Return the class of registers for which a mode change from FROM to TO is invalid .


<s> int ia64_epilogue_uses ( int regno ) { switch ( regno ) { case R_GR ( 1 ) : return ! ( TARGET_AUTO_PIC || TARGET_NO_PIC ) ; case IN_REG ( 0 ) : case IN_REG ( 1 ) : case IN_REG ( 2 ) : case IN_REG ( 3 ) : case IN_REG ( 4 ) : case IN_REG ( 5 ) : case IN_REG ( 6 ) : case IN_REG ( 7 ) : return lookup_attribute ( "syscall_linkage" , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) != NULL ; case R_BR ( 0 ) : return 1 ; case AR_PFS_REGNUM : return 1 ; default : return 0 ; } } </s>

Return true if REGNO is used by the epilogue .


<s>
StringRef
getPassName
(
)
const
override
{
return
"PPC Lower MASS Entries"
;
}
</s>


"Only optimizing constant comparisons so far"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> static bool mips_expand_msa_shuffle ( struct expand_vec_perm_d * d ) { rtx x , elts [ MAX_VECT_LEN ] ; rtvec v ; rtx_insn * insn ; unsigned i ; if ( ! ISA_HAS_MSA ) return false ; for ( i = 0 ; i < d -> nelt ; i ++ ) elts [ i ] = GEN_INT ( d -> perm [ i ] ) ; v = gen_rtvec_v ( d -> nelt , elts ) ; x = gen_rtx_PARALLEL ( VOIDmode , v ) ; if ( ! mips_const_vector_shuffle_set_p ( x , d -> vmode ) ) return false ; x = gen_rtx_VEC_SELECT ( d -> vmode , d -> op0 , x ) ; x = gen_rtx_SET ( d -> target , x ) ; insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel selector ) ) ) and return true if that 's a valid instruction in the active ISA .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> hasStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86TargetLowering :: isLoadBitCastBeneficial ( EVT LoadVT , EVT BitcastVT , const SelectionDAG & DAG , const MachineMemOperand & MMO ) const { if ( ! Subtarget . hasAVX512 ( ) && ! LoadVT . isVector ( ) && BitcastVT . isVector ( ) && BitcastVT . getVectorElementType ( ) == MVT :: i1 ) return false ; if ( ! Subtarget . hasDQI ( ) && BitcastVT == MVT :: v8i1 && LoadVT == MVT :: i8 ) return false ; if ( LoadVT . isVector ( ) && BitcastVT . isVector ( ) && isTypeLegal ( LoadVT ) && isTypeLegal ( BitcastVT ) ) return true ; return TargetLowering :: isLoadBitCastBeneficial ( LoadVT , BitcastVT , DAG , MMO ) ; } </s>

Return true if the following transform is beneficial : fold ( conv ( load x ) ) - > ( load ( conv * ) x ) On architectures that do n't natively support some vector loads efficiently , casting the load to a smaller vector of larger types and loading is more efficient , however , this can be undone by optimizations in dag combiner .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
char
Letter
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
unsigned
Value
=
CST
->
getZExtValue
(
)
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'J'
:
case
'L'
:
if
(
(
short
)
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'K'
:
if
(
(
Value
>>
16
)
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'N'
:
if
(
(
int
)
Value
>
0
&&
isPowerOf2_32
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
case
'P'
:
if
(
(
short
)
Value
==
(
int
)
Value
)
Result
=
DAG
.
getTargetConstant
(
Value
,
Op
.
getValueType
(
)
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Letter
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> static ARMOperand CreateReg ( unsigned RegNum , bool Writeback ) { ARMOperand Res ; Res . Kind = Register ; Res . Reg . RegNum = RegNum ; Res . Reg . Writeback = Writeback ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void rbt_dump ( struct rbt_strings * t , struct rbt_string_node * subtree ) { if ( subtree != t -> rbt_nil ) { rbt_dump ( t , subtree -> left ) ; fprintf ( stderr , "%s\n" , subtree -> str ) ; rbt_dump ( t , subtree -> right ) ; } } </s>

Inorder dump of the binary search tree .


<s> static int hppa_address_cost ( rtx X , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( X ) ) { case REG : case PLUS : case LO_SUM : return 1 ; case HIGH : return 2 ; default : return 4 ; } } </s>

For the HPPA , REG and REG+CONST is cost 0 and addresses involving symbolic constants are cost 2 . PIC addresses are very expensive . It is no coincidence that this has the same structure as GO_IF_LEGITIMATE_ADDRESS .


"no low registers available for popping high registers"

The bits which are n't usefully expanded as rtl .


<s>
static
void
handle_special_swappables
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
switch
(
insn_entry
[
i
]
.
special_handling
)
{
default
:
gcc_unreachable
(
)
;
case
SH_CONST_VECTOR
:
{
gcc_assert
(
GET_CODE
(
body
)
==
SET
)
;
swap_const_vector_halves
(
&
SET_SRC
(
body
)
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Swapping constant halves in insn %d\n"
,
i
)
;
break
;
}
case
SH_SUBREG
:
adjust_subreg_index
(
body
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Adjusting subreg in insn %d\n"
,
i
)
;
break
;
case
SH_NOSWAP_LD
:
permute_load
(
insn
)
;
break
;
case
SH_NOSWAP_ST
:
permute_store
(
insn
)
;
break
;
case
SH_EXTRACT
:
adjust_extract
(
insn
)
;
break
;
case
SH_SPLAT
:
adjust_splat
(
insn
)
;
break
;
case
SH_XXPERMDI
:
adjust_xxpermdi
(
insn
)
;
break
;
case
SH_CONCAT
:
adjust_concat
(
insn
)
;
break
;
case
SH_VPERM
:
adjust_vperm
(
insn
)
;
break
;
}
}
</s>

The insn described by INSN_ENTRY [ I ] can be swapped , but only with special handling . Take care of that here .

rs6000
"Swapping constant halves in insn %d\n"
"Adjusting subreg in insn %d\n"


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
assert
(
0
&&
"fixupNeedsRelaxation() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

Sparc
0
"fixupNeedsRelaxation() unimplemented"


<s> unsigned MipsFastISel :: fastMaterializeConstant ( const Constant * C ) { if ( ! TargetSupported ) return 0 ; EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? 0 : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return materializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s>
virtual
StringRef
getPassName
(
)
const
{
return
StringRef
(
"CJG Assembly Printer"
)
;
}
</s>

getPassName - Return a nice clean name for a pass .


Returns the description of caches on AIX .


<s>
StackOffset
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
needsStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
if
(
!
IgnoreSPUpdates
&&
!
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
return
getFrameIndexReferenceSP
(
MF
,
FI
,
FrameReg
,
StackSize
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> void scalar_chain :: emit_conversion_insns ( rtx insns , rtx_insn * after ) { if ( ! control_flow_insn_p ( after ) ) { emit_insn_after ( insns , after ) ; return ; } basic_block bb = BLOCK_FOR_INSN ( after ) ; edge e = find_fallthru_edge ( bb -> succs ) ; gcc_assert ( e ) ; basic_block new_bb = split_edge ( e ) ; emit_insn_after ( insns , BB_HEAD ( new_bb ) ) ; } </s>

Insert generated conversion instruction sequence INSNS after instruction AFTER . New BB may be required in case instruction has EH region attached .


<s> int arm_max_const_double_inline_cost ( ) { return ( ( optimize_size || arm_ld_sched ) ? 3 : 4 ) ; } </s>

Return maximum allowed cost of synthesizing a 64-bit constant VAL inline . Returns the number of insns needed , or 99 if we always want to synthesize the value .


<s> static MipsOperand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { MipsOperand * Op = new MipsOperand ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> static void ix86_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned int ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_target_flags_explicit = ptr -> x_ix86_target_flags_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = 1u << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( ix86_tune , false ) ; } </s>


<s> bool ARMTargetLowering :: shouldConvertFpToSat ( unsigned Op , EVT FPVT , EVT VT ) const { if ( ! isOperationLegalOrCustom ( Op , VT ) || ! FPVT . isSimple ( ) ) return false ; switch ( FPVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f16 : return Subtarget -> hasVFP2Base ( ) ; case MVT :: f32 : return Subtarget -> hasVFP2Base ( ) ; case MVT :: f64 : return Subtarget -> hasFP64 ( ) ; case MVT :: v4f32 : case MVT :: v8f16 : return Subtarget -> hasMVEFloatOps ( ) ; default : return false ; } } </s>

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min ( max ( fptoi ) ) saturation patterns .


<s> bool isFPImm ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int Val = ARM_AM :: getFP32Imm ( APInt ( 32 , CE -> getValue ( ) ) ) ; return Val != - 1 ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other , MVT :: Glue ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( 1 ) ; SDValue Glue = End . getValue ( 2 ) ; SmallVector < SDValue , 5 > Ops ; Ops . push_back ( End ) ; Ops . push_back ( DAG . getConstant ( 0 , PtrVT ) ) ; Ops . push_back ( DAG . getConstant ( SystemZ :: CCMASK_SRST , MVT :: i32 ) ) ; Ops . push_back ( DAG . getConstant ( SystemZ :: CCMASK_SRST_FOUND , MVT :: i32 ) ) ; Ops . push_back ( Glue ) ; VTs = DAG . getVTList ( PtrVT , MVT :: Glue ) ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , VTs , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s> void SVEIntrinsicOpts :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool OR1KDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && DataTy -> getVectorNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s> static bool ix86_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && ( mode == V64SFmode || mode == V64SImode ) && MOD4_SSE_REGNO_P ( regno ) ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> static bool mips_lo_sum_offset_lookup ( mips_offset_table * htab , rtx x , enum insert_option option ) { rtx base , offset ; mips_lo_sum_offset * * slot ; struct mips_lo_sum_offset * entry ; split_const ( x , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) base = UNSPEC_ADDRESS ( base ) ; slot = htab -> find_slot_with_hash ( base , mips_hash_base ( base ) , option ) ; if ( slot == NULL ) return false ; entry = ( struct mips_lo_sum_offset * ) * slot ; if ( option == INSERT ) { if ( entry == NULL ) { entry = XNEW ( struct mips_lo_sum_offset ) ; entry -> base = base ; entry -> offset = INTVAL ( offset ) ; * slot = entry ; } else { if ( INTVAL ( offset ) > entry -> offset ) entry -> offset = INTVAL ( offset ) ; } } return INTVAL ( offset ) <= entry -> offset ; } </s>

Look up symbolic constant X in HTAB , which is a hash table of mips_lo_sum_offsets . If OPTION is NO_INSERT , return true if X can be paired with a recorded LO_SUM , otherwise record X in the table .


<s> bool PPCPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; TargetRegisterClass * RC = X86 :: VR256RegisterClass ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( MRI . isPhysRegUsed ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , 0 ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , 0 ) ; while ( 1 ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; bool isWin64 = TM . getSubtarget < X86Subtarget > ( ) . isTargetWin64 ( ) ; unsigned SlotSize = is64Bit ? 8 : 4 ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned FPReg = RI . getFrameRegister ( MF ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned Opc = is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( ! X86 :: VR128RegClass . contains ( Reg ) && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , & RI ) ; } } X86FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool runOnFunction ( Function & F ) override { this -> F = & F ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; bool Changed = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) Changed |= runOnLoop ( * L ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool aarch64_return_address_signing_enabled ( void ) { gcc_assert ( cfun -> machine -> frame . laid_out ) ; return ( aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL || ( aarch64_ra_sign_scope == AARCH64_FUNCTION_NON_LEAF && cfun -> machine -> frame . reg_offset [ LR_REGNUM ] >= 0 ) ) ; } </s>

Return TRUE if return address signing should be enabled for the current function , otherwise return FALSE .


<s> static bool i386_pe_dllimport_p ( tree decl ) { if ( TREE_CODE ( decl ) != VAR_DECL && TREE_CODE ( decl ) != FUNCTION_DECL ) return false ; if ( lookup_attribute ( "dllimport" , DECL_ATTRIBUTES ( decl ) ) ) return true ; if ( associated_type ( decl ) && lookup_attribute ( "dllimport" , TYPE_ATTRIBUTES ( associated_type ( decl ) ) ) ) return i386_pe_type_dllimport_p ( decl ) ; return false ; } </s>

Return non-zero if DECL is a dllimport 'd object .


<s> unsigned Mips16InstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { return 0 ; } </s>

Emit a series of instructions to load an immediate .


<s> void FISCInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( FISC :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned MipsTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) return divideCeil ( VT . getSizeInBits ( ) , Subtarget . isABI_O32 ( ) ? 32 : 64 ) ; return MipsTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool rs6000_discover_homogeneous_aggregate ( machine_mode mode , const_tree type , machine_mode * elt_mode , int * n_elts ) { if ( DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P ( type ) ) { machine_mode field_mode = VOIDmode ; int field_count = rs6000_aggregate_candidate ( type , & field_mode ) ; if ( field_count > 0 ) { int n_regs = ( SCALAR_FLOAT_MODE_P ( field_mode ) ? ( GET_MODE_SIZE ( field_mode ) + 7 ) >> 3 : 1 ) ; if ( field_count * n_regs <= AGGR_ARG_NUM_REG ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) * elt_mode = mode ; if ( n_elts ) * n_elts = 1 ; return false ; } </s>

If an argument , whose type is described by TYPE and MODE , is a homogeneous float or vector aggregate that shall be passed in FP/vector registers according to the ELFv2 ABI , return the homogeneous element mode in * ELT_MODE and the number of elements in * N_ELTS , and return TRUE . Otherwise , set * ELT_MODE to MODE and * N_ELTS to 1 , and return FALSE .


<s> void DLXInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , unsigned SourceRegister , bool IsKill , int FrameIndex , const TargetRegisterClass * RegisterClass , const TargetRegisterInfo * RegisterInfo ) const { } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const X86RegisterInfo * RegInfo = static_cast < const X86RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( CSI [ i ] . getReg ( ) == FPReg ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static bool timode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = pseudo_reg_set ( insn ) ; if ( ! def_set ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_MODE ( dst ) != TImode ) return false ; if ( MEM_P ( dst ) ) { if ( misaligned_operand ( dst , TImode ) && ! TARGET_SSE_UNALIGNED_STORE_OPTIMAL ) return false ; switch ( GET_CODE ( src ) ) { default : return false ; case REG : case CONST_WIDE_INT : return true ; case CONST_INT : return standard_sse_constant_p ( src , TImode ) ; } } else if ( MEM_P ( src ) ) { return ( REG_P ( dst ) && ( ! misaligned_operand ( src , TImode ) || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL ) ) ; } return false ; } </s>

The TImode version of scalar_to_vector_candidate_p .


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> unsigned postKnownBits ( unsigned LogAlign = 0 ) const { return std :: max ( std :: max ( unsigned ( PostAlign ) , LogAlign ) , internalKnownBits ( ) ) ; } </s>

Compute the number of known low bits of postOffset .


<s> unsigned getStackAlignment ( ) const { return StackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = Subtarget ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = Mips :: ADDu ; unsigned ADDiu = Mips :: ADDiu ; if ( isInt < 14 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { const TargetRegisterClass * RC = & Mips :: GPR32RegClass ; unsigned Reg = MBB . getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , get ( Mips :: LOAD_IMM_PSEUDO ) , Reg ) . addImm ( Amount ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> void AArch64_ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SupportDebugThreadLocalLocation = false ; } </s>

This method must be called before any actual lowering is done .


<s> bool Cpu0SEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Cpu0 :: RetLR : expandRetLR ( MBB , MI ) ; break ; case Cpu0 :: CPU0eh_return32 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static void unw_access_gr ( struct _Unwind_Context * info , int regnum , unsigned long * val , char * nat , int write ) { unsigned long * addr , * nat_addr = 0 , nat_mask = 0 , dummy_nat ; struct unw_ireg * ireg ; if ( ( unsigned ) regnum - 1 >= 127 ) abort ( ) ; if ( regnum < 1 ) { nat_addr = addr = & dummy_nat ; dummy_nat = 0 ; } else if ( regnum < 32 ) { ireg = & info -> ireg [ regnum - 2 ] ; addr = ireg -> loc ; if ( addr ) { nat_addr = addr + ireg -> nat . off ; switch ( ireg -> nat . type ) { case UNW_NAT_VAL : if ( write ) { if ( * nat ) { addr [ 0 ] = 0 ; addr [ 1 ] = 0x1fffe ; return ; } addr [ 1 ] = 0x1003e ; } else if ( addr [ 0 ] == 0 && addr [ 1 ] == 0x1ffe ) { * val = 0 ; * nat = 1 ; return ; } case UNW_NAT_NONE : dummy_nat = 0 ; nat_addr = & dummy_nat ; break ; case UNW_NAT_MEMSTK : nat_mask = 1UL << ( ( long ) addr & 0x1f8 ) / 8 ; break ; case UNW_NAT_REGSTK : nat_addr = ia64_rse_rnat_addr ( addr ) ; if ( ( unsigned long ) nat_addr >= info -> regstk_top ) nat_addr = & info -> rnat ; nat_mask = 1UL << ia64_rse_slot_num ( addr ) ; break ; } } } else { addr = ia64_rse_skip_regs ( ( unsigned long * ) info -> bsp , regnum - 32 ) ; nat_addr = ia64_rse_rnat_addr ( addr ) ; if ( ( unsigned long ) nat_addr >= info -> regstk_top ) nat_addr = & info -> rnat ; nat_mask = 1UL << ia64_rse_slot_num ( addr ) ; } if ( write ) { * addr = * val ; if ( * nat ) * nat_addr |= nat_mask ; else * nat_addr &= ~ nat_mask ; } else { * val = * addr ; * nat = ( * nat_addr & nat_mask ) != 0 ; } } </s>


<s> static void rs6000_split_logical_inner ( rtx dest , rtx op1 , rtx op2 , enum rtx_code code , machine_mode mode , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { rtx bool_rtx ; if ( op2 && GET_CODE ( op2 ) == CONST_INT && ( mode == SImode || ( mode == DImode && TARGET_POWERPC64 ) ) && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { HOST_WIDE_INT mask = GET_MODE_MASK ( mode ) ; HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == 0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( VOIDmode , dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == 0 ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( VOIDmode , dest , op1 ) ) ; return ; } } } if ( code == AND && mode == SImode && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { emit_insn ( gen_andsi3 ( dest , op1 , op2 ) ) ; return ; } if ( complement_op1_p ) op1 = gen_rtx_NOT ( mode , op1 ) ; if ( complement_op2_p ) op2 = gen_rtx_NOT ( mode , op2 ) ; if ( ! complement_op1_p && complement_op2_p ) std :: swap ( op1 , op2 ) ; bool_rtx = ( ( code == NOT ) ? gen_rtx_NOT ( mode , op1 ) : gen_rtx_fmt_ee ( code , mode , op1 , op2 ) ) ; if ( complement_final_p ) bool_rtx = gen_rtx_NOT ( mode , bool_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , bool_rtx ) ) ; } </s>

Helper function for rs6000_split_logical to emit a logical instruction after spliting the operation to single GPR registers . DEST is the destination register . OP1 and OP2 are the input source registers . CODE is the base operation ( AND , IOR , XOR , NOT ) . MODE is the machine mode . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


<s> static bool sh_unspec_insn_p ( rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( i , array , x , ALL ) if ( * i != NULL && ( GET_CODE ( * i ) == UNSPEC || GET_CODE ( * i ) == UNSPEC_VOLATILE ) ) return true ; return false ; } </s>

Return true if the specified insn contains any UNSPECs or UNSPEC_VOLATILEs .


<s> static void mips_sim_wait_reg ( struct mips_sim * state , rtx_insn * insn , rtx reg ) { unsigned int regno , end_regno ; end_regno = END_REGNO ( reg ) ; for ( regno = REGNO ( reg ) ; regno < end_regno ; regno ++ ) if ( state -> last_set [ regno ] . insn != 0 ) { unsigned int t ; t = ( state -> last_set [ regno ] . time + insn_latency ( state -> last_set [ regno ] . insn , insn ) ) ; while ( state -> time < t ) mips_sim_next_cycle ( state ) ; } } </s>

Advance simulation state STATE until instruction INSN can read register REG .


<s> static bool abi_v4_pass_in_fpr ( machine_mode mode , bool named ) { if ( ! TARGET_HARD_FLOAT ) return false ; if ( mode == DFmode ) return true ; if ( mode == SFmode && named ) return true ; if ( is_complex_IBM_long_double ( mode ) ) return false ; if ( FLOAT128_2REG_P ( mode ) ) return true ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return true ; return false ; } </s>

Whether ABI_V4 passes MODE args to a function in floating point registers .


<s> bool X86MCInstrAnalysis :: evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const { if ( Inst . getNumOperands ( ) == 0 || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Size + Inst . getOperand ( 0 ) . getImm ( ) ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s> static bool r10k_needs_protection_p ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) return r10k_needs_protection_p_call ( PATTERN ( insn ) ) ; if ( mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE ) { note_stores ( PATTERN ( insn ) , r10k_needs_protection_p_store , & insn ) ; return insn == NULL_RTX ; } return r10k_needs_protection_p_1 ( PATTERN ( insn ) , insn ) ; } </s>

Return true if instruction INSN needs to be protected by an R10K cache barrier .


<s> void ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const char * IA64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case IA64ISD :: GETFD : return "IA64ISD::GETFD" ; case IA64ISD :: BRCALL : return "IA64ISD::BRCALL" ; case IA64ISD :: RET_FLAG : return "IA64ISD::RET_FLAG" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static bool mmix_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { RTX_CODE code = GET_CODE ( x ) ; if ( code == CONST_INT || code == CONST_DOUBLE ) return 1 ; return CONSTANT_ADDRESS_P ( x ) ; } </s>


<s> void MipsMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . hasMips64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < MipsFunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < 16 > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void PPCInstrInfo :: genAlternativeCodeSequence ( MachineInstr & Root , MachineCombinerPattern Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr * > & DelInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg ) const { switch ( Pattern ) { case MachineCombinerPattern :: REASSOC_XY_AMM_BMM : case MachineCombinerPattern :: REASSOC_XMM_AMM_BMM : case MachineCombinerPattern :: REASSOC_XY_BCA : case MachineCombinerPattern :: REASSOC_XY_BAC : reassociateFMA ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; default : TargetInstrInfo :: genAlternativeCodeSequence ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; } } </s>

When getMachineCombinerPatterns ( ) finds potential patterns , this function generates the instructions that could replace the original code sequence .


<s>
static
void
rs6000_xcoff_file_end
(
void
)
{
text_section
(
)
;
fputs
(
"_section_.text:\n"
,
asm_out_file
)
;
data_section
(
)
;
fputs
(
TARGET_32BIT
"\t.long _section_.text\n"
:
"\t.llong _section_.text\n"
,
asm_out_file
)
;
}
</s>

Output at end of assembler file . On the RS/6000 , referencing data should automatically pull in text .


<s> void X86PassConfig :: addPostRegAlloc ( ) { if ( CustomRegAlloc ) addPass ( createX86RegisterAllocator ( ) ) ; addPass ( createX86FloatingPointStackifierPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return nullptr ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> bool x86_extended_reg_mentioned_p ( rtx insn ) { return for_each_rtx ( & PATTERN ( insn ) , extended_reg_mentioned_1 , NULL ) ; } </s>

Return true when INSN mentions register that must be encoded using REX prefix .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
if
(
!
IsVarArg
)
return
CC_AArch64_DarwinPCS
;
return
Subtarget
->
isTargetILP32
(
)
CC_AArch64_DarwinPCS_ILP32_VarArg
:
CC_AArch64_DarwinPCS_VarArg
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
AArch64_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool SparcFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const CSKYRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static const char * detect_caches_intel ( bool xeon_mp , unsigned max_level , unsigned max_ext_level , unsigned * l2sizekb ) { struct cache_desc level1 = { 0 , 0 , 0 } , level2 = { 0 , 0 , 0 } , level3 = { 0 , 0 , 0 } ; if ( max_level >= 4 ) detect_caches_cpuid4 ( & level1 , & level2 , & level3 ) ; else if ( max_level >= 2 ) detect_caches_cpuid2 ( xeon_mp , & level1 , & level2 ) ; else return "" ; if ( level1 . sizekb == 0 ) return "" ; if ( level3 . sizekb ) level2 = level3 ; if ( level2 . sizekb == 0 && max_ext_level >= 0x80000006 ) detect_l2_cache ( & level2 ) ; * l2sizekb = level2 . sizekb ; return describe_cache ( level1 , level2 ) ; } </s>

Returns the description of caches for an Intel processor .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; Register ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt , PPCSubTarget -> hasSPE ( ) ? PPC :: EVLDD : PPC :: LFD ) ) return false ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , false ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , false ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static void CreateReg ( OwningPtr < ARMOperand > & Op , unsigned RegNum , bool Writeback , SMLoc S , SMLoc E ) { Op . reset ( new ARMOperand ) ; Op -> Kind = Register ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Writeback = Writeback ; Op -> StartLoc = S ; Op -> EndLoc = E ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 || ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; if ( UI -> getNumOperands ( ) > 4 ) return false ; if ( UI -> getNumOperands ( ) == 4 && UI -> getOperand ( UI -> getNumOperands ( ) - 1 ) . getValueType ( ) != MVT :: Glue ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . hasEHFunclets ( ) ) return true ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; return false ; } </s>


<s>
void
PPCHazardRecognizer970
::
AdvanceCycle
(
)
{
assert
(
NumIssued
<
5
&&
"Illegal dispatch group!"
)
;
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> static bool ix86_binds_local_p ( const_tree exp ) { bool direct_extern_access = ( ix86_direct_extern_access && ! ( VAR_OR_FUNCTION_DECL_P ( exp ) && lookup_attribute ( "nodirect_extern_access" , DECL_ATTRIBUTES ( exp ) ) ) ) ; if ( ! direct_extern_access ) ix86_has_no_direct_extern_access = true ; return default_binds_local_p_3 ( exp , flag_shlib != 0 , true , direct_extern_access , ( direct_extern_access && ( ! flag_pic || ( TARGET_64BIT && HAVE_LD_PIE_COPYRELOC != 0 ) ) ) ) ; } </s>

For i386 , common symbol is local only for non-PIE binaries . For x86-64 , common symbol is local only for non-PIE binaries or linker supports copy reloc in PIE binaries .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , * Subtarget -> getRegisterInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) -> hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void ARMPassConfig :: addPreEmitPass2 ( ) { addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> inline tree function_instance :: tuple_type ( unsigned int i ) const { unsigned int num_vectors = vectors_per_tuple ( ) ; return acle_vector_types [ num_vectors - 1 ] [ type_suffix ( i ) . vector_type ] ; } </s>

If the function operates on tuples of vectors , return the tuple type associated with type suffix I , otherwise return the vector type associated with type suffix I .


<s> static bool dimode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( ( GET_MODE ( src ) != DImode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFTRT : if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , 1 ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , 1 ) ) , 0 , 63 ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 1 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ! CONST_INT_P ( XEXP ( src , 0 ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 0 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) return false ; return true ; } </s>

The DImode version of scalar_to_vector_candidate_p .


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; bool all_same = true ; rtx x ; int i ; if ( GET_CODE ( vals ) != CONST_VECTOR ) return NULL_RTX ; for ( i = 1 ; i < n_elts ; ++ i ) { x = CONST_VECTOR_ELT ( vals , i ) ; if ( ! rtx_equal_p ( x , CONST_VECTOR_ELT ( vals , 0 ) ) ) all_same = false ; } if ( ! all_same ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , CONST_VECTOR_ELT ( vals , 0 ) ) ; return gen_rtx_VEC_DUPLICATE ( mode , x ) ; } </s>

If VALS is a vector constant that can be loaded into a register using DUP , generate instructions to do so and return an RTX to assign to the register . Otherwise return NULL_RTX .


<s>
char
*
output_e500_flip_gt_bit
(
rtx
dst
,
rtx
src
)
{
static
char
string
[
64
]
;
int
a
,
b
;
gcc_assert
(
GET_CODE
(
dst
)
==
REG
&&
CR_REGNO_P
(
REGNO
(
dst
)
)
&&
GET_CODE
(
src
)
==
REG
&&
CR_REGNO_P
(
REGNO
(
src
)
)
)
;
a
=
4
*
(
REGNO
(
dst
)
CR0_REGNO
)
+
1
;
b
=
4
*
(
REGNO
(
src
)
CR0_REGNO
)
+
1
;
sprintf
(
string
,
"crnot %d,%d"
,
a
,
b
)
;
return
string
;
}
</s>

Return the string to flip the GT bit on a CR .


<s> static _Unwind_Reason_Code unwind_phase2_forced ( _Unwind_Control_Block * ucbp , phase2_vrs * entry_vrs , int resuming ) { _Unwind_Stop_Fn stop_fn = ( _Unwind_Stop_Fn ) UCB_FORCED_STOP_FN ( ucbp ) ; void * stop_arg = ( void * ) UCB_FORCED_STOP_ARG ( ucbp ) ; _Unwind_Reason_Code pr_result = 0 ; phase1_vrs saved_vrs , next_vrs ; saved_vrs . core = entry_vrs -> core ; saved_vrs . demand_save_flags = 0 ; do { _Unwind_State action ; _Unwind_Reason_Code entry_code ; _Unwind_Reason_Code stop_code ; entry_code = get_eit_entry ( ucbp , saved_vrs . core . r [ R_PC ] ) ; if ( resuming ) { action = _US_UNWIND_FRAME_RESUME | _US_FORCE_UNWIND ; resuming = 0 ; } else action = _US_UNWIND_FRAME_STARTING | _US_FORCE_UNWIND ; if ( entry_code == _URC_OK ) { UCB_SAVED_CALLSITE_ADDR ( ucbp ) = saved_vrs . core . r [ R_PC ] ; next_vrs = saved_vrs ; pr_result = ( ( personality_routine ) UCB_PR_ADDR ( ucbp ) ) ( action , ucbp , ( void * ) & next_vrs ) ; saved_vrs . prev_sp = next_vrs . core . r [ R_SP ] ; } else { action |= _US_END_OF_STACK ; saved_vrs . prev_sp = saved_vrs . core . r [ R_SP ] ; } stop_code = stop_fn ( 1 , action , ucbp -> exception_class , ucbp , ( void * ) & saved_vrs , stop_arg ) ; if ( stop_code != _URC_NO_REASON ) return _URC_FAILURE ; if ( entry_code != _URC_OK ) return entry_code ; saved_vrs = next_vrs ; } while ( pr_result == _URC_CONTINUE_UNWIND ) ; if ( pr_result != _URC_INSTALL_CONTEXT ) { return _URC_FAILURE ; } restore_core_regs ( & saved_vrs . core ) ; } </s>


"FramePointer is not implemented on AIX yet."

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
val
=
;
char
buf
[
128
]
;
FILE
*
f
=
;
bool
arch
;
const
struct
vendor_cpu
*
cpu_table
=
;
char
*
fcpu_info
=
;
if
(
argc
<
1
)
goto
not_found
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"cpu"
)
!=
0
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
goto
not_found
;
fcpu_info
=
getenv
(
"GCC_CPUINFO"
)
;
if
(
fcpu_info
)
f
=
fopen
(
fcpu_info
,
"r"
)
;
else
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
not_found
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
{
if
(
strncmp
(
buf
,
"CPU implementer"
,
sizeof
(
"CPU implementer"
)
1
)
==
0
)
{
int
i
;
for
(
i
=
0
;
vendors_table
[
i
]
.
vendor_no
!=
;
i
++
)
if
(
strstr
(
buf
,
vendors_table
[
i
]
.
vendor_no
)
!=
)
{
cpu_table
=
vendors_table
[
i
]
.
vendor_parts
;
break
;
}
}
if
(
strncmp
(
buf
,
"CPU part"
,
sizeof
(
"CPU part"
)
1
)
==
0
)
{
int
i
;
if
(
cpu_table
==
)
goto
not_found
;
for
(
i
=
0
;
cpu_table
[
i
]
.
part_no
!=
;
i
++
)
if
(
strstr
(
buf
,
cpu_table
[
i
]
.
part_no
)
!=
)
{
val
=
arch
cpu_table
[
i
]
.
arch_name
:
cpu_table
[
i
]
.
cpu_name
;
break
;
}
break
;
}
}
if
(
val
)
{
fclose
(
f
)
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
val
,
)
;
}
not_found
:
{
unsigned
int
i
;
unsigned
int
opt
;
const
char
*
search
[
]
=
{
,
"arch"
}
;
if
(
f
)
fclose
(
f
)
;
search
[
0
]
=
argv
[
0
]
;
for
(
opt
=
0
;
opt
<
ARRAY_SIZE
(
search
)
;
opt
++
)
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
configure_default_options
)
;
i
++
)
if
(
strcmp
(
configure_default_options
[
i
]
.
name
,
search
[
opt
]
)
==
0
)
return
concat
(
"-m"
,
search
[
opt
]
,
"="
,
configure_default_options
[
i
]
.
value
,
)
;
return
;
}
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> bool ARMBaseInstrInfo :: hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr & DefMI , unsigned DefIdx ) const { const InstrItineraryData * ItinData = SchedModel . getInstrItineraries ( ) ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return false ; unsigned DDomain = DefMI . getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( DDomain == ARMII :: DomainGeneral ) { unsigned DefClass = DefMI . getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - 1 && DefCycle <= 2 ) ; } return false ; } </s>

Compute operand latency of a def of 'Reg ' .

ARM ARM ARMII::DomainMask ARMII::DomainGeneral 1 2


<s> bool ARMBaseInstrInfo :: isPredicated ( const MachineInstr & MI ) const { if ( MI . isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 && I -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ) return true ; } return false ; } int PIdx = MI . findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI . getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ; } </s>

Returns true if the instruction is already predicated .


<s> bool AArch64TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { return ExtVal . getValueType ( ) . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( ExtVal . getValueType ( ) , Subtarget -> useSVEForFixedLengthVectors ( ) ) ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> bool Mips16FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return isInt < 15 > ( MFI . getMaxCallFrameSize ( ) ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
void
CJGInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
CJG
::
GPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
CJG
::
CPYrr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>

CJG
CJG
CJG::GPRegsRegClass
CJG::CPYrr
"Impossible reg-to-reg copy"


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
const
LegalizerInfo
*
X86Subtarget
::
getLegalizerInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getLegalizerInfo
(
)
;
}
</s>

Expose LegalizerInfo so the clients can re-use .


<s> rtx gen_pop ( rtx arg ) { if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( arg , gen_rtx_MEM ( word_mode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ) ; } </s>

Generate an `` pop '' pattern for input ARG .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I , * this ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( createX86InstructionSelector ( * I , * RBI ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static rtx arm_expand_ternop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; tree arg2 = CALL_EXPR_ARG ( exp , 2 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; rtx op3 = NULL_RTX ; bool builtin_sha1cpm_p = false ; if ( insn_data [ icode ] . n_operands == 5 ) { gcc_assert ( icode == CODE_FOR_crypto_sha1c || icode == CODE_FOR_crypto_sha1p || icode == CODE_FOR_crypto_sha1m ) ; builtin_sha1cpm_p = true ; } machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ 3 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( VECTOR_MODE_P ( mode2 ) ) op2 = safe_vector_operand ( op2 , mode2 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) && ( GET_MODE ( op2 ) == mode2 || GET_MODE ( op2 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ 3 ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; if ( builtin_sha1cpm_p ) op3 = GEN_INT ( TARGET_BIG_END ? 1 : 0 ) ; if ( builtin_sha1cpm_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 , op3 ) ; else pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> static bool arm_promote_prototypes ( const_tree t ATTRIBUTE_UNUSED ) { return ! TARGET_AAPCS_BASED ; } </s>

We ca n't rely on the caller doing the proper promotion when using APCS or ATPCS .


<s> const MipsFrameLowering * MipsFrameLowering :: create ( MipsTargetMachine & TM , const MipsSubtarget & ST ) { if ( TM . getSubtargetImpl ( ) -> inMips16Mode ( ) ) return llvm :: createMips16FrameLowering ( ST ) ; return llvm :: createMipsSEFrameLowering ( ST ) ; } </s>


<s>
const
char
*
pa_singlemove_string
(
rtx
*
operands
)
{
HOST_WIDE_INT
intval
;
if
(
GET_CODE
(
operands
[
0
]
)
==
MEM
)
return
"stw %r1,%0"
;
if
(
GET_CODE
(
operands
[
1
]
)
==
MEM
)
return
"ldw %1,%0"
;
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_DOUBLE
)
{
long
i
;
REAL_VALUE_TYPE
d
;
gcc_assert
(
GET_MODE
(
operands
[
1
]
)
==
SFmode
)
;
REAL_VALUE_FROM_CONST_DOUBLE
(
d
,
operands
[
1
]
)
;
REAL_VALUE_TO_TARGET_SINGLE
(
d
,
i
)
;
operands
[
1
]
=
GEN_INT
(
i
)
;
}
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
{
intval
=
INTVAL
(
operands
[
1
]
)
;
if
(
VAL_14_BITS_P
(
intval
)
)
return
"ldi %1,%0"
;
else
if
(
(
intval
&
0x7ff
)
==
0
)
return
"ldil L'%1,%0"
;
else
if
(
pa_zdepi_cint_p
(
intval
)
)
return
"{zdepi %Z1,%0|depwi,z %Z1,%0}"
;
else
return
"ldil L'%1,%0\n\tldo R'%1(%0),%0"
;
}
return
"copy %1,%0"
;
}
</s>

Return the best assembler insn template for moving operands [ 1 ] into operands [ 0 ] as a fullword .


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo . get ( ) ; } </s>

getRegInfo - Return information about the registers currently in use .


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


Define the ` __builtin_va_list ' type for the ABI .


<s> bool SystemZInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = 0 ; unsigned LowReg = 0 , HighReg = 0 , StartOffset = - 1U , EndOffset = 0 ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! SystemZ :: FP64RegClass . contains ( Reg ) ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += 8 ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64mr : SystemZ :: MOV64mrm ) ) ) ; MIB . addReg ( SystemZ :: R15D ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( SystemZ :: FP64RegClass . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , & SystemZ :: FP64RegClass , & RI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op_true , rtx op_false , rtx cond , rtx cc_op0 , rtx cc_op1 ) { machine_mode dest_mode = GET_MODE ( dest ) ; machine_mode mask_mode = GET_MODE ( cc_op0 ) ; enum rtx_code rcode = GET_CODE ( cond ) ; machine_mode cc_mode = CCmode ; rtx mask ; rtx cond2 ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return 0 ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return 0 ; break ; case GE : case LE : if ( GET_MODE_CLASS ( mask_mode ) == MODE_VECTOR_INT ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; case GTU : case GEU : case LTU : case LEU : cc_mode = CCUNSmode ; if ( rcode == GEU || rcode == LEU ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return 0 ; if ( invert_move ) std :: swap ( op_true , op_false ) ; if ( GET_MODE_CLASS ( dest_mode ) == MODE_VECTOR_INT && ( GET_CODE ( op_true ) == CONST_VECTOR || GET_CODE ( op_false ) == CONST_VECTOR ) ) { rtx constant_0 = CONST0_RTX ( dest_mode ) ; rtx constant_m1 = CONSTM1_RTX ( dest_mode ) ; if ( op_true == constant_m1 && op_false == constant_0 ) { emit_move_insn ( dest , mask ) ; return 1 ; } else if ( op_true == constant_0 && op_false == constant_m1 ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_NOT ( dest_mode , mask ) ) ) ; return 1 ; } if ( op_true == constant_m1 ) op_true = mask ; if ( op_false == constant_0 ) op_false = mask ; } if ( ! REG_P ( op_true ) && ! SUBREG_P ( op_true ) ) op_true = force_reg ( dest_mode , op_true ) ; if ( ! REG_P ( op_false ) && ! SUBREG_P ( op_false ) ) op_false = force_reg ( dest_mode , op_false ) ; cond2 = gen_rtx_fmt_ee ( NE , cc_mode , gen_lowpart ( dest_mode , mask ) , CONST0_RTX ( dest_mode ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( dest_mode , cond2 , op_true , op_false ) ) ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s>
void
ARMConstantPoolValue
::
dump
(
)
const
{
errs
(
)
<<
"  "
<<
*
this
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> void Mips16InstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( Mips :: AddiuSpImmX16 ) ) . addImm ( Amount ) ; else adjustStackPtrBigUnrestricted ( SP , Amount , MBB , I ) ; } </s>


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , MaybeAlign StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : X86GenSubtargetInfo ( TT , CPU , FS ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool Cpu0DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s>
void
PPCMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
uint64_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
unsigned
Size
=
getInstSizeInBytes
(
MI
)
;
support
::
endianness
E
=
IsLittleEndian
support
::
little
:
support
::
big
;
switch
(
Size
)
{
case
0
:
break
;
case
4
:
support
::
endian
::
write
<
uint32_t
>
(
OS
,
Bits
,
E
)
;
break
;
case
8
:
support
::
endian
::
write
<
uint32_t
>
(
OS
,
Bits
>>
32
,
E
)
;
support
::
endian
::
write
<
uint32_t
>
(
OS
,
Bits
,
E
)
;
break
;
default
:
llvm_unreachable
(
"Invalid instruction size"
)
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

PowerPC
PPC
support::endianness
support::little
support::big
0
4
support::endian
8
support::endian
32
support::endian
"Invalid instruction size"


<s> bool DLXInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


"module has aliases, which LLVM does not yet support for AIX"

Set up the AsmPrinter when we are working on a new module .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; STI = & TM . getSubtarget < ARMSubtarget > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>


Return 1 if br.ret can do all the work required to return from a function .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64FrameLowering
*
TFI
=
static_cast
<
const
AArch64FrameLowering
*
>
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> virtual const PPCFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> static int mips16_constant_cost ( int code , HOST_WIDE_INT x ) { switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( IN_RANGE ( x , 1 , 8 ) ) return 0 ; return COSTS_N_INSNS ( 1 ) ; case PLUS : if ( IN_RANGE ( x , - 128 , 127 ) ) return 0 ; if ( SMALL_OPERAND ( x ) ) return COSTS_N_INSNS ( 1 ) ; return - 1 ; case LEU : if ( x == - 1 ) return - 1 ; case LE : x += 1 ; case XOR : case LT : case LTU : if ( IN_RANGE ( x , 0 , 255 ) ) return 0 ; if ( SMALL_OPERAND_UNSIGNED ( x ) ) return COSTS_N_INSNS ( 1 ) ; return - 1 ; case EQ : case NE : if ( x == 0 ) return 0 ; return - 1 ; default : return - 1 ; } } </s>

Return the cost of X when used as an operand to the MIPS16 instruction that implements CODE . Return -1 if there is no such instruction , or if X is not a valid immediate operand for it .


<s>
static
int
rs6000_arg_partial_bytes
(
cumulative_args_t
cum_v
,
machine_mode
mode
,
tree
type
,
bool
named
)
{
CUMULATIVE_ARGS
*
cum
=
get_cumulative_args
(
cum_v
)
;
bool
passed_in_gprs
=
true
;
int
ret
=
0
;
int
align_words
;
machine_mode
elt_mode
;
int
n_elts
;
rs6000_discover_homogeneous_aggregate
(
mode
,
type
,
&
elt_mode
,
&
n_elts
)
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
elt_mode
,
named
)
)
{
if
(
TARGET_64BIT
&&
!
cum
->
prototype
&&
(
!
cum
->
libcall
||
!
FLOAT128_VECTOR_P
(
elt_mode
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
vregno
+
n_elts
>
ALTIVEC_ARG_MAX_REG
+
1
)
ret
=
(
ALTIVEC_ARG_MAX_REG
+
1
cum
->
vregno
)
*
16
;
}
if
(
TARGET_MACHO
&&
rs6000_darwin64_struct_check_p
(
mode
,
type
)
)
return
0
;
align_words
=
rs6000_parm_start
(
mode
,
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
elt_mode
)
)
{
unsigned
long
n_fpreg
=
(
GET_MODE_SIZE
(
elt_mode
)
+
7
)
>>
3
;
if
(
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
fregno
+
n_elts
*
n_fpreg
>
FP_ARG_MAX_REG
+
1
)
{
int
fpr
=
(
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
MIN
(
8
,
GET_MODE_SIZE
(
elt_mode
)
)
)
;
int
fpr_words
=
fpr
/
(
TARGET_32BIT
4
:
8
)
;
if
(
align_words
+
fpr_words
<
GP_ARG_NUM_REG
)
passed_in_gprs
=
true
;
else
ret
=
fpr
;
}
}
if
(
passed_in_gprs
&&
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
mode
,
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


<s> void ix86_expand_copysign ( rtx operands [ ] ) { enum machine_mode mode , vmode ; rtx dest , op0 , op1 , mask , nmask ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; vmode = mode == SFmode ? V4SFmode : V2DFmode ; if ( GET_CODE ( op0 ) == CONST_DOUBLE ) { rtvec v ; if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op0 ) ) ) op0 = simplify_unary_operation ( ABS , mode , op0 , mode ) ; if ( op0 == CONST0_RTX ( mode ) ) op0 = CONST0_RTX ( vmode ) ; else { if ( mode == SFmode ) v = gen_rtvec ( 4 , op0 , CONST0_RTX ( SFmode ) , CONST0_RTX ( SFmode ) , CONST0_RTX ( SFmode ) ) ; else v = gen_rtvec ( 2 , op0 , CONST0_RTX ( DFmode ) ) ; op0 = force_reg ( vmode , gen_rtx_CONST_VECTOR ( vmode , v ) ) ; } mask = ix86_build_signbit_mask ( mode , 0 , 0 ) ; if ( mode == SFmode ) emit_insn ( gen_copysignsf3_const ( dest , op0 , op1 , mask ) ) ; else emit_insn ( gen_copysigndf3_const ( dest , op0 , op1 , mask ) ) ; } else { nmask = ix86_build_signbit_mask ( mode , 0 , 1 ) ; mask = ix86_build_signbit_mask ( mode , 0 , 0 ) ; if ( mode == SFmode ) emit_insn ( gen_copysignsf3_var ( dest , NULL , op0 , op1 , nmask , mask ) ) ; else emit_insn ( gen_copysigndf3_var ( dest , NULL , op0 , op1 , nmask , mask ) ) ; } } </s>

Expand a copysign operation . Special case operand 0 being a constant .


<s> unsigned ARMTargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) const { return ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / 128 ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .