<s> static bool x86_can_output_mi_thunk ( tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta ATTRIBUTE_UNUSED , HOST_WIDE_INT vcall_offset , tree function ) { if ( TARGET_64BIT ) return true ; if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < 3 ) return true ; if ( vcall_offset ) return false ; if ( flag_pic && ! ( * targetm . binds_local_p ) ( function ) ) return false ; return true ; } </s>

Determine whether x86_output_mi_thunk can succeed .


<s> void ix86_expand_lround ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op1 ) ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx adj ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; adj = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ; ix86_sse_copysign_to_positive ( adj , adj , force_reg ( mode , op1 ) , NULL_RTX ) ; adj = expand_simple_binop ( mode , PLUS , adj , op1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; expand_fix ( op0 , adj , 0 ) ; } </s>

Expand SSE sequence for computing lround from OP1 storing into OP0 .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool mips_emit_scc ( enum rtx_code code , rtx target ) { if ( GET_MODE_CLASS ( GET_MODE ( cmp_operands [ 0 ] ) ) != MODE_INT ) return false ; target = gen_lowpart ( GET_MODE ( cmp_operands [ 0 ] ) , target ) ; if ( code == EQ || code == NE ) { rtx zie = mips_zero_if_equal ( cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; mips_emit_binary ( code , target , zie , const0_rtx ) ; } else mips_emit_int_relational ( code , 0 , target , cmp_operands [ 0 ] , cmp_operands [ 1 ] ) ; return true ; } </s>

Try comparing cmp_operands [ 0 ] and cmp_operands [ 1 ] using rtl code CODE . Store the result in TARGET and return true if successful . On 64-bit targets , TARGET may be wider than cmp_operands [ 0 ] .


<s> int ia32_multipass_dfa_lookahead ( void ) { if ( reload_completed ) return ix86_issue_rate ( ) ; return 0 ; } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler .


<s> static bool aarch64_scalar_mode_supported_p ( machine_mode mode ) { return ( mode == HFmode ? true : default_scalar_mode_supported_p ( mode ) ) ; } </s>

Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE if MODE is HFmode , and punt to the generic implementation otherwise .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute TuneAttr = F . getFnAttribute ( "tune-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) : ( StringRef ) CPU ; StringRef FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; unsigned PreferVectorWidthOverride = 0 ; Attribute PreferVecWidthAttr = F . getFnAttribute ( "prefer-vector-width" ) ; if ( PreferVecWidthAttr . isValid ( ) ) { StringRef Val = PreferVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += 'p' ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; Attribute MinLegalVecWidthAttr = F . getFnAttribute ( "min-legal-vector-width" ) ; if ( MinLegalVecWidthAttr . isValid ( ) ) { StringRef Val = MinLegalVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += 'm' ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; Key += TuneCPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : "+soft-float," ; Key += FS ; FS = Key . substr ( FSStart ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , TuneCPU , FS , * this , MaybeAlign ( F . getParent ( ) -> getOverrideStackAlignment ( ) ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool mips_expand_ext_as_unaligned_load ( rtx dest , rtx src , HOST_WIDE_INT width , HOST_WIDE_INT bitpos , bool unsigned_p ) { rtx left , right , temp ; rtx dest1 = NULL_RTX ; if ( GET_MODE ( dest ) == DImode && ( REG_P ( dest ) || ( SUBREG_P ( dest ) && ! MEM_P ( SUBREG_REG ( dest ) ) ) ) && GET_MODE_BITSIZE ( SImode ) == width ) { dest1 = dest ; dest = gen_reg_rtx ( SImode ) ; } if ( ! mips_get_unaligned_mem ( src , width , bitpos , & left , & right ) ) return false ; temp = gen_reg_rtx ( GET_MODE ( dest ) ) ; if ( GET_MODE ( dest ) == DImode ) { emit_insn ( gen_mov_ldl ( temp , src , left ) ) ; emit_insn ( gen_mov_ldr ( dest , copy_rtx ( src ) , right , temp ) ) ; } else { emit_insn ( gen_mov_lwl ( temp , src , left ) ) ; emit_insn ( gen_mov_lwr ( dest , copy_rtx ( src ) , right , temp ) ) ; } if ( dest1 ) { if ( unsigned_p ) emit_insn ( gen_zero_extendsidi2 ( dest1 , dest ) ) ; else emit_insn ( gen_extendsidi2 ( dest1 , dest ) ) ; } return true ; } </s>

Try to use left/right loads to expand an `` extv '' or `` extzv '' pattern . DEST , SRC , WIDTH and BITPOS are the operands passed to the expander ; the operation is the equivalent of : ( set DEST ( * _extract SRC WIDTH BITPOS ) ) Return true on success .


<s> PPCTargetLowering :: ConstraintType PPCTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == "wc" ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool enablePostRAScheduler ( ) const override { return UsePostRAScheduler ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> FastISel * X86TargetLowering :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmo , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , 8 > & cil ) { return X86 :: createFastISel ( mf , mmo , dw , vm , bm , am , cil ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static MachineInstr * getDef ( unsigned Reg , const MachineRegisterInfo * MRI ) { if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return 0 ; return MRI -> getUniqueVRegDef ( Reg ) ; } </s>

Get the concrete record with the specified name .


<s> const VERegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> MachineBasicBlock * MandarinTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MDCC :: CondCodes CC = ( MDCC :: CondCodes ) MI -> getOperand ( 3 ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( MD :: JCCi ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( MD :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( ) ; return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
0
)
)
;
return
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool AArch64TargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! I -> getType ( ) -> isVectorTy ( ) ) return false ; if ( IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: aarch64_neon_umull : if ( ! areExtractShuffleVectors ( II -> getOperand ( 0 ) , II -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & II -> getOperandUse ( 0 ) ) ; Ops . push_back ( & II -> getOperandUse ( 1 ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( 0 ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( 1 ) ) ; if ( areExtractShuffleVectors ( Ext1 , Ext2 ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( 0 ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( 0 ) ) ; } Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } return false ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { if ( Subtarget . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .

PowerPC PPC PPC PPC::G8RCRegClass PPC::GPRCRegClass


<s>
const
char
*
output_jump_label_table
(
void
)
{
if
(
pool_size
)
{
fprintf
(
asm_out_file
,
"\t.align 2\n"
)
;
for
(
int
i
=
0
;
i
<
pool_size
;
i
++
)
{
pool_node
*
p
=
&
pool_vector
[
i
]
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
p
->
label
)
)
;
output_asm_insn
(
".long	%O0"
,
&
p
->
value
)
;
}
pool_size
=
0
;
}
return
""
;
}
</s>

Dump out any constants accumulated in the final pass . These will only be labels .


<s> bool hasMFence ( ) const { return hasSSE2 ( ) || is64Bit ( ) ; } </s>

Use mfence if we have SSE2 or we 're on x86-64 ( even if we asked for no-sse2 ) .


<s> static bool align_ok_ldrd_strd ( HOST_WIDE_INT align , HOST_WIDE_INT offset ) { return ( unaligned_access ? ( align >= BITS_PER_WORD && ( offset & 3 ) == 0 ) : ( align >= 2 * BITS_PER_WORD && ( offset & 7 ) == 0 ) ) ; } </s>

Return true if a 64-bit access with alignment ALIGN and with a constant offset OFFSET from the base pointer is permitted on this architecture .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
bool
tDest
=
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
;
bool
tSrc
=
ARM
::
tGPRRegClass
.
contains
(
SrcReg
)
;
unsigned
Opc
=
ARM
::
tMOVgpr2gpr
;
if
(
tDest
&&
tSrc
)
Opc
=
ARM
::
tMOVr
;
else
if
(
tSrc
)
Opc
=
ARM
::
tMOVtgpr2gpr
;
else
if
(
tDest
)
Opc
=
ARM
::
tMOVgpr2tgpr
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
}
</s>

ARM
ARM::tGPRRegClass
ARM::tGPRRegClass
ARM::tMOVgpr2gpr
ARM::tMOVr
ARM::tMOVtgpr2gpr
ARM::tMOVgpr2tgpr
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"


<s> void ARMAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { const bool WasThumb = isThumb ( StartInfo ) ; if ( EndInfo == NULL || WasThumb != isThumb ( * EndInfo ) ) { OutStreamer . EmitAssemblerFlag ( WasThumb ? MCAF_Code16 : MCAF_Code32 ) ; } } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s>
bool
PPCCTRLoopsVerify
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
for
(
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
,
IE
=
MF
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineBasicBlock
*
MBB
=
&
*
I
;
if
(
!
MDT
->
isReachableFromEntry
(
MBB
)
)
continue
;
for
(
MachineBasicBlock
::
iterator
MII
=
MBB
->
getFirstTerminator
(
)
,
MIIE
=
MBB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
unsigned
Opc
=
MII
->
getOpcode
(
)
;
if
(
Opc
==
PPC
::
BDNZ8
||
Opc
==
PPC
::
BDNZ
||
Opc
==
PPC
::
BDZ8
||
Opc
==
PPC
::
BDZ
)
if
(
!
verifyCTRBranch
(
MBB
,
MII
)
)
llvm_unreachable
(
"Invalid PPC CTR loop!"
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

PowerPC
PPC
PPC::BDNZ8
PPC::BDNZ
PPC::BDZ8
PPC::BDZ
"Invalid PPC CTR loop!"


<s>
void
ARM64InstrInfo
::
suppressLdStPair
(
MachineInstr
*
MI
)
const
{
if
(
MI
->
memoperands_empty
(
)
)
return
;
assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
&&
"Too many target MO flags"
)
;
(
*
MI
->
memoperands_begin
(
)
)
->
setFlags
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
;
}
</s>

Hint that pairing the given load or store is unprofitable .


<s> static void xstormy16_asm_out_destructor ( rtx symbol , int priority ) { const char * section = ".dtors" ; char buf [ 16 ] ; if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , ".dtors.%.5u" , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , 0 , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , POINTER_SIZE , 1 ) ; } </s>

Output constructors and destructors . Just like default_named_section_asm_out_ * but do n't set the sections writable .


"Chain: broken invariant. A Chain can only be killed after its last "


<s> void rs6000_emit_le_vsx_load ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_mem , permute_reg ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , 0 ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; permute_mem = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_reg = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , permute_mem ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , permute_reg ) ) ; } </s>

Emit a little-endian load from vector memory location SOURCE to VSX register DEST in mode MODE . The load is done with two permuting insn 's that represent an lxvd2x and xxpermdi .


<s>
bool
ARMAsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
assert
(
MMI
)
;
DW
=
getAnalysisIfAvailable
<
DwarfWriter
>
(
)
;
assert
(
DW
&&
"Dwarf Writer is not available"
)
;
DW
->
BeginModule
(
&
M
,
MMI
,
O
,
this
,
TAI
)
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
Mang
->
setUseQuotes
(
true
)
;
if
(
Subtarget
->
isTargetELF
(
)
)
{
std
::
string
CPUString
=
Subtarget
->
getCPUString
(
)
;
if
(
CPUString
!=
"generic"
)
O
<<
"\t.cpu "
<<
CPUString
<<
'\n'
;
if
(
Subtarget
->
hasVFP2
(
)
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
VFP_arch
<<
", 2\n"
;
if
(
!
UnsafeFPMath
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_denormal
<<
", 1\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_exceptions
<<
", 1\n"
;
if
(
FiniteOnlyFPMath
(
)
)
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_number_model
<<
", 1\n"
;
else
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_FP_number_model
<<
", 3\n"
;
O
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_align8_needed
<<
", 1\n"
<<
"\t.eabi_attribute "
<<
ARMBuildAttrs
::
ABI_align8_preserved
<<
", 1\n"
;
}
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

ARM
ARM
"Dwarf Writer is not available"
"generic"
"\t.cpu "
"\t.eabi_attribute "
ARMBuildAttrs::VFP_arch
", 2\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_denormal
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_exceptions
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_number_model
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_FP_number_model
", 3\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_align8_needed
", 1\n"
"\t.eabi_attribute "
ARMBuildAttrs::ABI_align8_preserved
", 1\n"


<s> static void predict_jump ( int prob ) { rtx insn = get_last_insn ( ) ; gcc_assert ( JUMP_P ( insn ) ) ; add_int_reg_note ( insn , REG_BR_PROB , prob ) ; } </s>

Predict just emitted jump instruction to be taken with probability PROB .


<s>
StringRef
getPassName
(
)
const
override
{
return
"StackPU2 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : case ARM :: GPRPairRegClassID : return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM::GPRRegClassID ARM::SPRRegClassID ARM::DPRRegClassID ARM::QPRRegClassID ARM::QQPRRegClassID ARM::QQQQPRRegClassID ARM::GPRPairRegClassID


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( VT . isScalableVector ( ) || Subtarget -> useSVEForFixedLengthVectors ( ) ) return SDValue ( N , 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CSel . getNode ( ) ) ; SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; Created . push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> static rtx x86_this_parameter ( tree function ) { tree type = TREE_TYPE ( function ) ; bool aggr = aggregate_value_p ( TREE_TYPE ( type ) , type ) != 0 ; int nregs ; if ( TARGET_64BIT ) { const int * parm_regs ; if ( ix86_function_type_abi ( type ) == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; return gen_rtx_REG ( Pmode , parm_regs [ aggr ] ) ; } nregs = ix86_function_regparm ( type , function ) ; if ( nregs > 0 && ! stdarg_p ( type ) ) { int regno ; unsigned int ccvt = ix86_get_callcvt ( type ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) regno = aggr ? DX_REG : CX_REG ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { regno = CX_REG ; if ( aggr ) return gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 ) ) ; } else { regno = AX_REG ; if ( aggr ) { regno = DX_REG ; if ( nregs == 1 ) return gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 ) ) ; } } return gen_rtx_REG ( SImode , regno ) ; } return gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , aggr ? 8 : 4 ) ) ; } </s>

Returns an expression indicating where the this parameter is located on entry to the FUNCTION .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { AArch64MachineFunctionInfo * MFI = MF . getInfo < AArch64MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> bool MipsAsmParser :: processInstruction ( MCInst & Inst , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { const MCInstrDesc & MCID = getInstDesc ( Inst . getOpcode ( ) ) ; Inst . setLoc ( IDLoc ) ; if ( MCID . hasDelaySlot ( ) && Options . isReorder ( ) ) { Instructions . push_back ( Inst ) ; MCInst NopInst ; NopInst . setOpcode ( Mips :: SLL ) ; NopInst . addOperand ( MCOperand :: CreateReg ( Mips :: ZERO ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( Mips :: ZERO ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; Instructions . push_back ( NopInst ) ; return false ; } if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) { for ( unsigned i = 0 ; i < MCID . getNumOperands ( ) ; i ++ ) { const MCOperandInfo & OpInfo = MCID . OpInfo [ i ] ; if ( ( OpInfo . OperandType == MCOI :: OPERAND_MEMORY ) || ( OpInfo . OperandType == MCOI :: OPERAND_UNKNOWN ) ) { MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isImm ( ) ) { int MemOffset = Op . getImm ( ) ; if ( MemOffset < - 32768 || MemOffset > 32767 ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , true ) ; return false ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Expr = Op . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * SR = static_cast < const MCSymbolRefExpr * > ( Expr ) ; if ( SR -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } else if ( ! isEvaluated ( Expr ) ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } } } } if ( needsExpansion ( Inst ) ) expandInstruction ( Inst , IDLoc , Instructions ) ; else Instructions . push_back ( Inst ) ; return false ; } </s>

Process a single instruction and collect debug info anchors .


<s> static int power10_sched_reorder ( rtx_insn * * ready , int lastpos ) { rtx mem1 ; if ( ! reload_completed ) return cached_can_issue_more ; if ( load_store_pendulum != 0 ) { load_store_pendulum = 0 ; return cached_can_issue_more ; } if ( TARGET_P10_FUSION && is_fusable_store ( last_scheduled_insn , & mem1 ) ) { int pos = lastpos ; while ( pos >= 0 ) { rtx mem2 ; if ( is_fusable_store ( ready [ pos ] , & mem2 ) && ( ( INTEGRAL_MODE_P ( GET_MODE ( mem1 ) ) && adjacent_mem_locations ( mem1 , mem2 ) ) || ( FLOAT_MODE_P ( GET_MODE ( mem1 ) ) && ( adjacent_mem_locations ( mem1 , mem2 ) == mem1 ) ) ) ) { move_to_end_of_ready ( ready , pos , lastpos ) ; load_store_pendulum = - 1 ; break ; } pos -- ; } } return cached_can_issue_more ; } </s>

Do Power10 specific reordering of the ready list .


<s> static void rs6000_xcoff_select_rtx_section ( enum machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) toc_section ( ) ; else read_only_private_data_section ( ) ; } </s>

Select section for constant in constant pool . On RS/6000 , all constants are in the private read-only data area . However , if this is being placed in the TOC it must be output as a toc entry .


<s> bool isImm ( ) const { return Kind == Immediate ; } </s>


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return RegisterVT ; } return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s>
const
char
*
vfp_output_vstmd
(
rtx
*
operands
)
{
char
pattern
[
100
]
;
int
p
;
int
base
;
int
i
;
rtx
addr_reg
=
REG_P
(
XEXP
(
operands
[
0
]
,
0
)
)
XEXP
(
operands
[
0
]
,
0
)
:
XEXP
(
XEXP
(
operands
[
0
]
,
0
)
,
0
)
;
bool
push_p
=
REGNO
(
addr_reg
)
==
SP_REGNUM
;
if
(
push_p
)
strcpy
(
pattern
,
"vpush%?.64\t{%P1"
)
;
else
strcpy
(
pattern
,
"vstmdb%?.64\t%m0!, {%P1"
)
;
p
=
strlen
(
pattern
)
;
gcc_assert
(
REG_P
(
operands
[
1
]
)
)
;
base
=
(
REGNO
(
operands
[
1
]
)
FIRST_VFP_REGNUM
)
/
2
;
for
(
i
=
1
;
i
<
XVECLEN
(
operands
[
2
]
,
0
)
;
i
++
)
{
p
+=
sprintf
(
&
pattern
[
p
]
,
", d%d"
,
base
+
i
)
;
}
strcpy
(
&
pattern
[
p
]
,
"}"
)
;
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>

Output the assembly for a store multiple .


"insertBranch must not be told to insert a fallthrough"

"ARM branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> int fldi_ok ( ) { return ! TARGET_SH4 || TARGET_FMOVD || reload_completed ; } </s>

For -m4 and -m4-single-only , mode switching is used . If we are compiling without -mfmovd , movsf_ie is n't taken into account for mode switching . We could check in machine_dependent_reorg for cases where we know we are in single precision mode , but there is interface to find that out during reload , so we must avoid choosing an fldi alternative during reload and thus failing to allocate a scratch register for the constant loading .


<s> void changingInstr ( MachineInstr & MI ) override { } </s>

This instruction is about to be mutated in some way .


<s> static int uses_TOC ( void ) { rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) { rtx sub = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , 0 ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , 1 ) == UNSPEC_TOC ) return 1 ; } } } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


<s> void X86PassConfig :: addPreEmitPass2 ( ) { const Triple & TT = TM -> getTargetTriple ( ) ; const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( createX86RetpolineThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( createX86AvoidTrailingCallPass ( ) ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> void order_regs_for_local_alloc ( void ) { static int last_order_nonleaf = 1 ; if ( regs_ever_live [ 15 ] != last_order_nonleaf ) { last_order_nonleaf = ! last_order_nonleaf ; memcpy ( ( char * ) reg_alloc_order , ( const char * ) reg_alloc_orders [ last_order_nonleaf ] , FIRST_PSEUDO_REGISTER * sizeof ( int ) ) ; } } </s>

Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


<s> static void rs6000_expand_vector_set_var_p9 ( rtx target , rtx val , rtx idx ) { machine_mode mode = GET_MODE ( target ) ; gcc_assert ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( idx ) ) ; machine_mode inner_mode = GET_MODE ( val ) ; int width = GET_MODE_SIZE ( inner_mode ) ; gcc_assert ( width >= 1 && width <= 8 ) ; int shift = exact_log2 ( width ) ; machine_mode idx_mode = GET_MODE ( idx ) ; machine_mode shift_mode ; rtx ( * gen_ashl ) ( rtx , rtx , rtx ) ; rtx ( * gen_pcvr1 ) ( rtx , rtx ) ; rtx ( * gen_pcvr2 ) ( rtx , rtx ) ; if ( TARGET_POWERPC64 ) { shift_mode = DImode ; gen_ashl = gen_ashldi3 ; gen_pcvr1 = BYTES_BIG_ENDIAN ? gen_altivec_lvsl_reg_di : gen_altivec_lvsr_reg_di ; gen_pcvr2 = BYTES_BIG_ENDIAN ? gen_altivec_lvsr_reg_di : gen_altivec_lvsl_reg_di ; } else { shift_mode = SImode ; gen_ashl = gen_ashlsi3 ; gen_pcvr1 = BYTES_BIG_ENDIAN ? gen_altivec_lvsl_reg_si : gen_altivec_lvsr_reg_si ; gen_pcvr2 = BYTES_BIG_ENDIAN ? gen_altivec_lvsr_reg_si : gen_altivec_lvsl_reg_si ; } rtx tmp = gen_reg_rtx ( shift_mode ) ; idx = convert_modes ( shift_mode , idx_mode , idx , 1 ) ; emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; rtx pcvr1 = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_pcvr1 ( pcvr1 , tmp ) ) ; rtx sub_target = simplify_gen_subreg ( V16QImode , target , mode , 0 ) ; rtx perm1 = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvr1 ) ; emit_insn ( perm1 ) ; rs6000_expand_vector_set ( target , val , const0_rtx ) ; rtx pcvr2 = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_pcvr2 ( pcvr2 , tmp ) ) ; rtx perm2 = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvr2 ) ; emit_insn ( perm2 ) ; } </s>

Insert VAL into IDX of TARGET , VAL size is same of the vector element , IDX is variable and also counts by vector element size for p9 and above .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 16


<s> const MipsInstrInfo * getInstrInfo ( ) const { return InstrInfo . get ( ) ; } </s>


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
BITCAST
:
ReplaceBITCASTResults
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
VECREDUCE_ADD
:
case
ISD
::
VECREDUCE_SMAX
:
case
ISD
::
VECREDUCE_SMIN
:
case
ISD
::
VECREDUCE_UMAX
:
case
ISD
::
VECREDUCE_UMIN
:
Results
.
push_back
(
LowerVECREDUCE
(
SDValue
(
N
,
0
)
,
DAG
)
)
;
return
;
case
AArch64ISD
::
SADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
SADDV
)
;
return
;
case
AArch64ISD
::
UADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
UADDV
)
;
return
;
case
AArch64ISD
::
SMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMIN
,
AArch64ISD
::
SMINV
)
;
return
;
case
AArch64ISD
::
UMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMIN
,
AArch64ISD
::
UMINV
)
;
return
;
case
AArch64ISD
::
SMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMAX
,
AArch64ISD
::
SMAXV
)
;
return
;
case
AArch64ISD
::
UMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMAX
,
AArch64ISD
::
UMAXV
)
;
return
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_128Results
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask : CSR_Darwin64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask ) ; if ( CC == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_RegMask : CSR_SVR32_ColdCC_RegMask ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : CSR_SVR432_RegMask ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void rs6000_emit_msub ( rtx target , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( target ) ; rtx dst ; if ( optab_handler ( fms_optab , mode ) != CODE_FOR_nothing ) dst = expand_ternary_op ( mode , fms_optab , m1 , m2 , a , target , 0 ) ; else { a = expand_unop ( mode , neg_optab , a , NULL_RTX , 0 ) ; dst = expand_ternary_op ( mode , fma_optab , m1 , m2 , a , target , 0 ) ; } gcc_assert ( dst != NULL ) ; if ( dst != target ) emit_move_insn ( target , dst ) ; } </s>

Generate a FMSUB instruction : dst = fma ( m1 , m2 , -a ) .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> static rtx rs6000_emit_stack_reset ( rs6000_stack_t * info , rtx frame_reg_rtx , HOST_WIDE_INT frame_off , unsigned updt_regno ) { if ( frame_off == 0 && REGNO ( frame_reg_rtx ) == updt_regno ) return NULL_RTX ; rtx updt_reg_rtx = gen_rtx_REG ( Pmode , updt_regno ) ; if ( DEFAULT_ABI == ABI_V4 || ( TARGET_SPE_ABI && info -> spe_64bit_regs_used != 0 && info -> first_gp_reg_save != 32 ) ) return emit_insn ( gen_stack_restore_tie ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; if ( frame_off != 0 ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else return emit_move_insn ( updt_reg_rtx , frame_reg_rtx ) ; return NULL_RTX ; } </s>

Emit a sequence of insns , including a stack tie if needed , for resetting the stack pointer . If UPDT_REGNO is not 1 , then do n't reset the stack pointer , but move the base of the frame into reg UPDT_REGNO for use by out-of-line register restore routines .


<s> void pure_scalable_type_info :: add_piece ( const piece & p ) { if ( ! pieces . is_empty ( ) ) { piece & prev = pieces . last ( ) ; gcc_assert ( VECTOR_MODE_P ( p . mode ) && VECTOR_MODE_P ( prev . mode ) ) ; unsigned int nelems1 , nelems2 ; if ( prev . orig_mode == p . orig_mode && known_eq ( prev . offset + GET_MODE_SIZE ( prev . mode ) , p . offset ) && constant_multiple_p ( GET_MODE_NUNITS ( prev . mode ) , GET_MODE_NUNITS ( p . orig_mode ) , & nelems1 ) && constant_multiple_p ( GET_MODE_NUNITS ( p . mode ) , GET_MODE_NUNITS ( p . orig_mode ) , & nelems2 ) && targetm . array_mode ( p . orig_mode , nelems1 + nelems2 ) . exists ( & prev . mode ) ) { prev . num_zr += p . num_zr ; prev . num_pr += p . num_pr ; return ; } } pieces . quick_push ( p ) ; } </s>

Add P to the list of pieces in the type .


<s>
static
void
mmix_asm_output_mi_thunk
(
FILE
*
stream
,
tree
thunk_fndecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
func
)
{
const
char
*
regname
=
reg_names
[
MMIX_FIRST_INCOMING_ARG_REGNUM
]
;
const
char
*
fnname
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
thunk_fndecl
)
)
;
assemble_start_function
(
thunk_fndecl
,
fnname
)
;
if
(
delta
>=
0
&&
delta
<
65536
)
fprintf
(
stream
,
"\tINCL %s,%d\n"
,
regname
,
(
int
)
delta
)
;
else
if
(
delta
<
0
&&
delta
>=
255
)
fprintf
(
stream
,
"\tSUBU %s,%s,%d\n"
,
regname
,
regname
,
(
int
)
delta
)
;
else
{
mmix_output_register_setting
(
stream
,
255
,
delta
,
1
)
;
fprintf
(
stream
,
"\tADDU %s,%s,$255\n"
,
regname
,
regname
)
;
}
fprintf
(
stream
,
"\tJMP "
)
;
assemble_name
(
stream
,
XSTR
(
XEXP
(
DECL_RTL
(
func
)
,
0
)
,
0
)
)
;
fprintf
(
stream
,
"\n"
)
;
assemble_end_function
(
thunk_fndecl
,
fnname
)
;
}
</s>


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> int shmedia_cleanup_truncate ( rtx x ) { int n_changes = 0 ; subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , NONCONST ) { rtx x = * iter ; if ( GET_CODE ( x ) == TRUNCATE ) { rtx reg = XEXP ( x , 0 ) ; machine_mode reg_mode = GET_MODE ( reg ) ; if ( REG_P ( reg ) && GET_MODE_SIZE ( reg_mode ) > 8 ) { int offset = subreg_lowpart_offset ( DImode , reg_mode ) ; XEXP ( x , 0 ) = simplify_subreg ( DImode , reg , reg_mode , offset ) ; n_changes += 1 ; iter . skip_subrtxes ( ) ; } } } return n_changes ; } </s>

Look through X cleaning up truncates of registers that span multiple actual hard registers . Return the number of changes made .


<s> static int mips_small_data_pattern_1 ( rtx * loc , void * data ATTRIBUTE_UNUSED ) { if ( GET_CODE ( * loc ) == LO_SUM ) return - 1 ; return mips_rewrite_small_data_p ( * loc ) ; } </s>

A for_each_rtx callback for mips_small_data_pattern_p .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned getCacheLineSize ( ) const override { return 256 ; } </s>

Return the target cache line size in bytes .


<s> bool MipsSEInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 1 ) . getImm ( ) != ( 1 << 4 ) ) return false ; else if ( isDSPControlWrite ) { Src = & MI . getOperand ( 0 ) ; Dest = & MI . getOperand ( 2 ) ; } else { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 2 ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } return false ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> static void emit_and_preserve ( rtx seq , rtx reg , rtx reg2 ) { HOST_WIDE_INT offset = 16 * UNITS_PER_WORD ; HOST_WIDE_INT size = SPARC_STACK_ALIGN ( offset + 2 * UNITS_PER_WORD ) ; rtx slot = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , stack_pointer_rtx , SPARC_STACK_BIAS + offset ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - size ) ) ) ; emit_insn ( gen_rtx_SET ( slot , reg ) ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( adjust_address ( slot , word_mode , UNITS_PER_WORD ) , reg2 ) ) ; emit_insn ( seq ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( reg2 , adjust_address ( slot , word_mode , UNITS_PER_WORD ) ) ) ; emit_insn ( gen_rtx_SET ( reg , slot ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; } </s>

Emit the sequence of insns SEQ while preserving the registers .


<s> OperandMatchResultTy CSKYAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( getSTI ( ) , ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> size_type count ( ) const { return V . count ( ) ; } </s>

Return 1 if the specified key is in the map , 0 otherwise .


<s> void FixupSFBPass :: buildCopy ( MachineInstr * LoadInst , unsigned NLoadOpcode , int64_t LoadDisp , MachineInstr * StoreInst , unsigned NStoreOpcode , int64_t StoreDisp , unsigned Size , int64_t LMMOffset , int64_t SMMOffset ) { MachineOperand & LoadBase = getBaseOperand ( LoadInst ) ; MachineOperand & StoreBase = getBaseOperand ( StoreInst ) ; MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; MachineMemOperand * LMMO = * LoadInst -> memoperands_begin ( ) ; MachineMemOperand * SMMO = * StoreInst -> memoperands_begin ( ) ; unsigned Reg1 = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( NLoadOpcode ) , 0 , TRI , * ( MBB -> getParent ( ) ) ) ) ; BuildMI ( * MBB , LoadInst , LoadInst -> getDebugLoc ( ) , TII -> get ( NLoadOpcode ) , Reg1 ) . add ( LoadBase ) . addImm ( 1 ) . addReg ( X86 :: NoRegister ) . addImm ( LoadDisp ) . addReg ( X86 :: NoRegister ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( LMMO , LMMOffset , Size ) ) ; DEBUG ( LoadInst -> getPrevNode ( ) -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; if ( StoreInst -> getPrevNode ( ) == LoadInst ) StInst = LoadInst ; BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( 1 ) . addReg ( X86 :: NoRegister ) . addImm ( StoreDisp ) . addReg ( X86 :: NoRegister ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ; DEBUG ( StInst -> getPrevNode ( ) -> dump ( ) ) ; } </s>


<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: const_iterator I = MemOp2RegOpTable . find ( Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return 0 ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I -> second . second & TB_FOLDED_STORE ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; if ( LoadRegIndex ) * LoadRegIndex = I -> second . second & TB_INDEX_MASK ; return I -> second . first ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


"AArch64 Collect Linker Optimization Hint (LOH)"

getPassName - Return a nice clean name for a pass .


<s> TargetPassConfig * TOYTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TOYPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
static_cast
<
MipsTargetMachine
&
>
(
TM
)
.
getABI
(
)
.
GetEnumValue
(
)
)
{
case
MipsABIInfo
::
ABI
::
O32
:
return
"abi32"
;
case
MipsABIInfo
::
ABI
::
N32
:
return
"abiN32"
;
case
MipsABIInfo
::
ABI
::
N64
:
return
"abi64"
;
case
MipsABIInfo
::
ABI
::
EABI
:
return
"eabi32"
;
default
:
llvm_unreachable
(
"Unknown Mips ABI"
)
;
}
}
</s>

Mips
Mips
Mips
Mips
"abi32"
Mips
"abiN32"
Mips
"abi64"
Mips
"eabi32"
"Unknown Mips ABI"


<s>
int
rs6000_arg_partial_bytes
(
cumulative_args_t
cum_v
,
const
function_arg_info
&
arg
)
{
CUMULATIVE_ARGS
*
cum
=
get_cumulative_args
(
cum_v
)
;
bool
passed_in_gprs
=
true
;
int
ret
=
0
;
int
align_words
;
machine_mode
elt_mode
;
int
n_elts
;
rs6000_discover_homogeneous_aggregate
(
arg
.
mode
,
arg
.
type
,
&
elt_mode
,
&
n_elts
)
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
elt_mode
,
arg
.
named
)
)
{
if
(
TARGET_64BIT
&&
!
cum
->
prototype
&&
(
!
cum
->
libcall
||
!
FLOAT128_VECTOR_P
(
elt_mode
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
vregno
+
n_elts
>
ALTIVEC_ARG_MAX_REG
+
1
)
ret
=
(
ALTIVEC_ARG_MAX_REG
+
1
cum
->
vregno
)
*
16
;
}
if
(
TARGET_MACHO
&&
rs6000_darwin64_struct_check_p
(
arg
.
mode
,
arg
.
type
)
)
return
0
;
align_words
=
rs6000_parm_start
(
arg
.
mode
,
arg
.
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
elt_mode
)
&&
!
(
TARGET_AIX
&&
!
TARGET_ELF
&&
arg
.
aggregate_type_p
(
)
)
)
{
unsigned
long
n_fpreg
=
(
GET_MODE_SIZE
(
elt_mode
)
+
7
)
>>
3
;
if
(
arg
.
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
fregno
+
n_elts
*
n_fpreg
>
FP_ARG_MAX_REG
+
1
)
{
int
fpr
=
(
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
MIN
(
8
,
GET_MODE_SIZE
(
elt_mode
)
)
)
;
int
fpr_words
=
fpr
/
(
TARGET_32BIT
4
:
8
)
;
if
(
align_words
+
fpr_words
<
GP_ARG_NUM_REG
)
passed_in_gprs
=
true
;
else
ret
=
fpr
;
}
}
if
(
passed_in_gprs
&&
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
arg
.
mode
,
arg
.
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None , bool MatchingInlineAsm = false ) { if ( MatchingInlineAsm ) return true ; return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> rtx rs6000_emit_fp_cror ( rtx_code code , machine_mode mode , rtx x ) { rtx cond [ 2 ] ; int n = 0 ; if ( code == LTGT || code == LE || code == UNLT ) cond [ n ++ ] = gen_rtx_fmt_ee ( LT , mode , x , const0_rtx ) ; if ( code == LTGT || code == GE || code == UNGT ) cond [ n ++ ] = gen_rtx_fmt_ee ( GT , mode , x , const0_rtx ) ; if ( code == LE || code == GE || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( EQ , mode , x , const0_rtx ) ; if ( code == UNLT || code == UNGT || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( UNORDERED , mode , x , const0_rtx ) ; gcc_assert ( n == 2 ) ; rtx cc = gen_reg_rtx ( CCEQmode ) ; rtx logical = gen_rtx_IOR ( mode , cond [ 0 ] , cond [ 1 ] ) ; emit_insn ( gen_cceq_ior_compare ( mode , cc , logical , cond [ 0 ] , x , cond [ 1 ] , x ) ) ; return cc ; } </s>

Emit code doing a cror of two CR bits , for FP comparisons with a CODE that requires this . The result is mode MODE .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCFrameLowering * PPCFI = static_cast < const PPCFrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( PPCFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: X86_FastCall ) ; F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } return ; } auto GuardMode = getTargetMachine ( ) . Options . StackProtectorGuard ; if ( ( GuardMode == llvm :: StackProtectorGuards :: TLS || GuardMode == llvm :: StackProtectorGuards :: None ) && hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> static void emit_hard_tfmode_operation ( enum rtx_code code , rtx * operands ) { rtx op , dest ; if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) { operands [ 1 ] = force_reg ( GET_MODE ( operands [ 1 ] ) , operands [ 1 ] ) ; op = gen_rtx_fmt_e ( code , GET_MODE ( operands [ 0 ] ) , operands [ 1 ] ) ; } else { operands [ 1 ] = force_reg ( GET_MODE ( operands [ 1 ] ) , operands [ 1 ] ) ; operands [ 2 ] = force_reg ( GET_MODE ( operands [ 2 ] ) , operands [ 2 ] ) ; op = gen_rtx_fmt_ee ( code , GET_MODE ( operands [ 0 ] ) , operands [ 1 ] , operands [ 2 ] ) ; } if ( register_operand ( operands [ 0 ] , VOIDmode ) ) dest = operands [ 0 ] ; else dest = gen_reg_rtx ( GET_MODE ( operands [ 0 ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , op ) ) ; if ( dest != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dest ) ; } </s>

Expand a hard-float tfmode operation . All arguments must be in registers .


<s> unsigned getNumFixupKinds ( ) const { return 4 ; } </s>

Get the number of target specific fixup kinds .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
begin
(
)
,
RPIE
=
RegPairs
.
end
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
return
true
;
}
</s>


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass 0 ARM::t2STRi12 0 ARM


<s> static machine_mode rs6000_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VSX ) switch ( mode ) { case E_DFmode : return V2DFmode ; default : ; } if ( TARGET_ALTIVEC || TARGET_VSX ) switch ( mode ) { case E_SFmode : return V4SFmode ; case E_TImode : return V1TImode ; case E_DImode : return V2DImode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; default : ; } if ( TARGET_SPE ) switch ( mode ) { case E_SFmode : return V2SFmode ; case E_SImode : return V2SImode ; default : ; } if ( TARGET_PAIRED_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode ; } </s>


<s>
bool
ARM64InstrInfo
::
isGPRZero
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
ARM64
::
MOVZWi
:
case
ARM64
::
MOVZXi
:
if
(
MI
->
getOperand
(
1
)
.
isImm
(
)
&&
MI
->
getOperand
(
1
)
.
getImm
(
)
==
0
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
&&
"invalid MOVZi operands"
)
;
return
true
;
}
break
;
case
ARM64
::
ANDWri
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
ARM64
::
WZR
;
case
ARM64
::
ANDXri
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
ARM64
::
XZR
;
case
TargetOpcode
::
COPY
:
return
MI
->
getOperand
(
1
)
.
getReg
(
)
==
ARM64
::
WZR
;
}
return
false
;
}
</s>

Does this instruction set its full destination register to zero ?


<s>
static
void
ix86_code_end
(
void
)
{
rtx
xops
[
2
]
;
int
regno
;
for
(
regno
=
AX_REG
;
regno
<=
SP_REG
;
regno
++
)
{
char
name
[
32
]
;
tree
decl
;
if
(
!
(
pic_labels_used
&
(
1
<<
regno
)
)
)
continue
;
get_pc_thunk_name
(
name
,
regno
)
;
decl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
name
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
DECL_RESULT
(
decl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
DECL_IGNORED_P
(
decl
)
=
1
;
if
(
TARGET_MACHO
)
{
switch_to_section
(
darwin_sections
[
text_coal_section
]
)
;
fputs
(
"\t.weak_definition\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
fputs
(
"\n\t.private_extern\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
DECL_WEAK
(
decl
)
=
1
;
}
else
if
(
USE_HIDDEN_LINKONCE
)
{
cgraph_node
::
create
(
decl
)
->
set_comdat_group
(
DECL_ASSEMBLER_NAME
(
decl
)
)
;
targetm
.
asm_out
.
unique_section
(
decl
,
0
)
;
switch_to_section
(
get_named_section
(
decl
,
,
0
)
)
;
targetm
.
asm_out
.
globalize_label
(
asm_out_file
,
name
)
;
fputs
(
"\t.hidden\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_DECLARE_FUNCTION_NAME
(
asm_out_file
,
name
,
decl
)
;
}
else
{
switch_to_section
(
text_section
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
}
DECL_INITIAL
(
decl
)
=
make_node
(
BLOCK
)
;
current_function_decl
=
decl
;
allocate_struct_function
(
decl
,
false
)
;
init_function_start
(
decl
)
;
first_function_block_is_cold
=
false
;
final_start_function
(
emit_barrier
(
)
,
asm_out_file
,
1
)
;
if
(
TARGET_PAD_SHORT_FUNCTION
)
{
int
i
=
8
;
while
(
i
)
fputs
(
"\tnop\n"
,
asm_out_file
)
;
}
xops
[
0
]
=
gen_rtx_REG
(
Pmode
,
regno
)
;
xops
[
1
]
=
gen_rtx_MEM
(
Pmode
,
stack_pointer_rtx
)
;
output_asm_insn
(
"mov%z0\t{%1, %0|%0, %1}"
,
xops
)
;
output_asm_insn
(
"%!ret"
,
)
;
final_end_function
(
)
;
init_insn_lengths
(
)
;
free_after_compilation
(
cfun
)
;
set_cfun
(
)
;
current_function_decl
=
;
}
if
(
flag_split_stack
)
file_end_indicate_split_stack
(
)
;
}
</s>

This function generates code for -fpic that loads % ebx with the return address of the caller and then returns .


<s> const char * getClearCacheBuiltinName ( ) const override { return nullptr ; } </s>

Intel processors have a unified instruction and data cache .


"-mno-power9-vector turns off -mpower9-dform"

If the user used -mno-vsx , we need turn off all of the implicit ISA 2.06 , 2.07 , and 3.0 options that relate to the vector unit ( -mdirect-move , -mupper-regs-df , etc. ) . If the user used -mno-power8-vector , we need to turn off all of the implicit ISA 2.07 and 3.0 options that relate to the vector unit . If the user used -mno-power9-vector , we need to turn off all of the implicit ISA 3.0 options that relate to the vector unit . This function does not handle explicit options such as the user specifying -mdirect-move . These are handled in rs6000_option_override_internal , and the appropriate error is given if needed . We return a mask of all of the implicit options that should not be enabled by default .


<s> static bool ix86_class_likely_spilled_p ( reg_class_t rclass ) { switch ( rclass ) { case AREG : case DREG : case CREG : case BREG : case AD_REGS : case SIREG : case DIREG : case SSE_FIRST_REG : case FP_TOP_REG : case FP_SECOND_REG : case BND_REGS : return true ; default : break ; } return false ; } </s>


<s> static void arm_add_cfa_adjust_cfa_note ( rtx insn , int size , rtx dest , rtx src ) { rtx dwarf ; RTX_FRAME_RELATED_P ( insn ) = 1 ; dwarf = gen_rtx_SET ( VOIDmode , dest , plus_constant ( Pmode , src , size ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , dwarf ) ; } </s>

Add a REG_CFA_ADJUST_CFA REG note to INSN . SIZE is the offset to be adjusted . DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx .


<s> unsigned TeeRISCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { assert ( 0 ) ; if ( MI -> getOpcode ( ) == TeeRISC :: LD ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void finish ( ) override { for ( auto * Sym : UpdateOther ) if ( Sym -> isVariable ( ) ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s>
bool
X86CallFrameOptimization
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
STI
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
STI
->
getInstrInfo
(
)
;
TFL
=
STI
->
getFrameLowering
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
const
X86RegisterInfo
&
RegInfo
=
*
static_cast
<
const
X86RegisterInfo
*
>
(
STI
->
getRegisterInfo
(
)
)
;
SlotSize
=
RegInfo
.
getSlotSize
(
)
;
assert
(
isPowerOf2_32
(
SlotSize
)
&&
"Expect power of 2 stack slot size"
)
;
Log2SlotSize
=
Log2_32
(
SlotSize
)
;
if
(
!
isLegal
(
MF
)
)
return
false
;
unsigned
FrameSetupOpcode
=
TII
->
getCallFrameSetupOpcode
(
)
;
bool
Changed
=
false
;
ContextVector
CallSeqVector
;
for
(
auto
&
MBB
:
MF
)
for
(
auto
&
MI
:
MBB
)
if
(
MI
.
getOpcode
(
)
==
FrameSetupOpcode
)
{
CallContext
Context
;
collectCallInfo
(
MF
,
MBB
,
MI
,
Context
)
;
CallSeqVector
.
push_back
(
Context
)
;
}
if
(
!
isProfitable
(
MF
,
CallSeqVector
)
)
return
false
;
for
(
auto
CC
:
CallSeqVector
)
{
if
(
CC
.
UsePush
)
{
adjustCallSequence
(
MF
,
CC
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , TSInfo ( * TM . getDataLayout ( ) ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM


<s> static bool sh_cannot_modify_jumps_p ( ) { return ( TARGET_SHMEDIA && ( reload_in_progress || reload_completed ) ) ; } </s>

SHmedia requires registers for branches , so we ca n't generate new branches past reload .


<s> static int arm_issue_rate ( void ) { return current_tune -> issue_rate ; } </s>

Most ARM cores are single issue , but some newer ones can dual issue . The scheduler descriptions rely on this being correct .


<s> bool gen_stm_seq ( rtx * operands , int nops ) { int i ; int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int stm_case ; rtx addr ; bool base_reg_dies ; stm_case = store_multiple_sequence ( operands , nops , nops , regs , NULL , mem_order , & base_reg , & offset , true ) ; if ( stm_case == 0 ) return false ; base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; base_reg_dies = peep2_reg_dead_p ( nops , base_reg_rtx ) ; if ( TARGET_THUMB1 ) { gcc_assert ( base_reg_dies ) ; write_back = TRUE ; } if ( stm_case == 5 ) { gcc_assert ( base_reg_dies ) ; emit_insn ( gen_addsi3 ( base_reg_rtx , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = 0 ; } addr = plus_constant ( Pmode , base_reg_rtx , offset ) ; for ( i = 0 ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , 0 ) ; } emit_insn ( arm_gen_store_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * 4 : 0 ) ) ; return true ; } </s>

Called from a peephole2 expander to turn a sequence of stores into an STM instruction . OPERANDS are the operands found by the peephole matcher ; NOPS indicates how many separate stores we are trying to combine . Returns true iff we could generate a new instruction .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool MipsAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void SystemZTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { bool HasCall = false ; unsigned NumStores = 0 ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == Intrinsic :: memcpy || F -> getIntrinsicID ( ) == Intrinsic :: memset ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( 0 ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , 0 , TTI :: TCK_RecipThroughput ) ; } } unsigned const Max = ( NumStores ? ( 12 / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = 1 ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= 1 ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = 75 ; UP . DefaultUnrollRuntimeCount = 4 ; UP . AllowExpensiveTripCount = true ; UP . Force = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static reg_class_t ia64_preferred_reload_class ( rtx x , reg_class_t rclass ) { switch ( rclass ) { case FR_REGS : case FP_REGS : if ( MEM_P ( x ) && MEM_VOLATILE_P ( x ) ) return NO_REGS ; if ( CONSTANT_P ( x ) ) return NO_REGS ; break ; case AR_M_REGS : case AR_I_REGS : if ( ! OBJECT_P ( x ) ) return NO_REGS ; break ; default : break ; } return rclass ; } </s>

Implement PREFERRED_RELOAD_CLASS . Place additional restrictions on CLASS to use when copying X into that class .


<s> static bool mips_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; if ( TARGET_MIPS16 ) { mips_compute_frame_info ( ) ; if ( ! SMALL_OPERAND ( cfun -> machine -> frame . total_size ) ) return true ; } return false ; } </s>


<s> bool ARMPassConfig :: addPreISel ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMParallelDSPPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } return false ; } </s>


<s> static rtx expand_msb ( function_expander & e , unsigned int merge_argno = DEFAULT_MERGE_ARGNO ) { if ( e . pred == PRED_x ) { insn_code icode ; if ( e . type_suffix ( 0 ) . integer_p ) icode = code_for_aarch64_pred_fnma ( e . vector_mode ( 0 ) ) ; else icode = code_for_aarch64_pred ( UNSPEC_COND_FMLS , e . vector_mode ( 0 ) ) ; return e . use_pred_x_insn ( icode ) ; } insn_code icode = e . direct_optab_handler ( cond_fnma_optab ) ; return e . use_cond_insn ( icode , merge_argno ) ; } </s>

Expand a call to svmsb , or svmls after reordering its operands . Make _m forms merge with argument MERGE_ARGNO .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > ( ) ; PPCAsmPrinter :: getAnalysisUsage ( AU ) ; } </s>


<s> bool PPCTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( ! getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return false ; if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) . getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = 0 ; i != Ins . size ( ) ; i ++ ) { ISD :: ArgFlagsTy Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

PowerPC PPC ISD::InputArg 0 ISD::ArgFlagsTy


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs ) const { return NumInstrs && NumInstrs == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( is64bit ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> CCAssignFn * AArch64FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: WebKit_JS ) return CC_AArch64_WebKit_JS ; if ( CC == CallingConv :: GHC ) return CC_AArch64_GHC ; if ( CC == CallingConv :: CFGuard_Check ) return CC_AArch64_Win64_CFGuard_Check ; return Subtarget -> isTargetDarwin ( ) ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool n9_3r2w_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_PBSAD : case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


"A single use instruction with no uses."

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> void PPCPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; X86OutgoingValueAssigner Assigner ( CC_X86 ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static const char * pa_strip_name_encoding ( const char * str ) { str += ( * str == '@' ) ; str += ( * str == '*' ) ; return str ; } </s>

This is sort of inverse to pa_encode_section_info .


<s> bool ARMBaseInstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI . getDesc ( ) . TSFlags & ARMII :: DomainMask ; unsigned UDomain = UseMI . getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Subtarget . nonpipelinedVFP ( ) && ( DDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainVFP ) ) return true ; unsigned Latency = SchedModel . computeOperandLatency ( & DefMI , DefIdx , & UseMI , UseIdx ) ; if ( Latency <= 3 ) return false ; return DDomain == ARMII :: DomainVFP || DDomain == ARMII :: DomainNEON || UDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainNEON ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .

ARM ARM ARMII::DomainMask ARMII::DomainMask ARMII::DomainVFP ARMII::DomainVFP 3 ARMII::DomainVFP ARMII::DomainNEON ARMII::DomainVFP ARMII::DomainNEON


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
bool
LEAUsesAG
=
ST
.
LEAusesAG
(
)
;
bool
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
bool
UseLEAForSP
=
ST
.
useLeaForSP
(
)
;
TSM
.
init
(
&
ST
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
{
if
(
!
isLEA
(
I
->
getOpcode
(
)
)
)
continue
;
if
(
optTwoAddrLEA
(
I
,
MBB
,
OptIncDec
,
UseLEAForSP
)
)
continue
;
if
(
IsSlowLEA
)
processInstructionForSlowLEA
(
I
,
MBB
)
;
else
if
(
IsSlow3OpsLEA
)
processInstrForSlow3OpLEA
(
I
,
MBB
,
OptIncDec
)
;
}
if
(
LEAUsesAG
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
processInstruction
(
I
,
MBB
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static poly_int64 vax_return_pops_args ( tree fundecl ATTRIBUTE_UNUSED , tree funtype ATTRIBUTE_UNUSED , poly_int64 size ) { return size > 255 * 4 ? 0 : ( HOST_WIDE_INT ) size ; } </s>

Value is the number of bytes of arguments automatically popped when returning from a subroutine call . FUNDECL is the declaration node of the function ( as a tree ) , FUNTYPE is the data type of the function ( as a tree ) , or for a library call it is an identifier node for the subroutine name . SIZE is the number of bytes of arguments passed on the stack . On the VAX , the RET insn pops a maximum of 255 args for any function .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> unsigned X86TargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) { RegisterVT = MVT :: i8 ; IntermediateVT = MVT :: i1 ; NumIntermediates = VT . getVectorNumElements ( ) ; return NumIntermediates ; } return TargetLowering :: getVectorTypeBreakdownForCallingConv ( Context , CC , VT , IntermediateVT , NumIntermediates , RegisterVT ) ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> rtx mips_pic_base_register ( rtx temp ) { if ( ! TARGET_MIPS16 ) return pic_offset_table_rtx ; if ( currently_expanding_to_rtl ) return mips16_gp_pseudo_reg ( ) ; if ( can_create_pseudo_p ( ) ) temp = gen_reg_rtx ( Pmode ) ; if ( TARGET_USE_GOT ) mips_emit_move ( temp , pic_offset_table_rtx ) ; else emit_insn ( gen_load_const_gp ( temp ) ) ; return temp ; } </s>

Return a base register that holds pic_offset_table_rtx . TEMP , if nonnull , is a scratch Pmode base register .


<s> static HOST_WIDE_INT mips_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


"Handling of TOC entry displacement larger than 32767 "

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitMappingSymbol ( "$t" ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


"Unable to build a return instruction?!"

"The insertion did not happen where we expected"

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
const
TargetRegisterClass
*
ARMBaseRegisterInfo
::
getMatchingSuperRegClass
(
const
TargetRegisterClass
*
A
,
const
TargetRegisterClass
*
B
,
unsigned
SubIdx
)
const
{
switch
(
SubIdx
)
{
default
:
return
0
;
case
ARM
::
ssub_0
:
case
ARM
::
ssub_1
:
case
ARM
::
ssub_2
:
case
ARM
::
ssub_3
:
{
if
(
A
->
getSize
(
)
==
8
)
{
if
(
B
==
&
ARM
::
SPR_8RegClass
)
return
&
ARM
::
DPR_8RegClass
;
assert
(
B
==
&
ARM
::
SPRRegClass
&&
"Expecting SPR register class!"
)
;
if
(
A
==
&
ARM
::
DPR_8RegClass
)
return
A
;
return
&
ARM
::
DPR_VFP2RegClass
;
}
if
(
A
->
getSize
(
)
==
16
)
{
if
(
B
==
&
ARM
::
SPR_8RegClass
)
return
&
ARM
::
QPR_8RegClass
;
return
&
ARM
::
QPR_VFP2RegClass
;
}
if
(
A
->
getSize
(
)
==
32
)
{
if
(
B
==
&
ARM
::
SPR_8RegClass
)
return
0
;
return
&
ARM
::
QQPR_VFP2RegClass
;
}
assert
(
A
->
getSize
(
)
==
64
&&
"Expecting a QQQQ register class!"
)
;
return
0
;
}
case
ARM
::
dsub_0
:
case
ARM
::
dsub_1
:
case
ARM
::
dsub_2
:
case
ARM
::
dsub_3
:
{
if
(
A
->
getSize
(
)
==
16
)
{
if
(
B
==
&
ARM
::
DPR_VFP2RegClass
)
return
&
ARM
::
QPR_VFP2RegClass
;
if
(
B
==
&
ARM
::
DPR_8RegClass
)
return
0
;
return
A
;
}
if
(
A
->
getSize
(
)
==
32
)
{
if
(
B
==
&
ARM
::
DPR_VFP2RegClass
)
return
&
ARM
::
QQPR_VFP2RegClass
;
if
(
B
==
&
ARM
::
DPR_8RegClass
)
return
0
;
return
A
;
}
assert
(
A
->
getSize
(
)
==
64
&&
"Expecting a QQQQ register class!"
)
;
if
(
B
!=
&
ARM
::
DPRRegClass
)
return
0
;
return
A
;
}
case
ARM
::
dsub_4
:
case
ARM
::
dsub_5
:
case
ARM
::
dsub_6
:
case
ARM
::
dsub_7
:
{
if
(
A
->
getSize
(
)
==
64
&&
B
==
&
ARM
::
DPRRegClass
)
return
A
;
return
0
;
}
case
ARM
::
qsub_0
:
case
ARM
::
qsub_1
:
{
if
(
A
->
getSize
(
)
==
32
)
{
if
(
B
==
&
ARM
::
QPR_VFP2RegClass
)
return
&
ARM
::
QQPR_VFP2RegClass
;
if
(
B
==
&
ARM
::
QPR_8RegClass
)
return
0
;
return
A
;
}
assert
(
A
->
getSize
(
)
==
64
&&
"Expecting a QQQQ register class!"
)
;
if
(
B
==
&
ARM
::
QPRRegClass
)
return
A
;
return
0
;
}
case
ARM
::
qsub_2
:
case
ARM
::
qsub_3
:
{
if
(
A
->
getSize
(
)
==
64
&&
B
==
&
ARM
::
QPRRegClass
)
return
A
;
return
0
;
}
}
return
0
;
}
</s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s> static tree altivec_build_resolved_builtin ( tree * args , int n , tree fntype , tree ret_type , rs6000_gen_builtins bif_id , rs6000_gen_builtins ovld_id ) { tree argtypes = TYPE_ARG_TYPES ( fntype ) ; tree arg_type [ MAX_OVLD_ARGS ] ; tree fndecl = rs6000_builtin_decls [ bif_id ] ; for ( int i = 0 ; i < n ; i ++ ) { arg_type [ i ] = TREE_VALUE ( argtypes ) ; argtypes = TREE_CHAIN ( argtypes ) ; } if ( n == 3 && ovld_id == RS6000_OVLD_VEC_CMPGE_P && bif_id != RS6000_BIF_VCMPGEFP_P && bif_id != RS6000_BIF_XVCMPGEDP_P ) { std :: swap ( args [ 1 ] , args [ 2 ] ) ; std :: swap ( arg_type [ 1 ] , arg_type [ 2 ] ) ; args [ 0 ] = fold_build2 ( BIT_XOR_EXPR , TREE_TYPE ( args [ 0 ] ) , args [ 0 ] , build_int_cst ( NULL_TREE , 2 ) ) ; } for ( int j = 0 ; j < n ; j ++ ) args [ j ] = fully_fold_convert ( arg_type [ j ] , args [ j ] ) ; gcc_assert ( MAX_OVLD_ARGS <= 4 ) ; tree call ; switch ( n ) { case 0 : call = build_call_expr ( fndecl , 0 ) ; break ; case 1 : call = build_call_expr ( fndecl , 1 , args [ 0 ] ) ; break ; case 2 : call = build_call_expr ( fndecl , 2 , args [ 0 ] , args [ 1 ] ) ; break ; case 3 : call = build_call_expr ( fndecl , 3 , args [ 0 ] , args [ 1 ] , args [ 2 ] ) ; break ; case 4 : call = build_call_expr ( fndecl , 4 , args [ 0 ] , args [ 1 ] , args [ 2 ] , args [ 3 ] ) ; break ; default : gcc_unreachable ( ) ; } return fold_convert ( ret_type , call ) ; } </s>

Build a tree for a function call to an Altivec non-overloaded builtin . The overloaded builtin that matched the types and args is described by DESC . The N arguments are given in ARGS , respectively . Actually the only thing it does is calling fold_convert on ARGS , with a small exception for vec_ { all , any } _ { ge , le } predicates .


<s> static void rs6000_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; if ( cost_data -> loop_info ) rs6000_density_test ( cost_data ) ; if ( cost_data -> loop_info ) { loop_vec_info vec_info = loop_vec_info_for_loop ( cost_data -> loop_info ) ; if ( ! rs6000_vect_nonmem && LOOP_VINFO_VECT_FACTOR ( vec_info ) == 2 && LOOP_REQUIRES_VERSIONING ( vec_info ) ) cost_data -> cost [ vect_body ] += 10000 ; } * prologue_cost = cost_data -> cost [ vect_prologue ] ; * body_cost = cost_data -> cost [ vect_body ] ; * epilogue_cost = cost_data -> cost [ vect_epilogue ] ; } </s>


<s> bool SparcAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; const MachineBasicBlock * Pred = * PI ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> CCAssignFn * AArch64FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: WebKit_JS ) return CC_AArch64_WebKit_JS ; if ( CC == CallingConv :: GHC ) return CC_AArch64_GHC ; return Subtarget -> isTargetDarwin ( ) ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0


<s> unsigned X86FastISel :: fastMaterializeFloatZero ( const ConstantFP * CF ) { MVT VT ; if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return 0 ; bool HasSSE1 = Subtarget -> hasSSE1 ( ) ; bool HasSSE2 = Subtarget -> hasSSE2 ( ) ; bool HasAVX512 = Subtarget -> hasAVX512 ( ) ; unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : return 0 ; case MVT :: f32 : Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SS : HasSSE1 ? X86 :: FsFLD0SS : X86 :: LD_Fp032 ; break ; case MVT :: f64 : Opc = HasAVX512 ? X86 :: AVX512_FsFLD0SD : HasSSE2 ? X86 :: FsFLD0SD : X86 :: LD_Fp064 ; break ; case MVT :: f80 : return 0 ; } Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } </s>

Emit the floating-point constant +0.0 in a register using target- specific logic .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> rtx rs6000_longcall_ref ( rtx call_ref ) { const char * call_name ; tree node ; if ( GET_CODE ( call_ref ) != SYMBOL_REF ) return call_ref ; call_name = XSTR ( call_ref , 0 ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } return force_reg ( Pmode , call_ref ) ; } </s>

Return a reference suitable for calling a function with the longcall attribute .


Count number of GROUP restricted instructions in a dispatch window WINDOW_LIST .


<s> static bool sparc_pic_register_p ( rtx x ) { if ( ! REG_P ( x ) || ! pic_offset_table_rtx ) return false ; if ( x == pic_offset_table_rtx ) return true ; if ( ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ( HARD_REGISTER_P ( x ) || lra_in_progress ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return false ; } </s>

Return true if X is a representation of the PIC register .


<s> static void ix86_pad_short_function ( void ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) { rtx_insn * ret = BB_END ( e -> src ) ; if ( JUMP_P ( ret ) && ANY_RETURN_P ( PATTERN ( ret ) ) ) { int insn_count = ix86_count_insn ( e -> src ) ; if ( insn_count < 4 ) { rtx_insn * insn = ret ; while ( insn && ( ! NOTE_P ( insn ) || NOTE_KIND ( insn ) != NOTE_INSN_EPILOGUE_BEG ) ) insn = PREV_INSN ( insn ) ; if ( ! insn ) insn = ret ; insn_count = 2 * ( 4 - insn_count ) ; emit_insn_before ( gen_nops ( GEN_INT ( insn_count ) ) , insn ) ; } } } } </s>


<s> unsigned SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static inline unsigned long ia64_rse_slot_num ( unsigned long * addr ) { return ( ( ( unsigned long ) addr ) >> 3 ) & 0x3f ; } </s>


<s>
static
void
rs6000_darwin_file_start
(
void
)
{
static
const
struct
{
const
char
*
arg
;
const
char
*
name
;
int
if_set
;
}
mapping
[
]
=
{
{
"ppc64"
,
"ppc64"
,
MASK_64BIT
}
,
{
"970"
,
"ppc970"
,
MASK_PPC_GPOPT
|
MASK_MFCRF
|
MASK_POWERPC64
}
,
{
"power4"
,
"ppc970"
,
0
}
,
{
"G5"
,
"ppc970"
,
0
}
,
{
"7450"
,
"ppc7450"
,
0
}
,
{
"7400"
,
"ppc7400"
,
MASK_ALTIVEC
}
,
{
"G4"
,
"ppc7400"
,
0
}
,
{
"750"
,
"ppc750"
,
0
}
,
{
"740"
,
"ppc750"
,
0
}
,
{
"G3"
,
"ppc750"
,
0
}
,
{
"604e"
,
"ppc604e"
,
0
}
,
{
"604"
,
"ppc604"
,
0
}
,
{
"603e"
,
"ppc603"
,
0
}
,
{
"603"
,
"ppc603"
,
0
}
,
{
"601"
,
"ppc601"
,
0
}
,
{
,
"ppc"
,
0
}
}
;
const
char
*
cpu_id
=
""
;
size_t
i
;
rs6000_file_start
(
)
;
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
rs6000_select
)
;
i
++
)
if
(
rs6000_select
[
i
]
.
set_arch_p
&&
rs6000_select
[
i
]
.
string
&&
rs6000_select
[
i
]
.
string
[
0
]
!=
'\0'
)
cpu_id
=
rs6000_select
[
i
]
.
string
;
i
=
0
;
while
(
mapping
[
i
]
.
arg
!=
&&
strcmp
(
mapping
[
i
]
.
arg
,
cpu_id
)
!=
0
&&
(
mapping
[
i
]
.
if_set
&
target_flags
)
==
0
)
i
++
;
fprintf
(
asm_out_file
,
"\t.machine %s\n"
,
mapping
[
i
]
.
name
)
;
}
</s>

Output a .machine directive for the Darwin assembler , and call the generic start_file routine .


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . RealignStack && ! MFI -> hasVarSizedObjects ( ) ) ; } </s>

True if the stack can be realigned for the target .


<s> int dimode_scalar_chain :: vector_const_cost ( rtx exp ) { gcc_assert ( CONST_INT_P ( exp ) ) ; if ( standard_sse_constant_p ( exp , V2DImode ) ) return COSTS_N_INSNS ( 1 ) ; return ix86_cost -> sse_load [ 1 ] ; } </s>

Return a cost of building a vector costant instead of using a scalar one .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void aarch64_emit_atomic_swap ( machine_mode mode , rtx dst , rtx value , rtx mem , rtx model ) { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_QImode : gen = gen_aarch64_atomic_swpqi ; break ; case E_HImode : gen = gen_aarch64_atomic_swphi ; break ; case E_SImode : gen = gen_aarch64_atomic_swpsi ; break ; case E_DImode : gen = gen_aarch64_atomic_swpdi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , mem , value , model ) ) ; } </s>