<s> void ix86_expand_fp_absneg_operator ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { rtx mask , set , use , clob , dst , src ; bool matching_memory ; bool use_sse = false ; bool vector_mode = VECTOR_MODE_P ( mode ) ; enum machine_mode elt_mode = mode ; if ( vector_mode ) { elt_mode = GET_MODE_INNER ( mode ) ; use_sse = true ; } else if ( TARGET_SSE_MATH ) use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( use_sse ) mask = ix86_build_signbit_mask ( elt_mode , vector_mode , code == ABS ) ; else { mask = const0_rtx ; } dst = operands [ 0 ] ; src = operands [ 1 ] ; matching_memory = false ; if ( MEM_P ( dst ) ) { if ( rtx_equal_p ( dst , src ) ) matching_memory = true ; else dst = gen_reg_rtx ( mode ) ; } if ( MEM_P ( src ) && ! matching_memory ) src = force_reg ( mode , src ) ; if ( vector_mode ) { set = gen_rtx_fmt_ee ( code == NEG ? XOR : AND , mode , src , mask ) ; set = gen_rtx_SET ( VOIDmode , dst , set ) ; emit_insn ( set ) ; } else { set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( VOIDmode , dst , set ) ; use = gen_rtx_USE ( VOIDmode , mask ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 3 , set , use , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Generate code for floating point ABS or NEG .


<s> static reg_class_t xstormy16_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == GENERAL_REGS && MEM_P ( x ) ) return EIGHT_REGS ; return rclass ; } </s>

Worker function for TARGET_PREFERRED_RELOAD_CLASS and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS .


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname , tree fndecl , int caller ) { struct cgraph_local_info * i = NULL ; struct cgraph_node * target = NULL ; memset ( cum , 0 , sizeof ( * cum ) ) ; if ( fndecl ) { target = cgraph_node :: get ( fndecl ) ; if ( target ) { target = target -> function_symbol ( ) ; i = cgraph_node :: local_info ( target -> decl ) ; cum -> call_abi = ix86_function_abi ( target -> decl ) ; } else cum -> call_abi = ix86_function_abi ( fndecl ) ; } else cum -> call_abi = ix86_function_type_abi ( fntype ) ; cum -> caller = caller ; cum -> nregs = ix86_regparm ; if ( TARGET_64BIT ) { cum -> nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; } if ( TARGET_SSE ) { cum -> sse_nregs = SSE_REGPARM_MAX ; if ( TARGET_64BIT ) { cum -> sse_nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_SSE_REGPARM_MAX : X86_64_MS_SSE_REGPARM_MAX ) ; } } if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_avx512f = true ; cum -> warn_avx = true ; cum -> warn_sse = true ; cum -> warn_mmx = true ; if ( i && i -> local && i -> can_change_signature ) fntype = TREE_TYPE ( target -> decl ) ; cum -> stdarg = stdarg_p ( fntype ) ; cum -> maybe_vaarg = ( fntype ? ( ! prototype_p ( fntype ) || stdarg_p ( fntype ) ) : ! libname ) ; cum -> bnd_regno = FIRST_BND_REG ; cum -> bnds_in_bt = 0 ; cum -> force_bnd_pass = 0 ; if ( ! TARGET_64BIT ) { if ( stdarg_p ( fntype ) ) { cum -> nregs = 0 ; cum -> sse_nregs = 0 ; cum -> mmx_nregs = 0 ; cum -> warn_avx512f = false ; cum -> warn_avx = false ; cum -> warn_sse = false ; cum -> warn_mmx = false ; return ; } if ( fntype ) { unsigned int ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { cum -> nregs = 1 ; cum -> fastcall = 1 ; } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) { cum -> nregs = 2 ; cum -> fastcall = 1 ; } else cum -> nregs = ix86_function_regparm ( fntype , fndecl ) ; } cum -> float_in_sse = ix86_function_sseregparm ( fntype , fndecl , true ) ; } } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; ConstPoolId2AddrMap . resize ( AFI -> getNumConstPoolEntries ( ) ) ; JumpTableId2AddrMap . resize ( AFI -> getNumJumpTables ( ) ) ; IsPIC = isPIC ; } </s>

This method must be called before any actual lowering is done .


<s>
int
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
needsStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
if
(
!
IgnoreSPUpdates
&&
!
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
return
getFrameIndexReferenceSP
(
MF
,
FI
,
FrameReg
,
StackSize
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> static void core2i7_first_cycle_multipass_end ( const void * _data ) { const_ix86_first_cycle_multipass_data_t data = ( const_ix86_first_cycle_multipass_data_t ) _data ; ix86_first_cycle_multipass_data_t next_data = ix86_first_cycle_multipass_data ; if ( data != NULL ) { next_data -> ifetch_block_len = data -> ifetch_block_len ; next_data -> ifetch_block_n_insns = data -> ifetch_block_n_insns ; } } </s>

Save the result of multipass lookahead scheduling for the next round .


<s> bool AArch64TargetLowering :: isLegalICmpImmediate ( int64_t Val ) const { if ( Val < 0 ) Val = - Val ; return ( Val & ~ 0xfff ) == 0 || ( Val & ~ 0xfff000 ) == 0 ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> bool nds32_indirect_call_referenced_p ( rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_ICT ) x = XVECEXP ( x , 0 , 0 ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) { tree decl = SYMBOL_REF_DECL ( x ) ; return decl && ( lookup_attribute ( "indirect_call" , DECL_ATTRIBUTES ( decl ) ) != NULL ) ; } return false ; } </s>

Return true X is a indirect call symbol .


<s> HOST_WIDE_INT or1k_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; switch ( from ) { case ARG_POINTER_REGNUM : offset = cfun -> machine -> total_size ; break ; case FRAME_POINTER_REGNUM : offset = cfun -> machine -> args_size + cfun -> machine -> local_vars_size ; break ; default : gcc_unreachable ( ) ; } if ( to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> total_size ; return offset ; } </s>

Helper for defining INITIAL_ELIMINATION_OFFSET . We allow the following eliminiations : FP - > HARD_FP or SP AP - > HARD_FP or SP HARD_FP and AP are the same which is handled below .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'L'
:
O
<<
getDataLayout
(
)
.
getPointerSize
(
)
<<
"("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
->
isDarwin
(
)
)
RegName
=
PPCRegisterInfo
::
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Lanai load / store optimization pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Lanai
"Lanai load / store optimization pass"


<s> bool PPCAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; O << "0(" ; printOperand ( MI , OpNo , O ) ; O << ")" ; return false ; } </s>


<s> static rtx mips_prepare_builtin_target ( enum insn_code icode , unsigned int op , rtx target ) { enum machine_mode mode ; mode = insn_data [ icode ] . operand [ op ] . mode ; if ( target == 0 || ! insn_data [ icode ] . operand [ op ] . predicate ( target , mode ) ) target = gen_reg_rtx ( mode ) ; return target ; } </s>

Return an rtx suitable for output operand OP of instruction ICODE . If TARGET is non-null , try to use it where possible .


<s> bool function_checker :: require_immediate_one_of ( unsigned int rel_argno , HOST_WIDE_INT value0 , HOST_WIDE_INT value1 , HOST_WIDE_INT value2 , HOST_WIDE_INT value3 ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; if ( actual != value0 && actual != value1 && actual != value2 && actual != value3 ) { report_not_one_of ( location , fndecl , argno , actual , value0 , value1 , value2 , value3 ) ; return false ; } return true ; } </s>

Check that argument REL_ARGNO is an integer constant expression that has one of the given values .


<s> static void sparc_solaris_elf_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { if ( HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE ) { solaris_elf_asm_comdat_section ( name , flags , decl ) ; return ; } fprintf ( asm_out_file , "\t.section\t\"%s\"" , name ) ; if ( ! ( flags & SECTION_DEBUG ) ) fputs ( ",#alloc" , asm_out_file ) ; if ( flags & SECTION_WRITE ) fputs ( ",#write" , asm_out_file ) ; if ( flags & SECTION_TLS ) fputs ( ",#tls" , asm_out_file ) ; if ( flags & SECTION_CODE ) fputs ( ",#execinstr" , asm_out_file ) ; if ( flags & SECTION_NOTYPE ) ; else if ( flags & SECTION_BSS ) fputs ( ",#nobits" , asm_out_file ) ; else fputs ( ",#progbits" , asm_out_file ) ; fputc ( '\n' , asm_out_file ) ; } </s>

Solaris implementation of TARGET_ASM_NAMED_SECTION .

sparc "\t.section\t\"%s\"" ",#alloc" ",#write" ",#tls" ",#execinstr" ",#nobits" ",#progbits"


<s> static unsigned parse_field ( const std :: string & field ) { const char * rest = strchr ( field . c_str ( ) , ':' ) ; if ( rest == NULL ) return - 1 ; char * after ; unsigned fint = strtol ( rest + 1 , & after , 16 ) ; if ( after == rest + 1 ) return - 1 ; return fint ; } </s>

Returns the hex integer that is after ' : ' for the FIELD . Returns -1 is returned if there was problem parsing the integer .


<s> void neon_pairwise_reduce ( rtx op0 , rtx op1 , machine_mode mode , rtx ( * reduc ) ( rtx , rtx , rtx ) ) { machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int i , parts = GET_MODE_SIZE ( mode ) / GET_MODE_SIZE ( inner ) ; rtx tmpsum = op1 ; for ( i = parts / 2 ; i >= 1 ; i /= 2 ) { rtx dest = ( i == 1 ) ? op0 : gen_reg_rtx ( mode ) ; emit_insn ( reduc ( dest , tmpsum , tmpsum ) ) ; tmpsum = dest ; } } </s>

Output a sequence of pairwise operations to implement a reduction . NOTE : We do `` too much work '' here , because pairwise operations work on two registers-worth of operands in one go . Unfortunately we ca n't exploit those extra calculations to do the full operation in fewer steps , I do n't think . Although all vector elements of the result but the first are ignored , we actually calculate the same result in each of the elements . An alternative such as initially loading a vector with zero to use as each of the second operands would use up an additional register and take an extra instruction , for no particular gain .


<s> MVT getPointerTy ( const DataLayout & DL , uint32_t AS = 0 ) const override { return MVT :: getIntegerVT ( 64 ) ; } </s>

Return the pointer type for the given address space , defaults to the pointer type from the data layout .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AssertZext : return performAssertZextCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUB : return performSUBCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::AssertZext ISD::SHL ISD::SUB


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return AArch64 :: X1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> static rtx mips_legitimize_tls_address ( rtx loc ) { rtx dest , insn , v0 , tp , tmp1 , tmp2 , eqv , offset ; enum tls_model model ; model = SYMBOL_REF_TLS_MODEL ( loc ) ; if ( ! TARGET_ABICALLS ) model = TLS_MODEL_LOCAL_EXEC ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; offset = mips_unspec_address ( loc , SYMBOL_DTPREL ) ; if ( mips_split_p [ SYMBOL_DTPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , 0 , 0 , OPTAB_DIRECT ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = mips_get_tp ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = mips_unspec_address ( loc , SYMBOL_GOTTPREL ) ; if ( Pmode == DImode ) emit_insn ( gen_load_gotdi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; else emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp1 = mips_get_tp ( ) ; offset = mips_unspec_address ( loc , SYMBOL_TPREL ) ; if ( mips_split_p [ SYMBOL_TPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_TPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , 0 , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread local SYMBOL_REF . The return value will be a valid address and move_operand ( either a REG or a LO_SUM ) .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static bool load_insn_p ( rtx_insn * insn ) { if ( GET_CODE ( PATTERN ( insn ) ) != SET ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : case TYPE_SLOAD : case TYPE_FPLOAD : return true ; default : return false ; } } </s>


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { if ( ! ( Subtarget -> hasFMA ( ) || Subtarget -> hasFMA4 ( ) || Subtarget -> hasAVX512 ( ) ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> int vspltis_shifted ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i , j ; unsigned nunits ; unsigned mask ; HOST_WIDE_INT val ; if ( mode != V16QImode && mode != V8HImode && mode != V4SImode ) return false ; if ( ! can_create_pseudo_p ( ) || ( cfun -> curr_properties & PROP_rtl_split_insns ) ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? 0 : nunits - 1 ) ; if ( EASY_VECTOR_15 ( val ) ) ; else if ( EASY_VECTOR_MSB ( val , inner ) ) ; else return 0 ; for ( i = 1 ; i < nunits ; ++ i ) { unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i ; HOST_WIDE_INT elt_val = const_vector_elt_as_int ( op , elt ) ; if ( val != elt_val ) { if ( elt_val == 0 ) { for ( j = i + 1 ; j < nunits ; ++ j ) { unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j ; if ( const_vector_elt_as_int ( op , elt2 ) != 0 ) return 0 ; } return ( nunits - i ) * GET_MODE_SIZE ( inner ) ; } else if ( ( elt_val & mask ) == mask ) { for ( j = i + 1 ; j < nunits ; ++ j ) { unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j ; if ( ( const_vector_elt_as_int ( op , elt2 ) & mask ) != mask ) return 0 ; } return - ( ( nunits - i ) * GET_MODE_SIZE ( inner ) ) ; } else return 0 ; } } return 0 ; } </s>

Like vsplitis_constant , but allow the value to be shifted left with a VSLDOI instruction , filling in the bottom elements with 0 or -1 . Return 0 if the constant can not be generated with VSLDOI . Return positive for the number of zeroes to shift in , or negative for the number of 0xff bytes to shift in . OP is a CONST_VECTOR .


<s> void AArch64O0PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::VASTART ISD::FCOPYSIGN ISD::FRAMEADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE


<s> int X86TTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static tree def_builtin_const ( const char * name , enum insn_code icode , enum sparc_builtins code , tree type ) { tree t = def_builtin ( name , icode , code , type ) ; if ( t ) TREE_READONLY ( t ) = 1 ; return t ; } </s>

Likewise , but also marks the function as `` const '' .


<s> unsigned int rs6000_special_adjust_field_align ( tree type , unsigned int computed ) { if ( computed <= 32 ) return computed ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; while ( AGGREGATE_TYPE_P ( type ) ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return computed ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node && ( TYPE_MODE ( type ) == DFmode || TYPE_MODE ( type ) == DCmode ) ) computed = MIN ( computed , 32 ) ; return computed ; } </s>

AIX word-aligns FP doubles but doubleword-aligns 64-bit ints .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override { if ( ! VT . isScalableVector ( ) && VT . getVectorNumElements ( ) != 1 && VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static void initialize_aarch64_tls_size ( struct gcc_options * opts ) { if ( aarch64_tls_size == 0 ) aarch64_tls_size = 24 ; switch ( opts -> x_aarch64_cmodel_var ) { case AARCH64_CMODEL_TINY : if ( aarch64_tls_size > 24 ) aarch64_tls_size = 24 ; break ; case AARCH64_CMODEL_SMALL : if ( aarch64_tls_size > 32 ) aarch64_tls_size = 32 ; break ; case AARCH64_CMODEL_LARGE : if ( aarch64_tls_size > 48 ) aarch64_tls_size = 48 ; break ; default : gcc_unreachable ( ) ; } return ; } </s>

A checking mechanism for the implementation of the tls size .


<s> char * aarch64_output_sve_inc_dec_immediate ( const char * operands , rtx x ) { int factor ; unsigned int nelts_per_vq ; if ( ! aarch64_sve_inc_dec_immediate_p ( x , & factor , & nelts_per_vq ) ) gcc_unreachable ( ) ; if ( factor < 0 ) return aarch64_output_sve_cnt_immediate ( "dec" , operands , - factor , nelts_per_vq ) ; else return aarch64_output_sve_cnt_immediate ( "inc" , operands , factor , nelts_per_vq ) ; } </s>

Return the asm template for an SVE vector INC or DEC instruction . OPERANDS gives the operands before the vector count and X is the value of the vector count operand itself .


<s> bool X86TargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { bool ShouldPrint = false ; if ( OptLevel != CodeGenOpt :: None && ( Subtarget . hasSSE2 ( ) || Subtarget . hasAVX ( ) ) ) { PM . add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned getNumFixupKinds ( ) const override { return LEG :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static bool aarch64_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V1DFmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static int loongarch_issue_rate ( void ) { if ( ( unsigned long ) LARCH_ACTUAL_TUNE < N_TUNE_TYPES ) return loongarch_cpu_issue_rate [ LARCH_ACTUAL_TUNE ] ; else return 1 ; } </s>

Return the number of instructions that can be issued per cycle .


<s>
int
AArch64LoadStoreOpt
::
getMemSize
(
MachineInstr
*
MemMI
)
{
switch
(
MemMI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown size!"
)
;
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
return
4
;
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
return
8
;
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
return
16
;
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
return
4
;
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
return
8
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
return
16
;
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
return
4
;
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
return
8
;
}
}
</s>

Returns the size in bytes of the memory access .


<s> bool FPGATTIImpl :: isTruncateFree ( Type * Ty1 , Type * Ty2 ) { if ( ! Ty1 -> isIntegerTy ( ) || ! Ty2 -> isIntegerTy ( ) ) return false ; unsigned NumBits1 = Ty1 -> getPrimitiveSizeInBits ( ) ; unsigned NumBits2 = Ty2 -> getPrimitiveSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> void xstormy16_expand_andqi3 ( rtx * operands ) { rtx in , out , outsub , val ; out = operands [ 0 ] ; in = operands [ 1 ] ; val = operands [ 2 ] ; if ( xstormy16_onebit_clr_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_andqi3_internal ( out , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; return ; } if ( ! REG_P ( in ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! REG_P ( val ) && ! CONST_INT_P ( val ) ) val = copy_to_mode_reg ( QImode , val ) ; if ( ! REG_P ( out ) ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , 0 ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , 0 ) ; if ( ! CONST_INT_P ( val ) ) val = simplify_gen_subreg ( HImode , val , QImode , 0 ) ; emit_insn ( gen_andhi3 ( outsub , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; } </s>


<s> unsigned ARMFastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return 0 ; MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return 0 ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned Opc = isThumb2 ? ARM :: t2ADDri : ARM :: ADDri ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; Register ResultReg = createResultReg ( RC ) ; ResultReg = constrainOperandRegClass ( TII . get ( Opc ) , ResultReg , 0 ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( 0 ) ) ; return ResultReg ; } return 0 ; } </s>

Emit an alloca address in a register using target-specific logic .


<s> static void ix86_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( TARGET_AVX512F && ! TARGET_PREFER_AVX256 ) { sizes -> safe_push ( 64 ) ; sizes -> safe_push ( 32 ) ; sizes -> safe_push ( 16 ) ; } else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) { sizes -> safe_push ( 32 ) ; sizes -> safe_push ( 16 ) ; } } </s>

If AVX is enabled then try vectorizing with both 256bit and 128bit vectors . If AVX512F is enabled then try vectorizing with 512bit , 256bit and 128bit vectors .


<s> static bool nds32_pic_tls_group ( rtx_insn * def_insn , enum nds32_relax_insn_type relax_type , int sym_type ) { df_ref def_record ; df_link * link ; rtx_insn * use_insn = NULL ; rtx pat , new_pat ; def_record = DF_INSN_DEFS ( def_insn ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( ! dominated_by_p ( CDI_DOMINATORS , BLOCK_FOR_INSN ( use_insn ) , BLOCK_FOR_INSN ( def_insn ) ) ) return FALSE ; if ( ! active_insn_p ( use_insn ) ) return FALSE ; switch ( relax_type ) { case RELAX_ORI : if ( ( sym_type == UNSPEC_TLSLE || sym_type == UNSPEC_GOTOFF ) && ( recog_memoized ( use_insn ) == CODE_FOR_addsi3 ) ) { pat = XEXP ( PATTERN ( use_insn ) , 1 ) ; new_pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( 2 , XEXP ( pat , 0 ) , XEXP ( pat , 1 ) ) , UNSPEC_ADD32 ) ; validate_replace_rtx ( pat , new_pat , use_insn ) ; nds32_group_infos . safe_push ( use_insn ) ; } else if ( nds32_plus_reg_load_store_p ( use_insn ) && ! nds32_sp_base_or_plus_load_store_p ( use_insn ) ) nds32_group_infos . safe_push ( use_insn ) ; else return FALSE ; break ; default : return FALSE ; } } return TRUE ; } </s>

Group the PIC and TLS relax candidate instructions for linker .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> unsigned getMaxSupportedInterleaveFactor ( ) const override { return 4 ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < ReachingDefAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool sh_legitimate_index_p ( machine_mode mode , rtx op , bool consider_sh2a , bool allow_zero ) { if ( ! CONST_INT_P ( op ) ) return false ; if ( TARGET_SHMEDIA ) { int size ; if ( mode == VOIDmode ) return satisfies_constraint_I06 ( op ) ; size = GET_MODE_SIZE ( mode ) ; return ( ! ( INTVAL ( op ) & ( size - 1 ) ) && INTVAL ( op ) >= - 512 * size && INTVAL ( op ) < 512 * size ) ; } else { const HOST_WIDE_INT offset = INTVAL ( op ) ; const int max_disp = sh_max_mov_insn_displacement ( mode , consider_sh2a ) ; const int align_mask = mov_insn_alignment_mask ( mode , consider_sh2a ) ; if ( ! allow_zero && max_disp < 1 ) return false ; return offset >= 0 && offset <= max_disp && ( offset & align_mask ) == 0 ; } } </s>

Return TRUE for a valid displacement for the REG+disp addressing with MODE .


<s> static bool classof ( const AArch64MCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static bool rs6000_secondary_memory_needed ( enum reg_class from_class , enum reg_class to_class , machine_mode mode ) { enum rs6000_reg_type from_type , to_type ; bool altivec_p = ( ( from_class == ALTIVEC_REGS ) || ( to_class == ALTIVEC_REGS ) ) ; from_type = reg_class_to_reg_type [ ( int ) from_class ] ; to_type = reg_class_to_reg_type [ ( int ) to_class ] ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , ( secondary_reload_info * ) 0 , altivec_p ) ) return false ; if ( IS_FP_VECT_REG_TYPE ( from_type ) || IS_FP_VECT_REG_TYPE ( to_type ) ) return true ; return false ; } </s>

If we are copying between FP or AltiVec registers and anything else , we need a memory location . The exception is when we are targeting ppc64 and the move to/from fpr to gpr instructions are available . Also , under VSX , you can copy vector registers from the FP register set to the Altivec register set and vice versa .


<s> static machine_mode ix86_secondary_memory_needed_mode ( machine_mode mode ) { if ( GET_MODE_BITSIZE ( mode ) < 32 && INTEGRAL_MODE_P ( mode ) ) return mode_for_size ( 32 , GET_MODE_CLASS ( mode ) , 0 ) . require ( ) ; return mode ; } </s>

Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE . get_secondary_mem widens integral modes to BITS_PER_WORD . There is no need to emit full 64 bit move on 64 bit targets for integral modes that can be moved using 32 bit move .


<s>
SDValue
SparcTargetLowering
::
LowerReturn
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Sparc32
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SPISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


"X32 does not support %<ms_abi%> attribute"

Returns value SYSV_ABI , MS_ABI dependent on fntype , specifying the call abi used .


<s> int num_insns_constant_wide ( HOST_WIDE_INT value ) { if ( ( ( unsigned HOST_WIDE_INT ) value + 0x8000 ) < 0x10000 ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_wide ( low ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } else return 2 ; } </s>

Return the number of instructions it takes to form a constant in an integer register .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86AvoidStoreForwardingBlocks ( ) ) ; } addPass ( createX86SpeculativeLoadHardeningPass ( ) ) ; addPass ( createX86FlagsCopyLoweringPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PreTileConfigPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> int64_t getOffset ( ) { return Offset ; } </s>

Get the offest of a string in the string table .


<s> int rs6000_memory_move_cost ( enum machine_mode mode , enum reg_class class , int in ATTRIBUTE_UNUSED ) { if ( reg_classes_intersect_p ( class , GENERAL_REGS ) ) return 4 * hard_regno_nregs [ 0 ] [ mode ] ; else if ( reg_classes_intersect_p ( class , FLOAT_REGS ) ) return 4 * hard_regno_nregs [ 32 ] [ mode ] ; else if ( reg_classes_intersect_p ( class , ALTIVEC_REGS ) ) return 4 * hard_regno_nregs [ FIRST_ALTIVEC_REGNO ] [ mode ] ; else return 4 + rs6000_register_move_cost ( mode , class , GENERAL_REGS ) ; } </s>

A C expressions returning the cost of moving data of MODE from a register to or from memory .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function * F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = 6 ; else if ( F -> optForMinSize ( ) ) OptimizationGoal = 4 ; else if ( F -> optForSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer -> EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCAIXAsmPrinter :: doFinalization ( Module & M ) { if ( ! MAI -> usesDwarfFileAndLocDirectives ( ) && MMI -> hasDebugInfo ( ) ) OutStreamer -> doFinalizationAtSectionEnd ( OutStreamer -> getContext ( ) . getObjectFileInfo ( ) -> getTextSection ( ) ) ; for ( MCSymbol * Sym : ExtSymSDNodeSymbols ) OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Extern ) ; return PPCAsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static vector_costs * ix86_vectorize_create_costs ( vec_info * vinfo , bool costing_for_scalar ) { return new ix86_vector_costs ( vinfo , costing_for_scalar ) ; } </s>


"value of -mfixed-range must have form REG1-REG2"

Parse the -mfixed-range= option string .


"\t.section .directive, \"SM\", @progbits, 1\n"

Output the start of the assembler file .


<s> static machine_mode sparc_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree , int ) { if ( type && POINTER_TYPE_P ( type ) ) { * punsignedp = POINTERS_EXTEND_UNSIGNED ; return Pmode ; } if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) return word_mode ; return mode ; } </s>

Handle promotion of pointer and integer arguments .


<s>
SDNode
*
FISCDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
DEBUG
(
errs
(
)
<<
">>>>>> Selecting Node: "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
LOAD
:
return
SelectIndexedLoad
(
N
)
;
case
ISD
::
STORE
:
return
SelectIndexedStore
(
N
)
;
case
ISD
::
FrameIndex
:
return
SelectFrameIndex
(
N
)
;
case
ISD
::
Constant
:
return
ConstantToRegisterExpand
(
N
,
SDValue
(
N
,
0
)
)
.
getNode
(
)
;
case
ISD
::
ADD
:
if
(
N
->
getOperand
(
0
)
.
getOpcode
(
)
==
ISD
::
TargetGlobalAddress
)
return
SelectTargetGlobalAddressforADD
(
N
,
N
->
getOperand
(
0
)
.
getNode
(
)
)
;
break
;
case
FISCISD
::
CMP
:
return
SelectCompare
(
N
)
;
case
ISD
::
BR_CC
:
return
SelectConditionalBranch
(
N
)
;
case
ISD
::
CopyToReg
:
if
(
N
->
getOperand
(
2
)
.
getOpcode
(
)
==
ISD
::
TargetGlobalAddress
)
{
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
N
->
getOperand
(
2
)
)
;
const
GlobalValue
*
GV
=
GA
->
getGlobal
(
)
;
unsigned
char
TargetFlags
=
FISCII
::
MO_MOVRZ
;
if
(
GV
->
getValueID
(
)
==
Value
::
FunctionVal
)
TargetFlags
=
FISCII
::
MO_Q1
;
SDValue
TargetGlobalAddr
=
CurDAG
->
getTargetGlobalAddress
(
GV
,
SDLoc
(
N
)
,
MVT
::
i64
,
GA
->
getOffset
(
)
,
TargetFlags
)
;
MachineSDNode
*
Move
=
CurDAG
->
getMachineNode
(
FISC
::
MOVRZ
,
N
,
MVT
::
i64
,
TargetGlobalAddr
,
CurDAG
->
getTargetConstant
(
0
,
N
,
MVT
::
i64
)
)
;
CurDAG
->
ReplaceAllUsesWith
(
N
->
getOperand
(
2
)
,
SDValue
(
Move
,
0
)
)
;
}
break
;
case
FISCISD
::
CALL
:
{
unsigned
int
operand2Opc
=
N
->
getOperand
(
1
)
.
getOpcode
(
)
;
if
(
operand2Opc
==
ISD
::
LOAD
||
operand2Opc
==
ISD
::
CopyFromReg
)
{
return
SelectCallFunctionPointer
(
N
)
;
}
break
;
}
case
ISD
::
SRL
:
return
SelectShifts
(
N
)
;
case
ISD
::
MULHU
:
case
ISD
::
MULHS
:
return
SelectMUL
(
N
)
;
}
return
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
override
{
assert
(
0
&&
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .

Sparc
0
"relaxInstruction() unimplemented"


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> bool quad_address_p ( rtx addr , machine_mode mode , bool strict ) { rtx op0 , op1 ; if ( GET_MODE_SIZE ( mode ) != 16 ) return false ; if ( legitimate_indirect_address_p ( addr , strict ) ) return true ; if ( VECTOR_MODE_P ( mode ) && ! mode_supports_dq_form ( mode ) ) return false ; if ( GET_CODE ( addr ) != PLUS ) return false ; op0 = XEXP ( addr , 0 ) ; if ( ! REG_P ( op0 ) || ! INT_REG_OK_FOR_BASE_P ( op0 , strict ) ) return false ; op1 = XEXP ( addr , 1 ) ; if ( ! CONST_INT_P ( op1 ) ) return false ; return quad_address_offset_p ( INTVAL ( op1 ) ) ; } </s>

Return true if the ADDR is an acceptable address for a quad memory operation of mode MODE ( either LQ/STQ for general purpose registers , or LXV/STXV for vector registers under ISA 3.0 . GPR_P is true if this address is intended for LQ/STQ . If it is false , the address is intended for the ISA 3.0 LXV/STXV instruction .


<s> unsigned OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Mips :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 0 ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> bool AArch64PassConfig :: addLegalizeMachineIR ( ) { addPass ( new MachineLegalizePass ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool SystemZAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && * ExtraCode == 'n' ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return true ; OS << - int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; } else { SystemZMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; SystemZInstPrinter :: printOperand ( MO , MAI , OS ) ; } return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static rtx nds32_read_argument ( tree exp , unsigned int index ) { return expand_normal ( CALL_EXPR_ARG ( exp , index ) ) ; } </s>

Read the requested argument from the EXP given by INDEX . Return the value as an rtx .


<s> bool SystemZCopyPhysRegs :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; MRI = & F . getRegInfo ( ) ; bool Modified = false ; for ( auto & MBB : F ) Modified |= visitMBB ( MBB ) ; return Modified ; } </s>


"iwmmxt requires an AAPCS compatible ABI for proper operation"

"iwmmxt abi requires an iwmmxt capable cpu"

"target CPU does not support interworking"

"AAPCS does not support %<-mcaller-super-interworking%>"

"AAPCS does not support %<-mcallee-super-interworking%>"

"target CPU does not support ARMv8-M Security Extensions"

"ARMv8-M Security Extensions incompatible with selected FPU"

"%<-mfloat-abi=hard%>: selected architecture lacks an FPU"

Perform some validation between the desired architecture and the rest of the options .


<s> static int arm_save_coproc_regs ( void ) { int saved_size = 0 ; unsigned reg ; unsigned start_reg ; rtx insn ; if ( TARGET_REALLY_IWMMXT ) for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( reg_needs_saving_p ( reg ) ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG ( V2SImode , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; saved_size += 8 ; } if ( TARGET_VFP_BASE ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += 2 ) { if ( ! reg_needs_saving_p ( reg ) && ! reg_needs_saving_p ( reg + 1 ) ) { if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; start_reg = reg + 2 ; } } if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; } return saved_size ; } </s>

Emit RTL to save coprocessor registers on function entry . Returns the number of bytes pushed .


<s> bool ARMTTIImpl :: isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == 32 && ( ! Alignment || * Alignment >= 4 ) ) || ( EltWidth == 16 && ( ! Alignment || * Alignment >= 2 ) ) || EltWidth == 8 ) ; } </s>

Return true if the target supports masked gather .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned AArch64InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: STRWui : case AArch64 :: STRXui : case AArch64 :: STRBui : case AArch64 :: STRHui : case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: LDR_PXI : case AArch64 :: STR_PXI : if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void MipsAsmPrinter :: emitBasicBlockEnd ( const MachineBasicBlock & MBB ) { AsmPrinter :: emitBasicBlockEnd ( MBB ) ; MipsTargetStreamer & TS = getTargetStreamer ( ) ; if ( MBB . empty ( ) ) TS . emitDirectiveInsn ( ) ; } </s>

Targets can override this to emit stuff at the end of a basic block .


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool PPCTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : case Intrinsic :: ppc_vsx_lxvd2x_be : case Intrinsic :: ppc_vsx_lxvw4x_be : case Intrinsic :: ppc_vsx_lxvl : case Intrinsic :: ppc_vsx_lxvll : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_lvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_lvewx : VT = MVT :: i32 ; break ; case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvd2x_be : VT = MVT :: v2f64 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = Align ( 1 ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : case Intrinsic :: ppc_vsx_stxvd2x_be : case Intrinsic :: ppc_vsx_stxvw4x_be : case Intrinsic :: ppc_vsx_stxvl : case Intrinsic :: ppc_vsx_stxvll : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_stvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_stvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_stvewx : VT = MVT :: i32 ; break ; case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvd2x_be : VT = MVT :: v2f64 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = Align ( 1 ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static char * detect_caches_linux ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; const char * platform ; platform = elf_platform ( ) ; if ( platform != NULL ) { l1_line = 128 ; if ( platform [ 5 ] == '6' ) l1_sizekb = 64 ; else l1_sizekb = 32 ; } else { l1_line = elf_dcachebsize ( ) ; l1_sizekb = 32 ; } l1_assoc = 0 ; l2_sizekb = 512 ; return describe_cache ( l1_sizekb , l1_line , l1_assoc , l2_sizekb ) ; } </s>

Returns the description of caches on Linux .


<s> bool SystemZMCAsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind ( ) >= FirstLiteralRelocationKind ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , MaybeAlign StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : X86GenSubtargetInfo ( TT , CPU , FS ) , PICStyle ( PICStyles :: Style :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: Style :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: Style :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: Style :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static machine_mode rx_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree funtype ATTRIBUTE_UNUSED , int for_return ) { if ( for_return != 1 || GET_MODE_SIZE ( mode ) >= 4 || COMPLEX_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) || VECTOR_TYPE_P ( type ) || GET_MODE_SIZE ( mode ) < 1 ) return mode ; return SImode ; } </s>

TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with regard to function returns as does TARGET_FUNCTION_VALUE .


<s> static reg_class_t sh_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == NO_REGS && TARGET_SHMEDIA && ( CONST_DOUBLE_P ( x ) || GET_CODE ( x ) == SYMBOL_REF || PIC_ADDR_P ( x ) ) ) return GENERAL_REGS ; return rclass ; } </s>


<s> static int ix86_fp_comparison_arithmetics_cost ( enum rtx_code code ) { if ( ! TARGET_IEEE_FP ) return 4 ; switch ( code ) { case UNLE : case UNLT : case LTGT : case GT : case GE : case UNORDERED : case ORDERED : case UNEQ : return 4 ; break ; case LT : case NE : case EQ : case UNGE : return 5 ; break ; case LE : case UNGT : return 6 ; break ; default : gcc_unreachable ( ) ; } } </s>

Return cost of comparison done fcom + arithmetics operations on AX . All following functions do use number of instructions as a cost metrics . In future this should be tweaked to compute bytes for optimize_size and take into account performance of various instructions on various CPUs .


<s> CCAssignFn * AArch64TargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { return CC == CallingConv :: WebKit_JS ? RetCC_AArch64_WebKit_JS : RetCC_AArch64_AAPCS ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
mf
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( & getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloat ( getMipsTargetMachine ( ) ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> static bool has_immediate ( rtx insn ) { int num_imm_operand ; int num_imm32_operand ; int num_imm64_operand ; if ( insn ) return get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; return false ; } </s>

This function indicates if an operand of an instruction is an immediate .


<s> static bool is_cracked_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_NO ) || ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_NO && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( type == TYPE_STORE && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( ( type == TYPE_FPLOAD || type == TYPE_FPSTORE ) && get_attr_update ( insn ) == UPDATE_YES ) || type == TYPE_DELAYED_CR || ( type == TYPE_EXTS && get_attr_dot ( insn ) == DOT_YES ) || ( type == TYPE_SHIFT && get_attr_dot ( insn ) == DOT_YES && get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) || ( type == TYPE_MUL && get_attr_dot ( insn ) == DOT_YES ) || type == TYPE_DIV || ( type == TYPE_INSERT && get_attr_size ( insn ) == SIZE_32 ) ) return true ; } return false ; } </s>

The function returns true if INSN is cracked into 2 instructions by the processor ( and therefore occupies 2 issue slots ) .


<s> static struct aarch64_arch_driver_info * get_arch_from_id ( const char * id ) { unsigned int i = 0 ; for ( i = 0 ; aarch64_arches [ i ] . id != NULL ; i ++ ) { if ( strcmp ( id , aarch64_arches [ i ] . id ) == 0 ) return & aarch64_arches [ i ] ; } return NULL ; } </s>

Return an aarch64_arch_driver_info for the architecture described by ID , or NULL if ID describes something we do n't know about .


<s> static bool sh_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( 1 && ( ! TARGET_SHCOMPACT || crtl -> args . info . stack_regs == 0 ) && ! sh_cfun_interrupt_handler_p ( ) && ( ! flag_pic || ( decl && ! TREE_PUBLIC ( decl ) ) || ( decl && DECL_VISIBILITY ( decl ) != VISIBILITY_DEFAULT ) ) ) ; } </s>

If PIC , we can not make sibling calls to global functions because the PLT requires r12 to be live .


<s> static void compute_zdepdi_operands ( unsigned HOST_WIDE_INT imm , unsigned * op ) { int lsb , len , maxlen ; maxlen = MIN ( HOST_BITS_PER_WIDE_INT , 64 ) ; for ( lsb = 0 ; lsb < maxlen ; lsb ++ ) { if ( ( imm & 1 ) != 0 ) break ; imm >>= 1 ; } if ( ( imm & 0x10 ) == 0 ) len = ( lsb <= maxlen - 4 ) ? 4 : maxlen - lsb ; else { for ( len = 5 ; len < maxlen - lsb ; len ++ ) { if ( ( imm & ( ( unsigned HOST_WIDE_INT ) 1 << len ) ) == 0 ) break ; } if ( HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb ) len += 32 ; imm = ( imm & 0xf ) - 0x10 ; } op [ 0 ] = imm ; op [ 1 ] = 63 - lsb ; op [ 2 ] = len ; } </s>

Compute position ( in OP [ 1 ] ) and width ( in OP [ 2 ] ) useful for copying IMM to a register using the depdi , z instructions . Store the immediate value to insert in OP [ 0 ] .


<s> bool ARMBaseRegisterInfo :: hasFP ( const MachineFunction & MF ) const { if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
CSKYAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
Res
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
LLVM_DEBUG
(
Inst
.
dump
(
)
)
;
llvm_unreachable
(
"Opcode not expected!"
)
;
case
CSKY
::
LRW16
:
Res
.
setOpcode
(
CSKY
::
LRW32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
BR16
:
Res
.
setOpcode
(
CSKY
::
BR32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
case
CSKY
::
JBSR32
:
Res
.
setOpcode
(
CSKY
::
JSRI32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBR32
:
Res
.
setOpcode
(
CSKY
::
JMPI32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBT32
:
case
CSKY
::
JBF32
:
Res
.
setOpcode
(
Inst
.
getOpcode
(
)
==
CSKY
::
JBT32
CSKY
::
JBT_E
:
CSKY
::
JBF_E
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
2
)
)
;
break
;
case
CSKY
::
JBR16
:
Res
.
setOpcode
(
CSKY
::
JBR32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBT16
:
case
CSKY
::
JBF16
:
unsigned
opcode
;
if
(
STI
.
getFeatureBits
(
)
[
CSKY
::
HasE2
]
)
opcode
=
Inst
.
getOpcode
(
)
==
CSKY
::
JBT16
CSKY
::
JBT32
:
CSKY
::
JBF32
;
else
opcode
=
Inst
.
getOpcode
(
)
==
CSKY
::
JBT16
CSKY
::
JBT_E
:
CSKY
::
JBF_E
;
Res
.
setOpcode
(
opcode
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
2
)
)
;
break
;
}
Inst
=
std
::
move
(
Res
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { auto PTy = cast < PointerType > ( LI -> getPointerOperand ( ) -> getType ( ) ) ; return needsCmpXchgNb ( PTy -> getElementType ( ) ) ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> bool ARMTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static bool nds32_have_prologue_p ( void ) { int i ; for ( i = 0 ; i < 28 ; i ++ ) if ( NDS32_REQUIRED_CALLEE_SAVED_P ( i ) ) return true ; return ( flag_pic || NDS32_REQUIRED_CALLEE_SAVED_P ( FP_REGNUM ) || NDS32_REQUIRED_CALLEE_SAVED_P ( LP_REGNUM ) ) ; } </s>

A helper function to check if this function should contain prologue .


<s> static reg_class_t aarch64_ira_change_pseudo_allocno_class ( int regno , reg_class_t allocno_class , reg_class_t best_class ) { machine_mode mode ; if ( allocno_class != ALL_REGS ) return allocno_class ; if ( best_class != ALL_REGS ) return best_class ; mode = PSEUDO_REGNO_MODE ( regno ) ; return FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ? FP_REGS : GENERAL_REGS ; } </s>

Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS . The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have the same cost even if ALL_REGS has a much larger cost . ALL_REGS is also used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory cost ( in this case the best class is the lowest cost one ) . Using ALL_REGS irrespectively of its cost results in bad allocations with many redundant int < - > FP moves which are expensive on various cores . To avoid this we do n't allow ALL_REGS as the allocno class , but force a decision between FP_REGS and GENERAL_REGS . We use the allocno class if it is n't ALL_REGS . Similarly , use the best class if it is n't ALL_REGS . Otherwise set the allocno class depending on the mode . The result of this is that it is no longer inefficient to have a higher memory move cost than the register move cost .


<s> static int rs6000_use_sched_lookahead_guard ( rtx_insn * insn , int ready_index ) { if ( ready_index == 0 ) return 0 ; if ( rs6000_cpu_attr != CPU_CELL ) return 0 ; gcc_assert ( insn != NULL_RTX && INSN_P ( insn ) ) ; if ( ! reload_completed || is_nonpipeline_insn ( insn ) || is_microcoded_insn ( insn ) ) return 1 ; return 0 ; } </s>

We are choosing insn from the ready queue . Return zero if INSN can be chosen .


<s> static bool sparc_use_pseudo_pic_reg ( void ) { return ! TARGET_VXWORKS_RTP && flag_pic ; } </s>


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void AArch64CondBrTuning :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> std :: pair < unsigned , unsigned > LanaiInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s>
unsigned
MipsOutgoingValueHandler
::
assignCustomValue
(
CallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
,
std
::
function
<
void
(
)
>
*
Thunk
)
{
const
CCValAssign
&
VALo
=
VAs
[
0
]
;
const
CCValAssign
&
VAHi
=
VAs
[
1
]
;
assert
(
VALo
.
getLocVT
(
)
==
MVT
::
i32
&&
VAHi
.
getLocVT
(
)
==
MVT
::
i32
&&
VALo
.
getValVT
(
)
==
MVT
::
f64
&&
VAHi
.
getValVT
(
)
==
MVT
::
f64
&&
"unexpected custom value"
)
;
auto
Unmerge
=
MIRBuilder
.
buildUnmerge
(
{
LLT
::
scalar
(
32
)
,
LLT
::
scalar
(
32
)
}
,
Arg
.
Regs
[
0
]
)
;
Register
Lo
=
Unmerge
.
getReg
(
0
)
;
Register
Hi
=
Unmerge
.
getReg
(
1
)
;
Arg
.
OrigRegs
.
assign
(
Arg
.
Regs
.
begin
(
)
,
Arg
.
Regs
.
end
(
)
)
;
Arg
.
Regs
=
{
Lo
,
Hi
}
;
if
(
!
STI
.
isLittle
(
)
)
std
::
swap
(
Lo
,
Hi
)
;
if
(
Thunk
)
{
*
Thunk
=
[
=
]
(
)
{
MIRBuilder
.
buildCopy
(
VALo
.
getLocReg
(
)
,
Lo
)
;
MIRBuilder
.
buildCopy
(
VAHi
.
getLocReg
(
)
,
Hi
)
;
}
;
return
2
;
}
MIRBuilder
.
buildCopy
(
VALo
.
getLocReg
(
)
,
Lo
)
;
MIRBuilder
.
buildCopy
(
VAHi
.
getLocReg
(
)
,
Hi
)
;
return
2
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> bool AArch64TargetLowering :: isProfitableToHoist ( Instruction * I ) const { if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( I -> getNumUses ( ) != 1 ) return true ; Instruction * User = I -> user_back ( ) ; if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const DataLayout & DL = I -> getModule ( ) -> getDataLayout ( ) ; EVT VT = getValueType ( DL , User -> getOperand ( 0 ) -> getType ( ) ) ; return ! ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( ISD :: FMA , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) ; } </s>

Return true if it is profitable to hoist instruction in the then/else to before if .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FP_TO_SINT ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::SELECT ISD::SETCC ISD::VASTART


<s> static bool isConditionalBranch ( unsigned Opc ) { switch ( Opc ) { default : return false ; case ARM64 :: TBZ : case ARM64 :: TBNZ : case ARM64 :: CBZW : case ARM64 :: CBNZW : case ARM64 :: CBZX : case ARM64 :: CBNZX : case ARM64 :: Bcc : return true ; } } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> static bool classof ( const ARMConstantPoolValue * APV ) { return APV -> isGlobalValue ( ) || APV -> isBlockAddress ( ) || APV -> isLSDA ( ) || APV -> isPromotedGlobal ( ) ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s>
SDValue
XNCMTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
doesNotRet
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

XNCM
XNCM
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Constant Islands"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool ix86_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return SUBTARGET_RETURN_IN_MEMORY ( type , fntype ) ; const machine_mode mode = type_natural_mode ( type , NULL , true ) ; HOST_WIDE_INT size ; if ( POINTER_BOUNDS_TYPE_P ( type ) ) return false ; if ( TARGET_64BIT ) { if ( ix86_function_type_abi ( fntype ) == MS_ABI ) { size = int_size_in_bytes ( type ) ; if ( ( ! type || VECTOR_INTEGER_TYPE_P ( type ) || INTEGRAL_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( SCALAR_INT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) && ! COMPLEX_MODE_P ( mode ) && ( GET_MODE_SIZE ( mode ) == 16 || size == 16 ) ) return false ; return size != 1 && size != 2 && size != 4 && size != 8 ; } else { int needed_intregs , needed_sseregs ; return examine_argument ( mode , type , 1 , & needed_intregs , & needed_sseregs ) ; } } else { size = int_size_in_bytes ( type ) ; if ( TARGET_IAMCU ) return VECTOR_MODE_P ( mode ) || size < 0 || size > 8 ; if ( mode == BLKmode ) return true ; if ( MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P ( type ) && size <= 8 ) return false ; if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { if ( size < 8 ) return false ; if ( size == 8 ) return TARGET_VECT8_RETURNS || ! TARGET_MMX ; if ( size == 16 ) return ! TARGET_SSE ; if ( size == 32 ) return ! TARGET_AVX ; if ( size == 64 ) return ! TARGET_AVX512F ; } if ( mode == XFmode ) return false ; if ( size > 12 ) return true ; gcc_assert ( mode != OImode ) ; return false ; } } </s>

Return false iff type is returned in memory .


<s> rtx function_expander :: use_vcond_mask_insn ( insn_code icode , unsigned int merge_argno ) { machine_mode mode = vector_mode ( 0 ) ; unsigned int opno = 0 ; rtx false_arg = get_fallback_value ( mode , 1 , merge_argno , opno ) ; rtx pred_arg = args [ opno ++ ] ; rtx true_arg = args [ opno ++ ] ; add_output_operand ( icode ) ; add_input_operand ( icode , true_arg ) ; add_input_operand ( icode , false_arg ) ; add_input_operand ( icode , pred_arg ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , which is a select-like operation with the following operands : 0 : output 1 : true value 2 : false value 3 : predicate MERGE_ARGNO is the argument that provides the `` false '' value for _m functions , or DEFAULT_MERGE_ARGNO if we should apply the usual rules .


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C ) const { if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool ix86_expand_vecop_qihi2 ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { machine_mode himode , qimode = GET_MODE ( dest ) ; rtx hop1 , hop2 , hdest ; rtx ( * gen_extend ) ( rtx , rtx ) ; rtx ( * gen_truncate ) ( rtx , rtx ) ; bool uns_p = ( code == ASHIFTRT ) ? false : true ; if ( qimode == E_V64QImode ) return false ; if ( ! TARGET_AVX512BW ) return false ; if ( ( qimode == V8QImode || qimode == V16QImode ) && ! TARGET_AVX512VL ) return false ; if ( qimode == V32QImode && ( TARGET_PREFER_AVX128 || TARGET_PREFER_AVX256 ) ) return false ; switch ( qimode ) { case E_V8QImode : himode = V8HImode ; gen_extend = uns_p ? gen_zero_extendv8qiv8hi2 : gen_extendv8qiv8hi2 ; gen_truncate = gen_truncv8hiv8qi2 ; break ; case E_V16QImode : himode = V16HImode ; gen_extend = uns_p ? gen_zero_extendv16qiv16hi2 : gen_extendv16qiv16hi2 ; gen_truncate = gen_truncv16hiv16qi2 ; break ; case E_V32QImode : himode = V32HImode ; gen_extend = uns_p ? gen_zero_extendv32qiv32hi2 : gen_extendv32qiv32hi2 ; gen_truncate = gen_truncv32hiv32qi2 ; break ; default : gcc_unreachable ( ) ; } hop1 = gen_reg_rtx ( himode ) ; hop2 = gen_reg_rtx ( himode ) ; hdest = gen_reg_rtx ( himode ) ; emit_insn ( gen_extend ( hop1 , op1 ) ) ; emit_insn ( gen_extend ( hop2 , op2 ) ) ; emit_insn ( gen_rtx_SET ( hdest , simplify_gen_binary ( code , himode , hop1 , hop2 ) ) ) ; emit_insn ( gen_truncate ( dest , hdest ) ) ; return true ; } </s>

This function is similar as ix86_expand_vecop_qihi , but optimized under AVX512BW by using vpmovwb . For example , optimize vector MUL generation like vpmovzxbw ymm2 , xmm0 vpmovzxbw ymm3 , xmm1 vpmullw ymm4 , ymm2 , ymm3 vpmovwb xmm0 , ymm4 it would take less instructions than ix86_expand_vecop_qihi . Return true if success .


<s> const SpillSlot * getCalleeSavedSpillSlots ( unsigned & NumEntries ) const override { static const SpillSlot Offsets [ ] = { { VE :: SX17 , 40 } , { VE :: SX18 , 48 } , { VE :: SX19 , 56 } , { VE :: SX20 , 64 } , { VE :: SX21 , 72 } , { VE :: SX22 , 80 } , { VE :: SX23 , 88 } , { VE :: SX24 , 96 } , { VE :: SX25 , 104 } , { VE :: SX26 , 112 } , { VE :: SX27 , 120 } , { VE :: SX28 , 128 } , { VE :: SX29 , 136 } , { VE :: SX30 , 144 } , { VE :: SX31 , 152 } , { VE :: SX32 , 160 } , { VE :: SX33 , 168 } } ; NumEntries = array_lengthof ( Offsets ) ; return Offsets ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> bool AArch64TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( useSVEForFixedLengthVectorVT ( VT ) ) return false ; if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned Cost = getPerfectShuffleCost ( M ) ; if ( Cost <= 1 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static void ix86_init_tm_builtins ( void ) { enum ix86_builtin_func_type ftype ; const struct builtin_description * d ; size_t i ; tree decl ; tree attrs_load , attrs_type_load , attrs_store , attrs_type_store ; tree attrs_log , attrs_type_log ; if ( ! flag_tm ) return ; if ( ! builtin_decl_explicit_p ( BUILT_IN_TM_LOAD_1 ) ) return ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOAD_1 ) ; attrs_load = DECL_ATTRIBUTES ( decl ) ; attrs_type_load = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_STORE_1 ) ; attrs_store = DECL_ATTRIBUTES ( decl ) ; attrs_type_store = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOG ) ; attrs_log = DECL_ATTRIBUTES ( decl ) ; attrs_type_log = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; for ( i = 0 , d = bdesc_tm ; i < ARRAY_SIZE ( bdesc_tm ) ; i ++ , d ++ ) { if ( ( d -> mask & ix86_isa_flags ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type , attrs , attrs_type ; enum built_in_function code = ( enum built_in_function ) d -> code ; ftype = ( enum ix86_builtin_func_type ) d -> flag ; type = ix86_get_builtin_func_type ( ftype ) ; if ( BUILTIN_TM_LOAD_P ( code ) ) { attrs = attrs_load ; attrs_type = attrs_type_load ; } else if ( BUILTIN_TM_STORE_P ( code ) ) { attrs = attrs_store ; attrs_type = attrs_type_store ; } else { attrs = attrs_log ; attrs_type = attrs_type_log ; } decl = add_builtin_function ( d -> name , type , code , BUILT_IN_NORMAL , d -> name + strlen ( "__builtin_" ) , attrs ) ; decl_attributes ( & TREE_TYPE ( decl ) , attrs_type , ATTR_FLAG_BUILT_IN ) ; set_builtin_decl ( code , decl , false ) ; } } } </s>

Initialize the transactional memory vector load/store builtins .


<s> unsigned getCSRFirstUseCost ( ) const { return 5 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s>
virtual
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Assembly Printer"
;
}
</s>


<s> Register ARMTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return Subtarget -> useSjLjEH ( ) ? Register ( ) : ARM :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s>
void
ARMAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
if
(
EnableMCInst
)
{
printInstructionThroughMCStreamer
(
MI
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
ARM
::
CONSTPOOL_ENTRY
)
EmitAlignment
(
2
)
;
SmallString
<
128
>
Str
;
raw_svector_ostream
OS
(
Str
)
;
if
(
MI
->
getOpcode
(
)
==
ARM
::
DBG_VALUE
)
{
unsigned
NOps
=
MI
->
getNumOperands
(
)
;
assert
(
NOps
==
4
)
;
OS
<<
'\t'
<<
MAI
->
getCommentString
(
)
<<
"DEBUG_VALUE: "
;
DIVariable
V
(
const_cast
<
MDNode
*
>
(
MI
->
getOperand
(
NOps
1
)
.
getMetadata
(
)
)
)
;
OS
<<
V
.
getName
(
)
;
OS
<<
" <- "
;
assert
(
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
MI
->
getOperand
(
1
)
.
isImm
(
)
)
;
OS
<<
'['
;
printOperand
(
MI
,
0
,
OS
)
;
OS
<<
'+'
;
printOperand
(
MI
,
1
,
OS
)
;
OS
<<
']'
;
OS
<<
"+"
;
printOperand
(
MI
,
NOps
2
,
OS
)
;
OutStreamer
.
EmitRawText
(
OS
.
str
(
)
)
;
return
;
}
printInstruction
(
MI
,
OS
)
;
OutStreamer
.
EmitRawText
(
OS
.
str
(
)
)
;
if
(
MI
->
getOpcode
(
)
==
ARM
::
t2TBB
)
EmitAlignment
(
1
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void arm_function_arg_advance ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { aapcs_layout_arg ( pcum , arg . mode , arg . type , arg . named ) ; if ( pcum -> aapcs_cprc_slot >= 0 ) { aapcs_cp_arg_layout [ pcum -> aapcs_cprc_slot ] . advance ( pcum , arg . mode , arg . type ) ; pcum -> aapcs_cprc_slot = - 1 ; } pcum -> aapcs_arg_processed = false ; pcum -> aapcs_ncrn = pcum -> aapcs_next_ncrn ; pcum -> aapcs_reg = NULL_RTX ; pcum -> aapcs_partial = 0 ; } else { pcum -> nargs += 1 ; if ( arm_vector_mode_supported_p ( arg . mode ) && pcum -> named_count > pcum -> nargs && TARGET_IWMMXT_ABI ) pcum -> iwmmxt_nregs += 1 ; else pcum -> nregs += ARM_NUM_REGS2 ( arg . mode , arg . type ) ; } } </s>

Update the data in PCUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> int X86TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static void csky_conditional_register_usage ( void ) { if ( TARGET_MINI_REGISTERS ) { int i ; for ( i = ( CSKY_LAST_MINI_REGNUM + 1 ) ; i < 32 ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; } } else if ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) || ! TARGET_HIGH_REGISTERS ) { int i ; for ( i = CSKY_FIRST_HIGH_REGNUM ; i <= CSKY_LAST_HIGH_REGNUM ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; } } if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) { fixed_regs [ CSKY_LR_REGNUM ] = 1 ; call_used_regs [ CSKY_LR_REGNUM ] = 0 ; } if ( ! TARGET_DSP ) { fixed_regs [ CSKY_HI_REGNUM ] = 1 ; call_used_regs [ CSKY_HI_REGNUM ] = 1 ; fixed_regs [ CSKY_LO_REGNUM ] = 1 ; call_used_regs [ CSKY_LO_REGNUM ] = 1 ; } if ( ! TARGET_HARD_FLOAT ) { int regno ; for ( regno = CSKY_FIRST_VFP_REGNUM ; regno <= CSKY_LAST_VFP3_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 1 ; call_used_regs [ regno ] = 1 ; } } if ( ! TARGET_SUPPORT_FPV3 ) { int regno ; for ( regno = CSKY_FIRST_VFP3_REGNUM ; regno <= CSKY_LAST_VFP3_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 1 ; call_used_regs [ regno ] = 1 ; } } if ( flag_pic ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 0 ; } } </s>

Implement TARGET_CONDITIONAL_REGISTER_USAGE . Conditionally modify five variables fixed_regs , call_used_regs , global_regs , reg_names , and reg_class_contents , to take into account any dependence of these register sets on target flags . CK801 has registers r0-r8 and r13-r15 . CK802 and CK803 have registers r0-r15 ( the `` low '' registers ) . Other cpus use registers r0-r31 with -mhigh-registers , otherwise also only r0-r15 . CK801 only has 16-bit instructions , most of which can only reference r0-r7 ( the `` mini '' registers ) . So we mark regs outside that range as fixed . -msmart can be used on other arch variants to force the same behavior because it results in smaller code size . TODO : investigate whether it 's beneficial to use r8-r13 as a spill class when TARGET_MINI_REGISTERS instead of making them unusable by the register allocator .


<s> bool ARMBaseTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createARMISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void ix86_output_patchable_area ( unsigned int patch_area_size , bool record_p ) { default_print_patchable_function_entry ( asm_out_file , patch_area_size , record_p ) ; } </s>

Output patchable area . NB : default_print_patchable_function_entry is n't available in i386.md .


<s> void emitVERegisterScratch ( unsigned reg ) override { } </s>

Emit `` .register < reg > , # scratch '' .


<s> bool isReg ( ) const override { return Kind == k_Register && ! Reg . isVector ; } </s>


<s> TargetLoweringBase :: LegalizeTypeAction AArch64TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT == MVT :: v1i8 || VT == MVT :: v1i16 || VT == MVT :: v1i32 || VT == MVT :: v1f32 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static rtx arm_expand_ternop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; tree arg2 = CALL_EXPR_ARG ( exp , 2 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ 3 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( VECTOR_MODE_P ( mode2 ) ) op2 = safe_vector_operand ( op2 , mode2 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) && ( GET_MODE ( op2 ) == mode2 || GET_MODE ( op2 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ 3 ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> void altivec_expand_stvex_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx tmp = gen_reg_rtx ( mode ) ; rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( 1 , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( gen_rtx_SET ( op0 , stvx ) ) ; } </s>

Generate code for a `` stve * x '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; Register SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static bool dispatch_violation ( void ) { if ( dispatch_window_list -> next ) return dispatch_window_list -> next -> violation ; return dispatch_window_list -> violation ; } </s>

Return true if a dispatch violation encountered .


<s> TargetPassConfig * LanaiTargetMachine :: createPassConfig ( PassManagerBase & PassManager ) { return new LanaiPassConfig ( this , & PassManager ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"passing arg %d of %qE discards qualifiers from"

"invalid parameter combination for AltiVec intrinsic"

Implementation of the resolve_overloaded_builtin target hook , to support Altivec 's overloaded builtins .


<s> ARMRelocator :: Result unsupported ( Relocation & pReloc , ARMRelocator & pParent ) { return Relocator :: Unsupported ; } </s>