<s> void expand_fusion_p9_store ( rtx * operands ) { rtx tmp_reg = operands [ 0 ] ; rtx addis_value = operands [ 1 ] ; rtx orig_mem = operands [ 2 ] ; rtx src = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset , set , clobber , insn , new_src ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( orig_mem ) ; machine_mode ptr_mode = Pmode ; gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; new_src = gen_rtx_UNSPEC ( target_mode , gen_rtvec ( 1 , src ) , UNSPEC_FUSION_P9 ) ; set = gen_rtx_SET ( new_mem , new_src ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , tmp_reg ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ; emit_insn ( insn ) ; return ; } </s>

During the peephole2 pass , adjust and expand the insns for an extended fusion store sequence . The operands are : operands [ 0 ] register set with addis operands [ 1 ] value set via addis operands [ 2 ] target D-form memory being stored to operands [ 3 ] register being stored This is similar to the fusion introduced with power8 , except it scales to both loads/stores and does not require the result register to be the same as the base register . At the moment , we only do this if register set with addis is dead .


<s> static rtx ix86_expand_vec_init_builtin ( tree type , tree arglist , rtx target ) { enum machine_mode tmode = TYPE_MODE ( type ) ; enum machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; rtvec v = rtvec_alloc ( n_elt ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; for ( i = 0 ; i < n_elt ; ++ i , arglist = TREE_CHAIN ( arglist ) ) { rtx x = expand_expr ( TREE_VALUE ( arglist ) , NULL_RTX , VOIDmode , 0 ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } gcc_assert ( arglist == NULL ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_init ( true , target , gen_rtx_PARALLEL ( tmode , v ) ) ; return target ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_init . We DO have language-level syntax for this , in the form of ( type ) { init-list } . Except that since we ca n't place emms instructions from inside the compiler , we ca n't allow the use of MMX registers unless the user explicitly asks for it . So we do * not * define vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md . Instead we have builtins invoked by mmintrin.h that gives us license to emit these sorts of instructions .


<s> MachineBasicBlock :: iterator SHUXIFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const SHUXIInstrInfo & TII = * static_cast < const SHUXIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; uint64_t Amount = Old . getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( SHUXI :: SUBri ) , SHUXI :: SP ) . addReg ( SHUXI :: SP ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old . getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( SHUXI :: ADDri ) , SHUXI :: SP ) . addReg ( SHUXI :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( SHUXI :: SUBri ) , SHUXI :: SP ) . addReg ( SHUXI :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool X86InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern :: MC_PATTERN > & Patterns ) const { bool Commute ; if ( isReassociationCandidate ( Root , Commute ) ) { if ( Commute ) { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_YB ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_YB ) ; } else { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_BY ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_BY ) ; } return true ; } return false ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s>
static
void
thumb_pop
(
FILE
*
f
,
unsigned
long
mask
)
{
int
regno
;
int
lo_mask
=
mask
&
0xFF
;
int
pushed_words
=
0
;
gcc_assert
(
mask
)
;
if
(
lo_mask
==
0
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
thumb_exit
(
f
,
1
)
;
return
;
}
fprintf
(
f
,
"\tpop\t{"
)
;
for
(
regno
=
0
;
regno
<=
LAST_LO_REGNUM
;
regno
++
,
lo_mask
>>=
1
)
{
if
(
lo_mask
&
1
)
{
asm_fprintf
(
f
,
"%r"
,
regno
)
;
if
(
(
lo_mask
&
~
1
)
!=
0
)
fprintf
(
f
,
", "
)
;
pushed_words
++
;
}
}
if
(
mask
&
(
1
<<
PC_REGNUM
)
)
{
if
(
TARGET_INTERWORK
||
TARGET_BACKTRACE
||
crtl
->
calls_eh_return
)
{
fprintf
(
f
,
"}\n"
)
;
thumb_exit
(
f
,
1
)
;
return
;
}
else
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
PC_REGNUM
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
}
</s>

Emit code to push or pop registers to or from the stack . F is the assembly file . MASK is the registers to pop .


<s> CCAssignFn * MipsFastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { return CC_MipsO32 ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static void x86_64_elf_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && ix86_in_large_data_p ( decl ) ) { const char * sname = NULL ; unsigned int flags = SECTION_WRITE ; switch ( categorize_decl_for_section ( decl , reloc , flag_pic ) ) { case SECCAT_DATA : sname = ".ldata" ; break ; case SECCAT_DATA_REL : sname = ".ldata.rel" ; break ; case SECCAT_DATA_REL_LOCAL : sname = ".ldata.rel.local" ; break ; case SECCAT_DATA_REL_RO : sname = ".ldata.rel.ro" ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = ".ldata.rel.ro.local" ; break ; case SECCAT_BSS : sname = ".lbss" ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : sname = ".lrodata" ; flags = 0 ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( sname ) { if ( ! DECL_P ( decl ) ) named_section_flags ( sname , flags ) ; else named_section ( decl , sname , reloc ) ; return ; } } default_elf_select_section ( decl , reloc , align ) ; } </s>

switch to the appropriate section for output of DECL . DECL is either a ` VAR_DECL ' node or a constant of some sort . RELOC indicates whether forming the initial value of DECL requires link-time relocations .


<s> static void mips_extra_live_on_entry ( bitmap regs ) { if ( TARGET_USE_GOT ) { if ( ! TARGET_ABSOLUTE_ABICALLS ) bitmap_set_bit ( regs , PIC_FUNCTION_ADDR_REGNUM ) ; if ( TARGET_MIPS16 ) bitmap_set_bit ( regs , MIPS16_PIC_TEMP_REGNUM ) ; bitmap_set_bit ( regs , GOT_VERSION_REGNUM ) ; } } </s>


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> bool isLegalMaskedGather ( Type * DataType , MaybeAlign Alignment ) { return isVectorLaneType ( * getLaneType ( DataType ) ) ; } </s>

Return true if the target supports masked gather .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } if ( getPPCTargetMachine ( ) . isPositionIndependent ( ) ) { addPass ( & LiveVariablesID , false ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SPISD :: NodeType ) Opcode ) { case SPISD :: FIRST_NUMBER : break ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool mips_small_data_pattern_p ( rtx op ) { return mips_small_data_pattern_1 ( op , SYMBOL_CONTEXT_LEA ) ; } </s>

Return true if OP refers to small data symbols directly , not through a LO_SUM .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( Subtarget -> hasMSA ( ) && type -> isVectorTy ( ) && cast < VectorType > ( type ) -> getBitWidth ( ) == 128 ) weight = CW_Register ; else if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void LC3bFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool detect_cmse_nonsecure_call ( tree addr ) { if ( ! addr ) return FALSE ; tree fntype = TREE_TYPE ( addr ) ; if ( use_cmse && lookup_attribute ( "cmse_nonsecure_call" , TYPE_ATTRIBUTES ( fntype ) ) ) return TRUE ; return FALSE ; } </s>

Returns true if -mcmse has been passed and the function pointed to by 'addr ' has the cmse_nonsecure_call attribute and returns false otherwise .


<s>
void
SystemZFrameInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
const
TargetFrameInfo
&
TFI
=
*
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
SystemZInstrInfo
&
TII
=
*
static_cast
<
const
SystemZInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
SystemZMachineFunctionInfo
*
SystemZMFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
StackSize
-=
SystemZMFI
->
getCalleeSavedFrameSize
(
)
;
uint64_t
NumBytes
=
StackSize
TFI
.
getOffsetOfLocalArea
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mr
||
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mrm
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
StackSize
||
MFI
->
hasCalls
(
)
)
{
assert
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
SystemZ
::
R15D
)
&&
"Invalid stack frame calculation!"
)
;
emitSPUpdate
(
MBB
,
MBBI
,
(
int64_t
)
NumBytes
,
TII
)
;
}
if
(
hasFP
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
SystemZ
::
MOV64rr
)
,
SystemZ
::
R11D
)
.
addReg
(
SystemZ
::
R15D
)
;
for
(
MachineFunction
::
iterator
I
=
llvm
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
SystemZ
::
R11D
)
;
}
}
</s>


<s> Optional < MCFixupKind > AArch64AsmBackend :: getFixupKind ( StringRef Name ) const { if ( TheTriple . isOSBinFormatELF ( ) && Name == "R_AARCH64_NONE" ) return FK_NONE ; return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetMachO ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
InMips16Mode
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"


<s> static bool is_va_list_char_pointer ( tree type ) { tree canonic ; if ( ! TARGET_64BIT ) return true ; canonic = ix86_canonical_va_list_type ( type ) ; return ( canonic == ms_va_list_type_node || ( ix86_abi == MS_ABI && canonic == va_list_type_node ) ) ; } </s>

Checks if TYPE is of kind va_list char * .


"Huge Stack Frame not yet supported on z/OS"


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: ERet : expandERet ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI ) ; break ; case Mips :: PseudoMFHI_MM : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI16_MM ) ; break ; case Mips :: PseudoMFLO : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO ) ; break ; case Mips :: PseudoMFLO_MM : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO16_MM ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : Opc = isMicroMips ? Mips :: CVT_D32_W_MM : Mips :: CVT_D32_W ; expandCvtFPInt ( MBB , MI , Opc , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : Opc = isMicroMips ? Mips :: CVT_D64_W_MM : Mips :: CVT_D64_W ; expandCvtFPInt ( MBB , MI , Opc , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , isMicroMips , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , isMicroMips , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , isMicroMips , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , isMicroMips , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool X86TargetLowering :: IsEligibleForTailCallOptimization ( CallSDNode * TheCall , SDValue Ret , SelectionDAG & DAG ) const { if ( ! PerformTailCallOpt ) return false ; if ( CheckTailCallReturnConstraints ( TheCall , Ret ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; unsigned CalleeCC = TheCall -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { SDValue Callee = TheCall -> getCallee ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ || ! Subtarget -> isPICStyleGOT ( ) || ! Subtarget -> is64Bit ( ) ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> static rtx nds32_expand_binop_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; int op0_num = return_p ? 1 : 0 ; int op1_num = return_p ? 2 : 1 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take two operands .


<s> void AArch64InstrInfo :: suppressLdStPair ( MachineInstr & MI ) const { if ( MI . memoperands_empty ( ) ) return ; ( * MI . memoperands_begin ( ) ) -> setFlags ( MOSuppressPair ) ; } </s>

Hint that pairing the given load or store is unprofitable .


<s> tree rs6000_builtin_decl ( unsigned code , bool ) { rs6000_gen_builtins fcode = ( rs6000_gen_builtins ) code ; if ( fcode >= RS6000_OVLD_MAX ) return error_mark_node ; return rs6000_builtin_decls [ code ] ; } </s>

Returns the rs6000 builtin decl for CODE .


<s>
void
MipsCodeEmitter
::
emitInstruction
(
const
MachineInstr
&
MI
)
{
DEBUG
(
errs
(
)
<<
"JIT: "
<<
(
void
*
)
MCE
.
getCurrentPCValue
(
)
<<
":\t"
<<
MI
)
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
true
)
;
if
(
(
MI
.
getDesc
(
)
.
TSFlags
&
MipsII
::
FormMask
)
==
MipsII
::
Pseudo
)
return
;
++
NumEmitted
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
emitWordLE
(
getBinaryCodeForInstr
(
MI
)
)
;
break
;
}
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
false
)
;
}
</s>

Targets should implement this to emit instructions .

Mips
Mips
"JIT: "
":\t"
MipsII::FormMask
MipsII::Pseudo


<s> static bool mips_use_blocks_for_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , const_rtx x ATTRIBUTE_UNUSED ) { return ! TARGET_MIPS16_PCREL_LOADS ; } </s>

Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P . We ca n't use blocks for constants when we 're using a per-function constant pool .


<s> static void mips_start_function_definition ( const char * name , bool mips16_p ) { if ( mips16_p ) fprintf ( asm_out_file , "\t.set\tmips16\n" ) ; else fprintf ( asm_out_file , "\t.set\tnomips16\n" ) ; if ( TARGET_MICROMIPS ) fprintf ( asm_out_file , "\t.set\tmicromips\n" ) ; else fprintf ( asm_out_file , "\t.set\tnomicromips\n" ) ; if ( ! flag_inhibit_size_directive ) { fputs ( "\t.ent\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( "\n" , asm_out_file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( asm_out_file , name , "function" ) ; assemble_name ( asm_out_file , name ) ; fputs ( ":\n" , asm_out_file ) ; } </s>

Start a definition of function NAME . MIPS16_P indicates whether the function contains MIPS16 code .


<s> StringRef NamedImmMapper :: toString ( uint32_t Value , bool & Valid ) const { for ( unsigned i = 0 ; i < NumPairs ; ++ i ) { if ( Pairs [ i ] . Value == Value ) { Valid = true ; return Pairs [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . padShortFunctions ( ) ) { addPass ( createX86PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . LEAusesAG ( ) ) { addPass ( createX86FixupLEAs ( ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( createX86NaClRewritePass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool aarch64_evpc_uzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( i * 2 + odd ) & mask ; if ( d -> perm [ i ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_uzp2v16qi ; break ; case V8QImode : gen = gen_aarch64_uzp2v8qi ; break ; case V8HImode : gen = gen_aarch64_uzp2v8hi ; break ; case V4HImode : gen = gen_aarch64_uzp2v4hi ; break ; case V4SImode : gen = gen_aarch64_uzp2v4si ; break ; case V2SImode : gen = gen_aarch64_uzp2v2si ; break ; case V2DImode : gen = gen_aarch64_uzp2v2di ; break ; case V4SFmode : gen = gen_aarch64_uzp2v4sf ; break ; case V2SFmode : gen = gen_aarch64_uzp2v2sf ; break ; case V2DFmode : gen = gen_aarch64_uzp2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_uzp1v16qi ; break ; case V8QImode : gen = gen_aarch64_uzp1v8qi ; break ; case V8HImode : gen = gen_aarch64_uzp1v8hi ; break ; case V4HImode : gen = gen_aarch64_uzp1v4hi ; break ; case V4SImode : gen = gen_aarch64_uzp1v4si ; break ; case V2SImode : gen = gen_aarch64_uzp1v2si ; break ; case V2DImode : gen = gen_aarch64_uzp1v2di ; break ; case V4SFmode : gen = gen_aarch64_uzp1v4sf ; break ; case V2SFmode : gen = gen_aarch64_uzp1v2sf ; break ; case V2DFmode : gen = gen_aarch64_uzp1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the UZP instructions .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
<<
"("
<<
AArch64_AM
::
getFPImmFloat
(
getFPImm
(
)
)
<<
") >"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
if
(
!
getShiftExtendAmount
(
)
&&
!
hasShiftExtendAmount
(
)
)
break
;
LLVM_FALLTHROUGH
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
"("
AArch64_AM::getFPImmFloat
") >"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<register "
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> rtx legitimize_tls_address ( rtx x , rtx reg ) { rtx dest , tp , label , labelno , sum , insns , ret , eqv , addend ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; return dest ; case TLS_MODEL_LOCAL_DYNAMIC : insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; return gen_rtx_PLUS ( Pmode , dest , addend ) ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? 8 : 4 ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; reg = force_reg ( SImode , gen_rtx_CONST ( SImode , reg ) ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; default : abort ( ) ; } } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void release_scratch_register_on_entry ( struct scratch_reg * sr , HOST_WIDE_INT offset , bool release_via_pop ) { if ( sr -> saved ) { if ( release_via_pop ) { struct machine_function * m = cfun -> machine ; rtx x , insn = emit_insn ( gen_pop ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; } else { rtx x = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; x = gen_rtx_SET ( sr -> reg , gen_rtx_MEM ( word_mode , x ) ) ; emit_insn ( x ) ; } } } </s>

Release a scratch register obtained from the preceding function . If RELEASE_VIA_POP is true , we just pop the register off the stack to release it . This is what non-Linux systems use with -fstack-check . Otherwise we use OFFSET to locate the saved register and the allocated stack space becomes part of the local frame and is deallocated by the epilogue .


<s> llvm :: FastISel * X86 :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmi , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , 8 > & cil ) { return new X86FastISel ( mf , mmi , dw , vm , bm , am , cil ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void mips_expand_synci_loop ( rtx begin , rtx end ) { rtx inc , cmp_result , mask , length ; rtx_code_label * label , * end_label ; end_label = gen_label_rtx ( ) ; cmp_result = gen_rtx_EQ ( VOIDmode , begin , end ) ; emit_jump_insn ( gen_condjump ( cmp_result , end_label ) ) ; inc = gen_reg_rtx ( Pmode ) ; emit_insn ( PMODE_INSN ( gen_rdhwr_synci_step , ( inc ) ) ) ; cmp_result = gen_rtx_EQ ( VOIDmode , inc , const0_rtx ) ; emit_jump_insn ( gen_condjump ( cmp_result , end_label ) ) ; mask = mips_force_unary ( Pmode , NEG , inc ) ; begin = mips_force_binary ( Pmode , AND , begin , mask ) ; length = mips_force_binary ( Pmode , MINUS , end , begin ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; emit_insn ( gen_synci ( begin ) ) ; mips_emit_binary ( MINUS , length , length , inc ) ; mips_emit_binary ( PLUS , begin , begin , inc ) ; cmp_result = gen_rtx_GT ( VOIDmode , length , const0_rtx ) ; emit_jump_insn ( gen_condjump ( cmp_result , label ) ) ; emit_label ( end_label ) ; } </s>

Expand a loop of synci insns for the address range [ BEGIN , END ) .


<s> static bool ia64_return_in_memory ( const_tree valtype , const_tree fntype ATTRIBUTE_UNUSED ) { machine_mode mode ; machine_mode hfa_mode ; HOST_WIDE_INT byte_size ; mode = TYPE_MODE ( valtype ) ; byte_size = GET_MODE_SIZE ( mode ) ; if ( mode == BLKmode ) { byte_size = int_size_in_bytes ( valtype ) ; if ( byte_size < 0 ) return true ; } hfa_mode = hfa_element_mode ( valtype , 0 ) ; if ( hfa_mode != VOIDmode ) { int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; if ( byte_size / hfa_size > MAX_ARGUMENT_SLOTS ) return true ; else return false ; } else if ( byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS ) return true ; else return false ; } </s>

Return 1 if function return value returned in memory . Return 0 if it is in a register .


<s> TargetPassConfig * AArch64TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AArch64PassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> char * aarch64_output_sve_cnt_immediate ( const char * prefix , const char * operands , rtx x ) { poly_int64 value = rtx_to_poly_int64 ( x ) ; gcc_assert ( aarch64_sve_cnt_immediate_p ( value ) ) ; return aarch64_output_sve_cnt_immediate ( prefix , operands , AARCH64_SV_ALL , value . coeffs [ 1 ] , 0 ) ; } </s>

Return the asm string for an instruction with a CNT-like vector size operand ( a vector pattern followed by a multiplier in the range [ 1 , 16 ] ) . PREFIX is the mnemonic without the size suffix and OPERANDS is the first part of the operands template ( the part that comes before the vector size itself ) . X is the value of the vector size operand , as a polynomial integer rtx .


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ; int fp_reg_size = 8 ; int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> static void sh_emit_storehi ( rtx addr , HOST_WIDE_INT offset , uint16_t w0 , uint16_t w1 ) { sh_emit_storesi ( addr , offset , gen_int_mode ( TARGET_LITTLE_ENDIAN ? ( w0 | ( w1 << 16 ) ) : ( w1 | ( w0 << 16 ) ) , SImode ) ) ; } </s>

Emit insns to store w0 at addr + offset and w1 at addr + offset + 2 .


<s> int ia64_load_pair_ok ( rtx dst , rtx src ) { if ( GET_CODE ( dst ) != REG || ! FP_REGNO_P ( REGNO ( dst ) ) ) return 0 ; if ( GET_CODE ( src ) != MEM || MEM_VOLATILE_P ( src ) ) return 0 ; switch ( GET_CODE ( XEXP ( src , 0 ) ) ) { case REG : case POST_INC : break ; case POST_DEC : return 0 ; case POST_MODIFY : { rtx adjust = XEXP ( XEXP ( XEXP ( src , 0 ) , 1 ) , 1 ) ; if ( GET_CODE ( adjust ) != CONST_INT || INTVAL ( adjust ) != GET_MODE_SIZE ( GET_MODE ( src ) ) ) return 0 ; } break ; default : abort ( ) ; } return 1 ; } </s>

Return 1 if the operands are ok for a floating point load pair .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentInstruction ( Inst , Operands , getContext ( ) , MII , Out ) ; Out . EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static unsigned int aarch64_get_next_set_bit ( sbitmap bmp , unsigned int start ) { unsigned int nbits = SBITMAP_SIZE ( bmp ) ; if ( start == nbits ) return start ; gcc_assert ( start < nbits ) ; for ( unsigned int i = start ; i < nbits ; i ++ ) if ( bitmap_bit_p ( bmp , i ) ) return i ; return nbits ; } </s>

Return the next set bit in BMP from START onwards . Return the total number of bits in BMP if no set bit is found at or after START .


<s> void rs6000_split_v4si_init ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; if ( REG_P ( dest ) || SUBREG_P ( dest ) ) { int d_regno = regno_or_subregno ( dest ) ; rtx scalar1 = operands [ 1 ] ; rtx scalar2 = operands [ 2 ] ; rtx scalar3 = operands [ 3 ] ; rtx scalar4 = operands [ 4 ] ; rtx tmp1 = operands [ 5 ] ; rtx tmp2 = operands [ 6 ] ; if ( BYTES_BIG_ENDIAN ) { rtx di_lo = gen_rtx_REG ( DImode , d_regno ) ; rtx di_hi = gen_rtx_REG ( DImode , d_regno + 1 ) ; rs6000_split_v4si_init_di_reg ( di_lo , scalar1 , scalar2 , tmp1 ) ; rs6000_split_v4si_init_di_reg ( di_hi , scalar3 , scalar4 , tmp2 ) ; } else { rtx di_lo = gen_rtx_REG ( DImode , d_regno + 1 ) ; rtx di_hi = gen_rtx_REG ( DImode , d_regno ) ; gcc_assert ( ! VECTOR_ELT_ORDER_BIG ) ; rs6000_split_v4si_init_di_reg ( di_lo , scalar4 , scalar3 , tmp1 ) ; rs6000_split_v4si_init_di_reg ( di_hi , scalar2 , scalar1 , tmp2 ) ; } return ; } else gcc_unreachable ( ) ; } </s>


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( EH_SJLJ_LONGJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETUP_DISPATCH ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( TS1AM ) TARGET_NODE_CASE ( VEC_BROADCAST ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER VE


"ACLE function %qD requires ISA extension %qs"

"you can enable %qs using the command-line"

" option %<-march%>, or by using the %<target%>"

Report an error against LOCATION that the user has tried to use function FNDECL when extension EXTENSION is disabled .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) <= 32 ) return std :: make_pair ( 0U , & AArch64 :: GPR32RegClass ) ; else if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64RegClass ) ; break ; case 'w' : if ( VT == MVT :: f16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; else if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; else if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; else if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Size = 0 ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFI . getObjectOffset ( I ) > 0 ) Size += MFI . getObjectSize ( I ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned RegSize = TRI . getSpillSize ( * TRI . getMinimalPhysRegClass ( * R ) ) ; Size = alignTo ( Size + RegSize , RegSize ) ; } return Size + MFI . estimateStackSize ( MF ) ; } </s>

Estimate and return the size of the stack frame .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void i386_pe_unique_section ( tree decl , int reloc ) { int len ; const char * name , * prefix ; char * string ; if ( ! flag_writable_rel_rdata ) reloc = 0 ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = i386_pe_strip_name_encoding_full ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = ".text$" ; else if ( decl_readonly_section ( decl , reloc ) ) prefix = ".rdata$" ; else prefix = ".data$" ; len = strlen ( name ) + strlen ( prefix ) ; string = XALLOCAVEC ( char , len + 1 ) ; sprintf ( string , "%s%s" , prefix , name ) ; set_decl_section_name ( decl , string ) ; } </s>


"instruction requires a CPU feature not currently enabled"

"source and destination must be different"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool isFPImm ( ) const { return Kind == k_FPImm ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> bool MipsSETargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! EnableMipsTailCalls ) return false ; if ( CCInfo . getInRegsParamsCount ( ) > 0 || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s> static bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == 64 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 64 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; if ( ( mode1 == E_SCmode && mode2 == E_DImode ) || ( mode1 == E_DImode && mode2 == E_SCmode ) ) return TARGET_64BIT ; if ( ( mode1 == E_SCmode && mode2 == E_V2SFmode ) || ( mode1 == E_V2SFmode && mode2 == E_SCmode ) || ( mode1 == E_DCmode && mode2 == E_V2DFmode ) || ( mode1 == E_V2DFmode && mode2 == E_DCmode ) ) return true ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


<s> static bool arm_block_set_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { if ( ( ( align & 3 ) != 0 || ( length & 3 ) != 0 ) && ( ! unaligned_access || BYTES_BIG_ENDIAN ) ) return false ; if ( ( align & 3 ) == 0 ) return arm_block_set_aligned_vect ( dstbase , length , value , align ) ; else return arm_block_set_unaligned_vect ( dstbase , length , value , align ) ; } </s>

Set a block of memory using vectorization instructions for both aligned and unaligned cases . We fill the first LENGTH bytes of the memory area starting from DSTBASE with byte constant VALUE . ALIGN is the alignment requirement of memory .


<s> static unsigned int ATTRIBUTE_UNUSED x86_64_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ix86_in_large_data_p ( decl ) ) flags |= SECTION_LARGE ; if ( decl == NULL_TREE && ( strcmp ( name , ".ldata.rel.ro" ) == 0 || strcmp ( name , ".ldata.rel.ro.local" ) == 0 ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , ".lbss" ) == 0 || startswith ( name , ".lbss." ) || startswith ( name , ".gnu.linkonce.lb." ) ) flags |= SECTION_BSS ; return flags ; } </s>

Select a set of attributes for section NAME based on the properties of DECL and whether or not RELOC indicates that DECL 's initializer might contain runtime relocations .


<s> static void mmix_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( 2 * UNITS_PER_WORD ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , DImode , 2 * UNITS_PER_WORD ) ; emit_move_insn ( mem , static_chain ) ; mem = adjust_address ( m_tramp , DImode , 3 * UNITS_PER_WORD ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , DImode , 0 ) ; emit_insn ( gen_sync_icache ( mem , GEN_INT ( TRAMPOLINE_SIZE - 1 ) ) ) ; } </s>

Set the static chain and function pointer field in the trampoline . We also SYNCID here to be sure ( does n't matter in the simulator , but some day it will ) .


<s>
const
char
*
output_adjust_stack_and_probe
(
rtx
reg
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
GEN_INT
(
get_probe_interval
(
)
)
;
output_asm_insn
(
"sub%z0\t{%1, %0|%0, %1}"
,
xops
)
;
xops
[
1
]
=
const0_rtx
;
output_asm_insn
(
"or%z0\t{%1, (%0)|DWORD PTR [%0], %1}"
,
xops
)
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
reg
;
output_asm_insn
(
"cmp%z0\t{%1, %0|%0, %1}"
,
xops
)
;
fputs
(
"\tjne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Adjust the stack pointer up to REG while probing it .


<s> static void add_compiler_branch_island ( tree label_name , tree function_name , int line_number ) { branch_island bi = { function_name , label_name , line_number } ; vec_safe_push ( branch_islands , bi ) ; } </s>

Remember to generate a branch island for far calls to the given function .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = RoundUpToAlignment ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> static rtx emit_adjust_base_to_offset ( rtx base , int offset ) { rtx new_base = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( new_base , GEN_INT ( offset ) ) ; emit_insn ( gen_rtx_SET ( new_base , gen_rtx_PLUS ( Pmode , base , new_base ) ) ) ; return new_base ; } </s>

Emit code to adjust BASE to OFFSET . Return the new base .


<s>
void
PPCMIPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"*** PowerPC MI peephole pass ***\n\n"
)
;
DEBUG
(
MF
->
dump
(
)
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

PowerPC
PPC
PPC
"*** PowerPC MI peephole pass ***\n\n"


<s>
int
AArch64LoadStoreOpt
::
getMemSize
(
MachineInstr
*
MemMI
)
{
switch
(
MemMI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown size!"
)
;
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
return
4
;
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
return
8
;
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
return
16
;
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
return
4
;
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
return
8
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
return
16
;
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
return
4
;
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
return
8
;
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
return
4
;
}
}
</s>

Returns the size in bytes of the memory access .


<s> bool X86TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == MVT :: f32 ) return X86ScalarSSEf32 ; else if ( VT == MVT :: f64 ) return X86ScalarSSEf64 ; return TargetLowering :: isSafeMemOpType ( VT ) ; } </s>

Returns true if it 's safe to use load / store of the specified type to expand memcpy / memset inline .


"parameter passing for argument of type "

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


Allocate ORIG_SIZE bytes on the stack and probe the newly allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes . COPY_REG , if non-null , should contain a copy of the original stack pointer at exit from this function . This is subtly different than the Ada probing in that it tries hard to prevent attacks that jump the stack guard . Thus it is never allowed to allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack space without a suitable probe .


"force: group count = %d, can_issue_more = %d\n"

"done force: group count = %d, can_issue_more = %d\n"

Utility of the function redefine_groups . Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS in the same dispatch group . If so , insert nops before NEXT_INSN , in order to keep it `` far '' ( in a separate group ) from GROUP_INSNS , following one of the following schemes , depending on the value of the flag -minsert_sched_nops = X : ( 1 ) X == sched_finish_regroup_exact : insert exactly as many nops as needed in order to force NEXT_INSN into a separate group . ( 2 ) X < sched_finish_regroup_exact : insert exactly X nops . GROUP_END , CAN_ISSUE_MORE and GROUP_COUNT record the state after nop insertion ( has a group just ended , how many vacant issue slots remain in the last group , and how many dispatch groups were encountered so far ) .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> void AnalyzeCallResult ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn , const TargetLowering :: CallLoweringInfo & CLI ) { PreAnalyzeCallResultForF128 ( Ins , CLI ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeCallResult - Same as above except it 's specialized for calls which produce a single value .


<s> bool use_simple_return_p ( void ) { arm_stack_offsets * offsets ; if ( ! reload_completed ) arm_compute_frame_layout ( ) ; offsets = arm_get_frame_offsets ( ) ; return offsets -> outgoing_args != 0 ; } </s>

Return TRUE if we should try to use a simple_return insn , i.e . perform shrink-wrapping if possible . This is the case if we need to emit a prologue , which we can test by looking at the offsets .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetHazardRecognizer
(
const
TargetMachine
*
TM
,
const
ScheduleDAG
*
DAG
)
const
{
const
TargetInstrInfo
*
TII
=
TM
->
getInstrInfo
(
)
;
assert
(
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
TII
)
;
}
</s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> static rtx or1k_libcall_value ( machine_mode mode , const_rtx ) { return gen_rtx_REG ( mode , RV_REGNUM ) ; } </s>

Worker for TARGET_LIBCALL_VALUE . Returns an RTX representing the location where function return values to external libraries will be stored . On OpenRISC this the same as local function calls .


<s> AArch64Subtarget & AArch64Subtarget :: initializeSubtargetDependencies ( StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"passing %qT to argument %d of %qE, which"

" expects a vector of 32-bit or 64-bit integers"

Require argument ARGNO to be a vector displacement in a gather-style address . Return its type on success , otherwise return NUM_VECTOR_TYPES .


<s> static int eligible_for_restore_insn ( rtx trial , bool return_p ) { rtx pat = PATTERN ( trial ) ; rtx src = SET_SRC ( pat ) ; if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_operand ( src , GET_MODE ( src ) ) ) { if ( TARGET_ARCH64 ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( SImode ) ; } else if ( GET_MODE_CLASS ( GET_MODE ( src ) ) != MODE_FLOAT && arith_double_operand ( src , GET_MODE ( src ) ) ) return GET_MODE_SIZE ( GET_MODE ( src ) ) <= GET_MODE_SIZE ( DImode ) ; else if ( ! TARGET_FPU && register_operand ( src , SFmode ) ) return 1 ; else if ( ! TARGET_FPU && TARGET_ARCH64 && register_operand ( src , DFmode ) ) return 1 ; else if ( return_p && TARGET_V9 && ! epilogue_renumber ( & pat , 1 ) && ( get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ) ) return 1 ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , 0 ) , SImode ) && arith_operand ( XEXP ( src , 1 ) , SImode ) ) return 1 ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , 0 ) , DImode ) && arith_double_operand ( XEXP ( src , 1 ) , DImode ) ) return 1 ; else if ( GET_CODE ( src ) == LO_SUM && ! TARGET_CM_MEDMID && ( ( register_operand ( XEXP ( src , 0 ) , SImode ) && immediate_operand ( XEXP ( src , 1 ) , SImode ) ) || ( TARGET_ARCH64 && register_operand ( XEXP ( src , 0 ) , DImode ) && immediate_operand ( XEXP ( src , 1 ) , DImode ) ) ) ) return 1 ; else if ( GET_CODE ( src ) == ASHIFT && ( register_operand ( XEXP ( src , 0 ) , SImode ) || register_operand ( XEXP ( src , 0 ) , DImode ) ) && XEXP ( src , 1 ) == const1_rtx ) return 1 ; return 0 ; } </s>

Return nonzero if TRIAL , an insn , can be combined with a 'restore ' instruction . RETURN_P is true if the v9 variant 'return ' is to be considered in the test too . TRIAL must be a SET whose destination is a REG appropriate for the 'restore ' instruction or , if RETURN_P is true , for the 'return ' instruction .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static void mips_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , temp1 , temp2 , fnaddr ; rtx_insn * insn ; bool use_sibcall_p ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = XEXP ( DECL_RTL ( function ) , 0 ) ; use_sibcall_p = ( mips_function_ok_for_sibcall ( function , NULL ) && const_call_insn_operand ( fnaddr , Pmode ) ) ; if ( ! use_sibcall_p && ( mips_got_symbol_type_p ( mips_classify_symbol ( fnaddr , SYMBOL_CONTEXT_LEA ) ) ) ) { cfun -> machine -> global_pointer = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM ; cfun -> machine -> must_initialize_gp_p = true ; SET_REGNO ( pic_offset_table_rtx , cfun -> machine -> global_pointer ) ; mips_emit_loadgp ( ) ; } temp1 = gen_rtx_REG ( Pmode , 2 ) ; temp2 = gen_rtx_REG ( Pmode , 3 ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != 0 ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { mips_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != 0 ) { rtx addr ; mips_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = mips_add_offset ( temp2 , temp1 , vcall_offset ) ; mips_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } if ( use_sibcall_p ) { insn = emit_call_insn ( gen_sibcall_internal ( fnaddr , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; } else { if ( TARGET_USE_PIC_FN_ADDR_REG && ! TARGET_MIPS16 && ! mips_dangerous_for_la25_p ( fnaddr ) ) temp1 = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; mips_load_call_address ( MIPS_CALL_SIBCALL , temp1 , fnaddr ) ; if ( TARGET_USE_PIC_FN_ADDR_REG && REGNO ( temp1 ) != PIC_FUNCTION_ADDR_REGNUM ) mips_emit_move ( gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) , temp1 ) ; emit_jump_insn ( gen_indirect_jump ( temp1 ) ) ; } insn = get_insns ( ) ; split_all_insns_noflow ( ) ; mips16_lay_out_constants ( true ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; } </s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Generate rtl rather than asm text in order to avoid duplicating too much logic from elsewhere .


<s> void OutgoingValueHandler :: assignValueToAddress ( unsigned ValVReg , const CCValAssign & VA ) { MachineMemOperand * MMO ; unsigned Addr = getStackAddress ( VA , MMO ) ; unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> static bool isEqual ( const MemOpKey & LHS , const MemOpKey & RHS ) { if ( RHS . Disp == PtrInfo :: getEmptyKey ( ) ) return LHS . Disp == PtrInfo :: getEmptyKey ( ) ; if ( RHS . Disp == PtrInfo :: getTombstoneKey ( ) ) return LHS . Disp == PtrInfo :: getTombstoneKey ( ) ; return LHS == RHS ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s>
InstructionCost
X86TTIImpl
::
getScalarizationOverhead
(
VectorType
*
Ty
,
const
APInt
&
DemandedElts
,
bool
Insert
,
bool
Extract
)
{
InstructionCost
Cost
=
0
;
if
(
Insert
)
{
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
Ty
)
;
MVT
MScalarTy
=
LT
.
second
.
getScalarType
(
)
;
if
(
(
MScalarTy
==
MVT
::
i16
&&
ST
->
hasSSE2
(
)
)
||
(
MScalarTy
.
isInteger
(
)
&&
ST
->
hasSSE41
(
)
)
||
(
MScalarTy
==
MVT
::
f32
&&
ST
->
hasSSE41
(
)
)
)
{
if
(
LT
.
second
.
getSizeInBits
(
)
<=
128
)
{
Cost
+=
BaseT
::
getScalarizationOverhead
(
Ty
,
DemandedElts
,
Insert
,
false
)
;
}
else
{
const
int
CostValue
=
*
LT
.
first
.
getValue
(
)
;
assert
(
CostValue
>=
0
&&
"Negative cost!"
)
;
unsigned
Num128Lanes
=
LT
.
second
.
getSizeInBits
(
)
/
128
*
CostValue
;
unsigned
NumElts
=
LT
.
second
.
getVectorNumElements
(
)
*
CostValue
;
APInt
WidenedDemandedElts
=
DemandedElts
.
zextOrSelf
(
NumElts
)
;
unsigned
Scale
=
NumElts
/
Num128Lanes
;
for
(
unsigned
I
=
0
;
I
<
NumElts
;
I
+=
Scale
)
{
APInt
Mask
=
WidenedDemandedElts
.
getBitsSet
(
NumElts
,
I
,
I
+
Scale
)
;
APInt
MaskedDE
=
Mask
&
WidenedDemandedElts
;
unsigned
Population
=
MaskedDE
.
countPopulation
(
)
;
Cost
+=
(
Population
>
0
&&
Population
!=
Scale
&&
I
%
LT
.
second
.
getVectorNumElements
(
)
!=
0
)
;
Cost
+=
Population
>
0
;
}
Cost
+=
DemandedElts
.
countPopulation
(
)
;
if
(
MScalarTy
==
MVT
::
f32
)
for
(
unsigned
i
=
0
,
e
=
cast
<
FixedVectorType
>
(
Ty
)
->
getNumElements
(
)
;
i
<
e
;
i
+=
4
)
if
(
DemandedElts
[
i
]
)
Cost
;
}
}
else
if
(
LT
.
second
.
isVector
(
)
)
{
if
(
Ty
->
isIntOrIntVectorTy
(
)
)
Cost
+=
DemandedElts
.
countPopulation
(
)
;
unsigned
NumElts
=
LT
.
second
.
getVectorNumElements
(
)
;
unsigned
Pow2Elts
=
PowerOf2Ceil
(
cast
<
FixedVectorType
>
(
Ty
)
->
getNumElements
(
)
)
;
Cost
+=
(
std
::
min
<
unsigned
>
(
NumElts
,
Pow2Elts
)
1
)
*
LT
.
first
;
}
}
if
(
Extract
)
Cost
+=
BaseT
::
getScalarizationOverhead
(
Ty
,
DemandedElts
,
false
,
Extract
)
;
return
Cost
;
}
</s>

Estimate the overhead of scalarizing an instruction .


<s> bool SystemZAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { SystemZInstPrinter :: printAddress ( MI -> getOperand ( OpNo ) . getReg ( ) , MI -> getOperand ( OpNo + 1 ) . getImm ( ) , MI -> getOperand ( OpNo + 2 ) . getReg ( ) , OS ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? DAG . getTarget ( ) . getSubtarget < AArch64Subtarget > ( ) . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * static_cast < const AArch64TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> void IA64RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( hasFP ( MF ) ) { MachineInstr * Old = I ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; DebugLoc dl = Old -> getDebugLoc ( ) ; if ( Amount != 0 ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; if ( Old -> getOpcode ( ) == IA64 :: ADJUSTCALLSTACKDOWN ) { BuildMI ( MBB , I , dl , TII . get ( IA64 :: ADDIMM22 ) , IA64 :: r12 ) . addReg ( IA64 :: r12 ) . addImm ( - Amount ) ; } else { assert ( Old -> getOpcode ( ) == IA64 :: ADJUSTCALLSTACKUP ) ; BuildMI ( MBB , I , dl , TII . get ( IA64 :: ADDIMM22 ) , IA64 :: r12 ) . addReg ( IA64 :: r12 ) . addImm ( Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI . isThumb1Only ( ) ) return false ; const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = STI . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> static void ignore_all_aliases ( HARD_REG_SET * unavailable , machine_mode mode , unsigned reg ) { add_to_hard_reg_set ( unavailable , mode , reg ) ; add_to_hard_reg_set ( unavailable , mode , reg + 16 ) ; add_to_hard_reg_set ( unavailable , mode , reg + 32 ) ; add_to_hard_reg_set ( unavailable , mode , reg + 48 ) ; } </s>

Add all aliases of the register to the unavailable register set . REG is the smallest register number that can then be used to reference its aliases . UNAVAILABLE is the hard register set to add the ignored register numbers to and MODE is the mode in which the registers would have been used .


<s> bool runOnModule ( Module & M ) { DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; bool Changed = false ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static void rs6000_set_default_type_attributes ( tree type ) { if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( "longcall" ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ; darwin_set_default_type_attributes ( type ) ; } </s>

Set longcall attributes on all functions declared when rs6000_default_long_calls is true .


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . optForSize ( ) ; MinimizeSize = STI -> optForMinSize ( ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ; return Modified ; } </s>


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { unsigned MaxSize = Size * 8 ; if ( ! Arg . IsFixed ) MaxSize = 0 ; Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ 0 ] , VA , MaxSize ) : Arg . Regs [ 0 ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ; assignValueToAddress ( ValVReg , Addr , Size , MPO , VA ) ; } </s>


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { ( void ) isDivergent ; if ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegClass MVT::v8i64 ARM::QQQQPRRegClass


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) , GISel ( ) { } </s>


<s> ScheduleHazardRecognizer :: HazardType SystemZHazardRecognizer :: getHazardType ( SUnit * m , int Stalls ) { return ( fitsIntoCurrentGroup ( m ) ? NoHazard : Hazard ) ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> static rtx strip_offset_and_salt ( rtx addr , poly_int64 * offset ) { return strip_salt ( strip_offset ( addr , offset ) ) ; } </s>

Like strip_offset , but also strip any UNSPEC_SALT_ADDR from the expression .


<s> static enum aarch64_parse_opt_result aarch64_parse_arch ( const char * to_parse , const struct processor * * res , uint64_t * isa_flags , std :: string * invalid_extension ) { const char * ext ; const struct processor * arch ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( arch = all_architectures ; arch -> name != NULL ; arch ++ ) { if ( strlen ( arch -> name ) == len && strncmp ( arch -> name , to_parse , len ) == 0 ) { uint64_t isa_temp = arch -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = arch ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the architecture struct that it selects into RES and the architectural features into ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> ~ SystemZXPLINK64Registers ( ) { } </s>

Destroys the object . Bogus destructor overriding base class destructor .


"Not expecting bundled instructions here"

Replace a StackProbe inline-stub with the actual probe code inline .


<s>
bool
AArch64PostSelectOptimize
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
FailedISel
)
)
return
false
;
assert
(
MF
.
getProperties
(
)
.
hasProperty
(
MachineFunctionProperties
::
Property
::
Selected
)
&&
"Expected a selected MF"
)
;
bool
Changed
=
false
;
for
(
auto
&
BB
:
MF
)
Changed
|=
optimizeNZCVDefs
(
BB
)
;
return
Changed
;
}
</s>


<s> bool enableEarlyIfConversion ( ) const override { return true ; } </s>

Enable the use of the early if conversion pass .


<s> int loongarch_regno_mode_ok_for_base_p ( int regno , machine_mode mode ATTRIBUTE_UNUSED , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM ) return true ; return GP_REG_P ( regno ) ; } </s>

Return true if register REGNO is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s> void X86AsmBackend :: emitInstructionBegin ( MCObjectStreamer & OS , const MCInst & Inst ) { if ( ! needAlign ( OS ) ) return ; if ( hasInterruptDelaySlot ( PrevInst ) ) return ; if ( isPrefix ( PrevInst , * MCII ) ) return ; if ( isRightAfterData ( OS . getCurrentFragment ( ) , PrevInstPosition ) ) return ; if ( ! isMacroFused ( PrevInst , Inst ) ) PendingBoundaryAlign = nullptr ; if ( PendingBoundaryAlign && OS . getCurrentFragment ( ) -> getPrevNode ( ) == PendingBoundaryAlign ) { return ; } if ( needAlignInst ( Inst ) || ( ( AlignBranchType & X86 :: AlignBranchFused ) && isFirstMacroFusibleInst ( Inst , * MCII ) ) ) { OS . insert ( PendingBoundaryAlign = new MCBoundaryAlignFragment ( AlignBoundary ) ) ; } } </s>

Give the target a chance to manipulate state related to instruction alignment ( e.g .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> SDValue PPCTargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasQPX ( ) ) || ( VT == MVT :: v4f64 && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; return DAG . getNode ( PPCISD :: FRE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> void DCPU16RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( DCPU16 :: SUB16ri ) , DCPU16 :: SP ) . addReg ( DCPU16 :: SP ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( DCPU16 :: ADD16ri ) , DCPU16 :: SP ) . addReg ( DCPU16 :: SP ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( DCPU16 :: SUB16ri ) , DCPU16 :: SP ) . addReg ( DCPU16 :: SP ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
if
(
(
VA
.
getLocReg
(
)
==
X86
::
FP0
||
VA
.
getLocReg
(
)
==
X86
::
FP1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
SDValue
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: SPERCRegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool SVEExpandLibCall :: runOnFunction ( Function & F ) { this -> F = & F ; bool Changed = false ; SmallVector < Instruction * , 4 > VectorWorkList ; SmallVector < Instruction * , 4 > MemWorkList ; SmallVector < Instruction * , 4 > StructLoadWorkList ; SmallVector < Instruction * , 4 > StructStoreWorkList ; for ( auto I = inst_begin ( F ) , E = inst_end ( F ) ; I != E ; ++ I ) { if ( isVectorLibCall ( & * I ) ) VectorWorkList . push_back ( & * I ) ; else if ( isMemLibCall ( & * I ) ) MemWorkList . push_back ( & * I ) ; else if ( isStructMemOp < LoadInst > ( & * I ) ) StructLoadWorkList . push_back ( & * I ) ; else if ( isStructMemOp < StoreInst > ( & * I ) ) StructStoreWorkList . push_back ( & * I ) ; } for ( auto I : VectorWorkList ) Changed |= ExpandCallToLoop ( cast < IntrinsicInst > ( I ) ) ; for ( auto I : MemWorkList ) Changed |= ExpandMemCallToLoop ( cast < MemIntrinsic > ( I ) ) ; for ( auto I : StructLoadWorkList ) Changed |= ExpandStructLoad ( cast < LoadInst > ( I ) ) ; for ( auto I : StructStoreWorkList ) Changed |= ExpandStructStore ( cast < StoreInst > ( I ) ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const uint32_t * LoongArchRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> static reg_class_t pa_secondary_reload ( bool in_p , rtx x , reg_class_t rclass_i , machine_mode mode , secondary_reload_info * sri ) { int regno ; enum reg_class rclass = ( enum reg_class ) rclass_i ; if ( rclass == R1_REGS ) return NO_REGS ; if ( REG_P ( x ) ) { regno = REGNO ( x ) ; if ( rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER ) return NO_REGS ; } else regno = - 1 ; if ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , 0 ) ) == MEM ) return NO_REGS ; if ( flag_pic && FP_REG_CLASS_P ( rclass ) && ( GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST_DOUBLE ) ) { switch ( mode ) { case SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; case SFmode : sri -> icode = CODE_FOR_reload_insf_r1 ; break ; case DFmode : sri -> icode = CODE_FOR_reload_indf_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } if ( pa_symbolic_expression_p ( x ) ) { if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; if ( flag_pic || ! read_only_operand ( x , VOIDmode ) ) { switch ( mode ) { case SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } } if ( regno >= FIRST_PSEUDO_REGISTER || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( ( regno >= FIRST_PSEUDO_REGISTER || regno == - 1 ) && FP_REG_CLASS_P ( rclass ) ) { if ( MEM_P ( x ) ) { x = XEXP ( x , 0 ) ; if ( IS_INDEX_ADDR_P ( x ) ) return NO_REGS ; } sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( rclass == SHIFT_REGS ) { if ( regno >= FIRST_PSEUDO_REGISTER || regno < 0 ) { sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( FP_REG_CLASS_P ( REGNO_REG_CLASS ( regno ) ) ) return GENERAL_REGS ; } if ( regno >= 0 && regno < FIRST_PSEUDO_REGISTER && REGNO_REG_CLASS ( regno ) == SHIFT_REGS && FP_REG_CLASS_P ( rclass ) ) return GENERAL_REGS ; return NO_REGS ; } </s>

Inform reload about cases where moving X with a mode MODE to or from a register in RCLASS requires an extra scratch or immediate register . Return the class needed for the immediate register .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : case vector_gather_load : if ( TARGET_P9_VECTOR ) return 3 ; if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return 5 ; else if ( INTEGRAL_TYPE_P ( elem_type ) ) { if ( TARGET_P9_VECTOR ) return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 2 ; else return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 11 ; } else return 2 ; default : gcc_unreachable ( ) ; } } </s>


<s> bool PPCAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; if ( MI -> getOperand ( OpNo ) . isReg ( ) ) printMemRegReg ( MI , OpNo ) ; else printMemRegImm ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> int pa_adjust_insn_length ( rtx_insn * insn , int length ) { rtx pat = PATTERN ( insn ) ; if ( ( unsigned int ) length >= INT_MAX ) { if ( GET_CODE ( pat ) == SEQUENCE ) insn = as_a < rtx_insn * > ( XVECEXP ( pat , 0 , 0 ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MILLI : length = pa_attr_length_millicode_call ( insn ) ; break ; case TYPE_CALL : length = pa_attr_length_call ( insn , 0 ) ; break ; case TYPE_SIBCALL : length = pa_attr_length_call ( insn , 1 ) ; break ; case TYPE_DYNCALL : length = pa_attr_length_indirect_call ( insn ) ; break ; case TYPE_SH_FUNC_ADRS : length = pa_attr_length_millicode_call ( insn ) + 20 ; break ; default : gcc_unreachable ( ) ; } } if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) ) == BLKmode ) length += compute_movmem_length ( insn ) - 4 ; else if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 0 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == MEM && XEXP ( XVECEXP ( pat , 0 , 0 ) , 1 ) == const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , 0 , 0 ) , 0 ) ) == BLKmode ) length += compute_clrmem_length ( insn ) - 4 ; else if ( JUMP_P ( insn ) && ! simplejump_p ( insn ) ) { if ( GET_CODE ( pat ) == SET && length == 4 && JUMP_LABEL ( insn ) != NULL_RTX && ! forward_branch_p ( insn ) ) length += 4 ; else if ( GET_CODE ( pat ) == PARALLEL && get_attr_type ( insn ) == TYPE_PARALLEL_BRANCH && length == 4 ) length += 4 ; else if ( GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , 0 , 1 ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) == REG && ! FP_REG_P ( XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ) && length == 4 && ! forward_branch_p ( insn ) ) length += 4 ; } return length ; } </s>

Return any length adjustment needed by INSN which already has its length computed as LENGTH . Return zero if no adjustment is necessary . For the PA : function calls , millicode calls , and backwards short conditional branches with unfilled delay slots need an adjustment by +1 ( to account for the NOP which will be inserted into the instruction stream ) . Also compute the length of an inline block move here as it is too complicated to express as a length attribute in pa.md .


<s> bool X86AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { MCAsmParser & Parser = getParser ( ) ; if ( getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) && MatchRegisterName ( Parser . getTok ( ) . getString ( ) ) ) ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; if ( ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Res = X86MCExpr :: create ( RegNo , Parser . getContext ( ) ) ; return false ; } return Parser . parsePrimaryExpr ( Res , EndLoc , nullptr ) ; } </s>


<s> bool isLegalMaskedScatter ( Type * Ty , MaybeAlign Alignment ) { return false ; } </s>

Return true if the target supports masked scatter .


<s> bool X86PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> static inline bool save_reg_p ( int r ) { return ! call_used_regs [ r ] && df_regs_ever_live_p ( r ) ; } </s>

Determine whether the REG is really used .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function & F = MF -> getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F . getCallingConv ( ) == CallingConv :: CFGuard_Check ) { return CSR_Win_AAPCS_CFGuard_Check_SaveList ; } else if ( F . getCallingConv ( ) == CallingConv :: SwiftTail ) { return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftTail_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SwiftTail_SaveList : CSR_AAPCS_SwiftTail_SaveList ) ; } else if ( F . hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F . getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


For stack frames that ca n't be allocated with a single ADDI instruction , compute the best value to initially allocate . It must at a minimum allocate enough space to spill the callee-saved registers .


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( x , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s> int ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; return getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Sparc Double-FP Move Fixer"
;
}
</s>

getPassName - Return a nice clean name for a pass .