<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev64v16qi ; break ; case V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev32v16qi ; break ; case V8QImode : gen = gen_neon_vrev32v8qi ; break ; case V8HImode : gen = gen_neon_vrev64v8hi ; break ; case V4HImode : gen = gen_neon_vrev64v4hi ; break ; case V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ; case V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s> const MCExpr * AArch64_MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . createTempSymbol ( ) ; Streamer . emitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: create ( PCSym , getContext ( ) ) ; return MCBinaryExpr :: createSub ( Res , PC , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> Optional < DestSourcePair > Mips16InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s>
unsigned
SparcMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
SparcMCExpr
*
SExpr
=
dyn_cast
<
SparcMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
evaluateAsAbsolute
(
Res
)
)
return
Res
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> static bool rs6000_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == PTImode ) return mode2 == PTImode ; if ( mode2 == PTImode ) return false ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode1 ) ) return ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ; if ( GET_MODE_CLASS ( mode1 ) == MODE_CC ) return GET_MODE_CLASS ( mode2 ) == MODE_CC ; if ( GET_MODE_CLASS ( mode2 ) == MODE_CC ) return false ; if ( PAIRED_VECTOR_MODE ( mode1 ) ) return PAIRED_VECTOR_MODE ( mode2 ) ; if ( PAIRED_VECTOR_MODE ( mode2 ) ) return false ; return true ; } </s>

Implement TARGET_MODES_TIEABLE_P . PTImode can not tie with other modes because PTImode is restricted to even GPR registers , and TImode can go in any GPR as well as VSX registers ( PR 57744 ) . Similarly , do n't allow OOmode ( vector pair , restricted to even VSX registers ) or XOmode ( vector quad , restricted to FPR registers divisible by 4 ) to tie with other modes . Altivec/VSX vector tests were moved ahead of scalar float mode , so that IEEE 128-bit floating point on VSX systems ties with other vectors .


<s> static void arm_relayout_function ( tree fndecl ) { if ( DECL_USER_ALIGN ( fndecl ) ) return ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; DECL_ALIGN ( fndecl ) = FUNCTION_BOUNDARY_P ( TREE_TARGET_OPTION ( callee_tree ) -> x_target_flags ) ; } </s>

Hook to fix function 's alignment affected by target attribute .


<s> unsigned MandarinInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { MI -> dump ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> LoadInst * getLoad ( ) { return NewLd ; } </s>

Loads are not normal binary operators : their result type is not determined by their operands , and they produce a value AND a token chain .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
VT
=
VA
.
getValVT
(
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VT
,
InFlag
)
.
getValue
(
1
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void arm_gen_unlikely_cbranch ( enum rtx_code code , machine_mode cc_mode , rtx label_ref ) { rtx x ; x = gen_rtx_fmt_ee ( code , VOIDmode , gen_rtx_REG ( cc_mode , CC_REGNUM ) , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( VOIDmode , label_ref ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } </s>

Generate RTL for a conditional branch with rtx comparison CODE in mode CC_MODE . The destination of the unlikely conditional branch is LABEL_REF .


<s> unsigned X86VectorTargetTransformInfo :: getNumberOfRegisters ( bool Vector ) const { const X86Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < X86Subtarget > ( ) ; if ( ST . is64Bit ( ) ) return 16 ; return 8 ; } </s>


"FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD "

"instructions with NOPs and floating-point store"

getPassName - Return a nice clean name for a pass .


<s> static bool indirectable_address_p ( rtx x , bool strict , bool indirect ) { if ( indirectable_constant_address_p ( x , indirect ) || BASE_REGISTER_P ( x , strict ) ) return true ; if ( GET_CODE ( x ) != PLUS || ! BASE_REGISTER_P ( XEXP ( x , 0 ) , strict ) || ( flag_pic && ! CONST_INT_P ( XEXP ( x , 1 ) ) ) ) return false ; return indirectable_constant_address_p ( XEXP ( x , 1 ) , indirect ) ; } </s>

Nonzero if X is an address which can be indirected . External symbols could be in a sharable image library , so we disallow those .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { return createPPCPostMachineScheduler ( C ) ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> bool X86RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( Reg == FramePtr && TFI -> hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> bool SHUXIAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> unsigned int rs6000_data_alignment ( tree type , unsigned int align , enum data_align how ) { if ( how != align_opt ) { if ( TREE_CODE ( type ) == VECTOR_TYPE ) { if ( ( TARGET_SPE && SPE_VECTOR_MODE ( TYPE_MODE ( type ) ) ) || ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( TYPE_MODE ( type ) ) ) ) { if ( align < 64 ) align = 64 ; } else if ( align < 128 ) align = 128 ; } else if ( TARGET_E500_DOUBLE && TREE_CODE ( type ) == REAL_TYPE && TYPE_MODE ( type ) == DFmode ) { if ( align < 64 ) align = 64 ; } } if ( how != align_abi ) { if ( TREE_CODE ( type ) == ARRAY_TYPE && TYPE_MODE ( TREE_TYPE ( type ) ) == QImode ) { if ( align < BITS_PER_WORD ) align = BITS_PER_WORD ; } } return align ; } </s>

Return alignment of TYPE . Existing alignment is ALIGN . HOW selects whether the alignment is abi mandated , optional , or both abi and optional alignment .


<s> unsigned getNumberOfRegisters ( bool Vector ) const override { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 32 ; } </s>


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( StringRef Constraint ) const { unsigned S = Constraint . size ( ) ; if ( S == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Immediate ; case 'Q' : return C_Memory ; } } else if ( S == 2 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'T' : return C_RegisterClass ; case 'U' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> unsigned AArch64RegisterBankInfo :: copyCost ( const RegisterBank & A , const RegisterBank & B , unsigned Size ) const { return RegisterBankInfo :: copyCost ( A , B , Size ) ; } </s>

Get the cost of a copy from B to A , or put differently , get the cost of A = COPY B .


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( UseVZeroUpper ) { addPass ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; ShouldPrint = true ; } addPass ( createX86ProtectReturnSupport ( ) ) ; addPass ( createX86ProtectSpillSupport ( ) ) ; addPass ( createX86EnqueueExits ( ) ) ; return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"X86 Load Value Injection (LVI) Load Hardening"


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
*
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
->
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
||
ST
.
slow3OpsLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
(
Kind
==
k_Register
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> static rtx_code_label * add_constant ( rtx x , machine_mode mode , rtx last_value ) { rtx_code_label * lab , * new_rtx ; label_ref_list_t ref , newref ; for ( int i = 0 ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , 3 ) != XINT ( pool_vector [ i ] . value , 3 ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new_rtx = 0 ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - 1 ] . value ) ) { new_rtx = gen_label_rtx ( ) ; LABEL_REFS ( new_rtx ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new_rtx ; } if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new_rtx ) pool_window_label = new_rtx ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - 1 ] . value ) ) { lab = 0 ; pool_vector [ pool_size - 1 ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == 0 ) ; if ( lab && pool_window_label ) { newref = label_ref_list_d_pool . allocate ( ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size ; pool_size ++ ; return lab ; } </s>

Add a constant to the pool and return its label .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
OptForSize
=
MF
.
getFunction
(
)
->
optForSize
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { if ( usePreRAHazardRecognizer ( ) ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , "pre-RA-sched" ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s>
void
MipsInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
Opc
=
IsN64
Mips
::
LW_P8
:
Mips
::
LW
;
else
if
(
RC
==
Mips
::
CPU64RegsRegisterClass
)
Opc
=
IsN64
Mips
::
LD_P8
:
Mips
::
LD
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
Opc
=
IsN64
Mips
::
LWC1_P8
:
Mips
::
LWC1
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
Opc
=
Mips
::
LDC1
;
else
if
(
RC
==
Mips
::
FGR64RegisterClass
)
Opc
=
IsN64
Mips
::
LDC164_P8
:
Mips
::
LDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


"Nested function trampolines not supported on CK801."

Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE . Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . Note that STATIC_CHAIN_REGNUM is t1 ( aka r12 ) on ck801 and t1 ( r13 ) otherwise .


<s> static int loongarch_fp_div_cost ( machine_mode mode ) { return mode == DFmode ? loongarch_cost -> fp_div_df : loongarch_cost -> fp_div_sf ; } </s>

Return the cost of floating-point divisions of mode MODE .


<s> rtx function_expander :: get_contiguous_base ( machine_mode mem_mode ) { rtx base = convert_to_pmode ( args [ 1 ] ) ; if ( mode_suffix_id == MODE_vnum ) { poly_int64 size = ordered_min ( GET_MODE_SIZE ( mem_mode ) , BYTES_PER_SVE_VECTOR ) ; rtx offset = gen_int_mode ( size , Pmode ) ; offset = simplify_gen_binary ( MULT , Pmode , args [ 2 ] , offset ) ; base = simplify_gen_binary ( PLUS , Pmode , base , offset ) ; } return base ; } </s>

Return the base address for a contiguous load or store function . MEM_MODE is the mode of the addressed memory .


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && SYMBOL_REF_P ( XEXP ( XEXP ( x , 0 ) , 0 ) ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) != 0 ) return true ; return TARGET_ELF && tls_referenced_p ( x ) ; } </s>


<s> static opt_scalar_float_mode arm_floatn_mode ( int n , bool extended ) { if ( ! extended && n == 16 ) { if ( arm_fp16_format == ARM_FP16_FORMAT_IEEE ) return HFmode ; return opt_scalar_float_mode ( ) ; } return default_floatn_mode ( n , extended ) ; } </s>

Implement TARGET_FLOATN_MODE . Make very sure that we do n't provide _Float16 if we are using anything other than ieee format for 16-bit floating point . Otherwise , punt to the default implementation .


<s>
MachineBasicBlock
*
Cpu0TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
Cpu0
::
ATOMIC_LOAD_ADD_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
ADDu
)
;
case
Cpu0
::
ATOMIC_LOAD_ADD_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
ADDu
)
;
case
Cpu0
::
ATOMIC_LOAD_ADD_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
ADDu
)
;
case
Cpu0
::
ATOMIC_LOAD_AND_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
AND
)
;
case
Cpu0
::
ATOMIC_LOAD_AND_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
AND
)
;
case
Cpu0
::
ATOMIC_LOAD_AND_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
AND
)
;
case
Cpu0
::
ATOMIC_LOAD_OR_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
OR
)
;
case
Cpu0
::
ATOMIC_LOAD_OR_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
OR
)
;
case
Cpu0
::
ATOMIC_LOAD_OR_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
OR
)
;
case
Cpu0
::
ATOMIC_LOAD_XOR_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
XOR
)
;
case
Cpu0
::
ATOMIC_LOAD_XOR_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
XOR
)
;
case
Cpu0
::
ATOMIC_LOAD_XOR_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
XOR
)
;
case
Cpu0
::
ATOMIC_LOAD_NAND_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
0
,
true
)
;
case
Cpu0
::
ATOMIC_LOAD_NAND_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
0
,
true
)
;
case
Cpu0
::
ATOMIC_LOAD_NAND_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
0
,
true
)
;
case
Cpu0
::
ATOMIC_LOAD_SUB_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
Cpu0
::
SUBu
)
;
case
Cpu0
::
ATOMIC_LOAD_SUB_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
Cpu0
::
SUBu
)
;
case
Cpu0
::
ATOMIC_LOAD_SUB_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
Cpu0
::
SUBu
)
;
case
Cpu0
::
ATOMIC_SWAP_I8
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
1
,
0
)
;
case
Cpu0
::
ATOMIC_SWAP_I16
:
return
emitAtomicBinaryPartword
(
MI
,
BB
,
2
,
0
)
;
case
Cpu0
::
ATOMIC_SWAP_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
4
,
0
)
;
case
Cpu0
::
ATOMIC_CMP_SWAP_I8
:
return
emitAtomicCmpSwapPartword
(
MI
,
BB
,
1
)
;
case
Cpu0
::
ATOMIC_CMP_SWAP_I16
:
return
emitAtomicCmpSwapPartword
(
MI
,
BB
,
2
)
;
case
Cpu0
::
ATOMIC_CMP_SWAP_I32
:
return
emitAtomicCmpSwap
(
MI
,
BB
,
4
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
int
AArch64TTIImpl
::
getMinMaxReductionCost
(
VectorType
*
Ty
,
VectorType
*
CondTy
,
bool
IsPairwise
,
bool
IsUnsigned
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
!
isa
<
ScalableVectorType
>
(
Ty
)
)
return
BaseT
::
getMinMaxReductionCost
(
Ty
,
CondTy
,
IsPairwise
,
IsUnsigned
,
CostKind
)
;
assert
(
(
isa
<
ScalableVectorType
>
(
Ty
)
&&
isa
<
ScalableVectorType
>
(
CondTy
)
)
&&
"Both vector needs to be scalable"
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
Ty
)
;
int
LegalizationCost
=
0
;
if
(
LT
.
first
>
1
)
{
Type
*
LegalVTy
=
EVT
(
LT
.
second
)
.
getTypeForEVT
(
Ty
->
getContext
(
)
)
;
unsigned
CmpOpcode
=
Ty
->
isFPOrFPVectorTy
(
)
Instruction
::
FCmp
:
Instruction
::
ICmp
;
LegalizationCost
=
getCmpSelInstrCost
(
CmpOpcode
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
+
getCmpSelInstrCost
(
Instruction
::
Select
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
;
LegalizationCost
*=
LT
.
first
1
;
}
return
LegalizationCost
+
2
;
}
</s>

Try to calculate op costs for min/max reduction operations .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; PPCSubTarget = & MF . getSubtarget < PPCSubtarget > ( ) ; Subtarget = & MF . getSubtarget < PPCSubtarget > ( ) ; PPCLowering = Subtarget -> getTargetLowering ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } CASE_OBF_MASK ( 0 ) CASE_OBF_MASK ( 1 ) CASE_OBF_MASK ( 2 ) CASE_OBF_MASK ( 3 ) CASE_OBF_MASK ( 4 ) CASE_OBF_MASK ( 5 ) CASE_OBF_MASK ( 6 ) CASE_OBF_MASK ( 7 ) CASE_OBF_MASK ( 8 ) CASE_OBF_MASK ( 9 ) case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> virtual const PPCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : 0 ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : 0 ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : 0 ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : 0 ) | ( ( TARGET_POWERPC64 ) ? RS6000_BTM_POWERPC64 : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : 0 ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : 0 ) | ( ( TARGET_FLOAT128_HW ) ? RS6000_BTM_FLOAT128_HW : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


"No ISEL instructions in this function\n"


<s> bool MipsRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; unsigned FP = Subtarget . isGP32bit ( ) ? Mips :: FP : Mips :: FP_64 ; unsigned BP = Subtarget . isGP32bit ( ) ? Mips :: S7 : Mips :: S7_64 ; if ( ! Subtarget . hasStandardEncoding ( ) ) return false ; if ( ! MF . getRegInfo ( ) . canReserveReg ( FP ) ) return false ; if ( Subtarget . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MF . getRegInfo ( ) . canReserveReg ( BP ) ; } </s>

True if the stack can be realigned for the target .


Given the pattern ( X & ( C l > > / < < Y ) ) ==/ ! = 0 return true if it should be transformed into : ( ( X < < /l > > Y ) & C ) ==/ ! = 0 WARNING : if ' X ' is a constant , the fold may deadlock ! FIXME : we could avoid passing XC , but we ca n't use isConstOrConstSplat ( ) here because it can end up being not linked in .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_VE
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
OutVal
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
ZExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
AExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
}
assert
(
!
VA
.
needsCustom
(
)
&&
"Unexpected custom lowering"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVal
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { Changed |= SimplifyInstructionsInBlock ( & BB ) ; for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 0 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Instruction * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( L -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Instruction * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( S -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> tree memory_scalar_type ( const function_instance & fi ) const override { return fi . scalar_type ( 0 ) ; } </s>

If the function addresses memory , return the type of a single scalar memory element .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> static void mips_expand_vi_loongson_one_pinsrh ( rtx target , rtx vals , unsigned one_var ) { mips_expand_vi_constant ( V4HImode , 4 , target , vals ) ; emit_insn ( gen_vec_setv4hi ( target , target , XVECEXP ( vals , 0 , one_var ) , GEN_INT ( one_var ) ) ) ; } </s>

A subroutine of mips_expand_vec_init , expand via pinsrh .


<s> void aarch64_init_builtin_rsqrt ( void ) { tree fndecl = NULL ; tree ftype = NULL ; tree V2SF_type_node = build_vector_type ( float_type_node , 2 ) ; tree V2DF_type_node = build_vector_type ( double_type_node , 2 ) ; tree V4SF_type_node = build_vector_type ( float_type_node , 4 ) ; struct builtin_decls_data { tree type_node ; const char * builtin_name ; int function_code ; } ; builtin_decls_data bdda [ ] = { { double_type_node , "__builtin_aarch64_rsqrt_df" , AARCH64_BUILTIN_RSQRT_DF } , { float_type_node , "__builtin_aarch64_rsqrt_sf" , AARCH64_BUILTIN_RSQRT_SF } , { V2DF_type_node , "__builtin_aarch64_rsqrt_v2df" , AARCH64_BUILTIN_RSQRT_V2DF } , { V2SF_type_node , "__builtin_aarch64_rsqrt_v2sf" , AARCH64_BUILTIN_RSQRT_V2SF } , { V4SF_type_node , "__builtin_aarch64_rsqrt_v4sf" , AARCH64_BUILTIN_RSQRT_V4SF } } ; builtin_decls_data * bdd = bdda ; builtin_decls_data * bdd_end = bdd + ( sizeof ( bdda ) / sizeof ( builtin_decls_data ) ) ; for ( ; bdd < bdd_end ; bdd ++ ) { ftype = build_function_type_list ( bdd -> type_node , bdd -> type_node , NULL_TREE ) ; fndecl = add_builtin_function ( bdd -> builtin_name , ftype , bdd -> function_code , BUILT_IN_MD , NULL , NULL_TREE ) ; aarch64_builtin_decls [ bdd -> function_code ] = fndecl ; } } </s>

Add builtins for reciprocal square root .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( ( uint32_t ) Fixup . getKind ( ) == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; AArch64MCExpr :: VariantKind RefKind = static_cast < AArch64MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; AArch64MCExpr :: VariantKind SymLoc = AArch64MCExpr :: getSymbolLoc ( RefKind ) ; if ( ( uint32_t ) Fixup . getKind ( ) == AArch64 :: fixup_aarch64_ldr_pcrel_imm19 && SymLoc == AArch64MCExpr :: VK_GOT ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> size_type empty ( ) const { return V . none ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

Reset options between modes that the user has specified .


<s> static rtx get_next_active_insn ( rtx insn , rtx tail ) { if ( insn == NULL_RTX || insn == tail ) return NULL_RTX ; while ( 1 ) { insn = NEXT_INSN ( insn ) ; if ( insn == NULL_RTX || insn == tail ) return NULL_RTX ; if ( CALL_P ( insn ) || JUMP_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && INSN_CODE ( insn ) != CODE_FOR_stack_tie ) ) break ; } return insn ; } </s>

Return the next insn after INSN that is found before TAIL is reached , skipping any `` non-active '' insns - insns that will not actually occupy an issue slot . Return NULL_RTX if such an insn is not found .


<s> bool is_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , "interrupt" ) ; } </s>

Returns true if the provided function has the `` interrupt '' attribute .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else { UsedSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; } unsigned FrameSizeMinusRBP = alignTo ( CSSize + UsedSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> int legitimate_constant_address_p ( rtx x ) { return ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST || GET_CODE ( x ) == HIGH ) ; } </s>

1 if X is an rtx for a constant that is a valid address .


<s> static void update_total_code_bytes ( int nbytes ) { if ( ( TARGET_PORTABLE_RUNTIME || ! TARGET_GAS || ! TARGET_SOM ) && ! IN_NAMED_SECTION_P ( cfun -> decl ) ) { if ( INSN_ADDRESSES_SET_P ( ) ) { unsigned long old_total = total_code_bytes ; total_code_bytes += nbytes ; if ( old_total > total_code_bytes ) total_code_bytes = - 1 ; } else total_code_bytes = - 1 ; } } </s>

Update the total code bytes output to the text section .


<s> static void mips_macc_chains_reorder ( rtx * ready , int nready ) { int i , j ; if ( mips_macc_chains_last_hilo != 0 ) for ( i = nready - 1 ; i >= 0 ; i -- ) if ( mips_linked_madd_p ( mips_macc_chains_last_hilo , ready [ i ] ) ) { for ( j = nready - 1 ; j > i ; j -- ) if ( recog_memoized ( ready [ j ] ) >= 0 && get_attr_may_clobber_hilo ( ready [ j ] ) ) { mips_promote_ready ( ready , i , j ) ; break ; } break ; } } </s>

A TUNE_MACC_CHAINS helper function . Search ready queue READY , which has NREADY elements , looking for a multiply-add or multiply-subtract instruction that is cumulative with mips_macc_chains_last_hilo . If there is one , promote it ahead of anything else that might clobber hi or lo .


<s> static bool loongarch_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; return false ; } </s>


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> bool mips_stack_address_p ( rtx x , machine_mode mode ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && addr . reg == stack_pointer_rtx ) ; } </s>

Return true if X is a legitimate $ sp-based address for mode MDOE .


<s> bool ARMTargetLowering :: isFNegFree ( EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case MVT :: f16 : return Subtarget -> hasFullFP16 ( ) ; } return false ; } </s>

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


<s>
static
void
adjust_splat
(
rtx_insn
*
insn
)
{
rtx
body
=
PATTERN
(
insn
)
;
rtx
unspec
=
XEXP
(
body
,
1
)
;
int
half_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
unspec
)
)
>>
1
;
int
lane
=
INTVAL
(
XVECEXP
(
unspec
,
0
,
1
)
)
;
lane
=
lane
>=
half_elts
lane
half_elts
:
lane
+
half_elts
;
XVECEXP
(
unspec
,
0
,
1
)
=
GEN_INT
(
lane
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lane for splat %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a vector direct-splat operation , adjust the index of the source lane to account for the doubleword swap .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createLEGELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
OperandMatchResultTy
LoongArchAsmParser
::
tryParseRegister
(
unsigned
&
RegNo
,
SMLoc
&
StartLoc
,
SMLoc
&
EndLoc
)
{
llvm_unreachable
(
"Unimplemented function."
)
;
}
</s>

tryParseRegister - parse one register if possible

LoongArch
LoongArch
"Unimplemented function."


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SIC Del Useless jump"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> Align getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { const Align ABIAlign ( DL . getABITypeAlignment ( ArgTy ) ) ; if ( ArgTy -> isVectorTy ( ) ) return std :: min ( ABIAlign , Align ( 8 ) ) ; return ABIAlign ; } </s>

Return the correct alignment for the current calling convention .


<s> void F2003fInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( F2003f :: KRZrm ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addReg ( 0 ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void rs6000_emit_cbranch ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx , loc_ref ; condition_rtx = rs6000_generate_compare ( operands [ 0 ] , mode ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


"builtin ID '%s' not found in bif file.\n"

Parse one two-line entry in the overload file .


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return nullptr ; } </s>

If the information for the register banks is available , return it .


<s> static bool rs6000_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { unsigned from_size = GET_MODE_SIZE ( from ) ; unsigned to_size = GET_MODE_SIZE ( to ) ; if ( from_size != to_size ) { enum reg_class xclass = ( TARGET_VSX ) ? VSX_REGS : FLOAT_REGS ; if ( reg_classes_intersect_p ( xclass , rclass ) ) { unsigned to_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , to ) ; unsigned from_nregs = hard_regno_nregs ( FIRST_FPR_REGNO , from ) ; bool to_float128_vector_p = FLOAT128_VECTOR_P ( to ) ; bool from_float128_vector_p = FLOAT128_VECTOR_P ( from ) ; if ( to_float128_vector_p && from_float128_vector_p ) return true ; else if ( to_float128_vector_p || from_float128_vector_p ) return false ; if ( ! BYTES_BIG_ENDIAN && ( to == TDmode || from == TDmode ) ) return false ; if ( ( to == DDmode && from == SDmode ) || ( to == SDmode && from == DDmode ) ) return true ; if ( from_size < 8 || to_size < 8 ) return false ; if ( from_size == 8 && ( 8 * to_nregs ) != to_size ) return false ; if ( to_size == 8 && ( 8 * from_nregs ) != from_size ) return false ; return true ; } else return true ; } if ( TARGET_VSX && VSX_REG_CLASS_P ( rclass ) ) { unsigned num_regs = ( from_size + 15 ) / 16 ; if ( hard_regno_nregs ( FIRST_FPR_REGNO , to ) > num_regs || hard_regno_nregs ( FIRST_FPR_REGNO , from ) > num_regs ) return false ; return ( from_size == 8 || from_size == 16 ) ; } if ( TARGET_ALTIVEC && rclass == ALTIVEC_REGS && ( ALTIVEC_VECTOR_MODE ( from ) + ALTIVEC_VECTOR_MODE ( to ) ) == 1 ) return false ; return true ; } </s>


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
CSR_Darwin_AArch64_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> void SHUXIInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( SHUXI :: PUSH ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const LC2200Subtarget * getSubtargetImpl ( const Function & ) const override { return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool arm_have_conditional_execution ( void ) { bool has_cond_exec , enable_ifcvt_trans ; has_cond_exec = ! TARGET_THUMB1 ; enable_ifcvt_trans = TARGET_COND_ARITH && ! reload_completed ; return has_cond_exec && ! enable_ifcvt_trans ; } </s>

Implement the TARGET_HAVE_CONDITIONAL_EXECUTION hook . All modes except THUMB1 have conditional execution . If we have conditional arithmetic , return false before reload to enable some ifcvt transformations .


<s> static inline built_in_function complex_divide_builtin_code ( machine_mode mode ) { gcc_assert ( IN_RANGE ( mode , MIN_MODE_COMPLEX_FLOAT , MAX_MODE_COMPLEX_FLOAT ) ) ; int func = BUILT_IN_COMPLEX_DIV_MIN + mode - MIN_MODE_COMPLEX_FLOAT ; return ( built_in_function ) func ; } </s>

Internal function to return the built-in function id for the complex divide operation for a given mode .


<s> static void rs6000_set_handled_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> fpr_is_wrapped_separately [ i - 32 ] = true ; if ( bitmap_bit_p ( components , 0 ) ) cfun -> machine -> lr_is_wrapped_separately = true ; } </s>


<s>
static
void
arm_asm_trampoline_template
(
FILE
*
f
)
{
if
(
TARGET_ARM
)
{
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
if
(
TARGET_THUMB2
)
{
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
{
ASM_OUTPUT_ALIGN
(
f
,
2
)
;
fprintf
(
f
,
"\t.code\t16\n"
)
;
fprintf
(
f
,
".Ltrampoline_start:\n"
)
;
asm_fprintf
(
f
,
"\tpush\t{r0, r1}\n"
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tmov\t%r, r0\n"
,
STATIC_CHAIN_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tstr\tr0, [%r, #4]\n"
,
SP_REGNUM
)
;
asm_fprintf
(
f
,
"\tpop\t{r0, %r}\n"
,
PC_REGNUM
)
;
}
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
}
</s>

Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . On the ARM , ( if r8 is the static chain regnum , and remembering that referencing pc adds an offset of 8 ) the trampoline looks like : ldr r8 , [ pc , # 0 ] ldr pc , [ pc ] .word static chain value .word function 's address XXX FIXME : When the trampoline returns , r8 will be clobbered .


<s> static bool sh_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align , enum by_pieces_operation op , bool speed_p ) { switch ( op ) { case MOVE_BY_PIECES : return move_by_pieces_ninsns ( size , align , MOVE_MAX_PIECES + 1 ) < ( ! speed_p ? 2 : ( align >= 32 ) ? 16 : 2 ) ; case STORE_BY_PIECES : case SET_BY_PIECES : return move_by_pieces_ninsns ( size , align , STORE_MAX_PIECES + 1 ) < ( ! speed_p ? 2 : ( align >= 32 ) ? 16 : 2 ) ; default : return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; } } </s>


<s> static bool is_end_basic_block ( enum dispatch_group group ) { return group == disp_branch ; } </s>

This function returns true if a branch is detected . End of a basic block does not have to be a branch , but here we assume only branches end a window .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x60000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"%s only supports non-pic code on M-profile targets with the "

Check any incompatible options that the user has specified .


<s> uint64_t MipsFrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * MF . getTarget ( ) . getRegisterInfo ( ) ; int64_t Offset = 0 ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != 0 ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const uint16_t * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = 0 , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = RoundUpToAlignment ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = RoundUpToAlignment ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return RoundUpToAlignment ( Offset , getStackAlignment ( ) ) ; } </s>

Estimate and return the size of the stack frame .


<s> static int ia64_adjust_cost_2 ( rtx_insn * insn , int dep_type1 , rtx_insn * dep_insn , int cost , dw_t dw ) { enum reg_note dep_type = ( enum reg_note ) dep_type1 ; enum attr_itanium_class dep_class ; enum attr_itanium_class insn_class ; insn_class = ia64_safe_itanium_class ( insn ) ; dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return 0 ; if ( dw == MIN_DEP_WEAK ) return PARAM_VALUE ( PARAM_SCHED_MEM_TRUE_DEP_COST ) ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF ) return 0 ; else return cost ; } if ( dep_type != REG_DEP_OUTPUT ) return cost ; if ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF ) return 0 ; return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN . COST is the current cost , DW is dependency weakness .


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) { if ( ! VECTOR_MODE_P ( mode ) ) return cost ; if ( GET_MODE_BITSIZE ( mode ) == 128 && TARGET_SSE_SPLIT_REGS ) return cost * GET_MODE_BITSIZE ( mode ) / 64 ; else if ( GET_MODE_BITSIZE ( mode ) > 128 && TARGET_AVX256_SPLIT_REGS ) return cost * GET_MODE_BITSIZE ( mode ) / 128 ; else if ( GET_MODE_BITSIZE ( mode ) > 256 && TARGET_AVX512_SPLIT_REGS ) return cost * GET_MODE_BITSIZE ( mode ) / 256 ; return cost ; } </s>

Return cost of vector operation in MODE given that scalar version has COST . If PARALLEL is true assume that CPU has more than one unit performing the operation .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const unsigned ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: GP , Mips :: SP , Mips :: FP , Mips :: RA } ; static const unsigned ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: GP_64 , Mips :: SP_64 , Mips :: FP_64 , Mips :: RA_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegisterClass -> begin ( ) ; Reg != Mips :: AFGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegisterClass -> begin ( ) ; Reg != Mips :: CPU64RegsRegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegisterClass -> begin ( ) ; Reg != Mips :: FGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const TargetRegisterClass * DCPU16RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & DCPU16 :: GR16RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64FrameLowering
*
TFI
=
static_cast
<
const
AArch64FrameLowering
*
>
(
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool CAHPAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isReg ( ) ) return true ; OS << "0(" << CAHPInstPrinter :: getRegisterName ( MO . getReg ( ) ) << ")" ; return false ; } return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo , ExtraCode , OS ) ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
static
void
initialize_aarch64_code_model
(
void
)
{
if
(
flag_pic
)
{
switch
(
aarch64_cmodel_var
)
{
case
AARCH64_CMODEL_TINY
:
aarch64_cmodel
=
AARCH64_CMODEL_TINY_PIC
;
break
;
case
AARCH64_CMODEL_SMALL
:
aarch64_cmodel
=
AARCH64_CMODEL_SMALL_PIC
;
break
;
case
AARCH64_CMODEL_LARGE
:
sorry
(
"code model %qs with -f%s"
,
"large"
,
flag_pic
>
1
"PIC"
:
"pic"
)
;
default
:
gcc_unreachable
(
)
;
}
}
else
aarch64_cmodel
=
aarch64_cmodel_var
;
}
</s>

A checking mechanism for the implementation of the various code models .

aarch64
"code model %qs with -f%s"
"large"
1
"PIC"
"pic"


Probe a range of stack addresses from REG1 to REG3 inclusive . These are addresses , not offsets . REG2 contains the backchain that must be stored into * sp at each allocation . This is subtly different than the Ada probing above in that it tries hard to prevent attacks that jump the stack guard . Thus , it is never allowed to allocate more than PROBE_INTERVAL bytes of stack space without a suitable probe .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
bool
NeedShadowCallStackProlog
=
false
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
,
NeedShadowCallStackProlog
)
;
auto
EmitMI
=
[
&
]
(
const
RegPairInfo
&
RPI
)
{
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
LLVM_DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
;
if
(
ReverseCSRRestoreSeq
)
for
(
const
RegPairInfo
&
RPI
:
reverse
(
RegPairs
)
)
EmitMI
(
RPI
)
;
else
for
(
const
RegPairInfo
&
RPI
:
RegPairs
)
EmitMI
(
RPI
)
;
if
(
NeedShadowCallStackProlog
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AArch64
::
LDRXpre
)
)
.
addReg
(
AArch64
::
X18
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
X18
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool SparcPassConfig :: addPreEmitPass ( ) { PM -> add ( createSparcFPMoverPass ( getSparcTargetMachine ( ) ) ) ; PM -> add ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
void
dump
(
SelectionDAG
*
DAG
=
nullptr
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
DAG
)
;
else
dbgs
(
)
<<
"nul\n"
;
if
(
BaseType
==
FrameIndexBase
)
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
;
dbgs
(
)
<<
" Scale "
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
NegateIndex
)
dbgs
(
)
<<
"negate "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
DAG
)
;
else
dbgs
(
)
<<
"nul\n"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" MCSym "
;
if
(
MCSym
)
dbgs
(
)
<<
MCSym
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Alignment
.
value
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul\n"
" Base.FrameIndex "
" Scale "
"IndexReg "
"negate "
"nul\n"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" MCSym "
"nul"
" JT"
" Align"


<s> void ix86_emit_i387_log1p ( rtx op0 , rtx op1 ) { rtx_code_label * label1 = gen_label_rtx ( ) ; rtx_code_label * label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx tmp2 = gen_reg_rtx ( XFmode ) ; rtx test ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; test = gen_rtx_GE ( VOIDmode , tmp , const_double_from_real_value ( REAL_VALUE_ATOF ( "0.29289321881345247561810596348408353" , XFmode ) , XFmode ) ) ; emit_jump_insn ( gen_cbranchxf4 ( test , XEXP ( test , 0 ) , XEXP ( test , 1 ) , label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xp1xf3_i387 ( op0 , op1 , tmp2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( tmp , op1 , tmp ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xxf3_i387 ( op0 , tmp , tmp2 ) ) ; emit_label ( label2 ) ; } </s>

Output code to perform a log1p XFmode calculation .


<s> const MCSection * X86ELFMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , MCSectionELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s>
void
MipsAsmPrinter
::
emitDebugValue
(
const
MCExpr
*
Value
,
unsigned
Size
)
const
{
if
(
auto
*
MipsExpr
=
dyn_cast
<
MipsMCExpr
>
(
Value
)
)
{
if
(
MipsExpr
&&
MipsExpr
->
getKind
(
)
==
MipsMCExpr
::
MEK_DTPREL
)
{
switch
(
Size
)
{
case
4
:
OutStreamer
->
emitDTPRel32Value
(
MipsExpr
->
getSubExpr
(
)
)
;
break
;
case
8
:
OutStreamer
->
emitDTPRel64Value
(
MipsExpr
->
getSubExpr
(
)
)
;
break
;
default
:
llvm_unreachable
(
"Unexpected size of expression value."
)
;
}
return
;
}
}
AsmPrinter
::
emitDebugValue
(
Value
,
Size
)
;
}
</s>

Emit the directive and value for debug thread local expression .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
4
Mips
8
Mips
"Unexpected size of expression value."


<s>
const
MipsMCExpr
*
MipsMCExpr
::
Create
(
MCSymbolRefExpr
::
VariantKind
VK
,
const
MCExpr
*
Expr
,
MCContext
&
Ctx
)
{
VariantKind
Kind
;
switch
(
VK
)
{
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
Kind
=
VK_Mips_LO
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
Kind
=
VK_Mips_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHER
:
Kind
=
VK_Mips_HIGHER
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHEST
:
Kind
=
VK_Mips_HIGHEST
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_IJMP_HI
:
Kind
=
VK_Mips_IJMP_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_IJMP_LO
:
Kind
=
VK_Mips_IJMP_LO
;
break
;
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
return
new
(
Ctx
)
MipsMCExpr
(
Kind
,
Expr
)
;
}
</s>

Construct a unary instruction , given the opcode and an operand .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid kind!"
Mips


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


<s> StringRef getType ( ) { return CurType ; } </s>

Overload to return most specific vector type .


<s> static bool sh_can_follow_jump ( const rtx_insn * branch1 , const rtx_insn * branch2 ) { if ( TARGET_SH1 && flag_reorder_blocks_and_partition && simplejump_p ( branch2 ) && CROSSING_JUMP_P ( branch2 ) ) return false ; if ( flag_expensive_optimizations && simplejump_p ( branch2 ) ) { rtx dest = XEXP ( SET_SRC ( single_set ( branch2 ) ) , 0 ) ; rtx_insn * insn ; int distance ; for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = PREV_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = NEXT_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } } return false ; } </s>

Return true if it 's possible to redirect BRANCH1 to the destination of an unconditional jump BRANCH2 . We only want to do this if the resulting branch will have a short displacement .


<s> const uint32_t * TOYRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isSVR4ABI ( ) ) { if ( Subtarget . isPPC64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> virtual const KudeyarSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool mips_offset_within_alignment_p ( rtx x , HOST_WIDE_INT offset ) { HOST_WIDE_INT align ; align = SYMBOL_REF_DECL ( x ) ? DECL_ALIGN_UNIT ( SYMBOL_REF_DECL ( x ) ) : 1 ; return IN_RANGE ( offset , 0 , align - 1 ) ; } </s>

Return true if OFFSET is within the range [ 0 , ALIGN ) , where ALIGN is the alignment in bytes of SYMBOL_REF X .


<s> unsigned Cpu0FunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; if ( FixGlobalBaseReg ) return GlobalBaseReg = Cpu0 :: GP ; const TargetRegisterClass * RC ; RC = ( const TargetRegisterClass * ) & Cpu0 :: CPURegsRegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static inline int inline_memory_move_cost ( machine_mode mode , enum reg_class regclass , int in ) { int cost ; if ( FLOAT_CLASS_P ( regclass ) ) { int index ; switch ( mode ) { case E_SFmode : index = 0 ; break ; case E_DFmode : index = 1 ; break ; case E_XFmode : index = 2 ; break ; default : return 100 ; } if ( in == 2 ) return MAX ( ix86_cost -> fp_load [ index ] , ix86_cost -> fp_store [ index ] ) ; return in ? ix86_cost -> fp_load [ index ] : ix86_cost -> fp_store [ index ] ; } if ( SSE_CLASS_P ( regclass ) ) { int index = sse_store_index ( mode ) ; if ( index == - 1 ) return 100 ; if ( in == 2 ) return MAX ( ix86_cost -> sse_load [ index ] , ix86_cost -> sse_store [ index ] ) ; return in ? ix86_cost -> sse_load [ index ] : ix86_cost -> sse_store [ index ] ; } if ( MMX_CLASS_P ( regclass ) ) { int index ; switch ( GET_MODE_SIZE ( mode ) ) { case 4 : index = 0 ; break ; case 8 : index = 1 ; break ; default : return 100 ; } if ( in == 2 ) return MAX ( ix86_cost -> mmx_load [ index ] , ix86_cost -> mmx_store [ index ] ) ; return in ? ix86_cost -> mmx_load [ index ] : ix86_cost -> mmx_store [ index ] ; } switch ( GET_MODE_SIZE ( mode ) ) { case 1 : if ( Q_CLASS_P ( regclass ) || TARGET_64BIT ) { if ( ! in ) return ix86_cost -> int_store [ 0 ] ; if ( TARGET_PARTIAL_REG_DEPENDENCY && optimize_function_for_speed_p ( cfun ) ) cost = ix86_cost -> movzbl_load ; else cost = ix86_cost -> int_load [ 0 ] ; if ( in == 2 ) return MAX ( cost , ix86_cost -> int_store [ 0 ] ) ; return cost ; } else { if ( in == 2 ) return MAX ( ix86_cost -> movzbl_load , ix86_cost -> int_store [ 0 ] + 4 ) ; if ( in ) return ix86_cost -> movzbl_load ; else return ix86_cost -> int_store [ 0 ] + 4 ; } break ; case 2 : if ( in == 2 ) return MAX ( ix86_cost -> int_load [ 1 ] , ix86_cost -> int_store [ 1 ] ) ; return in ? ix86_cost -> int_load [ 1 ] : ix86_cost -> int_store [ 1 ] ; default : if ( in == 2 ) cost = MAX ( ix86_cost -> int_load [ 2 ] , ix86_cost -> int_store [ 2 ] ) ; else if ( in ) cost = ix86_cost -> int_load [ 2 ] ; else cost = ix86_cost -> int_store [ 2 ] ; return cost * CEIL ( ( int ) GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } } </s>

Return the cost of moving data of mode M between a register and memory . A value of 2 is the default ; this cost is relative to those in ` REGISTER_MOVE_COST ' . This function is used extensively by register_move_cost that is used to build tables at startup . Make it inline in this case . When IN is 2 , return maximum of in and out move cost . If moving between registers and memory is more expensive than between two registers , you should define this macro to express the relative cost . Model also increased moving costs of QImode registers in non Q_REGS classes .


<s> static void ix86_init_large_pic_reg ( unsigned int tmp_regno ) { rtx_code_label * label ; rtx tmp_reg ; gcc_assert ( Pmode == DImode ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; LABEL_PRESERVE_P ( label ) = 1 ; tmp_reg = gen_rtx_REG ( Pmode , tmp_regno ) ; gcc_assert ( REGNO ( pic_offset_table_rtx ) != tmp_regno ) ; emit_insn ( gen_set_rip_rex64 ( pic_offset_table_rtx , label ) ) ; emit_insn ( gen_set_got_offset_rex64 ( tmp_reg , label ) ) ; emit_insn ( gen_add2_insn ( pic_offset_table_rtx , tmp_reg ) ) ; const char * name = LABEL_NAME ( label ) ; PUT_CODE ( label , NOTE ) ; NOTE_KIND ( label ) = NOTE_INSN_DELETED_LABEL ; NOTE_DELETED_LABEL_NAME ( label ) = name ; } </s>


<s> void F2003fMCAsmStreamer :: emitExplicitComments ( ) { StringRef Comments = ExplicitCommentToEmit ; if ( ! Comments . empty ( ) ) OS << Comments ; ExplicitCommentToEmit . clear ( ) ; } </s>


<s> void DLXInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annotation , const MCSubtargetInfo & ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"AArch64 load / store optimization pass"

getPassName - Return a nice clean name for a pass .


<s> static bool ia64_function_value_regno_p ( const unsigned int regno ) { return ( ( regno >= GR_RET_FIRST && regno <= GR_RET_LAST ) || ( regno >= FR_RET_FIRST && regno <= FR_RET_LAST ) ) ; } </s>

Worker function for FUNCTION_VALUE_REGNO_P .


<s> bool arm_vector_mode_supported_p ( enum machine_mode mode ) { if ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 Machine Code Emitter"
;
}
</s>


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static int ia64_issue_rate ( ) { return 6 ; } </s>

Return the maximum number of instructions a cpu can issue .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return Subtarget . inMips16Mode ( ) ? nullptr : & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static void aarch64_emit_store_exclusive ( machine_mode mode , rtx bval , rtx mem , rtx rval , rtx model_rtx ) { if ( mode == TImode ) emit_insn ( gen_aarch64_store_exclusive_pair ( bval , mem , operand_subword ( rval , 0 , 0 , TImode ) , operand_subword ( rval , 1 , 0 , TImode ) , model_rtx ) ) ; else emit_insn ( gen_aarch64_store_exclusive ( mode , bval , mem , rval , model_rtx ) ) ; } </s>


<s> static bool csky_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CSKY_CC_REGNUM ; * p2 = INVALID_REGNUM ; return true ; } </s>


<s> bool LEGRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static bool mips_callee_copies ( cumulative_args_t , const function_arg_info & arg ) { return mips_abi == ABI_EABI && arg . named ; } </s>


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI , OS ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>


<s> static void ix86_init_tm_builtins ( void ) { enum ix86_builtin_func_type ftype ; const struct builtin_description * d ; size_t i ; tree decl ; tree attrs_load , attrs_type_load , attrs_store , attrs_type_store ; tree attrs_log , attrs_type_log ; if ( ! flag_tm ) return ; if ( ! builtin_decl_explicit_p ( BUILT_IN_TM_LOAD_1 ) ) return ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOAD_1 ) ; attrs_load = DECL_ATTRIBUTES ( decl ) ; attrs_type_load = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_STORE_1 ) ; attrs_store = DECL_ATTRIBUTES ( decl ) ; attrs_type_store = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOG ) ; attrs_log = DECL_ATTRIBUTES ( decl ) ; attrs_type_log = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; for ( i = 0 , d = bdesc_tm ; i < ARRAY_SIZE ( bdesc_tm ) ; i ++ , d ++ ) { if ( ( d -> mask & ix86_isa_flags ) != 0 || ( ( d -> mask & OPTION_MASK_ISA_MMX ) != 0 && TARGET_MMX_WITH_SSE ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type , attrs , attrs_type ; enum built_in_function code = ( enum built_in_function ) d -> code ; ftype = ( enum ix86_builtin_func_type ) d -> flag ; type = ix86_get_builtin_func_type ( ftype ) ; if ( BUILTIN_TM_LOAD_P ( code ) ) { attrs = attrs_load ; attrs_type = attrs_type_load ; } else if ( BUILTIN_TM_STORE_P ( code ) ) { attrs = attrs_store ; attrs_type = attrs_type_store ; } else { attrs = attrs_log ; attrs_type = attrs_type_log ; } decl = add_builtin_function ( d -> name , type , code , BUILT_IN_NORMAL , d -> name + strlen ( "__builtin_" ) , attrs ) ; decl_attributes ( & TREE_TYPE ( decl ) , attrs_type , ATTR_FLAG_BUILT_IN ) ; set_builtin_decl ( code , decl , false ) ; } } } </s>

Initialize the transactional memory vector load/store builtins .


<s> const MCPhysReg * PPCTargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { PPC :: X12 , PPC :: LR8 , PPC :: CTR8 , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> static void loongarch_emit_int_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 ) { static const enum rtx_code mag_comparisons [ ] [ 2 ] = { { LEU , LTU } , { GTU , GEU } , { LE , LT } , { GT , GE } } ; if ( splittable_const_int_operand ( * op1 , VOIDmode ) ) { HOST_WIDE_INT rhs = INTVAL ( * op1 ) ; if ( * code == EQ || * code == NE ) { if ( IMM12_OPERAND ( - rhs ) ) { * op0 = loongarch_force_binary ( GET_MODE ( * op0 ) , PLUS , * op0 , GEN_INT ( - rhs ) ) ; * op1 = const0_rtx ; } } else { for ( size_t i = 0 ; i < ARRAY_SIZE ( mag_comparisons ) ; i ++ ) { HOST_WIDE_INT new_rhs ; bool increment = * code == mag_comparisons [ i ] [ 0 ] ; bool decrement = * code == mag_comparisons [ i ] [ 1 ] ; if ( ! increment && ! decrement ) continue ; if ( ( increment && rhs == HOST_WIDE_INT_MAX ) || ( decrement && rhs == HOST_WIDE_INT_MIN ) ) break ; new_rhs = rhs + ( increment ? 1 : - 1 ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) ) { * op1 = GEN_INT ( new_rhs ) ; * code = mag_comparisons [ i ] [ increment ] ; } break ; } } } loongarch_extend_comparands ( * code , op0 , op1 ) ; * op0 = force_reg ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = force_reg ( word_mode , * op1 ) ; } </s>

Convert a comparison into something that can be used in a branch . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update them to describe the final comparison .


<s> bool ARM64InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , const SmallVectorImpl < MachineOperand > & Cond , unsigned TrueReg , unsigned FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; unsigned ExtraCondLat = Cond . size ( ) != 1 ; if ( ARM64 :: GPR64allRegClass . hasSubClassEq ( RC ) || ARM64 :: GPR32allRegClass . hasSubClassEq ( RC ) ) { CondCycles = 1 + ExtraCondLat ; TrueCycles = FalseCycles = 1 ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = 0 ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = 0 ; return true ; } if ( ARM64 :: FPR64RegClass . hasSubClassEq ( RC ) || ARM64 :: FPR32RegClass . hasSubClassEq ( RC ) ) { CondCycles = 5 + ExtraCondLat ; TrueCycles = FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> int arm_apply_result_size ( void ) { int size = 16 ; if ( TARGET_32BIT ) { if ( TARGET_HARD_FLOAT_ABI && TARGET_VFP ) size += 32 ; if ( TARGET_IWMMXT_ABI ) size += 8 ; } return size ; } </s>

Determine the amount of memory needed to store the possible return registers of an untyped call .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getVectorElementType ( ) . getSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s>
bool
AArch64InstrInfo
::
shouldClusterMemOps
(
MachineInstr
&
FirstLdSt
,
MachineInstr
&
SecondLdSt
,
unsigned
NumLoads
)
const
{
if
(
NumLoads
>
1
)
return
false
;
unsigned
FirstOpc
=
FirstLdSt
.
getOpcode
(
)
;
unsigned
SecondOpc
=
SecondLdSt
.
getOpcode
(
)
;
if
(
!
canPairLdStOpc
(
FirstOpc
,
SecondOpc
)
)
return
false
;
if
(
!
isCandidateToMergeOrPair
(
FirstLdSt
)
||
!
isCandidateToMergeOrPair
(
SecondLdSt
)
)
return
false
;
int64_t
Offset1
=
FirstLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
FirstOpc
)
&&
!
scaleOffset
(
FirstOpc
,
Offset1
)
)
return
false
;
int64_t
Offset2
=
SecondLdSt
.
getOperand
(
2
)
.
getImm
(
)
;
if
(
isUnscaledLdSt
(
SecondOpc
)
&&
!
scaleOffset
(
SecondOpc
,
Offset2
)
)
return
false
;
if
(
Offset1
>
63
||
Offset1
<
64
)
return
false
;
assert
(
Offset1
<=
Offset2
&&
"Caller should have ordered offsets."
)
;
return
Offset1
+
1
==
Offset2
;
}
</s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> const TargetRegisterClass * SICRegisterInfo :: intRegClass ( unsigned Size ) const { return & SIC :: CPURegsRegClass ; } </s>


<s>
unsigned
TOYRegisterInfo
::
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
llvm_unreachable
(
"getFrameRegister not implemented yet"
)
;
}
</s>

TOY
TOY
"getFrameRegister not implemented yet"


<s>
PPC
::
Predicate
PPC
::
getSwappedPredicate
(
PPC
::
Predicate
Opcode
)
{
switch
(
Opcode
)
{
case
PPC
::
PRED_EQ
:
return
PPC
::
PRED_EQ
;
case
PPC
::
PRED_NE
:
return
PPC
::
PRED_NE
;
case
PPC
::
PRED_LT
:
return
PPC
::
PRED_GT
;
case
PPC
::
PRED_GE
:
return
PPC
::
PRED_LE
;
case
PPC
::
PRED_GT
:
return
PPC
::
PRED_LT
;
case
PPC
::
PRED_LE
:
return
PPC
::
PRED_GE
;
case
PPC
::
PRED_NU
:
return
PPC
::
PRED_NU
;
case
PPC
::
PRED_UN
:
return
PPC
::
PRED_UN
;
}
llvm_unreachable
(
"Unknown PPC branch opcode!"
)
;
}
</s>

This is a static version that you can use without an instruction available .


"\tj\t%s ! jump to first level handler\n"

"\tmovi\t$r0, %d ! preparing software vid\n"


<s> static tree get_prev_label ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return bi -> label_name ; return NULL_TREE ; } </s>

GET_PREV_LABEL gets the label name from the previous definition of the function .


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) reg_size = UNITS_PER_SPE_WORD ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else if ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SCmode && ! DECIMAL_FLOAT_MODE_P ( mode ) && SPE_SIMD_REGNO_P ( regno ) ) reg_size = UNITS_PER_FP_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


<s> bool MipsNaClRewritePass :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= SandboxLoadsInBlock ( MBB ) ; Modified |= SandboxStoresInBlock ( MBB ) ; Modified |= SandboxBranchesInBlock ( MBB ) ; Modified |= SandboxStackChangesInBlock ( MBB ) ; } AlignAllJumpTargets ( MF ) ; return Modified ; } </s>


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static ARM64Operand * CreateMem ( unsigned BaseRegNum , const MCExpr * Off , SMLoc S , SMLoc E , SMLoc OffsetLoc , MCContext & Ctx ) { ARM64Operand * Op = new ARM64Operand ( k_Memory , Ctx ) ; Op -> Mem . BaseRegNum = BaseRegNum ; Op -> Mem . OffsetRegNum = 0 ; Op -> Mem . OffsetImm = Off ; Op -> Mem . ExtType = ARM64_AM :: UXTX ; Op -> Mem . ShiftVal = 0 ; Op -> Mem . ExplicitShift = false ; Op -> Mem . Mode = ImmediateOffset ; Op -> OffsetLoc = OffsetLoc ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> void MipsSETargetLowering :: addMSAFloatType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; if ( Ty != MVT :: v8f16 ) { setOperationAction ( ISD :: FADD , Ty , Legal ) ; setOperationAction ( ISD :: FDIV , Ty , Legal ) ; setOperationAction ( ISD :: FLOG2 , Ty , Legal ) ; setOperationAction ( ISD :: FMUL , Ty , Legal ) ; setOperationAction ( ISD :: FRINT , Ty , Legal ) ; setOperationAction ( ISD :: FSQRT , Ty , Legal ) ; setOperationAction ( ISD :: FSUB , Ty , Legal ) ; } } </s>

Enable MSA support for the given floating-point type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::LOAD ISD::STORE ISD::BITCAST MVT::v8f16 ISD::FADD ISD::FDIV ISD::FLOG2 ISD::FMUL ISD::FRINT ISD::FSQRT ISD::FSUB


<s> bool MipsPassConfig :: addInstSelector ( ) { PM . add ( createMipsISelDag ( getMipsTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static int num_insns_constant_gpr ( HOST_WIDE_INT value ) { if ( SIGNED_INTEGER_16BIT_P ( value ) ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P ( value ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = sext_hwi ( value , 32 ) ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 || low == high ) return num_insns_constant_gpr ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_gpr ( low ) + 1 ; else return ( num_insns_constant_gpr ( high ) + num_insns_constant_gpr ( low ) + 1 ) ; } else return 2 ; } </s>

Helper for num_insns_constant . Calculate number of instructions to load VALUE to a single gpr using combinations of addi , addis , ori , oris , sldi and rldimi instructions .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr & MI , const MachineRegisterInfo * MRI , Register & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; SmallVector < unsigned , 1 > SrcOperandIds ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) ) return nullptr ; SrcOperandIds . push_back ( i ) ; } if ( SrcOperandIds . empty ( ) ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandIds , * DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> void mips_split_64bit_move ( rtx dest , rtx src ) { if ( FP_REG_RTX_P ( dest ) ) { emit_insn ( gen_load_df_low ( copy_rtx ( dest ) , mips_subword ( src , 0 ) ) ) ; emit_insn ( gen_load_df_high ( dest , mips_subword ( src , 1 ) , copy_rtx ( dest ) ) ) ; } else if ( FP_REG_RTX_P ( src ) ) { emit_move_insn ( mips_subword ( dest , 0 ) , mips_subword ( src , 0 ) ) ; emit_insn ( gen_store_df_high ( mips_subword ( dest , 1 ) , src ) ) ; } else { rtx low_dest ; low_dest = mips_subword ( dest , 0 ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { emit_move_insn ( mips_subword ( dest , 1 ) , mips_subword ( src , 1 ) ) ; emit_move_insn ( low_dest , mips_subword ( src , 0 ) ) ; } else { emit_move_insn ( low_dest , mips_subword ( src , 0 ) ) ; emit_move_insn ( mips_subword ( dest , 1 ) , mips_subword ( src , 1 ) ) ; } } } </s>

Split a 64-bit move from SRC to DEST assuming that mips_split_64bit_move_p holds . Moves into and out of FPRs cause some difficulty here . Such moves will always be DFmode , since paired FPRs are not allowed to store DImode values . The most natural representation would be two separate 32-bit moves , such as : ( set ( reg : SI $ f0 ) ( mem : SI ... ) ) ( set ( reg : SI $ f1 ) ( mem : SI ... ) ) However , the second insn is invalid because odd-numbered FPRs are not allowed to store independent values . Use the patterns load_df_low , load_df_high and store_df_high instead .


<s> static rtx pa_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode valmode ; if ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || TREE_CODE ( valtype ) == VECTOR_TYPE ) { HOST_WIDE_INT valsize = int_size_in_bytes ( valtype ) ; if ( valsize == UNITS_PER_WORD || valsize == 2 * UNITS_PER_WORD ) return gen_rtx_REG ( TYPE_MODE ( valtype ) , 28 ) ; if ( TARGET_64BIT ) { rtx loc [ 2 ] ; int i , offset = 0 ; int ub = valsize <= UNITS_PER_WORD ? 1 : 2 ; for ( i = 0 ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 + i ) , GEN_INT ( offset ) ) ; offset += 8 ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( valsize > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( 1 , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( TYPE_MODE ( valtype ) ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ; else valmode = TYPE_MODE ( valtype ) ; if ( TREE_CODE ( valtype ) == REAL_TYPE && ! AGGREGATE_TYPE_P ( valtype ) && TYPE_MODE ( valtype ) != TFmode && ! TARGET_SOFT_FLOAT ) return gen_rtx_REG ( valmode , 32 ) ; return gen_rtx_REG ( valmode , 28 ) ; } </s>

On the HP-PA the value is found in register ( s ) 28 ( -29 ) , unless the mode is SF or DF . Then the value is returned in fr4 ( 32 ) . This must perform the same promotions as PROMOTE_MODE , else promoting return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly . Small structures must be returned in a PARALLEL on PA64 in order to match the HP Compiler ABI .


"MSA requires a 64-bit FPU register file (FR=1 mode). "

This constructor initializes the data members to match that of the specified triple .


<s> PPCGenScalarMASSEntries ( ) : ModulePass ( ID ) { ScalarMASSFuncs = { } ; } </s>


"%s instructions aren't allowed in %s service routine"

"%s instructions aren't allowed in function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { switch ( Inst . getOpcode ( ) ) { case Mips :: JALR_HB : case Mips :: JALRC_HB_MMR6 : case Mips :: JALRC_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: LWP_MM : case Mips :: LWP_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 2 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: BLEZC : case Mips :: BLEZC_MMR6 : case Mips :: BGEZC : case Mips :: BGEZC_MMR6 : case Mips :: BGTZC : case Mips :: BGTZC_MMR6 : case Mips :: BLTZC : case Mips :: BLTZC_MMR6 : case Mips :: BEQZC : case Mips :: BEQZC_MMR6 : case Mips :: BNEZC : case Mips :: BNEZC_MMR6 : case Mips :: BLEZC64 : case Mips :: BGEZC64 : case Mips :: BGTZC64 : case Mips :: BLTZC64 : case Mips :: BEQZC64 : case Mips :: BNEZC64 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; return Match_Success ; case Mips :: BGEC : case Mips :: BGEC_MMR6 : case Mips :: BLTC : case Mips :: BLTC_MMR6 : case Mips :: BGEUC : case Mips :: BGEUC_MMR6 : case Mips :: BLTUC : case Mips :: BLTUC_MMR6 : case Mips :: BEQC : case Mips :: BEQC_MMR6 : case Mips :: BNEC : case Mips :: BNEC_MMR6 : case Mips :: BGEC64 : case Mips :: BLTC64 : case Mips :: BGEUC64 : case Mips :: BLTUC64 : case Mips :: BEQC64 : case Mips :: BNEC64 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 1 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 1 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; default : return Match_Success ; } } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return SrcAS < 256 && DestAS < 256 ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> unsigned ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return FramePtr ; return ARM :: SP ; } </s>


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s> bool X86InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned FPReg = RI . getFrameRegister ( MF ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; bool isWin64 = TM . getSubtarget < X86Subtarget > ( ) . isTargetWin64 ( ) ; unsigned Opc = is64Bit ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == FPReg ) continue ; if ( ! X86 :: VR128RegClass . contains ( Reg ) && ! isWin64 ) { BuildMI ( MBB , MI , DL , get ( Opc ) , Reg ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , & RI ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool loongarch_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return loongarch_hard_regno_mode_ok_p [ mode ] [ regno ] ; } </s>