<s> int rs6000_register_move_cost ( enum machine_mode mode , enum reg_class from , enum reg_class to ) { if ( reg_classes_intersect_p ( to , GENERAL_REGS ) || reg_classes_intersect_p ( from , GENERAL_REGS ) ) { if ( ! reg_classes_intersect_p ( to , GENERAL_REGS ) ) from = to ; if ( from == FLOAT_REGS || from == ALTIVEC_REGS ) return ( rs6000_memory_move_cost ( mode , from , 0 ) + rs6000_memory_move_cost ( mode , GENERAL_REGS , 0 ) ) ; else if ( from == CR_REGS ) return 4 ; else return 2 * hard_regno_nregs [ 0 ] [ mode ] ; } else if ( reg_classes_intersect_p ( to , from ) ) return mode == TFmode ? 4 : 2 ; else return ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; } </s>

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; SavedRegs . reset ( PPC :: VSRp26 ) ; SavedRegs . reset ( PPC :: VSRp27 ) ; SavedRegs . reset ( PPC :: VSRp28 ) ; SavedRegs . reset ( PPC :: VSRp29 ) ; SavedRegs . reset ( PPC :: VSRp30 ) ; SavedRegs . reset ( PPC :: VSRp31 ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { const uint64_t SpillSize = 4 ; const int64_t SpillOffset = Subtarget . isPPC64 ( ) ? 8 : Subtarget . isAIXABI ( ) ? 4 : - 4 ; int FrameIdx = MFI . CreateFixedObject ( SpillSize , SpillOffset , true , false ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( ExperimentalVectorWideningLegalization && VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) . getSimpleVT ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static MipsOperand * CreateMem ( unsigned Base , const MCExpr * Off , SMLoc S , SMLoc E ) { MipsOperand * Op = new MipsOperand ( k_Memory ) ; Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


"getBranchTargetOpValue expects only expressions or immediates"

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool X86AsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) { return Fixup . getKind ( ) >= FirstLiteralRelocationKind ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
PSI
=
&
getAnalysis
<
ProfileSummaryInfoWrapperPass
>
(
)
.
getPSI
(
)
;
MBFI
=
(
PSI
&&
PSI
->
hasProfileSummary
(
)
)
&
getAnalysis
<
LazyMachineBlockFrequencyInfoPass
>
(
)
.
getBFI
(
)
:
nullptr
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static bool isAllOnes ( SDValue V ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( V ) ; return C && C -> isAllOnesValue ( ) ; } </s>


<s> bool SSACCmpConv :: isDeadDef ( unsigned DstReg ) { if ( DstReg == AArch64 :: WZR || DstReg == AArch64 :: XZR ) return true ; if ( ! Register :: isVirtualRegister ( DstReg ) ) return false ; return MRI -> use_nodbg_empty ( DstReg ) ; } </s>

Return true if this instruction has a dead def .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> void i386_pe_seh_unwind_emit ( FILE * out_file , rtx_insn * insn ) { rtx note , pat ; bool handled_one = false ; struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( prev && ( CALL_P ( prev ) || ! insn_nothrow_p ( prev ) ) ) fputs ( "\tnop\n" , out_file ) ; fputs ( "\t.seh_endproc\n" , out_file ) ; seh -> in_cold_section = true ; return ; } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( seh -> after_prologue ) return ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , 1 ) ) { switch ( REG_NOTE_KIND ( note ) ) { case REG_FRAME_RELATED_EXPR : pat = XEXP ( note , 0 ) ; goto found ; case REG_CFA_DEF_CFA : case REG_CFA_EXPRESSION : gcc_unreachable ( ) ; break ; case REG_CFA_REGISTER : gcc_unreachable ( ) ; case REG_CFA_ADJUST_CFA : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; } seh_cfa_adjust_cfa ( out_file , seh , pat ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) pat = single_set ( insn ) ; seh_cfa_offset ( out_file , seh , pat ) ; handled_one = true ; break ; default : break ; } } if ( handled_one ) return ; pat = PATTERN ( insn ) ; found : seh_frame_related_expr ( out_file , seh , pat ) ; } </s>

This function looks at a single insn and emits any SEH directives required for unwind of this insn .


<s> OperandMatchResultTy X86AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { bool Result = ParseRegister ( RegNo , StartLoc , EndLoc , true ) ; bool PendingErrors = getParser ( ) . hasPendingError ( ) ; getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> void MINA32FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; } </s>


<s> virtual const X86RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static bool sparc_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_FLAT ) return false ; return ! ( crtl -> is_leaf && only_leaf_regs_used ( ) ) ; } </s>


<s> bool ARMPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> static section * arm_function_section ( tree decl , enum node_frequency freq , bool startup , bool exit ) { const char * section_name ; section * sec ; if ( ! decl || TREE_CODE ( decl ) != FUNCTION_DECL ) return default_function_section ( decl , freq , startup , exit ) ; if ( ! target_pure_code ) return default_function_section ( decl , freq , startup , exit ) ; section_name = DECL_SECTION_NAME ( decl ) ; if ( ! section_name ) { section * default_sec = default_function_section ( decl , freq , startup , exit ) ; if ( default_sec ) default_sec -> common . flags |= SECTION_ARM_PURECODE ; return default_sec ; } sec = get_named_section ( decl , section_name , 0 ) ; if ( ! sec ) sec = get_named_section ( decl , NULL , 0 ) ; sec -> common . flags |= SECTION_ARM_PURECODE ; return sec ; } </s>

Implement the TARGET_ASM_FUNCTION_SECTION hook . If pure-code is passed as an option , make sure all functions are in sections that have the SHF_ARM_PURECODE attribute .


<s> static rtx sh_struct_value_rtx ( tree fndecl , int incoming ATTRIBUTE_UNUSED ) { if ( TARGET_HITACHI || sh_attr_renesas_p ( fndecl ) ) return NULL_RTX ; return gen_rtx_REG ( Pmode , 2 ) ; } </s>

The Renesas calling convention does n't quite fit into this scheme since the address is passed like an invisible argument , but one that is always passed in memory .


<s> static void iq2000_annotate_frame_insn ( rtx_insn * insn , rtx dwarf_pattern ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf_pattern , REG_NOTES ( insn ) ) ; } </s>

Make INSN frame related and note that it performs the frame-related operation DWARF_PATTERN .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void ix86_fp_comparison_codes ( enum rtx_code code , enum rtx_code * bypass_code , enum rtx_code * first_code , enum rtx_code * second_code ) { * first_code = code ; * bypass_code = UNKNOWN ; * second_code = UNKNOWN ; switch ( code ) { case GT : case GE : case ORDERED : case UNORDERED : case UNEQ : case UNLT : case UNLE : case LTGT : break ; case LT : * first_code = UNLT ; * bypass_code = UNORDERED ; break ; case LE : * first_code = UNLE ; * bypass_code = UNORDERED ; break ; case EQ : * first_code = UNEQ ; * bypass_code = UNORDERED ; break ; case NE : * first_code = LTGT ; * second_code = UNORDERED ; break ; case UNGE : * first_code = GE ; * second_code = UNORDERED ; break ; case UNGT : * first_code = GT ; * second_code = UNORDERED ; break ; default : gcc_unreachable ( ) ; } if ( ! TARGET_IEEE_FP ) { * second_code = UNKNOWN ; * bypass_code = UNKNOWN ; } } </s>

Split comparison code CODE into comparisons we can do using branch instructions . BYPASS_CODE is comparison code for branch that will branch around FIRST_CODE and SECOND_CODE . If some of branches is not required , set value to UNKNOWN . We never require more than two branches .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { NumNoNeedForFrame ++ ; if ( UpdateMF ) MFI . setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const PPCSubtarget * > ( STI ) -> getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = & static_cast < const PPCSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> static void arm_emit_multi_reg_pop ( unsigned long saved_regs_mask ) { int num_regs = 0 ; int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( 1 << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? 1 : 0 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 16 ) ; emit_update = ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ? 0 : 1 ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , 0 , 0 ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , offset_adj ) = tmp ; } for ( j = 0 , i = 0 ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; if ( ( num_regs == 1 ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( ! return_in_pc ) arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD * num_regs , stack_pointer_rtx , stack_pointer_rtx ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi . SAVED_REGS_MASK shows which registers need to be restored . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! PPCSubTarget . isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>


<s> static void ix86_adjust_counter ( rtx countreg , HOST_WIDE_INT value ) { if ( GET_MODE ( countreg ) == DImode ) emit_insn ( gen_adddi3 ( countreg , countreg , GEN_INT ( - value ) ) ) ; else emit_insn ( gen_addsi3 ( countreg , countreg , GEN_INT ( - value ) ) ) ; } </s>


"ARM constant island placement and branch shortening pass"

getPassName - Return a nice clean name for a pass .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool Inserter :: runOnMachineFunction ( MachineFunction & F ) { MipsFunctionInfo * MipsFI = F . getInfo < MipsFunctionInfo > ( ) ; if ( ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) || ( ! MipsFI -> globalBaseRegFixed ( ) ) ) return false ; bool Changed = false ; int FI = MipsFI -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isLandingPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( Mips :: LW ) , Mips :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != Mips :: JALR ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( Mips :: LW ) , Mips :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips::LW Mips::GP 0 Mips::JALR Mips::LW Mips::GP 0


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
const
char
*
output_call
(
rtx
*
operands
)
{
gcc_assert
(
!
arm_arch5
)
;
if
(
REGNO
(
operands
[
0
]
)
==
LR_REGNUM
)
{
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
IP_REGNUM
)
;
output_asm_insn
(
"mov%?\t%0, %|lr"
,
operands
)
;
}
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
if
(
TARGET_INTERWORK
||
arm_arch4t
)
output_asm_insn
(
"bx%?\t%0"
,
operands
)
;
else
output_asm_insn
(
"mov%?\t%|pc, %0"
,
operands
)
;
return
""
;
}
</s>

INSN is either a function call or a millicode call . It may have an unconditional jump in its delay slot . CALL_DEST is the routine we are calling .


<s>
static
void
output_indirect_thunk
(
enum
indirect_thunk_prefix
need_prefix
,
unsigned
int
regno
)
{
char
indirectlabel1
[
32
]
;
char
indirectlabel2
[
32
]
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel1
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
ASM_GENERATE_INTERNAL_LABEL
(
indirectlabel2
,
INDIRECT_LABEL
,
indirectlabelno
++
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd call\t"
,
asm_out_file
)
;
else
fputs
(
"\tcall\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel2
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel1
)
;
fprintf
(
asm_out_file
,
"\tpause\n\tlfence\n"
)
;
fputs
(
"\tjmp\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
indirectlabel1
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
indirectlabel2
)
;
if
(
regno
!=
INVALID_REGNUM
)
{
rtx
xops
[
2
]
;
xops
[
0
]
=
gen_rtx_MEM
(
word_mode
,
stack_pointer_rtx
)
;
xops
[
1
]
=
gen_rtx_REG
(
word_mode
,
regno
)
;
output_asm_insn
(
"mov\t{%1, %0|%0, %1}"
,
xops
)
;
}
else
{
rtx
xops
[
2
]
;
xops
[
0
]
=
stack_pointer_rtx
;
xops
[
1
]
=
plus_constant
(
Pmode
,
stack_pointer_rtx
,
UNITS_PER_WORD
)
;
output_asm_insn
(
"lea\t{%E1, %0|%0, %E1}"
,
xops
)
;
}
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
fputs
(
"\tbnd ret\n"
,
asm_out_file
)
;
else
fputs
(
"\tret\n"
,
asm_out_file
)
;
}
</s>

Output a call and return thunk for indirect branch . If BND_P is true , the BND prefix is needed . If REGNO ! = -1 , the function address is in REGNO and the call and return thunk looks like : call L2 L1 : pause lfence jmp L1 L2 : mov % REG , ( % sp ) ret Otherwise , the function address is on the top of stack and the call and return thunk looks like : call L2 L1 : pause lfence jmp L1 L2 : lea WORD_SIZE ( % sp ) , % sp ret


<s> static opt_machine_mode aarch64_array_mode ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( aarch64_classify_vector_mode ( mode ) == VEC_SVE_DATA && IN_RANGE ( nelems , 2 , 4 ) ) return mode_for_vector ( GET_MODE_INNER ( mode ) , GET_MODE_NUNITS ( mode ) * nelems ) ; return opt_machine_mode ( ) ; } </s>

Implement target hook TARGET_ARRAY_MODE .


<s> bool AArch64AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { OS . write_zeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) support :: endian :: write < uint32_t > ( OS , 0xd503201f , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool preferZeroCompareBranch ( ) const override { return true ; } </s>

Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare .


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ; } </s>

True if the stack can be realigned for the target .


<s> bool SystemZXPLINKFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool PPCPassConfig :: addPreRegAlloc ( ) { if ( getPPCSubtarget ( ) . hasVSX ( ) ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
const
char
*
thumb_load_double_from_address
(
rtx
*
operands
)
{
rtx
addr
;
rtx
base
;
rtx
offset
;
rtx
arg1
;
rtx
arg2
;
gcc_assert
(
REG_P
(
operands
[
0
]
)
)
;
gcc_assert
(
MEM_P
(
operands
[
1
]
)
)
;
addr
=
XEXP
(
operands
[
1
]
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
if
(
REGNO
(
operands
[
0
]
)
==
REGNO
(
addr
)
)
{
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
}
else
{
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
}
break
;
case
CONST
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
break
;
case
PLUS
:
arg1
=
XEXP
(
addr
,
0
)
;
arg2
=
XEXP
(
addr
,
1
)
;
if
(
CONSTANT_P
(
arg1
)
)
base
=
arg2
,
offset
=
arg1
;
else
base
=
arg1
,
offset
=
arg2
;
gcc_assert
(
REG_P
(
base
)
)
;
if
(
REG_P
(
offset
)
)
{
int
reg_offset
=
REGNO
(
offset
)
;
int
reg_base
=
REGNO
(
base
)
;
int
reg_dest
=
REGNO
(
operands
[
0
]
)
;
asm_fprintf
(
asm_out_file
,
"\tadd\t%r, %r, %r"
,
reg_dest
+
1
,
reg_base
,
reg_offset
)
;
asm_fprintf
(
asm_out_file
,
"\tldr\t%r, [%r, #0]"
,
reg_dest
,
reg_dest
+
1
)
;
asm_fprintf
(
asm_out_file
,
"\tldr\t%r, [%r, #4]"
,
reg_dest
+
1
,
reg_dest
+
1
)
;
}
else
{
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
if
(
REGNO
(
operands
[
0
]
)
==
REGNO
(
base
)
)
{
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
}
else
{
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
}
}
break
;
case
LABEL_REF
:
operands
[
2
]
=
adjust_address
(
operands
[
1
]
,
SImode
,
4
)
;
output_asm_insn
(
"ldr\t%H0, %2"
,
operands
)
;
output_asm_insn
(
"ldr\t%0, %1"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
""
;
}
</s>

Handle the case of a double word load into a low register from a computed memory address . The computed address may involve a register which is overwritten by the load .


<s> void ia64_expand_vecint_cmov ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; bool negate ; rtx cmp , x , ot , of ; cmp = gen_reg_rtx ( mode ) ; negate = ia64_expand_vecint_compare ( code , mode , cmp , operands [ 4 ] , operands [ 5 ] ) ; ot = operands [ 1 + negate ] ; of = operands [ 2 - negate ] ; if ( ot == CONST0_RTX ( mode ) ) { if ( of == CONST0_RTX ( mode ) ) { emit_move_insn ( operands [ 0 ] , ot ) ; return ; } x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , of ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , x ) ) ; } else if ( of == CONST0_RTX ( mode ) ) { x = gen_rtx_AND ( mode , cmp , ot ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , x ) ) ; } else { rtx t , f ; t = gen_reg_rtx ( mode ) ; x = gen_rtx_AND ( mode , cmp , operands [ 1 + negate ] ) ; emit_insn ( gen_rtx_SET ( t , x ) ) ; f = gen_reg_rtx ( mode ) ; x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , operands [ 2 - negate ] ) ; emit_insn ( gen_rtx_SET ( f , x ) ) ; x = gen_rtx_IOR ( mode , t , f ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , x ) ) ; } } </s>

Emit an integral vector conditional move .


<s> static void rs6000_emit_move_from_cr ( rtx reg ) { if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ 8 ] , count = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == 1 ) { rtvec p = rtvec_alloc ( 1 ) ; rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ 0 ] ) ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - cr_reg [ 0 ] ) ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ; } } emit_insn ( gen_movesi_from_cr ( reg ) ) ; } </s>

Emit code to store CR fields that need to be saved into REG .


<s> void insert ( unsigned BBNum , BasicBlockInfo BBI ) { BBInfo . insert ( BBInfo . begin ( ) + BBNum , BBI ) ; } </s>

insert - Append entry to the vector if it does n't already exist .


<s> static reg_class_t arm_preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , reg_class_t rclass ) { if ( TARGET_32BIT ) return rclass ; else { if ( rclass == GENERAL_REGS ) return LO_REGS ; else return rclass ; } } </s>

Worker function for TARGET_PREFERRED_RELOAD_CLASS . Given an rtx X being reloaded into a reg required to be in class CLASS , return the class of reg to actually use . In general this is just CLASS , but for the Thumb core registers and immediate constants we prefer a LO_REGS class or a subset .


<s> InstructionCost AArch64TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case Intrinsic :: umin : case Intrinsic :: umax : { auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . second == MVT :: v2i64 ) return LT . first * 2 ; LLVM_FALLTHROUGH ; } case Intrinsic :: smin : case Intrinsic :: smax : { static const auto ValidMinMaxTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } case Intrinsic :: sadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: uadd_sat : case Intrinsic :: usub_sat : { static const auto ValidSatTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 , MVT :: v2i64 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned Instrs = LT . second . getScalarSizeInBits ( ) == RetTy -> getScalarSizeInBits ( ) ? 1 : 4 ; if ( any_of ( ValidSatTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first * Instrs ; break ; } case Intrinsic :: abs : { static const auto ValidAbsTys = { MVT :: v8i8 , MVT :: v16i8 , MVT :: v4i16 , MVT :: v8i16 , MVT :: v2i32 , MVT :: v4i32 , MVT :: v2i64 } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidAbsTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } case Intrinsic :: experimental_stepvector : { InstructionCost Cost = 1 ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . first > 1 ) { Type * LegalVTy = EVT ( LT . second ) . getTypeForEVT ( RetTy -> getContext ( ) ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , LegalVTy , CostKind ) ; Cost += AddCost * ( LT . first - 1 ) ; } return Cost ; } default : break ; } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . getArgumentList ( ) ) { ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + 1 , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ Idx ] , Regs , Offsets ) ; } ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> unsigned getCSRFirstUseCost ( ) const override { return 5 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s> const MipsRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"DCPU16 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> rtx ix86_build_signbit_mask ( machine_mode mode , bool vect , bool invert ) { machine_mode vec_mode , imode ; wide_int w ; rtx mask , v ; switch ( mode ) { case E_V8HFmode : case E_V16HFmode : case E_V32HFmode : vec_mode = mode ; imode = HImode ; break ; case E_V16SImode : case E_V16SFmode : case E_V8SImode : case E_V4SImode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V2SImode : vec_mode = mode ; imode = SImode ; break ; case E_V8DImode : case E_V4DImode : case E_V2DImode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : vec_mode = mode ; imode = DImode ; break ; case E_TImode : case E_TFmode : vec_mode = VOIDmode ; imode = TImode ; break ; default : gcc_unreachable ( ) ; } machine_mode inner_mode = GET_MODE_INNER ( mode ) ; w = wi :: set_bit_in_zero ( GET_MODE_BITSIZE ( inner_mode ) - 1 , GET_MODE_BITSIZE ( inner_mode ) ) ; if ( invert ) w = wi :: bit_not ( w ) ; mask = immed_wide_int_const ( w , imode ) ; mask = gen_lowpart ( inner_mode , mask ) ; if ( vec_mode == VOIDmode ) return force_reg ( inner_mode , mask ) ; v = ix86_build_const_vector ( vec_mode , vect , mask ) ; return force_reg ( vec_mode , v ) ; } </s>

A subroutine of ix86_expand_fp_absneg_operator and copysign expanders . Create a mask for the sign bit in MODE for an SSE register . If VECT is true , then replicate the mask for all elements of the vector register . If INVERT is true , then create a mask excluding the sign bit .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP


<s> void ARMFrameLowering :: getCalleeSaves ( const MachineFunction & MF , BitVector & SavedRegs ) const { TargetFrameLowering :: getCalleeSaves ( MF , SavedRegs ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getPreservesR0 ( ) ) SavedRegs . set ( ARM :: R0 ) ; } </s>

Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs .


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; dup = gen_rtx_VEC_DUPLICATE ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; start_sequence ( ) ; XEXP ( dup , 0 ) = force_reg ( GET_MODE_INNER ( mode ) , val ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s> std :: pair < unsigned , const TargetRegisterClass * > MandarinTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & MD :: GenericRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void OutgoingValueHandler :: assignValueToReg ( Register ValVReg , const CCValAssign & VA , const EVT & VT ) { Register PhysReg = VA . getLocReg ( ) ; if ( VT == MVT :: f64 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; bool IsEL = STI . isLittle ( ) ; auto Unmerge = MIRBuilder . buildUnmerge ( LLT :: scalar ( 32 ) , ValVReg ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? 0 : 1 ) ) , Unmerge . getReg ( 0 ) ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? 1 : 0 ) ) , Unmerge . getReg ( 1 ) ) ; } else if ( VT == MVT :: f32 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; } else { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> int mmix_legitimate_address ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx x , int strict_checking ) { ( ( strict_checking \ && ( REGNO ( X ) <= MMIX_LAST_GENERAL_REGISTER \ || ( reg_renumber [ REGNO ( X ) ] > 0 \ && reg_renumber [ REGNO ( X ) ] <= MMIX_LAST_GENERAL_REGISTER ) ) ) \ || ( ! strict_checking \ && ( REGNO ( X ) <= MMIX_LAST_GENERAL_REGISTER \ || REGNO ( X ) >= FIRST_PSEUDO_REGISTER \ || REGNO ( X ) == ARG_POINTER_REGNUM ) ) ) if ( REG_P ( x ) && MMIX_REG_OK ( x ) ) return 1 ; if ( GET_CODE ( x ) == PLUS ) { rtx x1 = XEXP ( x , 0 ) ; rtx x2 = XEXP ( x , 1 ) ; if ( ! REG_P ( x1 ) ) { rtx tem = x1 ; x1 = x2 ; x2 = tem ; } if ( ! REG_P ( x1 ) || ! MMIX_REG_OK ( x1 ) ) return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; if ( REG_P ( x2 ) && MMIX_REG_OK ( x2 ) ) return 1 ; if ( GET_CODE ( x2 ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( x2 ) , 'I' ) ) return 1 ; return 0 ; } return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; } </s>

Return 1 if the address is OK , otherwise 0 . Used by GO_IF_LEGITIMATE_ADDRESS .


<s> static void ix86_emit_save_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to save registers using MOV insns . First register is restored from POINTER + OFFSET .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> bool SystemZTargetLowering :: findOptimalMemOpLowering ( std :: vector < EVT > & MemOps , unsigned Limit , const MemOp & Op , unsigned DstAS , unsigned SrcAS , const AttributeList & FuncAttributes ) const { const int MVCFastLen = 16 ; if ( Op . isMemcpy ( ) && Op . allowOverlap ( ) && Op . size ( ) <= MVCFastLen ) return false ; if ( Op . isMemset ( ) && Op . size ( ) - 1 <= MVCFastLen ) return false ; if ( Op . isZeroMemset ( ) ) return false ; return TargetLowering :: findOptimalMemOpLowering ( MemOps , Limit , Op , DstAS , SrcAS , FuncAttributes ) ; } </s>

Determines the optimal series of memory ops to replace the memset / memcpy .


<s> static inline int arm_arm_address_cost ( rtx x ) { enum rtx_code c = GET_CODE ( x ) ; if ( c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC ) return 0 ; if ( c == MEM || c == LABEL_REF || c == SYMBOL_REF ) return 10 ; if ( c == PLUS || c == MINUS ) { if ( GET_CODE ( XEXP ( x , 0 ) ) == CONST_INT ) return 2 ; if ( ARITHMETIC_P ( XEXP ( x , 0 ) ) || ARITHMETIC_P ( XEXP ( x , 1 ) ) ) return 3 ; return 4 ; } return 6 ; } </s>

All address computations that can be done are free , but rtx cost returns the same for practically all of them . So we weight the different types of address here in the order ( most pref first ) : PRE/POST_INC/DEC , SHIFT or NON-INT sum , INT sum , REG , MEM or LABEL .


"missing %<target%> attribute for multi-versioned %D"

This function returns true if FN1 and FN2 are versions of the same function , that is , the target strings of the function decls are different . This assumes that FN1 and FN2 have the same signature .


<s> bool AArch64InstrInfo :: isWhileOpcode ( unsigned Opc ) const { return get ( Opc ) . TSFlags & AArch64 :: InstrFlagIsWhile ; } </s>

Returns true if the opcode is for an SVE WHILE # # instruction .


<s> bool ARMBaseInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { if ( Pred1 . size ( ) > 2 || Pred2 . size ( ) > 2 ) return false ; ARMCC :: CondCodes CC1 = ( ARMCC :: CondCodes ) Pred1 [ 0 ] . getImm ( ) ; ARMCC :: CondCodes CC2 = ( ARMCC :: CondCodes ) Pred2 [ 0 ] . getImm ( ) ; if ( CC1 == CC2 ) return true ; switch ( CC1 ) { default : return false ; case ARMCC :: AL : return true ; case ARMCC :: HS : return CC2 == ARMCC :: HI ; case ARMCC :: LS : return CC2 == ARMCC :: LO || CC2 == ARMCC :: EQ ; case ARMCC :: GE : return CC2 == ARMCC :: GT ; case ARMCC :: LE : return CC2 == ARMCC :: LT ; } } </s>

Returns true if the first specified predicate subsumes the second , e.g .

ARM ARM 2 2 ARMCC::CondCodes ARMCC::CondCodes 0 ARMCC::CondCodes ARMCC::CondCodes 0 ARMCC::AL ARMCC::HS ARMCC::HI ARMCC::LS ARMCC::LO ARMCC::EQ ARMCC::GE ARMCC::GT ARMCC::LE ARMCC::LT


<s> void ix86_emit_fp_unordered_jump ( rtx label ) { rtx reg = gen_reg_rtx ( HImode ) ; rtx_insn * insn ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_1_ccno ( reg , GEN_INT ( 0x04 ) ) ) ; temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , temp ) ) ; predict_jump ( REG_BR_PROB_BASE * 10 / 100 ) ; JUMP_LABEL ( insn ) = label ; } </s>

Output code to perform a conditional jump to LABEL , if C2 flag in FP status register is set .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> static bool xstormy16_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) { if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , 0 ) && ! LEGITIMATE_ADDRESS_CONST_INT_P ( x , 6 ) ) return true ; if ( GET_CODE ( x ) == PLUS && LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , 1 ) , 0 ) && ! LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , 1 ) , 6 ) ) return true ; return false ; } </s>

Return nonzero if memory address X ( an RTX ) can have different meanings depending on the machine mode of the memory reference it is used for or if the address is valid for some modes but not others . Autoincrement and autodecrement addresses typically have mode-dependent effects because the amount of the increment or decrement is the size of the operand being addressed . Some machines have other mode-dependent addresses . Many RISC machines have no mode-dependent addresses . You may assume that ADDR is a valid address for the machine . On this chip , this is true if the address is valid with an offset of 0 but not of 6 , because in that case it can not be used as an address for DImode or DFmode , or if the address is a post-increment or pre-decrement address .


<s> static int shcompact_byref ( const CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type , bool named ) { unsigned HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( cum -> arg_count [ SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! named || GET_SH_ARG_CLASS ( mode ) == SH_ARG_INT || ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT && cum -> arg_count [ SH_ARG_FLOAT ] >= NPARM_REGS ( SFmode ) ) ) && size > 4 && ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) return size ; else return 0 ; } </s>

Whether an argument must be passed by reference . On SHcompact , we pretend arguments wider than 32-bits that would have been passed in registers are passed by reference , so that an SHmedia trampoline loads them into the full 64-bits registers .


<s> static int csky_arg_partial_bytes ( cumulative_args_t pcum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int param_size = csky_num_arg_regs ( mode , type ) ; if ( * pcum < CSKY_NPARM_REGS && * pcum + param_size > CSKY_NPARM_REGS ) return ( CSKY_NPARM_REGS - * pcum ) * UNITS_PER_WORD ; return 0 ; } </s>

Implement TARGET_ARG_PARTIAL_BYTES . Return the number of bytes at the beginning of an argument that must be put in registers . The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack .


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , FK_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Case ( "R_MIPS_CALL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_HI16 ) . Case ( "R_MIPS_CALL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_LO16 ) . Case ( "R_MIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL16 ) . Case ( "R_MIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_OFST ) . Case ( "R_MIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_DISP ) . Case ( "R_MIPS_GOT_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_HI16 ) . Case ( "R_MIPS_GOT_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_LO16 ) . Case ( "R_MIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_Mips_GOTTPREL ) . Case ( "R_MIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_HI ) . Case ( "R_MIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_LO ) . Case ( "R_MIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_Mips_TLSGD ) . Case ( "R_MIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_Mips_TLSLDM ) . Case ( "R_MIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_HI ) . Case ( "R_MIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_LO ) . Case ( "R_MICROMIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_CALL16 ) . Case ( "R_MICROMIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_DISP ) . Case ( "R_MICROMIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_PAGE ) . Case ( "R_MICROMIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_OFST ) . Case ( "R_MICROMIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT16 ) . Case ( "R_MICROMIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOTTPREL ) . Case ( "R_MICROMIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 ) . Case ( "R_MICROMIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_GD ) . Case ( "R_MICROMIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_LDM ) . Case ( "R_MICROMIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 ) . Case ( "R_MIPS_JALR" , ( MCFixupKind ) Mips :: fixup_Mips_JALR ) . Case ( "R_MICROMIPS_JALR" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_JALR ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> SDValue MandarinTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> unsigned X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> MCSymbol * OR1KMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> static HOST_WIDE_INT iq2000_starting_frame_offset ( void ) { return crtl -> outgoing_args_size ; } </s>


<s> static void sparc_asm_function_epilogue ( FILE * file ) { rtx_insn * insn = get_last_insn ( ) ; rtx last_real_insn = prev_real_insn ( insn ) ; if ( last_real_insn && NONJUMP_INSN_P ( last_real_insn ) && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE ) last_real_insn = XVECEXP ( PATTERN ( last_real_insn ) , 0 , 0 ) ; if ( last_real_insn && CALL_P ( last_real_insn ) && ! SIBLING_CALL_P ( last_real_insn ) ) fputs ( "\tnop\n" , file ) ; sparc_output_deferred_case_vectors ( ) ; } </s>

This function generates the assembly code for function exit .


<s> bool Mips16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> void mips_order_regs_for_local_alloc ( ) { register int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = i ; if ( TARGET_MIPS16 ) { reg_alloc_order [ 0 ] = 24 ; reg_alloc_order [ 24 ] = 0 ; } } </s>

On the mips16 , we want to allocate $ 24 ( T_REG ) before other registers for instructions for which it is possible . This helps avoid shuffling registers around in order to set up for an xor , encouraging the compiler to use a cmp instead .


<s> DecodeStatus ARMDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { if ( STI . getFeatureBits ( ) [ ARM :: ModeThumb ] ) return getThumbInstruction ( MI , Size , Bytes , Address , OS , CS ) ; return getARMInstruction ( MI , Size , Bytes , Address , OS , CS ) ; } </s>

Returns the disassembly of a single instruction .


"SVE requires vector length in multiples of 128!"

"Minimum SVE vector size should not be larger than its maximum!"

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new ARMMCAsmInfoDarwin ( ) ; default : return new ARMELFMCAsmInfo ( ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( PPCSubTarget . isSVR4ABI ( ) && ! PPCSubTarget . isPPC64 ( ) ) { return LowerFormalArguments_SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool nds32_n13_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; gcc_assert ( get_attr_type ( producer ) == TYPE_LOAD ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; return n13_consumed_by_e2_dep_p ( consumer , def_reg ) ; } </s>

Check dependencies from Load-Store Unit ( E3 ) to E2 .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> Align getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> MVT MipsTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) { if ( Subtarget . isABI_O32 ( ) ) { return MVT :: i32 ; } else { return ( VT . getSizeInBits ( ) == 32 ) ? MVT :: i32 : MVT :: i64 ; } } return MipsTargetLowering :: getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> SDNode * LEGDAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectMoveImmediate ( N ) ; case ISD :: BR_CC : return SelectConditionalBranch ( N ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .

PowerPC
PPC
"Unknown rematerializable operation!"
PPC::LI
PPC::LI8
PPC::LIS
PPC::LIS8
PPC::QVGPCI
PPC::ADDIStocHA
PPC::ADDItocL
PPC::LOAD_STACK_GUARD


<s> static int loongarch_move_to_gpr_cost ( reg_class_t from ) { switch ( from ) { case GENERAL_REGS : return 2 ; case FP_REGS : return 4 ; default : return 0 ; } } </s>

Return the cost of moving a value from a register of class FROM to a GPR . Return 0 for classes that are unions of other classes handled by this function .


<s> static void csky_layout_stack_frame ( void ) { machine_function * infp = cfun -> machine ; int reg_count ; if ( infp -> frame_init_p ) return ; infp -> outbound_size = CSKY_STACK_ALIGN ( crtl -> outgoing_args_size ) ; infp -> local_offset = infp -> outbound_size ; infp -> local_size = CSKY_STACK_ALIGN ( get_frame_size ( ) ) ; infp -> reg_offset = infp -> local_offset + infp -> local_size ; infp -> reg_mask = get_csky_live_regs ( & reg_count ) ; infp -> reg_size = reg_count * UNITS_PER_WORD ; infp -> arg_offset = infp -> reg_offset + infp -> reg_size ; infp -> arg_size = crtl -> args . pretend_args_size ; infp -> frame_size = infp -> arg_offset + infp -> arg_size ; infp -> frame_init_p = reload_completed ; } </s>

Compute the stack frame layout , storing sizes of the various pieces in cfun- > machine . Stack frames constructed in the prologue look like : ... caller 's frame ... incoming SP - > caller 's outbound argument overflow argument spill optional FP - > register save local variables alloca ( ) space adjusted SP - > outbound argument overflow with SP/FP pointing at the base ( low address ) of the respective area , and each area aligned to a word boundary .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( Subtarget . enableLongBranchPass ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( Subtarget . inMips16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


"Replacing load %d with permuted load\n"

Convert the non-permuting load INSN to a permuting one .


<s> const uint16_t * SparcRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> static bool expand_vec_perm_even_odd_trunc ( struct expand_vec_perm_d * d ) { rtx t1 , t2 , t3 , t4 ; unsigned i , odd , nelt = d -> nelt ; if ( ! TARGET_AVX512BW || d -> one_operand_p || d -> vmode != V64QImode ) return false ; odd = d -> perm [ 0 ] ; if ( odd > 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != 2 * i + odd ) return false ; if ( d -> testing_p ) return true ; if ( odd ) { t1 = gen_reg_rtx ( V32HImode ) ; t2 = gen_reg_rtx ( V32HImode ) ; emit_insn ( gen_lshrv32hi3 ( t1 , gen_lowpart ( V32HImode , d -> op0 ) , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_lshrv32hi3 ( t2 , gen_lowpart ( V32HImode , d -> op1 ) , GEN_INT ( 8 ) ) ) ; } else { t1 = gen_lowpart ( V32HImode , d -> op0 ) ; t2 = gen_lowpart ( V32HImode , d -> op1 ) ; } t3 = gen_reg_rtx ( V32QImode ) ; t4 = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_avx512bw_truncatev32hiv32qi2 ( t3 , t1 ) ) ; emit_insn ( gen_avx512bw_truncatev32hiv32qi2 ( t4 , t2 ) ) ; emit_insn ( gen_avx_vec_concatv64qi ( d -> target , t3 , t4 ) ) ; return true ; } </s>

A subroutine of expand_vec_perm_even_odd_1 . Implement extract-even and extract-odd permutations of two V64QI operands with two `` shifts '' , two `` truncs '' and one `` concat '' insns for `` odd '' and two `` truncs '' and one concat insn for `` even . '' Have already failed all two instruction sequences .


<s> static rtx emit_multi_reg_push ( unsigned long mask ) { int num_regs = 0 ; int num_dwarf_regs ; int i , j ; rtx par ; rtx dwarf ; int dwarf_par_index ; rtx tmp , reg ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 16 ) ; num_dwarf_regs = num_regs ; if ( mask & ( 1 << PC_REGNUM ) ) num_dwarf_regs -- ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + 1 ) ) ; dwarf_par_index = 1 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_DEC ( BLKmode , stack_pointer_rtx ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( i != PC_REGNUM ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ) = tmp ; dwarf_par_index ++ ; } break ; } } for ( j = 1 , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( i != PC_REGNUM ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , plus_constant ( stack_pointer_rtx , 4 * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } j ++ ; } } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( SImode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - 4 * num_regs ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; REG_NOTES ( par ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf , REG_NOTES ( par ) ) ; return par ; } </s>

Generate and emit an insn that we will recognize as a push_multi . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> unsigned X86InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != 0 || ! hasPartialRegUpdate ( MI . getOpcode ( ) ) ) return 0 ; const MachineOperand & MO = MI . getOperand ( 0 ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return 0 ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return 0 ; } return PartialRegUpdateClearance ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s> void CSKYPassConfig :: addPreEmitPass ( ) { addPass ( createCSKYConstantIslandPass ( ) ) ; } </s>


"cannot return value in vector register because"

" altivec instructions are disabled, use -maltivec"

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> static rtx rs6000_delegitimize_address ( rtx orig_x ) { rtx x , y , offset ; orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , 1 ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , 1 ) ) ) { offset = XEXP ( y , 1 ) ; y = XEXP ( y , 0 ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , 0 , 0 ) ; if ( TARGET_XCOFF && GET_CODE ( y ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , 1 ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , 1 ) , 0 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP ( y , 0 , 0 ) ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> static bool pa_scalar_mode_supported_p ( machine_mode mode ) { int precision = GET_MODE_PRECISION ( mode ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_PARTIAL_INT : case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE ) return true ; if ( precision == LONG_TYPE_SIZE ) return true ; if ( precision == LONG_LONG_TYPE_SIZE ) return true ; return false ; case MODE_FLOAT : if ( precision == FLOAT_TYPE_SIZE ) return true ; if ( precision == DOUBLE_TYPE_SIZE ) return true ; if ( precision == LONG_DOUBLE_TYPE_SIZE ) return true ; return false ; case MODE_DECIMAL_FLOAT : return false ; default : gcc_unreachable ( ) ; } } </s>

True if MODE is valid for the target . By `` valid '' , we mean able to be manipulated in non-trivial ways . In particular , this means all the arithmetic is supported .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; } </s>


<s> static bool csky_can_use_ldstm ( int mask , int * br , int * er ) { int regno ; int begin_reg = 0 , end_reg = 0 ; int count = 0 ; if ( ! TARGET_MULTIPLE_STLD ) return false ; if ( mask & 0xf ) return false ; for ( regno = 4 ; regno <= 11 ; regno ++ ) { if ( mask & 1 << regno ) { if ( ! begin_reg ) begin_reg = regno ; end_reg = regno ; count ++ ; } else if ( begin_reg ) break ; } if ( count >= CSKY_MIN_MULTIPLE_STLD && count <= CSKY_MAX_MULTIPLE_STLD ) { if ( br ) * br = begin_reg ; if ( er ) * er = end_reg ; return true ; } return false ; } </s>

Return true if store/load multiple instructions can be used to save/restore at least some of the registers indicated by MASK . Unlike the push/pop case , this does handle partial ranges . Set * BR and * ER to the beginning and end ( respectively ) of the register range that can be handled .


<s> void aarch64_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; rtx_code_label * label ; rtx x ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , 0 ) ; aarch64_emit_load_exclusive ( mode , old_out , mem , model_rtx ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ; break ; } aarch64_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , model_rtx ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; } </s>


<s> bool isMem ( ) const override { return false ; } </s>


<s> static unsigned int frame_header_opt ( ) { struct cgraph_node * node ; function * fn ; FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node -> get_fun ( ) ; if ( fn != NULL ) fn -> machine -> does_not_use_frame_header = ! needs_frame_header_p ( fn ) ; } FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node -> get_fun ( ) ; if ( fn != NULL ) fn -> machine -> optimize_call_stack = ! callees_functions_use_frame_header ( fn ) && ! is_leaf_function ( fn ) ; } FOR_EACH_DEFINED_FUNCTION ( node ) { fn = node -> get_fun ( ) ; if ( fn != NULL && fn -> machine -> optimize_call_stack ) set_callers_may_not_allocate_frame ( fn ) ; } return 0 ; } </s>

Scan each function to determine those that need its frame headers . Perform a second scan to determine if the allocation can be skipped because none of their callees require the frame header .


<s> const MCPhysReg * ARM64TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { ARM64 :: X16 , ARM64 :: X17 , ARM64 :: LR , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> static bool aapcs_vfp_allocate ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { int shift = GET_MODE_SIZE ( pcum -> aapcs_vfp_rmode ) / GET_MODE_SIZE ( SFmode ) ; unsigned mask = ( 1 << ( shift * pcum -> aapcs_vfp_rcount ) ) - 1 ; int regno ; for ( regno = 0 ; regno < NUM_VFP_ARG_REGS ; regno += shift ) if ( ( ( pcum -> aapcs_vfp_regs_free >> regno ) & mask ) == mask ) { pcum -> aapcs_vfp_reg_alloc = mask << regno ; if ( mode == BLKmode || ( mode == TImode && ! TARGET_NEON ) || ! arm_hard_regno_mode_ok ( FIRST_VFP_REGNUM + regno , mode ) ) { int i ; int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! TARGET_NEON ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= 2 ; rshift /= 2 ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = 0 ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM + regno ) ; return true ; } return false ; } </s>

Implement the allocate field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> static const char * pru_comparison_str ( enum rtx_code cond ) { switch ( cond ) { case NE : return "ne" ; case EQ : return "eq" ; case GEU : return "ge" ; case GTU : return "gt" ; case LEU : return "le" ; case LTU : return "lt" ; default : gcc_unreachable ( ) ; } } </s>

Map rtx_code to unsigned PRU branch op suffix . Callers must handle sign comparison themselves for signed operations .


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( IsN64 ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool PPCTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return ( EnableQuadPrecision && Subtarget . hasP9Vector ( ) ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> void ARMPassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( getARMSubtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( createARMOptimizeBarriersPass ( ) ) ; addPass ( createARMConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static unsigned getBasePointerSaveOffset ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI ) return isPPC64 ? - 16U : - 8U ; return isPPC64 ? - 16U : - 8U ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s> void rs6000_emit_swdiv ( rtx dst , rtx n , rtx d , bool note_p ) { machine_mode mode = GET_MODE ( dst ) ; rtx one , x0 , e0 , x1 , xprev , eprev , xnext , enext , u , v ; int i ; int passes = ( TARGET_RECIP_PRECISION ) ? 1 : 3 ; if ( mode == DFmode || mode == V2DFmode ) passes ++ ; enum insn_code code = optab_handler ( smul_optab , mode ) ; insn_gen_fn gen_mul = GEN_FCN ( code ) ; gcc_assert ( code != CODE_FOR_nothing ) ; one = rs6000_load_constant_and_splat ( mode , dconst1 ) ; x0 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , d ) , UNSPEC_FRES ) ) ) ; if ( passes > 1 ) { e0 = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( e0 , d , x0 , one ) ; x1 = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( x1 , e0 , x0 , x0 ) ; for ( i = 0 , xprev = x1 , eprev = e0 ; i < passes - 2 ; ++ i , xprev = xnext , eprev = enext ) { enext = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( enext , eprev , eprev ) ) ; xnext = gen_reg_rtx ( mode ) ; rs6000_emit_madd ( xnext , enext , xprev , xprev ) ; } } else xprev = x0 ; u = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , n , xprev ) ) ; v = gen_reg_rtx ( mode ) ; rs6000_emit_nmsub ( v , d , u , n ) ; rs6000_emit_madd ( dst , v , xprev , u ) ; if ( note_p ) add_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_DIV ( mode , n , d ) ) ; } </s>

Newton-Raphson approximation of floating point divide DST = N/D . If NOTE_P , add a reg_note saying that this was a division . Support both scalar and vector divide . Assumes no trapping math and finite arguments .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; TII = static_cast < const AArch64InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock :: iterator I , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = I -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII . get ( ADDriOpc ) , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri


<s> bool ARMAsmParser :: ParseInstruction ( const StringRef & Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Operands . push_back ( new ARMOperand ( ARMOperand :: CreateToken ( Name ) ) ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { ARMOperand Op ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( new ARMOperand ( Op ) ) ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( new ARMOperand ( Op ) ) ; } } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> static section * rs6000_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

A C statement or statements to switch to the appropriate section for output of RTX in mode MODE . You can assume that RTX is some kind of constant in RTL . The argument MODE is redundant except in the case of a ` const_int ' rtx . Select the section by calling ` text_section ' or one of the alternatives for other sections . Do not define this macro if you put all constants in the read-only data section .


<s> static void aarch64_emit_binop ( rtx dest , optab binoptab , rtx op0 , rtx op1 ) { rtx tmp = expand_binop ( GET_MODE ( dest ) , binoptab , op0 , op1 , dest , 0 , OPTAB_DIRECT ) ; if ( dest != tmp ) emit_move_insn ( dest , tmp ) ; } </s>

Apply BINOPTAB to OP0 and OP1 and store the result in DEST .


<s> static inline bool mode_supports_vsx_dform_quad ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) != 0 ) ; } </s>

Return true if we have D-form addressing in VSX registers . This addressing is more limited than normal d-form addressing in that the offset must be aligned on a 16-byte boundary .


<s> void X86AsmParser :: emitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Out . emitInstruction ( Inst , getSTI ( ) ) ; } </s>

Targets should implement this to emit instructions .


<s> static int iq2000_address_cost ( rtx addr ) { switch ( GET_CODE ( addr ) ) { case LO_SUM : return 1 ; case LABEL_REF : return 2 ; case CONST : { rtx offset = const0_rtx ; addr = eliminate_constant_term ( XEXP ( addr , 0 ) , & offset ) ; if ( GET_CODE ( addr ) == LABEL_REF ) return 2 ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return 4 ; if ( ! SMALL_INT ( offset ) ) return 2 ; } case SYMBOL_REF : return SYMBOL_REF_FLAG ( addr ) ? 1 : 2 ; case PLUS : { rtx plus0 = XEXP ( addr , 0 ) ; rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG && GET_CODE ( plus1 ) == REG ) plus0 = XEXP ( addr , 1 ) , plus1 = XEXP ( addr , 0 ) ; if ( GET_CODE ( plus0 ) != REG ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return SMALL_INT ( plus1 ) ? 1 : 2 ; case CONST : case SYMBOL_REF : case LABEL_REF : case HIGH : case LO_SUM : return iq2000_address_cost ( plus1 ) + 1 ; default : break ; } } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR .


<s> bool AArch64InstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) ) return false ; unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x01000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 2 ) . getImm ( ) ; if ( MI . getOpcode ( ) == VE :: STQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 3 ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , VE :: sub_even ) ; Register SrcLoReg = getSubReg ( SrcReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: STrii ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( SrcLoReg ) ; replaceFI ( MF , II , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: STrii ) ) ; MI . getOperand ( 3 ) . setReg ( SrcHiReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == VE :: LDQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , VE :: sub_even ) ; Register DestLoReg = getSubReg ( DestReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: LDrii ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) ; replaceFI ( MF , II , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: LDrii ) ) ; MI . getOperand ( 0 ) . setReg ( DestHiReg ) ; Offset += 8 ; } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static struct machine_function * nds32_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> use_eh_return_p = 0 ; machine -> naked_p = 0 ; machine -> fp_as_gp_p = 0 ; machine -> strict_aligned_p = 0 ; machine -> attr_naked_p = 0 ; machine -> attr_no_prologue_p = 0 ; return machine ; } </s>

Function to save and restore machine-specific function data .


<s> static bool aarch64_get_sve_pred_bits ( rtx_vector_builder & builder , rtx x ) { if ( GET_CODE ( x ) != CONST_VECTOR ) return false ; unsigned int factor = vector_element_size ( GET_MODE_NUNITS ( VNx16BImode ) , GET_MODE_NUNITS ( GET_MODE ( x ) ) ) ; unsigned int npatterns = CONST_VECTOR_NPATTERNS ( x ) * factor ; unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN ( x ) ; builder . new_vector ( VNx16BImode , npatterns , nelts_per_pattern ) ; unsigned int nelts = const_vector_encoded_nelts ( x ) ; for ( unsigned int i = 0 ; i < nelts ; ++ i ) { rtx elt = CONST_VECTOR_ENCODED_ELT ( x , i ) ; if ( ! CONST_INT_P ( elt ) ) return false ; builder . quick_push ( elt ) ; for ( unsigned int j = 1 ; j < factor ; ++ j ) builder . quick_push ( const0_rtx ) ; } builder . finalize ( ) ; return true ; } </s>

Return true if predicate value X is a constant in which every element is a CONST_INT . When returning true , describe X in BUILDER as a VNx16BI value , i.e . as a predicate in which all bits are significant .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NEON reg-reg move conversion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } initAsmInfo ( ) ; } </s>


<s> static inline bool quad_address_offset_p ( HOST_WIDE_INT offset ) { return ( IN_RANGE ( offset , - 32768 , 32767 ) && ( ( offset ) & 0xf ) == 0 ) ; } </s>

Return true if the OFFSET is valid for the quad address instructions that use d-form ( register + offset ) addressing .


<s> void final_prescan_insn ( rtx_insn * insn , rtx opvec [ ] ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) { if ( dslots_number_nops > 0 ) { rtx pattern = PATTERN ( insn ) ; int length = get_attr_length ( insn ) ; if ( length == 0 || ( iq2000_load_reg != 0 && reg_mentioned_p ( iq2000_load_reg , pattern ) ) || ( iq2000_load_reg2 != 0 && reg_mentioned_p ( iq2000_load_reg2 , pattern ) ) || ( iq2000_load_reg3 != 0 && reg_mentioned_p ( iq2000_load_reg3 , pattern ) ) || ( iq2000_load_reg4 != 0 && reg_mentioned_p ( iq2000_load_reg4 , pattern ) ) ) fputs ( "\tnop\n" , asm_out_file ) ; else dslots_load_filled ++ ; while ( -- dslots_number_nops > 0 ) fputs ( "\tnop\n" , asm_out_file ) ; iq2000_load_reg = 0 ; iq2000_load_reg2 = 0 ; iq2000_load_reg3 = 0 ; iq2000_load_reg4 = 0 ; } if ( ( JUMP_P ( insn ) || CALL_P ( insn ) || ( GET_CODE ( PATTERN ( insn ) ) == RETURN ) ) && NEXT_INSN ( PREV_INSN ( insn ) ) == insn ) { rtx_insn * nop_insn = emit_insn_after ( gen_nop ( ) , insn ) ; INSN_ADDRESSES_NEW ( nop_insn , - 1 ) ; } if ( TARGET_STATS && ( JUMP_P ( insn ) || CALL_P ( insn ) ) ) dslots_jump_total ++ ; } </s>

If defined , a C statement to be executed just prior to the output of assembler code for INSN , to modify the extracted operands so they will be output differently . Here the argument OPVEC is the vector containing the operands extracted from INSN , and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn . The contents of this vector are what will be used to convert the insn template into assembler code , so you can change the assembler output by changing the contents of the vector . We use it to check if the current insn needs a nop in front of it because of load delays , and also to update the delay slot statistics .


<s>
MachineBasicBlock
*
VETargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown Custom Instruction!"
)
;
case
VE
::
EH_SjLj_LongJmp
:
return
emitEHSjLjLongJmp
(
MI
,
BB
)
;
case
VE
::
EH_SjLj_SetJmp
:
return
emitEHSjLjSetJmp
(
MI
,
BB
)
;
case
VE
::
EH_SjLj_Setup_Dispatch
:
return
emitSjLjDispatchBlock
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool sparc_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( aligned_p && size == 8 && ( GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_DOUBLE ) ) { if ( TARGET_V9 ) { assemble_integer_with_op ( "\t.xword\t" , x ) ; return true ; } else { assemble_aligned_integer ( 4 , const0_rtx ) ; assemble_aligned_integer ( 4 , x ) ; return true ; } } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The sparc version has special handling for aligned DI-mode objects .


<s>
const
char
*
output_v9branch
(
rtx
op
,
rtx
dest
,
int
reg
,
int
label
,
int
reversed
,
int
annul
,
rtx_insn
*
insn
)
{
static
char
string
[
64
]
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
machine_mode
mode
=
GET_MODE
(
XEXP
(
op
,
0
)
)
;
rtx
note
;
int
far
;
char
*
p
;
far
=
get_attr_length
(
insn
)
>=
3
;
if
(
reversed
^
far
)
code
=
reverse_condition
(
code
)
;
gcc_assert
(
mode
==
DImode
)
;
switch
(
code
)
{
case
NE
:
strcpy
(
string
,
"brnz"
)
;
break
;
case
EQ
:
strcpy
(
string
,
"brz"
)
;
break
;
case
GE
:
strcpy
(
string
,
"brgez"
)
;
break
;
case
LT
:
strcpy
(
string
,
"brlz"
)
;
break
;
case
LE
:
strcpy
(
string
,
"brlez"
)
;
break
;
case
GT
:
strcpy
(
string
,
"brgz"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
p
=
strchr
(
string
,
'\0'
)
;
if
(
annul
&&
!
far
)
{
strcpy
(
p
,
",a"
)
;
p
+=
2
;
}
if
(
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
profile_probability
::
from_reg_br_prob_note
(
XINT
(
note
,
0
)
)
>=
profile_probability
::
even
(
)
)
^
far
)
",pt"
:
",pn"
)
;
p
+=
3
;
}
*
p
=
p
<
string
+
8
'\t'
:
' '
;
p
++
;
*
p
++
=
'%'
;
*
p
++
=
'0'
+
reg
;
*
p
++
=
','
;
*
p
++
=
' '
;
if
(
far
)
{
int
veryfar
=
1
,
delta
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
{
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
260000
&&
delta
<
260000
)
veryfar
=
0
;
}
strcpy
(
p
,
".+12\n\t nop\n\t"
)
;
if
(
annul
||
!
final_sequence
)
p
[
3
]
=
'6'
;
p
+=
12
;
if
(
veryfar
)
{
strcpy
(
p
,
"b\t"
)
;
p
+=
2
;
}
else
{
strcpy
(
p
,
"ba,pt\t%%xcc, "
)
;
p
+=
13
;
}
}
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
+
label
;
*
p
++
=
'%'
;
*
p
++
=
'#'
;
*
p
=
'\0'
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , testing register REG . LABEL is the operand number of the label ; REG is the operand number of the reg . OP is the conditional expression . The mode of REG says what kind of comparison we made . REVERSED is non-zero if we should reverse the sense of the comparison . ANNUL is non-zero if we should generate an annulling branch . NOOP is non-zero if we have to follow this branch by a noop .


<s> static rtx rs6000_parallel_return ( machine_mode mode , int n_elts , machine_mode elt_mode , unsigned int regno , unsigned int reg_stride ) { rtx par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( n_elts ) ) ; int i ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx r = gen_rtx_REG ( elt_mode , regno ) ; rtx off = GEN_INT ( i * GET_MODE_SIZE ( elt_mode ) ) ; XVECEXP ( par , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; regno += reg_stride ; } return par ; } </s>

Return an rtx describing a return value of MODE as a PARALLEL in N_ELTS registers , each of mode ELT_MODE , starting at REGNO , stride REG_STRIDE .